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author | Jingchang Lu <jingchang.lu@freescale.com> | 2014-08-29 08:57:20 (GMT) |
---|---|---|
committer | Matthew Weigel <Matthew.Weigel@freescale.com> | 2014-12-11 18:35:48 (GMT) |
commit | 36cf34973f840c0868fd24d5b29f8eca1f9c6c54 (patch) | |
tree | e1c9a43314f360681ef5852b795fa5047a04aefa | |
parent | ac69145e065cc0ae66a172a3763feab4b660114a (diff) | |
download | linux-fsl-qoriq-36cf34973f840c0868fd24d5b29f8eca1f9c6c54.tar.xz |
clk: ppc-corenet: rename to ppc-qoriq for better represention
The IP is shared on PPC and ARM, rename it to qoriq for better
represention.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Change-Id: Ib02baa7731d9d1d9955ffde9860deb517d8d7ca8
Reviewed-on: http://git.am.freescale.net:8181/17836
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
-rw-r--r-- | drivers/clk/Kconfig | 8 | ||||
-rw-r--r-- | drivers/clk/Makefile | 2 | ||||
-rw-r--r-- | drivers/clk/clk-qoriq.c (renamed from drivers/clk/clk-ppc-corenet.c) | 18 |
3 files changed, 14 insertions, 14 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 60c0a01..0e29396 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -86,12 +86,12 @@ config COMMON_CLK_AXI_CLKGEN Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx FPGAs. It is commonly used in Analog Devices' reference designs. -config CLK_PPC_CORENET - bool "Clock driver for PowerPC corenet platforms" - depends on (PPC_E500MC || FSL_SOC) && OF +config CLK_QORIQ + bool "Clock driver for PowerPC corenet and ARM-based platforms" + depends on (PPC_E500MC || ARM) && OF ---help--- This adds the clock driver support for Freescale PowerPC corenet - platforms using common clock framework. + and Freescale ARM based platforms using common clock framework. endmenu diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 7b11106..d653137 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -42,4 +42,4 @@ obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o -obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o +obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-qoriq.c index bb8b5e0..6be6930 100644 --- a/drivers/clk/clk-ppc-corenet.c +++ b/drivers/clk/clk-qoriq.c @@ -244,7 +244,7 @@ static const struct of_device_id clk_match[] __initconst = { {} }; -static int __init ppc_corenet_clk_probe(struct platform_device *pdev) +static int __init qoriq_corenet_clk_probe(struct platform_device *pdev) { struct device_node *np; @@ -259,26 +259,26 @@ static int __init ppc_corenet_clk_probe(struct platform_device *pdev) return 0; } -static const struct of_device_id ppc_clk_ids[] __initconst = { +static const struct of_device_id qoriq_clk_ids[] __initconst = { { .compatible = "fsl,qoriq-clockgen-1.0", }, { .compatible = "fsl,qoriq-clockgen-2.0", }, {} }; -static struct platform_driver ppc_corenet_clk_driver __initdata = { +static struct platform_driver qoriq_corenet_clk_driver __initdata = { .driver = { - .name = "ppc_corenet_clock", + .name = "qoriq_corenet_clock", .owner = THIS_MODULE, - .of_match_table = ppc_clk_ids, + .of_match_table = qoriq_clk_ids, }, - .probe = ppc_corenet_clk_probe, + .probe = qoriq_corenet_clk_probe, }; -static int __init ppc_corenet_clk_init(void) +static int __init qoriq_corenet_clk_init(void) { - return platform_driver_register(&ppc_corenet_clk_driver); + return platform_driver_register(&qoriq_corenet_clk_driver); } -subsys_initcall(ppc_corenet_clk_init); +subsys_initcall(qoriq_corenet_clk_init); static void __init ls1021a_clocks_init(struct device_node *np) { |