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author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2013-04-09 21:06:36 (GMT) |
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committer | Jason Cooper <jason@lakedaemon.net> | 2013-04-15 14:53:34 (GMT) |
commit | bf4f9c634633a473438001e93b31fe976b3c3aac (patch) | |
tree | bccfb427bfc150f748a62701ed340d3dafa8e96f /arch/arm/boot | |
parent | 95999cf0985e3b3c66e7a6e9feda850b6a903b50 (diff) | |
download | linux-fsl-qoriq-bf4f9c634633a473438001e93b31fe976b3c3aac.tar.xz |
arm: mvebu: PCIe Device Tree informations for Armada XP DB
The Marvell evaluation board (DB) for the Armada XP SoC has 6
physicals full-size PCIe slots, so we enable the corresponding PCIe
interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r-- | arch/arm/boot/dts/armada-xp-db.dts | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index e83505e..54cc5bb 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -121,5 +121,38 @@ spi-max-frequency = <20000000>; }; }; + + pcie-controller { + status = "okay"; + + /* + * All 6 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + pcie@3,0 { + /* Port 0, Lane 2 */ + status = "okay"; + }; + pcie@4,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@10,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; + }; }; }; |