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authorWill Deacon <will.deacon@arm.com>2013-05-23 17:29:18 (GMT)
committerWill Deacon <will.deacon@arm.com>2013-08-12 11:25:44 (GMT)
commit587b9b6487acddf777301c867c24f31fdf4ada4a (patch)
tree2679cd18aab608967178492a3958f9eddcbc2750 /arch/arm/include
parentf0915781bd5edf78b1154e61efe962dc15872d09 (diff)
downloadlinux-fsl-qoriq-587b9b6487acddf777301c867c24f31fdf4ada4a.tar.xz
ARM: tlb: don't bother with barriers for branch predictor maintenance
Branch predictor maintenance is only required when we are either changing the kernel's view of memory (switching tables completely) or dealing with ASID rollover. Both of these use-cases require subsequent TLB invalidation, which has the relevant barrier instructions to ensure completion and visibility of the maintenance, so this patch removes the instruction barrier from [local_]flush_bp_all. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/tlbflush.h7
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 3316264..9b725d2 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -527,6 +527,10 @@ static inline void __flush_tlb_kernel_page(unsigned long kaddr)
}
}
+/*
+ * Branch predictor maintenance is paired with full TLB invalidation, so
+ * there is no need for any barriers here.
+ */
static inline void local_flush_bp_all(void)
{
const int zero = 0;
@@ -536,9 +540,6 @@ static inline void local_flush_bp_all(void)
asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));
else if (tlb_flag(TLB_V6_BP))
asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));
-
- if (tlb_flag(TLB_BARRIER))
- isb();
}
#include <asm/cputype.h>