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author | Olof Johansson <olof@lixom.net> | 2012-11-30 06:49:30 (GMT) |
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committer | Olof Johansson <olof@lixom.net> | 2012-11-30 06:49:30 (GMT) |
commit | 9121dfca73d81fa886f15610cac2bf372391f3eb (patch) | |
tree | 9aff09bb821f632ea6b7a1117c094d662eb2ecd3 /arch/arm/mach-omap2/dpll44xx.c | |
parent | 77f9db89c928773e5fb1df0df4d13d5cc8abd178 (diff) | |
parent | 8b9c1ac2e11a9fb3a5a8860fb7570ff7633aa7f7 (diff) | |
download | linux-fsl-qoriq-9121dfca73d81fa886f15610cac2bf372391f3eb.tar.xz |
Merge tag 'omap-for-v3.8/devel-prcm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/pm2
From Tony Lindgren:
omap prcm changes via Paul Walmsley <paul@pwsan.com>:
Some miscellaneous OMAP hwmod changes for 3.8, along with a PRM
change needed for one of the hwmod patches to function.
Basic test logs for this branch on top of Tony's
omap-for-v3.8/clock branch at commit
558a0780b0a04862a678f7823215424b4e5501f9 are here:
http://www.pwsan.com/omap/testlogs/hwmod_devel_a_3.8/20121121161522/
However, omap-for-v3.8/clock at 558a0780 does not include some fixes
that are needed for a successful test. With several reverts,
fixes, and workarounds applied, the following test logs were
obtained:
http://www.pwsan.com/omap/testlogs/TEST_hwmod_devel_a_3.8/20121121162719/
which indicate that the series tests cleanly.
* tag 'omap-for-v3.8/devel-prcm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (49 commits)
ARM: OMAP2+: omap_device: Correct resource handling for DT boot
ARM: OMAP2+: hwmod: Add possibility to count hwmod resources based on type
ARM: OMAP2+: hwmod: Add support for per hwmod/module context lost count
ARM: OMAP2+: PRM: initialize some PRM functions early
ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts
ARM: OMAP2xxx: clock: drop obsolete clock data
ARM: OMAP2: clock: Cleanup !CONFIG_COMMON_CLK parts
ARM: OMAP3+: DPLL: drop !CONFIG_COMMON_CLK sections
ARM: AM33xx: clock: drop obsolete clock data
ARM: OMAP3xxx: clk: drop obsolete clock data
ARM: OMAP3: clock: Cleanup !CONFIG_COMMON_CLK parts
ARM: OMAP44xx: clock: drop obsolete clock data
ARM: OMAP4: clock: Cleanup !CONFIG_COMMON_CLK parts
ARM: OMAP: hwmod: Cleanup !CONFIG_COMMON_CLK parts
ARM: OMAP: clock: Switch to COMMON clk
ARM: OMAP2: clock: Add 24xx data using common struct clk
ARM: OMAP3: clock: Add 3xxx data using common struct clk
ARM: AM33XX: clock: add clock data in common clock format
ARM: OMAP4: clock: Add 44xx data using common struct clk
ARM: OMAP2+: clock: add OMAP CCF convenience macros to mach-omap2/clock.h
...
Some context conflicts due to nearby changes resolved in
arch/arm/mach-omap2/io.c.
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-omap2/dpll44xx.c')
-rw-r--r-- | arch/arm/mach-omap2/dpll44xx.c | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 5854da1..d3326c4 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -21,7 +21,7 @@ #include "cm-regbits-44xx.h" /* Supported only on OMAP4 */ -int omap4_dpllmx_gatectrl_read(struct clk *clk) +int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) { u32 v; u32 mask; @@ -40,7 +40,7 @@ int omap4_dpllmx_gatectrl_read(struct clk *clk) return v; } -void omap4_dpllmx_allow_gatectrl(struct clk *clk) +void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) { u32 v; u32 mask; @@ -58,7 +58,7 @@ void omap4_dpllmx_allow_gatectrl(struct clk *clk) __raw_writel(v, clk->clksel_reg); } -void omap4_dpllmx_deny_gatectrl(struct clk *clk) +void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) { u32 v; u32 mask; @@ -76,9 +76,9 @@ void omap4_dpllmx_deny_gatectrl(struct clk *clk) __raw_writel(v, clk->clksel_reg); } -const struct clkops clkops_omap4_dpllmx_ops = { +const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { .allow_idle = omap4_dpllmx_allow_gatectrl, - .deny_idle = omap4_dpllmx_deny_gatectrl, + .deny_idle = omap4_dpllmx_deny_gatectrl, }; /** @@ -90,8 +90,10 @@ const struct clkops clkops_omap4_dpllmx_ops = { * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers) * upon success, or 0 upon error. */ -unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk) +unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, + unsigned long parent_rate) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); u32 v; unsigned long rate; struct dpll_data *dd; @@ -123,8 +125,11 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk) * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or * ~0 if an error occurred in omap2_dpll_round_rate(). */ -long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate) +long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, + unsigned long target_rate, + unsigned long *parent_rate) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); u32 v; struct dpll_data *dd; long r; @@ -140,7 +145,7 @@ long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate) if (v) target_rate = target_rate / OMAP4430_REGM4XEN_MULT; - r = omap2_dpll_round_rate(clk, target_rate); + r = omap2_dpll_round_rate(hw, target_rate, NULL); if (r == ~0) return r; |