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author | Matthew Wilcox <willy@linux.intel.com> | 2009-03-17 12:54:09 (GMT) |
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committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2009-03-20 17:48:13 (GMT) |
commit | f2440d9acbe866b917b16cc0f927366341ce9215 (patch) | |
tree | ed868ca5b61fcadaf782f85c9a900b06e77fc3ce /arch/x86/kernel/io_apic.c | |
parent | 264d9caaa1c574c0274b019a810abfe957391005 (diff) | |
download | linux-fsl-qoriq-f2440d9acbe866b917b16cc0f927366341ce9215.tar.xz |
PCI MSI: Refactor interrupt masking code
Since most of the callers already know whether they have an MSI or
an MSI-X capability, split msi_set_mask_bits() into msi_mask_irq()
and msix_mask_irq(). The only callers which don't (mask_msi_irq()
and unmask_msi_irq()) can share code in msi_set_mask_bit(). This then
becomes the only caller of msix_flush_writes(), so we can inline it.
The flushing read can be to any address that belongs to the device,
so we can eliminate the calculation too.
We can also get rid of maskbits_mask from struct msi_desc and simply
recalculate it on the rare occasion that we need it. The single-bit
'masked' element is replaced by a copy of the 32-bit 'masked' register,
so this patch does not affect the size of msi_desc.
Signed-off-by: Matthew Wilcox <willy@linux.intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'arch/x86/kernel/io_apic.c')
0 files changed, 0 insertions, 0 deletions