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author | Varun Sethi <Varun.Sethi@freescale.com> | 2013-08-15 18:58:26 (GMT) |
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committer | Rivera Jose-B46482 <German.Rivera@freescale.com> | 2013-08-27 18:48:38 (GMT) |
commit | 03f7a7ce577c7fbe4cb84d23f23009ae21f8880f (patch) | |
tree | b62d8d49c8d16ffa88010d31203688e917b50c87 /drivers/iommu | |
parent | d31ab8884b031d63f82f9946c7bf7aaf235c9260 (diff) | |
download | linux-fsl-qoriq-03f7a7ce577c7fbe4cb84d23f23009ae21f8880f.tar.xz |
Enhance get_stash_id API to get the stashid for DSP L2 cache.
The stashid for the DSP cluster L2 cache is programmed by SDOS.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: I7a8203e2dd99e6ccfeacd25305378a4c33becac2
Reviewed-on: http://git.am.freescale.net:8181/4036
Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
Tested-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
Diffstat (limited to 'drivers/iommu')
-rw-r--r-- | drivers/iommu/fsl_pamu.c | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/drivers/iommu/fsl_pamu.c b/drivers/iommu/fsl_pamu.c index 4d466d6..e4064cf 100644 --- a/drivers/iommu/fsl_pamu.c +++ b/drivers/iommu/fsl_pamu.c @@ -32,6 +32,7 @@ #include <asm/io.h> #include <asm/bitops.h> #include <asm/fsl_guts.h> +#include <asm/fsl_kibo.h> #include "fsl_pamu.h" @@ -529,6 +530,72 @@ void get_ome_index(u32 *omi_index, struct device *dev) *omi_index = OMI_QMAN_PRIV; } +/* + * We get the stash id programmed by SDOS from the shared + * cluster L2 l2csr1 register. + */ +static u32 get_dsp_l2_stash_id(u32 cluster) +{ + const u32 *prop; + struct device_node *node; + struct device_node *dsp_cpu_node; + struct ccsr_cluster_l2 *l2cache_regs; + u32 stash_id; + + for_each_compatible_node(node, NULL, "fsl,sc3900-cluster") { + prop = of_get_property(node, "reg", 0); + if (!prop) { + pr_err("missing reg property in dsp cluster %s\n", + node->full_name); + of_node_put(node); + return ~(u32)0; + } + + if (*prop == cluster) { + dsp_cpu_node = of_find_compatible_node(node, NULL, "fsl,sc3900"); + if (!dsp_cpu_node) { + pr_err("missing dsp cpu node in dsp cluster %s\n", + node->full_name); + of_node_put(node); + return ~(u32)0; + } + of_node_put(node); + + prop = of_get_property(dsp_cpu_node, "next-level-cache", 0); + if (!prop) { + pr_err("missing next level cache property in dsp cpu %s\n", + node->full_name); + of_node_put(dsp_cpu_node); + return ~(u32)0; + } + of_node_put(dsp_cpu_node); + + node = of_find_node_by_phandle(*prop); + if (!node) { + pr_err("Invalid node for cache hierarchy %s\n", + node->full_name); + return ~(u32)0; + } + + l2cache_regs = of_iomap(node, 0); + if (!l2cache_regs) { + pr_err("failed to map cluster l2 cache registers %s\n", + node->full_name); + of_node_put(node); + return ~(u32)0; + } + + stash_id = in_be32(&l2cache_regs->l2csr1) & + CLUSTER_L2_STASH_MASK; + of_node_put(node); + iounmap(l2cache_regs); + + return stash_id; + } + } + return ~(u32)0; +} + /** * get_stash_id - Returns stash destination id corresponding to a * cache type and vcpu. @@ -546,6 +613,10 @@ u32 get_stash_id(u32 stash_dest_hint, u32 vcpu) int len, found = 0; int i; + /* check for DSP L2 cache */ + if (stash_dest_hint == IOMMU_ATTR_CACHE_DSP_L2) { + return get_dsp_l2_stash_id(vcpu); + } /* Fastpath, exit early if L3/CPC cache is target for stashing */ if (stash_dest_hint == IOMMU_ATTR_CACHE_L3) { node = of_find_matching_node(NULL, l3_device_ids); |