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| author | Chunhe Lan <Chunhe.Lan@freescale.com> | 2014-10-30 11:06:33 (GMT) |
|---|---|---|
| committer | Matthew Weigel <Matthew.Weigel@freescale.com> | 2014-12-11 18:39:05 (GMT) |
| commit | 2e8fef913763401a2fe35ec4eb1658d01a3c0db9 (patch) | |
| tree | 9d797addbda623a6ef3633571b5a01deb55ce7ce /include | |
| parent | 330f4843df0ad2e06090ad7b234b34ce48569606 (diff) | |
| download | linux-fsl-qoriq-2e8fef913763401a2fe35ec4eb1658d01a3c0db9.tar.xz | |
mtd: spi-nor: Add support for flag status register on Micron chips
Some new Micron SPI N25Q512 chips require reading the flag
status register to determine when operations have completed.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Change-Id: I52a87e1ae55da75248108d6db39f027318bacf22
Reviewed-on: http://git.am.freescale.net:8181/22632
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mtd/spi-nor.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index e1bc2c3..bde191c 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -37,6 +37,7 @@ #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ +#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ #define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */ @@ -70,6 +71,9 @@ #define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */ +/* Flag Status Register bits */ +#define FSR_READY 0x80 + /* Configuration Register bits. */ #define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */ |