diff options
Diffstat (limited to 'arch/arm/mach-shmobile/setup-r8a7790.c')
| -rw-r--r-- | arch/arm/mach-shmobile/setup-r8a7790.c | 94 |
1 files changed, 79 insertions, 15 deletions
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index c47bceb..d0f5c9f 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/clocksource.h> #include <linux/irq.h> #include <linux/kernel.h> #include <linux/of_platform.h> @@ -30,18 +31,17 @@ #include <mach/r8a7790.h> #include <asm/mach/arch.h> -static const struct resource pfc_resources[] __initconst = { +static struct resource pfc_resources[] __initdata = { DEFINE_RES_MEM(0xe6060000, 0x250), }; #define R8A7790_GPIO(idx) \ -static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \ +static struct resource r8a7790_gpio##idx##_resources[] __initdata = { \ DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \ DEFINE_RES_IRQ(gic_spi(4 + (idx))), \ }; \ \ -static const struct gpio_rcar_config \ -r8a7790_gpio##idx##_platform_data __initconst = { \ +static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data __initdata = { \ .gpio_base = 32 * (idx), \ .irq_base = 0, \ .number_of_pins = 32, \ @@ -112,7 +112,7 @@ void __init r8a7790_pinmux_init(void) enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, HSCIF0, HSCIF1 }; -static const struct plat_sci_port scif[] __initconst = { +static struct plat_sci_port scif[] __initdata = { SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ @@ -131,11 +131,11 @@ static inline void r8a7790_register_scif(int idx) sizeof(struct plat_sci_port)); } -static const struct renesas_irqc_config irqc0_data __initconst = { +static struct renesas_irqc_config irqc0_data __initdata = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ }; -static const struct resource irqc0_resources[] __initconst = { +static struct resource irqc0_resources[] __initdata = { DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ @@ -150,7 +150,7 @@ static const struct resource irqc0_resources[] __initconst = { &irqc##idx##_data, \ sizeof(struct renesas_irqc_config)) -static const struct resource thermal_resources[] __initconst = { +static struct resource thermal_resources[] __initdata = { DEFINE_RES_MEM(0xe61f0000, 0x14), DEFINE_RES_MEM(0xe61f0100, 0x38), DEFINE_RES_IRQ(gic_spi(69)), @@ -161,13 +161,13 @@ static const struct resource thermal_resources[] __initconst = { thermal_resources, \ ARRAY_SIZE(thermal_resources)) -static const struct sh_timer_config cmt00_platform_data __initconst = { +static struct sh_timer_config cmt00_platform_data __initdata = { .name = "CMT00", .timer_bit = 0, .clockevent_rating = 80, }; -static const struct resource cmt00_resources[] __initconst = { +static struct resource cmt00_resources[] __initdata = { DEFINE_RES_MEM(0xffca0510, 0x0c), DEFINE_RES_MEM(0xffca0500, 0x04), DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */ @@ -202,7 +202,72 @@ void __init r8a7790_add_standard_devices(void) r8a7790_register_thermal(); } -void __init r8a7790_init_early(void) +#define MODEMR 0xe6160060 + +u32 __init r8a7790_read_mode_pins(void) +{ + void __iomem *modemr = ioremap_nocache(MODEMR, 4); + u32 mode; + + BUG_ON(!modemr); + mode = ioread32(modemr); + iounmap(modemr); + + return mode; +} + +#define CNTCR 0 +#define CNTFID0 0x20 + +void __init r8a7790_timer_init(void) +{ +#ifdef CONFIG_ARM_ARCH_TIMER + u32 mode = r8a7790_read_mode_pins(); + void __iomem *base; + int extal_mhz = 0; + u32 freq; + + /* At Linux boot time the r8a7790 arch timer comes up + * with the counter disabled. Moreover, it may also report + * a potentially incorrect fixed 13 MHz frequency. To be + * correct these registers need to be updated to use the + * frequency EXTAL / 2 which can be determined by the MD pins. + */ + + switch (mode & (MD(14) | MD(13))) { + case 0: + extal_mhz = 15; + break; + case MD(13): + extal_mhz = 20; + break; + case MD(14): + extal_mhz = 26; + break; + case MD(13) | MD(14): + extal_mhz = 30; + break; + } + + /* The arch timer frequency equals EXTAL / 2 */ + freq = extal_mhz * (1000000 / 2); + + /* Remap "armgcnt address map" space */ + base = ioremap(0xe6080000, PAGE_SIZE); + + /* Update registers with correct frequency */ + iowrite32(freq, base + CNTFID0); + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); + + /* make sure arch timer is started by setting bit 0 of CNTCR */ + iowrite32(1, base + CNTCR); + iounmap(base); +#endif /* CONFIG_ARM_ARCH_TIMER */ + + clocksource_of_init(); +} + +void __init r8a7790_init_delay(void) { #ifndef CONFIG_ARM_ARCH_TIMER shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */ @@ -211,15 +276,14 @@ void __init r8a7790_init_early(void) #ifdef CONFIG_USE_OF -static const char * const r8a7790_boards_compat_dt[] __initconst = { +static const char *r8a7790_boards_compat_dt[] __initdata = { "renesas,r8a7790", NULL, }; DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") - .smp = smp_ops(r8a7790_smp_ops), - .init_early = r8a7790_init_early, - .init_time = rcar_gen2_timer_init, + .init_early = r8a7790_init_delay, + .init_time = r8a7790_timer_init, .dt_compat = r8a7790_boards_compat_dt, MACHINE_END #endif /* CONFIG_USE_OF */ |