From cf03c44ec4a431b0e755e6696a355f7f959f08e1 Mon Sep 17 00:00:00 2001 From: Claudiu Manoil Date: Mon, 17 Feb 2014 12:53:18 +0200 Subject: gianfar: Add missing graceful reset steps and fixes gfar_halt() and gfar_start() are responsible for stopping and starting the DMA and the Rx/Tx hw rings. They implement the support for the "graceful Rx/Tx stop/start" hw procedure, and also disable/enable eTSEC's hw interrupts in the process. The GRS/GTS procedure requires however to have the RQUEUE/TQUEUE registers cleared first and to wait for a period of time for the current frame to pass through the interface (around ~10ms for a jumbo frame). Only then may the GTS and GRS bits from DMACTRL be set to shut down the DMA, and finally the Tx_EN and Rx_EN bits in MACCFG1 may be cleared to disable the Tx/Rx blocks. The same register programming order applies to start the Rx/Tx: enabling the RQUEUE/TQUEUE *before* clearing the GRS/GTS bits. This is a HW recommendation in order to avoid a possible controller "lock up" during graceful reset. Cleanup the gfar_halt()/start() prototypes, to take priv instead of ndev as their purpose is to operate on HW. Enabling the RQUEUE/TQUEUE in the hw_init() is not needed anymore since that's the job of gfar_start(). Signed-off-by: Claudiu Manoil Signed-off-by: David S. Miller Change-Id: Idd62100c52aca887f743298c63df15bf54f38308 Reviewed-on: http://git.am.freescale.net:8181/9053 Tested-by: Review Code-CDREVIEW Reviewed-by: Madalin-Cristian Bucur Tested-by: Madalin-Cristian Bucur diff --git a/drivers/net/ethernet/freescale/gianfar.c b/drivers/net/ethernet/freescale/gianfar.c index efc5d63..4a63717 100644 --- a/drivers/net/ethernet/freescale/gianfar.c +++ b/drivers/net/ethernet/freescale/gianfar.c @@ -146,9 +146,7 @@ int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int amount_pull, struct napi_struct *napi); -void gfar_halt(struct net_device *dev); -static void gfar_halt_nodisable(struct net_device *dev); -void gfar_start(struct net_device *dev); +static void gfar_halt_nodisable(struct gfar_private *priv); static void gfar_clear_exact_match(struct net_device *dev); static void gfar_set_mac_for_addr(struct net_device *dev, int num, const u8 *addr); @@ -1064,10 +1062,6 @@ static void gfar_hw_init(struct gfar_private *priv) /* Program the interrupt steering regs, only for MG devices */ if (priv->num_grps > 1) gfar_write_isrg(priv); - - /* Enable all Rx/Tx queues after MAC reset */ - gfar_write(®s->rqueue, priv->rqueue); - gfar_write(®s->tqueue, priv->tqueue); } static void __init gfar_init_addr_hash_table(struct gfar_private *priv) @@ -1140,7 +1134,7 @@ static int gfar_probe(struct platform_device *ofdev) /* Stop the DMA engine now, in case it was running before * (The firmware could have used it, and left it running). */ - gfar_halt(dev); + gfar_halt(priv); gfar_hw_init(priv); @@ -1308,7 +1302,7 @@ static int gfar_suspend(struct device *dev) lock_tx_qs(priv); lock_rx_qs(priv); - gfar_halt_nodisable(ndev); + gfar_halt_nodisable(priv); /* Disable Tx, and Rx if wake-on-LAN is disabled. */ tempval = gfar_read(®s->maccfg1); @@ -1372,7 +1366,7 @@ static int gfar_resume(struct device *dev) tempval &= ~MACCFG2_MPEN; gfar_write(®s->maccfg2, tempval); - gfar_start(ndev); + gfar_start(priv); unlock_rx_qs(priv); unlock_tx_qs(priv); @@ -1404,7 +1398,7 @@ static int gfar_restore(struct device *dev) init_registers(ndev); gfar_set_mac_address(ndev); gfar_init_mac(ndev); - gfar_start(ndev); + gfar_start(priv); priv->oldlink = 0; priv->oldspeed = 0; @@ -1627,9 +1621,8 @@ static int __gfar_is_rx_idle(struct gfar_private *priv) } /* Halt the receive and transmit queues */ -static void gfar_halt_nodisable(struct net_device *dev) +static void gfar_halt_nodisable(struct gfar_private *priv) { - struct gfar_private *priv = netdev_priv(dev); struct gfar __iomem *regs = priv->gfargrp[0].regs; u32 tempval; @@ -1655,15 +1648,20 @@ static void gfar_halt_nodisable(struct net_device *dev) } /* Halt the receive and transmit queues */ -void gfar_halt(struct net_device *dev) +void gfar_halt(struct gfar_private *priv) { - struct gfar_private *priv = netdev_priv(dev); struct gfar __iomem *regs = priv->gfargrp[0].regs; u32 tempval; - gfar_halt_nodisable(dev); + /* Dissable the Rx/Tx hw queues */ + gfar_write(®s->rqueue, 0); + gfar_write(®s->tqueue, 0); - /* Disable Rx and Tx */ + mdelay(10); + + gfar_halt_nodisable(priv); + + /* Disable Rx/Tx DMA */ tempval = gfar_read(®s->maccfg1); tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); gfar_write(®s->maccfg1, tempval); @@ -1690,7 +1688,7 @@ void stop_gfar(struct net_device *dev) lock_tx_qs(priv); lock_rx_qs(priv); - gfar_halt(dev); + gfar_halt(priv); unlock_rx_qs(priv); unlock_tx_qs(priv); @@ -1795,17 +1793,15 @@ static void free_skb_resources(struct gfar_private *priv) priv->tx_queue[0]->tx_bd_dma_base); } -void gfar_start(struct net_device *dev) +void gfar_start(struct gfar_private *priv) { - struct gfar_private *priv = netdev_priv(dev); struct gfar __iomem *regs = priv->gfargrp[0].regs; u32 tempval; int i = 0; - /* Enable Rx and Tx in MACCFG1 */ - tempval = gfar_read(®s->maccfg1); - tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); - gfar_write(®s->maccfg1, tempval); + /* Enable Rx/Tx hw queues */ + gfar_write(®s->rqueue, priv->rqueue); + gfar_write(®s->tqueue, priv->tqueue); /* Initialize DMACTRL to have WWR and WOP */ tempval = gfar_read(®s->dmactrl); @@ -1824,9 +1820,14 @@ void gfar_start(struct net_device *dev) gfar_write(®s->rstat, priv->gfargrp[i].rstat); } + /* Enable Rx/Tx DMA */ + tempval = gfar_read(®s->maccfg1); + tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); + gfar_write(®s->maccfg1, tempval); + gfar_ints_enable(priv); - dev->trans_start = jiffies; /* prevent tx timeout */ + priv->ndev->trans_start = jiffies; /* prevent tx timeout */ } static void gfar_configure_coalescing(struct gfar_private *priv, @@ -1950,7 +1951,7 @@ int startup_gfar(struct net_device *ndev) } /* Start the controller */ - gfar_start(ndev); + gfar_start(priv); phy_start(priv->phydev); diff --git a/drivers/net/ethernet/freescale/gianfar.h b/drivers/net/ethernet/freescale/gianfar.h index 00db12d..16ffa4b 100644 --- a/drivers/net/ethernet/freescale/gianfar.h +++ b/drivers/net/ethernet/freescale/gianfar.h @@ -1228,7 +1228,8 @@ void unlock_tx_qs(struct gfar_private *priv); irqreturn_t gfar_receive(int irq, void *dev_id); int startup_gfar(struct net_device *dev); void stop_gfar(struct net_device *dev); -void gfar_halt(struct net_device *dev); +void gfar_halt(struct gfar_private *priv); +void gfar_start(struct gfar_private *priv); void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, int enable, u32 regnum, u32 read); void gfar_configure_coalescing_all(struct gfar_private *priv); diff --git a/drivers/net/ethernet/freescale/gianfar_ethtool.c b/drivers/net/ethernet/freescale/gianfar_ethtool.c index 5900dba..86bb12d 100644 --- a/drivers/net/ethernet/freescale/gianfar_ethtool.c +++ b/drivers/net/ethernet/freescale/gianfar_ethtool.c @@ -45,7 +45,6 @@ #include "gianfar.h" -extern void gfar_start(struct net_device *dev); extern int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); @@ -505,7 +504,7 @@ static int gfar_sringparam(struct net_device *dev, lock_tx_qs(priv); lock_rx_qs(priv); - gfar_halt(dev); + gfar_halt(priv); unlock_rx_qs(priv); unlock_tx_qs(priv); @@ -628,7 +627,7 @@ int gfar_set_features(struct net_device *dev, netdev_features_t features) lock_tx_qs(priv); lock_rx_qs(priv); - gfar_halt(dev); + gfar_halt(priv); unlock_tx_qs(priv); unlock_rx_qs(priv); -- cgit v0.10.2