From 6e7582bf35b8a5a330fd08b398ae445bac86917a Mon Sep 17 00:00:00 2001 From: Jiang Liu Date: Fri, 17 May 2013 14:45:08 +0000 Subject: MIPS: PowerTV: use free_reserved_area() to simplify code Use common help function free_reserved_area() to simplify code. Signed-off-by: Jiang Liu Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Andrew Morton Cc: Jiang Liu Cc: David Rientjes Cc: Wen Congyang Cc: Mel Gorman Cc: Minchan Kim Cc: KAMEZAWA Hiroyuki Cc: Michal Hocko Cc: James Bottomley Cc: Sergei Shtylyov Cc: David Howells Cc: Mark Salter Cc: Jianguo Wu Cc: linux-mm@kvack.org Cc: linux-arch@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5248/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c index d38b095..9f64c23 100644 --- a/arch/mips/powertv/asic/asic_devices.c +++ b/arch/mips/powertv/asic/asic_devices.c @@ -529,17 +529,8 @@ EXPORT_SYMBOL(asic_resource_get); */ void platform_release_memory(void *ptr, int size) { - unsigned long addr; - unsigned long end; - - addr = ((unsigned long)ptr + (PAGE_SIZE - 1)) & PAGE_MASK; - end = ((unsigned long)ptr + size) & PAGE_MASK; - - for (; addr < end; addr += PAGE_SIZE) { - ClearPageReserved(virt_to_page(__va(addr))); - init_page_count(virt_to_page(__va(addr))); - free_page((unsigned long)__va(addr)); - } + free_reserved_area((unsigned long)ptr, (unsigned long)(ptr + size), + -1, NULL); } EXPORT_SYMBOL(platform_release_memory); -- cgit v0.10.2 From 9ddebc46e70b434e485060f7c1b53c5b848a6c8c Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 22 May 2013 15:10:46 +0000 Subject: MIPS: OCTEON: Rename Kconfig CAVIUM_OCTEON_REFERENCE_BOARD to CAVIUM_OCTEON_SOC CAVIUM_OCTEON_SOC most place we used to use CPU_CAVIUM_OCTEON. This allows us to CPU_CAVIUM_OCTEON in places where we have no OCTEON SOC. Remove CAVIUM_OCTEON_SIMULATOR as it doesn't really do anything, we can get the same configuration with CAVIUM_OCTEON_SOC. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Cc: linux-ide@vger.kernel.org Cc: linux-edac@vger.kernel.org Cc: linux-i2c@vger.kernel.org Cc: netdev@vger.kernel.org Cc: spi-devel-general@lists.sourceforge.net Cc: devel@driverdev.osuosl.org Cc: linux-usb@vger.kernel.org Acked-by: Greg Kroah-Hartman Acked-by: Wolfram Sang Acked-by: Mauro Carvalho Chehab Patchwork: https://patchwork.linux-mips.org/patch/5295/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7a58ab9..ade9973 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -735,23 +735,8 @@ config WR_PPMC This enables support for the Wind River MIPS32 4KC PPMC evaluation board, which is based on GT64120 bridge chip. -config CAVIUM_OCTEON_SIMULATOR - bool "Cavium Networks Octeon Simulator" - select CEVT_R4K - select 64BIT_PHYS_ADDR - select DMA_COHERENT - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_HOTPLUG_CPU - select SYS_HAS_CPU_CAVIUM_OCTEON - select HOLES_IN_ZONE - help - The Octeon simulator is software performance model of the Cavium - Octeon Processor. It supports simulating Octeon processors on x86 - hardware. - -config CAVIUM_OCTEON_REFERENCE_BOARD - bool "Cavium Networks Octeon reference board" +config CAVIUM_OCTEON_SOC + bool "Cavium Networks Octeon SoC based boards" select CEVT_R4K select 64BIT_PHYS_ADDR select DMA_COHERENT diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index 75a6df7..a12444a 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -10,6 +10,10 @@ config CAVIUM_CN63XXP1 non-CN63XXP1 hardware, so it is recommended to select "n" unless it is known the workarounds are needed. +endif # CPU_CAVIUM_OCTEON + +if CAVIUM_OCTEON_SOC + config CAVIUM_OCTEON_2ND_KERNEL bool "Build the kernel to be used as a 2nd kernel on the same chip" default "n" @@ -103,4 +107,4 @@ config OCTEON_ILM To compile this driver as a module, choose M here. The module will be called octeon-ilm -endif # CPU_CAVIUM_OCTEON +endif # CAVIUM_OCTEON_SOC diff --git a/arch/mips/cavium-octeon/Platform b/arch/mips/cavium-octeon/Platform index 1e43ccf..8a301cb 100644 --- a/arch/mips/cavium-octeon/Platform +++ b/arch/mips/cavium-octeon/Platform @@ -1,11 +1,11 @@ # # Cavium Octeon # -platform-$(CONFIG_CPU_CAVIUM_OCTEON) += cavium-octeon/ -cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += \ +platform-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon/ +cflags-$(CONFIG_CAVIUM_OCTEON_SOC) += \ -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL -load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff84100000 +load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff84100000 else -load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000 +load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff81100000 endif diff --git a/arch/mips/configs/cavium_octeon_defconfig b/arch/mips/configs/cavium_octeon_defconfig index 014ba4b..1888e5f 100644 --- a/arch/mips/configs/cavium_octeon_defconfig +++ b/arch/mips/configs/cavium_octeon_defconfig @@ -1,4 +1,4 @@ -CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y +CONFIG_CAVIUM_OCTEON_SOC=y CONFIG_CAVIUM_CN63XXP1=y CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2 CONFIG_SPARSEMEM_MANUAL=y diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 2cb1d31..fa3bcd2 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -54,10 +54,10 @@ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o -obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o +obj-$(CONFIG_CAVIUM_OCTEON_SOC) += pci-octeon.o pcie-octeon.o obj-$(CONFIG_CPU_XLR) += pci-xlr.o obj-$(CONFIG_CPU_XLP) += pci-xlp.o ifdef CONFIG_PCI_MSI -obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o +obj-$(CONFIG_CAVIUM_OCTEON_SOC) += msi-octeon.o endif diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index a5a3ebc..dc20774 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -160,7 +160,7 @@ config PDC_ADMA config PATA_OCTEON_CF tristate "OCTEON Boot Bus Compact Flash support" - depends on CPU_CAVIUM_OCTEON + depends on CAVIUM_OCTEON_SOC help This option enables a polled compact flash driver for use with compact flash cards attached to the OCTEON boot bus. diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index 2f9dbf7..40a8654 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -167,7 +167,7 @@ config HW_RANDOM_OMAP config HW_RANDOM_OCTEON tristate "Octeon Random Number Generator support" - depends on HW_RANDOM && CPU_CAVIUM_OCTEON + depends on HW_RANDOM && CAVIUM_OCTEON_SOC default HW_RANDOM ---help--- This driver provides kernel-side support for the Random Number diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index e443f2c1..923d2e8 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -349,21 +349,21 @@ config EDAC_OCTEON_PC config EDAC_OCTEON_L2C tristate "Cavium Octeon Secondary Caches (L2C)" - depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON + depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC help Support for error detection and correction on the Cavium Octeon family of SOCs. config EDAC_OCTEON_LMC tristate "Cavium Octeon DRAM Memory Controller (LMC)" - depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON + depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC help Support for error detection and correction on the Cavium Octeon family of SOCs. config EDAC_OCTEON_PCI tristate "Cavium Octeon PCI Controller" - depends on EDAC_MM_EDAC && PCI && CPU_CAVIUM_OCTEON + depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC help Support for error detection and correction on the Cavium Octeon family of SOCs. diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 631736e..a8fff77 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -726,7 +726,7 @@ config I2C_VERSATILE config I2C_OCTEON tristate "Cavium OCTEON I2C bus support" - depends on CPU_CAVIUM_OCTEON + depends on CAVIUM_OCTEON_SOC help Say yes if you want to support the I2C serial bus on Cavium OCTEON SOC. diff --git a/drivers/net/ethernet/octeon/Kconfig b/drivers/net/ethernet/octeon/Kconfig index 3de52ff..a7aa280 100644 --- a/drivers/net/ethernet/octeon/Kconfig +++ b/drivers/net/ethernet/octeon/Kconfig @@ -4,7 +4,7 @@ config OCTEON_MGMT_ETHERNET tristate "Octeon Management port ethernet driver (CN5XXX, CN6XXX)" - depends on CPU_CAVIUM_OCTEON + depends on CAVIUM_OCTEON_SOC select PHYLIB select MDIO_OCTEON default y diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 1e11f2b..84461e8 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -135,7 +135,7 @@ config MDIO_GPIO config MDIO_OCTEON tristate "Support for MDIO buses on Octeon SOCs" - depends on CPU_CAVIUM_OCTEON + depends on CAVIUM_OCTEON_SOC default y help diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 92a9345..2015897 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -266,7 +266,7 @@ config SPI_OC_TINY config SPI_OCTEON tristate "Cavium OCTEON SPI controller" - depends on CPU_CAVIUM_OCTEON + depends on CAVIUM_OCTEON_SOC help SPI host driver for the hardware found on some Cavium OCTEON SOCs. diff --git a/drivers/staging/octeon/Kconfig b/drivers/staging/octeon/Kconfig index 9493128..6e1d5f8 100644 --- a/drivers/staging/octeon/Kconfig +++ b/drivers/staging/octeon/Kconfig @@ -1,6 +1,6 @@ config OCTEON_ETHERNET tristate "Cavium Networks Octeon Ethernet support" - depends on CPU_CAVIUM_OCTEON && NETDEVICES + depends on CAVIUM_OCTEON_SOC && NETDEVICES select PHYLIB select MDIO_OCTEON help diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 344d5e2..54c1215 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -285,7 +285,7 @@ config USB_EHCI_HCD_PLATFORM config USB_OCTEON_EHCI bool "Octeon on-chip EHCI support" - depends on CPU_CAVIUM_OCTEON + depends on CAVIUM_OCTEON_SOC default n select USB_EHCI_BIG_ENDIAN_MMIO help @@ -480,7 +480,7 @@ config USB_OHCI_HCD_PLATFORM config USB_OCTEON_OHCI bool "Octeon on-chip OHCI support" - depends on CPU_CAVIUM_OCTEON + depends on CAVIUM_OCTEON_SOC default USB_OCTEON_EHCI select USB_OHCI_BIG_ENDIAN_MMIO select USB_OHCI_LITTLE_ENDIAN diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index e89fc31..9d03af1 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -1072,7 +1072,7 @@ config TXX9_WDT config OCTEON_WDT tristate "Cavium OCTEON SOC family Watchdog Timer" - depends on CPU_CAVIUM_OCTEON + depends on CAVIUM_OCTEON_SOC default y select EXPORT_UASM if OCTEON_WDT = m help -- cgit v0.10.2 From 02a49d5144c58a2b9826946934533a7a9f28c2ec Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 22 May 2013 20:46:23 +0000 Subject: MIPS: Octeon: Remove vestiges of CONFIG_CAVIUM_DECODE_RSL This config option doesn't exist any more, remove the leftover code for it too. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5302/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 01b1b3f..0acc8ef 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -40,12 +40,6 @@ #include #include -#ifdef CONFIG_CAVIUM_DECODE_RSL -extern void cvmx_interrupt_rsl_decode(void); -extern int __cvmx_interrupt_ecc_report_single_bit_errors; -extern void cvmx_interrupt_rsl_enable(void); -#endif - extern struct plat_smp_ops octeon_smp_ops; #ifdef CONFIG_PCI @@ -463,18 +457,6 @@ static void octeon_halt(void) } /** - * Handle all the error condition interrupts that might occur. - * - */ -#ifdef CONFIG_CAVIUM_DECODE_RSL -static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id) -{ - cvmx_interrupt_rsl_decode(); - return IRQ_HANDLED; -} -#endif - -/** * Return a string representing the system type * * Returns @@ -1064,15 +1046,6 @@ void prom_free_prom_memory(void) panic("Core-14449 WAR not in place (%04x).\n" "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn); } -#ifdef CONFIG_CAVIUM_DECODE_RSL - cvmx_interrupt_rsl_enable(); - - /* Add an interrupt handler for general failures. */ - if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED, - "RML/RSL", octeon_rlm_interrupt)) { - panic("Unable to request_irq(OCTEON_IRQ_RML)"); - } -#endif } int octeon_prune_device_tree(void); -- cgit v0.10.2 From 0ec315121c8391a14bbeb5eecc146c470dfc00cb Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 22 May 2013 20:46:44 +0000 Subject: MIPS: OCTEON: Get rid of CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED When you turn it off, the kernel is unusable, so get rid of the option and always allow unaligned access. The Octeon specific memcpy intentionally does unaligned accesses and it must not fault. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5303/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index a12444a..227705d 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -23,17 +23,6 @@ config CAVIUM_OCTEON_2ND_KERNEL with this option to be run at the same time as one built without this option. -config CAVIUM_OCTEON_HW_FIX_UNALIGNED - bool "Enable hardware fixups of unaligned loads and stores" - default "y" - help - Configure the Octeon hardware to automatically fix unaligned loads - and stores. Normally unaligned accesses are fixed using a kernel - exception handler. This option enables the hardware automatic fixups, - which requires only an extra 3 cycles. Disable this option if you - are running code that relies on address exceptions on unaligned - accesses. - config CAVIUM_OCTEON_CVMSEG_SIZE int "Number of L1 cache lines reserved for CVMSEG memory" range 0 54 diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h index 1e7dbb1..1668ee5 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h @@ -34,15 +34,10 @@ ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register -#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED # Disable unaligned load/store support but leave HW fixup enabled + # Needed for octeon specific memcpy or v0, v0, 0x5001 xor v0, v0, 0x1001 -#else - # Disable unaligned load/store and HW fixup support - or v0, v0, 0x5001 - xor v0, v0, 0x5001 -#endif # Read the processor ID register mfc0 v1, CP0_PRID_REG # Disable instruction prefetching (Octeon Pass1 errata) -- cgit v0.10.2 From 90a6fb120d9c039b108d37405b0e8ba2258403bf Mon Sep 17 00:00:00 2001 From: Chen Gang Date: Sun, 26 May 2013 06:51:49 +0000 Subject: MIPS: Lantiq: Use strlcpy() instead of strncpy(). 'compatible' is used by strlen() in __of_device_is_compatible(). Ensure strings are always '\0' terminated. 'of_ids is not a structure in "include/uapi/*", so no need to initialize it completly; using strlcpy() instead of strncpy() will do. Signed-off-by: Chen Gang Acked-by: John Crispin Cc: linux-mips@linux-mips.org Cc: Linux-Arch Patchwork: https://patchwork.linux-mips.org/patch/5329/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index 9f9e875..49c4603 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -112,7 +112,7 @@ int __init plat_of_setup(void) if (!of_have_populated_dt()) panic("device tree not present"); - strncpy(of_ids[0].compatible, soc_info.compatible, + strlcpy(of_ids[0].compatible, soc_info.compatible, sizeof(of_ids[0].compatible)); strncpy(of_ids[1].compatible, "simple-bus", sizeof(of_ids[1].compatible)); -- cgit v0.10.2 From 24b1944fc6b7be857c81f0cb0ff264c57b85ee29 Mon Sep 17 00:00:00 2001 From: Chen Gang Date: Sun, 26 May 2013 07:01:46 +0000 Subject: MIPS: Ralink: Use strlcpy() instead of strncpy(). 'compatible' is used by strlen() in __of_device_is_compatible(). Ensure strings are always '\0' terminated. 'of_ids is not a structure in "include/uapi/*", so no need to initialize it completly; using strlcpy() instead of strncpy() will do. Signed-off-by: Chen Gang Acked-by: John Crispin Cc: juhosg@openwrt.org Cc: linux-mips@linux-mips.org Cc: Linux-Arch Patchwork: https://patchwork.linux-mips.org/patch/5330/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c index 6b5f340..f25ea5b 100644 --- a/arch/mips/ralink/of.c +++ b/arch/mips/ralink/of.c @@ -104,7 +104,7 @@ static int __init plat_of_setup(void) if (!of_have_populated_dt()) panic("device tree not present"); - strncpy(of_ids[0].compatible, soc_info.compatible, len); + strlcpy(of_ids[0].compatible, soc_info.compatible, len); strncpy(of_ids[1].compatible, "palmbus", len); if (of_platform_populate(NULL, of_ids, NULL, NULL)) -- cgit v0.10.2 From 41c8366be83a7c868c5281ad8d9e6715c1564351 Mon Sep 17 00:00:00 2001 From: Chen Gang Date: Sun, 26 May 2013 07:06:06 +0000 Subject: MIPS: using strlcpy() instead of strncpy() Ensure strings are always '\0' terminated. Or in the next pr_info() shit may hit the fan. Signed-off-by: Chen Gang Acked-by: John Crispin Cc: david.daney@cavium.com Cc: linux-mips@linux-mips.org Cc: Linux-Arch Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5331/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c index 5712bb5..7e95404 100644 --- a/arch/mips/kernel/prom.c +++ b/arch/mips/kernel/prom.c @@ -30,7 +30,7 @@ __init void mips_set_machine_name(const char *name) if (name == NULL) return; - strncpy(mips_machine_name, name, sizeof(mips_machine_name)); + strlcpy(mips_machine_name, name, sizeof(mips_machine_name)); pr_info("MIPS: machine is %s\n", mips_get_machine_name()); } -- cgit v0.10.2 From e7f3b48af7be9f8007a224663a5b91340626fed5 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 29 May 2013 01:02:18 +0200 Subject: MIPS: Cleanup flags in syscall flags handlers. This will simplify further modifications. Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index 895320e..cdea4f6 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -131,6 +131,8 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_FPUBOUND (1< yes diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 97a5909..be6627e 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -54,7 +54,7 @@ NESTED(handle_sys64, PT_SIZE, sp) sd a3, PT_R26(sp) # save a3 for syscall restarting - li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT + li t1, _TIF_WORK_SYSCALL_ENTRY LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? and t0, t1, t0 bnez t0, syscall_trace_entry diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index edcb659..cab1507 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -47,7 +47,7 @@ NESTED(handle_sysn32, PT_SIZE, sp) sd a3, PT_R26(sp) # save a3 for syscall restarting - li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT + li t1, _TIF_WORK_SYSCALL_ENTRY LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? and t0, t1, t0 bnez t0, n32_syscall_trace_entry diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 74f485d..37605dc 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -81,7 +81,7 @@ NESTED(handle_sys, PT_SIZE, sp) PTR 4b, bad_stack .previous - li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT + li t1, _TIF_WORK_SYSCALL_ENTRY LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? and t0, t1, t0 bnez t0, trace_a_syscall -- cgit v0.10.2 From c3fc5cd5c5a5f4738776a965a020a32c1a37c8fd Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 29 May 2013 01:07:19 +0200 Subject: MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ade9973..87ddac9 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1,6 +1,7 @@ config MIPS bool default y + select HAVE_CONTEXT_TRACKING select HAVE_GENERIC_DMA_COHERENT select HAVE_IDE select HAVE_OPROFILE diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index cdea4f6..61215a3 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -109,6 +109,7 @@ static inline struct thread_info *current_thread_info(void) #define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ #define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ +#define TIF_NOHZ 19 /* in adaptive nohz mode */ #define TIF_FIXADE 20 /* Fix address errors in software */ #define TIF_LOGADE 21 /* Log address errors to syslog */ #define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */ @@ -124,6 +125,7 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_SECCOMP (1< #include #include #include @@ -171,8 +172,12 @@ static volatile int daddi_ov __cpuinitdata; asmlinkage void __init do_daddi_ov(struct pt_regs *regs) { + enum ctx_state prev_state; + + prev_state = exception_enter(); daddi_ov = 1; regs->cp0_epc += 4; + exception_exit(prev_state); } static inline void check_daddi(void) diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 9c6299c..8ae1ebe 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -15,6 +15,7 @@ * binaries. */ #include +#include #include #include #include @@ -534,6 +535,8 @@ static inline int audit_arch(void) */ asmlinkage void syscall_trace_enter(struct pt_regs *regs) { + user_exit(); + /* do the secure computing check first */ secure_computing_strict(regs->regs[2]); @@ -570,6 +573,13 @@ out: */ asmlinkage void syscall_trace_leave(struct pt_regs *regs) { + /* + * We may come here right after calling schedule_user() + * or do_notify_resume(), in which case we can be in RCU + * user mode. + */ + user_exit(); + audit_syscall_exit(regs); if (!(current->ptrace & PT_PTRACED)) @@ -592,4 +602,6 @@ asmlinkage void syscall_trace_leave(struct pt_regs *regs) send_sig(current->exit_code, current, 1); current->exit_code = 0; } + + user_enter(); } diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index fd3ef2c..2f285ab 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -8,6 +8,7 @@ * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ #include +#include #include #include #include @@ -573,6 +574,8 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused, { local_irq_enable(); + user_exit(); + /* deal with pending signal delivery */ if (thread_info_flags & _TIF_SIGPENDING) do_signal(regs); @@ -581,6 +584,8 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused, clear_thread_flag(TIF_NOTIFY_RESUME); tracehook_notify_resume(regs); } + + user_enter(); } #ifdef CONFIG_SMP diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index a75ae40..beba1e6 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -13,6 +13,7 @@ */ #include #include +#include #include #include #include @@ -423,7 +424,9 @@ asmlinkage void do_be(struct pt_regs *regs) const struct exception_table_entry *fixup = NULL; int data = regs->cp0_cause & 4; int action = MIPS_BE_FATAL; + enum ctx_state prev_state; + prev_state = exception_enter(); /* XXX For now. Fixme, this searches the wrong table ... */ if (data && !user_mode(regs)) fixup = search_dbe_tables(exception_epc(regs)); @@ -436,11 +439,11 @@ asmlinkage void do_be(struct pt_regs *regs) switch (action) { case MIPS_BE_DISCARD: - return; + goto out; case MIPS_BE_FIXUP: if (fixup) { regs->cp0_epc = fixup->nextinsn; - return; + goto out; } break; default: @@ -455,10 +458,13 @@ asmlinkage void do_be(struct pt_regs *regs) field, regs->cp0_epc, field, regs->regs[31]); if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS) == NOTIFY_STOP) - return; + goto out; die_if_kernel("Oops", regs); force_sig(SIGBUS, current); + +out: + exception_exit(prev_state); } /* @@ -673,8 +679,10 @@ static int simulate_sync(struct pt_regs *regs, unsigned int opcode) asmlinkage void do_ov(struct pt_regs *regs) { + enum ctx_state prev_state; siginfo_t info; + prev_state = exception_enter(); die_if_kernel("Integer overflow", regs); info.si_code = FPE_INTOVF; @@ -682,6 +690,7 @@ asmlinkage void do_ov(struct pt_regs *regs) info.si_errno = 0; info.si_addr = (void __user *) regs->cp0_epc; force_sig_info(SIGFPE, &info, current); + exception_exit(prev_state); } int process_fpemu_return(int sig, void __user *fault_addr) @@ -713,11 +722,13 @@ int process_fpemu_return(int sig, void __user *fault_addr) */ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) { + enum ctx_state prev_state; siginfo_t info = {0}; + prev_state = exception_enter(); if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE) == NOTIFY_STOP) - return; + goto out; die_if_kernel("FP exception in kernel code", regs); if (fcr31 & FPU_CSR_UNI_X) { @@ -753,7 +764,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) /* If something went wrong, signal */ process_fpemu_return(sig, fault_addr); - return; + goto out; } else if (fcr31 & FPU_CSR_INV_X) info.si_code = FPE_FLTINV; else if (fcr31 & FPU_CSR_DIV_X) @@ -770,6 +781,9 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) info.si_errno = 0; info.si_addr = (void __user *) regs->cp0_epc; force_sig_info(SIGFPE, &info, current); + +out: + exception_exit(prev_state); } static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, @@ -835,9 +849,11 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, asmlinkage void do_bp(struct pt_regs *regs) { unsigned int opcode, bcode; + enum ctx_state prev_state; unsigned long epc; u16 instr[2]; + prev_state = exception_enter(); if (get_isa16_mode(regs->cp0_epc)) { /* Calculate EPC. */ epc = exception_epc(regs); @@ -852,7 +868,7 @@ asmlinkage void do_bp(struct pt_regs *regs) goto out_sigsegv; bcode = (instr[0] >> 6) & 0x3f; do_trap_or_bp(regs, bcode, "Break"); - return; + goto out; } } else { if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) @@ -876,12 +892,12 @@ asmlinkage void do_bp(struct pt_regs *regs) switch (bcode) { case BRK_KPROBE_BP: if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) - return; + goto out; else break; case BRK_KPROBE_SSTEPBP: if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) - return; + goto out; else break; default: @@ -889,18 +905,24 @@ asmlinkage void do_bp(struct pt_regs *regs) } do_trap_or_bp(regs, bcode, "Break"); + +out: + exception_exit(prev_state); return; out_sigsegv: force_sig(SIGSEGV, current); + goto out; } asmlinkage void do_tr(struct pt_regs *regs) { u32 opcode, tcode = 0; + enum ctx_state prev_state; u16 instr[2]; unsigned long epc = msk_isa16_mode(exception_epc(regs)); + prev_state = exception_enter(); if (get_isa16_mode(regs->cp0_epc)) { if (__get_user(instr[0], (u16 __user *)(epc + 0)) || __get_user(instr[1], (u16 __user *)(epc + 2))) @@ -918,10 +940,14 @@ asmlinkage void do_tr(struct pt_regs *regs) } do_trap_or_bp(regs, tcode, "Trap"); + +out: + exception_exit(prev_state); return; out_sigsegv: force_sig(SIGSEGV, current); + goto out; } asmlinkage void do_ri(struct pt_regs *regs) @@ -929,17 +955,19 @@ asmlinkage void do_ri(struct pt_regs *regs) unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); unsigned long old_epc = regs->cp0_epc; unsigned long old31 = regs->regs[31]; + enum ctx_state prev_state; unsigned int opcode = 0; int status = -1; + prev_state = exception_enter(); if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL) == NOTIFY_STOP) - return; + goto out; die_if_kernel("Reserved instruction in kernel code", regs); if (unlikely(compute_return_epc(regs) < 0)) - return; + goto out; if (get_isa16_mode(regs->cp0_epc)) { unsigned short mmop[2] = { 0 }; @@ -974,6 +1002,9 @@ asmlinkage void do_ri(struct pt_regs *regs) regs->regs[31] = old31; force_sig(status, current); } + +out: + exception_exit(prev_state); } /* @@ -1040,6 +1071,7 @@ static int default_cu2_call(struct notifier_block *nfb, unsigned long action, asmlinkage void do_cpu(struct pt_regs *regs) { + enum ctx_state prev_state; unsigned int __user *epc; unsigned long old_epc, old31; unsigned int opcode; @@ -1047,6 +1079,7 @@ asmlinkage void do_cpu(struct pt_regs *regs) int status; unsigned long __maybe_unused flags; + prev_state = exception_enter(); die_if_kernel("do_cpu invoked from kernel context!", regs); cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; @@ -1060,7 +1093,7 @@ asmlinkage void do_cpu(struct pt_regs *regs) status = -1; if (unlikely(compute_return_epc(regs) < 0)) - return; + goto out; if (get_isa16_mode(regs->cp0_epc)) { unsigned short mmop[2] = { 0 }; @@ -1093,7 +1126,7 @@ asmlinkage void do_cpu(struct pt_regs *regs) force_sig(status, current); } - return; + goto out; case 3: /* @@ -1131,19 +1164,26 @@ asmlinkage void do_cpu(struct pt_regs *regs) mt_ase_fp_affinity(); } - return; + goto out; case 2: raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); - return; + goto out; } force_sig(SIGILL, current); + +out: + exception_exit(prev_state); } asmlinkage void do_mdmx(struct pt_regs *regs) { + enum ctx_state prev_state; + + prev_state = exception_enter(); force_sig(SIGILL, current); + exception_exit(prev_state); } /* @@ -1151,8 +1191,10 @@ asmlinkage void do_mdmx(struct pt_regs *regs) */ asmlinkage void do_watch(struct pt_regs *regs) { + enum ctx_state prev_state; u32 cause; + prev_state = exception_enter(); /* * Clear WP (bit 22) bit of cause register so we don't loop * forever. @@ -1174,13 +1216,16 @@ asmlinkage void do_watch(struct pt_regs *regs) mips_clear_watch_registers(); local_irq_enable(); } + exception_exit(prev_state); } asmlinkage void do_mcheck(struct pt_regs *regs) { const int field = 2 * sizeof(unsigned long); int multi_match = regs->cp0_status & ST0_TS; + enum ctx_state prev_state; + prev_state = exception_enter(); show_regs(regs); if (multi_match) { @@ -1202,6 +1247,7 @@ asmlinkage void do_mcheck(struct pt_regs *regs) panic("Caught Machine Check exception - %scaused by multiple " "matching entries in the TLB.", (multi_match) ? "" : "not "); + exception_exit(prev_state); } asmlinkage void do_mt(struct pt_regs *regs) diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 203d885..3eaa02a 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -72,6 +72,7 @@ * A store crossing a page boundary might be executed only partially. * Undo the partial store in this case. */ +#include #include #include #include @@ -1550,9 +1551,11 @@ sigill: } asmlinkage void do_ade(struct pt_regs *regs) { + enum ctx_state prev_state; unsigned int __user *pc; mm_segment_t seg; + prev_state = exception_enter(); perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, regs->cp0_badvaddr); /* @@ -1628,6 +1631,7 @@ sigbus: /* * XXX On return from the signal handler we should advance the epc */ + exception_exit(prev_state); } #ifdef CONFIG_DEBUG_FS diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index 0fead53..85df1cd 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -5,6 +5,7 @@ * * Copyright (C) 1995 - 2000 by Ralf Baechle */ +#include #include #include #include @@ -32,8 +33,8 @@ * and the problem, and then passes it off to one of the appropriate * routines. */ -asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, unsigned long write, - unsigned long address) +static void __kprobes __do_page_fault(struct pt_regs *regs, unsigned long write, + unsigned long address) { struct vm_area_struct * vma = NULL; struct task_struct *tsk = current; @@ -312,3 +313,13 @@ vmalloc_fault: } #endif } + +asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, + unsigned long write, unsigned long address) +{ + enum ctx_state prev_state; + + prev_state = exception_enter(); + __do_page_fault(regs, write, address); + exception_exit(prev_state); +} -- cgit v0.10.2 From 5a5f1efc8f5bce01773c6b769d7912a15e8eee07 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Tue, 11 Jun 2013 08:02:55 +0000 Subject: MIPS: kernel: mcount.S: Drop FRAME_POINTER codepath CONFIG_FRAME_POINTER is not selectable for MIPS so this codepath was never executed. Signed-off-by: Markos Chandras Acked-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5440/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S index 33d0671..a03e93c 100644 --- a/arch/mips/kernel/mcount.S +++ b/arch/mips/kernel/mcount.S @@ -168,15 +168,11 @@ NESTED(ftrace_graph_caller, PT_SIZE, ra) #endif /* arg3: Get frame pointer of current stack */ -#ifdef CONFIG_FRAME_POINTER - move a2, fp -#else /* ! CONFIG_FRAME_POINTER */ #ifdef CONFIG_64BIT PTR_LA a2, PT_SIZE(sp) #else PTR_LA a2, (PT_SIZE+8)(sp) #endif -#endif jal prepare_ftrace_return nop -- cgit v0.10.2 From b378758658d91656b864170ad896f45269c22e2f Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 11 Jun 2013 23:10:49 +0200 Subject: MIPS: Kconfig: Remove extranous help keyword. Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7a58ab9..49f98bf 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1030,7 +1030,6 @@ config CPU_BIG_ENDIAN config CPU_LITTLE_ENDIAN bool "Little endian" depends on SYS_SUPPORTS_LITTLE_ENDIAN - help endchoice -- cgit v0.10.2 From b8121f0f2fd9668ac4290bd969b664a4c1ca9ad5 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 12 Jun 2013 19:05:05 +0200 Subject: MIPS: : Don't reference CONFIG_* symbols. Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/uapi/asm/fcntl.h b/arch/mips/include/uapi/asm/fcntl.h index 0bda78f..6e9e746 100644 --- a/arch/mips/include/uapi/asm/fcntl.h +++ b/arch/mips/include/uapi/asm/fcntl.h @@ -8,6 +8,7 @@ #ifndef _ASM_FCNTL_H #define _ASM_FCNTL_H +#include #define O_APPEND 0x0008 #define O_DSYNC 0x0010 /* used to be O_SYNC, see below */ @@ -55,7 +56,8 @@ * contain all the same fields as struct flock. */ -#ifdef CONFIG_32BIT +#if _MIPS_SIM != _MIPS_SIM_ABI64 + #include struct flock { @@ -70,7 +72,7 @@ struct flock { #define HAVE_ARCH_STRUCT_FLOCK -#endif /* CONFIG_32BIT */ +#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ #include -- cgit v0.10.2 From e05eb3f8c1125405692bb0c41a13b560bc7f464d Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 12 Jun 2013 10:54:11 +0200 Subject: MIPS: Kconfig: Move ZONE_DMA to a more appropriate place. Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 87ddac9..f17ba1e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -46,9 +46,6 @@ config MIPS menu "Machine selection" -config ZONE_DMA - bool - choice prompt "System type" default SGI_IP22 @@ -2464,6 +2461,9 @@ config I8253 select CLKEVT_I8253 select MIPS_EXTERNAL_TIMER +config ZONE_DMA + bool + config ZONE_DMA32 bool -- cgit v0.10.2 From 0cecddecd3d0f4e2d9499ad2f226969e82910e79 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 11 Jun 2013 23:10:49 +0200 Subject: MIPS: Kconfig: Remove extranous help keyword. Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f17ba1e..a46b0a2 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1013,7 +1013,6 @@ config CPU_BIG_ENDIAN config CPU_LITTLE_ENDIAN bool "Little endian" depends on SYS_SUPPORTS_LITTLE_ENDIAN - help endchoice -- cgit v0.10.2 From 4954a9a211f1863e3ca3958fd56ad06e1bddc22d Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:28:08 +0000 Subject: MIPS: Support SWIOTLB in default dma operations Provide a default implementation of phys_to_dma and dma_to_phys in mach-generic/dma_coherence.h. If CONFIG_NEED_SG_DMA_LENGTH is defined, the dma_length field in struct scatterlist is used. Set this up in mips_dma_map_sg so that the default mips DMA ops can be used when SWIOTLB is enabled. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5409/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index fe23034..74cb992 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -66,4 +66,16 @@ static inline int plat_device_is_coherent(struct device *dev) #endif } +#ifdef CONFIG_SWIOTLB +static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) +{ + return paddr; +} + +static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) +{ + return daddr; +} +#endif + #endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index caf92ec..aaccf1c 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -246,6 +246,9 @@ static int mips_dma_map_sg(struct device *dev, struct scatterlist *sg, if (!plat_device_is_coherent(dev)) __dma_sync(sg_page(sg), sg->offset, sg->length, direction); +#ifdef CONFIG_NEED_SG_DMA_LENGTH + sg->dma_length = sg->length; +#endif sg->dma_address = plat_map_dma_mem_page(dev, sg_page(sg)) + sg->offset; } -- cgit v0.10.2 From 79f8511c83f13689913f54d2f189297c226ec064 Mon Sep 17 00:00:00 2001 From: Ganesan Ramalingam Date: Mon, 10 Jun 2013 06:28:09 +0000 Subject: MIPS: Netlogic: SWIOTLB dma ops for 32-bit DMA Add SWIOTLB config option and related files to Netlogic platform. Some XLP SoC components like the SD/MMC interface cannot do DMA beyond 32-bit physical address. The SD/MMC driver can use memory outside this range for IO, to support this we have to add bounce buffers implemented by SWIOTLB. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Cc: Ganesan Ramalingam Patchwork: https://patchwork.linux-mips.org/patch/5410/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h index aef560a..70351b9 100644 --- a/arch/mips/include/asm/netlogic/common.h +++ b/arch/mips/include/asm/netlogic/common.h @@ -76,6 +76,9 @@ void nlm_node_init(int node); extern struct plat_smp_ops nlm_smp_ops; extern char nlm_reset_entry[], nlm_reset_entry_end[]; +/* SWIOTLB */ +extern struct dma_map_ops nlm_swiotlb_dma_ops; + extern unsigned int nlm_threads_per_core; extern cpumask_t nlm_cpumask; diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig index e0873a3..2447bf9 100644 --- a/arch/mips/netlogic/Kconfig +++ b/arch/mips/netlogic/Kconfig @@ -51,4 +51,15 @@ endif config NLM_COMMON bool +config IOMMU_HELPER + bool + +config NEED_SG_DMA_LENGTH + bool + +config SWIOTLB + def_bool y + select NEED_SG_DMA_LENGTH + select IOMMU_HELPER + endif diff --git a/arch/mips/netlogic/common/Makefile b/arch/mips/netlogic/common/Makefile index 291372a..b295497 100644 --- a/arch/mips/netlogic/common/Makefile +++ b/arch/mips/netlogic/common/Makefile @@ -1,3 +1,4 @@ obj-y += irq.o time.o +obj-y += nlm-dma.o obj-$(CONFIG_SMP) += smp.o smpboot.o obj-$(CONFIG_EARLY_PRINTK) += earlycons.o diff --git a/arch/mips/netlogic/common/nlm-dma.c b/arch/mips/netlogic/common/nlm-dma.c new file mode 100644 index 0000000..f3d4ae8 --- /dev/null +++ b/arch/mips/netlogic/common/nlm-dma.c @@ -0,0 +1,107 @@ +/* +* Copyright (C) 2003-2013 Broadcom Corporation +* All Rights Reserved + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the Broadcom + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static char *nlm_swiotlb; + +static void *nlm_dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t gfp, struct dma_attrs *attrs) +{ + void *ret; + + if (dma_alloc_from_coherent(dev, size, dma_handle, &ret)) + return ret; + + /* ignore region specifiers */ + gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM); + +#ifdef CONFIG_ZONE_DMA32 + if (dev->coherent_dma_mask <= DMA_BIT_MASK(32)) + gfp |= __GFP_DMA32; +#endif + + /* Don't invoke OOM killer */ + gfp |= __GFP_NORETRY; + + return swiotlb_alloc_coherent(dev, size, dma_handle, gfp); +} + +static void nlm_dma_free_coherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle, struct dma_attrs *attrs) +{ + int order = get_order(size); + + if (dma_release_from_coherent(dev, order, vaddr)) + return; + + swiotlb_free_coherent(dev, size, vaddr, dma_handle); +} + +struct dma_map_ops nlm_swiotlb_dma_ops = { + .alloc = nlm_dma_alloc_coherent, + .free = nlm_dma_free_coherent, + .map_page = swiotlb_map_page, + .unmap_page = swiotlb_unmap_page, + .map_sg = swiotlb_map_sg_attrs, + .unmap_sg = swiotlb_unmap_sg_attrs, + .sync_single_for_cpu = swiotlb_sync_single_for_cpu, + .sync_single_for_device = swiotlb_sync_single_for_device, + .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu, + .sync_sg_for_device = swiotlb_sync_sg_for_device, + .mapping_error = swiotlb_dma_mapping_error, + .dma_supported = swiotlb_dma_supported +}; + +void __init plat_swiotlb_setup(void) +{ + size_t swiotlbsize; + unsigned long swiotlb_nslabs; + + swiotlbsize = 1 << 20; /* 1 MB for now */ + swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT; + swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE); + swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT; + + nlm_swiotlb = alloc_bootmem_low_pages(swiotlbsize); + swiotlb_init_with_tbl(nlm_swiotlb, swiotlb_nslabs, 1); +} -- cgit v0.10.2 From 2c952e06e4f57716109b609956eda28c900faac0 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:30:00 +0000 Subject: MIPS: Move cop2 save/restore to switch_to() Move the common code for saving and restoring platform specific COP2 registers to switch_to(). This will make supporting new platforms (like Netlogic XLP) easier. The platform specific COP2 definitions are to be specified in asm/processor.h and in asm/cop2.h. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5411/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h index 3532e2c..b17f38e 100644 --- a/arch/mips/include/asm/cop2.h +++ b/arch/mips/include/asm/cop2.h @@ -11,6 +11,25 @@ #include +#if defined(CONFIG_CPU_CAVIUM_OCTEON) + +extern void octeon_cop2_save(struct octeon_cop2_state *); +extern void octeon_cop2_restore(struct octeon_cop2_state *); + +#define cop2_save(r) octeon_cop2_save(r) +#define cop2_restore(r) octeon_cop2_restore(r) + +#define cop2_present 1 +#define cop2_lazy_restore 1 + +#else + +#define cop2_present 0 +#define cop2_lazy_restore 0 +#define cop2_save(r) +#define cop2_restore(r) +#endif + enum cu2_ops { CU2_EXCEPTION, CU2_LWC2_OP, diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 1470b7b..7c637a4 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -137,7 +137,7 @@ union mips_watch_reg_state { struct mips3264_watch_reg_state mips3264; }; -#ifdef CONFIG_CPU_CAVIUM_OCTEON +#if defined(CONFIG_CPU_CAVIUM_OCTEON) struct octeon_cop2_state { /* DMFC2 rt, 0x0201 */ @@ -182,13 +182,16 @@ struct octeon_cop2_state { /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */ unsigned long cop2_gfm_result[2]; }; -#define INIT_OCTEON_COP2 {0,} +#define COP2_INIT \ + .cp2 = {0,}, struct octeon_cvmseg_state { unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE] [cpu_dcache_line_size() / sizeof(unsigned long)]; }; +#else +#define COP2_INIT #endif typedef struct { @@ -245,13 +248,6 @@ struct thread_struct { #define FPAFF_INIT #endif /* CONFIG_MIPS_MT_FPAFF */ -#ifdef CONFIG_CPU_CAVIUM_OCTEON -#define OCTEON_INIT \ - .cp2 = INIT_OCTEON_COP2, -#else -#define OCTEON_INIT -#endif /* CONFIG_CPU_CAVIUM_OCTEON */ - #define INIT_THREAD { \ /* \ * Saved main processor registers \ @@ -300,9 +296,9 @@ struct thread_struct { .cp0_baduaddr = 0, \ .error_code = 0, \ /* \ - * Cavium Octeon specifics (null if not Octeon) \ + * Platform specific cop2 registers(null if no COP2) \ */ \ - OCTEON_INIT \ + COP2_INIT \ } struct task_struct; diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h index fd16bcb..eb0af15 100644 --- a/arch/mips/include/asm/switch_to.h +++ b/arch/mips/include/asm/switch_to.h @@ -15,6 +15,7 @@ #include #include #include +#include struct task_struct; @@ -66,10 +67,18 @@ do { \ #define switch_to(prev, next, last) \ do { \ - u32 __usedfpu; \ + u32 __usedfpu, __c0_stat; \ __mips_mt_fpaff_switch_to(prev); \ if (cpu_has_dsp) \ __save_dsp(prev); \ + if (cop2_present && (KSTK_STATUS(prev) & ST0_CU2)) { \ + if (cop2_lazy_restore) \ + KSTK_STATUS(prev) &= ~ST0_CU2; \ + __c0_stat = read_c0_status(); \ + write_c0_status(__c0_stat | ST0_CU2); \ + cop2_save(&prev->thread.cp2); \ + write_c0_status(__c0_stat & ~ST0_CU2); \ + } \ __clear_software_ll_bit(); \ __usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU); \ (last) = resume(prev, next, task_thread_info(next), __usedfpu); \ @@ -77,6 +86,14 @@ do { \ #define finish_arch_switch(prev) \ do { \ + u32 __c0_stat; \ + if (cop2_present && !cop2_lazy_restore && \ + (KSTK_STATUS(current) & ST0_CU2)) { \ + __c0_stat = read_c0_status(); \ + write_c0_status(__c0_stat | ST0_CU2); \ + cop2_restore(¤t->thread.cp2); \ + write_c0_status(__c0_stat & ~ST0_CU2); \ + } \ if (cpu_has_dsp) \ __restore_dsp(current); \ if (cpu_has_userlocal) \ diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S index 0e23343..22e2aa1 100644 --- a/arch/mips/kernel/octeon_switch.S +++ b/arch/mips/kernel/octeon_switch.S @@ -40,33 +40,6 @@ cpu_save_nonscratch a0 LONG_S ra, THREAD_REG31(a0) - /* check if we need to save COP2 registers */ - PTR_L t2, TASK_THREAD_INFO(a0) - LONG_L t0, ST_OFF(t2) - bbit0 t0, 30, 1f - - /* Disable COP2 in the stored process state */ - li t1, ST0_CU2 - xor t0, t1 - LONG_S t0, ST_OFF(t2) - - /* Enable COP2 so we can save it */ - mfc0 t0, CP0_STATUS - or t0, t1 - mtc0 t0, CP0_STATUS - - /* Save COP2 */ - daddu a0, THREAD_CP2 - jal octeon_cop2_save - dsubu a0, THREAD_CP2 - - /* Disable COP2 now that we are done */ - mfc0 t0, CP0_STATUS - li t1, ST0_CU2 - xor t0, t1 - mtc0 t0, CP0_STATUS - -1: #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 /* Check if we need to store CVMSEG state */ mfc0 t0, $11,7 /* CvmMemCtl */ -- cgit v0.10.2 From 83bee792d7cb20d250be57e99d97f8cc83d9b4d5 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:30:01 +0000 Subject: MIPS: Allow kernel to use coprocessor 2 Kernel threads should be able to use COP2 if the platform needs it. Do not call die_if_kernel() for a coprocessor unusable exception if the exception due to COP2 usage. Instead, the default notifier for COP2 exceptions is updated to call die_if_kernel. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5415/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index beba1e6..142d2be 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1056,15 +1056,9 @@ static int default_cu2_call(struct notifier_block *nfb, unsigned long action, { struct pt_regs *regs = data; - switch (action) { - default: - die_if_kernel("Unhandled kernel unaligned access or invalid " + die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " "instruction", regs); - /* Fall through */ - - case CU2_EXCEPTION: - force_sig(SIGILL, current); - } + force_sig(SIGILL, current); return NOTIFY_OK; } @@ -1080,10 +1074,11 @@ asmlinkage void do_cpu(struct pt_regs *regs) unsigned long __maybe_unused flags; prev_state = exception_enter(); - die_if_kernel("do_cpu invoked from kernel context!", regs); - cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; + if (cpid != 2) + die_if_kernel("do_cpu invoked from kernel context!", regs); + switch (cpid) { case 0: epc = (unsigned int __user *)exception_epc(regs); -- cgit v0.10.2 From 1c146cd46fccfaa5525152f086da2752fe0ed4dd Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:30:02 +0000 Subject: MIPS: Netlogic: Fix nlm_read_c2_status() definition The sel argument os nlm_read_c2_status() was not used and the macro returned the sel 0 in all cases. Fix this by defining two macros: nlm_read_c2_status0() and nlm_read_c2_status1() to return the two status registers. Add functions to write to the status registers as well. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5414/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/netlogic/xlr/fmn.h b/arch/mips/include/asm/netlogic/xlr/fmn.h index 2a78929..56c7b85 100644 --- a/arch/mips/include/asm/netlogic/xlr/fmn.h +++ b/arch/mips/include/asm/netlogic/xlr/fmn.h @@ -175,6 +175,10 @@ #define nlm_write_c2_cc14(s, v) __write_32bit_c2_register($30, s, v) #define nlm_write_c2_cc15(s, v) __write_32bit_c2_register($31, s, v) +#define nlm_read_c2_status0() __read_32bit_c2_register($2, 0) +#define nlm_write_c2_status0(v) __write_32bit_c2_register($2, 0, v) +#define nlm_read_c2_status1() __read_32bit_c2_register($2, 1) +#define nlm_write_c2_status1(v) __write_32bit_c2_register($2, 1, v) #define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0) #define nlm_read_c2_config() __read_32bit_c2_register($3, 0) #define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v) @@ -296,7 +300,7 @@ static inline int nlm_fmn_send(unsigned int size, unsigned int code, */ for (i = 0; i < 8; i++) { nlm_msgsnd(dest); - status = nlm_read_c2_status(0); + status = nlm_read_c2_status0(); if ((status & 0x2) == 1) pr_info("Send pending fail!\n"); if ((status & 0x4) == 0) @@ -316,7 +320,7 @@ static inline int nlm_fmn_receive(int bucket, int *size, int *code, int *stid, /* wait for load pending to clear */ do { - status = nlm_read_c2_status(1); + status = nlm_read_c2_status0(); } while ((status & 0x08) != 0); /* receive error bits */ diff --git a/arch/mips/netlogic/xlr/fmn.c b/arch/mips/netlogic/xlr/fmn.c index 4d74f03..0fdce61 100644 --- a/arch/mips/netlogic/xlr/fmn.c +++ b/arch/mips/netlogic/xlr/fmn.c @@ -80,7 +80,7 @@ static irqreturn_t fmn_message_handler(int irq, void *data) while (1) { /* 8 bkts per core, [24:31] each bit represents one bucket * Bit is Zero if bucket is not empty */ - bkt_status = (nlm_read_c2_status() >> 24) & 0xff; + bkt_status = (nlm_read_c2_status0() >> 24) & 0xff; if (bkt_status == 0xff) break; for (bucket = 0; bucket < 8; bucket++) { -- cgit v0.10.2 From 64f6ebe63914835ad5cd5bc4c490f3deaeac2511 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:30:03 +0000 Subject: MIPS: Netlogic: rename nlm_cop2_save/restore Rename macro nlm_cop2_enable() to nlm_cop2_enable_irqsave() and the macro nlm_cop2_restore to nlm_cop2_disable_irqrestore(). The new names will reflect the functionality better, and will make nlm_cop2_restore() available to be used later in COP2 save/restore patch. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5412/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/netlogic/xlr/fmn.h b/arch/mips/include/asm/netlogic/xlr/fmn.h index 56c7b85..5604db3 100644 --- a/arch/mips/include/asm/netlogic/xlr/fmn.h +++ b/arch/mips/include/asm/netlogic/xlr/fmn.h @@ -241,7 +241,7 @@ static inline void nlm_msgwait(unsigned int mask) /* * Disable interrupts and enable COP2 access */ -static inline uint32_t nlm_cop2_enable(void) +static inline uint32_t nlm_cop2_enable_irqsave(void) { uint32_t sr = read_c0_status(); @@ -249,7 +249,7 @@ static inline uint32_t nlm_cop2_enable(void) return sr; } -static inline void nlm_cop2_restore(uint32_t sr) +static inline void nlm_cop2_disable_irqrestore(uint32_t sr) { write_c0_status(sr); } diff --git a/arch/mips/netlogic/xlr/fmn.c b/arch/mips/netlogic/xlr/fmn.c index 0fdce61..d428e84 100644 --- a/arch/mips/netlogic/xlr/fmn.c +++ b/arch/mips/netlogic/xlr/fmn.c @@ -74,7 +74,7 @@ static irqreturn_t fmn_message_handler(int irq, void *data) struct nlm_fmn_msg msg; uint32_t mflags, bkt_status; - mflags = nlm_cop2_enable(); + mflags = nlm_cop2_enable_irqsave(); /* Disable message ring interrupt */ nlm_fmn_setup_intr(irq, 0); while (1) { @@ -97,16 +97,16 @@ static irqreturn_t fmn_message_handler(int irq, void *data) pr_warn("No msgring handler for stnid %d\n", src_stnid); else { - nlm_cop2_restore(mflags); + nlm_cop2_disable_irqrestore(mflags); hndlr->action(bucket, src_stnid, size, code, &msg, hndlr->arg); - mflags = nlm_cop2_enable(); + mflags = nlm_cop2_enable_irqsave(); } } }; /* Enable message ring intr, to any thread in core */ nlm_fmn_setup_intr(irq, (1 << nlm_threads_per_core) - 1); - nlm_cop2_restore(mflags); + nlm_cop2_disable_irqrestore(mflags); return IRQ_HANDLED; } @@ -128,7 +128,7 @@ void xlr_percpu_fmn_init(void) bucket_sizes = xlr_board_fmn_config.bucket_size; cpu_fmn_info = &xlr_board_fmn_config.cpu[id]; - flags = nlm_cop2_enable(); + flags = nlm_cop2_enable_irqsave(); /* Setup bucket sizes for the core. */ nlm_write_c2_bucksize(0, bucket_sizes[id * 8 + 0]); @@ -166,7 +166,7 @@ void xlr_percpu_fmn_init(void) /* enable FMN interrupts on this CPU */ nlm_fmn_setup_intr(IRQ_FMN, (1 << nlm_threads_per_core) - 1); - nlm_cop2_restore(flags); + nlm_cop2_disable_irqrestore(flags); } @@ -198,7 +198,7 @@ void nlm_setup_fmn_irq(void) /* setup irq only once */ setup_irq(IRQ_FMN, &fmn_irqaction); - flags = nlm_cop2_enable(); + flags = nlm_cop2_enable_irqsave(); nlm_fmn_setup_intr(IRQ_FMN, (1 << nlm_threads_per_core) - 1); - nlm_cop2_restore(flags); + nlm_cop2_disable_irqrestore(flags); } -- cgit v0.10.2 From 5649d37c2b23ad6545709c976b9abbfa8d5f4e11 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:30:04 +0000 Subject: MIPS: Netlogic: COP2 save/restore code Add COP2 register state structure and functions for Netlogic XLP. The RX and TX buffers and status registers are to be saved. Since the registers are 64-bit, do the implementation in inline assembly which works on both 32-bit and 64-bit kernels. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5413/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h index b17f38e..c1516cc 100644 --- a/arch/mips/include/asm/cop2.h +++ b/arch/mips/include/asm/cop2.h @@ -22,6 +22,16 @@ extern void octeon_cop2_restore(struct octeon_cop2_state *); #define cop2_present 1 #define cop2_lazy_restore 1 +#elif defined(CONFIG_CPU_XLP) + +extern void nlm_cop2_save(struct nlm_cop2_state *); +extern void nlm_cop2_restore(struct nlm_cop2_state *); +#define cop2_save(r) nlm_cop2_save(r) +#define cop2_restore(r) nlm_cop2_restore(r) + +#define cop2_present 1 +#define cop2_lazy_restore 0 + #else #define cop2_present 0 diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 7c637a4..016dc4b 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -190,6 +190,16 @@ struct octeon_cvmseg_state { [cpu_dcache_line_size() / sizeof(unsigned long)]; }; +#elif defined(CONFIG_CPU_XLP) +struct nlm_cop2_state { + u64 rx[4]; + u64 tx[4]; + u32 tx_msg_status; + u32 rx_msg_status; +}; + +#define COP2_INIT \ + .cp2 = {{0}, {0}, 0, 0}, #else #define COP2_INIT #endif @@ -237,6 +247,9 @@ struct thread_struct { struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); #endif +#ifdef CONFIG_CPU_XLP + struct nlm_cop2_state cp2; +#endif struct mips_abi *abi; }; diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile index a84d6ed..e8dd14c 100644 --- a/arch/mips/netlogic/xlp/Makefile +++ b/arch/mips/netlogic/xlp/Makefile @@ -1,3 +1,3 @@ -obj-y += setup.o nlm_hal.o +obj-y += setup.o nlm_hal.o cop2-ex.o obj-$(CONFIG_SMP) += wakeup.o obj-$(CONFIG_USB) += usb-init.o diff --git a/arch/mips/netlogic/xlp/cop2-ex.c b/arch/mips/netlogic/xlp/cop2-ex.c new file mode 100644 index 0000000..52bc5de --- /dev/null +++ b/arch/mips/netlogic/xlp/cop2-ex.c @@ -0,0 +1,118 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2013 Broadcom Corporation. + * + * based on arch/mips/cavium-octeon/cpu.c + * Copyright (C) 2009 Wind River Systems, + * written by Ralf Baechle + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +/* + * 64 bit ops are done in inline assembly to support 32 bit + * compilation + */ +void nlm_cop2_save(struct nlm_cop2_state *r) +{ + asm volatile( + ".set push\n" + ".set noat\n" + "dmfc2 $1, $0, 0\n" + "sd $1, 0(%1)\n" + "dmfc2 $1, $0, 1\n" + "sd $1, 8(%1)\n" + "dmfc2 $1, $0, 2\n" + "sd $1, 16(%1)\n" + "dmfc2 $1, $0, 3\n" + "sd $1, 24(%1)\n" + "dmfc2 $1, $1, 0\n" + "sd $1, 0(%2)\n" + "dmfc2 $1, $1, 1\n" + "sd $1, 8(%2)\n" + "dmfc2 $1, $1, 2\n" + "sd $1, 16(%2)\n" + "dmfc2 $1, $1, 3\n" + "sd $1, 24(%2)\n" + ".set pop\n" + : "=m"(*r) + : "r"(r->tx), "r"(r->rx)); + + r->tx_msg_status = __read_32bit_c2_register($2, 0); + r->rx_msg_status = __read_32bit_c2_register($3, 0) & 0x0fffffff; +} + +void nlm_cop2_restore(struct nlm_cop2_state *r) +{ + u32 rstat; + + asm volatile( + ".set push\n" + ".set noat\n" + "ld $1, 0(%1)\n" + "dmtc2 $1, $0, 0\n" + "ld $1, 8(%1)\n" + "dmtc2 $1, $0, 1\n" + "ld $1, 16(%1)\n" + "dmtc2 $1, $0, 2\n" + "ld $1, 24(%1)\n" + "dmtc2 $1, $0, 3\n" + "ld $1, 0(%2)\n" + "dmtc2 $1, $1, 0\n" + "ld $1, 8(%2)\n" + "dmtc2 $1, $1, 1\n" + "ld $1, 16(%2)\n" + "dmtc2 $1, $1, 2\n" + "ld $1, 24(%2)\n" + "dmtc2 $1, $1, 3\n" + ".set pop\n" + : : "m"(*r), "r"(r->tx), "r"(r->rx)); + + __write_32bit_c2_register($2, 0, r->tx_msg_status); + rstat = __read_32bit_c2_register($3, 0) & 0xf0000000u; + __write_32bit_c2_register($3, 0, r->rx_msg_status | rstat); +} + +static int nlm_cu2_call(struct notifier_block *nfb, unsigned long action, + void *data) +{ + unsigned long flags; + unsigned int status; + + switch (action) { + case CU2_EXCEPTION: + if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) + break; + local_irq_save(flags); + KSTK_STATUS(current) |= ST0_CU2; + status = read_c0_status(); + write_c0_status(status | ST0_CU2); + nlm_cop2_restore(&(current->thread.cp2)); + write_c0_status(status & ~ST0_CU2); + local_irq_restore(flags); + pr_info("COP2 access enabled for pid %d (%s)\n", + current->pid, current->comm); + return NOTIFY_BAD; /* Don't call default notifier */ + } + + return NOTIFY_OK; /* Let default notifier send signals */ +} + +static int __init nlm_cu2_setup(void) +{ + return cu2_notifier(nlm_cu2_call, 0); +} +early_initcall(nlm_cu2_setup); -- cgit v0.10.2 From d6a5078459d95137d8d620787d1099a3016932a9 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:33:25 +0000 Subject: MIPS: boot: Fixes for compressed/uart-16550.c Fix uart-16550.c for adding XLR/XLP support, changes are: * Make register read/write use volatile pointers * Support 32 bit IO read/write * Increase timeout in waiting for UART LSR Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5416/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c index 1c7b739..90ae440 100644 --- a/arch/mips/boot/compressed/uart-16550.c +++ b/arch/mips/boot/compressed/uart-16550.c @@ -23,23 +23,27 @@ #define PORT(offset) (UART0_BASE + (4 * offset)) #endif +#ifndef IOTYPE +#define IOTYPE char +#endif + #ifndef PORT #error please define the serial port address for your own machine #endif static inline unsigned int serial_in(int offset) { - return *((char *)PORT(offset)); + return *((volatile IOTYPE *)PORT(offset)) & 0xFF; } static inline void serial_out(int offset, int value) { - *((char *)PORT(offset)) = value; + *((volatile IOTYPE *)PORT(offset)) = value & 0xFF; } void putc(char c) { - int timeout = 1024; + int timeout = 1000000; while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0)) ; -- cgit v0.10.2 From 8f0b043045d0b19d7eb8b510bfe279c9bb05d952 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:33:26 +0000 Subject: MIPS: Netlogic: Support compressed kernel Add SYS_SUPPORTS_ZBOOT and SYS_SUPPORTS_ZBOOT_UART16550 config options for XLR and XLP. Update boot/compressed/uart-16550.c to add UART port for XLR and XLP. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5417/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a46b0a2..69bf310 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -788,6 +788,8 @@ config NLM_XLR_BOARD select SYS_HAS_EARLY_PRINTK select USB_ARCH_HAS_OHCI if USB_SUPPORT select USB_ARCH_HAS_EHCI if USB_SUPPORT + select SYS_SUPPORTS_ZBOOT + select SYS_SUPPORTS_ZBOOT_UART16550 help Support for systems based on Netlogic XLR and XLS processors. Say Y here if you have a XLR or XLS based board. @@ -814,6 +816,8 @@ config NLM_XLP_BOARD select SYNC_R4K select SYS_HAS_EARLY_PRINTK select USE_OF + select SYS_SUPPORTS_ZBOOT + select SYS_SUPPORTS_ZBOOT_UART16550 help This board is based on Netlogic XLP Processor. Say Y here if you have a XLP based board. diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c index 90ae440..c01d343 100644 --- a/arch/mips/boot/compressed/uart-16550.c +++ b/arch/mips/boot/compressed/uart-16550.c @@ -23,6 +23,18 @@ #define PORT(offset) (UART0_BASE + (4 * offset)) #endif +#ifdef CONFIG_CPU_XLR +#define UART0_BASE 0x1EF14000 +#define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) +#define IOTYPE unsigned int +#endif + +#ifdef CONFIG_CPU_XLP +#define UART0_BASE 0x18030100 +#define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) +#define IOTYPE unsigned int +#endif + #ifndef IOTYPE #define IOTYPE char #endif -- cgit v0.10.2 From aceee09d4f09dd7a6be48d04d329c140a5caaaf7 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:41:00 +0000 Subject: MIPS: Netlogic: Split XLP device tree code to dt.c Create new flle arch/mips/netlogic/xlp/dt.c and move the device tree related code there. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5422/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h index 7e47209..f4ea0f7 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h @@ -59,6 +59,7 @@ void xlp_wakeup_secondary_cpus(void); void xlp_mmu_init(void); void nlm_hal_init(void); +void *xlp_dt_init(void *fdtp); #endif /* !__ASSEMBLY__ */ #endif /* _ASM_NLM_XLP_H */ diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile index e8dd14c..85ac4a8 100644 --- a/arch/mips/netlogic/xlp/Makefile +++ b/arch/mips/netlogic/xlp/Makefile @@ -1,3 +1,3 @@ -obj-y += setup.o nlm_hal.o cop2-ex.o +obj-y += setup.o nlm_hal.o cop2-ex.o dt.o obj-$(CONFIG_SMP) += wakeup.o obj-$(CONFIG_USB) += usb-init.o diff --git a/arch/mips/netlogic/xlp/dt.c b/arch/mips/netlogic/xlp/dt.c new file mode 100644 index 0000000..a15cdbb --- /dev/null +++ b/arch/mips/netlogic/xlp/dt.c @@ -0,0 +1,99 @@ +/* + * Copyright 2003-2013 Broadcom Corporation. + * All Rights Reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the Broadcom + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include + +extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], __dtb_start[]; + +void __init *xlp_dt_init(void *fdtp) +{ + if (!fdtp) { + switch (current_cpu_data.processor_id & 0xff00) { +#ifdef CONFIG_DT_XLP_SVP + case PRID_IMP_NETLOGIC_XLP3XX: + fdtp = __dtb_xlp_svp_begin; + break; +#endif +#ifdef CONFIG_DT_XLP_EVP + case PRID_IMP_NETLOGIC_XLP8XX: + fdtp = __dtb_xlp_evp_begin; + break; +#endif + default: + /* Pick a built-in if any, and hope for the best */ + fdtp = __dtb_start; + break; + } + } + initial_boot_params = fdtp; + return fdtp; +} + +void __init device_tree_init(void) +{ + unsigned long base, size; + + if (!initial_boot_params) + return; + + base = virt_to_phys((void *)initial_boot_params); + size = be32_to_cpu(initial_boot_params->totalsize); + + /* Before we do anything, lets reserve the dt blob */ + reserve_bootmem(base, size, BOOTMEM_DEFAULT); + + unflatten_device_tree(); + + /* free the space reserved for the dt blob */ + free_bootmem(base, size); +} + +static struct of_device_id __initdata xlp_ids[] = { + { .compatible = "simple-bus", }, + {}, +}; + +int __init xlp8xx_ds_publish_devices(void) +{ + if (!of_have_populated_dt()) + return 0; + return of_platform_bus_probe(NULL, xlp_ids, NULL); +} + +device_initcall(xlp8xx_ds_publish_devices); diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c index eaa99d2..7b66949 100644 --- a/arch/mips/netlogic/xlp/setup.c +++ b/arch/mips/netlogic/xlp/setup.c @@ -33,19 +33,13 @@ */ #include -#include -#include -#include +#include #include #include #include #include -#include -#include -#include - #include #include @@ -57,7 +51,6 @@ uint64_t nlm_io_base; struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; cpumask_t nlm_cpumask = CPU_MASK_CPU0; unsigned int nlm_threads_per_core; -extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], __dtb_start[]; static void nlm_linux_exit(void) { @@ -70,39 +63,13 @@ static void nlm_linux_exit(void) void __init plat_mem_setup(void) { - void *fdtp; - panic_timeout = 5; _machine_restart = (void (*)(char *))nlm_linux_exit; _machine_halt = nlm_linux_exit; pm_power_off = nlm_linux_exit; - /* - * If no FDT pointer is passed in, use the built-in FDT. - * device_tree_init() does not handle CKSEG0 pointers in - * 64-bit, so convert pointer. - */ - fdtp = (void *)(long)fw_arg0; - if (!fdtp) { - switch (current_cpu_data.processor_id & 0xff00) { -#ifdef CONFIG_DT_XLP_SVP - case PRID_IMP_NETLOGIC_XLP3XX: - fdtp = __dtb_xlp_svp_begin; - break; -#endif -#ifdef CONFIG_DT_XLP_EVP - case PRID_IMP_NETLOGIC_XLP8XX: - fdtp = __dtb_xlp_evp_begin; - break; -#endif - default: - /* Pick a built-in if any, and hope for the best */ - fdtp = __dtb_start; - break; - } - } - fdtp = phys_to_virt(__pa(fdtp)); - early_init_devtree(fdtp); + /* memory and bootargs from DT */ + early_init_devtree(initial_boot_params); } const char *get_system_type(void) @@ -134,6 +101,7 @@ void __init prom_init(void) nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE); xlp_mmu_init(); nlm_node_init(0); + xlp_dt_init((void *)(long)fw_arg0); #ifdef CONFIG_SMP cpumask_setall(&nlm_cpumask); @@ -145,36 +113,3 @@ void __init prom_init(void) register_smp_ops(&nlm_smp_ops); #endif } - -void __init device_tree_init(void) -{ - unsigned long base, size; - - if (!initial_boot_params) - return; - - base = virt_to_phys((void *)initial_boot_params); - size = be32_to_cpu(initial_boot_params->totalsize); - - /* Before we do anything, lets reserve the dt blob */ - reserve_bootmem(base, size, BOOTMEM_DEFAULT); - - unflatten_device_tree(); - - /* free the space reserved for the dt blob */ - free_bootmem(base, size); -} - -static struct of_device_id __initdata xlp_ids[] = { - { .compatible = "simple-bus", }, - {}, -}; - -int __init xlp8xx_ds_publish_devices(void) -{ - if (!of_have_populated_dt()) - return 0; - return of_platform_bus_probe(NULL, xlp_ids, NULL); -} - -device_initcall(xlp8xx_ds_publish_devices); -- cgit v0.10.2 From 9584c55a5cc0db82329dd1142ca570e2d64ea491 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:41:01 +0000 Subject: MIPS: Netlogic: Split reset code out of smpboot.S The reset and core initialization code should be available for uniprocessor as well. This changes is just to take out the code into a different file, without any change to the logic. The change for uniprocessor initialization code is in a later patch. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5423/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h index 70351b9..d4ede12 100644 --- a/arch/mips/include/asm/netlogic/common.h +++ b/arch/mips/include/asm/netlogic/common.h @@ -71,6 +71,7 @@ nlm_set_nmi_handler(void *handler) /* * Misc. */ +void nlm_init_boot_cpu(void); unsigned int nlm_get_cpu_frequency(void); void nlm_node_init(int node); extern struct plat_smp_ops nlm_smp_ops; diff --git a/arch/mips/netlogic/common/Makefile b/arch/mips/netlogic/common/Makefile index b295497..a396a39 100644 --- a/arch/mips/netlogic/common/Makefile +++ b/arch/mips/netlogic/common/Makefile @@ -1,4 +1,4 @@ obj-y += irq.o time.o obj-y += nlm-dma.o -obj-$(CONFIG_SMP) += smp.o smpboot.o +obj-$(CONFIG_SMP) += smp.o smpboot.o reset.o obj-$(CONFIG_EARLY_PRINTK) += earlycons.o diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S new file mode 100644 index 0000000..98691d6 --- /dev/null +++ b/arch/mips/netlogic/common/reset.S @@ -0,0 +1,249 @@ +/* + * Copyright 2003-2013 Broadcom Corporation. + * All Rights Reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the Broadcom + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#define CP0_EBASE $15 +#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \ + XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ + SYS_CPU_NONCOHERENT_MODE * 4 + +#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */ + +/* Enable XLP features and workarounds in the LSU */ +.macro xlp_config_lsu + li t0, LSU_DEFEATURE + mfcr t1, t0 + + lui t2, 0xc080 /* SUE, Enable Unaligned Access, L2HPE */ + or t1, t1, t2 +#ifdef XLP_AX_WORKAROUND + li t2, ~0xe /* S1RCM */ + and t1, t1, t2 +#endif + mtcr t1, t0 + + li t0, ICU_DEFEATURE + mfcr t1, t0 + ori t1, 0x1000 /* Enable Icache partitioning */ + mtcr t1, t0 + + +#ifdef XLP_AX_WORKAROUND + li t0, SCHED_DEFEATURE + lui t1, 0x0100 /* Disable BRU accepting ALU ops */ + mtcr t1, t0 +#endif +.endm + +/* + * Low level flush for L1D cache on XLP, the normal cache ops does + * not do the complete and correct cache flush. + */ +.macro xlp_flush_l1_dcache + li t0, LSU_DEBUG_DATA0 + li t1, LSU_DEBUG_ADDR + li t2, 0 /* index */ + li t3, 0x1000 /* loop count */ +1: + sll v0, t2, 5 + mtcr zero, t0 + ori v1, v0, 0x3 /* way0 | write_enable | write_active */ + mtcr v1, t1 +2: + mfcr v1, t1 + andi v1, 0x1 /* wait for write_active == 0 */ + bnez v1, 2b + nop + mtcr zero, t0 + ori v1, v0, 0x7 /* way1 | write_enable | write_active */ + mtcr v1, t1 +3: + mfcr v1, t1 + andi v1, 0x1 /* wait for write_active == 0 */ + bnez v1, 3b + nop + addi t2, 1 + bne t3, t2, 1b + nop +.endm + +/* + * nlm_reset_entry will be copied to the reset entry point for + * XLR and XLP. The XLP cores start here when they are woken up. This + * is also the NMI entry point. + * + * We use scratch reg 6/7 to save k0/k1 and check for NMI first. + * + * The data corresponding to reset/NMI is stored at RESET_DATA_PHYS + * location, this will have the thread mask (used when core is woken up) + * and the current NMI handler in case we reached here for an NMI. + * + * When a core or thread is newly woken up, it marks itself ready and + * loops in a 'wait'. When the CPU really needs waking up, we send an NMI + * IPI to it, with the NMI handler set to prom_boot_secondary_cpus + */ + .set noreorder + .set noat + .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */ + +FEXPORT(nlm_reset_entry) + dmtc0 k0, $22, 6 + dmtc0 k1, $22, 7 + mfc0 k0, CP0_STATUS + li k1, 0x80000 + and k1, k0, k1 + beqz k1, 1f /* go to real reset entry */ + nop + li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */ + ld k0, BOOT_NMI_HANDLER(k1) + jr k0 + nop + +1: /* Entry point on core wakeup */ + mfc0 t0, CP0_EBASE, 1 + mfc0 t1, CP0_EBASE, 1 + srl t1, 5 + andi t1, 0x3 /* t1 <- node */ + li t2, 0x40000 + mul t3, t2, t1 /* t3 = node * 0x40000 */ + srl t0, t0, 2 + and t0, t0, 0x7 /* t0 <- core */ + li t1, 0x1 + sll t0, t1, t0 + nor t0, t0, zero /* t0 <- ~(1 << core) */ + li t2, SYS_CPU_COHERENT_BASE(0) + add t2, t2, t3 /* t2 <- SYS offset for node */ + lw t1, 0(t2) + and t1, t1, t0 + sw t1, 0(t2) + + /* read back to ensure complete */ + lw t1, 0(t2) + sync + + /* Configure LSU on Non-0 Cores. */ + xlp_config_lsu + /* FALL THROUGH */ + +/* + * Wake up sibling threads from the initial thread in + * a core. + */ +EXPORT(nlm_boot_siblings) + /* core L1D flush before enable threads */ + xlp_flush_l1_dcache + /* Enable hw threads by writing to MAP_THREADMODE of the core */ + li t0, CKSEG1ADDR(RESET_DATA_PHYS) + lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */ + li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE) + mfcr t2, t0 + or t2, t2, t1 + mtcr t2, t0 + + /* + * The new hardware thread starts at the next instruction + * For all the cases other than core 0 thread 0, we will + * jump to the secondary wait function. + */ + mfc0 v0, CP0_EBASE, 1 + andi v0, 0x3ff /* v0 <- node/core */ + + /* Init MMU in the first thread after changing THREAD_MODE + * register (Ax Errata?) + */ + andi v1, v0, 0x3 /* v1 <- thread id */ + bnez v1, 2f + nop + + li t0, MMU_SETUP + li t1, 0 + mtcr t1, t0 + _ehb + +2: beqz v0, 4f /* boot cpu (cpuid == 0)? */ + nop + + /* setup status reg */ + move t1, zero +#ifdef CONFIG_64BIT + ori t1, ST0_KX +#endif + mtc0 t1, CP0_STATUS + /* mark CPU ready */ + PTR_LA t1, nlm_cpu_ready + sll v1, v0, 2 + PTR_ADDU t1, v1 + li t2, 1 + sw t2, 0(t1) + /* Wait until NMI hits */ +3: wait + j 3b + nop + + /* + * For the boot CPU, we have to restore registers and + * return + */ +4: dmfc0 t0, $4, 2 /* restore SP from UserLocal */ + li t1, 0xfadebeef + dmtc0 t1, $4, 2 /* restore SP from UserLocal */ + PTR_SUBU sp, t0, PT_SIZE + RESTORE_ALL + jr ra + nop +EXPORT(nlm_reset_entry_end) + +LEAF(nlm_init_boot_cpu) +#ifdef CONFIG_CPU_XLP + xlp_config_lsu +#endif + jr ra + nop +END(nlm_init_boot_cpu) diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S index 0265174..7c7e884 100644 --- a/arch/mips/netlogic/common/smpboot.S +++ b/arch/mips/netlogic/common/smpboot.S @@ -50,197 +50,12 @@ #include #define CP0_EBASE $15 -#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \ - XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ - SYS_CPU_NONCOHERENT_MODE * 4 - -#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */ - -/* Enable XLP features and workarounds in the LSU */ -.macro xlp_config_lsu - li t0, LSU_DEFEATURE - mfcr t1, t0 - - lui t2, 0xc080 /* SUE, Enable Unaligned Access, L2HPE */ - or t1, t1, t2 -#ifdef XLP_AX_WORKAROUND - li t2, ~0xe /* S1RCM */ - and t1, t1, t2 -#endif - mtcr t1, t0 - - li t0, ICU_DEFEATURE - mfcr t1, t0 - ori t1, 0x1000 /* Enable Icache partitioning */ - mtcr t1, t0 - - -#ifdef XLP_AX_WORKAROUND - li t0, SCHED_DEFEATURE - lui t1, 0x0100 /* Disable BRU accepting ALU ops */ - mtcr t1, t0 -#endif -.endm - -/* - * This is the code that will be copied to the reset entry point for - * XLR and XLP. The XLP cores start here when they are woken up. This - * is also the NMI entry point. - */ -.macro xlp_flush_l1_dcache - li t0, LSU_DEBUG_DATA0 - li t1, LSU_DEBUG_ADDR - li t2, 0 /* index */ - li t3, 0x1000 /* loop count */ -1: - sll v0, t2, 5 - mtcr zero, t0 - ori v1, v0, 0x3 /* way0 | write_enable | write_active */ - mtcr v1, t1 -2: - mfcr v1, t1 - andi v1, 0x1 /* wait for write_active == 0 */ - bnez v1, 2b - nop - mtcr zero, t0 - ori v1, v0, 0x7 /* way1 | write_enable | write_active */ - mtcr v1, t1 -3: - mfcr v1, t1 - andi v1, 0x1 /* wait for write_active == 0 */ - bnez v1, 3b - nop - addi t2, 1 - bne t3, t2, 1b - nop -.endm - -/* - * The cores can come start when they are woken up. This is also the NMI - * entry, so check that first. - * - * The data corresponding to reset/NMI is stored at RESET_DATA_PHYS - * location, this will have the thread mask (used when core is woken up) - * and the current NMI handler in case we reached here for an NMI. - * - * When a core or thread is newly woken up, it loops in a 'wait'. When - * the CPU really needs waking up, we send an NMI to it, with the NMI - * handler set to prom_boot_secondary_cpus - */ .set noreorder .set noat - .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */ - -FEXPORT(nlm_reset_entry) - dmtc0 k0, $22, 6 - dmtc0 k1, $22, 7 - mfc0 k0, CP0_STATUS - li k1, 0x80000 - and k1, k0, k1 - beqz k1, 1f /* go to real reset entry */ - nop - li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */ - ld k0, BOOT_NMI_HANDLER(k1) - jr k0 - nop - -1: /* Entry point on core wakeup */ - mfc0 t0, CP0_EBASE, 1 - mfc0 t1, CP0_EBASE, 1 - srl t1, 5 - andi t1, 0x3 /* t1 <- node */ - li t2, 0x40000 - mul t3, t2, t1 /* t3 = node * 0x40000 */ - srl t0, t0, 2 - and t0, t0, 0x7 /* t0 <- core */ - li t1, 0x1 - sll t0, t1, t0 - nor t0, t0, zero /* t0 <- ~(1 << core) */ - li t2, SYS_CPU_COHERENT_BASE(0) - add t2, t2, t3 /* t2 <- SYS offset for node */ - lw t1, 0(t2) - and t1, t1, t0 - sw t1, 0(t2) - - /* read back to ensure complete */ - lw t1, 0(t2) - sync - - /* Configure LSU on Non-0 Cores. */ - xlp_config_lsu - /* FALL THROUGH */ - -/* - * Wake up sibling threads from the initial thread in - * a core. - */ -EXPORT(nlm_boot_siblings) - /* core L1D flush before enable threads */ - xlp_flush_l1_dcache - /* Enable hw threads by writing to MAP_THREADMODE of the core */ - li t0, CKSEG1ADDR(RESET_DATA_PHYS) - lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */ - li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE) - mfcr t2, t0 - or t2, t2, t1 - mtcr t2, t0 - - /* - * The new hardware thread starts at the next instruction - * For all the cases other than core 0 thread 0, we will - * jump to the secondary wait function. - */ - mfc0 v0, CP0_EBASE, 1 - andi v0, 0x3ff /* v0 <- node/core */ - - /* Init MMU in the first thread after changing THREAD_MODE - * register (Ax Errata?) - */ - andi v1, v0, 0x3 /* v1 <- thread id */ - bnez v1, 2f - nop - - li t0, MMU_SETUP - li t1, 0 - mtcr t1, t0 - _ehb - -2: beqz v0, 4f /* boot cpu (cpuid == 0)? */ - nop - - /* setup status reg */ - move t1, zero -#ifdef CONFIG_64BIT - ori t1, ST0_KX -#endif - mtc0 t1, CP0_STATUS - /* mark CPU ready */ - PTR_LA t1, nlm_cpu_ready - sll v1, v0, 2 - PTR_ADDU t1, v1 - li t2, 1 - sw t2, 0(t1) - /* Wait until NMI hits */ -3: wait - j 3b - nop - - /* - * For the boot CPU, we have to restore registers and - * return - */ -4: dmfc0 t0, $4, 2 /* restore SP from UserLocal */ - li t1, 0xfadebeef - dmtc0 t1, $4, 2 /* restore SP from UserLocal */ - PTR_SUBU sp, t0, PT_SIZE - RESTORE_ALL - jr ra - nop -EXPORT(nlm_reset_entry_end) + .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */ FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */ - xlp_config_lsu dmtc0 sp, $4, 2 /* SP saved in UserLocal */ SAVE_ALL sync diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c index abb3e08..1a7d529 100644 --- a/arch/mips/netlogic/xlp/wakeup.c +++ b/arch/mips/netlogic/xlp/wakeup.c @@ -137,6 +137,7 @@ void xlp_wakeup_secondary_cpus() * In case of u-boot, the secondaries are in reset * first wakeup core 0 threads */ + nlm_init_boot_cpu(); xlp_boot_core0_siblings(); /* now get other cores out of reset */ -- cgit v0.10.2 From 571886b2a52395f030d439c6259663a033e11e6a Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:41:02 +0000 Subject: MIPS: Netlogic: Initialization when !CONFIG_SMP The core initialization and reset vector setup needs to be done even when booting uniprocessor. Move this code from smp.c to setup.c Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5428/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/netlogic/common/Makefile b/arch/mips/netlogic/common/Makefile index a396a39..362739d 100644 --- a/arch/mips/netlogic/common/Makefile +++ b/arch/mips/netlogic/common/Makefile @@ -1,4 +1,5 @@ obj-y += irq.o time.o obj-y += nlm-dma.o -obj-$(CONFIG_SMP) += smp.o smpboot.o reset.o +obj-y += reset.o +obj-$(CONFIG_SMP) += smp.o smpboot.o obj-$(CONFIG_EARLY_PRINTK) += earlycons.o diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c index ffba524..da3d3bc 100644 --- a/arch/mips/netlogic/common/smp.c +++ b/arch/mips/netlogic/common/smp.c @@ -254,15 +254,9 @@ unsupp: int __cpuinit nlm_wakeup_secondary_cpus(void) { - unsigned long reset_vec; char *reset_data; int threadmode; - /* Update reset entry point with CPU init code */ - reset_vec = CKSEG1ADDR(RESET_VEC_PHYS); - memcpy((void *)reset_vec, (void *)nlm_reset_entry, - (nlm_reset_entry_end - nlm_reset_entry)); - /* verify the mask and setup core config variables */ threadmode = nlm_parse_cpumask(&nlm_cpumask); diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c index 7b66949..5bdd354 100644 --- a/arch/mips/netlogic/xlp/setup.c +++ b/arch/mips/netlogic/xlp/setup.c @@ -98,11 +98,19 @@ void nlm_percpu_init(int hwcpuid) void __init prom_init(void) { + void *reset_vec; + nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE); + nlm_init_boot_cpu(); xlp_mmu_init(); nlm_node_init(0); xlp_dt_init((void *)(long)fw_arg0); + /* Update reset entry point with CPU init code */ + reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); + memcpy(reset_vec, (void *)nlm_reset_entry, + (nlm_reset_entry_end - nlm_reset_entry)); + #ifdef CONFIG_SMP cpumask_setall(&nlm_cpumask); nlm_wakeup_secondary_cpus(); diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c index 1a7d529..abb3e08 100644 --- a/arch/mips/netlogic/xlp/wakeup.c +++ b/arch/mips/netlogic/xlp/wakeup.c @@ -137,7 +137,6 @@ void xlp_wakeup_secondary_cpus() * In case of u-boot, the secondaries are in reset * first wakeup core 0 threads */ - nlm_init_boot_cpu(); xlp_boot_core0_siblings(); /* now get other cores out of reset */ diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c index 89c8c10..7e27f85 100644 --- a/arch/mips/netlogic/xlr/setup.c +++ b/arch/mips/netlogic/xlr/setup.c @@ -196,6 +196,7 @@ void __init prom_init(void) { int *argv, *envp; /* passed as 32 bit ptrs */ struct psb_info *prom_infop; + void *reset_vec; #ifdef CONFIG_SMP int i; #endif @@ -208,6 +209,11 @@ void __init prom_init(void) nlm_prom_info = *prom_infop; nlm_init_node(); + /* Update reset entry point with CPU init code */ + reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); + memcpy(reset_vec, (void *)nlm_reset_entry, + (nlm_reset_entry_end - nlm_reset_entry)); + nlm_early_serial_setup(); build_arcs_cmdline(argv); prom_add_memory(); -- cgit v0.10.2 From 53c832197f3adc5a360336f75fe34a95fe2d796b Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:41:03 +0000 Subject: MIPS: Netlogic: Add nlm_get_boot_data() helper This moves the calculation and casting needed to access the CPU initialization data to a function nlm_get_boot_data() Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5426/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h index d4ede12..1b54adb 100644 --- a/arch/mips/include/asm/netlogic/common.h +++ b/arch/mips/include/asm/netlogic/common.h @@ -59,13 +59,18 @@ int nlm_wakeup_secondary_cpus(void); void nlm_rmiboot_preboot(void); void nlm_percpu_init(int hwcpuid); +static inline void * +nlm_get_boot_data(int offset) +{ + return (void *)(CKSEG1ADDR(RESET_DATA_PHYS) + offset); +} + static inline void nlm_set_nmi_handler(void *handler) { - char *reset_data; + void *nmih = nlm_get_boot_data(BOOT_NMI_HANDLER); - reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS); - *(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler; + *(int64_t *)nmih = (long)handler; } /* diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c index da3d3bc..1f66eef 100644 --- a/arch/mips/netlogic/common/smp.c +++ b/arch/mips/netlogic/common/smp.c @@ -254,15 +254,15 @@ unsupp: int __cpuinit nlm_wakeup_secondary_cpus(void) { - char *reset_data; + u32 *reset_data; int threadmode; /* verify the mask and setup core config variables */ threadmode = nlm_parse_cpumask(&nlm_cpumask); /* Setup CPU init parameters */ - reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS); - *(int *)(reset_data + BOOT_THREAD_MODE) = threadmode; + reset_data = nlm_get_boot_data(BOOT_THREAD_MODE); + *reset_data = threadmode; #ifdef CONFIG_CPU_XLP xlp_wakeup_secondary_cpus(); -- cgit v0.10.2 From 919f9abb3723f088290c62648b12fbfc7600d923 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:41:04 +0000 Subject: MIPS: Netlogic: move cpu_ready array to boot area Move the nlm_cpu_ready[] array used by the cpu wakeup code to the boot area, along with rest of the boot parameter code. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5425/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h index 1b54adb..bb68c33 100644 --- a/arch/mips/include/asm/netlogic/common.h +++ b/arch/mips/include/asm/netlogic/common.h @@ -39,11 +39,17 @@ * Common SMP definitions */ #define RESET_VEC_PHYS 0x1fc00000 +#define RESET_VEC_SIZE 8192 /* 8KB reset code and data */ #define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10)) + +/* Offsets of parameters in the RESET_DATA_PHYS area */ #define BOOT_THREAD_MODE 0 #define BOOT_NMI_LOCK 4 #define BOOT_NMI_HANDLER 8 +/* CPU ready flags for each CPU */ +#define BOOT_CPU_READY 2048 + #ifndef __ASSEMBLY__ #include #include diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S index 98691d6..b11691c 100644 --- a/arch/mips/netlogic/common/reset.S +++ b/arch/mips/netlogic/common/reset.S @@ -216,8 +216,10 @@ EXPORT(nlm_boot_siblings) ori t1, ST0_KX #endif mtc0 t1, CP0_STATUS - /* mark CPU ready */ - PTR_LA t1, nlm_cpu_ready + + /* mark CPU ready, careful here, previous mtcr trashed registers */ + li t3, CKSEG1ADDR(RESET_DATA_PHYS) + ADDIU t1, t3, BOOT_CPU_READY sll v1, v0, 2 PTR_ADDU t1, v1 li t2, 1 diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c index 1f66eef..885d293 100644 --- a/arch/mips/netlogic/common/smp.c +++ b/arch/mips/netlogic/common/smp.c @@ -145,7 +145,6 @@ void nlm_cpus_done(void) * Boot all other cpus in the system, initialize them, and bring them into * the boot function */ -int nlm_cpu_ready[NR_CPUS]; unsigned long nlm_next_gp; unsigned long nlm_next_sp; static cpumask_t phys_cpu_present_mask; @@ -168,6 +167,7 @@ void __init nlm_smp_setup(void) { unsigned int boot_cpu; int num_cpus, i, ncore; + volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); char buf[64]; boot_cpu = hard_smp_processor_id(); @@ -181,10 +181,10 @@ void __init nlm_smp_setup(void) num_cpus = 1; for (i = 0; i < NR_CPUS; i++) { /* - * nlm_cpu_ready array is not set for the boot_cpu, + * cpu_ready array is not set for the boot_cpu, * it is only set for ASPs (see smpboot.S) */ - if (nlm_cpu_ready[i]) { + if (cpu_ready[i]) { cpumask_set_cpu(i, &phys_cpu_present_mask); __cpu_number_map[i] = num_cpus; __cpu_logical_map[num_cpus] = i; diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S index 7c7e884..6029d1b 100644 --- a/arch/mips/netlogic/common/smpboot.S +++ b/arch/mips/netlogic/common/smpboot.S @@ -109,8 +109,9 @@ NESTED(nlm_rmiboot_preboot, 16, sp) andi t2, t0, 0x3 /* thread num */ sll t0, 2 /* offset in cpu array */ - PTR_LA t1, nlm_cpu_ready /* mark CPU ready */ - PTR_ADDU t1, t0 + li t3, CKSEG1ADDR(RESET_DATA_PHYS) + ADDIU t1, t3, BOOT_CPU_READY + ADDU t1, t0 li t3, 1 sw t3, 0(t1) diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c index 5bdd354..8f69924 100644 --- a/arch/mips/netlogic/xlp/setup.c +++ b/arch/mips/netlogic/xlp/setup.c @@ -108,6 +108,7 @@ void __init prom_init(void) /* Update reset entry point with CPU init code */ reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); + memset(reset_vec, 0, RESET_VEC_SIZE); memcpy(reset_vec, (void *)nlm_reset_entry, (nlm_reset_entry_end - nlm_reset_entry)); diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c index abb3e08..feb5736 100644 --- a/arch/mips/netlogic/xlp/wakeup.c +++ b/arch/mips/netlogic/xlp/wakeup.c @@ -82,6 +82,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) struct nlm_soc_info *nodep; uint64_t syspcibase; uint32_t syscoremask; + volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); int core, n, cpu, count, val; for (n = 0; n < NLM_NR_NODES; n++) { @@ -125,7 +126,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) /* spin until the first hw thread sets its ready */ count = 0x20000000; do { - val = *(volatile int *)&nlm_cpu_ready[cpu]; + val = cpu_ready[cpu]; } while (val == 0 && --count > 0); } } diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c index 7e27f85..214d123 100644 --- a/arch/mips/netlogic/xlr/setup.c +++ b/arch/mips/netlogic/xlr/setup.c @@ -211,6 +211,7 @@ void __init prom_init(void) /* Update reset entry point with CPU init code */ reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); + memset(reset_vec, 0, RESET_VEC_SIZE); memcpy(reset_vec, (void *)nlm_reset_entry, (nlm_reset_entry_end - nlm_reset_entry)); diff --git a/arch/mips/netlogic/xlr/wakeup.c b/arch/mips/netlogic/xlr/wakeup.c index 3ebf741..c06e4c9 100644 --- a/arch/mips/netlogic/xlr/wakeup.c +++ b/arch/mips/netlogic/xlr/wakeup.c @@ -53,6 +53,7 @@ int __cpuinit xlr_wakeup_secondary_cpus(void) { struct nlm_soc_info *nodep; unsigned int i, j, boot_cpu; + volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); /* * In case of RMI boot, hit with NMI to get the cores @@ -71,7 +72,7 @@ int __cpuinit xlr_wakeup_secondary_cpus(void) nodep->coremask = 1; for (i = 1; i < NLM_CORES_PER_NODE; i++) { for (j = 1000000; j > 0; j--) { - if (nlm_cpu_ready[i * NLM_THREADS_PER_CORE]) + if (cpu_ready[i * NLM_THREADS_PER_CORE]) break; udelay(10); } -- cgit v0.10.2 From fd5f527cc58f7112f0d2c3cf2c29ae3ea5417de5 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:41:05 +0000 Subject: MIPS: Netlogic: use branch instead of jump Fix an issue in the reset code. Since this code is copied to the reset vector, using 'j' for looping is not correct. Use relative branch 'b'. Update the usage of 'j' in smpboot.S to be consistent although it is not a bug there. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5427/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S index b11691c..0ebd50a 100644 --- a/arch/mips/netlogic/common/reset.S +++ b/arch/mips/netlogic/common/reset.S @@ -226,7 +226,7 @@ EXPORT(nlm_boot_siblings) sw t2, 0(t1) /* Wait until NMI hits */ 3: wait - j 3b + b 3b nop /* diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S index 6029d1b..528c46c 100644 --- a/arch/mips/netlogic/common/smpboot.S +++ b/arch/mips/netlogic/common/smpboot.S @@ -137,7 +137,7 @@ NESTED(nlm_rmiboot_preboot, 16, sp) mtcr t1, t0 /* update core control */ 1: wait - j 1b + b 1b nop END(nlm_rmiboot_preboot) __FINIT -- cgit v0.10.2 From 9f1f1e7b8b76d8503673a3777b3ee743d8c50e13 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:41:06 +0000 Subject: MIPS: Netlogic: Fix sign extension in PIC write This does not cause a problem yet, but we do not want to write 1 to reserved bits. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5424/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h index a981f46..4b5108d 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h @@ -315,7 +315,7 @@ nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) { uint64_t ipi; - ipi = (nmi << 31) | (irq << 20); + ipi = ((uint64_t)nmi << 31) | (irq << 20); ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */ nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); } -- cgit v0.10.2 From 4033d38ceb9d84ed66b925c1740c1a88f8a4a8f9 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:41:07 +0000 Subject: MIPS: Netlogic: wait for all hardware threads Earlier we just waited for the first thread of the CPU to come online before proceeding to wake up others. Update it to wait for all the CPUs in the core. This will be useful when the boot-up is slow, like while debugging or when running in a simulator. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5429/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c index feb5736..0cce37c 100644 --- a/arch/mips/netlogic/xlp/wakeup.c +++ b/arch/mips/netlogic/xlp/wakeup.c @@ -77,13 +77,28 @@ static int xlp_wakeup_core(uint64_t sysbase, int node, int core) return count != 0; } +static int wait_for_cpus(int cpu, int bootcpu) +{ + volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); + int i, count, notready; + + count = 0x20000000; + do { + notready = nlm_threads_per_core; + for (i = 0; i < nlm_threads_per_core; i++) + if (cpu_ready[cpu + i] || cpu == bootcpu) + --notready; + } while (notready != 0 && --count > 0); + + return count != 0; +} + static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) { struct nlm_soc_info *nodep; uint64_t syspcibase; uint32_t syscoremask; - volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); - int core, n, cpu, count, val; + int core, n, cpu; for (n = 0; n < NLM_NR_NODES; n++) { syspcibase = nlm_get_sys_pcibase(n); @@ -123,11 +138,8 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) /* core is up */ nodep->coremask |= 1u << core; - /* spin until the first hw thread sets its ready */ - count = 0x20000000; - do { - val = cpu_ready[cpu]; - } while (val == 0 && --count > 0); + /* spin until the hw threads sets their ready */ + wait_for_cpus(cpu, 0); } } } @@ -139,6 +151,7 @@ void xlp_wakeup_secondary_cpus() * first wakeup core 0 threads */ xlp_boot_core0_siblings(); + wait_for_cpus(0, 0); /* now get other cores out of reset */ xlp_enable_secondary_cores(&nlm_cpumask); -- cgit v0.10.2 From 722138340b9f08d081255ba50928831a972c2e6f Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:41:08 +0000 Subject: MIPS: Netlogic: Fixup memory regions for prefetch Fix a cache error found in stress test, caused by the prefetch instruction going beyond valid memory when acessing the last page of a region. Add the pref_backup logic similar to XLR in XLP too. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5431/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c index 8f69924..7b638f7 100644 --- a/arch/mips/netlogic/xlp/setup.c +++ b/arch/mips/netlogic/xlp/setup.c @@ -61,6 +61,18 @@ static void nlm_linux_exit(void) cpu_wait(); } +static void nlm_fixup_mem(void) +{ + const int pref_backup = 512; + int i; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + if (boot_mem_map.map[i].type != BOOT_MEM_RAM) + continue; + boot_mem_map.map[i].size -= pref_backup; + } +} + void __init plat_mem_setup(void) { panic_timeout = 5; @@ -70,6 +82,7 @@ void __init plat_mem_setup(void) /* memory and bootargs from DT */ early_init_devtree(initial_boot_params); + nlm_fixup_mem(); } const char *get_system_type(void) -- cgit v0.10.2 From 6099115e7e5e2c49d3822e093ca7df7015ca57a9 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:41:09 +0000 Subject: MIPS: Netlogic: Remove workarounds for early SoCs The XLPs in production do not need these workarounds. Remove the code and the associated ifdef. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5430/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S index 0ebd50a..adb1828 100644 --- a/arch/mips/netlogic/common/reset.S +++ b/arch/mips/netlogic/common/reset.S @@ -54,8 +54,6 @@ XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ SYS_CPU_NONCOHERENT_MODE * 4 -#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */ - /* Enable XLP features and workarounds in the LSU */ .macro xlp_config_lsu li t0, LSU_DEFEATURE @@ -63,10 +61,6 @@ lui t2, 0xc080 /* SUE, Enable Unaligned Access, L2HPE */ or t1, t1, t2 -#ifdef XLP_AX_WORKAROUND - li t2, ~0xe /* S1RCM */ - and t1, t1, t2 -#endif mtcr t1, t0 li t0, ICU_DEFEATURE @@ -74,12 +68,9 @@ ori t1, 0x1000 /* Enable Icache partitioning */ mtcr t1, t0 - -#ifdef XLP_AX_WORKAROUND li t0, SCHED_DEFEATURE lui t1, 0x0100 /* Disable BRU accepting ALU ops */ mtcr t1, t0 -#endif .endm /* @@ -195,19 +186,7 @@ EXPORT(nlm_boot_siblings) mfc0 v0, CP0_EBASE, 1 andi v0, 0x3ff /* v0 <- node/core */ - /* Init MMU in the first thread after changing THREAD_MODE - * register (Ax Errata?) - */ - andi v1, v0, 0x3 /* v1 <- thread id */ - bnez v1, 2f - nop - - li t0, MMU_SETUP - li t1, 0 - mtcr t1, t0 - _ehb - -2: beqz v0, 4f /* boot cpu (cpuid == 0)? */ + beqz v0, 4f /* boot cpu (cpuid == 0)? */ nop /* setup status reg */ -- cgit v0.10.2 From 8ecd08378c132536c7d47af225e09bd6f3a16779 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:41:10 +0000 Subject: MIPS: Netlogic: Fix plat_irq_dispatch Fix an issue in plat_irq_dispatch due to which it can call do_IRQ with a PIC irq that is not mapped. When a per-cpu interrupt and a PIC interrupt are both active, the check 'eirr & PERCPU_IRQ_MASK' will be true, but the interrupt in 'i' will be the number of the PIC interrupt. In this case, we will call do_IRQ on the PIC interrupt without mapping it with nlm_irq_to_xirq(). Fix this by using __ffs64 instead of __ilog2_u64 and using the interrupt number instead of mask to identify per-cpu interrupts. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5432/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c index 9f84c60..73facb2 100644 --- a/arch/mips/netlogic/common/irq.c +++ b/arch/mips/netlogic/common/irq.c @@ -253,13 +253,12 @@ asmlinkage void plat_irq_dispatch(void) node = nlm_nodeid(); eirr = read_c0_eirr_and_eimr(); - - i = __ilog2_u64(eirr); - if (i == -1) + if (eirr == 0) return; + i = __ffs64(eirr); /* per-CPU IRQs don't need translation */ - if (eirr & PERCPU_IRQ_MASK) { + if (i < PIC_IRQ_BASE) { do_IRQ(i); return; } -- cgit v0.10.2 From 7777b9395b77664cb736b941f95fb8f656edd111 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Tue, 11 Jun 2013 14:41:35 +0000 Subject: MIPS: Allow platform specific scratch registers XLR/XLP COP0 scratch is register 22, sel 0-7. Add a function c0_kscratch() which returns the scratch register for the platform, and use the return value while generating TLB handlers. Setup kscratch_mask to 0xf for XLR/XLP since the config4 register does not exist. This allows the kernel to allocate scratch registers 0-3 if needed. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5445/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index c6568bf..265c97d 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -959,6 +959,7 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) set_isa(c, MIPS_CPU_ISA_M64R1); c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; } + c->kscratch_mask = 0xf; } #ifdef CONFIG_64BIT diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index afeef93..c052df8 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -305,6 +305,17 @@ static int check_for_high_segbits __cpuinitdata; static unsigned int kscratch_used_mask __cpuinitdata; +static inline int __maybe_unused c0_kscratch(void) +{ + switch (current_cpu_type()) { + case CPU_XLP: + case CPU_XLR: + return 22; + default: + return 31; + } +} + static int __cpuinit allocate_kscratch(void) { int r; @@ -336,7 +347,7 @@ static struct work_registers __cpuinit build_get_work_registers(u32 **p) if (scratch_reg > 0) { /* Save in CPU local C0_KScratch? */ - UASM_i_MTC0(p, 1, 31, scratch_reg); + UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); r.r1 = K0; r.r2 = K1; r.r3 = 1; @@ -385,7 +396,7 @@ static struct work_registers __cpuinit build_get_work_registers(u32 **p) static void __cpuinit build_restore_work_registers(u32 **p) { if (scratch_reg > 0) { - UASM_i_MFC0(p, 1, 31, scratch_reg); + UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); return; } /* K0 already points to save area, restore $1 and $2 */ @@ -674,7 +685,7 @@ static __cpuinit void build_restore_pagemask(u32 **p, uasm_il_b(p, r, lid); } if (scratch_reg > 0) - UASM_i_MFC0(p, 1, 31, scratch_reg); + UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); else UASM_i_LW(p, 1, scratchpad_offset(0), 0); } else { @@ -817,7 +828,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, #ifdef CONFIG_MIPS_PGD_C0_CONTEXT if (pgd_reg != -1) { /* pgd is in pgd_reg */ - UASM_i_MFC0(p, ptr, 31, pgd_reg); + UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); } else { /* * &pgd << 11 stored in CONTEXT [23..63]. @@ -930,7 +941,7 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, if (mode == refill_scratch) { if (scratch_reg > 0) - UASM_i_MFC0(p, 1, 31, scratch_reg); + UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); else UASM_i_LW(p, 1, scratchpad_offset(0), 0); } else { @@ -1096,7 +1107,7 @@ struct mips_huge_tlb_info { static struct mips_huge_tlb_info __cpuinit build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, struct uasm_reloc **r, unsigned int tmp, - unsigned int ptr, int c0_scratch) + unsigned int ptr, int c0_scratch_reg) { struct mips_huge_tlb_info rv; unsigned int even, odd; @@ -1110,12 +1121,12 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, UASM_i_MFC0(p, tmp, C0_BADVADDR); if (pgd_reg != -1) - UASM_i_MFC0(p, ptr, 31, pgd_reg); + UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); else UASM_i_MFC0(p, ptr, C0_CONTEXT); - if (c0_scratch >= 0) - UASM_i_MTC0(p, scratch, 31, c0_scratch); + if (c0_scratch_reg >= 0) + UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); else UASM_i_SW(p, scratch, scratchpad_offset(0), 0); @@ -1130,14 +1141,14 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, } } else { if (pgd_reg != -1) - UASM_i_MFC0(p, ptr, 31, pgd_reg); + UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); else UASM_i_MFC0(p, ptr, C0_CONTEXT); UASM_i_MFC0(p, tmp, C0_BADVADDR); - if (c0_scratch >= 0) - UASM_i_MTC0(p, scratch, 31, c0_scratch); + if (c0_scratch_reg >= 0) + UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); else UASM_i_SW(p, scratch, scratchpad_offset(0), 0); @@ -1242,8 +1253,8 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, } UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ - if (c0_scratch >= 0) { - UASM_i_MFC0(p, scratch, 31, c0_scratch); + if (c0_scratch_reg >= 0) { + UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); build_tlb_write_entry(p, l, r, tlb_random); uasm_l_leave(l, *p); rv.restore_scratch = 1; @@ -1490,7 +1501,7 @@ static void __cpuinit build_r4000_setup_pgd(void) } else { /* PGD in c0_KScratch */ uasm_i_jr(&p, 31); - UASM_i_MTC0(&p, a0, 31, pgd_reg); + UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); } if (p - tlbmiss_handler_setup_pgd_array > ARRAY_SIZE(tlbmiss_handler_setup_pgd_array)) panic("tlbmiss_handler_setup_pgd_array space exceeded"); -- cgit v0.10.2 From 0e6ecc1a9aa7cbf991d9711a12cae2b4853ef718 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Tue, 11 Jun 2013 14:41:36 +0000 Subject: MIPS: Fixup check for invalid scratch register The invalid value for scratch register is -1, so update the checks of the form (scratch_reg > 0) to be (scratch_reg >= 0). This will fix the case in Netlogic XLP where the scratch_reg can be 0. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5444/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index c052df8..9b988c0 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -345,7 +345,7 @@ static struct work_registers __cpuinit build_get_work_registers(u32 **p) int smp_processor_id_sel; int smp_processor_id_shift; - if (scratch_reg > 0) { + if (scratch_reg >= 0) { /* Save in CPU local C0_KScratch? */ UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); r.r1 = K0; @@ -395,7 +395,7 @@ static struct work_registers __cpuinit build_get_work_registers(u32 **p) static void __cpuinit build_restore_work_registers(u32 **p) { - if (scratch_reg > 0) { + if (scratch_reg >= 0) { UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); return; } @@ -684,7 +684,7 @@ static __cpuinit void build_restore_pagemask(u32 **p, uasm_i_mtc0(p, 0, C0_PAGEMASK); uasm_il_b(p, r, lid); } - if (scratch_reg > 0) + if (scratch_reg >= 0) UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); else UASM_i_LW(p, 1, scratchpad_offset(0), 0); @@ -940,7 +940,7 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, uasm_i_jr(p, ptr); if (mode == refill_scratch) { - if (scratch_reg > 0) + if (scratch_reg >= 0) UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); else UASM_i_LW(p, 1, scratchpad_offset(0), 0); @@ -1297,7 +1297,7 @@ static void __cpuinit build_r4000_tlb_refill_handler(void) memset(relocs, 0, sizeof(relocs)); memset(final_handler, 0, sizeof(final_handler)); - if ((scratch_reg > 0 || scratchpad_available()) && use_bbit_insns()) { + if ((scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, scratch_reg); vmalloc_mode = refill_scratch; -- cgit v0.10.2 From 9601cd159565fa228edc8e5ea3ed2c0ac3fb4d1f Mon Sep 17 00:00:00 2001 From: Paul Bolle Date: Thu, 30 May 2013 09:20:15 +0000 Subject: MIPS: DEC: remove unbuildable promcon.c promcon.o is built if CONFIG_PROM_CONSOLE is set. But there's no Kconfig symbol PROM_CONSOLE, so promcon.c is unbuildable. Remove it. Signed-off-by: Paul Bolle Acked-by: Maciej W. Rozycki Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5344/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/dec/Makefile b/arch/mips/dec/Makefile index 9eb2f9c..3d5d2c5 100644 --- a/arch/mips/dec/Makefile +++ b/arch/mips/dec/Makefile @@ -5,6 +5,5 @@ obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \ kn02-irq.o kn02xa-berr.o reset.o setup.o time.o -obj-$(CONFIG_PROM_CONSOLE) += promcon.o obj-$(CONFIG_TC) += tc.o obj-$(CONFIG_CPU_HAS_WB) += wbflush.o diff --git a/arch/mips/dec/promcon.c b/arch/mips/dec/promcon.c deleted file mode 100644 index c239c25..0000000 --- a/arch/mips/dec/promcon.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Wrap-around code for a console using the - * DECstation PROM io-routines. - * - * Copyright (c) 1998 Harald Koerfgen - */ - -#include -#include -#include -#include -#include - -#include - -static void prom_console_write(struct console *co, const char *s, - unsigned count) -{ - unsigned i; - - /* - * Now, do each character - */ - for (i = 0; i < count; i++) { - if (*s == 10) - prom_printf("%c", 13); - prom_printf("%c", *s++); - } -} - -static int __init prom_console_setup(struct console *co, char *options) -{ - return 0; -} - -static struct console sercons = { - .name = "ttyS", - .write = prom_console_write, - .setup = prom_console_setup, - .flags = CON_PRINTBUFFER, - .index = -1, -}; - -/* - * Register console. - */ - -static int __init prom_console_init(void) -{ - register_console(&sercons); - - return 0; -} -console_initcall(prom_console_init); -- cgit v0.10.2 From b8061134f83a36b9eb6e38a184f3982f8d8bc58c Mon Sep 17 00:00:00 2001 From: Paul Bolle Date: Thu, 30 May 2013 09:51:21 +0000 Subject: MIPS: MSP71xx: Remove gpio drivers The PMC MSP71XX gpio drivers were added in v2.6.28, see commit 9fa32c6b02 ("MIPS: PMC MSP71XX gpio drivers"). They are only built if CONFIG_HAVE_GPIO_LIB is set. But the Kconfig symbol HAVE_GPIO_LIB was already removed in v2.6.27, see commit 7444a72eff ("gpiolib: allow user-selection"). So these drivers were never buildable. Perhaps no-one noticed because there are no in tree users of msp71xx_init_gpio() and msp71xx_init_gpio_extended(). Anyhow, these drivers can safely be removed. Signed-off-by: Paul Bolle Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5345/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h b/arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h deleted file mode 100644 index ebdbab9..0000000 --- a/arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * include/asm-mips/pmc-sierra/msp71xx/gpio.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * @author Patrick Glass - */ - -#ifndef __PMC_MSP71XX_GPIO_H -#define __PMC_MSP71XX_GPIO_H - -/* Max number of gpio's is 28 on chip plus 3 banks of I2C IO Expanders */ -#define ARCH_NR_GPIOS (28 + (3 * 8)) - -/* new generic GPIO API - see Documentation/gpio.txt */ -#include - -#define gpio_get_value __gpio_get_value -#define gpio_set_value __gpio_set_value -#define gpio_cansleep __gpio_cansleep - -/* Setup calls for the gpio and gpio extended */ -extern void msp71xx_init_gpio(void); -extern void msp71xx_init_gpio_extended(void); -extern int msp71xx_set_output_drive(unsigned gpio, int value); - -/* Custom output drive functionss */ -static inline int gpio_set_output_drive(unsigned gpio, int value) -{ - return msp71xx_set_output_drive(gpio, value); -} - -/* IRQ's are not supported for gpio lines */ -static inline int gpio_to_irq(unsigned gpio) -{ - return -EINVAL; -} - -static inline int irq_to_gpio(unsigned irq) -{ - return -EINVAL; -} - -#endif /* __PMC_MSP71XX_GPIO_H */ diff --git a/arch/mips/pmcs-msp71xx/Makefile b/arch/mips/pmcs-msp71xx/Makefile index cefba77..9201c8b 100644 --- a/arch/mips/pmcs-msp71xx/Makefile +++ b/arch/mips/pmcs-msp71xx/Makefile @@ -3,7 +3,6 @@ # obj-y += msp_prom.o msp_setup.o msp_irq.o \ msp_time.o msp_serial.o msp_elb.o -obj-$(CONFIG_HAVE_GPIO_LIB) += gpio.o gpio_extended.o obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o msp_irq_per.o diff --git a/arch/mips/pmcs-msp71xx/gpio.c b/arch/mips/pmcs-msp71xx/gpio.c deleted file mode 100644 index aaccbe5..0000000 --- a/arch/mips/pmcs-msp71xx/gpio.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Generic PMC MSP71xx GPIO handling. These base gpio are controlled by two - * types of registers. The data register sets the output level when in output - * mode and when in input mode will contain the value at the input. The config - * register sets the various modes for each gpio. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * @author Patrick Glass - */ - -#include -#include -#include -#include -#include -#include - -#define MSP71XX_CFG_OFFSET(gpio) (4 * (gpio)) -#define CONF_MASK 0x0F -#define MSP71XX_GPIO_INPUT 0x01 -#define MSP71XX_GPIO_OUTPUT 0x08 - -#define MSP71XX_GPIO_BASE 0x0B8400000L - -#define to_msp71xx_gpio_chip(c) container_of(c, struct msp71xx_gpio_chip, chip) - -static spinlock_t gpio_lock; - -/* - * struct msp71xx_gpio_chip - container for gpio chip and registers - * @chip: chip structure for the specified gpio bank - * @data_reg: register for reading and writing the gpio pin value - * @config_reg: register to set the mode for the gpio pin bank - * @out_drive_reg: register to set the output drive mode for the gpio pin bank - */ -struct msp71xx_gpio_chip { - struct gpio_chip chip; - void __iomem *data_reg; - void __iomem *config_reg; - void __iomem *out_drive_reg; -}; - -/* - * msp71xx_gpio_get() - return the chip's gpio value - * @chip: chip structure which controls the specified gpio - * @offset: gpio whose value will be returned - * - * It will return 0 if gpio value is low and other if high. - */ -static int msp71xx_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip); - - return __raw_readl(msp_chip->data_reg) & (1 << offset); -} - -/* - * msp71xx_gpio_set() - set the output value for the gpio - * @chip: chip structure who controls the specified gpio - * @offset: gpio whose value will be assigned - * @value: logic level to assign to the gpio initially - * - * This will set the gpio bit specified to the desired value. It will set the - * gpio pin low if value is 0 otherwise it will be high. - */ -static void msp71xx_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -{ - struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip); - unsigned long flags; - u32 data; - - spin_lock_irqsave(&gpio_lock, flags); - - data = __raw_readl(msp_chip->data_reg); - if (value) - data |= (1 << offset); - else - data &= ~(1 << offset); - __raw_writel(data, msp_chip->data_reg); - - spin_unlock_irqrestore(&gpio_lock, flags); -} - -/* - * msp71xx_set_gpio_mode() - declare the mode for a gpio - * @chip: chip structure which controls the specified gpio - * @offset: gpio whose value will be assigned - * @mode: desired configuration for the gpio (see datasheet) - * - * It will set the gpio pin config to the @mode value passed in. - */ -static int msp71xx_set_gpio_mode(struct gpio_chip *chip, - unsigned offset, int mode) -{ - struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip); - const unsigned bit_offset = MSP71XX_CFG_OFFSET(offset); - unsigned long flags; - u32 cfg; - - spin_lock_irqsave(&gpio_lock, flags); - - cfg = __raw_readl(msp_chip->config_reg); - cfg &= ~(CONF_MASK << bit_offset); - cfg |= (mode << bit_offset); - __raw_writel(cfg, msp_chip->config_reg); - - spin_unlock_irqrestore(&gpio_lock, flags); - - return 0; -} - -/* - * msp71xx_direction_output() - declare the direction mode for a gpio - * @chip: chip structure which controls the specified gpio - * @offset: gpio whose value will be assigned - * @value: logic level to assign to the gpio initially - * - * This call will set the mode for the @gpio to output. It will set the - * gpio pin low if value is 0 otherwise it will be high. - */ -static int msp71xx_direction_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - msp71xx_gpio_set(chip, offset, value); - - return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_OUTPUT); -} - -/* - * msp71xx_direction_input() - declare the direction mode for a gpio - * @chip: chip structure which controls the specified gpio - * @offset: gpio whose to which the value will be assigned - * - * This call will set the mode for the @gpio to input. - */ -static int msp71xx_direction_input(struct gpio_chip *chip, unsigned offset) -{ - return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_INPUT); -} - -/* - * msp71xx_set_output_drive() - declare the output drive for the gpio line - * @gpio: gpio pin whose output drive you wish to modify - * @value: zero for active drain 1 for open drain drive - * - * This call will set the output drive mode for the @gpio to output. - */ -int msp71xx_set_output_drive(unsigned gpio, int value) -{ - unsigned long flags; - u32 data; - - if (gpio > 15 || gpio < 0) - return -EINVAL; - - spin_lock_irqsave(&gpio_lock, flags); - - data = __raw_readl((void __iomem *)(MSP71XX_GPIO_BASE + 0x190)); - if (value) - data |= (1 << gpio); - else - data &= ~(1 << gpio); - __raw_writel(data, (void __iomem *)(MSP71XX_GPIO_BASE + 0x190)); - - spin_unlock_irqrestore(&gpio_lock, flags); - - return 0; -} -EXPORT_SYMBOL(msp71xx_set_output_drive); - -#define MSP71XX_GPIO_BANK(name, dr, cr, base_gpio, num_gpio) \ -{ \ - .chip = { \ - .label = name, \ - .direction_input = msp71xx_direction_input, \ - .direction_output = msp71xx_direction_output, \ - .get = msp71xx_gpio_get, \ - .set = msp71xx_gpio_set, \ - .base = base_gpio, \ - .ngpio = num_gpio \ - }, \ - .data_reg = (void __iomem *)(MSP71XX_GPIO_BASE + dr), \ - .config_reg = (void __iomem *)(MSP71XX_GPIO_BASE + cr), \ - .out_drive_reg = (void __iomem *)(MSP71XX_GPIO_BASE + 0x190), \ -} - -/* - * struct msp71xx_gpio_banks[] - container array of gpio banks - * @chip: chip structure for the specified gpio bank - * @data_reg: register for reading and writing the gpio pin value - * @config_reg: register to set the mode for the gpio pin bank - * - * This array structure defines the gpio banks for the PMC MIPS Processor. - * We specify the bank name, the data register, the config register, base - * starting gpio number, and the number of gpios exposed by the bank. - */ -static struct msp71xx_gpio_chip msp71xx_gpio_banks[] = { - - MSP71XX_GPIO_BANK("GPIO_1_0", 0x170, 0x180, 0, 2), - MSP71XX_GPIO_BANK("GPIO_5_2", 0x174, 0x184, 2, 4), - MSP71XX_GPIO_BANK("GPIO_9_6", 0x178, 0x188, 6, 4), - MSP71XX_GPIO_BANK("GPIO_15_10", 0x17C, 0x18C, 10, 6), -}; - -void __init msp71xx_init_gpio(void) -{ - int i; - - spin_lock_init(&gpio_lock); - - for (i = 0; i < ARRAY_SIZE(msp71xx_gpio_banks); i++) - gpiochip_add(&msp71xx_gpio_banks[i].chip); -} diff --git a/arch/mips/pmcs-msp71xx/gpio_extended.c b/arch/mips/pmcs-msp71xx/gpio_extended.c deleted file mode 100644 index 2a99f36..0000000 --- a/arch/mips/pmcs-msp71xx/gpio_extended.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Generic PMC MSP71xx EXTENDED (EXD) GPIO handling. The extended gpio is - * a set of hardware registers that have no need for explicit locking as - * it is handled by unique method of writing individual set/clr bits. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * @author Patrick Glass - */ - -#include -#include -#include -#include -#include - -#define MSP71XX_DATA_OFFSET(gpio) (2 * (gpio)) -#define MSP71XX_READ_OFFSET(gpio) (MSP71XX_DATA_OFFSET(gpio) + 1) -#define MSP71XX_CFG_OUT_OFFSET(gpio) (MSP71XX_DATA_OFFSET(gpio) + 16) -#define MSP71XX_CFG_IN_OFFSET(gpio) (MSP71XX_CFG_OUT_OFFSET(gpio) + 1) - -#define MSP71XX_EXD_GPIO_BASE 0x0BC000000L - -#define to_msp71xx_exd_gpio_chip(c) \ - container_of(c, struct msp71xx_exd_gpio_chip, chip) - -/* - * struct msp71xx_exd_gpio_chip - container for gpio chip and registers - * @chip: chip structure for the specified gpio bank - * @reg: register for control and data of gpio pin - */ -struct msp71xx_exd_gpio_chip { - struct gpio_chip chip; - void __iomem *reg; -}; - -/* - * msp71xx_exd_gpio_get() - return the chip's gpio value - * @chip: chip structure which controls the specified gpio - * @offset: gpio whose value will be returned - * - * It will return 0 if gpio value is low and other if high. - */ -static int msp71xx_exd_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct msp71xx_exd_gpio_chip *msp71xx_chip = - to_msp71xx_exd_gpio_chip(chip); - const unsigned bit = MSP71XX_READ_OFFSET(offset); - - return __raw_readl(msp71xx_chip->reg) & (1 << bit); -} - -/* - * msp71xx_exd_gpio_set() - set the output value for the gpio - * @chip: chip structure who controls the specified gpio - * @offset: gpio whose value will be assigned - * @value: logic level to assign to the gpio initially - * - * This will set the gpio bit specified to the desired value. It will set the - * gpio pin low if value is 0 otherwise it will be high. - */ -static void msp71xx_exd_gpio_set(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct msp71xx_exd_gpio_chip *msp71xx_chip = - to_msp71xx_exd_gpio_chip(chip); - const unsigned bit = MSP71XX_DATA_OFFSET(offset); - - __raw_writel(1 << (bit + (value ? 1 : 0)), msp71xx_chip->reg); -} - -/* - * msp71xx_exd_direction_output() - declare the direction mode for a gpio - * @chip: chip structure which controls the specified gpio - * @offset: gpio whose value will be assigned - * @value: logic level to assign to the gpio initially - * - * This call will set the mode for the @gpio to output. It will set the - * gpio pin low if value is 0 otherwise it will be high. - */ -static int msp71xx_exd_direction_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct msp71xx_exd_gpio_chip *msp71xx_chip = - to_msp71xx_exd_gpio_chip(chip); - - msp71xx_exd_gpio_set(chip, offset, value); - __raw_writel(1 << MSP71XX_CFG_OUT_OFFSET(offset), msp71xx_chip->reg); - return 0; -} - -/* - * msp71xx_exd_direction_input() - declare the direction mode for a gpio - * @chip: chip structure which controls the specified gpio - * @offset: gpio whose to which the value will be assigned - * - * This call will set the mode for the @gpio to input. - */ -static int msp71xx_exd_direction_input(struct gpio_chip *chip, unsigned offset) -{ - struct msp71xx_exd_gpio_chip *msp71xx_chip = - to_msp71xx_exd_gpio_chip(chip); - - __raw_writel(1 << MSP71XX_CFG_IN_OFFSET(offset), msp71xx_chip->reg); - return 0; -} - -#define MSP71XX_EXD_GPIO_BANK(name, exd_reg, base_gpio, num_gpio) \ -{ \ - .chip = { \ - .label = name, \ - .direction_input = msp71xx_exd_direction_input, \ - .direction_output = msp71xx_exd_direction_output, \ - .get = msp71xx_exd_gpio_get, \ - .set = msp71xx_exd_gpio_set, \ - .base = base_gpio, \ - .ngpio = num_gpio, \ - }, \ - .reg = (void __iomem *)(MSP71XX_EXD_GPIO_BASE + exd_reg), \ -} - -/* - * struct msp71xx_exd_gpio_banks[] - container array of gpio banks - * @chip: chip structure for the specified gpio bank - * @reg: register for reading and writing the gpio pin value - * - * This array structure defines the extended gpio banks for the - * PMC MIPS Processor. We specify the bank name, the data/config - * register,the base starting gpio number, and the number of - * gpios exposed by the bank of gpios. - */ -static struct msp71xx_exd_gpio_chip msp71xx_exd_gpio_banks[] = { - - MSP71XX_EXD_GPIO_BANK("GPIO_23_16", 0x188, 16, 8), - MSP71XX_EXD_GPIO_BANK("GPIO_27_24", 0x18C, 24, 4), -}; - -void __init msp71xx_init_gpio_extended(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(msp71xx_exd_gpio_banks); i++) - gpiochip_add(&msp71xx_exd_gpio_banks[i].chip); -} -- cgit v0.10.2 From d3478d5b73efb713378bebb31ac9a11f5a6dc587 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Fri, 14 Jun 2013 01:37:29 +0000 Subject: mips: lasat: sysctl: Convert use of typedef ctl_table to struct ctl_table This typedef is unnecessary and should just be removed. Signed-off-by: Joe Perches Cc: Jiri Kosina Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5460/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c index f27694f..3b7f65c 100644 --- a/arch/mips/lasat/sysctl.c +++ b/arch/mips/lasat/sysctl.c @@ -39,7 +39,7 @@ /* And the same for proc */ -int proc_dolasatstring(ctl_table *table, int write, +int proc_dolasatstring(struct ctl_table *table, int write, void *buffer, size_t *lenp, loff_t *ppos) { int r; @@ -54,7 +54,7 @@ int proc_dolasatstring(ctl_table *table, int write, } /* proc function to write EEPROM after changing int entry */ -int proc_dolasatint(ctl_table *table, int write, +int proc_dolasatint(struct ctl_table *table, int write, void *buffer, size_t *lenp, loff_t *ppos) { int r; @@ -72,7 +72,7 @@ int proc_dolasatint(ctl_table *table, int write, static int rtctmp; /* proc function to read/write RealTime Clock */ -int proc_dolasatrtc(ctl_table *table, int write, +int proc_dolasatrtc(struct ctl_table *table, int write, void *buffer, size_t *lenp, loff_t *ppos) { struct timespec ts; @@ -97,7 +97,7 @@ int proc_dolasatrtc(ctl_table *table, int write, #endif #ifdef CONFIG_INET -int proc_lasat_ip(ctl_table *table, int write, +int proc_lasat_ip(struct ctl_table *table, int write, void *buffer, size_t *lenp, loff_t *ppos) { unsigned int ip; @@ -157,7 +157,7 @@ int proc_lasat_ip(ctl_table *table, int write, } #endif -int proc_lasat_prid(ctl_table *table, int write, +int proc_lasat_prid(struct ctl_table *table, int write, void *buffer, size_t *lenp, loff_t *ppos) { int r; @@ -176,7 +176,7 @@ int proc_lasat_prid(ctl_table *table, int write, extern int lasat_boot_to_service; -static ctl_table lasat_table[] = { +static struct ctl_table lasat_table[] = { { .procname = "cpu-hz", .data = &lasat_board_info.li_cpu_hz, @@ -262,7 +262,7 @@ static ctl_table lasat_table[] = { {} }; -static ctl_table lasat_root_table[] = { +static struct ctl_table lasat_root_table[] = { { .procname = "lasat", .mode = 0555, -- cgit v0.10.2 From c5cdc67a58a22c49f558b450c6f748251ceb2e7b Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Thu, 13 Jun 2013 22:19:43 +0000 Subject: irqdomain: Remove temporary MIPS workaround code The MIPS interrupt controllers are all registering their own irq_domains now. Drop the MIPS specific code because it is no longer needed. Signed-off-by: Grant Likely Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5458/ Signed-off-by: Ralf Baechle diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index 54a4d52..a341b3d 100644 --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -665,18 +665,6 @@ unsigned int irq_create_of_mapping(struct device_node *controller, domain = controller ? irq_find_host(controller) : irq_default_domain; if (!domain) { -#ifdef CONFIG_MIPS - /* - * Workaround to avoid breaking interrupt controller drivers - * that don't yet register an irq_domain. This is temporary - * code. ~~~gcl, Feb 24, 2012 - * - * Scheduled for removal in Linux v3.6. That should be enough - * time. - */ - if (intsize > 0) - return intspec[0]; -#endif pr_warning("no irq domain found for %s !\n", of_node_full_name(controller)); return 0; -- cgit v0.10.2 From f746caa3fcd23663489bb6d4b41091b75a16efa2 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 12 Jun 2013 20:04:36 +0200 Subject: MIPS: diff --git a/arch/mips/include/uapi/asm/resource.h b/arch/mips/include/uapi/asm/resource.h index 87cb308..b26439d 100644 --- a/arch/mips/include/uapi/asm/resource.h +++ b/arch/mips/include/uapi/asm/resource.h @@ -26,7 +26,7 @@ * but we keep the old value on MIPS32, * for compatibility: */ -#ifdef CONFIG_32BIT +#ifndef __mips64 # define RLIM_INFINITY 0x7fffffffUL #endif -- cgit v0.10.2 From cfb9a4e7a0d821902e8cf77cabd34ef76e214e9d Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 12 Jun 2013 21:06:52 +0200 Subject: MIPS: : Don't reference CONFIG_* symbols. Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/uapi/asm/swab.h b/arch/mips/include/uapi/asm/swab.h index 97c2f81..ac9a8f9 100644 --- a/arch/mips/include/uapi/asm/swab.h +++ b/arch/mips/include/uapi/asm/swab.h @@ -13,7 +13,7 @@ #define __SWAB_64_THRU_32__ -#ifdef CONFIG_CPU_MIPSR2 +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) static inline __attribute_const__ __u16 __arch_swab16(__u16 x) { @@ -39,10 +39,10 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x) #define __arch_swab32 __arch_swab32 /* - * Having already checked for CONFIG_CPU_MIPSR2, enable the - * optimized version for 64-bit kernel on r2 CPUs. + * Having already checked for MIPS R2, enable the optimized version for + * 64-bit kernel on r2 CPUs. */ -#ifdef CONFIG_64BIT +#ifdef __mips64 static inline __attribute_const__ __u64 __arch_swab64(__u64 x) { __asm__( @@ -54,6 +54,6 @@ static inline __attribute_const__ __u64 __arch_swab64(__u64 x) return x; } #define __arch_swab64 __arch_swab64 -#endif /* CONFIG_64BIT */ -#endif /* CONFIG_CPU_MIPSR2 */ +#endif /* __mips64 */ +#endif /* MIPS R2 or newer */ #endif /* _ASM_SWAB_H */ -- cgit v0.10.2 From cfceb5e210d28d5dbc4d10e2a9191f4a81c4cece Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 12 Jun 2013 21:16:15 +0200 Subject: MIPS: : Don't reference CONFIG_* symbols. Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/uapi/asm/msgbuf.h b/arch/mips/include/uapi/asm/msgbuf.h index 0d6c7f1..df849e8 100644 --- a/arch/mips/include/uapi/asm/msgbuf.h +++ b/arch/mips/include/uapi/asm/msgbuf.h @@ -14,25 +14,25 @@ struct msqid64_ds { struct ipc64_perm msg_perm; -#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) +#if !defined(__mips64) && defined(__MIPSEB__) unsigned long __unused1; #endif __kernel_time_t msg_stime; /* last msgsnd time */ -#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) +#if !defined(__mips64) && defined(__MIPSEL__) unsigned long __unused1; #endif -#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) +#if !defined(__mips64) && defined(__MIPSEB__) unsigned long __unused2; #endif __kernel_time_t msg_rtime; /* last msgrcv time */ -#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) +#if !defined(__mips64) && defined(__MIPSEL__) unsigned long __unused2; #endif -#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) +#if !defined(__mips64) && defined(__MIPSEB__) unsigned long __unused3; #endif __kernel_time_t msg_ctime; /* last change time */ -#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) +#if !defined(__mips64) && defined(__MIPSEL__) unsigned long __unused3; #endif unsigned long msg_cbytes; /* current number of bytes on queue */ -- cgit v0.10.2 From c8d5c685647f7ce73ed642a9130e930ab69178d4 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 12 Jun 2013 21:23:52 +0200 Subject: MIPS: : Don't reference CONFIG_* symbols. Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/uapi/asm/siginfo.h b/arch/mips/include/uapi/asm/siginfo.h index 6a87141..b7a2306 100644 --- a/arch/mips/include/uapi/asm/siginfo.h +++ b/arch/mips/include/uapi/asm/siginfo.h @@ -25,10 +25,10 @@ struct siginfo; /* * Careful to keep union _sifields from shifting ... */ -#ifdef CONFIG_32BIT +#if __SIZEOF_LONG__ == 4 #define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int)) #endif -#ifdef CONFIG_64BIT +#if __SIZEOF_LONG__ == 8 #define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) #endif -- cgit v0.10.2 From 39205750efa6d335fac4f9bcd32b49c7e71c12b7 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 13 Jun 2013 01:29:24 +0200 Subject: MIPS: Oceton: Fix build error. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB, CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION, CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT and CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT are all undefined: arch/mips/cavium-octeon/setup.c: In function ‘prom_init’: arch/mips/cavium-octeon/setup.c:715:12: error: unused variable ‘ebase’ [-Werror=unused-variable] Signed-off-by: Ralf Baechle diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 01b1b3f..1bcc144 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -7,6 +7,7 @@ * Copyright (C) 2008, 2009 Wind River Systems * written by Ralf Baechle */ +#include #include #include #include @@ -712,7 +713,7 @@ void __init prom_init(void) if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { pr_info("Skipping L2 locking due to reduced L2 cache size\n"); } else { - uint32_t ebase = read_c0_ebase() & 0x3ffff000; + uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000; #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB /* TLB refill */ cvmx_l2c_lock_mem_region(ebase, 0x100); -- cgit v0.10.2 From 368b062509fac95c1e403ae4d2ff25fd4ca151fe Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 20 Jun 2013 16:10:50 +0200 Subject: MIPS: Octeon: Fix build error if CONFIG_BUG=n MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CC init/do_mounts.o In file included from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/dma-mapping.h:10:0, from include/linux/dma-mapping.h:76, from include/linux/skbuff.h:33, from include/linux/icmpv6.h:4, from include/linux/ipv6.h:59, from include/net/ipv6.h:16, from include/linux/sunrpc/clnt.h:26, from include/linux/nfs_fs.h:30, from init/do_mounts.c:30: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_map_dma_mem’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:24:1: warning: no return statement in function returning non-void [-Wreturn-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_map_dma_mem_page’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:30:1: warning: no return statement in function returning non-void [-Wreturn-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_addr_to_phys’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:36:1: warning: no return statement in function returning non-void [-Wreturn-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_supported’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:47:1: warning: no return statement in function returning non-void [-Wreturn-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_mapping_error’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:63:1: warning: no return statement in function returning non-void [-Wreturn-type] LD init/mounts.o CC init/init_task.o In file included from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/dma-mapping.h:10:0, from include/linux/dma-mapping.h:76, from include/linux/skbuff.h:33, from include/linux/netfilter.h:5, from include/net/netns/netfilter.h:5, from include/net/net_namespace.h:20, from include/linux/init_task.h:14, from init/init_task.c:1: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_map_dma_mem’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:24:1: warning: no return statement in function returning non-void [-Wreturn-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_map_dma_mem_page’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:30:1: warning: no return statement in function returning non-void [-Wreturn-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_addr_to_phys’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:36:1: warning: no return statement in function returning non-void [-Wreturn-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_supported’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:47:1: warning: no return statement in function returning non-void [-Wreturn-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_mapping_error’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:63:1: warning: no return statement in function returning non-void [-Wreturn-type] LD init/built-in.o CC arch/mips/cavium-octeon/setup.o In file included from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/dma-mapping.h:10:0, from include/linux/dma-mapping.h:76, from include/asm-generic/pci-dma-compat.h:7, from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/pci.h:129, from include/linux/pci.h:1451, from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/octeon/pci-octeon.h:12, from arch/mips/cavium-octeon/setup.c:41: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_map_dma_mem’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:24:1: error: no return statement in function returning non-void [-Werror=return-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_map_dma_mem_page’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:30:1: error: no return statement in function returning non-void [-Werror=return-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_addr_to_phys’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:36:1: error: no return statement in function returning non-void [-Werror=return-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_supported’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:47:1: error: no return statement in function returning non-void [-Werror=return-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_mapping_error’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:63:1: error: no return statement in function returning non-void [-Werror=return-type] cc1: all warnings being treated as errors make[2]: *** [arch/mips/cavium-octeon/setup.o] Error 1 make[1]: *** [arch/mips/cavium-octeon] Error 2 make: *** [arch/mips] Error 2 [ralf@linux-mips.org: while at it, also include directly.] Signed-off-by: David Daney Patchwork: https://patchwork.linux-mips.org/patch/5519/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h index be8fb42..47fb247 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h +++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h @@ -13,6 +13,8 @@ #ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H #define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H +#include + struct device; extern void octeon_pci_dma_init(void); @@ -21,18 +23,21 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) { BUG(); + return 0; } static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) { BUG(); + return 0; } static inline unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) { BUG(); + return 0; } static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, @@ -44,6 +49,7 @@ static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, static inline int plat_dma_supported(struct device *dev, u64 mask) { BUG(); + return 0; } static inline void plat_extra_sync_for_device(struct device *dev) @@ -60,6 +66,7 @@ static inline int plat_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { BUG(); + return 0; } dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr); -- cgit v0.10.2 From 68651ff6373421fff7452a0fdeed589801a26b6d Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 13 Jun 2013 02:26:34 +0200 Subject: MIPS: Octeon: Fix build error if CONFIG_MTD=n Signed-off-by: Ralf Baechle diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 3595aff..e3fd50c 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -13,10 +13,11 @@ CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o -obj-y += dma-octeon.o flash_setup.o +obj-y += dma-octeon.o obj-y += octeon-memcpy.o obj-y += executive/ +obj-$(CONFIG_MTD) += flash_setup.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o -- cgit v0.10.2 From 27f62b9f294b7e2019c94c385abda43a0af6bb8b Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 13 Jun 2013 02:45:53 +0200 Subject: RAPIDIO: IDT_GEN2: Fix build error. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CC drivers/rapidio/switches/idt_gen2.o drivers/rapidio/switches/idt_gen2.c: In function ‘idtg2_show_errlog’: drivers/rapidio/switches/idt_gen2.c:379:30: error: ‘PAGE_SIZE’ undeclared (first use in this function) drivers/rapidio/switches/idt_gen2.c:379:30: note: each undeclared identifier is reported only once for each function it appears in Signed-off-by: Ralf Baechle Acked-by: Alexandre Bounine diff --git a/drivers/rapidio/switches/idt_gen2.c b/drivers/rapidio/switches/idt_gen2.c index 809b7a3..5d3b0f0 100644 --- a/drivers/rapidio/switches/idt_gen2.c +++ b/drivers/rapidio/switches/idt_gen2.c @@ -15,6 +15,8 @@ #include #include #include + +#include #include "../rio.h" #define LOCAL_RTE_CONF_DESTID_SEL 0x010070 -- cgit v0.10.2 From 23946ef1658dc7f3d8e2fbdbb2110b4cc4267654 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 13 Jun 2013 12:32:32 +0200 Subject: MIPS: Move gas macro MAPPED_KERNEL_SETUP_TLB to IP27-specific code. It's IP27-specific and can only cause trouble in head.S. Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h index a323efb..3f6bc85 100644 --- a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h @@ -23,6 +23,45 @@ dsrl \res, NSRI_NODEID_SHFT .endm + /* + * inputs are the text nasid in t1, data nasid in t2. + */ + .macro MAPPED_KERNEL_SETUP_TLB +#ifdef CONFIG_MAPPED_KERNEL + /* + * This needs to read the nasid - assume 0 for now. + * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0, + * 0+DVG in tlblo_1. + */ + dli t0, 0xffffffffc0000000 + dmtc0 t0, CP0_ENTRYHI + li t0, 0x1c000 # Offset of text into node memory + dsll t1, NASID_SHFT # Shift text nasid into place + dsll t2, NASID_SHFT # Same for data nasid + or t1, t1, t0 # Physical load address of kernel text + or t2, t2, t0 # Physical load address of kernel data + dsrl t1, 12 # 4K pfn + dsrl t2, 12 # 4K pfn + dsll t1, 6 # Get pfn into place + dsll t2, 6 # Get pfn into place + li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6) + or t0, t0, t1 + mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr + li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6) + or t0, t0, t2 + mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr + li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M + mtc0 t0, CP0_PAGEMASK + li t0, 0 # KMAP_INX + mtc0 t0, CP0_INDEX + li t0, 1 + mtc0 t0, CP0_WIRED + tlbwi +#else + mtc0 zero, CP0_WIRED +#endif + .endm + /* * Intentionally empty macro, used in head.S. Override in * arch/mips/mach-xxx/kernel-entry-init.h when necessary. diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index c61cdae..0999123 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -28,45 +28,6 @@ #include /* - * inputs are the text nasid in t1, data nasid in t2. - */ - .macro MAPPED_KERNEL_SETUP_TLB -#ifdef CONFIG_MAPPED_KERNEL - /* - * This needs to read the nasid - assume 0 for now. - * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0, - * 0+DVG in tlblo_1. - */ - dli t0, 0xffffffffc0000000 - dmtc0 t0, CP0_ENTRYHI - li t0, 0x1c000 # Offset of text into node memory - dsll t1, NASID_SHFT # Shift text nasid into place - dsll t2, NASID_SHFT # Same for data nasid - or t1, t1, t0 # Physical load address of kernel text - or t2, t2, t0 # Physical load address of kernel data - dsrl t1, 12 # 4K pfn - dsrl t2, 12 # 4K pfn - dsll t1, 6 # Get pfn into place - dsll t2, 6 # Get pfn into place - li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6) - or t0, t0, t1 - mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr - li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6) - or t0, t0, t2 - mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr - li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M - mtc0 t0, CP0_PAGEMASK - li t0, 0 # KMAP_INX - mtc0 t0, CP0_INDEX - li t0, 1 - mtc0 t0, CP0_WIRED - tlbwi -#else - mtc0 zero, CP0_WIRED -#endif - .endm - - /* * For the moment disable interrupts, mark the kernel mode and * set ST0_KX so that the CPU does not spit fire when using * 64-bit addresses. A full initialization of the CPU's status -- cgit v0.10.2 From 28963b1e2054f8c0ea968717ecf68c5fa2da6745 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 13 Jun 2013 13:40:09 +0200 Subject: MIPS: IP27: Fix build error with CONFIG_MAPPED_KERNEL Some of the TLB bit definitions in have become rather complex and are no longer usable from assembler resulting in an explosion like this: AS arch/mips/kernel/head.o arch/mips/kernel/head.S: Assembler messages: arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: Illegal operands `li $12,(((1<<((cpu_has_rixi?(cpu_has_rixi?((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))+1:((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1))))+1:(cpu_has_rixi?((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))+1:((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))))+1))|(1<<(((cpu_has_rixi?(cpu_has_rixi?((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))+1:((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1))))+1:(cpu_has_rixi?((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))+1:((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))))+1)+1))|(5<<(((((cpu_has_rixi?(cpu_has_rixi?((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))+1:((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1))))+1:(cpu_has_rixi?((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))+1:((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))))+1)+1)+1)+1)))>>6)' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: missing ')' arch/mips/kernel/head.S:147: Error: Illegal operands `li $12,(((1<<((cpu_has_rixi?(cpu_has_rixi?((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))+1:((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1))))+1:(cpu_has_rixi?((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))+1:((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))))+1))|(1<<(((cpu_has_rixi?(cpu_has_rixi?((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))+1:((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1))))+1:(cpu_has_rixi?((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))+1:((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))))+1)+1))|(1<<((((cpu_has_rixi?(cpu_has_rixi?((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))+1:((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1))))+1:(cpu_has_rixi?((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))+1:((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))))+1)+1)+1))|(5<<(((((cpu_has_rixi?(cpu_has_rixi?((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))+1:((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1))))+1:(cpu_has_rixi?((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))+1:((((((cpu_has_rixi?(0):(0)+1)+1)+1)+1)))))+1)+1)+1)+1)))>>6)' make[2]: *** [arch/mips/kernel/head.o] Error 1 Since now MAPPED_KERNEL_SETUP_TLB is in platform-specific code it's safe to hardcode the TLB bits there. Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h index 3f6bc85..b087cb8 100644 --- a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h @@ -23,6 +23,14 @@ dsrl \res, NSRI_NODEID_SHFT .endm +/* + * TLB bits + */ +#define PAGE_GLOBAL (1 << 6) +#define PAGE_VALID (1 << 7) +#define PAGE_DIRTY (1 << 8) +#define CACHE_CACHABLE_COW (5 << 9) + /* * inputs are the text nasid in t1, data nasid in t2. */ @@ -44,10 +52,10 @@ dsrl t2, 12 # 4K pfn dsll t1, 6 # Get pfn into place dsll t2, 6 # Get pfn into place - li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6) + li t0, ((PAGE_GLOBAL | PAGE_VALID | CACHE_CACHABLE_COW) >> 6) or t0, t0, t1 mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr - li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6) + li t0, ((PAGE_GLOBAL | PAGE_VALID | PAGE_DIRTY | CACHE_CACHABLE_COW) >> 6) or t0, t0, t2 mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M -- cgit v0.10.2 From 8ea2b8b605d0053fc87abde56ff42b19520322f0 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 13 Jun 2013 14:04:16 +0200 Subject: MIPS: IP27: Fix build errors with CONFIG_PCI disabled. LD init/built-in.o arch/mips/built-in.o: In function `startup_bridge_irq': ip27-irq.c:(.text+0x434): undefined reference to `irq_to_slot' ip27-irq.c:(.text+0x43c): undefined reference to `irq_to_slot' ip27-irq.c:(.text+0x460): undefined reference to `irq_to_bridge' ip27-irq.c:(.text+0x464): undefined reference to `irq_to_bridge' arch/mips/built-in.o: In function `shutdown_bridge_irq': ip27-irq.c:(.text+0x564): undefined reference to `irq_to_bridge' ip27-irq.c:(.text+0x56c): undefined reference to `irq_to_bridge' ip27-irq.c:(.text+0x5a0): undefined reference to `irq_to_slot' ip27-irq.c:(.text+0x5a4): undefined reference to `irq_to_slot' Signed-off-by: Ralf Baechle diff --git a/arch/mips/sgi-ip27/Makefile b/arch/mips/sgi-ip27/Makefile index 1f29e76..da8f681 100644 --- a/arch/mips/sgi-ip27/Makefile +++ b/arch/mips/sgi-ip27/Makefile @@ -7,4 +7,5 @@ obj-y := ip27-berr.o ip27-irq.o ip27-init.o ip27-klconfig.o ip27-klnuma.o \ ip27-xtalk.o obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o +obj-$(CONFIG_PCI) += ip27-irq-pci.o obj-$(CONFIG_SMP) += ip27-smp.o diff --git a/arch/mips/sgi-ip27/ip27-irq-pci.c b/arch/mips/sgi-ip27/ip27-irq-pci.c new file mode 100644 index 0000000..ec22ec5 --- /dev/null +++ b/arch/mips/sgi-ip27/ip27-irq-pci.c @@ -0,0 +1,266 @@ +/* + * ip27-irq.c: Highlevel interrupt handling for IP27 architecture. + * + * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 1999 - 2001 Kanoj Sarcar + */ + +#undef DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* + * Linux has a controller-independent x86 interrupt architecture. + * every controller has a 'controller-template', that is used + * by the main code to do the right thing. Each driver-visible + * interrupt source is transparently wired to the appropriate + * controller. Thus drivers need not be aware of the + * interrupt-controller. + * + * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC, + * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC. + * (IO-APICs assumed to be messaging to Pentium local-APICs) + * + * the code is designed to be easily extended with new/different + * interrupt controllers, without having to do assembly magic. + */ + +extern struct bridge_controller *irq_to_bridge[]; +extern int irq_to_slot[]; + +/* + * use these macros to get the encoded nasid and widget id + * from the irq value + */ +#define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)] +#define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i] + +static inline int alloc_level(int cpu, int irq) +{ + struct hub_data *hub = hub_data(cpu_to_node(cpu)); + struct slice_data *si = cpu_data[cpu].data; + int level; + + level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE); + if (level >= LEVELS_PER_SLICE) + panic("Cpu %d flooded with devices", cpu); + + __set_bit(level, hub->irq_alloc_mask); + si->level_to_irq[level] = irq; + + return level; +} + +static inline int find_level(cpuid_t *cpunum, int irq) +{ + int cpu, i; + + for_each_online_cpu(cpu) { + struct slice_data *si = cpu_data[cpu].data; + + for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++) + if (si->level_to_irq[i] == irq) { + *cpunum = cpu; + + return i; + } + } + + panic("Could not identify cpu/level for irq %d", irq); +} + +static int intr_connect_level(int cpu, int bit) +{ + nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); + struct slice_data *si = cpu_data[cpu].data; + + set_bit(bit, si->irq_enable_mask); + + if (!cputoslice(cpu)) { + REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); + REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]); + } else { + REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]); + REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]); + } + + return 0; +} + +static int intr_disconnect_level(int cpu, int bit) +{ + nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); + struct slice_data *si = cpu_data[cpu].data; + + clear_bit(bit, si->irq_enable_mask); + + if (!cputoslice(cpu)) { + REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); + REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]); + } else { + REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]); + REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]); + } + + return 0; +} + +/* Startup one of the (PCI ...) IRQs routes over a bridge. */ +static unsigned int startup_bridge_irq(struct irq_data *d) +{ + struct bridge_controller *bc; + bridgereg_t device; + bridge_t *bridge; + int pin, swlevel; + cpuid_t cpu; + + pin = SLOT_FROM_PCI_IRQ(d->irq); + bc = IRQ_TO_BRIDGE(d->irq); + bridge = bc->base; + + pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin); + /* + * "map" irq to a swlevel greater than 6 since the first 6 bits + * of INT_PEND0 are taken + */ + swlevel = find_level(&cpu, d->irq); + bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8)); + bridge->b_int_enable |= (1 << pin); + bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */ + + /* + * Enable sending of an interrupt clear packt to the hub on a high to + * low transition of the interrupt pin. + * + * IRIX sets additional bits in the address which are documented as + * reserved in the bridge docs. + */ + bridge->b_int_mode |= (1UL << pin); + + /* + * We assume the bridge to have a 1:1 mapping between devices + * (slots) and intr pins. + */ + device = bridge->b_int_device; + device &= ~(7 << (pin*3)); + device |= (pin << (pin*3)); + bridge->b_int_device = device; + + bridge->b_wid_tflush; + + intr_connect_level(cpu, swlevel); + + return 0; /* Never anything pending. */ +} + +/* Shutdown one of the (PCI ...) IRQs routes over a bridge. */ +static void shutdown_bridge_irq(struct irq_data *d) +{ + struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq); + bridge_t *bridge = bc->base; + int pin, swlevel; + cpuid_t cpu; + + pr_debug("bridge_shutdown: irq 0x%x\n", d->irq); + pin = SLOT_FROM_PCI_IRQ(d->irq); + + /* + * map irq to a swlevel greater than 6 since the first 6 bits + * of INT_PEND0 are taken + */ + swlevel = find_level(&cpu, d->irq); + intr_disconnect_level(cpu, swlevel); + + bridge->b_int_enable &= ~(1 << pin); + bridge->b_wid_tflush; +} + +static inline void enable_bridge_irq(struct irq_data *d) +{ + cpuid_t cpu; + int swlevel; + + swlevel = find_level(&cpu, d->irq); /* Criminal offence */ + intr_connect_level(cpu, swlevel); +} + +static inline void disable_bridge_irq(struct irq_data *d) +{ + cpuid_t cpu; + int swlevel; + + swlevel = find_level(&cpu, d->irq); /* Criminal offence */ + intr_disconnect_level(cpu, swlevel); +} + +static struct irq_chip bridge_irq_type = { + .name = "bridge", + .irq_startup = startup_bridge_irq, + .irq_shutdown = shutdown_bridge_irq, + .irq_mask = disable_bridge_irq, + .irq_unmask = enable_bridge_irq, +}; + +void register_bridge_irq(unsigned int irq) +{ + irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq); +} + +int request_bridge_irq(struct bridge_controller *bc) +{ + int irq = allocate_irqno(); + int swlevel, cpu; + nasid_t nasid; + + if (irq < 0) + return irq; + + /* + * "map" irq to a swlevel greater than 6 since the first 6 bits + * of INT_PEND0 are taken + */ + cpu = bc->irq_cpu; + swlevel = alloc_level(cpu, irq); + if (unlikely(swlevel < 0)) { + free_irqno(irq); + + return -EAGAIN; + } + + /* Make sure it's not already pending when we connect it. */ + nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); + REMOTE_HUB_CLR_INTR(nasid, swlevel); + + intr_connect_level(cpu, swlevel); + + register_bridge_irq(irq); + + return irq; +} diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index 2315cfe..3fbaef9 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c @@ -29,7 +29,6 @@ #include #include -#include #include #include #include @@ -54,50 +53,6 @@ extern asmlinkage void ip27_irq(void); -extern struct bridge_controller *irq_to_bridge[]; -extern int irq_to_slot[]; - -/* - * use these macros to get the encoded nasid and widget id - * from the irq value - */ -#define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)] -#define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i] - -static inline int alloc_level(int cpu, int irq) -{ - struct hub_data *hub = hub_data(cpu_to_node(cpu)); - struct slice_data *si = cpu_data[cpu].data; - int level; - - level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE); - if (level >= LEVELS_PER_SLICE) - panic("Cpu %d flooded with devices", cpu); - - __set_bit(level, hub->irq_alloc_mask); - si->level_to_irq[level] = irq; - - return level; -} - -static inline int find_level(cpuid_t *cpunum, int irq) -{ - int cpu, i; - - for_each_online_cpu(cpu) { - struct slice_data *si = cpu_data[cpu].data; - - for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++) - if (si->level_to_irq[i] == irq) { - *cpunum = cpu; - - return i; - } - } - - panic("Could not identify cpu/level for irq %d", irq); -} - /* * Find first bit set */ @@ -204,175 +159,6 @@ static void ip27_hub_error(void) panic("CPU %d got a hub error interrupt", smp_processor_id()); } -static int intr_connect_level(int cpu, int bit) -{ - nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); - struct slice_data *si = cpu_data[cpu].data; - - set_bit(bit, si->irq_enable_mask); - - if (!cputoslice(cpu)) { - REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); - REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]); - } else { - REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]); - REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]); - } - - return 0; -} - -static int intr_disconnect_level(int cpu, int bit) -{ - nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); - struct slice_data *si = cpu_data[cpu].data; - - clear_bit(bit, si->irq_enable_mask); - - if (!cputoslice(cpu)) { - REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); - REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]); - } else { - REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]); - REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]); - } - - return 0; -} - -/* Startup one of the (PCI ...) IRQs routes over a bridge. */ -static unsigned int startup_bridge_irq(struct irq_data *d) -{ - struct bridge_controller *bc; - bridgereg_t device; - bridge_t *bridge; - int pin, swlevel; - cpuid_t cpu; - - pin = SLOT_FROM_PCI_IRQ(d->irq); - bc = IRQ_TO_BRIDGE(d->irq); - bridge = bc->base; - - pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin); - /* - * "map" irq to a swlevel greater than 6 since the first 6 bits - * of INT_PEND0 are taken - */ - swlevel = find_level(&cpu, d->irq); - bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8)); - bridge->b_int_enable |= (1 << pin); - bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */ - - /* - * Enable sending of an interrupt clear packt to the hub on a high to - * low transition of the interrupt pin. - * - * IRIX sets additional bits in the address which are documented as - * reserved in the bridge docs. - */ - bridge->b_int_mode |= (1UL << pin); - - /* - * We assume the bridge to have a 1:1 mapping between devices - * (slots) and intr pins. - */ - device = bridge->b_int_device; - device &= ~(7 << (pin*3)); - device |= (pin << (pin*3)); - bridge->b_int_device = device; - - bridge->b_wid_tflush; - - intr_connect_level(cpu, swlevel); - - return 0; /* Never anything pending. */ -} - -/* Shutdown one of the (PCI ...) IRQs routes over a bridge. */ -static void shutdown_bridge_irq(struct irq_data *d) -{ - struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq); - bridge_t *bridge = bc->base; - int pin, swlevel; - cpuid_t cpu; - - pr_debug("bridge_shutdown: irq 0x%x\n", d->irq); - pin = SLOT_FROM_PCI_IRQ(d->irq); - - /* - * map irq to a swlevel greater than 6 since the first 6 bits - * of INT_PEND0 are taken - */ - swlevel = find_level(&cpu, d->irq); - intr_disconnect_level(cpu, swlevel); - - bridge->b_int_enable &= ~(1 << pin); - bridge->b_wid_tflush; -} - -static inline void enable_bridge_irq(struct irq_data *d) -{ - cpuid_t cpu; - int swlevel; - - swlevel = find_level(&cpu, d->irq); /* Criminal offence */ - intr_connect_level(cpu, swlevel); -} - -static inline void disable_bridge_irq(struct irq_data *d) -{ - cpuid_t cpu; - int swlevel; - - swlevel = find_level(&cpu, d->irq); /* Criminal offence */ - intr_disconnect_level(cpu, swlevel); -} - -static struct irq_chip bridge_irq_type = { - .name = "bridge", - .irq_startup = startup_bridge_irq, - .irq_shutdown = shutdown_bridge_irq, - .irq_mask = disable_bridge_irq, - .irq_unmask = enable_bridge_irq, -}; - -void register_bridge_irq(unsigned int irq) -{ - irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq); -} - -int request_bridge_irq(struct bridge_controller *bc) -{ - int irq = allocate_irqno(); - int swlevel, cpu; - nasid_t nasid; - - if (irq < 0) - return irq; - - /* - * "map" irq to a swlevel greater than 6 since the first 6 bits - * of INT_PEND0 are taken - */ - cpu = bc->irq_cpu; - swlevel = alloc_level(cpu, irq); - if (unlikely(swlevel < 0)) { - free_irqno(irq); - - return -EAGAIN; - } - - /* Make sure it's not already pending when we connect it. */ - nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); - REMOTE_HUB_CLR_INTR(nasid, swlevel); - - intr_connect_level(cpu, swlevel); - - register_bridge_irq(irq); - - return irq; -} - asmlinkage void plat_irq_dispatch(void) { unsigned long pending = read_c0_cause() & read_c0_status(); -- cgit v0.10.2 From 73ec78b06ecadb2ce67aae2509e8683ad8b92d14 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 13 Jun 2013 14:05:03 +0200 Subject: MIPS: IP27: Fix build errors with CONFIG_PCI disabled. LD init/built-in.o arch/mips/built-in.o: In function `xtalk_probe_node': (.cpuinit.text+0x67c): undefined reference to `bridge_probe' arch/mips/built-in.o: In function `xtalk_probe_node': (.cpuinit.text+0x7d8): undefined reference to `bridge_probe' Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/xtalk/xtalk.h b/arch/mips/include/asm/xtalk/xtalk.h index 680e7ef..26d2ed1 100644 --- a/arch/mips/include/asm/xtalk/xtalk.h +++ b/arch/mips/include/asm/xtalk/xtalk.h @@ -47,6 +47,15 @@ typedef struct xtalk_piomap_s *xtalk_piomap_t; #define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT)) #define XIO_PACK(p, o) ((((uint64_t)(p))< Date: Thu, 13 Jun 2013 14:34:50 +0200 Subject: MIPS: IP27: Fix build error if CONFIG_PCI=y and CONFIG_NUMA disabled. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Then will define cpp macro as default definition for pcibus_to_node resulting in: CC arch/mips/pci/pci-ip27.o arch/mips/pci/pci-ip27.c:220:7: error: expected identifier or ‘(’ before ‘void’ arch/mips/pci/pci-ip27.c:220:12: error: expected ‘)’ before ‘(’ token make[1]: *** [arch/mips/pci/pci-ip27.o] Error 1 Signed-off-by: Ralf Baechle diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index 6eb65e4..7b2ac81 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -217,6 +217,7 @@ static void pci_fixup_ioc3(struct pci_dev *d) pci_disable_swapping(d); } +#ifdef CONFIG_NUMA int pcibus_to_node(struct pci_bus *bus) { struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); @@ -224,6 +225,7 @@ int pcibus_to_node(struct pci_bus *bus) return bc->nasid; } EXPORT_SYMBOL(pcibus_to_node); +#endif /* CONFIG_NUMA */ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, pci_fixup_ioc3); -- cgit v0.10.2 From d949b4fe6d23dd92b5fa48cbf7af90ca32beed2e Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 12 Jun 2013 17:28:33 +0000 Subject: MIPS: Octeon: Don't clobber bootloader data structures. Commit abe77f90dc (MIPS: Octeon: Add kexec and kdump support) added a bootmem region for the kernel image itself. The problem is that this is rounded up to a 0x100000 boundary, which is memory that may not be owned by the kernel. Depending on the kernel's configuration based size, this 'extra' memory may contain data passed from the bootloader to the kernel itself, which if clobbered makes the kernel crash in various ways. The fix: Quit rounding the size up, so that we only use memory assigned to the kernel. Signed-off-by: David Daney Cc: Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5449/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 1bcc144..2a75ff2 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -997,7 +997,7 @@ void __init plat_mem_setup(void) cvmx_bootmem_unlock(); /* Add the memory region for the kernel. */ kernel_start = (unsigned long) _text; - kernel_size = ALIGN(_end - _text, 0x100000); + kernel_size = _end - _text; /* Adjust for physical offset. */ kernel_start &= ~0xffffffff80000000ULL; -- cgit v0.10.2 From 25c87eae1725ed77a8b44d782a86abdc279b4ede Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Tue, 11 Jun 2013 08:49:50 +0000 Subject: lib/Kconfig.debug: Restrict FRAME_POINTER for MIPS FAULT_INJECTION_STACKTRACE_FILTER selects FRAME_POINTER but that symbol is not available for MIPS. Fixes the following problem on a randconfig: warning: (LOCKDEP && FAULT_INJECTION_STACKTRACE_FILTER && LATENCYTOP && KMEMCHECK) selects FRAME_POINTER which has unmet direct dependencies (DEBUG_KERNEL && (CRIS || M68K || FRV || UML || AVR32 || SUPERH || BLACKFIN || MN10300 || METAG) || ARCH_WANT_FRAME_POINTERS) Signed-off-by: Markos Chandras Acked-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5441/ Signed-off-by: Ralf Baechle diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index 566cf2b..74fdc5c 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -1272,7 +1272,7 @@ config FAULT_INJECTION_STACKTRACE_FILTER depends on FAULT_INJECTION_DEBUG_FS && STACKTRACE_SUPPORT depends on !X86_64 select STACKTRACE - select FRAME_POINTER if !PPC && !S390 && !MICROBLAZE && !ARM_UNWIND + select FRAME_POINTER if !MIPS && !PPC && !S390 && !MICROBLAZE && !ARM_UNWIND help Provide stacktrace filter for fault-injection capabilities -- cgit v0.10.2 From 2f963bfbd84207776725db82287b73cfeeab8a92 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Tue, 19 Feb 2013 02:00:39 +0200 Subject: MIPS: Loongson: Fix random early boot hang Some Loongson boards (e.g. Lemote FuLoong mini-PC) use ISA/southbridge device (CS5536 general purpose timer) for the timer interrupt. It starts running early and is already enabled during the PCI configuration, during which there is a small window in pci_read_base() when the register access is temporarily disabled. If the timer interrupts at this point, the system will hang. Fix this by adding a fixup that keeps the register access always enabled. The hang the patch fixes usually looks like this: [ 0.844000] pci 0000:00:0e.0: [1022:2090] type 00 class 0x060100 [ 0.848000] pci 0000:00:0e.0: reg 10: [io 0xb410-0xb417] [ 0.852000] pci 0000:00:0e.0: reg 14: [io 0xb000-0xb0ff] [ 0.856000] pci 0000:00:0e.0: reg 18: [io 0xb380-0xb3bf] [ 28.140000] BUG: soft lockup - CPU#0 stuck for 23s! [swapper:1] [ 28.140000] Modules linked in: [ 28.140000] irq event stamp: 37965 [ 28.140000] hardirqs last enabled at (37964): [] restore_partial+0x6c/0x13c [ 28.140000] hardirqs last disabled at (37965): [] handle_int+0x144/0x15c [ 28.140000] softirqs last enabled at (24316): [] __do_softirq+0x1cc/0x258 [ 28.140000] softirqs last disabled at (24327): [] do_softirq+0xc8/0xd0 [ 28.140000] Cpu 0 [ 28.140000] $ 0 : 0000000000000000 00000000140044e1 980000009f090000 0000000000000001 [ 28.140000] $ 4 : 980000009f090000 0000000000000000 0000000000000100 03b7fff87fbde011 [ 28.140000] $ 8 : ffffffff812b1928 000000000001e000 043ffff87fbde011 fffffff87fbde011 [ 28.140000] $12 : 000000000000000e ffffffff807a0000 0000000000000698 0000000000000000 [ 28.140000] $16 : 0000000000000002 ffffffff81055e20 ffffffff80786810 0000000000000000 [ 28.140000] $20 : 000000000000000a ffffffff807bc244 ffffffff807e6350 ffffffff80770000 [ 28.140000] $24 : 0000000000000d80 00000000fffedbe0 [ 28.140000] $28 : 980000009f07c000 980000009f07fa10 ffffffff81050000 ffffffff802380f8 [ 28.140000] Hi : 0000000000d0fc00 [ 28.140000] Lo : 0000000000f82b40 [ 28.140000] epc : ffffffff8023810c __do_softirq+0xe4/0x258 [ 28.140000] Not tainted [ 28.140000] ra : ffffffff802380f8 __do_softirq+0xd0/0x258 [ 28.140000] Status: 140044e3 KX SX UX KERNEL EXL IE [ 28.140000] Cause : 10008400 [ 28.140000] PrId : 00006303 (ICT Loongson-2) Signed-off-by: Aaro Koskinen Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/4958/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/loongson/common/cs5536/cs5536_isa.c b/arch/mips/loongson/common/cs5536/cs5536_isa.c index a6eb2e8..924be39 100644 --- a/arch/mips/loongson/common/cs5536/cs5536_isa.c +++ b/arch/mips/loongson/common/cs5536/cs5536_isa.c @@ -13,6 +13,7 @@ * option) any later version. */ +#include #include #include @@ -314,3 +315,16 @@ u32 pci_isa_read_reg(int reg) return conf_data; } + +/* + * The mfgpt timer interrupt is running early, so we must keep the south bridge + * mmio always enabled. Otherwise we may race with the PCI configuration which + * may temporarily disable it. When that happens and the timer interrupt fires, + * we are not able to clear it and the system will hang. + */ +static void cs5536_isa_mmio_always_on(struct pci_dev *dev) +{ + dev->mmio_always_on = 1; +} +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, + PCI_CLASS_BRIDGE_ISA, 8, cs5536_isa_mmio_always_on); -- cgit v0.10.2 From 2ddbc4e2f9729ce62f9286868eab6f1523f00d67 Mon Sep 17 00:00:00 2001 From: "Steven J. Hill" Date: Thu, 13 Jun 2013 19:55:04 +0000 Subject: MIPS: sead3: Fix ability to perform a soft reset. The soft reset register address and reset value to be written are incorrect for the SEAD-3 platform. This patch fixes them such that the SEAD-3 can actually perform a soft reset instead of causing an exception. Also remove usage of 'include/asm/mips-boards/generic.h' header file. Signed-off-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5454/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/mti-sead3/sead3-reset.c b/arch/mips/mti-sead3/sead3-reset.c index 20475c5..e6fb244 100644 --- a/arch/mips/mti-sead3/sead3-reset.c +++ b/arch/mips/mti-sead3/sead3-reset.c @@ -9,7 +9,9 @@ #include #include -#include + +#define SOFTRES_REG 0x1f000050 +#define GORESET 0x4d static void mips_machine_restart(char *command) { @@ -35,5 +37,4 @@ static int __init mips_reboot_setup(void) return 0; } - arch_initcall(mips_reboot_setup); -- cgit v0.10.2 From 36a29af4bed7169f3332c44846576243d5abe9a5 Mon Sep 17 00:00:00 2001 From: "Steven J. Hill" Date: Thu, 13 Jun 2013 19:55:05 +0000 Subject: MIPS: malta: Move defines of reset registers and values. Remove usage of 'include/asm/mips-boards/generic.h' header file. Instead, move the defines for SOFTRES_REG and GORESET local to the platform file. Signed-off-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5455/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/mti-malta/malta-reset.c b/arch/mips/mti-malta/malta-reset.c index 3294205..7911012 100644 --- a/arch/mips/mti-malta/malta-reset.c +++ b/arch/mips/mti-malta/malta-reset.c @@ -27,7 +27,9 @@ #include #include -#include + +#define SOFTRES_REG 0x1f000500 +#define GORESET 0x42 static void mips_machine_restart(char *command) { -- cgit v0.10.2 From b72d9a4ef322f55f159df144bc702d9643e5a221 Mon Sep 17 00:00:00 2001 From: "Steven J. Hill" Date: Thu, 13 Jun 2013 19:55:06 +0000 Subject: MIPS: malta: Remove software reset defines from generic header. Remove the software reset register and reset value definitions from the 'include/asm/mips-boards/generic.h' header file. Also clean up header and whitespace in platform file. Signed-off-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5456/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h index bd9746f..4861681 100644 --- a/arch/mips/include/asm/mips-boards/generic.h +++ b/arch/mips/include/asm/mips-boards/generic.h @@ -24,12 +24,6 @@ #define ASCII_DISPLAY_POS_BASE 0x1f000418 /* - * Reset register. - */ -#define SOFTRES_REG 0x1f000500 -#define GORESET 0x42 - -/* * Revision register. */ #define MIPS_REVISION_REG 0x1fc00010 diff --git a/arch/mips/mti-malta/malta-reset.c b/arch/mips/mti-malta/malta-reset.c index 7911012..d627d4b 100644 --- a/arch/mips/mti-malta/malta-reset.c +++ b/arch/mips/mti-malta/malta-reset.c @@ -1,31 +1,14 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * Carsten Langgaard, carstenl@mips.com * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Reset the MIPS boards. - * */ -#include +#include #include -#include #include #define SOFTRES_REG 0x1f000500 @@ -47,7 +30,6 @@ static void mips_machine_halt(void) __raw_writel(GORESET, softres_reg); } - static int __init mips_reboot_setup(void) { _machine_restart = mips_machine_restart; @@ -56,5 +38,4 @@ static int __init mips_reboot_setup(void) return 0; } - arch_initcall(mips_reboot_setup); -- cgit v0.10.2 From 9b1f812acb607bcdfafd8cacec89f9b736e2be0c Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 13 Jun 2013 20:10:47 +0000 Subject: MIPS/OCTEON: Override default address space layout. OCTEON II cannot execute code in the default CAC_BASE space, so we supply a value (0x8000000000000000) that does work. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5457/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/mach-cavium-octeon/spaces.h b/arch/mips/include/asm/mach-cavium-octeon/spaces.h new file mode 100644 index 0000000..daa91ac --- /dev/null +++ b/arch/mips/include/asm/mach-cavium-octeon/spaces.h @@ -0,0 +1,24 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 Cavium, Inc. + */ +#ifndef _ASM_MACH_CAVIUM_OCTEON_SPACES_H +#define _ASM_MACH_CAVIUM_OCTEON_SPACES_H + +#include + +#ifdef CONFIG_64BIT +/* They are all the same and some OCTEON II cores cannot handle 0xa8.. */ +#define CAC_BASE _AC(0x8000000000000000, UL) +#define UNCAC_BASE _AC(0x8000000000000000, UL) +#define IO_BASE _AC(0x8000000000000000, UL) + + +#endif /* CONFIG_64BIT */ + +#include + +#endif /* _ASM_MACH_CAVIUM_OCTEON_SPACES_H */ -- cgit v0.10.2 From 970cb7b963885afff070b315d85a56808bdf2788 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Mon, 17 Jun 2013 07:42:11 +0000 Subject: MIPS: ath79: Fix argument for the ap136_pc_init function ap136_pci_init expects a u8 pointer as an argument. Fixes the following build problem on a randconfig: arch/mips/ath79/mach-ap136.c:151:2: error: too many arguments to function 'ap136_pci_init' Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5476/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/ath79/mach-ap136.c b/arch/mips/ath79/mach-ap136.c index 479dd4b..07eac58 100644 --- a/arch/mips/ath79/mach-ap136.c +++ b/arch/mips/ath79/mach-ap136.c @@ -132,7 +132,7 @@ static void __init ap136_pci_init(u8 *eeprom) ath79_register_pci(); } #else -static inline void ap136_pci_init(void) {} +static inline void ap136_pci_init(u8 *eeprom) {} #endif /* CONFIG_PCI */ static void __init ap136_setup(void) -- cgit v0.10.2 From d6095cace181603a1200652c4b249ff648c205a8 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Mon, 17 Jun 2013 13:00:41 +0000 Subject: MIPS: sibyte: Remove unused variable. Fixes the following build problem: arch/mips/sibyte/sb1250/bus_watcher.c: In function 'sibyte_bw_int': arch/mips/sibyte/sb1250/bus_watcher.c:179:7: error: unused variable 'bw_buf' [-Werror=unused-variable] Signed-off-by: Markos Chandras Cc: sibyte-users@bitmover.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5481/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c index 8871e33..d0ca7b9 100644 --- a/arch/mips/sibyte/sb1250/bus_watcher.c +++ b/arch/mips/sibyte/sb1250/bus_watcher.c @@ -175,9 +175,6 @@ static irqreturn_t sibyte_bw_int(int irq, void *data) #ifdef CONFIG_SIBYTE_BW_TRACE int i; #endif -#ifndef CONFIG_PROC_FS - char bw_buf[1024]; -#endif #ifdef CONFIG_SIBYTE_BW_TRACE csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); -- cgit v0.10.2 From 0156915cc0202e87cac1c8507b2b71eb899a9652 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Mon, 17 Jun 2013 13:00:37 +0000 Subject: MIPS: Sibyte: Add missing sched.h header It's needed for the TASK_INTERRUPTIBLE definition. Fixes the following build problem: arch/mips/sibyte/common/sb_tbprof.c:235:4: error: 'TASK_INTERRUPTIBLE' undeclared (first use in this function) [ralf@linux-mips.org: Ideally sched.h should be included into the actual user of TASK_INTERRUPTIBLE, but that seems way too risky that close to a release.] Signed-off-by: Markos Chandras Acked-by: Steven J. Hill Cc: sibyte-users@bitmover.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5479/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c index 2188b39..059e28c 100644 --- a/arch/mips/sibyte/common/sb_tbprof.c +++ b/arch/mips/sibyte/common/sb_tbprof.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include -- cgit v0.10.2 From 39b6f3aa1979ad7df42474d3c63bbc7e25bd31e4 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Mon, 17 Jun 2013 13:00:36 +0000 Subject: MIPS: sibyte: Declare the cfe_write() buffer as constant The write() prototype expects a const char * as argument so declare it as such. Fixes the following build problem: arch/mips/sibyte/common/cfe_console.c:23:5: error: passing argument 2 of 'cfe_write' discards 'const' qualifier from pointer target type [-Werror] arch/mips/sibyte/common/cfe_console.c:34:4: error: passing argument 2 of 'cfe_write' makes pointer from integer without a cast [-Werror] Signed-off-by: Markos Chandras Acked-by: Steven J. Hill Cc: sibyte-users@bitmover.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5485/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/fw/cfe/cfe_api.c b/arch/mips/fw/cfe/cfe_api.c index d06dc5a6..cf84f01 100644 --- a/arch/mips/fw/cfe/cfe_api.c +++ b/arch/mips/fw/cfe/cfe_api.c @@ -406,12 +406,12 @@ int cfe_setenv(char *name, char *val) return xiocb.xiocb_status; } -int cfe_write(int handle, unsigned char *buffer, int length) +int cfe_write(int handle, const char *buffer, int length) { return cfe_writeblk(handle, 0, buffer, length); } -int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length) +int cfe_writeblk(int handle, s64 offset, const char *buffer, int length) { struct cfe_xiocb xiocb; diff --git a/arch/mips/include/asm/fw/cfe/cfe_api.h b/arch/mips/include/asm/fw/cfe/cfe_api.h index 1734755..a0ea69e 100644 --- a/arch/mips/include/asm/fw/cfe/cfe_api.h +++ b/arch/mips/include/asm/fw/cfe/cfe_api.h @@ -115,8 +115,8 @@ int cfe_read(int handle, unsigned char *buffer, int length); int cfe_readblk(int handle, int64_t offset, unsigned char *buffer, int length); int cfe_setenv(char *name, char *val); -int cfe_write(int handle, unsigned char *buffer, int length); -int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer, +int cfe_write(int handle, const char *buffer, int length); +int cfe_writeblk(int handle, int64_t offset, const char *buffer, int length); #endif /* CFE_API_H */ -- cgit v0.10.2 From 55e9741a323fb77a11c368de51f8a4fa757311df Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 19 Jun 2013 19:25:06 +0200 Subject: MIPS: Sibyte: Fix build for SIBYTE_BW_TRACE on BCM1x55 and BCM1x80. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CC arch/mips/mm/cerr-sb1.o arch/mips/mm/cerr-sb1.c: In function ‘sb1_cache_error’: arch/mips/mm/cerr-sb1.c:186:98: error: ‘M_BCM1480_SCD_TRACE_CFG_FREEZE’ undeclared (first use in this function) arch/mips/mm/cerr-sb1.c:186:98: note: each undeclared identifier is reported only once for each function it appears in make[1]: *** [arch/mips/mm/cerr-sb1.o] Error 1 This happens because 8deab1144b553548fb2f1b51affdd36dcd652aaa [[MIPS] Updated Sibyte headers] changed the headers but not all the users. Signed-off-by: Ralf Baechle Reported-by: Markos Chandras Patchwork: https://patchwork.linux-mips.org/patch/5511/ diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c index 576add3..ee5c1ff 100644 --- a/arch/mips/mm/cerr-sb1.c +++ b/arch/mips/mm/cerr-sb1.c @@ -182,11 +182,7 @@ asmlinkage void sb1_cache_error(void) #ifdef CONFIG_SIBYTE_BW_TRACE /* Freeze the trace buffer now */ -#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) - csr_out32(M_BCM1480_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); -#else csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); -#endif printk("Trace buffer frozen\n"); #endif -- cgit v0.10.2 From ae5b0e0973ae1326809084aa3243a97f180cc903 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 19 Jun 2013 20:18:55 +0200 Subject: MIPS: Sibyte: Fix bus watcher build for BCM1x55 and BCM1x80. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CC arch/mips/sibyte/bcm1480/bus_watcher.o CHK kernel/config_data.h arch/mips/sibyte/bcm1480/bus_watcher.c: In function ‘check_bus_watcher’: arch/mips/sibyte/bcm1480/bus_watcher.c:86:82: error: ‘A_SCD_BUS_ERR_STATUS_DEBUG’ undeclared (first use in this function) arch/mips/sibyte/bcm1480/bus_watcher.c:86:82: note: each undeclared identifier is reported only once for each function it appears in make[3]: *** [arch/mips/sibyte/bcm1480/bus_watcher.o] Error 1 make[2]: *** [arch/mips/sibyte/bcm1480] Error 2 make[1]: *** [arch/mips/sibyte] Error 2 make: *** [arch/mips] Error 2 The register moved around though it's otherwise the same but because of the changed address it now also has a different name. Signed-off-by: Ralf Baechle Patchwork: https://patchwork.linux-mips.org/patch/5514/ Reported-by: Markos Chandras diff --git a/arch/mips/sibyte/common/Makefile b/arch/mips/sibyte/common/Makefile index 36aa700..b3d6bf2 100644 --- a/arch/mips/sibyte/common/Makefile +++ b/arch/mips/sibyte/common/Makefile @@ -1,3 +1,4 @@ obj-y := cfe.o +obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o obj-$(CONFIG_SIBYTE_CFE_CONSOLE) += cfe_console.o obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o diff --git a/arch/mips/sibyte/common/bus_watcher.c b/arch/mips/sibyte/common/bus_watcher.c new file mode 100644 index 0000000..5581844 --- /dev/null +++ b/arch/mips/sibyte/common/bus_watcher.c @@ -0,0 +1,256 @@ +/* + * Copyright (C) 2002,2003 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * The Bus Watcher monitors internal bus transactions and maintains + * counts of transactions with error status, logging details and + * causing one of several interrupts. This driver provides a handler + * for those interrupts which aggregates the counts (to avoid + * saturating the 8-bit counters) and provides a presence in + * /proc/bus_watcher if PROC_FS is on. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +#include +#endif + + +struct bw_stats_struct { + uint64_t status; + uint32_t l2_err; + uint32_t memio_err; + int status_printed; + unsigned long l2_cor_d; + unsigned long l2_bad_d; + unsigned long l2_cor_t; + unsigned long l2_bad_t; + unsigned long mem_cor_d; + unsigned long mem_bad_d; + unsigned long bus_error; +} bw_stats; + + +static void print_summary(uint32_t status, uint32_t l2_err, + uint32_t memio_err) +{ + printk("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); + printk("\nLast recorded signature:\n"); + printk("Request %02x from %d, answered by %d with Dcode %d\n", + (unsigned int)(G_SCD_BERR_TID(status) & 0x3f), + (int)(G_SCD_BERR_TID(status) >> 6), + (int)G_SCD_BERR_RID(status), + (int)G_SCD_BERR_DCODE(status)); +} + +/* + * check_bus_watcher is exported for use in situations where we want + * to see the most recent status of the bus watcher, which might have + * already been destructively read out of the registers. + * + * notes: this is currently used by the cache error handler + * should provide locking against the interrupt handler + */ +void check_bus_watcher(void) +{ + u32 status, l2_err, memio_err; + +#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS + /* Destructive read, clears register and interrupt */ + status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); +#elif defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250) + /* Use non-destructive register */ + status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG)); +#elif defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) + /* Use non-destructive register */ + /* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */ + status = csr_in32(IOADDR(A_BCM1480_BUS_ERR_STATUS_DEBUG)); +#else +#error bus watcher being built for unknown Sibyte SOC! +#endif + if (!(status & 0x7fffffff)) { + printk("Using last values reaped by bus watcher driver\n"); + status = bw_stats.status; + l2_err = bw_stats.l2_err; + memio_err = bw_stats.memio_err; + } else { + l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); + memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); + } + if (status & ~(1UL << 31)) + print_summary(status, l2_err, memio_err); + else + printk("Bus watcher indicates no error\n"); +} + +#ifdef CONFIG_PROC_FS + +/* For simplicity, I want to assume a single read is required each + time */ +static int bw_proc_show(struct seq_file *m, void *v) +{ + struct bw_stats_struct *stats = m->private; + + seq_puts(m, "SiByte Bus Watcher statistics\n"); + seq_puts(m, "-----------------------------\n"); + seq_printf(m, "L2-d-cor %8ld\nL2-d-bad %8ld\n", + stats->l2_cor_d, stats->l2_bad_d); + seq_printf(m, "L2-t-cor %8ld\nL2-t-bad %8ld\n", + stats->l2_cor_t, stats->l2_bad_t); + seq_printf(m, "MC-d-cor %8ld\nMC-d-bad %8ld\n", + stats->mem_cor_d, stats->mem_bad_d); + seq_printf(m, "IO-err %8ld\n", stats->bus_error); + seq_puts(m, "\nLast recorded signature:\n"); + seq_printf(m, "Request %02x from %d, answered by %d with Dcode %d\n", + (unsigned int)(G_SCD_BERR_TID(stats->status) & 0x3f), + (int)(G_SCD_BERR_TID(stats->status) >> 6), + (int)G_SCD_BERR_RID(stats->status), + (int)G_SCD_BERR_DCODE(stats->status)); + /* XXXKW indicate multiple errors between printings, or stats + collection (or both)? */ + if (stats->status & M_SCD_BERR_MULTERRS) + seq_puts(m, "Multiple errors observed since last check.\n"); + if (stats->status_printed) { + seq_puts(m, "(no change since last printing)\n"); + } else { + stats->status_printed = 1; + } + + return 0; +} + +static int bw_proc_open(struct inode *inode, struct file *file) +{ + return single_open(file, bw_proc_show, PDE_DATA(inode)); +} + +static const struct file_operations bw_proc_fops = { + .open = bw_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static void create_proc_decoder(struct bw_stats_struct *stats) +{ + struct proc_dir_entry *ent; + + ent = proc_create_data("bus_watcher", S_IWUSR | S_IRUGO, NULL, + &bw_proc_fops, stats); + if (!ent) { + printk(KERN_INFO "Unable to initialize bus_watcher /proc entry\n"); + return; + } +} + +#endif /* CONFIG_PROC_FS */ + +/* + * sibyte_bw_int - handle bus watcher interrupts and accumulate counts + * + * notes: possible re-entry due to multiple sources + * should check/indicate saturation + */ +static irqreturn_t sibyte_bw_int(int irq, void *data) +{ + struct bw_stats_struct *stats = data; + unsigned long cntr; +#ifdef CONFIG_SIBYTE_BW_TRACE + int i; +#endif + +#ifdef CONFIG_SIBYTE_BW_TRACE + csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); + csr_out32(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG)); + + for (i=0; i<256*6; i++) + printk("%016llx\n", + (long long)__raw_readq(IOADDR(A_SCD_TRACE_READ))); + + csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); + csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG)); +#endif + + /* Destructive read, clears register and interrupt */ + stats->status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); + stats->status_printed = 0; + + stats->l2_err = cntr = csr_in32(IOADDR(A_BUS_L2_ERRORS)); + stats->l2_cor_d += G_SCD_L2ECC_CORR_D(cntr); + stats->l2_bad_d += G_SCD_L2ECC_BAD_D(cntr); + stats->l2_cor_t += G_SCD_L2ECC_CORR_T(cntr); + stats->l2_bad_t += G_SCD_L2ECC_BAD_T(cntr); + csr_out32(0, IOADDR(A_BUS_L2_ERRORS)); + + stats->memio_err = cntr = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); + stats->mem_cor_d += G_SCD_MEM_ECC_CORR(cntr); + stats->mem_bad_d += G_SCD_MEM_ECC_BAD(cntr); + stats->bus_error += G_SCD_MEM_BUSERR(cntr); + csr_out32(0, IOADDR(A_BUS_MEM_IO_ERRORS)); + + return IRQ_HANDLED; +} + +int __init sibyte_bus_watcher(void) +{ + memset(&bw_stats, 0, sizeof(struct bw_stats_struct)); + bw_stats.status_printed = 1; + + if (request_irq(K_INT_BAD_ECC, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) { + printk("Failed to register bus watcher BAD_ECC irq\n"); + return -1; + } + if (request_irq(K_INT_COR_ECC, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) { + free_irq(K_INT_BAD_ECC, &bw_stats); + printk("Failed to register bus watcher COR_ECC irq\n"); + return -1; + } + if (request_irq(K_INT_IO_BUS, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) { + free_irq(K_INT_BAD_ECC, &bw_stats); + free_irq(K_INT_COR_ECC, &bw_stats); + printk("Failed to register bus watcher IO_BUS irq\n"); + return -1; + } + +#ifdef CONFIG_PROC_FS + create_proc_decoder(&bw_stats); +#endif + +#ifdef CONFIG_SIBYTE_BW_TRACE + csr_out32((M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE | + K_SCD_TRSEQ_TRIGGER_ALL), + IOADDR(A_SCD_TRACE_SEQUENCE_0)); + csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); + csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG)); +#endif + + return 0; +} + +__initcall(sibyte_bus_watcher); diff --git a/arch/mips/sibyte/sb1250/Makefile b/arch/mips/sibyte/sb1250/Makefile index d3d969d..cdc4c56 100644 --- a/arch/mips/sibyte/sb1250/Makefile +++ b/arch/mips/sibyte/sb1250/Makefile @@ -1,4 +1,3 @@ obj-y := setup.o irq.o time.o obj-$(CONFIG_SMP) += smp.o -obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c deleted file mode 100644 index d0ca7b9..0000000 --- a/arch/mips/sibyte/sb1250/bus_watcher.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Copyright (C) 2002,2003 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -/* - * The Bus Watcher monitors internal bus transactions and maintains - * counts of transactions with error status, logging details and - * causing one of several interrupts. This driver provides a handler - * for those interrupts which aggregates the counts (to avoid - * saturating the 8-bit counters) and provides a presence in - * /proc/bus_watcher if PROC_FS is on. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - - -struct bw_stats_struct { - uint64_t status; - uint32_t l2_err; - uint32_t memio_err; - int status_printed; - unsigned long l2_cor_d; - unsigned long l2_bad_d; - unsigned long l2_cor_t; - unsigned long l2_bad_t; - unsigned long mem_cor_d; - unsigned long mem_bad_d; - unsigned long bus_error; -} bw_stats; - - -static void print_summary(uint32_t status, uint32_t l2_err, - uint32_t memio_err) -{ - printk("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); - printk("\nLast recorded signature:\n"); - printk("Request %02x from %d, answered by %d with Dcode %d\n", - (unsigned int)(G_SCD_BERR_TID(status) & 0x3f), - (int)(G_SCD_BERR_TID(status) >> 6), - (int)G_SCD_BERR_RID(status), - (int)G_SCD_BERR_DCODE(status)); -} - -/* - * check_bus_watcher is exported for use in situations where we want - * to see the most recent status of the bus watcher, which might have - * already been destructively read out of the registers. - * - * notes: this is currently used by the cache error handler - * should provide locking against the interrupt handler - */ -void check_bus_watcher(void) -{ - u32 status, l2_err, memio_err; - -#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS - /* Destructive read, clears register and interrupt */ - status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); -#else - /* Use non-destructive register */ - status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG)); -#endif - if (!(status & 0x7fffffff)) { - printk("Using last values reaped by bus watcher driver\n"); - status = bw_stats.status; - l2_err = bw_stats.l2_err; - memio_err = bw_stats.memio_err; - } else { - l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); - memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); - } - if (status & ~(1UL << 31)) - print_summary(status, l2_err, memio_err); - else - printk("Bus watcher indicates no error\n"); -} - -#ifdef CONFIG_PROC_FS - -/* For simplicity, I want to assume a single read is required each - time */ -static int bw_proc_show(struct seq_file *m, void *v) -{ - struct bw_stats_struct *stats = m->private; - - seq_puts(m, "SiByte Bus Watcher statistics\n"); - seq_puts(m, "-----------------------------\n"); - seq_printf(m, "L2-d-cor %8ld\nL2-d-bad %8ld\n", - stats->l2_cor_d, stats->l2_bad_d); - seq_printf(m, "L2-t-cor %8ld\nL2-t-bad %8ld\n", - stats->l2_cor_t, stats->l2_bad_t); - seq_printf(m, "MC-d-cor %8ld\nMC-d-bad %8ld\n", - stats->mem_cor_d, stats->mem_bad_d); - seq_printf(m, "IO-err %8ld\n", stats->bus_error); - seq_puts(m, "\nLast recorded signature:\n"); - seq_printf(m, "Request %02x from %d, answered by %d with Dcode %d\n", - (unsigned int)(G_SCD_BERR_TID(stats->status) & 0x3f), - (int)(G_SCD_BERR_TID(stats->status) >> 6), - (int)G_SCD_BERR_RID(stats->status), - (int)G_SCD_BERR_DCODE(stats->status)); - /* XXXKW indicate multiple errors between printings, or stats - collection (or both)? */ - if (stats->status & M_SCD_BERR_MULTERRS) - seq_puts(m, "Multiple errors observed since last check.\n"); - if (stats->status_printed) { - seq_puts(m, "(no change since last printing)\n"); - } else { - stats->status_printed = 1; - } - - return 0; -} - -static int bw_proc_open(struct inode *inode, struct file *file) -{ - return single_open(file, bw_proc_show, PDE_DATA(inode)); -} - -static const struct file_operations bw_proc_fops = { - .open = bw_proc_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static void create_proc_decoder(struct bw_stats_struct *stats) -{ - struct proc_dir_entry *ent; - - ent = proc_create_data("bus_watcher", S_IWUSR | S_IRUGO, NULL, - &bw_proc_fops, stats); - if (!ent) { - printk(KERN_INFO "Unable to initialize bus_watcher /proc entry\n"); - return; - } -} - -#endif /* CONFIG_PROC_FS */ - -/* - * sibyte_bw_int - handle bus watcher interrupts and accumulate counts - * - * notes: possible re-entry due to multiple sources - * should check/indicate saturation - */ -static irqreturn_t sibyte_bw_int(int irq, void *data) -{ - struct bw_stats_struct *stats = data; - unsigned long cntr; -#ifdef CONFIG_SIBYTE_BW_TRACE - int i; -#endif - -#ifdef CONFIG_SIBYTE_BW_TRACE - csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); - csr_out32(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG)); - - for (i=0; i<256*6; i++) - printk("%016llx\n", - (long long)__raw_readq(IOADDR(A_SCD_TRACE_READ))); - - csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); - csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG)); -#endif - - /* Destructive read, clears register and interrupt */ - stats->status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); - stats->status_printed = 0; - - stats->l2_err = cntr = csr_in32(IOADDR(A_BUS_L2_ERRORS)); - stats->l2_cor_d += G_SCD_L2ECC_CORR_D(cntr); - stats->l2_bad_d += G_SCD_L2ECC_BAD_D(cntr); - stats->l2_cor_t += G_SCD_L2ECC_CORR_T(cntr); - stats->l2_bad_t += G_SCD_L2ECC_BAD_T(cntr); - csr_out32(0, IOADDR(A_BUS_L2_ERRORS)); - - stats->memio_err = cntr = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); - stats->mem_cor_d += G_SCD_MEM_ECC_CORR(cntr); - stats->mem_bad_d += G_SCD_MEM_ECC_BAD(cntr); - stats->bus_error += G_SCD_MEM_BUSERR(cntr); - csr_out32(0, IOADDR(A_BUS_MEM_IO_ERRORS)); - - return IRQ_HANDLED; -} - -int __init sibyte_bus_watcher(void) -{ - memset(&bw_stats, 0, sizeof(struct bw_stats_struct)); - bw_stats.status_printed = 1; - - if (request_irq(K_INT_BAD_ECC, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) { - printk("Failed to register bus watcher BAD_ECC irq\n"); - return -1; - } - if (request_irq(K_INT_COR_ECC, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) { - free_irq(K_INT_BAD_ECC, &bw_stats); - printk("Failed to register bus watcher COR_ECC irq\n"); - return -1; - } - if (request_irq(K_INT_IO_BUS, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) { - free_irq(K_INT_BAD_ECC, &bw_stats); - free_irq(K_INT_COR_ECC, &bw_stats); - printk("Failed to register bus watcher IO_BUS irq\n"); - return -1; - } - -#ifdef CONFIG_PROC_FS - create_proc_decoder(&bw_stats); -#endif - -#ifdef CONFIG_SIBYTE_BW_TRACE - csr_out32((M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE | - K_SCD_TRSEQ_TRIGGER_ALL), - IOADDR(A_SCD_TRACE_SEQUENCE_0)); - csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); - csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG)); -#endif - - return 0; -} - -__initcall(sibyte_bus_watcher); -- cgit v0.10.2 From 6793f55cbc84d8520e79c67583f60058b4364daa Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Mon, 17 Jun 2013 13:00:38 +0000 Subject: MIPS: sibyte: Amend dependencies for SIBYTE_BUS_WATCHER SIBYTE_BUS_WATCHER is only visible if CONFIG_SIBYTE_BCM112X or CONFIG_SIBYTE_SB1250 is selected according to the arch/mips/sibyte/Makefile. This fixes the following build problem: arch/mips/mm/cerr-sb1.c:254: undefined reference to `check_bus_watcher' Signed-off-by: Markos Chandras Acked-by: Steven J. Hill Cc: sibyte-users@bitmover.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5482/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig index 01cc1a7..5fbd360 100644 --- a/arch/mips/sibyte/Kconfig +++ b/arch/mips/sibyte/Kconfig @@ -147,7 +147,8 @@ config SIBYTE_CFE_CONSOLE config SIBYTE_BUS_WATCHER bool "Support for Bus Watcher statistics" - depends on SIBYTE_SB1xxx_SOC + depends on SIBYTE_SB1xxx_SOC && \ + (SIBYTE_BCM112X || SIBYTE_SB1250) help Handle and keep statistics on the bus error interrupts (COR_ECC, BAD_ECC, IO_BUS). -- cgit v0.10.2 From c37441c127e000869a960a866fe2207626935e4f Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Mon, 17 Jun 2013 07:53:47 +0000 Subject: MIPS: powertv: Drop SYS_HAS_EARLY_PRINTK PowerTV does not provide a prom_putchar function needed for early printk so remove this symbol for this platform. Fixes the following problem when EARLY_PRINTK is enabled for powertv: arch/mips/kernel/early_printk.c:24: undefined reference to `prom_putchar' arch/mips/kernel/early_printk.c:23: undefined reference to `prom_putchar' Signed-off-by: Markos Chandras Acked-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5477/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 49f98bf..cd8fed8 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -419,7 +419,6 @@ config POWERTV select CSRC_POWERTV select DMA_NONCOHERENT select HW_HAS_PCI - select SYS_HAS_EARLY_PRINTK select SYS_HAS_CPU_MIPS32_R2 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN -- cgit v0.10.2 From c5e1503fd0428ed3a2e5e48734f47c9f4dfe5a3d Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 15 Jun 2013 15:34:40 +0000 Subject: MIPS: Fix execution hazard during watchpoint register probe Writing a value to a WatchLo* register creates an execution hazard, so if its value is then read before that hazard is cleared then said value may be invalid. The mips_probe_watch_registers function must therefore clear the execution hazard between setting the match bits in a WatchLo* register & reading the register back in order to check which are set. This fixes intermittent incorrect watchpoint register probing on some MIPS cores such as interAptiv & proAptiv. Signed-off-by: Paul Burton Reviewed-by: James Hogan Acked-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/5474/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/watch.c b/arch/mips/kernel/watch.c index 7726f61..cbdc4de 100644 --- a/arch/mips/kernel/watch.c +++ b/arch/mips/kernel/watch.c @@ -111,6 +111,7 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c) * disable the register. */ write_c0_watchlo0(7); + back_to_back_c0_hazard(); t = read_c0_watchlo0(); write_c0_watchlo0(0); c->watch_reg_masks[0] = t & 7; @@ -121,12 +122,14 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c) c->watch_reg_use_cnt = 1; t = read_c0_watchhi0(); write_c0_watchhi0(t | 0xff8); + back_to_back_c0_hazard(); t = read_c0_watchhi0(); c->watch_reg_masks[0] |= (t & 0xff8); if ((t & 0x80000000) == 0) return; write_c0_watchlo1(7); + back_to_back_c0_hazard(); t = read_c0_watchlo1(); write_c0_watchlo1(0); c->watch_reg_masks[1] = t & 7; @@ -135,12 +138,14 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c) c->watch_reg_use_cnt = 2; t = read_c0_watchhi1(); write_c0_watchhi1(t | 0xff8); + back_to_back_c0_hazard(); t = read_c0_watchhi1(); c->watch_reg_masks[1] |= (t & 0xff8); if ((t & 0x80000000) == 0) return; write_c0_watchlo2(7); + back_to_back_c0_hazard(); t = read_c0_watchlo2(); write_c0_watchlo2(0); c->watch_reg_masks[2] = t & 7; @@ -149,12 +154,14 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c) c->watch_reg_use_cnt = 3; t = read_c0_watchhi2(); write_c0_watchhi2(t | 0xff8); + back_to_back_c0_hazard(); t = read_c0_watchhi2(); c->watch_reg_masks[2] |= (t & 0xff8); if ((t & 0x80000000) == 0) return; write_c0_watchlo3(7); + back_to_back_c0_hazard(); t = read_c0_watchlo3(); write_c0_watchlo3(0); c->watch_reg_masks[3] = t & 7; @@ -163,6 +170,7 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c) c->watch_reg_use_cnt = 4; t = read_c0_watchhi3(); write_c0_watchhi3(t | 0xff8); + back_to_back_c0_hazard(); t = read_c0_watchhi3(); c->watch_reg_masks[3] |= (t & 0xff8); if ((t & 0x80000000) == 0) -- cgit v0.10.2 From 318883517ebc56e1f9068597e9875f578016e225 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 18 Jun 2013 16:55:38 +0000 Subject: MIPS: BCM63XX: remove bogus Kconfig selects Remove the bogus selects on USB-related symbols for 6345 and 6338, not only we do not yet support USB on BCM63XX, but they also cause the following warnings: warning: (BCM63XX_CPU_6338 && BCM63XX_CPU_6345) selects USB_OHCI_BIG_ENDIAN_MMIO which has unmet direct dependencies (USB_SUPPORT && USB && USB_OHCI_HCD) warning: (BCM63XX_CPU_6338 && BCM63XX_CPU_6345) selects USB_OHCI_BIG_ENDIAN_DESC which has unmet direct dependencies (USB_SUPPORT && USB && USB_OHCI_HCD) make[4]: Leaving directory `/home/florian/dev/linux' Just get rid of these bogus Kconfig selects because neither 6345 nor 6338 actually have built-in USB host controllers. Signed-off-by: Florian Fainelli Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: http://patchwork.linux-mips.org/patch/5497/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig index 5639662..165727d 100644 --- a/arch/mips/bcm63xx/Kconfig +++ b/arch/mips/bcm63xx/Kconfig @@ -8,14 +8,9 @@ config BCM63XX_CPU_6328 config BCM63XX_CPU_6338 bool "support 6338 CPU" select HW_HAS_PCI - select USB_ARCH_HAS_OHCI - select USB_OHCI_BIG_ENDIAN_DESC - select USB_OHCI_BIG_ENDIAN_MMIO config BCM63XX_CPU_6345 bool "support 6345 CPU" - select USB_OHCI_BIG_ENDIAN_DESC - select USB_OHCI_BIG_ENDIAN_MMIO config BCM63XX_CPU_6348 bool "support 6348 CPU" -- cgit v0.10.2 From cd6cbde6b01b6e82662cad392c0d177b4af17443 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 19 Jun 2013 10:57:33 +0200 Subject: WATCHDOG: sb_wdog: Fix 32 bit build failure Fixes the following linking problem: drivers/watchdog/sb_wdog.c:211: undefined reference to `__udivdi3' This results from reading a 64 bit register, then dividing the value by 1000000. For 32 bit kernels gcc will use the helper function __udivdi3 from libgcc which the kernel intentionally doesn't provide. In the read registerbits 23..63 are always zero and only bits 0..22 are signficant. So a simple cast to truncate the read value to 32 bits fixes the issue. Reported and initial patch by Markos Chandras . Signed-off-by: Ralf Baechle Reported-by: Markos Chandras diff --git a/drivers/watchdog/sb_wdog.c b/drivers/watchdog/sb_wdog.c index 25c7a3f..ea5d84a 100644 --- a/drivers/watchdog/sb_wdog.c +++ b/drivers/watchdog/sb_wdog.c @@ -208,7 +208,7 @@ static long sbwdog_ioctl(struct file *file, unsigned int cmd, * get the remaining count from the ... count register * which is 1*8 before the config register */ - ret = put_user(__raw_readq(user_dog - 8) / 1000000, p); + ret = put_user((u32)__raw_readq(user_dog - 8) / 1000000, p); break; } return ret; -- cgit v0.10.2 From b90b3802624e1f2a509f3e9f39775d94ec4762d7 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 7 May 2013 14:10:24 +0200 Subject: MIPS: Fix rtlx build error. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CC arch/mips/kernel/rtlx.o /home/ralf/src/linux/upstream-sfr/arch/mips/kernel/rtlx.c: In function ‘file_write’: /home/ralf/src/linux/upstream-sfr/arch/mips/kernel/rtlx.c:439:23: error: unused variable ‘rt’ [-Werror=unused-variable] /home/ralf/src/linux/upstream-sfr/arch/mips/kernel/rtlx.c: In function ‘rtlx_module_init’: /home/ralf/src/linux/upstream-sfr/arch/mips/kernel/rtlx.c:523:3: error: implicit declaration of function ‘set_vi_handler’ [-Werror=implicit-function-declaration] cc1: all warnings being treated as errors Caused by 496ad9aa8ef448058e36ca7a787c61f2e63f0f54 [new helper: file_inode(file)]. Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index 6fa198d..d763f11 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -437,7 +437,6 @@ static ssize_t file_write(struct file *file, const char __user * buffer, size_t count, loff_t * ppos) { int minor = iminor(file_inode(file)); - struct rtlx_channel *rt = &rtlx->channel[minor]; /* any space left... */ if (!rtlx_write_poll(minor)) { -- cgit v0.10.2 From 73acc7df534ff458a81435178dab3ea037ed6d78 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 20 Jun 2013 14:56:17 +0200 Subject: MIPS: Fix TLBR-use hazards for R2 cores in the TLB reload handlers MIPS R2 documents state that an execution hazard barrier is needed after a TLBR before reading EntryLo. Original patch by Leonid Yegoshin . Signed-off-by: Ralf Baechle Patchwork: https://patchwork.linux-mips.org/patch/5526/ diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index afeef93..f0f4dc4 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -1935,6 +1935,19 @@ static void __cpuinit build_r4000_tlb_load_handler(void) uasm_i_nop(&p); uasm_i_tlbr(&p); + + switch (current_cpu_type()) { + default: + if (cpu_has_mips_r2) { + uasm_i_ehb(&p); + + case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: + case CPU_CAVIUM_OCTEON2: + break; + } + } + /* Examine entrylo 0 or 1 based on ptr. */ if (use_bbit_insns()) { uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); @@ -1989,6 +2002,19 @@ static void __cpuinit build_r4000_tlb_load_handler(void) uasm_i_nop(&p); uasm_i_tlbr(&p); + + switch (current_cpu_type()) { + default: + if (cpu_has_mips_r2) { + uasm_i_ehb(&p); + + case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: + case CPU_CAVIUM_OCTEON2: + break; + } + } + /* Examine entrylo 0 or 1 based on ptr. */ if (use_bbit_insns()) { uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); -- cgit v0.10.2 From dfb033f09e2a98a89b7a09f7e913f0b791dd01e1 Mon Sep 17 00:00:00 2001 From: Tony Wu Date: Thu, 20 Jun 2013 12:32:30 +0000 Subject: MIPS: microMIPS: Fix POOL16C minor opcode enum As pointed out by Maciej, POOL16C minor opcodes were mostly shifted by one bit. Correct those opcodes, and also add jraddiusp to the enum. Signed-off-by: Tony Wu Cc: Maciej W. Rozycki Acked-by: Steven J. Hill Cc: david.daney@cavium.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5527/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h index 0f4aec2..e5a676e 100644 --- a/arch/mips/include/uapi/asm/inst.h +++ b/arch/mips/include/uapi/asm/inst.h @@ -409,10 +409,11 @@ enum mm_32f_73_minor_op { enum mm_16c_minor_op { mm_lwm16_op = 0x04, mm_swm16_op = 0x05, - mm_jr16_op = 0x18, - mm_jrc_op = 0x1a, - mm_jalr16_op = 0x1c, - mm_jalrs16_op = 0x1e, + mm_jr16_op = 0x0c, + mm_jrc_op = 0x0d, + mm_jalr16_op = 0x0e, + mm_jalrs16_op = 0x0f, + mm_jraddiusp_op = 0x18, }; /* -- cgit v0.10.2 From 0be0aea2ffa2be1590c86dc226291939bd5535b0 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Tue, 25 Jun 2013 10:29:27 +0000 Subject: MIPS: Sibyte: Platform: Add load address for CONFIG_SIBYTE_LITTLESUR Fixes the following build problem: mips-linux-gnu-ld:arch/mips/kernel/vmlinux.lds:253: syntax error because VMLINUX_LOAD_ADDRESS was an empty string for that platform so the vmlinux.lds.S created an invalid section entry on line 50. Signed-off-by: Markos Chandras Acked-by: Steven J. Hill Cc: sibyte-users@bitmover.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5548/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/sibyte/Platform b/arch/mips/sibyte/Platform index d03a075..1bf90dc 100644 --- a/arch/mips/sibyte/Platform +++ b/arch/mips/sibyte/Platform @@ -41,3 +41,4 @@ load-$(CONFIG_SIBYTE_RHONE) := 0xffffffff80100000 load-$(CONFIG_SIBYTE_SENTOSA) := 0xffffffff80100000 load-$(CONFIG_SIBYTE_SWARM) := 0xffffffff80100000 load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000 +load-$(CONFIG_SIBYTE_LITTLESUR) := 0xffffffff80100000 -- cgit v0.10.2 From 5bd807659bfd5d5a393b2269dc3e9699dddd9ad6 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Mon, 24 Jun 2013 14:42:21 +0000 Subject: MIPS: SNI: pcimt: Guard sni_controller with CONFIG_PCI Fixes the following build problem: arch/mips/sni/pcimt.c:188:30: error: 'sni_controller' defined but not used [-Werror=unused-variable] Signed-off-by: Markos Chandras Acked-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5547/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c index cec4b8c..12336c2 100644 --- a/arch/mips/sni/pcimt.c +++ b/arch/mips/sni/pcimt.c @@ -185,6 +185,7 @@ static void __init sni_pcimt_resource_init(void) extern struct pci_ops sni_pcimt_ops; +#ifdef CONFIG_PCI static struct pci_controller sni_controller = { .pci_ops = &sni_pcimt_ops, .mem_resource = &sni_mem_resource, @@ -193,6 +194,7 @@ static struct pci_controller sni_controller = { .io_offset = 0x00000000UL, .io_map_base = SNI_PORT_BASE }; +#endif static void enable_pcimt_irq(struct irq_data *d) { -- cgit v0.10.2 From 6a72015d3c3602dd969e79510486807c481a0e1b Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 25 Jun 2013 17:10:28 +0200 Subject: MIPS: SNI: pcit: Fix build error with CONFIG_PCI=n disabled. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CC arch/mips/sni/pcit.o arch/mips/sni/pcit.c:150:30: warning: ‘sni_pcit_controller’ defined but not used [-Wunused-variable] Signed-off-by: Ralf Baechle diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c index 7cddd03..05bb516 100644 --- a/arch/mips/sni/pcit.c +++ b/arch/mips/sni/pcit.c @@ -128,13 +128,6 @@ static struct resource pcit_io_resources[] = { } }; -static struct resource sni_mem_resource = { - .start = 0x18000000UL, - .end = 0x1fbfffffUL, - .name = "PCIT PCI MEM", - .flags = IORESOURCE_MEM -}; - static void __init sni_pcit_resource_init(void) { int i; @@ -147,6 +140,14 @@ static void __init sni_pcit_resource_init(void) extern struct pci_ops sni_pcit_ops; +#ifdef CONFIG_PCI +static struct resource sni_mem_resource = { + .start = 0x18000000UL, + .end = 0x1fbfffffUL, + .name = "PCIT PCI MEM", + .flags = IORESOURCE_MEM +}; + static struct pci_controller sni_pcit_controller = { .pci_ops = &sni_pcit_ops, .mem_resource = &sni_mem_resource, @@ -155,6 +156,7 @@ static struct pci_controller sni_pcit_controller = { .io_offset = 0x00000000UL, .io_map_base = SNI_PORT_BASE }; +#endif /* CONFIG_PCI */ static void enable_pcit_irq(struct irq_data *d) { -- cgit v0.10.2 From a3d9086bb121a6459c9ed0452e3c58891a504785 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Fri, 21 Jun 2013 17:48:48 +0000 Subject: MIPS: Flush TLB handlers directly after writing them When having enabled MIPS_PGD_C0_CONTEXT, trap_init() might call the generated tlbmiss_handler_setup_pgd before it was committed to memory, causing boot failures: trap_init() |- per_cpu_trap_init() | |- TLBMISS_HANDLER_SETUP() | |- tlbmiss_handler_setup_pgd() |- flush_tlb_handlers() To avoid this, move flush_tlb_handlers() into build_tlb_refill_handler() right after they were generated. We can do this as the cache handling is initialized just before creating the tlb handlers. This issue was introduced in 3d8bfdd0307223de678962f1c1907a7cec549136 ("MIPS: Use C0_KScratch (if present) to hold PGD pointer."). Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: Steven J. Hill Cc: Jayachandran C Cc: David Daney Patchwork: https://patchwork.linux-mips.org/patch/5539/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index a75ae40..8ef484c 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1627,7 +1627,6 @@ void *set_vi_handler(int n, vi_handler_t addr) } extern void tlb_init(void); -extern void flush_tlb_handlers(void); /* * Timer interrupt @@ -1956,7 +1955,6 @@ void __init trap_init(void) set_handler(0x080, &except_vec3_generic, 0x80); local_flush_icache_range(ebase, ebase + 0x400); - flush_tlb_handlers(); sort_extable(__start___dbe_table, __stop___dbe_table); diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index f0f4dc4..7f6cd46 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -2181,6 +2181,20 @@ static void __cpuinit build_r4000_tlb_modify_handler(void) dump_handler("r4000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm)); } +static void __cpuinit flush_tlb_handlers(void) +{ + local_flush_icache_range((unsigned long)handle_tlbl, + (unsigned long)handle_tlbl + sizeof(handle_tlbl)); + local_flush_icache_range((unsigned long)handle_tlbs, + (unsigned long)handle_tlbs + sizeof(handle_tlbs)); + local_flush_icache_range((unsigned long)handle_tlbm, + (unsigned long)handle_tlbm + sizeof(handle_tlbm)); +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT + local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd_array, + (unsigned long)tlbmiss_handler_setup_pgd_array + sizeof(handle_tlbm)); +#endif +} + void __cpuinit build_tlb_refill_handler(void) { /* @@ -2213,6 +2227,7 @@ void __cpuinit build_tlb_refill_handler(void) build_r3000_tlb_load_handler(); build_r3000_tlb_store_handler(); build_r3000_tlb_modify_handler(); + flush_tlb_handlers(); run_once++; } #else @@ -2240,23 +2255,10 @@ void __cpuinit build_tlb_refill_handler(void) build_r4000_tlb_modify_handler(); if (!cpu_has_local_ebase) build_r4000_tlb_refill_handler(); + flush_tlb_handlers(); run_once++; } if (cpu_has_local_ebase) build_r4000_tlb_refill_handler(); } } - -void __cpuinit flush_tlb_handlers(void) -{ - local_flush_icache_range((unsigned long)handle_tlbl, - (unsigned long)handle_tlbl + sizeof(handle_tlbl)); - local_flush_icache_range((unsigned long)handle_tlbs, - (unsigned long)handle_tlbs + sizeof(handle_tlbs)); - local_flush_icache_range((unsigned long)handle_tlbm, - (unsigned long)handle_tlbm + sizeof(handle_tlbm)); -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT - local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd_array, - (unsigned long)tlbmiss_handler_setup_pgd_array + sizeof(handle_tlbm)); -#endif -} -- cgit v0.10.2 From 3f90b82df110ef9cb33761b56ca85ae0d0372d4a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 27 Jun 2013 02:04:25 +0200 Subject: MIPS: tlbex: Fix size of area to be flushed. Signed-off-by: Ralf Baechle diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 7f6cd46..2f88fd3 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -2191,7 +2191,7 @@ static void __cpuinit flush_tlb_handlers(void) (unsigned long)handle_tlbm + sizeof(handle_tlbm)); #ifdef CONFIG_MIPS_PGD_C0_CONTEXT local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd_array, - (unsigned long)tlbmiss_handler_setup_pgd_array + sizeof(handle_tlbm)); + (unsigned long)tlbmiss_handler_setup_pgd_array + sizeof(tlbmiss_handler_setup_pgd_array)); #endif } -- cgit v0.10.2 From 23df34155b29674465813b327647cd79722aa659 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Mon, 1 Jul 2013 09:38:30 +0000 Subject: MIPS: Boot: Compressed: Remove -fstack-protector from CFLAGS When building with -fstack-protector, gcc emits the __stack_chk_guard and __stack_chk_fail symbols to check for stack stability. These symbols are defined in vmlinux but the generated vmlinux.bin that is used to create the compressed vmlinuz image has no symbol table so the linker can't find these symbols during the final linking phase. As a result of which, we need either to redefine these symbols just for the compressed image or drop the -fstack-protector option when building the compressed image. This patch implements the latter of two options. Fixes the following linking problem: dbg.c:(.text+0x7c): undefined reference to `__stack_chk_guard' dbg.c:(.text+0x80): undefined reference to `__stack_chk_guard' dbg.c:(.text+0xd4): undefined reference to `__stack_chk_guard' dbg.c:(.text+0xec): undefined reference to `__stack_chk_fail' [ralf@linux-mips.org: I'm applying this before the patch that actually adds stack protector support for MIPS. This means, it will not be possible to trigger above error message with any commit from the tree but rather they are what one would hit without this commit.] Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Cc: Markos Chandras Patchwork: https://patchwork.linux-mips.org/patch/5575/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile index bbaa1d4..bb1dbf4 100644 --- a/arch/mips/boot/compressed/Makefile +++ b/arch/mips/boot/compressed/Makefile @@ -18,6 +18,8 @@ BOOT_HEAP_SIZE := 0x400000 # Disable Function Tracer KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) | sed -e "s/-pg//") +KBUILD_CFLAGS := $(filter-out -fstack-protector, $(KBUILD_CFLAGS)) + KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \ -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull" -- cgit v0.10.2 From 36ecafc5ad17861e2bc1fb12af4cc97680e25942 Mon Sep 17 00:00:00 2001 From: Gregory Fong Date: Wed, 12 Jun 2013 17:08:54 +0000 Subject: MIPS: initial stack protector support Implements basic stack protector support based on ARM version in c743f38013aeff58ef6252601e397b5ba281c633 , with Kconfig option, constant canary value set at boot time, and script to check if compiler actually supports stack protector. Tested by creating a kernel module that writes past end of char[]. Signed-off-by: Gregory Fong Cc: linux-mips@linux-mips.org Cc: Filippo Arcidiacono Cc: Carmelo Amoroso Patchwork: https://patchwork.linux-mips.org/patch/5448/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 69bf310..6dbeb27 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2367,6 +2367,19 @@ config SECCOMP If unsure, say Y. Only embedded should say N here. +config CC_STACKPROTECTOR + bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" + help + This option turns on the -fstack-protector GCC feature. This + feature puts, at the beginning of functions, a canary value on + the stack just before the return address, and validates + the value just before actually returning. Stack based buffer + overflows (that need to overwrite this return address) now also + overwrite the canary, which gets detected and the attack is then + neutralized via a kernel panic. + + This feature requires gcc version 4.2 or above. + config USE_OF bool select OF diff --git a/arch/mips/Makefile b/arch/mips/Makefile index dd58a04..37f9ef3 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -227,6 +227,10 @@ KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0) LDFLAGS += -m $(ld-emul) +ifdef CONFIG_CC_STACKPROTECTOR + KBUILD_CFLAGS += -fstack-protector +endif + ifdef CONFIG_MIPS CHECKFLAGS += $(shell $(CC) $(KBUILD_CFLAGS) -dM -E -x c /dev/null | \ egrep -vw '__GNUC_(|MINOR_|PATCHLEVEL_)_' | \ diff --git a/arch/mips/include/asm/stackprotector.h b/arch/mips/include/asm/stackprotector.h new file mode 100644 index 0000000..eb9b103 --- /dev/null +++ b/arch/mips/include/asm/stackprotector.h @@ -0,0 +1,40 @@ +/* + * GCC stack protector support. + * + * (This is directly adopted from the ARM implementation) + * + * Stack protector works by putting predefined pattern at the start of + * the stack frame and verifying that it hasn't been overwritten when + * returning from the function. The pattern is called stack canary + * and gcc expects it to be defined by a global variable called + * "__stack_chk_guard" on MIPS. This unfortunately means that on SMP + * we cannot have a different canary value per task. + */ + +#ifndef _ASM_STACKPROTECTOR_H +#define _ASM_STACKPROTECTOR_H 1 + +#include +#include + +extern unsigned long __stack_chk_guard; + +/* + * Initialize the stackprotector canary value. + * + * NOTE: this must only be called from functions that never return, + * and it must always be inlined. + */ +static __always_inline void boot_init_stack_canary(void) +{ + unsigned long canary; + + /* Try to get a semi random initial value. */ + get_random_bytes(&canary, sizeof(canary)); + canary ^= LINUX_VERSION_CODE; + + current->stack_canary = canary; + __stack_chk_guard = current->stack_canary; +} + +#endif /* _ASM_STACKPROTECTOR_H */ diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index c6a041d..7d62894 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -201,6 +201,12 @@ int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpr) return 1; } +#ifdef CONFIG_CC_STACKPROTECTOR +#include +unsigned long __stack_chk_guard __read_mostly; +EXPORT_SYMBOL(__stack_chk_guard); +#endif + /* * */ -- cgit v0.10.2 From 1400eb656760d14274ed08e45824ccbcc366585b Mon Sep 17 00:00:00 2001 From: Gregory Fong Date: Mon, 17 Jun 2013 19:36:07 +0000 Subject: MIPS: r4k,octeon,r2300: stack protector: change canary per task For non-SMP, uses the new random canary value that is stored in the task struct whenever a new task is forked. Based on ARM version in df0698be14c6683606d5df2d83e3ae40f85ed0d9 and subject to the same limitations: the variable GCC expects, __stack_chk_guard, is global, so this will not work on SMP. Quoting Nicolas Pitre : "One way to overcome this GCC limitation would be to locate the __stack_chk_guard variable into a memory page of its own for each CPU, and then use TLB locking to have each CPU see its own page at the same virtual address for each of them." Signed-off-by: Gregory Fong Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5488/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index 0845091..0c2e853 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -82,6 +82,9 @@ void output_task_defines(void) OFFSET(TASK_FLAGS, task_struct, flags); OFFSET(TASK_MM, task_struct, mm); OFFSET(TASK_PID, task_struct, pid); +#if defined(CONFIG_CC_STACKPROTECTOR) + OFFSET(TASK_STACK_CANARY, task_struct, stack_canary); +#endif DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct)); BLANK(); } diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S index 22e2aa1..4204d76 100644 --- a/arch/mips/kernel/octeon_switch.S +++ b/arch/mips/kernel/octeon_switch.S @@ -71,6 +71,13 @@ mtc0 t0, $11,7 /* CvmMemCtl */ #endif 3: + +#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) + PTR_L t8, __stack_chk_guard + LONG_L t9, TASK_STACK_CANARY(a1) + LONG_S t9, 0(t8) +#endif + /* * The order of restoring the registers takes care of the race * updating $28, $29 and kernelsp without disabling ints. diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S index 5266c6e..38af83f 100644 --- a/arch/mips/kernel/r2300_switch.S +++ b/arch/mips/kernel/r2300_switch.S @@ -65,6 +65,13 @@ LEAF(resume) fpu_save_single a0, t0 # clobbers t0 1: + +#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) + PTR_L t8, __stack_chk_guard + LONG_L t9, TASK_STACK_CANARY(a1) + LONG_S t9, 0(t8) +#endif + /* * The order of restoring the registers takes care of the race * updating $28, $29 and kernelsp without disabling ints. diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index 5e51219..921238a 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -68,6 +68,12 @@ # clobbers t1 1: +#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) + PTR_L t8, __stack_chk_guard + LONG_L t9, TASK_STACK_CANARY(a1) + LONG_S t9, 0(t8) +#endif + /* * The order of restoring the registers takes care of the race * updating $28, $29 and kernelsp without disabling ints. -- cgit v0.10.2 From 937ad1042572bb3641fcbbc477f5c6b137b3a5e0 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Mon, 3 Jun 2013 14:39:34 +0000 Subject: MIPS: BCM63XX: Handle SW IRQs 0-1 MIPS software IRQs 0 and 1 are used for interprocessor signaling (IPI) on BMIPS SMP. Make the board support code aware of them. Signed-off-by: Kevin Cernekee [jogo@openwrt.org: move sw irqs behind timer irq] Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Patchwork: https://patchwork.linux-mips.org/patch/5354/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index c0ab388..d744606 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -294,6 +294,10 @@ asmlinkage void plat_irq_dispatch(void) if (cause & CAUSEF_IP7) do_IRQ(7); + if (cause & CAUSEF_IP0) + do_IRQ(0); + if (cause & CAUSEF_IP1) + do_IRQ(1); if (cause & CAUSEF_IP2) dispatch_internal(); if (!is_ext_irq_cascaded) { -- cgit v0.10.2 From d6e3469832185db579e5b38fa2e0ff1b79f43886 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Mon, 3 Jun 2013 14:39:35 +0000 Subject: MIPS: BCM63XX: select BMIPS4350 and default to 2 CPUs for supported SoCs All BCM63XX SoCs starting with BCM6358 have a BMIPS4350 instead of a BMIPS3300, so select it unless support for any of the older SoCs is selected. All BMIPS4350 have only two CPUs, so select the appropriate default. Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Patchwork: https://patchwork.linux-mips.org/patch/5355/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6dbeb27..26779cc 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -126,6 +126,8 @@ config BCM63XX select DMA_NONCOHERENT select IRQ_CPU select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348 + select NR_CPUS_DEFAULT_2 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_HAS_EARLY_PRINTK -- cgit v0.10.2 From 4b54f06522ed97e7870e7146840fc8169bbcdb48 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sat, 15 Jun 2013 10:12:46 +0000 Subject: MIPS: remove alloc_pci_controller prototype Commit 610019baddcb4c4c323c12cd44ca7f73d7145d6f ("[MIPS] Remove unused function alloc_pci_controller.") removed the function, but left the prototype in the header file. Remove it as well so people don't get tempted to use it and wonder why it doesn't work. Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5473/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index b8e24fd..fa8e0aa 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -52,7 +52,6 @@ struct pci_controller { /* * Used by boards to register their PCI busses before the actual scanning. */ -extern struct pci_controller * alloc_pci_controller(void); extern void register_pci_controller(struct pci_controller *hose); /* -- cgit v0.10.2 From a932fec84c633a5123b7d449a0588018678684cb Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 18 Jun 2013 10:40:39 +0200 Subject: MIPS: Use proper include guard symbol for . Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/uapi/asm/fcntl.h b/arch/mips/include/uapi/asm/fcntl.h index 0bda78f..07afa6f 100644 --- a/arch/mips/include/uapi/asm/fcntl.h +++ b/arch/mips/include/uapi/asm/fcntl.h @@ -5,8 +5,8 @@ * * Copyright (C) 1995, 96, 97, 98, 99, 2003, 05 Ralf Baechle */ -#ifndef _ASM_FCNTL_H -#define _ASM_FCNTL_H +#ifndef _UAPI_ASM_FCNTL_H +#define _UAPI_ASM_FCNTL_H #define O_APPEND 0x0008 @@ -74,4 +74,4 @@ struct flock { #include -#endif /* _ASM_FCNTL_H */ +#endif /* _UAPI_ASM_FCNTL_H */ -- cgit v0.10.2 From 5a772eee5544f4f84139868f7cd05806b805610d Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 18 Jun 2013 13:39:12 +0200 Subject: MIPS: fcntl.h: Use __kernel_off_t, not off_t. Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/uapi/asm/fcntl.h b/arch/mips/include/uapi/asm/fcntl.h index 07afa6f..314c79b 100644 --- a/arch/mips/include/uapi/asm/fcntl.h +++ b/arch/mips/include/uapi/asm/fcntl.h @@ -61,8 +61,8 @@ struct flock { short l_type; short l_whence; - off_t l_start; - off_t l_len; + __kernel_off_t l_start; + __kernel_off_t l_len; long l_sysid; __kernel_pid_t l_pid; long pad[4]; -- cgit v0.10.2 From 169c3c164f0dd791dfa023ab02c12cb286a72e6e Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Tue, 18 Jun 2013 17:01:10 +0000 Subject: MIPS: Delete Wind River ppmc eval board support. This board has been EOL for many years now; lets not burden people doing build coverage and other tree wide work with working on essentially dead files. [ralf@linux-mips.org: Also remove arch/mips/include/asm/mach-wrppmc/war.h.] Signed-off-by: Paul Gortmaker Cc: linux-mips@linux-mips.org Cc: Paul Gortmaker Patchwork: http://patchwork.linux-mips.org/patch/5503/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 4b597d9..d9d81c2 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -30,7 +30,6 @@ platforms += sibyte platforms += sni platforms += txx9 platforms += vr41xx -platforms += wrppmc # include the platform specific files include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms)) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 26779cc..f4cc348 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -712,29 +712,6 @@ config MIKROTIK_RB532 Support the Mikrotik(tm) RouterBoard 532 series, based on the IDT RC32434 SoC. -config WR_PPMC - bool "Wind River PPMC board" - select CEVT_R4K - select CSRC_R4K - select IRQ_CPU - select BOOT_ELF32 - select DMA_NONCOHERENT - select HW_HAS_PCI - select PCI_GT64XXX_PCI0 - select SWAP_IO_SPACE - select SYS_HAS_CPU_MIPS32_R1 - select SYS_HAS_CPU_MIPS32_R2 - select SYS_HAS_CPU_MIPS64_R1 - select SYS_HAS_CPU_NEVADA - select SYS_HAS_CPU_RM7000 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_LITTLE_ENDIAN - help - This enables support for the Wind River MIPS32 4KC PPMC evaluation - board, which is based on GT64120 bridge chip. - config CAVIUM_OCTEON_SOC bool "Cavium Networks Octeon SoC based boards" select CEVT_R4K diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig deleted file mode 100644 index 44a451b..0000000 --- a/arch/mips/configs/wrppmc_defconfig +++ /dev/null @@ -1,97 +0,0 @@ -CONFIG_WR_PPMC=y -CONFIG_HZ_1000=y -CONFIG_EXPERIMENTAL=y -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -CONFIG_KALLSYMS_EXTRA_PASS=y -# CONFIG_EPOLL is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_PCI=y -CONFIG_HOTPLUG_PCI=y -CONFIG_BINFMT_MISC=y -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_MIGRATE=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_IP_MROUTE=y -CONFIG_ARPD=y -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m -CONFIG_TCP_MD5SIG=y -# CONFIG_IPV6 is not set -CONFIG_NETWORK_SECMARK=y -CONFIG_FW_LOADER=m -CONFIG_BLK_DEV_RAM=y -CONFIG_SGI_IOC4=m -CONFIG_NETDEVICES=y -CONFIG_PHYLIB=y -CONFIG_VITESSE_PHY=m -CONFIG_SMSC_PHY=m -CONFIG_NET_ETHERNET=y -CONFIG_NET_PCI=y -CONFIG_E100=y -CONFIG_QLA3XXX=m -CONFIG_CHELSIO_T3=m -CONFIG_NETXEN_NIC=m -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -# CONFIG_HW_RANDOM is not set -CONFIG_PROC_KCORE=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_DLM=m -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="console=ttyS0,115200n8" -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -CONFIG_LIBCRC32C=y diff --git a/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h b/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h deleted file mode 100644 index 00fa368..0000000 --- a/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This is a direct copy of the ev96100.h file, with a global - * search and replace. The numbers are the same. - * - * The reason I'm duplicating this is so that the 64120/96100 - * defines won't be confusing in the source code. - */ -#ifndef __ASM_MIPS_GT64120_H -#define __ASM_MIPS_GT64120_H - -/* - * This is the CPU physical memory map of PPMC Board: - * - * 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#) - * 0x1C000000-0x1C000000 - LED (CS0) - * 0x1C800000-0x1C800007 - UART 16550 port (CS1) - * 0x1F000000-0x1F000000 - MailBox (CS3) - * 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS) - */ - -#define WRPPMC_SDRAM_SCS0_BASE 0x00000000 -#define WRPPMC_SDRAM_SCS0_SIZE 0x04000000 - -#define WRPPMC_UART16550_BASE 0x1C800000 -#define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */ - -#define WRPPMC_LED_BASE 0x1C000000 -#define WRPPMC_MBOX_BASE 0x1F000000 - -#define WRPPMC_BOOTROM_BASE 0x1FC00000 -#define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */ - -#define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */ -#define WRPPMC_UART16550_IRQ 6 -#define WRPPMC_PCI_INTA_IRQ 3 - -/* - * PCI Bus I/O and Memory resources allocation - * - * NOTE: We only have PCI_0 hose interface - */ -#define GT_PCI_MEM_BASE 0x13000000UL -#define GT_PCI_MEM_SIZE 0x02000000UL -#define GT_PCI_IO_BASE 0x11000000UL -#define GT_PCI_IO_SIZE 0x02000000UL - -/* - * PCI interrupts will come in on either the INTA or INTD interrupt lines, - * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our - * boards, they all either come in on IntD or they all come in on IntA, they - * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the - * "requested" interrupt numbers and go through the list whenever we get an - * IntA/D. - * - * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and - * INTD is 11. - */ -#define GT_TIMER 4 -#define GT_INTA 2 -#define GT_INTD 5 - -#ifndef __ASSEMBLY__ - -/* - * GT64120 internal register space base address - */ -extern unsigned long gt64120_base; - -#define GT64120_BASE (gt64120_base) - -/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */ -#undef WRPPMC_EARLY_DEBUG - -#ifdef WRPPMC_EARLY_DEBUG -extern void wrppmc_led_on(int mask); -extern void wrppmc_led_off(int mask); -extern void wrppmc_early_printk(const char *fmt, ...); -#else -#define wrppmc_early_printk(fmt, ...) do {} while (0) -#endif /* WRPPMC_EARLY_DEBUG */ - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_MIPS_GT64120_H */ diff --git a/arch/mips/include/asm/mach-wrppmc/war.h b/arch/mips/include/asm/mach-wrppmc/war.h deleted file mode 100644 index e86084c..0000000 --- a/arch/mips/include/asm/mach-wrppmc/war.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle - */ -#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H -#define __ASM_MIPS_MACH_WRPPMC_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 1 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */ diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index fa3bcd2..b56fbc0 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -52,7 +52,6 @@ obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o -obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o obj-$(CONFIG_CAVIUM_OCTEON_SOC) += pci-octeon.o pcie-octeon.o obj-$(CONFIG_CPU_XLR) += pci-xlr.o diff --git a/arch/mips/pci/fixup-wrppmc.c b/arch/mips/pci/fixup-wrppmc.c deleted file mode 100644 index 29737ed..0000000 --- a/arch/mips/pci/fixup-wrppmc.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * fixup-wrppmc.c: PPMC board specific PCI fixup - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2006, Wind River Inc. Rongkai.zhan (rongkai.zhan@windriver.com) - */ -#include -#include -#include - -/* PCI interrupt pins */ -#define PCI_INTA 1 -#define PCI_INTB 2 -#define PCI_INTC 3 -#define PCI_INTD 4 - -#define PCI_SLOT_MAXNR 32 /* Each PCI bus has 32 physical slots */ - -static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = { - /* 0 INTA INTB INTC INTD */ - [0] = {0, 0, 0, 0, 0}, /* Slot 0: GT64120 PCI bridge */ - [6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0}, -}; - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return pci_irq_tab[slot][pin]; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/wrppmc/Makefile b/arch/mips/wrppmc/Makefile deleted file mode 100644 index 307cc69..0000000 --- a/arch/mips/wrppmc/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# This file is subject to the terms and conditions of the GNU General Public -# License. See the file "COPYING" in the main directory of this archive -# for more details. -# -# Copyright 2006 Wind River System, Inc. -# Author: Rongkai.Zhan -# -# Makefile for the Wind River MIPS 4Kc PPMC Eval Board -# - -obj-y += irq.o pci.o reset.o serial.o setup.o time.o diff --git a/arch/mips/wrppmc/Platform b/arch/mips/wrppmc/Platform deleted file mode 100644 index dc78b25..0000000 --- a/arch/mips/wrppmc/Platform +++ /dev/null @@ -1,7 +0,0 @@ -# -# Wind River PPMC Board (4KC + GT64120) -# -platform-$(CONFIG_WR_PPMC) += wrppmc/ -cflags-$(CONFIG_WR_PPMC) += \ - -I$(srctree)/arch/mips/include/asm/mach-wrppmc -load-$(CONFIG_WR_PPMC) += 0xffffffff80100000 diff --git a/arch/mips/wrppmc/irq.c b/arch/mips/wrppmc/irq.c deleted file mode 100644 index f237bf4..0000000 --- a/arch/mips/wrppmc/irq.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * irq.c: GT64120 Interrupt Controller - * - * Copyright (C) 2006, Wind River System Inc. - * Author: Rongkai.Zhan, - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include - -#include -#include -#include - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; - - if (pending & STATUSF_IP7) - do_IRQ(WRPPMC_MIPS_TIMER_IRQ); /* CPU Compare/Count internal timer */ - else if (pending & STATUSF_IP6) - do_IRQ(WRPPMC_UART16550_IRQ); /* UART 16550 port */ - else if (pending & STATUSF_IP3) - do_IRQ(WRPPMC_PCI_INTA_IRQ); /* PCI INT_A */ - else - spurious_interrupt(); -} - -/** - * Initialize GT64120 Interrupt Controller - */ -void gt64120_init_pic(void) -{ - /* clear CPU Interrupt Cause Registers */ - GT_WRITE(GT_INTRCAUSE_OFS, (0x1F << 21)); - GT_WRITE(GT_HINTRCAUSE_OFS, 0x00); - - /* Disable all interrupts from GT64120 bridge chip */ - GT_WRITE(GT_INTRMASK_OFS, 0x00); - GT_WRITE(GT_HINTRMASK_OFS, 0x00); - GT_WRITE(GT_PCI0_ICMASK_OFS, 0x00); - GT_WRITE(GT_PCI0_HICMASK_OFS, 0x00); -} - -void __init arch_init_irq(void) -{ - /* IRQ 0 - 7 are for MIPS common irq_cpu controller */ - mips_cpu_irq_init(); - - gt64120_init_pic(); -} diff --git a/arch/mips/wrppmc/pci.c b/arch/mips/wrppmc/pci.c deleted file mode 100644 index 8b8a0e1..0000000 --- a/arch/mips/wrppmc/pci.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * pci.c: GT64120 PCI support. - * - * Copyright (C) 2006, Wind River System Inc. Rongkai.Zhan - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include -#include -#include -#include - -#include - -extern struct pci_ops gt64xxx_pci0_ops; - -static struct resource pci0_io_resource = { - .name = "pci_0 io", - .start = GT_PCI_IO_BASE, - .end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1, - .flags = IORESOURCE_IO, -}; - -static struct resource pci0_mem_resource = { - .name = "pci_0 memory", - .start = GT_PCI_MEM_BASE, - .end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static struct pci_controller hose_0 = { - .pci_ops = >64xxx_pci0_ops, - .io_resource = &pci0_io_resource, - .mem_resource = &pci0_mem_resource, -}; - -static int __init gt64120_pci_init(void) -{ - (void) GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */ - (void) GT_READ(GT_PCI0_BARE_OFS); - - /* reset the whole PCI I/O space range */ - ioport_resource.start = GT_PCI_IO_BASE; - ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1; - - register_pci_controller(&hose_0); - return 0; -} - -arch_initcall(gt64120_pci_init); diff --git a/arch/mips/wrppmc/reset.c b/arch/mips/wrppmc/reset.c deleted file mode 100644 index 80beb18..0000000 --- a/arch/mips/wrppmc/reset.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997 Ralf Baechle - */ -#include -#include - -#include -#include -#include -#include - -void wrppmc_machine_restart(char *command) -{ - /* - * Ouch, we're still alive ... This time we take the silver bullet ... - * ... and find that we leave the hardware in a state in which the - * kernel in the flush locks up somewhen during of after the PCI - * detection stuff. - */ - local_irq_disable(); - set_c0_status(ST0_BEV | ST0_ERL); - change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); - flush_cache_all(); - write_c0_wired(0); - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); -} - -void wrppmc_machine_halt(void) -{ - local_irq_disable(); - - printk(KERN_NOTICE "You can safely turn off the power\n"); - while (1) { - if (cpu_wait) - cpu_wait(); - } -} diff --git a/arch/mips/wrppmc/serial.c b/arch/mips/wrppmc/serial.c deleted file mode 100644 index 83f0f7d..0000000 --- a/arch/mips/wrppmc/serial.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Registration of WRPPMC UART platform device. - * - * Copyright (C) 2007 Yoichi Yuasa - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include -#include -#include -#include -#include - -#include - -static struct resource wrppmc_uart_resource[] __initdata = { - { - .start = WRPPMC_UART16550_BASE, - .end = WRPPMC_UART16550_BASE + 7, - .flags = IORESOURCE_MEM, - }, - { - .start = WRPPMC_UART16550_IRQ, - .end = WRPPMC_UART16550_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct plat_serial8250_port wrppmc_serial8250_port[] = { - { - .irq = WRPPMC_UART16550_IRQ, - .uartclk = WRPPMC_UART16550_CLOCK, - .iotype = UPIO_MEM, - .flags = UPF_IOREMAP | UPF_SKIP_TEST, - .mapbase = WRPPMC_UART16550_BASE, - }, - {}, -}; - -static __init int wrppmc_uart_add(void) -{ - struct platform_device *pdev; - int retval; - - pdev = platform_device_alloc("serial8250", -1); - if (!pdev) - return -ENOMEM; - - pdev->id = PLAT8250_DEV_PLATFORM; - pdev->dev.platform_data = wrppmc_serial8250_port; - - retval = platform_device_add_resources(pdev, wrppmc_uart_resource, - ARRAY_SIZE(wrppmc_uart_resource)); - if (retval) - goto err_free_device; - - retval = platform_device_add(pdev); - if (retval) - goto err_free_device; - - return 0; - -err_free_device: - platform_device_put(pdev); - - return retval; -} -device_initcall(wrppmc_uart_add); diff --git a/arch/mips/wrppmc/setup.c b/arch/mips/wrppmc/setup.c deleted file mode 100644 index ca65c84..0000000 --- a/arch/mips/wrppmc/setup.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * setup.c: Setup pointers to hardware dependent routines. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2006, Wind River System Inc. Rongkai.zhan - */ -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -unsigned long gt64120_base = KSEG1ADDR(0x14000000); - -#ifdef WRPPMC_EARLY_DEBUG - -static volatile unsigned char * wrppmc_led = \ - (volatile unsigned char *)KSEG1ADDR(WRPPMC_LED_BASE); - -/* - * PPMC LED control register: - * -) bit[0] controls DS1 LED (1 - OFF, 0 - ON) - * -) bit[1] controls DS2 LED (1 - OFF, 0 - ON) - * -) bit[2] controls DS4 LED (1 - OFF, 0 - ON) - */ -void wrppmc_led_on(int mask) -{ - unsigned char value = *wrppmc_led; - - value &= (0xF8 | mask); - *wrppmc_led = value; -} - -/* If mask = 0, turn off all LEDs */ -void wrppmc_led_off(int mask) -{ - unsigned char value = *wrppmc_led; - - value |= (0x7 & mask); - *wrppmc_led = value; -} - -/* - * We assume that bootloader has initialized UART16550 correctly - */ -void __init wrppmc_early_putc(char ch) -{ - static volatile unsigned char *wrppmc_uart = \ - (volatile unsigned char *)KSEG1ADDR(WRPPMC_UART16550_BASE); - unsigned char value; - - /* Wait until Transmit-Holding-Register is empty */ - while (1) { - value = *(wrppmc_uart + 5); - if (value & 0x20) - break; - } - - *wrppmc_uart = ch; -} - -void __init wrppmc_early_printk(const char *fmt, ...) -{ - static char pbuf[256] = {'\0', }; - char *ch = pbuf; - va_list args; - unsigned int i; - - memset(pbuf, 0, 256); - va_start(args, fmt); - i = vsprintf(pbuf, fmt, args); - va_end(args); - - /* Print the string */ - while (*ch != '\0') { - wrppmc_early_putc(*ch); - /* if print '\n', also print '\r' */ - if (*ch++ == '\n') - wrppmc_early_putc('\r'); - } -} -#endif /* WRPPMC_EARLY_DEBUG */ - -void __init prom_free_prom_memory(void) -{ -} - -void __init plat_mem_setup(void) -{ - extern void wrppmc_machine_restart(char *command); - extern void wrppmc_machine_halt(void); - - _machine_restart = wrppmc_machine_restart; - _machine_halt = wrppmc_machine_halt; - pm_power_off = wrppmc_machine_halt; - - /* This makes the operations of 'in/out[bwl]' to the - * physical address ( < KSEG0) can work via KSEG1 - */ - set_io_port_base(KSEG1); -} - -const char *get_system_type(void) -{ - return "Wind River PPMC (GT64120)"; -} - -/* - * Initializes basic routines and structures pointers, memory size (as - * given by the bios and saves the command line. - */ -void __init prom_init(void) -{ - add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM); - add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA); - - wrppmc_early_printk("prom_init: GT64120 SDRAM Bank 0: 0x%x - 0x%08lx\n", - WRPPMC_SDRAM_SCS0_BASE, (WRPPMC_SDRAM_SCS0_BASE + WRPPMC_SDRAM_SCS0_SIZE)); -} diff --git a/arch/mips/wrppmc/time.c b/arch/mips/wrppmc/time.c deleted file mode 100644 index 668dbd5..0000000 --- a/arch/mips/wrppmc/time.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * time.c: MIPS CPU Count/Compare timer hookup - * - * Author: Mark.Zhan, - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2006, Wind River System Inc. - */ -#include -#include -#include - -#include -#include - -#define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */ - -/* - * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect - * - * NOTE: We disable all GT64120 timers, and use MIPS processor internal - * timer as the source of kernel clock tick. - */ -void __init plat_time_init(void) -{ - /* Disable GT64120 timers */ - GT_WRITE(GT_TC_CONTROL_OFS, 0x00); - GT_WRITE(GT_TC0_OFS, 0x00); - GT_WRITE(GT_TC1_OFS, 0x00); - GT_WRITE(GT_TC2_OFS, 0x00); - GT_WRITE(GT_TC3_OFS, 0x00); - - /* Use MIPS compare/count internal timer */ - mips_hpt_frequency = WRPPMC_CPU_CLK_FREQ; -} -- cgit v0.10.2 From ae8de61c726f4f2c4b1b4d8263c9c71b82503e0d Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 18 Jun 2013 16:55:39 +0000 Subject: MIPS: BCM63XX: select BOOT_RAW Enabling BOOT_RAW is mandatory to get a binary image (objcopy from ELF to binary) to work. This does not affect the ELF kernels which are used by CFE on BCM63XX DSL platforms, but is going to be necessary to support BCM63XX on Cable Modem chips such as BCM3368. Signed-off-by: Florian Fainelli Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/5500/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f4cc348..ba63cdb 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -121,6 +121,7 @@ config BCM47XX config BCM63XX bool "Broadcom BCM63XX based boards" + select BOOT_RAW select CEVT_R4K select CSRC_R4K select DMA_NONCOHERENT -- cgit v0.10.2 From 7b9334215f53135fb9cbdf0b44833cbc8e7d57b2 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 18 Jun 2013 16:55:40 +0000 Subject: MIPS: BCM63XX: add support for BCM3368 Cable Modem The Broadcom BCM3368 Cable Modem SoC is extremely similar to the existing BCM63xx DSL SoCs, in particular BCM6358, therefore little effort in the existing code base is required to get it supported. This patch adds support for the following on-chip peripherals: - two UARTS - GPIO - Ethernet - SPI - PCI - NOR Flash The most noticeable difference with 3368 is that it has its peripheral register at 0xfff8_0000 we check that separately in ioremap.h. Since 3368 is identical to 6358 for its clock and reset bits, we use them verbatim. Signed-off-by: Florian Fainelli Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/5499/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig index 5639662..afe52d4 100644 --- a/arch/mips/bcm63xx/Kconfig +++ b/arch/mips/bcm63xx/Kconfig @@ -1,6 +1,10 @@ menu "CPU support" depends on BCM63XX +config BCM63XX_CPU_3368 + bool "support 3368 CPU" + select HW_HAS_PCI + config BCM63XX_CPU_6328 bool "support 6328 CPU" select HW_HAS_PCI diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c index c726a97..fda2690 100644 --- a/arch/mips/bcm63xx/clk.c +++ b/arch/mips/bcm63xx/clk.c @@ -84,7 +84,7 @@ static void enetx_set(struct clk *clk, int enable) else clk_disable_unlocked(&clk_enet_misc); - if (BCMCPU_IS_6358()) { + if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) { u32 mask; if (clk->id == 0) @@ -110,9 +110,8 @@ static struct clk clk_enet1 = { */ static void ephy_set(struct clk *clk, int enable) { - if (!BCMCPU_IS_6358()) - return; - bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable); + if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) + bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable); } @@ -155,9 +154,10 @@ static struct clk clk_enetsw = { */ static void pcm_set(struct clk *clk, int enable) { - if (!BCMCPU_IS_6358()) - return; - bcm_hwclock_set(CKCTL_6358_PCM_EN, enable); + if (BCMCPU_IS_3368()) + bcm_hwclock_set(CKCTL_3368_PCM_EN, enable); + if (BCMCPU_IS_6358()) + bcm_hwclock_set(CKCTL_6358_PCM_EN, enable); } static struct clk clk_pcm = { @@ -211,7 +211,7 @@ static void spi_set(struct clk *clk, int enable) mask = CKCTL_6338_SPI_EN; else if (BCMCPU_IS_6348()) mask = CKCTL_6348_SPI_EN; - else if (BCMCPU_IS_6358()) + else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) mask = CKCTL_6358_SPI_EN; else if (BCMCPU_IS_6362()) mask = CKCTL_6362_SPI_EN; @@ -338,7 +338,7 @@ struct clk *clk_get(struct device *dev, const char *id) return &clk_xtm; if (!strcmp(id, "periph")) return &clk_periph; - if (BCMCPU_IS_6358() && !strcmp(id, "pcm")) + if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm")) return &clk_pcm; if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec")) return &clk_ipsec; diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c index 79fe32d..7e17374 100644 --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c @@ -29,6 +29,14 @@ static u8 bcm63xx_cpu_rev; static unsigned int bcm63xx_cpu_freq; static unsigned int bcm63xx_memory_size; +static const unsigned long bcm3368_regs_base[] = { + __GEN_CPU_REGS_TABLE(3368) +}; + +static const int bcm3368_irqs[] = { + __GEN_CPU_IRQ_TABLE(3368) +}; + static const unsigned long bcm6328_regs_base[] = { __GEN_CPU_REGS_TABLE(6328) }; @@ -116,6 +124,9 @@ unsigned int bcm63xx_get_memory_size(void) static unsigned int detect_cpu_clock(void) { switch (bcm63xx_get_cpu_id()) { + case BCM3368_CPU_ID: + return 300000000; + case BCM6328_CPU_ID: { unsigned int tmp, mips_pll_fcvo; @@ -266,7 +277,7 @@ static unsigned int detect_memory_size(void) banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; } - if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) { + if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) { val = bcm_memc_readl(MEMC_CFG_REG); rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; @@ -302,10 +313,17 @@ void __init bcm63xx_cpu_init(void) chipid_reg = BCM_6345_PERF_BASE; break; case CPU_BMIPS4350: - if ((read_c0_prid() & 0xf0) == 0x10) + switch ((read_c0_prid() & 0xff)) { + case 0x04: + chipid_reg = BCM_3368_PERF_BASE; + break; + case 0x10: chipid_reg = BCM_6345_PERF_BASE; - else + break; + default: chipid_reg = BCM_6368_PERF_BASE; + break; + } break; } @@ -322,6 +340,10 @@ void __init bcm63xx_cpu_init(void) bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; switch (bcm63xx_cpu_id) { + case BCM3368_CPU_ID: + bcm63xx_regs_base = bcm3368_regs_base; + bcm63xx_irqs = bcm3368_irqs; + break; case BCM6328_CPU_ID: bcm63xx_regs_base = bcm6328_regs_base; bcm63xx_irqs = bcm6328_irqs; diff --git a/arch/mips/bcm63xx/dev-flash.c b/arch/mips/bcm63xx/dev-flash.c index 588d1ec..172dd83 100644 --- a/arch/mips/bcm63xx/dev-flash.c +++ b/arch/mips/bcm63xx/dev-flash.c @@ -71,6 +71,7 @@ static int __init bcm63xx_detect_flash_type(void) case BCM6348_CPU_ID: /* no way to auto detect so assume parallel */ return BCM63XX_FLASH_TYPE_PARALLEL; + case BCM3368_CPU_ID: case BCM6358_CPU_ID: val = bcm_gpio_readl(GPIO_STRAPBUS_REG); if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL) diff --git a/arch/mips/bcm63xx/dev-spi.c b/arch/mips/bcm63xx/dev-spi.c index 3065bb6..d12daed 100644 --- a/arch/mips/bcm63xx/dev-spi.c +++ b/arch/mips/bcm63xx/dev-spi.c @@ -37,7 +37,8 @@ static __init void bcm63xx_spi_regs_init(void) { if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) bcm63xx_regs_spi = bcm6348_regs_spi; - if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) + if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || + BCMCPU_IS_6362() || BCMCPU_IS_6368()) bcm63xx_regs_spi = bcm6358_regs_spi; } #else @@ -87,7 +88,8 @@ int __init bcm63xx_spi_register(void) spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH; } - if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) { + if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() || + BCMCPU_IS_6368()) { spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1; spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE; spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT; diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c index d6e42c6..3bc7f3b 100644 --- a/arch/mips/bcm63xx/dev-uart.c +++ b/arch/mips/bcm63xx/dev-uart.c @@ -54,7 +54,8 @@ int __init bcm63xx_uart_register(unsigned int id) if (id >= ARRAY_SIZE(bcm63xx_uart_devices)) return -ENODEV; - if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368())) + if (id == 1 && (!BCMCPU_IS_3368() && !BCMCPU_IS_6358() && + !BCMCPU_IS_6368())) return -ENODEV; if (id == 0) { diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index d744606..1525f8a 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -27,6 +27,17 @@ static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused; static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; #ifndef BCMCPU_RUNTIME_DETECT +#ifdef CONFIG_BCM63XX_CPU_3368 +#define irq_stat_reg PERF_IRQSTAT_3368_REG +#define irq_mask_reg PERF_IRQMASK_3368_REG +#define irq_bits 32 +#define is_ext_irq_cascaded 0 +#define ext_irq_start 0 +#define ext_irq_end 0 +#define ext_irq_count 4 +#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_3368 +#define ext_irq_cfg_reg2 0 +#endif #ifdef CONFIG_BCM63XX_CPU_6328 #define irq_stat_reg PERF_IRQSTAT_6328_REG #define irq_mask_reg PERF_IRQMASK_6328_REG @@ -140,6 +151,13 @@ static void bcm63xx_init_irq(void) irq_mask_addr = bcm63xx_regset_address(RSET_PERF); switch (bcm63xx_get_cpu_id()) { + case BCM3368_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_3368_REG; + irq_mask_addr += PERF_IRQMASK_3368_REG; + irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; + break; case BCM6328_CPU_ID: irq_stat_addr += PERF_IRQSTAT_6328_REG; irq_mask_addr += PERF_IRQMASK_6328_REG; @@ -479,6 +497,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d, reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); break; + case BCM3368_CPU_ID: case BCM6328_CPU_ID: case BCM6338_CPU_ID: case BCM6345_CPU_ID: diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c index fd69808..f3ff28f 100644 --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -26,7 +26,9 @@ void __init prom_init(void) bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG); /* disable all hardware blocks clock for now */ - if (BCMCPU_IS_6328()) + if (BCMCPU_IS_3368()) + mask = CKCTL_3368_ALL_SAFE_EN; + else if (BCMCPU_IS_6328()) mask = CKCTL_6328_ALL_SAFE_EN; else if (BCMCPU_IS_6338()) mask = CKCTL_6338_ALL_SAFE_EN; diff --git a/arch/mips/bcm63xx/reset.c b/arch/mips/bcm63xx/reset.c index 317931c..acbeb1f 100644 --- a/arch/mips/bcm63xx/reset.c +++ b/arch/mips/bcm63xx/reset.c @@ -30,6 +30,19 @@ [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \ [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT, +#define BCM3368_RESET_SPI SOFTRESET_3368_SPI_MASK +#define BCM3368_RESET_ENET SOFTRESET_3368_ENET_MASK +#define BCM3368_RESET_USBH 0 +#define BCM3368_RESET_USBD SOFTRESET_3368_USBS_MASK +#define BCM3368_RESET_DSL 0 +#define BCM3368_RESET_SAR 0 +#define BCM3368_RESET_EPHY SOFTRESET_3368_EPHY_MASK +#define BCM3368_RESET_ENETSW 0 +#define BCM3368_RESET_PCM SOFTRESET_3368_PCM_MASK +#define BCM3368_RESET_MPI SOFTRESET_3368_MPI_MASK +#define BCM3368_RESET_PCIE 0 +#define BCM3368_RESET_PCIE_EXT 0 + #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK #define BCM6328_RESET_ENET 0 #define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK @@ -117,6 +130,10 @@ /* * core reset bits */ +static const u32 bcm3368_reset_bits[] = { + __GEN_RESET_BITS_TABLE(3368) +}; + static const u32 bcm6328_reset_bits[] = { __GEN_RESET_BITS_TABLE(6328) }; @@ -146,7 +163,10 @@ static int reset_reg; static int __init bcm63xx_reset_bits_init(void) { - if (BCMCPU_IS_6328()) { + if (BCMCPU_IS_3368()) { + reset_reg = PERF_SOFTRESET_6358_REG; + bcm63xx_reset_bits = bcm3368_reset_bits; + } else if (BCMCPU_IS_6328()) { reset_reg = PERF_SOFTRESET_6328_REG; bcm63xx_reset_bits = bcm6328_reset_bits; } else if (BCMCPU_IS_6338()) { @@ -170,6 +190,13 @@ static int __init bcm63xx_reset_bits_init(void) } #else +#ifdef CONFIG_BCM63XX_CPU_3368 +static const u32 bcm63xx_reset_bits[] = { + __GEN_RESET_BITS_TABLE(3368) +}; +#define reset_reg PERF_SOFTRESET_6358_REG +#endif + #ifdef CONFIG_BCM63XX_CPU_6328 static const u32 bcm63xx_reset_bits[] = { __GEN_RESET_BITS_TABLE(6328) diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c index 24a2444..6660c7d 100644 --- a/arch/mips/bcm63xx/setup.c +++ b/arch/mips/bcm63xx/setup.c @@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void) /* mask and clear all external irq */ switch (bcm63xx_get_cpu_id()) { + case BCM3368_CPU_ID: + perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368; + break; case BCM6328_CPU_ID: perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328; break; diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index 3362289..9d3c08e 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -9,6 +9,7 @@ * compile time if only one CPU support is enabled (idea stolen from * arm mach-types) */ +#define BCM3368_CPU_ID 0x3368 #define BCM6328_CPU_ID 0x6328 #define BCM6338_CPU_ID 0x6338 #define BCM6345_CPU_ID 0x6345 @@ -22,6 +23,19 @@ u16 __bcm63xx_get_cpu_id(void); u8 bcm63xx_get_cpu_rev(void); unsigned int bcm63xx_get_cpu_freq(void); +#ifdef CONFIG_BCM63XX_CPU_3368 +# ifdef bcm63xx_get_cpu_id +# undef bcm63xx_get_cpu_id +# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +# define BCMCPU_RUNTIME_DETECT +# else +# define bcm63xx_get_cpu_id() BCM3368_CPU_ID +# endif +# define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID) +#else +# define BCMCPU_IS_3368() (0) +#endif + #ifdef CONFIG_BCM63XX_CPU_6328 # ifdef bcm63xx_get_cpu_id # undef bcm63xx_get_cpu_id @@ -191,6 +205,53 @@ enum bcm63xx_regs_set { #define RSET_RNG_SIZE 20 /* + * 3368 register sets base address + */ +#define BCM_3368_DSL_LMEM_BASE (0xdeadbeef) +#define BCM_3368_PERF_BASE (0xfff8c000) +#define BCM_3368_TIMER_BASE (0xfff8c040) +#define BCM_3368_WDT_BASE (0xfff8c080) +#define BCM_3368_UART0_BASE (0xfff8c100) +#define BCM_3368_UART1_BASE (0xfff8c120) +#define BCM_3368_GPIO_BASE (0xfff8c080) +#define BCM_3368_SPI_BASE (0xfff8c800) +#define BCM_3368_HSSPI_BASE (0xdeadbeef) +#define BCM_3368_UDC0_BASE (0xdeadbeef) +#define BCM_3368_USBDMA_BASE (0xdeadbeef) +#define BCM_3368_OHCI0_BASE (0xdeadbeef) +#define BCM_3368_OHCI_PRIV_BASE (0xdeadbeef) +#define BCM_3368_USBH_PRIV_BASE (0xdeadbeef) +#define BCM_3368_USBD_BASE (0xdeadbeef) +#define BCM_3368_MPI_BASE (0xfff80000) +#define BCM_3368_PCMCIA_BASE (0xfff80054) +#define BCM_3368_PCIE_BASE (0xdeadbeef) +#define BCM_3368_SDRAM_REGS_BASE (0xdeadbeef) +#define BCM_3368_DSL_BASE (0xdeadbeef) +#define BCM_3368_UBUS_BASE (0xdeadbeef) +#define BCM_3368_ENET0_BASE (0xfff98000) +#define BCM_3368_ENET1_BASE (0xfff98800) +#define BCM_3368_ENETDMA_BASE (0xfff99800) +#define BCM_3368_ENETDMAC_BASE (0xfff99900) +#define BCM_3368_ENETDMAS_BASE (0xfff99a00) +#define BCM_3368_ENETSW_BASE (0xdeadbeef) +#define BCM_3368_EHCI0_BASE (0xdeadbeef) +#define BCM_3368_SDRAM_BASE (0xdeadbeef) +#define BCM_3368_MEMC_BASE (0xfff84000) +#define BCM_3368_DDR_BASE (0xdeadbeef) +#define BCM_3368_M2M_BASE (0xdeadbeef) +#define BCM_3368_ATM_BASE (0xdeadbeef) +#define BCM_3368_XTM_BASE (0xdeadbeef) +#define BCM_3368_XTMDMA_BASE (0xdeadbeef) +#define BCM_3368_XTMDMAC_BASE (0xdeadbeef) +#define BCM_3368_XTMDMAS_BASE (0xdeadbeef) +#define BCM_3368_PCM_BASE (0xfff9c200) +#define BCM_3368_PCMDMA_BASE (0xdeadbeef) +#define BCM_3368_PCMDMAC_BASE (0xdeadbeef) +#define BCM_3368_PCMDMAS_BASE (0xdeadbeef) +#define BCM_3368_RNG_BASE (0xdeadbeef) +#define BCM_3368_MISC_BASE (0xdeadbeef) + +/* * 6328 register sets base address */ #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef) @@ -620,6 +681,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) #ifdef BCMCPU_RUNTIME_DETECT return bcm63xx_regs_base[set]; #else +#ifdef CONFIG_BCM63XX_CPU_3368 + __GEN_RSET(3368) +#endif #ifdef CONFIG_BCM63XX_CPU_6328 __GEN_RSET(6328) #endif @@ -687,6 +751,52 @@ enum bcm63xx_irq { }; /* + * 3368 irqs + */ +#define BCM_3368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) +#define BCM_3368_SPI_IRQ (IRQ_INTERNAL_BASE + 1) +#define BCM_3368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) +#define BCM_3368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) +#define BCM_3368_DSL_IRQ 0 +#define BCM_3368_UDC0_IRQ 0 +#define BCM_3368_OHCI0_IRQ 0 +#define BCM_3368_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) +#define BCM_3368_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) +#define BCM_3368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) +#define BCM_3368_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) +#define BCM_3368_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) +#define BCM_3368_HSSPI_IRQ 0 +#define BCM_3368_EHCI0_IRQ 0 +#define BCM_3368_USBD_IRQ 0 +#define BCM_3368_USBD_RXDMA0_IRQ 0 +#define BCM_3368_USBD_TXDMA0_IRQ 0 +#define BCM_3368_USBD_RXDMA1_IRQ 0 +#define BCM_3368_USBD_TXDMA1_IRQ 0 +#define BCM_3368_USBD_RXDMA2_IRQ 0 +#define BCM_3368_USBD_TXDMA2_IRQ 0 +#define BCM_3368_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) +#define BCM_3368_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) +#define BCM_3368_PCI_IRQ (IRQ_INTERNAL_BASE + 31) +#define BCM_3368_PCMCIA_IRQ 0 +#define BCM_3368_ATM_IRQ 0 +#define BCM_3368_ENETSW_RXDMA0_IRQ 0 +#define BCM_3368_ENETSW_RXDMA1_IRQ 0 +#define BCM_3368_ENETSW_RXDMA2_IRQ 0 +#define BCM_3368_ENETSW_RXDMA3_IRQ 0 +#define BCM_3368_ENETSW_TXDMA0_IRQ 0 +#define BCM_3368_ENETSW_TXDMA1_IRQ 0 +#define BCM_3368_ENETSW_TXDMA2_IRQ 0 +#define BCM_3368_ENETSW_TXDMA3_IRQ 0 +#define BCM_3368_XTM_IRQ 0 +#define BCM_3368_XTM_DMA0_IRQ 0 + +#define BCM_3368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25) +#define BCM_3368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26) +#define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) +#define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) + + +/* * 6328 irqs */ #define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h index 35baa1a..565ff36 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h @@ -11,6 +11,7 @@ static inline unsigned long bcm63xx_gpio_count(void) switch (bcm63xx_get_cpu_id()) { case BCM6328_CPU_ID: return 32; + case BCM3368_CPU_ID: case BCM6358_CPU_ID: return 40; case BCM6338_CPU_ID: diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 3203fe4..6542137 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -15,6 +15,39 @@ /* Clock Control register */ #define PERF_CKCTL_REG 0x4 +#define CKCTL_3368_MAC_EN (1 << 3) +#define CKCTL_3368_TC_EN (1 << 5) +#define CKCTL_3368_US_TOP_EN (1 << 6) +#define CKCTL_3368_DS_TOP_EN (1 << 7) +#define CKCTL_3368_APM_EN (1 << 8) +#define CKCTL_3368_SPI_EN (1 << 9) +#define CKCTL_3368_USBS_EN (1 << 10) +#define CKCTL_3368_BMU_EN (1 << 11) +#define CKCTL_3368_PCM_EN (1 << 12) +#define CKCTL_3368_NTP_EN (1 << 13) +#define CKCTL_3368_ACP_B_EN (1 << 14) +#define CKCTL_3368_ACP_A_EN (1 << 15) +#define CKCTL_3368_EMUSB_EN (1 << 17) +#define CKCTL_3368_ENET0_EN (1 << 18) +#define CKCTL_3368_ENET1_EN (1 << 19) +#define CKCTL_3368_USBU_EN (1 << 20) +#define CKCTL_3368_EPHY_EN (1 << 21) + +#define CKCTL_3368_ALL_SAFE_EN (CKCTL_3368_MAC_EN | \ + CKCTL_3368_TC_EN | \ + CKCTL_3368_US_TOP_EN | \ + CKCTL_3368_DS_TOP_EN | \ + CKCTL_3368_APM_EN | \ + CKCTL_3368_SPI_EN | \ + CKCTL_3368_USBS_EN | \ + CKCTL_3368_BMU_EN | \ + CKCTL_3368_PCM_EN | \ + CKCTL_3368_NTP_EN | \ + CKCTL_3368_ACP_B_EN | \ + CKCTL_3368_ACP_A_EN | \ + CKCTL_3368_EMUSB_EN | \ + CKCTL_3368_USBU_EN) + #define CKCTL_6328_PHYMIPS_EN (1 << 0) #define CKCTL_6328_ADSL_QPROC_EN (1 << 1) #define CKCTL_6328_ADSL_AFE_EN (1 << 2) @@ -181,6 +214,7 @@ #define SYS_PLL_SOFT_RESET 0x1 /* Interrupt Mask register */ +#define PERF_IRQMASK_3368_REG 0xc #define PERF_IRQMASK_6328_REG 0x20 #define PERF_IRQMASK_6338_REG 0xc #define PERF_IRQMASK_6345_REG 0xc @@ -190,6 +224,7 @@ #define PERF_IRQMASK_6368_REG 0x20 /* Interrupt Status register */ +#define PERF_IRQSTAT_3368_REG 0x10 #define PERF_IRQSTAT_6328_REG 0x28 #define PERF_IRQSTAT_6338_REG 0x10 #define PERF_IRQSTAT_6345_REG 0x10 @@ -199,6 +234,7 @@ #define PERF_IRQSTAT_6368_REG 0x28 /* External Interrupt Configuration register */ +#define PERF_EXTIRQ_CFG_REG_3368 0x14 #define PERF_EXTIRQ_CFG_REG_6328 0x18 #define PERF_EXTIRQ_CFG_REG_6338 0x14 #define PERF_EXTIRQ_CFG_REG_6345 0x14 @@ -236,6 +272,13 @@ #define PERF_SOFTRESET_6362_REG 0x10 #define PERF_SOFTRESET_6368_REG 0x10 +#define SOFTRESET_3368_SPI_MASK (1 << 0) +#define SOFTRESET_3368_ENET_MASK (1 << 2) +#define SOFTRESET_3368_MPI_MASK (1 << 3) +#define SOFTRESET_3368_EPHY_MASK (1 << 6) +#define SOFTRESET_3368_USBS_MASK (1 << 11) +#define SOFTRESET_3368_PCM_MASK (1 << 13) + #define SOFTRESET_6328_SPI_MASK (1 << 0) #define SOFTRESET_6328_EPHY_MASK (1 << 1) #define SOFTRESET_6328_SAR_MASK (1 << 2) @@ -1293,7 +1336,7 @@ #define SPI_6348_RX_DATA 0x80 #define SPI_6348_RX_DATA_SIZE 0x3f -/* BCM 6358/6262/6368 SPI core */ +/* BCM 3368/6358/6262/6368 SPI core */ #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ #define SPI_6358_MSG_CTL_WIDTH 16 #define SPI_6358_MSG_DATA 0x02 diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h index 94e3011..ff15e3b 100644 --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h @@ -11,6 +11,10 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) static inline int is_bcm63xx_internal_registers(phys_t offset) { switch (bcm63xx_get_cpu_id()) { + case BCM3368_CPU_ID: + if (offset >= 0xfff80000) + return 1; + break; case BCM6338_CPU_ID: case BCM6345_CPU_ID: case BCM6348_CPU_ID: diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c index 2eb9542..151d9b5 100644 --- a/arch/mips/pci/pci-bcm63xx.c +++ b/arch/mips/pci/pci-bcm63xx.c @@ -266,7 +266,7 @@ static int __init bcm63xx_register_pci(void) /* setup PCI to local bus access, used by PCI device to target * local RAM while bus mastering */ bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3); - if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) + if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) val = MPI_SP0_REMAP_ENABLE_MASK; else val = 0; @@ -338,6 +338,7 @@ static int __init bcm63xx_pci_init(void) case BCM6328_CPU_ID: case BCM6362_CPU_ID: return bcm63xx_register_pcie(); + case BCM3368_CPU_ID: case BCM6348_CPU_ID: case BCM6358_CPU_ID: case BCM6368_CPU_ID: -- cgit v0.10.2 From d753601a2a5ff67bbc96ce6512a16305bfd293e7 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 18 Jun 2013 16:55:41 +0000 Subject: MIPS: BCM63XX: recognize Cable Modem firmware format Add the firmware header format which is used by Broadcom Cable Modem SoCs such as the BCM3368 SoC. We export the bcm_hcs firmware format structure because it is used by user-land tools to create firmware images for these SoCs and will later be used by a corresponding MTD parser. Signed-off-by: Florian Fainelli Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/5496/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index a9505c4..46eabb9 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -28,8 +28,12 @@ #include #include +#include + #define PFX "board_bcm963xx: " +#define HCS_OFFSET_128K 0x20000 + static struct board_info board; /* @@ -722,8 +726,9 @@ void __init board_prom_init(void) unsigned int i; u8 *boot_addr, *cfe; char cfe_version[32]; - char *board_name; + char *board_name = NULL; u32 val; + struct bcm_hcs *hcs; /* read base address of boot chip select (0) * 6328/6362 do not have MPI but boot from a fixed address @@ -747,7 +752,12 @@ void __init board_prom_init(void) bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET); - board_name = bcm63xx_nvram_get_name(); + if (BCMCPU_IS_3368()) { + hcs = (struct bcm_hcs *)boot_addr; + board_name = hcs->filename; + } else { + board_name = bcm63xx_nvram_get_name(); + } /* find board by name */ for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) { if (strncmp(board_name, bcm963xx_boards[i]->name, 16)) diff --git a/include/uapi/linux/Kbuild b/include/uapi/linux/Kbuild index ab5d499..ba1c11a 100644 --- a/include/uapi/linux/Kbuild +++ b/include/uapi/linux/Kbuild @@ -62,6 +62,7 @@ header-y += auxvec.h header-y += ax25.h header-y += b1lli.h header-y += baycom.h +header-y += bcm933xx_hcs.h header-y += bfs_fs.h header-y += binfmts.h header-y += blkpg.h diff --git a/include/uapi/linux/bcm933xx_hcs.h b/include/uapi/linux/bcm933xx_hcs.h new file mode 100644 index 0000000..d228218 --- /dev/null +++ b/include/uapi/linux/bcm933xx_hcs.h @@ -0,0 +1,24 @@ +/* + * Broadcom Cable Modem firmware format + */ + +#ifndef __BCM933XX_HCS_H +#define __BCM933XX_HCS_H + +#include + +struct bcm_hcs { + __u16 magic; + __u16 control; + __u16 rev_maj; + __u16 rev_min; + __u32 build_date; + __u32 filelen; + __u32 ldaddress; + char filename[64]; + __u16 hcs; + __u16 her_znaet_chto; + __u32 crc; +}; + +#endif /* __BCM933XX_HCS */ -- cgit v0.10.2 From 0680dc866d10806c85c40b54bbf8cf5be61206d1 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 18 Jun 2013 16:55:42 +0000 Subject: MIPS: BCM63XX: provide a MAC address for BCM3368 chips The BCM3368 SoC uses a NVRAM format which is not compatible with the one used by CFE, provide a default MAC address which is suitable for use and which is the default one also being used by the bootloader on these chips. Signed-off-by: Florian Fainelli Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/5498/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/bcm63xx/nvram.c b/arch/mips/bcm63xx/nvram.c index a4b8864..e652e57 100644 --- a/arch/mips/bcm63xx/nvram.c +++ b/arch/mips/bcm63xx/nvram.c @@ -42,6 +42,7 @@ void __init bcm63xx_nvram_init(void *addr) { unsigned int check_len; u32 crc, expected_crc; + u8 hcs_mac_addr[ETH_ALEN] = { 0x00, 0x10, 0x18, 0xff, 0xff, 0xff }; /* extract nvram data */ memcpy(&nvram, addr, sizeof(nvram)); @@ -62,6 +63,15 @@ void __init bcm63xx_nvram_init(void *addr) if (crc != expected_crc) pr_warn("nvram checksum failed, contents may be invalid (expected %08x, got %08x)\n", expected_crc, crc); + + /* Cable modems have a different NVRAM which is embedded in the eCos + * firmware and not easily extractible, give at least a MAC address + * pool. + */ + if (BCMCPU_IS_3368()) { + memcpy(nvram.mac_addr_base, hcs_mac_addr, ETH_ALEN); + nvram.mac_addr_count = 2; + } } u8 *bcm63xx_nvram_get_name(void) -- cgit v0.10.2 From 0b35f0c59a601a88ec8c08ebab0b5a733c8de79f Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 18 Jun 2013 16:55:43 +0000 Subject: MIPS: BCM63XX: let board specify an external GPIO to reset PHY Some boards may need to reset their external PHY or switch they are attached to, add a hook for doing this along with providing custom linux/gpio.h flags for doing this. Signed-off-by: Florian Fainelli Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Cc: Florian Fainelli Patchwork: https://patchwork.linux-mips.org/patch/5501/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index 46eabb9..611a420 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -883,5 +883,9 @@ int __init board_register_devices(void) platform_device_register(&bcm63xx_gpio_leds); + if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags) + gpio_request_one(board.ephy_reset_gpio, + board.ephy_reset_gpio_flags, "ephy-reset"); + return 0; } diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h index 682bcf3..5981fe0 100644 --- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h @@ -45,6 +45,12 @@ struct board_info { /* GPIO LEDs */ struct gpio_led leds[5]; + + /* External PHY reset GPIO */ + unsigned int ephy_reset_gpio; + + /* External PHY reset GPIO flags from gpio.h */ + unsigned long ephy_reset_gpio_flags; }; #endif /* ! BOARD_BCM963XX_H_ */ -- cgit v0.10.2 From 450acb0b120ebcdc7d2ea6888b5302a6a5a12420 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 18 Jun 2013 16:55:44 +0000 Subject: MIPS: BCM63XX: add support for the Netgear CVG834G Add support for the Netgear CVG834G and enable the two UARTs, Ethernet on the first MAC, PCI and the two leds. Signed-off-by: Florian Fainelli Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Cc: Florian Fainelli Patchwork: https://patchwork.linux-mips.org/patch/5502/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index 611a420..d3304dc 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -37,6 +37,38 @@ static struct board_info board; /* + * known 3368 boards + */ +#ifdef CONFIG_BCM63XX_CPU_3368 +static struct board_info __initdata board_cvg834g = { + .name = "CVG834G_E15R3921", + .expected_cpu_id = 0x3368, + + .has_uart0 = 1, + .has_uart1 = 1, + + .has_enet0 = 1, + .has_pci = 1, + + .enet0 = { + .has_phy = 1, + .use_internal_phy = 1, + }, + + .leds = { + { + .name = "CVG834G:green:power", + .gpio = 37, + .default_trigger= "default-on", + }, + }, + + .ephy_reset_gpio = 36, + .ephy_reset_gpio_flags = GPIOF_INIT_HIGH, +}; +#endif + +/* * known 6328 boards */ #ifdef CONFIG_BCM63XX_CPU_6328 @@ -643,6 +675,9 @@ static struct board_info __initdata board_DWVS0 = { * all boards */ static const struct board_info __initconst *bcm963xx_boards[] = { +#ifdef CONFIG_BCM63XX_CPU_3368 + &board_cvg834g, +#endif #ifdef CONFIG_BCM63XX_CPU_6328 &board_96328avng, #endif -- cgit v0.10.2 From 5219343f83a033fe5dfcbb0274b5a78e8b2d0fee Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 19 Jun 2013 20:37:26 +0000 Subject: MIPS: OCTEON: Set proper UART clock in internal device trees. Following patch to use generic 8250 drivers will need proper clock information. So when using the internal device tree, populate the "clock-frequency" property with the correct value. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Cc: Jamie Iles Cc: Greg Kroah-Hartman Cc: Jiri Slaby Cc: linux-serial@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5515/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index 389512e..7b746e7 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -490,8 +490,15 @@ int __init octeon_prune_device_tree(void) if (alias_prop) { uart = fdt_path_offset(initial_boot_params, alias_prop); - if (uart_mask & (1 << i)) + if (uart_mask & (1 << i)) { + __be32 f; + + f = cpu_to_be32(octeon_get_io_clock_rate()); + fdt_setprop_inplace(initial_boot_params, + uart, "clock-frequency", + &f, sizeof(f)); continue; + } pr_debug("Deleting uart%d\n", i); fdt_nop_node(initial_boot_params, uart); fdt_nop_property(initial_boot_params, aliases, -- cgit v0.10.2 From d5f1af7ece96cf52e0b110c72210ac15c2f65438 Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 19 Jun 2013 20:37:27 +0000 Subject: tty/8250_dw: Add support for OCTEON UARTS. A few differences needed by OCTEON: o These are DWC UARTS, but have USR at a different offset. o Internal SoC buses require reading back from registers to maintain write ordering. o 8250 on OCTEON appears with 64-bit wide registers, so when using readb/writeb in big endian mode we have to adjust the membase to hit the proper part of the register. o No UCV register, so we hard code some properties. Because OCTEON doesn't have a UCV register, I change where dw8250_setup_port(), which reads the UCV, is called by pushing it in to the OF and ACPI probe functions, and move unchanged dw8250_setup_port() earlier in the file. Signed-off-by: David Daney Acked-by: Greg Kroah-Hartman Cc: Arnd Bergmann Cc: Heikki Krogerus Cc: linux-mips@linux-mips.org Cc: Jamie Iles Cc: Jiri Slaby Cc: linux-serial@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5516/ Acked-by: Arnd Bergmann Reviewed-by: Heikki Krogerus Signed-off-by: Ralf Baechle diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index d07b6af..76a8daa 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -29,6 +29,8 @@ #include #include +#include + #include "8250.h" /* Offsets for the DesignWare specific registers */ @@ -57,6 +59,7 @@ struct dw8250_data { int last_lcr; int line; struct clk *clk; + u8 usr_reg; }; static void dw8250_serial_out(struct uart_port *p, int offset, int value) @@ -77,6 +80,13 @@ static unsigned int dw8250_serial_in(struct uart_port *p, int offset) return readb(p->membase + offset); } +/* Read Back (rb) version to ensure register access ording. */ +static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value) +{ + dw8250_serial_out(p, offset, value); + dw8250_serial_in(p, UART_LCR); +} + static void dw8250_serial_out32(struct uart_port *p, int offset, int value) { struct dw8250_data *d = p->private_data; @@ -104,7 +114,7 @@ static int dw8250_handle_irq(struct uart_port *p) return 1; } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { /* Clear the USR and write the LCR again. */ - (void)p->serial_in(p, DW_UART_USR); + (void)p->serial_in(p, d->usr_reg); p->serial_out(p, UART_LCR, d->last_lcr); return 1; @@ -125,12 +135,60 @@ dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) pm_runtime_put_sync_suspend(port->dev); } -static int dw8250_probe_of(struct uart_port *p) +static void dw8250_setup_port(struct uart_8250_port *up) +{ + struct uart_port *p = &up->port; + u32 reg = readl(p->membase + DW_UART_UCV); + + /* + * If the Component Version Register returns zero, we know that + * ADDITIONAL_FEATURES are not enabled. No need to go any further. + */ + if (!reg) + return; + + dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n", + (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); + + reg = readl(p->membase + DW_UART_CPR); + if (!reg) + return; + + /* Select the type based on fifo */ + if (reg & DW_UART_CPR_FIFO_MODE) { + p->type = PORT_16550A; + p->flags |= UPF_FIXED_TYPE; + p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); + up->tx_loadsz = p->fifosize; + up->capabilities = UART_CAP_FIFO; + } + + if (reg & DW_UART_CPR_AFCE_MODE) + up->capabilities |= UART_CAP_AFE; +} + +static int dw8250_probe_of(struct uart_port *p, + struct dw8250_data *data) { struct device_node *np = p->dev->of_node; u32 val; - - if (!of_property_read_u32(np, "reg-io-width", &val)) { + bool has_ucv = true; + + if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { +#ifdef __BIG_ENDIAN + /* + * Low order bits of these 64-bit registers, when + * accessed as a byte, are 7 bytes further down in the + * address space in big endian mode. + */ + p->membase += 7; +#endif + p->serial_out = dw8250_serial_out_rb; + p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; + p->type = PORT_OCTEON; + data->usr_reg = 0x27; + has_ucv = false; + } else if (!of_property_read_u32(np, "reg-io-width", &val)) { switch (val) { case 1: break; @@ -144,6 +202,8 @@ static int dw8250_probe_of(struct uart_port *p) return -EINVAL; } } + if (has_ucv) + dw8250_setup_port(container_of(p, struct uart_8250_port, port)); if (!of_property_read_u32(np, "reg-shift", &val)) p->regshift = val; @@ -168,6 +228,8 @@ static int dw8250_probe_acpi(struct uart_8250_port *up) const struct acpi_device_id *id; struct uart_port *p = &up->port; + dw8250_setup_port(up); + id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev); if (!id) return -ENODEV; @@ -196,38 +258,6 @@ static inline int dw8250_probe_acpi(struct uart_8250_port *up) } #endif /* CONFIG_ACPI */ -static void dw8250_setup_port(struct uart_8250_port *up) -{ - struct uart_port *p = &up->port; - u32 reg = readl(p->membase + DW_UART_UCV); - - /* - * If the Component Version Register returns zero, we know that - * ADDITIONAL_FEATURES are not enabled. No need to go any further. - */ - if (!reg) - return; - - dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n", - (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); - - reg = readl(p->membase + DW_UART_CPR); - if (!reg) - return; - - /* Select the type based on fifo */ - if (reg & DW_UART_CPR_FIFO_MODE) { - p->type = PORT_16550A; - p->flags |= UPF_FIXED_TYPE; - p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); - up->tx_loadsz = p->fifosize; - up->capabilities = UART_CAP_FIFO; - } - - if (reg & DW_UART_CPR_AFCE_MODE) - up->capabilities |= UART_CAP_AFE; -} - static int dw8250_probe(struct platform_device *pdev) { struct uart_8250_port uart = {}; @@ -259,6 +289,7 @@ static int dw8250_probe(struct platform_device *pdev) if (!data) return -ENOMEM; + data->usr_reg = DW_UART_USR; data->clk = devm_clk_get(&pdev->dev, NULL); if (!IS_ERR(data->clk)) { clk_prepare_enable(data->clk); @@ -270,10 +301,8 @@ static int dw8250_probe(struct platform_device *pdev) uart.port.serial_out = dw8250_serial_out; uart.port.private_data = data; - dw8250_setup_port(&uart); - if (pdev->dev.of_node) { - err = dw8250_probe_of(&uart.port); + err = dw8250_probe_of(&uart.port, data); if (err) return err; } else if (ACPI_HANDLE(&pdev->dev)) { @@ -362,6 +391,7 @@ static const struct dev_pm_ops dw8250_pm_ops = { static const struct of_device_id dw8250_of_match[] = { { .compatible = "snps,dw-apb-uart" }, + { .compatible = "cavium,octeon-3860-uart" }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, dw8250_of_match); -- cgit v0.10.2 From fde179901e2ebe55ebbbd4c635e1fff322640f7d Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 19 Jun 2013 20:37:28 +0000 Subject: MIPS: OCTEON: Remove custom serial setup code. We will use 8250_dw instead. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Cc: Jamie Iles Cc: Greg Kroah-Hartman Cc: Jiri Slaby Cc: linux-serial@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5517/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 3595aff..b703583 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -12,7 +12,7 @@ CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt -obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o +obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o obj-y += dma-octeon.o flash_setup.o obj-y += octeon-memcpy.o obj-y += executive/ diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c deleted file mode 100644 index f393f65..0000000 --- a/arch/mips/cavium-octeon/serial.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004-2007 Cavium Networks - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -#define DEBUG_UART 1 - -unsigned int octeon_serial_in(struct uart_port *up, int offset) -{ - int rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3))); - if (offset == UART_IIR && (rv & 0xf) == 7) { - /* Busy interrupt, read the USR (39) and try again. */ - cvmx_read_csr((uint64_t)(up->membase + (39 << 3))); - rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3))); - } - return rv; -} - -void octeon_serial_out(struct uart_port *up, int offset, int value) -{ - /* - * If bits 6 or 7 of the OCTEON UART's LCR are set, it quits - * working. - */ - if (offset == UART_LCR) - value &= 0x9f; - cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value); -} - -static int octeon_serial_probe(struct platform_device *pdev) -{ - int irq, res; - struct resource *res_mem; - struct uart_8250_port up; - - /* All adaptors have an irq. */ - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - - memset(&up, 0, sizeof(up)); - - up.port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; - up.port.type = PORT_OCTEON; - up.port.iotype = UPIO_MEM; - up.port.regshift = 3; - up.port.dev = &pdev->dev; - - if (octeon_is_simulation()) - /* Make simulator output fast*/ - up.port.uartclk = 115200 * 16; - else - up.port.uartclk = octeon_get_io_clock_rate(); - - up.port.serial_in = octeon_serial_in; - up.port.serial_out = octeon_serial_out; - up.port.irq = irq; - - res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (res_mem == NULL) { - dev_err(&pdev->dev, "found no memory resource\n"); - return -ENXIO; - } - up.port.mapbase = res_mem->start; - up.port.membase = ioremap(res_mem->start, resource_size(res_mem)); - - res = serial8250_register_8250_port(&up); - - return res >= 0 ? 0 : res; -} - -static struct of_device_id octeon_serial_match[] = { - { - .compatible = "cavium,octeon-3860-uart", - }, - {}, -}; -MODULE_DEVICE_TABLE(of, octeon_serial_match); - -static struct platform_driver octeon_serial_driver = { - .probe = octeon_serial_probe, - .driver = { - .owner = THIS_MODULE, - .name = "octeon_serial", - .of_match_table = octeon_serial_match, - }, -}; - -static int __init octeon_serial_init(void) -{ - return platform_driver_register(&octeon_serial_driver); -} -late_initcall(octeon_serial_init); -- cgit v0.10.2 From 1afb49d0e6429ba3997a3dfccb281bc473c4543e Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 19 Jun 2013 20:37:29 +0000 Subject: MIPS: Update cavium_octeon_defconfig The serial port changes make it advisable to enable the proper UART drivers. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Cc: Jamie Iles Cc: Greg Kroah-Hartman Cc: Jiri Slaby Cc: linux-serial@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5518/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/configs/cavium_octeon_defconfig b/arch/mips/configs/cavium_octeon_defconfig index 1888e5f..dace582 100644 --- a/arch/mips/configs/cavium_octeon_defconfig +++ b/arch/mips/configs/cavium_octeon_defconfig @@ -1,13 +1,11 @@ CONFIG_CAVIUM_OCTEON_SOC=y CONFIG_CAVIUM_CN63XXP1=y CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2 -CONFIG_SPARSEMEM_MANUAL=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_SMP=y CONFIG_NR_CPUS=32 CONFIG_HZ_100=y CONFIG_PREEMPT=y -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y @@ -50,7 +48,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y # CONFIG_MTD_OF_PARTS is not set -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_AMDSTD=y @@ -114,6 +111,7 @@ CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=2 CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_8250_DW=y # CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_OCTEON=y -- cgit v0.10.2 From a7543d6003bcd73b57d5244ce78cfe9462755f90 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 25 Jun 2013 12:57:54 +0200 Subject: MIPS: Sibyte: Remove duplicate but harmless line from Platform file. Signed-off-by: Ralf Baechle diff --git a/arch/mips/sibyte/Platform b/arch/mips/sibyte/Platform index d03a075..af9ee6a 100644 --- a/arch/mips/sibyte/Platform +++ b/arch/mips/sibyte/Platform @@ -13,7 +13,6 @@ cflags-$(CONFIG_SIBYTE_BCM112X) += \ -I$(srctree)/arch/mips/include/asm/mach-sibyte \ -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL -platform-$(CONFIG_SIBYTE_SB1250) += sibyte/ cflags-$(CONFIG_SIBYTE_SB1250) += \ -I$(srctree)/arch/mips/include/asm/mach-sibyte \ -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL -- cgit v0.10.2 From f69df6d33c020d3510a31d142edda3bd2107dff4 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 25 Jun 2013 14:13:13 +0200 Subject: MIPS: Sibyte: Fix comment. Signed-off-by: Ralf Baechle diff --git a/arch/mips/sibyte/Platform b/arch/mips/sibyte/Platform index af9ee6a..6cb6dcf 100644 --- a/arch/mips/sibyte/Platform +++ b/arch/mips/sibyte/Platform @@ -30,7 +30,8 @@ cflags-$(CONFIG_SIBYTE_BCM1x80) += \ # Sibyte BCM91120C (CRhine) board # Sibyte BCM91125C (CRhone) board # Sibyte BCM91125E (Rhone) board -# Sibyte SWARM board +# Sibyte BCM91250A (SWARM) board +# Sibyte BCM91250C2 (LittleSur) board # Sibyte BCM91x80 (BigSur) board # load-$(CONFIG_SIBYTE_CARMEL) := 0xffffffff80100000 -- cgit v0.10.2 From 0dad5d262278d24babbd62241fd238a3a3a0a39a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 25 Jun 2013 16:39:34 +0200 Subject: MIPS: Malta: Move platform-specific PCI code to arch/mips/pci. Signed-off-by: Ralf Baechle diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile index 0388fc8..72fdedb 100644 --- a/arch/mips/mti-malta/Makefile +++ b/arch/mips/mti-malta/Makefile @@ -10,7 +10,6 @@ obj-y := malta-amon.o malta-display.o malta-init.o \ malta-reset.o malta-setup.o malta-time.o obj-$(CONFIG_EARLY_PRINTK) += malta-console.o -obj-$(CONFIG_PCI) += malta-pci.o # FIXME FIXME FIXME obj-$(CONFIG_MIPS_MT_SMTC) += malta-smtc.o diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c deleted file mode 100644 index 37134dd..0000000 --- a/arch/mips/mti-malta/malta-pci.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * MIPS boards specific PCI support. - */ -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -static struct resource bonito64_mem_resource = { - .name = "Bonito PCI MEM", - .flags = IORESOURCE_MEM, -}; - -static struct resource bonito64_io_resource = { - .name = "Bonito PCI I/O", - .start = 0x00000000UL, - .end = 0x000fffffUL, - .flags = IORESOURCE_IO, -}; - -static struct resource gt64120_mem_resource = { - .name = "GT-64120 PCI MEM", - .flags = IORESOURCE_MEM, -}; - -static struct resource gt64120_io_resource = { - .name = "GT-64120 PCI I/O", - .flags = IORESOURCE_IO, -}; - -static struct resource msc_mem_resource = { - .name = "MSC PCI MEM", - .flags = IORESOURCE_MEM, -}; - -static struct resource msc_io_resource = { - .name = "MSC PCI I/O", - .flags = IORESOURCE_IO, -}; - -extern struct pci_ops bonito64_pci_ops; -extern struct pci_ops gt64xxx_pci0_ops; -extern struct pci_ops msc_pci_ops; - -static struct pci_controller bonito64_controller = { - .pci_ops = &bonito64_pci_ops, - .io_resource = &bonito64_io_resource, - .mem_resource = &bonito64_mem_resource, - .io_offset = 0x00000000UL, -}; - -static struct pci_controller gt64120_controller = { - .pci_ops = >64xxx_pci0_ops, - .io_resource = >64120_io_resource, - .mem_resource = >64120_mem_resource, -}; - -static struct pci_controller msc_controller = { - .pci_ops = &msc_pci_ops, - .io_resource = &msc_io_resource, - .mem_resource = &msc_mem_resource, -}; - -void __init mips_pcibios_init(void) -{ - struct pci_controller *controller; - resource_size_t start, end, map, start1, end1, map1, map2, map3, mask; - - switch (mips_revision_sconid) { - case MIPS_REVISION_SCON_GT64120: - /* - * Due to a bug in the Galileo system controller, we need - * to setup the PCI BAR for the Galileo internal registers. - * This should be done in the bios/bootprom and will be - * fixed in a later revision of YAMON (the MIPS boards - * boot prom). - */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, - (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */ - (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */ - (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/ - ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/ - GT_PCI0_CFGADDR_CONFIGEN_BIT); - - /* Perform the write */ - GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE)); - - /* Set up resource ranges from the controller's registers. */ - start = GT_READ(GT_PCI0M0LD_OFS); - end = GT_READ(GT_PCI0M0HD_OFS); - map = GT_READ(GT_PCI0M0REMAP_OFS); - end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); - start1 = GT_READ(GT_PCI0M1LD_OFS); - end1 = GT_READ(GT_PCI0M1HD_OFS); - map1 = GT_READ(GT_PCI0M1REMAP_OFS); - end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK); - /* Cannot support multiple windows, use the wider. */ - if (end1 - start1 > end - start) { - start = start1; - end = end1; - map = map1; - } - mask = ~(start ^ end); - /* We don't support remapping with a discontiguous mask. */ - BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && - mask != ~((mask & -mask) - 1)); - gt64120_mem_resource.start = start; - gt64120_mem_resource.end = end; - gt64120_controller.mem_offset = (start & mask) - (map & mask); - /* Addresses are 36-bit, so do shifts in the destinations. */ - gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF; - gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF; - gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; - gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF; - - start = GT_READ(GT_PCI0IOLD_OFS); - end = GT_READ(GT_PCI0IOHD_OFS); - map = GT_READ(GT_PCI0IOREMAP_OFS); - end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); - mask = ~(start ^ end); - /* We don't support remapping with a discontiguous mask. */ - BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && - mask != ~((mask & -mask) - 1)); - gt64120_io_resource.start = map & mask; - gt64120_io_resource.end = (map & mask) | ~mask; - gt64120_controller.io_offset = 0; - /* Addresses are 36-bit, so do shifts in the destinations. */ - gt64120_io_resource.start <<= GT_PCI_DCRM_SHF; - gt64120_io_resource.end <<= GT_PCI_DCRM_SHF; - gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; - - controller = >64120_controller; - break; - - case MIPS_REVISION_SCON_BONITO: - /* Set up resource ranges from the controller's registers. */ - map = BONITO_PCIMAP; - map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >> - BONITO_PCIMAP_PCIMAP_LO0_SHIFT; - map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >> - BONITO_PCIMAP_PCIMAP_LO1_SHIFT; - map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >> - BONITO_PCIMAP_PCIMAP_LO2_SHIFT; - /* Combine as many adjacent windows as possible. */ - map = map1; - start = BONITO_PCILO0_BASE; - end = 1; - if (map3 == map2 + 1) { - map = map2; - start = BONITO_PCILO1_BASE; - end++; - } - if (map2 == map1 + 1) { - map = map1; - start = BONITO_PCILO0_BASE; - end++; - } - bonito64_mem_resource.start = start; - bonito64_mem_resource.end = start + - BONITO_PCIMAP_WINBASE(end) - 1; - bonito64_controller.mem_offset = start - - BONITO_PCIMAP_WINBASE(map); - - controller = &bonito64_controller; - break; - - case MIPS_REVISION_SCON_SOCIT: - case MIPS_REVISION_SCON_ROCIT: - case MIPS_REVISION_SCON_SOCITSC: - case MIPS_REVISION_SCON_SOCITSCP: - /* Set up resource ranges from the controller's registers. */ - MSC_READ(MSC01_PCI_SC2PMBASL, start); - MSC_READ(MSC01_PCI_SC2PMMSKL, mask); - MSC_READ(MSC01_PCI_SC2PMMAPL, map); - msc_mem_resource.start = start & mask; - msc_mem_resource.end = (start & mask) | ~mask; - msc_controller.mem_offset = (start & mask) - (map & mask); -#ifdef CONFIG_MIPS_CMP - if (gcmp_niocu()) - gcmp_setregion(0, start, mask, - GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); -#endif - MSC_READ(MSC01_PCI_SC2PIOBASL, start); - MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); - MSC_READ(MSC01_PCI_SC2PIOMAPL, map); - msc_io_resource.start = map & mask; - msc_io_resource.end = (map & mask) | ~mask; - msc_controller.io_offset = 0; - ioport_resource.end = ~mask; -#ifdef CONFIG_MIPS_CMP - if (gcmp_niocu()) - gcmp_setregion(1, start, mask, - GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); -#endif - /* If ranges overlap I/O takes precedence. */ - start = start & mask; - end = start | ~mask; - if ((start >= msc_mem_resource.start && - start <= msc_mem_resource.end) || - (end >= msc_mem_resource.start && - end <= msc_mem_resource.end)) { - /* Use the larger space. */ - start = max(start, msc_mem_resource.start); - end = min(end, msc_mem_resource.end); - if (start - msc_mem_resource.start >= - msc_mem_resource.end - end) - msc_mem_resource.end = start - 1; - else - msc_mem_resource.start = end + 1; - } - - controller = &msc_controller; - break; - default: - return; - } - - /* Change start address to avoid conflicts with ACPI and SMB devices */ - if (controller->io_resource->start < 0x00002000UL) - controller->io_resource->start = 0x00002000UL; - - iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ - ioport_resource.end = controller->io_resource->end; - - controller->io_map_base = mips_io_port_base; - - register_pci_controller(controller); -} diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index b56fbc0..c382042 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -29,7 +29,7 @@ obj-$(CONFIG_LASAT) += pci-lasat.o obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o -obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o +obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o pci-malta.o obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o diff --git a/arch/mips/pci/pci-malta.c b/arch/mips/pci/pci-malta.c new file mode 100644 index 0000000..37134dd --- /dev/null +++ b/arch/mips/pci/pci-malta.c @@ -0,0 +1,254 @@ +/* + * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * + * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * MIPS boards specific PCI support. + */ +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +static struct resource bonito64_mem_resource = { + .name = "Bonito PCI MEM", + .flags = IORESOURCE_MEM, +}; + +static struct resource bonito64_io_resource = { + .name = "Bonito PCI I/O", + .start = 0x00000000UL, + .end = 0x000fffffUL, + .flags = IORESOURCE_IO, +}; + +static struct resource gt64120_mem_resource = { + .name = "GT-64120 PCI MEM", + .flags = IORESOURCE_MEM, +}; + +static struct resource gt64120_io_resource = { + .name = "GT-64120 PCI I/O", + .flags = IORESOURCE_IO, +}; + +static struct resource msc_mem_resource = { + .name = "MSC PCI MEM", + .flags = IORESOURCE_MEM, +}; + +static struct resource msc_io_resource = { + .name = "MSC PCI I/O", + .flags = IORESOURCE_IO, +}; + +extern struct pci_ops bonito64_pci_ops; +extern struct pci_ops gt64xxx_pci0_ops; +extern struct pci_ops msc_pci_ops; + +static struct pci_controller bonito64_controller = { + .pci_ops = &bonito64_pci_ops, + .io_resource = &bonito64_io_resource, + .mem_resource = &bonito64_mem_resource, + .io_offset = 0x00000000UL, +}; + +static struct pci_controller gt64120_controller = { + .pci_ops = >64xxx_pci0_ops, + .io_resource = >64120_io_resource, + .mem_resource = >64120_mem_resource, +}; + +static struct pci_controller msc_controller = { + .pci_ops = &msc_pci_ops, + .io_resource = &msc_io_resource, + .mem_resource = &msc_mem_resource, +}; + +void __init mips_pcibios_init(void) +{ + struct pci_controller *controller; + resource_size_t start, end, map, start1, end1, map1, map2, map3, mask; + + switch (mips_revision_sconid) { + case MIPS_REVISION_SCON_GT64120: + /* + * Due to a bug in the Galileo system controller, we need + * to setup the PCI BAR for the Galileo internal registers. + * This should be done in the bios/bootprom and will be + * fixed in a later revision of YAMON (the MIPS boards + * boot prom). + */ + GT_WRITE(GT_PCI0_CFGADDR_OFS, + (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */ + (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */ + (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/ + ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/ + GT_PCI0_CFGADDR_CONFIGEN_BIT); + + /* Perform the write */ + GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE)); + + /* Set up resource ranges from the controller's registers. */ + start = GT_READ(GT_PCI0M0LD_OFS); + end = GT_READ(GT_PCI0M0HD_OFS); + map = GT_READ(GT_PCI0M0REMAP_OFS); + end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); + start1 = GT_READ(GT_PCI0M1LD_OFS); + end1 = GT_READ(GT_PCI0M1HD_OFS); + map1 = GT_READ(GT_PCI0M1REMAP_OFS); + end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK); + /* Cannot support multiple windows, use the wider. */ + if (end1 - start1 > end - start) { + start = start1; + end = end1; + map = map1; + } + mask = ~(start ^ end); + /* We don't support remapping with a discontiguous mask. */ + BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && + mask != ~((mask & -mask) - 1)); + gt64120_mem_resource.start = start; + gt64120_mem_resource.end = end; + gt64120_controller.mem_offset = (start & mask) - (map & mask); + /* Addresses are 36-bit, so do shifts in the destinations. */ + gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF; + gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF; + gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; + gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF; + + start = GT_READ(GT_PCI0IOLD_OFS); + end = GT_READ(GT_PCI0IOHD_OFS); + map = GT_READ(GT_PCI0IOREMAP_OFS); + end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); + mask = ~(start ^ end); + /* We don't support remapping with a discontiguous mask. */ + BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && + mask != ~((mask & -mask) - 1)); + gt64120_io_resource.start = map & mask; + gt64120_io_resource.end = (map & mask) | ~mask; + gt64120_controller.io_offset = 0; + /* Addresses are 36-bit, so do shifts in the destinations. */ + gt64120_io_resource.start <<= GT_PCI_DCRM_SHF; + gt64120_io_resource.end <<= GT_PCI_DCRM_SHF; + gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; + + controller = >64120_controller; + break; + + case MIPS_REVISION_SCON_BONITO: + /* Set up resource ranges from the controller's registers. */ + map = BONITO_PCIMAP; + map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >> + BONITO_PCIMAP_PCIMAP_LO0_SHIFT; + map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >> + BONITO_PCIMAP_PCIMAP_LO1_SHIFT; + map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >> + BONITO_PCIMAP_PCIMAP_LO2_SHIFT; + /* Combine as many adjacent windows as possible. */ + map = map1; + start = BONITO_PCILO0_BASE; + end = 1; + if (map3 == map2 + 1) { + map = map2; + start = BONITO_PCILO1_BASE; + end++; + } + if (map2 == map1 + 1) { + map = map1; + start = BONITO_PCILO0_BASE; + end++; + } + bonito64_mem_resource.start = start; + bonito64_mem_resource.end = start + + BONITO_PCIMAP_WINBASE(end) - 1; + bonito64_controller.mem_offset = start - + BONITO_PCIMAP_WINBASE(map); + + controller = &bonito64_controller; + break; + + case MIPS_REVISION_SCON_SOCIT: + case MIPS_REVISION_SCON_ROCIT: + case MIPS_REVISION_SCON_SOCITSC: + case MIPS_REVISION_SCON_SOCITSCP: + /* Set up resource ranges from the controller's registers. */ + MSC_READ(MSC01_PCI_SC2PMBASL, start); + MSC_READ(MSC01_PCI_SC2PMMSKL, mask); + MSC_READ(MSC01_PCI_SC2PMMAPL, map); + msc_mem_resource.start = start & mask; + msc_mem_resource.end = (start & mask) | ~mask; + msc_controller.mem_offset = (start & mask) - (map & mask); +#ifdef CONFIG_MIPS_CMP + if (gcmp_niocu()) + gcmp_setregion(0, start, mask, + GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); +#endif + MSC_READ(MSC01_PCI_SC2PIOBASL, start); + MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); + MSC_READ(MSC01_PCI_SC2PIOMAPL, map); + msc_io_resource.start = map & mask; + msc_io_resource.end = (map & mask) | ~mask; + msc_controller.io_offset = 0; + ioport_resource.end = ~mask; +#ifdef CONFIG_MIPS_CMP + if (gcmp_niocu()) + gcmp_setregion(1, start, mask, + GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); +#endif + /* If ranges overlap I/O takes precedence. */ + start = start & mask; + end = start | ~mask; + if ((start >= msc_mem_resource.start && + start <= msc_mem_resource.end) || + (end >= msc_mem_resource.start && + end <= msc_mem_resource.end)) { + /* Use the larger space. */ + start = max(start, msc_mem_resource.start); + end = min(end, msc_mem_resource.end); + if (start - msc_mem_resource.start >= + msc_mem_resource.end - end) + msc_mem_resource.end = start - 1; + else + msc_mem_resource.start = end + 1; + } + + controller = &msc_controller; + break; + default: + return; + } + + /* Change start address to avoid conflicts with ACPI and SMB devices */ + if (controller->io_resource->start < 0x00002000UL) + controller->io_resource->start = 0x00002000UL; + + iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ + ioport_resource.end = controller->io_resource->end; + + controller->io_map_base = mips_io_port_base; + + register_pci_controller(controller); +} -- cgit v0.10.2 From 1990e5429c2149a30a81ff634215c1aa76560a89 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 26 Jun 2013 17:06:34 +0200 Subject: MIPS: Get rid of MIPS I flag and test macros. MIPS I is the ancestor of all MIPS ISA and architecture variants. Anything ever build in the MIPS empire is either MIPS I or at least contains MIPS I. If it's running Linux, that is. So there is little point in having cpu_has_mips_1 because it will always evaluate as true - though usually only at runtime. Thus there is no point in having the MIPS_CPU_ISA_I ISA flag, so get rid of it. Little complication: traps.c was using a test for a pure MIPS I ISA as a test for an R3000-style cp0. To deal with that, use a check for cpu_has_3kex or cpu_has_4kex instead. cpu_has_3kex is a new macro. At the moment its default implementation is !cpu_has_4kex but this may eventually change if Linux is ever going to support the oddball MIPS processors R6000 and R8000 so users of either of these macros should not make any assumptions. Signed-off-by: Ralf Baechle Patchwork: https://patchwork.linux-mips.org/patch/5551/ diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index e5ec8fc..9609812 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -24,6 +24,16 @@ #ifndef cpu_has_tlb #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) #endif + +/* + * For the moment we don't consider R6000 and R8000 so we can assume that + * anything that doesn't support R4000-style exceptions and interrupts is + * R3000-like. Users should still treat these two macro definitions as + * opaque. + */ +#ifndef cpu_has_3kex +#define cpu_has_3kex (!cpu_has_4kex) +#endif #ifndef cpu_has_4kex #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) #endif @@ -136,7 +146,6 @@ #endif #endif -# define cpu_has_mips_1 (cpu_data[0].isa_level & MIPS_CPU_ISA_I) #ifndef cpu_has_mips_2 # define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) #endif diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index dd86ab2..632bbe5 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -282,18 +282,17 @@ enum cpu_type_enum { * ISA Level encodings * */ -#define MIPS_CPU_ISA_I 0x00000001 -#define MIPS_CPU_ISA_II 0x00000002 -#define MIPS_CPU_ISA_III 0x00000004 -#define MIPS_CPU_ISA_IV 0x00000008 -#define MIPS_CPU_ISA_V 0x00000010 -#define MIPS_CPU_ISA_M32R1 0x00000020 -#define MIPS_CPU_ISA_M32R2 0x00000040 -#define MIPS_CPU_ISA_M64R1 0x00000080 -#define MIPS_CPU_ISA_M64R2 0x00000100 - -#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ - MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2) +#define MIPS_CPU_ISA_II 0x00000001 +#define MIPS_CPU_ISA_III 0x00000002 +#define MIPS_CPU_ISA_IV 0x00000004 +#define MIPS_CPU_ISA_V 0x00000008 +#define MIPS_CPU_ISA_M32R1 0x00000010 +#define MIPS_CPU_ISA_M32R2 0x00000020 +#define MIPS_CPU_ISA_M64R1 0x00000040 +#define MIPS_CPU_ISA_M64R2 0x00000080 + +#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \ + MIPS_CPU_ISA_M32R2) #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 265c97d..f87039d 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -146,8 +146,7 @@ static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa) case MIPS_CPU_ISA_IV: c->isa_level |= MIPS_CPU_ISA_IV; case MIPS_CPU_ISA_III: - c->isa_level |= MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | - MIPS_CPU_ISA_III; + c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; break; case MIPS_CPU_ISA_M32R2: @@ -156,8 +155,6 @@ static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa) c->isa_level |= MIPS_CPU_ISA_M32R1; case MIPS_CPU_ISA_II: c->isa_level |= MIPS_CPU_ISA_II; - case MIPS_CPU_ISA_I: - c->isa_level |= MIPS_CPU_ISA_I; break; } } @@ -332,7 +329,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) case PRID_IMP_R2000: c->cputype = CPU_R2000; __cpu_name[cpu] = "R2000"; - set_isa(c, MIPS_CPU_ISA_I); c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | MIPS_CPU_NOFPUEX; if (__cpu_has_fpu()) @@ -352,7 +348,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_R3000; __cpu_name[cpu] = "R3000"; } - set_isa(c, MIPS_CPU_ISA_I); c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | MIPS_CPU_NOFPUEX; if (__cpu_has_fpu()) @@ -455,7 +450,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) break; #endif case PRID_IMP_TX39: - set_isa(c, MIPS_CPU_ISA_I); c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index acb3437..8c58d8a 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -66,9 +66,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "]\n"); } if (cpu_has_mips_r) { - seq_printf(m, "isa\t\t\t:"); - if (cpu_has_mips_1) - seq_printf(m, "%s", " mips1"); + seq_printf(m, "isa\t\t\t: mips1"); if (cpu_has_mips_2) seq_printf(m, "%s", " mips2"); if (cpu_has_mips_3) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 142d2be..d97ea23 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -265,7 +265,7 @@ static void __show_regs(const struct pt_regs *regs) printk("Status: %08x ", (uint32_t) regs->cp0_status); - if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { + if (cpu_has_3kex) { if (regs->cp0_status & ST0_KUO) printk("KUo "); if (regs->cp0_status & ST0_IEO) @@ -278,7 +278,7 @@ static void __show_regs(const struct pt_regs *regs) printk("KUc "); if (regs->cp0_status & ST0_IEC) printk("IEc "); - } else { + } else if (cpu_has_4kex) { if (regs->cp0_status & ST0_KX) printk("KX "); if (regs->cp0_status & ST0_SX) -- cgit v0.10.2 From 6ba045f9fbdafb48da42aa8576ea7a3980443136 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Sun, 23 Jun 2013 17:16:19 +0000 Subject: MIPS: Move generated code to .text for microMIPS Prepare of a next patch which will call tlbmiss_handler_setup_pgd on microMIPS. MicroMIPS complains if the called code s not in the .text section. To fix this we generate code into space reserved in arch/mips/mm/tlb-funcs.S While there, move the rest of the generated functions (handle_tlbl, handle_tlbs, handle_tlbm) to the same file. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5542/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index 8201160..1fed8bd 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -28,11 +28,7 @@ #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ do { \ - void (*tlbmiss_handler_setup_pgd)(unsigned long); \ - extern u32 tlbmiss_handler_setup_pgd_array[16]; \ - \ - tlbmiss_handler_setup_pgd = \ - (__typeof__(tlbmiss_handler_setup_pgd)) tlbmiss_handler_setup_pgd_array; \ + extern void tlbmiss_handler_setup_pgd(unsigned long); \ tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ } while (0) diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index e87aae1..7f4f93a 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -4,7 +4,7 @@ obj-y += cache.o dma-default.o extable.o fault.o \ gup.o init.o mmap.o page.o page-funcs.o \ - tlbex.o tlbex-fault.o uasm-mips.o + tlbex.o tlbex-fault.o tlb-funcs.o uasm-mips.o obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o obj-$(CONFIG_64BIT) += pgtable-64.o diff --git a/arch/mips/mm/tlb-funcs.S b/arch/mips/mm/tlb-funcs.S new file mode 100644 index 0000000..30a494d --- /dev/null +++ b/arch/mips/mm/tlb-funcs.S @@ -0,0 +1,37 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Micro-assembler generated tlb handler functions. + * + * Copyright (C) 2013 Broadcom Corporation. + * + * Based on mm/page-funcs.c + * Copyright (C) 2012 MIPS Technologies, Inc. + * Copyright (C) 2012 Ralf Baechle + */ +#include +#include + +#define FASTPATH_SIZE 128 + +LEAF(tlbmiss_handler_setup_pgd) + .space 16 * 4 +END(tlbmiss_handler_setup_pgd) +EXPORT(tlbmiss_handler_setup_pgd_end) + +LEAF(handle_tlbm) + .space FASTPATH_SIZE * 4 +END(handle_tlbm) +EXPORT(handle_tlbm_end) + +LEAF(handle_tlbs) + .space FASTPATH_SIZE * 4 +END(handle_tlbs) +EXPORT(handle_tlbs_end) + +LEAF(handle_tlbl) + .space FASTPATH_SIZE * 4 +END(handle_tlbl) +EXPORT(handle_tlbl_end) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 9b988c0..4712f3c 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -1455,27 +1455,25 @@ static void __cpuinit build_r4000_tlb_refill_handler(void) dump_handler("r4000_tlb_refill", (u32 *)ebase, 64); } -/* - * 128 instructions for the fastpath handler is generous and should - * never be exceeded. - */ -#define FASTPATH_SIZE 128 +extern u32 handle_tlbl[], handle_tlbl_end[]; +extern u32 handle_tlbs[], handle_tlbs_end[]; +extern u32 handle_tlbm[], handle_tlbm_end[]; -u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; -u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; -u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; #ifdef CONFIG_MIPS_PGD_C0_CONTEXT -u32 tlbmiss_handler_setup_pgd_array[16] __cacheline_aligned; +extern u32 tlbmiss_handler_setup_pgd[], tlbmiss_handler_setup_pgd_end[]; static void __cpuinit build_r4000_setup_pgd(void) { const int a0 = 4; const int a1 = 5; u32 *p = tlbmiss_handler_setup_pgd_array; + const int tlbmiss_handler_setup_pgd_size = + tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd; struct uasm_label *l = labels; struct uasm_reloc *r = relocs; - memset(tlbmiss_handler_setup_pgd_array, 0, sizeof(tlbmiss_handler_setup_pgd_array)); + memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size * + sizeof(tlbmiss_handler_setup_pgd[0])); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); @@ -1503,15 +1501,15 @@ static void __cpuinit build_r4000_setup_pgd(void) uasm_i_jr(&p, 31); UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); } - if (p - tlbmiss_handler_setup_pgd_array > ARRAY_SIZE(tlbmiss_handler_setup_pgd_array)) - panic("tlbmiss_handler_setup_pgd_array space exceeded"); + if (p >= tlbmiss_handler_setup_pgd_end) + panic("tlbmiss_handler_setup_pgd space exceeded"); + uasm_resolve_relocs(relocs, labels); - pr_debug("Wrote tlbmiss_handler_setup_pgd_array (%u instructions).\n", - (unsigned int)(p - tlbmiss_handler_setup_pgd_array)); + pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", + (unsigned int)(p - tlbmiss_handler_setup_pgd)); - dump_handler("tlbmiss_handler", - tlbmiss_handler_setup_pgd_array, - ARRAY_SIZE(tlbmiss_handler_setup_pgd_array)); + dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, + tlbmiss_handler_setup_pgd_size); } #endif @@ -1756,10 +1754,11 @@ build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, static void __cpuinit build_r3000_tlb_load_handler(void) { u32 *p = handle_tlbl; + const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; struct uasm_label *l = labels; struct uasm_reloc *r = relocs; - memset(handle_tlbl, 0, sizeof(handle_tlbl)); + memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); @@ -1773,23 +1772,24 @@ static void __cpuinit build_r3000_tlb_load_handler(void) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); uasm_i_nop(&p); - if ((p - handle_tlbl) > FASTPATH_SIZE) + if (p >= handle_tlbl_end) panic("TLB load handler fastpath space exceeded"); uasm_resolve_relocs(relocs, labels); pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbl)); - dump_handler("r3000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl)); + dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size); } static void __cpuinit build_r3000_tlb_store_handler(void) { u32 *p = handle_tlbs; + const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; struct uasm_label *l = labels; struct uasm_reloc *r = relocs; - memset(handle_tlbs, 0, sizeof(handle_tlbs)); + memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); @@ -1803,23 +1803,24 @@ static void __cpuinit build_r3000_tlb_store_handler(void) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); uasm_i_nop(&p); - if ((p - handle_tlbs) > FASTPATH_SIZE) + if (p >= handle_tlbs) panic("TLB store handler fastpath space exceeded"); uasm_resolve_relocs(relocs, labels); pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbs)); - dump_handler("r3000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs)); + dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size); } static void __cpuinit build_r3000_tlb_modify_handler(void) { u32 *p = handle_tlbm; + const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; struct uasm_label *l = labels; struct uasm_reloc *r = relocs; - memset(handle_tlbm, 0, sizeof(handle_tlbm)); + memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); @@ -1833,14 +1834,14 @@ static void __cpuinit build_r3000_tlb_modify_handler(void) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); uasm_i_nop(&p); - if ((p - handle_tlbm) > FASTPATH_SIZE) + if (p >= handle_tlbm_end) panic("TLB modify handler fastpath space exceeded"); uasm_resolve_relocs(relocs, labels); pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbm)); - dump_handler("r3000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm)); + dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size); } #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ @@ -1904,11 +1905,12 @@ build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, static void __cpuinit build_r4000_tlb_load_handler(void) { u32 *p = handle_tlbl; + const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; struct uasm_label *l = labels; struct uasm_reloc *r = relocs; struct work_registers wr; - memset(handle_tlbl, 0, sizeof(handle_tlbl)); + memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); @@ -2047,24 +2049,25 @@ static void __cpuinit build_r4000_tlb_load_handler(void) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); uasm_i_nop(&p); - if ((p - handle_tlbl) > FASTPATH_SIZE) + if (p >= handle_tlbl_end) panic("TLB load handler fastpath space exceeded"); uasm_resolve_relocs(relocs, labels); pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbl)); - dump_handler("r4000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl)); + dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size); } static void __cpuinit build_r4000_tlb_store_handler(void) { u32 *p = handle_tlbs; + const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; struct uasm_label *l = labels; struct uasm_reloc *r = relocs; struct work_registers wr; - memset(handle_tlbs, 0, sizeof(handle_tlbs)); + memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); @@ -2101,24 +2104,25 @@ static void __cpuinit build_r4000_tlb_store_handler(void) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); uasm_i_nop(&p); - if ((p - handle_tlbs) > FASTPATH_SIZE) + if (p >= handle_tlbs_end) panic("TLB store handler fastpath space exceeded"); uasm_resolve_relocs(relocs, labels); pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbs)); - dump_handler("r4000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs)); + dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size); } static void __cpuinit build_r4000_tlb_modify_handler(void) { u32 *p = handle_tlbm; + const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; struct uasm_label *l = labels; struct uasm_reloc *r = relocs; struct work_registers wr; - memset(handle_tlbm, 0, sizeof(handle_tlbm)); + memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); @@ -2156,14 +2160,14 @@ static void __cpuinit build_r4000_tlb_modify_handler(void) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); uasm_i_nop(&p); - if ((p - handle_tlbm) > FASTPATH_SIZE) + if (p >= handle_tlbm_end) panic("TLB modify handler fastpath space exceeded"); uasm_resolve_relocs(relocs, labels); pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbm)); - dump_handler("r4000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm)); + dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size); } void __cpuinit build_tlb_refill_handler(void) @@ -2235,13 +2239,13 @@ void __cpuinit build_tlb_refill_handler(void) void __cpuinit flush_tlb_handlers(void) { local_flush_icache_range((unsigned long)handle_tlbl, - (unsigned long)handle_tlbl + sizeof(handle_tlbl)); + (unsigned long)handle_tlbl_end); local_flush_icache_range((unsigned long)handle_tlbs, - (unsigned long)handle_tlbs + sizeof(handle_tlbs)); + (unsigned long)handle_tlbs_end); local_flush_icache_range((unsigned long)handle_tlbm, - (unsigned long)handle_tlbm + sizeof(handle_tlbm)); + (unsigned long)handle_tlbm_end); #ifdef CONFIG_MIPS_PGD_C0_CONTEXT - local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd_array, - (unsigned long)tlbmiss_handler_setup_pgd_array + sizeof(handle_tlbm)); + local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, + (unsigned long)tlbmiss_handler_setup_pgd_end); #endif } -- cgit v0.10.2 From a135a9b5d9683ace787c7d86f1e642d9acfacdde Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Sun, 23 Jun 2013 20:38:44 +0000 Subject: MIPS: Octeon: Enable interfaces on EdgeRouter Lite Enable interfaces on EdgeRouter Lite. Tested with cavium_octeon_defconfig and busybox shell. DHCP & ping works with eth0, eth1 and eth2. The board type "UBNT_E100" is taken from the sources of the vendor kernel shipped with the product. Signed-off-by: Aaro Koskinen Acked-by: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5546/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c index 7c64977..0a1283c 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c @@ -181,6 +181,11 @@ int cvmx_helper_board_get_mii_address(int ipd_port) return ipd_port - 16 + 4; else return -1; + case CVMX_BOARD_TYPE_UBNT_E100: + if (ipd_port >= 0 && ipd_port <= 2) + return 7 - ipd_port; + else + return -1; } /* Some unknown board. Somebody forgot to update this function... */ @@ -706,6 +711,14 @@ int __cvmx_helper_board_hardware_enable(int interface) } } } + } else if (cvmx_sysinfo_get()->board_type == + CVMX_BOARD_TYPE_UBNT_E100) { + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0); + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 0x10); + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0); + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0x10); + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(2, interface), 0); + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(2, interface), 0x10); } return 0; } diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h index 284fa8d..7b7818d 100644 --- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h +++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h @@ -227,6 +227,7 @@ enum cvmx_board_types_enum { * use any numbers in this range. */ CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, + CVMX_BOARD_TYPE_UBNT_E100 = 20002, CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, /* The remaining range is reserved for future use. */ @@ -325,6 +326,7 @@ static inline const char *cvmx_board_type_to_string(enum /* Customer private range */ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100) ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX) } return "Unsupported Board"; -- cgit v0.10.2 From 8dfdd02a4c9de3aa7f2bfdec515e57340e401c87 Mon Sep 17 00:00:00 2001 From: David Daney Date: Fri, 21 Jun 2013 21:14:53 +0000 Subject: MIPS: Don't save/restore OCTEON wide multiplier state on syscalls. The ABI allows these to be clobbered on syscalls, so only save and restore the multiplier state when the temporary registers need to be preserved. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Cc: David Daney Patchwork: https://patchwork.linux-mips.org/patch/5540/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index a89d1b1..23fc95e 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -70,6 +70,14 @@ #ifndef CONFIG_CPU_HAS_SMARTMIPS LONG_S v1, PT_LO(sp) #endif +#ifdef CONFIG_CPU_CAVIUM_OCTEON + /* + * The Octeon multiplier state is affected by general + * multiply instructions. It must be saved before and + * kernel code might corrupt it + */ + jal octeon_mult_save +#endif .endm .macro SAVE_STATIC @@ -218,17 +226,8 @@ ori $28, sp, _THREAD_MASK xori $28, _THREAD_MASK #ifdef CONFIG_CPU_CAVIUM_OCTEON - .set mips64 - pref 0, 0($28) /* Prefetch the current pointer */ - pref 0, PT_R31(sp) /* Prefetch the $31(ra) */ - /* The Octeon multiplier state is affected by general multiply - instructions. It must be saved before and kernel code might - corrupt it */ - jal octeon_mult_save - LONG_L v1, 0($28) /* Load the current pointer */ - /* Restore $31(ra) that was changed by the jal */ - LONG_L ra, PT_R31(sp) - pref 0, 0(v1) /* Prefetch the current thread */ + .set mips64 + pref 0, 0($28) /* Prefetch the current pointer */ #endif .set pop .endm @@ -248,6 +247,10 @@ .endm .macro RESTORE_TEMP +#ifdef CONFIG_CPU_CAVIUM_OCTEON + /* Restore the Octeon multiplier state */ + jal octeon_mult_restore +#endif #ifdef CONFIG_CPU_HAS_SMARTMIPS LONG_L $24, PT_ACX(sp) mtlhx $24 @@ -360,10 +363,6 @@ DVPE 5 # dvpe a1 jal mips_ihb #endif /* CONFIG_MIPS_MT_SMTC */ -#ifdef CONFIG_CPU_CAVIUM_OCTEON - /* Restore the Octeon multiplier state */ - jal octeon_mult_restore -#endif mfc0 a0, CP0_STATUS ori a0, STATMASK xori a0, STATMASK -- cgit v0.10.2 From c214c03512b67e56dea3f4471705f8caae49553a Mon Sep 17 00:00:00 2001 From: Tony Wu Date: Fri, 21 Jun 2013 10:13:08 +0000 Subject: MIPS: GIC: Fix gic_set_affinity infinite loop There is an infinite loop in gic_set_affinity. When irq_set_affinity gets called on gic controller, it blocks forever. Signed-off-by: Tony Wu Cc: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5537/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index c01b307..5b5ddb2 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c @@ -219,16 +219,15 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, /* Assumption : cpumask refers to a single CPU */ spin_lock_irqsave(&gic_lock, flags); - for (;;) { - /* Re-route this IRQ */ - GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp)); - /* Update the pcpu_masks */ - for (i = 0; i < NR_CPUS; i++) - clear_bit(irq, pcpu_masks[i].pcpu_mask); - set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask); + /* Re-route this IRQ */ + GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp)); + + /* Update the pcpu_masks */ + for (i = 0; i < NR_CPUS; i++) + clear_bit(irq, pcpu_masks[i].pcpu_mask); + set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask); - } cpumask_copy(d->affinity, cpumask); spin_unlock_irqrestore(&gic_lock, flags); -- cgit v0.10.2 From 3ddc14add5e6341cf8ef4058c34c67ba7fd15317 Mon Sep 17 00:00:00 2001 From: David Daney Date: Fri, 24 May 2013 20:54:10 +0000 Subject: MIPS: Only set cpu_has_mmips if SYS_SUPPORTS_MICROMIPS As Jonas Gorske said in his patch: Disable cpu_has_mmips for everything but SEAD3 and MALTA. Most of these platforms are from before the micromips introduction, so they are very unlikely to implement it. Reduces an -Os compiled, uncompressed kernel image by 8KiB for BCM63XX. This patch taks a different approach than his, we gate the runtime test for microMIPS by the config symbol SYS_SUPPORTS_MICROMIPS. Signed-off-by: David Daney Cc: Jonas Gorski Cc: Steven J. Hill Acked-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5327/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 9609812..8e0c125 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -109,7 +109,11 @@ #define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) #endif #ifndef cpu_has_mmips -#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) +# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS +# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) +# else +# define cpu_has_mmips 0 +# endif #endif #ifndef cpu_has_vtag_icache #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) -- cgit v0.10.2 From 4df715aaf566110bedb3751ed235a3bacdebbdde Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 26 Jun 2013 18:11:56 +0000 Subject: MIPS: BMIPS: support booting from physical CPU other than 0 BMIPS43xx CPUs have two hardware threads, and on some SoCs such as 3368, the bootloader has configured the system to boot from TP1 instead of the more usual TP0. Create the physical to logical CPU mapping to cope with that, do not remap the software interrupts to be cross CPUs such that we do not have to do use the logical CPU mapping further down the code, and finally, reset the slave TP1 only if booted from TP0. Signed-off-by: Jonas Gorski Signed-off-by: Florian Fainelli Cc: linux-mips@linux-mips.org Cc: blogic@openwrt.org Cc: cernekee@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5553/ Patchwork: https://patchwork.linux-mips.org/patch/5556/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index 8e393b8..aea6c08 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -63,7 +63,7 @@ static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id); static void __init bmips_smp_setup(void) { - int i; + int i, cpu = 1, boot_cpu = 0; #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) /* arbitration priority */ @@ -72,13 +72,22 @@ static void __init bmips_smp_setup(void) /* NBK and weak order flags */ set_c0_brcm_config_0(0x30000); + /* Find out if we are running on TP0 or TP1 */ + boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); + /* * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output + * + * If booting from TP1, leave the existing CMT interrupt routing + * such that TP0 responds to SW1 and TP1 responds to SW0. */ - change_c0_brcm_cmt_intr(0xf8018000, - (0x02 << 27) | (0x03 << 15)); + if (boot_cpu == 0) + change_c0_brcm_cmt_intr(0xf8018000, + (0x02 << 27) | (0x03 << 15)); + else + change_c0_brcm_cmt_intr(0xf8018000, (0x1d << 27)); /* single core, 2 threads (2 pipelines) */ max_cpus = 2; @@ -106,9 +115,15 @@ static void __init bmips_smp_setup(void) if (!board_ebase_setup) board_ebase_setup = &bmips_ebase_setup; + __cpu_number_map[boot_cpu] = 0; + __cpu_logical_map[0] = boot_cpu; + for (i = 0; i < max_cpus; i++) { - __cpu_number_map[i] = 1; - __cpu_logical_map[i] = 1; + if (i != boot_cpu) { + __cpu_number_map[i] = cpu; + __cpu_logical_map[cpu] = i; + cpu++; + } set_cpu_possible(i, 1); set_cpu_present(i, 1); } @@ -157,7 +172,9 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle) bmips_send_ipi_single(cpu, 0); else { #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) - set_c0_brcm_cmt_ctrl(0x01); + /* Reset slave TP1 if booting from TP0 */ + if (cpu_logical_map(cpu) == 0) + set_c0_brcm_cmt_ctrl(0x01); #elif defined(CONFIG_CPU_BMIPS5000) if (cpu & 0x01) write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); -- cgit v0.10.2 From fc192e50f868d8f34b15a18c38407f4b9468a31d Mon Sep 17 00:00:00 2001 From: Tony Wu Date: Fri, 21 Jun 2013 10:10:46 +0000 Subject: MIPS: Cleanup indentation and whitespace Signed-off-by: Tony Wu Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5536/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 8e0c125..1dc0860 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -97,13 +97,13 @@ #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) #endif #ifndef cpu_has_mdmx -#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) +#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) #endif #ifndef cpu_has_mips3d -#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) +#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) #endif #ifndef cpu_has_smartmips -#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) +#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) #endif #ifndef cpu_has_rixi #define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) @@ -125,7 +125,7 @@ #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) #endif #ifndef cpu_has_pindexed_dcache -#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) +#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) #endif #ifndef cpu_has_local_ebase #define cpu_has_local_ebase 1 @@ -162,18 +162,18 @@ #ifndef cpu_has_mips_5 # define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) #endif -# ifndef cpu_has_mips32r1 +#ifndef cpu_has_mips32r1 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) -# endif -# ifndef cpu_has_mips32r2 +#endif +#ifndef cpu_has_mips32r2 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) -# endif -# ifndef cpu_has_mips64r1 +#endif +#ifndef cpu_has_mips64r1 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) -# endif -# ifndef cpu_has_mips64r2 +#endif +#ifndef cpu_has_mips64r2 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) -# endif +#endif /* * Shortcuts ... @@ -195,9 +195,9 @@ * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. */ -# ifndef cpu_has_clo_clz -# define cpu_has_clo_clz cpu_has_mips_r -# endif +#ifndef cpu_has_clo_clz +#define cpu_has_clo_clz cpu_has_mips_r +#endif #ifndef cpu_has_dsp #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) @@ -223,7 +223,7 @@ # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) # endif # ifndef cpu_has_64bit_zero_reg -# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) +# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) # endif # ifndef cpu_has_64bit_gp_regs # define cpu_has_64bit_gp_regs 0 diff --git a/arch/mips/include/asm/mach-generic/kernel-entry-init.h b/arch/mips/include/asm/mach-generic/kernel-entry-init.h index 7e66505..13b0751 100644 --- a/arch/mips/include/asm/mach-generic/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-generic/kernel-entry-init.h @@ -12,8 +12,8 @@ /* Intentionally empty macro, used in head.S. Override in * arch/mips/mach-xxx/kernel-entry-init.h when necessary. */ -.macro kernel_entry_setup -.endm + .macro kernel_entry_setup + .endm /* * Do SMP slave processor setup necessary before we can savely execute C code. diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 016dc4b..3605b84 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -244,8 +244,8 @@ struct thread_struct { unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ unsigned long error_code; #ifdef CONFIG_CPU_CAVIUM_OCTEON - struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); - struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); + struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); + struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); #endif #ifdef CONFIG_CPU_XLP struct nlm_cop2_state cp2; diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c index 46c2ad0..4d78bf4 100644 --- a/arch/mips/kernel/branch.c +++ b/arch/mips/kernel/branch.c @@ -467,5 +467,4 @@ unaligned: printk("%s: unaligned epc - sending SIGBUS.\n", current->comm); force_sig(SIGBUS, current); return -EFAULT; - } diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 3eaa02a..8eaf310 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -1549,6 +1549,7 @@ sigill: ("Unhandled kernel unaligned access or invalid instruction", regs); force_sig(SIGILL, current); } + asmlinkage void do_ade(struct pt_regs *regs) { enum ctx_state prev_state; diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 4eb8dcf..2c0bd58 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -232,7 +232,7 @@ static inline void __cpuinit build_clear_pref(u32 **buf, int off) uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0); } - } + } } extern u32 __clear_page_start; -- cgit v0.10.2 From 42a111797e8fa961d6168922e873d6b4be87e904 Mon Sep 17 00:00:00 2001 From: Tony Wu Date: Fri, 21 Jun 2013 10:09:23 +0000 Subject: MIPS: Fix typos and cleanup comment Signed-off-by: Tony Wu Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5535/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index 7153b32..b2e3e93 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h @@ -347,7 +347,7 @@ struct gic_shared_intr_map { #define GIC_CPU_INT2 2 /* . */ #define GIC_CPU_INT3 3 /* . */ #define GIC_CPU_INT4 4 /* . */ -#define GIC_CPU_INT5 5 /* Core Interrupt 5 */ +#define GIC_CPU_INT5 5 /* Core Interrupt 7 */ /* Local GIC interrupts. */ #define GIC_INT_TMR (GIC_CPU_INT5) diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 7d62894..ddc7610 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -207,9 +207,6 @@ unsigned long __stack_chk_guard __read_mostly; EXPORT_SYMBOL(__stack_chk_guard); #endif -/* - * - */ struct mips_frame_info { void *func; unsigned long func_size; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 4712f3c..357e0fd 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -972,7 +972,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) uasm_i_srl(p, ptr, ptr, 19); #else /* - * smp_processor_id() << 3 is stored in CONTEXT. + * smp_processor_id() << 2 is stored in CONTEXT. */ uasm_i_mfc0(p, ptr, C0_CONTEXT); UASM_i_LA_mostly(p, tmp, pgdc); -- cgit v0.10.2 From 74338805ec6869594d583535f941cb478c94dd73 Mon Sep 17 00:00:00 2001 From: David Daney Date: Fri, 24 May 2013 20:54:08 +0000 Subject: MIPS: Declare emulate_load_store_microMIPS as a static function. It is only used from within a single file, it should not be globally visible. Signed-off-by: David Daney Acked-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5325/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 8eaf310..c369a5d 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -685,7 +685,8 @@ const int reg16to32[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; /* Recode table from 16-bit STORE register notation to 32-bit GPR. */ const int reg16to32st[] = { 0, 17, 2, 3, 4, 5, 6, 7 }; -void emulate_load_store_microMIPS(struct pt_regs *regs, void __user * addr) +static void emulate_load_store_microMIPS(struct pt_regs *regs, + void __user *addr) { unsigned long value; unsigned int res; -- cgit v0.10.2 From fe6d29095d4370bed3a525404c45bbd6aa7c191b Mon Sep 17 00:00:00 2001 From: David Daney Date: Fri, 24 May 2013 20:54:09 +0000 Subject: MIPS: Don't try to decode microMIPS branch instructions where they cannot exist. In mm_isBranchInstr() we can short circuit the entire function if !cpu_has_mmips. Signed-off-by: David Daney Acked-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5326/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index f03771900..e773659 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -471,6 +471,9 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, unsigned int fcr31; unsigned int bit; + if (!cpu_has_mmips) + return 0; + switch (insn.mm_i_format.opcode) { case mm_pool32a_op: if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) == -- cgit v0.10.2 From c6213c6c9c189aeb97010673e3129a8929d2223e Mon Sep 17 00:00:00 2001 From: "Steven J. Hill" Date: Wed, 5 Jun 2013 21:25:17 +0000 Subject: MIPS: microMIPS: Fix improper definition of ISA exception bit. The ISA exception bit selects whether exceptions are taken in classic or microMIPS mode. This bit is Config3.ISAOnExc and was improperly defined as bits 16 and 17 instead of just bit 16. A new function was added so that platforms could set this bit when running a kernel compiled with only microMIPS instructions. Signed-off-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5377/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 87e6207..fed1c3e 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -596,7 +596,7 @@ #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) -#define MIPS_CONF3_ISA_OE (_ULCAST_(3) << 16) +#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f87039d..c7b1b3c 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -269,9 +269,6 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) c->options |= MIPS_CPU_ULRI; if (config3 & MIPS_CONF3_ISA) c->options |= MIPS_CPU_MICROMIPS; -#ifdef CONFIG_CPU_MICROMIPS - write_c0_config3(read_c0_config3() | MIPS_CONF3_ISA_OE); -#endif if (config3 & MIPS_CONF3_VZ) c->ases |= MIPS_ASE_VZ; diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index d97ea23..b0f3ad2 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1878,6 +1878,15 @@ void __init trap_init(void) ebase += (read_c0_ebase() & 0x3ffff000); } + if (cpu_has_mmips) { + unsigned int config3 = read_c0_config3(); + + if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) + write_c0_config3(config3 | MIPS_CONF3_ISA_OE); + else + write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); + } + if (board_ebase_setup) board_ebase_setup(); per_cpu_trap_init(true); -- cgit v0.10.2 From 271792eff2a272b527ce5aa74d499e346fb851de Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Mon, 17 Jun 2013 13:00:40 +0000 Subject: SSB: Kconfig: Amend SSB_EMBEDDED dependencies SSB_EMBEDDED needs functions from driver_pcicore which are only available if SSD_DRIVER_HOSTMODE is selected so make it depend on that symbol. Fixes the following linking problem: drivers/ssb/embedded.c:202: undefined reference to `ssb_pcicore_plat_dev_init' drivers/built-in.o: In function `ssb_pcibios_map_irq': drivers/ssb/embedded.c:247: undefined reference to `ssb_pcicore_pcibios_map_irq' Signed-off-by: Markos Chandras Acked-by: Steven J. Hill Cc: sibyte-users@bitmover.com Cc: netdev@vger.kernel.org Cc: Michael Buesch Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5484/ Acked-by: Florian Fainelli Signed-off-by: Ralf Baechle diff --git a/drivers/ssb/Kconfig b/drivers/ssb/Kconfig index 5ff3a4f..36171fd 100644 --- a/drivers/ssb/Kconfig +++ b/drivers/ssb/Kconfig @@ -144,7 +144,7 @@ config SSB_SFLASH # Assumption: We are on embedded, if we compile the MIPS core. config SSB_EMBEDDED bool - depends on SSB_DRIVER_MIPS + depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE default y config SSB_DRIVER_EXTIF -- cgit v0.10.2 From 4287f7915f33c1eb770e22589936cd9cd8a60b45 Mon Sep 17 00:00:00 2001 From: Deng-Cheng Zhu Date: Mon, 8 Apr 2013 15:53:00 +0000 Subject: MIPS: APSP: Remove Now that KSPD is gone, kspd.h has no reason to be there. Signed-off-by: Deng-Cheng Zhu Cc: Steven J. Hill Cc: linux-mips@linux-mips.org Cc: kevink@paralogos.com Cc: macro@linux-mips.org Cc: john@phrozen.org Patchwork: https://patchwork.linux-mips.org/patch/5060/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/kspd.h b/arch/mips/include/asm/kspd.h deleted file mode 100644 index ec68329..0000000 --- a/arch/mips/include/asm/kspd.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - */ - -#ifndef _ASM_KSPD_H -#define _ASM_KSPD_H - -struct kspd_notifications { - void (*kspd_sp_exit)(int sp_id); - - struct list_head list; -}; - -static inline void kspd_notify(struct kspd_notifications *notify) -{ -} - -#endif -- cgit v0.10.2 From ed3ce16c3d2ba7cac321d29ec0a7d21408ea8437 Mon Sep 17 00:00:00 2001 From: Leonid Yegoshin Date: Thu, 20 Jun 2013 14:36:30 +0000 Subject: Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET" This reverts commit 3f4579252aa166641861a64f1c2883365ca126c2. It is invalid because the macros CAC_ADDR and UNCAC_ADDR have a kernel virtual address as an argument and also returns a kernel virtual address. Using and physical address PHYS_OFFSET is blatantly wrong for a macro common to multiple platforms. Signed-off-by: Leonid Yegoshin Acked-by: Steven J. Hill Cc: linux-mips@linux-mips.org Cc: Florian Fainelli Patchwork: https://patchwork.linux-mips.org/patch/5528/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/mach-ar7/spaces.h b/arch/mips/include/asm/mach-ar7/spaces.h index ac28f27..660ab64 100644 --- a/arch/mips/include/asm/mach-ar7/spaces.h +++ b/arch/mips/include/asm/mach-ar7/spaces.h @@ -14,8 +14,11 @@ * This handles the memory map. * We handle pages at KSEG0 for kernels with 32 bit address space. */ -#define PAGE_OFFSET 0x94000000UL -#define PHYS_OFFSET 0x14000000UL +#define PAGE_OFFSET _AC(0x94000000, UL) +#define PHYS_OFFSET _AC(0x14000000, UL) + +#define UNCAC_BASE _AC(0xb4000000, UL) /* 0xa0000000 + PHYS_OFFSET */ +#define IO_BASE UNCAC_BASE #include diff --git a/arch/mips/include/asm/mach-ip28/spaces.h b/arch/mips/include/asm/mach-ip28/spaces.h index 5edf05d..5d6a764 100644 --- a/arch/mips/include/asm/mach-ip28/spaces.h +++ b/arch/mips/include/asm/mach-ip28/spaces.h @@ -11,11 +11,14 @@ #ifndef _ASM_MACH_IP28_SPACES_H #define _ASM_MACH_IP28_SPACES_H -#define CAC_BASE 0xa800000000000000 +#define CAC_BASE _AC(0xa800000000000000, UL) -#define HIGHMEM_START (~0UL) +#define HIGHMEM_START (~0UL) -#define PHYS_OFFSET _AC(0x20000000, UL) +#define PHYS_OFFSET _AC(0x20000000, UL) + +#define UNCAC_BASE _AC(0xc0000000, UL) /* 0xa0000000 + PHYS_OFFSET */ +#define IO_BASE UNCAC_BASE #include diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index f59552f..f6be474 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -205,10 +205,8 @@ extern int __virt_addr_valid(const volatile void *kaddr); #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) -#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE + \ - PHYS_OFFSET) -#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET - \ - PHYS_OFFSET) +#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE) +#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET) #include #include -- cgit v0.10.2 From 78276207a70e805cc022364218eefb8aa05ea647 Mon Sep 17 00:00:00 2001 From: Leonid Yegoshin Date: Thu, 20 Jun 2013 14:36:42 +0000 Subject: MIPS: Malta: Update GCMP detection. Add GCMP detection for IASim Marvell chip emulation support. Signed-off-by: Leonid Yegoshin Acked-by: Steven J. Hill Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin Patchwork: https://patchwork.linux-mips.org/patch/5529/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index 0a1339a..c69da37 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -422,8 +422,10 @@ static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { */ int __init gcmp_probe(unsigned long addr, unsigned long size) { - if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) { + if ((mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) && + (mips_revision_sconid != MIPS_REVISION_SCON_GT64120)) { gcmp_present = 0; + pr_debug("GCMP NOT present\n"); return gcmp_present; } -- cgit v0.10.2 From 78857614104a26cdada4c53eea104752042bf5a1 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Mon, 17 Jun 2013 08:09:00 +0000 Subject: MIPS: Expose missing pci_io{map,unmap} declarations The GENERIC_PCI_IOMAP does not depend on CONFIG_PCI so move it to the CONFIG_MIPS symbol so it's always selected for MIPS. This fixes the missing pci_iomap declaration for MIPS. Moreover, the pci_iounmap function was not defined in the io.h header file if the CONFIG_PCI symbol is not set, but it should since MIPS is not using CONFIG_GENERIC_IOMAP. This fixes the following problem on a allyesconfig: drivers/net/ethernet/3com/3c59x.c:1031:2: error: implicit declaration of function 'pci_iomap' [-Werror=implicit-function-declaration] drivers/net/ethernet/3com/3c59x.c:1044:3: error: implicit declaration of function 'pci_iounmap' [-Werror=implicit-function-declaration] Signed-off-by: Markos Chandras Acked-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5478/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ba63cdb..3a3e54c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -28,6 +28,7 @@ config MIPS select HAVE_GENERIC_HARDIRQS select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW + select GENERIC_PCI_IOMAP select HAVE_ARCH_JUMP_LABEL select ARCH_WANT_IPC_PARSE_VERSION select IRQ_FORCED_THREADING @@ -2391,7 +2392,6 @@ config PCI bool "Support for PCI controller" depends on HW_HAS_PCI select PCI_DOMAINS - select GENERIC_PCI_IOMAP select NO_GENERIC_PCI_IOPORT_MAP help Find out whether you have a PCI motherboard. PCI is the name of a diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index b7e5985..b84e1fb 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -170,6 +170,11 @@ static inline void * isa_bus_to_virt(unsigned long address) extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags); extern void __iounmap(const volatile void __iomem *addr); +#ifndef CONFIG_PCI +struct pci_dev; +static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {} +#endif + static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, unsigned long flags) { -- cgit v0.10.2 From edd4201ebc2f1a7ab2158ad91ddc0af71e58dce7 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 31 May 2013 13:07:44 +0000 Subject: MIPS: define write{b,w,l,q}_relaxed MIPS does define read{b,w,l,q}_relaxed but does not define their write counterparts: write{b,w,l,q}_relaxed. This patch adds the missing definitions for the write*_relaxed I/O accessors. Signed-off-by: Florian Fainelli Acked-by: John Crispin Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/5352/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index b84e1fb..3321dd5 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -454,6 +454,11 @@ __BUILDIO(q, u64) #define readl_relaxed readl #define readq_relaxed readq +#define writeb_relaxed writeb +#define writew_relaxed writew +#define writel_relaxed writel +#define writeq_relaxed writeq + #define readb_be(addr) \ __raw_readb((__force unsigned *)(addr)) #define readw_be(addr) \ -- cgit v0.10.2 From a068dde168e0c618e1dc2151a0922254ec3bbf04 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Tue, 18 Jun 2013 08:34:31 +0000 Subject: MIPS: BCM63xx: Add SMP support to prom.c This involves two changes to the BSP code: 1) register_smp_ops() for BMIPS SMP 2) The CPU1 boot vector on some of the BCM63xx platforms conflicts with the special interrupt vector (IV). Move it to 0x8000_0380 at boot time, to resolve the conflict. Signed-off-by: Kevin Cernekee [jogo@openwrt.org: moved SMP ops registration into ifdef guard, changed ifdef guards to if (IS_ENABLED())] Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Patchwork: https://patchwork.linux-mips.org/patch/5489/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c index f3ff28f..3b21454 100644 --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -8,7 +8,11 @@ #include #include +#include #include +#include +#include +#include #include #include #include @@ -54,6 +58,43 @@ void __init prom_init(void) /* do low level board init */ board_prom_init(); + + if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) { + /* set up SMP */ + register_smp_ops(&bmips_smp_ops); + + /* + * BCM6328 might not have its second CPU enabled, while BCM6358 + * needs special handling for its shared TLB, so disable SMP + * for now. + */ + if (BCMCPU_IS_6328()) { + bmips_smp_enabled = 0; + } else if (BCMCPU_IS_6358()) { + bmips_smp_enabled = 0; + } + + if (!bmips_smp_enabled) + return; + + /* + * The bootloader has set up the CPU1 reset vector at + * 0xa000_0200. + * This conflicts with the special interrupt vector (IV). + * The bootloader has also set up CPU1 to respond to the wrong + * IPI interrupt. + * Here we will start up CPU1 in the background and ask it to + * reconfigure itself then go back to sleep. + */ + memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20); + __sync(); + set_c0_cause(C_SW0); + cpumask_set_cpu(1, &bmips_booted_mask); + + /* + * FIXME: we really should have some sort of hazard barrier here + */ + } } void __init prom_free_prom_memory(void) -- cgit v0.10.2 From 7ac836ce2aa7b931f6347e554cb65f9e9cc1da57 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Tue, 18 Jun 2013 08:34:32 +0000 Subject: MIPS: BCM63xx: Enable second core SMP on BCM6328 if available BCM6328 has a OTP which tells us if the second core is available. Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: John Crispin Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Patchwork: https://patchwork.linux-mips.org/patch/5490/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c index 3b21454..8ac4e09 100644 --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -69,7 +69,11 @@ void __init prom_init(void) * for now. */ if (BCMCPU_IS_6328()) { - bmips_smp_enabled = 0; + reg = bcm_readl(BCM_6328_OTP_BASE + + OTP_USER_BITS_6328_REG(3)); + + if (reg & OTP_6328_REG3_TP1_DISABLED) + bmips_smp_enabled = 0; } else if (BCMCPU_IS_6358()) { bmips_smp_enabled = 0; } diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index 9d3c08e..22390a2 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -296,6 +296,8 @@ enum bcm63xx_regs_set { #define BCM_6328_PCMDMAS_BASE (0xdeadbeef) #define BCM_6328_RNG_BASE (0xdeadbeef) #define BCM_6328_MISC_BASE (0xb0001800) +#define BCM_6328_OTP_BASE (0xb0000600) + /* * 6338 register sets base address */ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 6542137..018628f 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -1477,4 +1477,11 @@ #define PCIE_DEVICE_OFFSET 0x8000 +/************************************************************************* + * _REG relative to RSET_OTP + *************************************************************************/ + +#define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4) +#define OTP_6328_REG3_TP1_DISABLED BIT(9) + #endif /* BCM63XX_REGS_H_ */ -- cgit v0.10.2 From 1535ac096d26538888d00881f5026cbc8b6dc20d Mon Sep 17 00:00:00 2001 From: "Steven J. Hill" Date: Thu, 27 Jun 2013 15:27:59 +0000 Subject: MIPS: SEAD3: Disable L2 cache on SEAD-3. The cores used on the SEAD-3 platform do not have L2 caches, so this option should not be turned on. Originally fixed on public 'linux-mti-3.8' release branch. Signed-off-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5559/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3a3e54c..567c45b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -342,7 +342,6 @@ config MIPS_SEAD3 select DMA_NONCOHERENT select IRQ_CPU select IRQ_GIC - select MIPS_CPU_SCACHE select MIPS_MSC select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 -- cgit v0.10.2 From 7aa2d05299f92ab73591988ab514f0ddc98138f3 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Tue, 2 Jul 2013 09:13:44 +0000 Subject: MIPS: BCM63xx: CLK: Add dummy clk_{set,round}_rate() functions Several drivers use the clk_{set,round}_rate() functions that need to be defined in the platform's clock code. The Broadcom BCM63xx platform hardcodes the clock rate so we create new clk_{set,round}_rate() functions which just return 0 like those in include/linux/clk.h for the common clock framework do. Also fixes the following build problem on a randconfig: drivers/built-in.o: In function `nop_usb_xceiv_probe': phy-nop.c:(.text+0x3ec26c): undefined reference to `clk_set_rate' Signed-off-by: Markos Chandras Acked-by: Steven J. Hill Acked-by: Florian Fainelli Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5580/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c index fda2690..43da4ae 100644 --- a/arch/mips/bcm63xx/clk.c +++ b/arch/mips/bcm63xx/clk.c @@ -318,6 +318,18 @@ unsigned long clk_get_rate(struct clk *clk) EXPORT_SYMBOL(clk_get_rate); +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + return 0; +} +EXPORT_SYMBOL_GPL(clk_set_rate); + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + return 0; +} +EXPORT_SYMBOL_GPL(clk_round_rate); + struct clk *clk_get(struct device *dev, const char *id) { if (!strcmp(id, "enet0")) -- cgit v0.10.2 From 704e6460ab75af0735b1ca7c0dcaa4ff0a4001b2 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Fri, 28 Jun 2013 11:25:27 +0000 Subject: MIPS: Kconfig: Add missing MODULES dependency to VPE_LOADER The vpe.c code uses the 'struct module' which is only available if CONFIG_MODULES is selected. Also fixes the following build problem on a lantiq allmodconfig: In file included from arch/mips/kernel/vpe.c:41:0: include/linux/moduleloader.h: In function 'apply_relocate': include/linux/moduleloader.h:48:63: error: dereferencing pointer to incomplete type include/linux/moduleloader.h: In function 'apply_relocate_add': include/linux/moduleloader.h:70:63: error: dereferencing pointer to incomplete type Signed-off-by: Markos Chandras Reviewed-by: James Hogan Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5562/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 567c45b..1e7a40e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1929,7 +1929,7 @@ config MIPS_MT_FPAFF config MIPS_VPE_LOADER bool "VPE loader support." - depends on SYS_SUPPORTS_MULTITHREADING + depends on SYS_SUPPORTS_MULTITHREADING && MODULES select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI select MIPS_MT -- cgit v0.10.2