From 6e30de84ab7c34eaaed13985b501a4fcb5d15c8b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Thu, 21 May 2009 21:13:12 +0200 Subject: IXP4xx: change the timer base frequency to 66.666000 MHz. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clock generators used by IXP4xx processors are usually 33.333 MHz, sometimes 33.33 MHz and few platforms use 33 MHz. The timers tick twice as fast, that means 66.666, 66.66 or 66 MHz. Current 66.666666 MHz means 10 ppm offset from the usual 66.666 MHz. Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/include/mach/timex.h b/arch/arm/mach-ixp4xx/include/mach/timex.h index 89ce3ee..2c3f93c 100644 --- a/arch/arm/mach-ixp4xx/include/mach/timex.h +++ b/arch/arm/mach-ixp4xx/include/mach/timex.h @@ -10,6 +10,6 @@ * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the * timer register ignores the bottom 2 bits of the LATCH value. */ -#define FREQ 66666666 +#define FREQ 66666000 #define CLOCK_TICK_RATE (((FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ) -- cgit v0.10.2 From 8ae45a535b172d350759eec2fcecf4368d4c13d1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Sun, 18 Oct 2009 21:03:08 +0200 Subject: IXP4xx: Fix normally-disabled debugging text in drivers/net/arm/ixp4xx_eth.c. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Hałasa diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c index 691b81e..c3dfbdd 100644 --- a/drivers/net/arm/ixp4xx_eth.c +++ b/drivers/net/arm/ixp4xx_eth.c @@ -322,7 +322,7 @@ static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location, ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val); spin_unlock_irqrestore(&mdio_lock, flags); #if DEBUG_MDIO - printk(KERN_DEBUG "%s #%i: MII read [%i] <- 0x%X, err = %i\n", + printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n", bus->name, phy_id, location, val, ret); #endif return ret; -- cgit v0.10.2 From 9f2c94928a0d713d223b53909734877fe4f340ab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Wed, 11 Nov 2009 00:21:48 +0100 Subject: ARM: fix insl() and outsl() endianness on IXP4xx architecture. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The repetitive in/out functions must preserve order, not value. Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h index 8a947d4..eb9c748 100644 --- a/arch/arm/mach-ixp4xx/include/mach/io.h +++ b/arch/arm/mach-ixp4xx/include/mach/io.h @@ -311,7 +311,7 @@ static inline void __ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count) { while (count--) - outl(*vaddr++, io_addr); + outl(cpu_to_le32(*vaddr++), io_addr); } static inline u8 @@ -366,7 +366,7 @@ static inline void __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count) { while (count--) - *vaddr++ = inl(io_addr); + *vaddr++ = le32_to_cpu(inl(io_addr)); } #define PIO_OFFSET 0x10000UL @@ -374,12 +374,13 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count) #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) + static inline unsigned int __ixp4xx_ioread8(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - return (unsigned int)__ixp4xx_inb(port & PIO_MASK); + return (unsigned int)__ixp4xx_inb(port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI return (unsigned int)__raw_readb(port); -- cgit v0.10.2 From efec194f576eebca8b0b3ac6e96fea05ae4567c9 Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Tue, 3 Nov 2009 23:05:32 +0100 Subject: IXP4xx: Ensure index is positive in irq_to_gpio() and npe_request(). MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The indexes were signed, so negatives were possible. Signed-off-by: Roel Kluin Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index cfd52fb..3bbf40f 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -117,7 +117,7 @@ int gpio_to_irq(int gpio) } EXPORT_SYMBOL(gpio_to_irq); -int irq_to_gpio(int irq) +int irq_to_gpio(unsigned int irq) { int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL; diff --git a/arch/arm/mach-ixp4xx/include/mach/gpio.h b/arch/arm/mach-ixp4xx/include/mach/gpio.h index cd5aec2..a5f87de 100644 --- a/arch/arm/mach-ixp4xx/include/mach/gpio.h +++ b/arch/arm/mach-ixp4xx/include/mach/gpio.h @@ -70,7 +70,7 @@ static inline void gpio_set_value(unsigned gpio, int value) #include /* cansleep wrappers */ extern int gpio_to_irq(int gpio); -extern int irq_to_gpio(int gpio); +extern int irq_to_gpio(unsigned int irq); #endif diff --git a/arch/arm/mach-ixp4xx/include/mach/npe.h b/arch/arm/mach-ixp4xx/include/mach/npe.h index 37d0511..e320db2 100644 --- a/arch/arm/mach-ixp4xx/include/mach/npe.h +++ b/arch/arm/mach-ixp4xx/include/mach/npe.h @@ -33,7 +33,7 @@ int npe_send_message(struct npe *npe, const void *msg, const char *what); int npe_recv_message(struct npe *npe, void *msg, const char *what); int npe_send_recv_message(struct npe *npe, void *msg, const char *what); int npe_load_firmware(struct npe *npe, const char *name, struct device *dev); -struct npe *npe_request(int id); +struct npe *npe_request(unsigned id); void npe_release(struct npe *npe); #endif /* __IXP4XX_NPE_H */ diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c index 47ac69c..e8bb257 100644 --- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c +++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c @@ -665,7 +665,7 @@ err: } -struct npe *npe_request(int id) +struct npe *npe_request(unsigned id) { if (id < NPE_COUNT) if (npe_tab[id].valid) -- cgit v0.10.2 From 28f85cd3f65808cde50bb0e395043f38c3efa1cb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Sat, 14 Nov 2009 19:44:44 +0100 Subject: IXP4xx: Rename indirect MMIO primitives from __ixp4xx_* to __indirect_*. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h index eb9c748..061a1f1 100644 --- a/arch/arm/mach-ixp4xx/include/mach/io.h +++ b/arch/arm/mach-ixp4xx/include/mach/io.h @@ -55,8 +55,8 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); * access registers. If something outside of PCI is ioremap'd, we * fallback to the default. */ -static inline void __iomem * -__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype) +static inline void __iomem * __indirect_ioremap(unsigned long addr, size_t size, + unsigned int mtype) { if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff)) return __arm_ioremap(addr, size, mtype); @@ -64,34 +64,32 @@ __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype) return (void __iomem *)addr; } -static inline void -__ixp4xx_iounmap(void __iomem *addr) +static inline void __indirect_iounmap(void __iomem *addr) { if ((__force u32)addr >= VMALLOC_START) __iounmap(addr); } -#define __arch_ioremap(a, s, f) __ixp4xx_ioremap(a, s, f) -#define __arch_iounmap(a) __ixp4xx_iounmap(a) +#define __arch_ioremap(a, s, f) __indirect_ioremap(a, s, f) +#define __arch_iounmap(a) __indirect_iounmap(a) -#define writeb(v, p) __ixp4xx_writeb(v, p) -#define writew(v, p) __ixp4xx_writew(v, p) -#define writel(v, p) __ixp4xx_writel(v, p) +#define writeb(v, p) __indirect_writeb(v, p) +#define writew(v, p) __indirect_writew(v, p) +#define writel(v, p) __indirect_writel(v, p) -#define writesb(p, v, l) __ixp4xx_writesb(p, v, l) -#define writesw(p, v, l) __ixp4xx_writesw(p, v, l) -#define writesl(p, v, l) __ixp4xx_writesl(p, v, l) - -#define readb(p) __ixp4xx_readb(p) -#define readw(p) __ixp4xx_readw(p) -#define readl(p) __ixp4xx_readl(p) - -#define readsb(p, v, l) __ixp4xx_readsb(p, v, l) -#define readsw(p, v, l) __ixp4xx_readsw(p, v, l) -#define readsl(p, v, l) __ixp4xx_readsl(p, v, l) +#define writesb(p, v, l) __indirect_writesb(p, v, l) +#define writesw(p, v, l) __indirect_writesw(p, v, l) +#define writesl(p, v, l) __indirect_writesl(p, v, l) -static inline void -__ixp4xx_writeb(u8 value, volatile void __iomem *p) +#define readb(p) __indirect_readb(p) +#define readw(p) __indirect_readw(p) +#define readl(p) __indirect_readl(p) + +#define readsb(p, v, l) __indirect_readsb(p, v, l) +#define readsw(p, v, l) __indirect_readsw(p, v, l) +#define readsl(p, v, l) __indirect_readsl(p, v, l) + +static inline void __indirect_writeb(u8 value, volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; @@ -107,15 +105,14 @@ __ixp4xx_writeb(u8 value, volatile void __iomem *p) ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); } -static inline void -__ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count) +static inline void __indirect_writesb(volatile void __iomem *bus_addr, + const u8 *vaddr, int count) { while (count--) writeb(*vaddr++, bus_addr); } -static inline void -__ixp4xx_writew(u16 value, volatile void __iomem *p) +static inline void __indirect_writew(u16 value, volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; @@ -131,15 +128,14 @@ __ixp4xx_writew(u16 value, volatile void __iomem *p) ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); } -static inline void -__ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count) +static inline void __indirect_writesw(volatile void __iomem *bus_addr, + const u16 *vaddr, int count) { while (count--) writew(*vaddr++, bus_addr); } -static inline void -__ixp4xx_writel(u32 value, volatile void __iomem *p) +static inline void __indirect_writel(u32 value, volatile void __iomem *p) { u32 addr = (__force u32)p; if (addr >= VMALLOC_START) { @@ -150,15 +146,14 @@ __ixp4xx_writel(u32 value, volatile void __iomem *p) ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value); } -static inline void -__ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count) +static inline void __indirect_writesl(volatile void __iomem *bus_addr, + const u32 *vaddr, int count) { while (count--) writel(*vaddr++, bus_addr); } -static inline unsigned char -__ixp4xx_readb(const volatile void __iomem *p) +static inline unsigned char __indirect_readb(const volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; @@ -174,15 +169,14 @@ __ixp4xx_readb(const volatile void __iomem *p) return data >> (8*n); } -static inline void -__ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count) +static inline void __indirect_readsb(const volatile void __iomem *bus_addr, + u8 *vaddr, u32 count) { while (count--) *vaddr++ = readb(bus_addr); } -static inline unsigned short -__ixp4xx_readw(const volatile void __iomem *p) +static inline unsigned short __indirect_readw(const volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; @@ -198,15 +192,14 @@ __ixp4xx_readw(const volatile void __iomem *p) return data>>(8*n); } -static inline void -__ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count) +static inline void __indirect_readsw(const volatile void __iomem *bus_addr, + u16 *vaddr, u32 count) { while (count--) *vaddr++ = readw(bus_addr); } -static inline unsigned long -__ixp4xx_readl(const volatile void __iomem *p) +static inline unsigned long __indirect_readl(const volatile void __iomem *p) { u32 addr = (__force u32)p; u32 data; @@ -220,8 +213,8 @@ __ixp4xx_readl(const volatile void __iomem *p) return data; } -static inline void -__ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) +static inline void __indirect_readsl(const volatile void __iomem *bus_addr, + u32 *vaddr, u32 count) { while (count--) *vaddr++ = readl(bus_addr); @@ -235,7 +228,7 @@ __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) #define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l)) #define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l)) -#endif +#endif /* CONFIG_IXP4XX_INDIRECT_PCI */ #ifndef CONFIG_PCI @@ -385,7 +378,7 @@ __ixp4xx_ioread8(const void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI return (unsigned int)__raw_readb(port); #else - return (unsigned int)__ixp4xx_readb(addr); + return (unsigned int)__indirect_readb(addr); #endif } @@ -399,7 +392,7 @@ __ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsb(addr, vaddr, count); #else - __ixp4xx_readsb(addr, vaddr, count); + __indirect_readsb(addr, vaddr, count); #endif } @@ -413,7 +406,7 @@ __ixp4xx_ioread16(const void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le16_to_cpu(__raw_readw((u32)port)); #else - return (unsigned int)__ixp4xx_readw(addr); + return (unsigned int)__indirect_readw(addr); #endif } @@ -427,7 +420,7 @@ __ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsw(addr, vaddr, count); #else - __ixp4xx_readsw(addr, vaddr, count); + __indirect_readsw(addr, vaddr, count); #endif } @@ -441,7 +434,7 @@ __ixp4xx_ioread32(const void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le32_to_cpu((__force __le32)__raw_readl(addr)); #else - return (unsigned int)__ixp4xx_readl(addr); + return (unsigned int)__indirect_readl(addr); #endif } } @@ -456,7 +449,7 @@ __ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsl(addr, vaddr, count); #else - __ixp4xx_readsl(addr, vaddr, count); + __indirect_readsl(addr, vaddr, count); #endif } @@ -470,7 +463,7 @@ __ixp4xx_iowrite8(u8 value, void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writeb(value, port); #else - __ixp4xx_writeb(value, addr); + __indirect_writeb(value, addr); #endif } @@ -484,7 +477,7 @@ __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesb(addr, vaddr, count); #else - __ixp4xx_writesb(addr, vaddr, count); + __indirect_writesb(addr, vaddr, count); #endif } @@ -498,7 +491,7 @@ __ixp4xx_iowrite16(u16 value, void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writew(cpu_to_le16(value), addr); #else - __ixp4xx_writew(value, addr); + __indirect_writew(value, addr); #endif } @@ -512,7 +505,7 @@ __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesw(addr, vaddr, count); #else - __ixp4xx_writesw(addr, vaddr, count); + __indirect_writesw(addr, vaddr, count); #endif } @@ -526,7 +519,7 @@ __ixp4xx_iowrite32(u32 value, void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writel((u32 __force)cpu_to_le32(value), addr); #else - __ixp4xx_writel(value, addr); + __indirect_writel(value, addr); #endif } @@ -540,7 +533,7 @@ __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesl(addr, vaddr, count); #else - __ixp4xx_writesl(addr, vaddr, count); + __indirect_writesl(addr, vaddr, count); #endif } -- cgit v0.10.2 From 58e570d1182a9dc3bc52d8dc508c6bd5b2d279c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Sat, 14 Nov 2009 22:55:42 +0100 Subject: IXP4xx: Drop "__ixp4xx_" prefix from in/out/ioread/iowrite functions for clarity. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h index 061a1f1..c06d4a2 100644 --- a/arch/arm/mach-ixp4xx/include/mach/io.h +++ b/arch/arm/mach-ixp4xx/include/mach/io.h @@ -243,25 +243,8 @@ static inline void __indirect_readsl(const volatile void __iomem *bus_addr, * transaction. This means that we need to override the default * I/O functions. */ -#define outb(p, v) __ixp4xx_outb(p, v) -#define outw(p, v) __ixp4xx_outw(p, v) -#define outl(p, v) __ixp4xx_outl(p, v) - -#define outsb(p, v, l) __ixp4xx_outsb(p, v, l) -#define outsw(p, v, l) __ixp4xx_outsw(p, v, l) -#define outsl(p, v, l) __ixp4xx_outsl(p, v, l) -#define inb(p) __ixp4xx_inb(p) -#define inw(p) __ixp4xx_inw(p) -#define inl(p) __ixp4xx_inl(p) - -#define insb(p, v, l) __ixp4xx_insb(p, v, l) -#define insw(p, v, l) __ixp4xx_insw(p, v, l) -#define insl(p, v, l) __ixp4xx_insl(p, v, l) - - -static inline void -__ixp4xx_outb(u8 value, u32 addr) +static inline void outb(u8 value, u32 addr) { u32 n, byte_enables, data; n = addr % 4; @@ -270,15 +253,13 @@ __ixp4xx_outb(u8 value, u32 addr) ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); } -static inline void -__ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count) +static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count) { while (count--) outb(*vaddr++, io_addr); } -static inline void -__ixp4xx_outw(u16 value, u32 addr) +static inline void outw(u16 value, u32 addr) { u32 n, byte_enables, data; n = addr % 4; @@ -287,28 +268,24 @@ __ixp4xx_outw(u16 value, u32 addr) ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); } -static inline void -__ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count) +static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count) { while (count--) outw(cpu_to_le16(*vaddr++), io_addr); } -static inline void -__ixp4xx_outl(u32 value, u32 addr) +static inline void outl(u32 value, u32 addr) { ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value); } -static inline void -__ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count) +static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count) { while (count--) outl(cpu_to_le32(*vaddr++), io_addr); } -static inline u8 -__ixp4xx_inb(u32 addr) +static inline u8 inb(u32 addr) { u32 n, byte_enables, data; n = addr % 4; @@ -319,15 +296,13 @@ __ixp4xx_inb(u32 addr) return data >> (8*n); } -static inline void -__ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count) +static inline void insb(u32 io_addr, u8 *vaddr, u32 count) { while (count--) *vaddr++ = inb(io_addr); } -static inline u16 -__ixp4xx_inw(u32 addr) +static inline u16 inw(u32 addr) { u32 n, byte_enables, data; n = addr % 4; @@ -338,15 +313,13 @@ __ixp4xx_inw(u32 addr) return data>>(8*n); } -static inline void -__ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count) +static inline void insw(u32 io_addr, u16 *vaddr, u32 count) { while (count--) *vaddr++ = le16_to_cpu(inw(io_addr)); } -static inline u32 -__ixp4xx_inl(u32 addr) +static inline u32 inl(u32 addr) { u32 data; if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data)) @@ -355,8 +328,7 @@ __ixp4xx_inl(u32 addr) return data; } -static inline void -__ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count) +static inline void insl(u32 io_addr, u32 *vaddr, u32 count) { while (count--) *vaddr++ = le32_to_cpu(inl(io_addr)); @@ -368,12 +340,12 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count) #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) -static inline unsigned int -__ixp4xx_ioread8(const void __iomem *addr) +#define ioread8(p) ioread8(p) +static inline unsigned int ioread8(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - return (unsigned int)__ixp4xx_inb(port & PIO_MASK); + return (unsigned int)inb(port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI return (unsigned int)__raw_readb(port); @@ -382,12 +354,12 @@ __ixp4xx_ioread8(const void __iomem *addr) #endif } -static inline void -__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) +#define ioread8_rep(p, v, c) ioread8_rep(p, v, c) +static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_insb(port & PIO_MASK, vaddr, count); + insb(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsb(addr, vaddr, count); @@ -396,12 +368,12 @@ __ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) #endif } -static inline unsigned int -__ixp4xx_ioread16(const void __iomem *addr) +#define ioread16(p) ioread16(p) +static inline unsigned int ioread16(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - return (unsigned int)__ixp4xx_inw(port & PIO_MASK); + return (unsigned int)inw(port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le16_to_cpu(__raw_readw((u32)port)); @@ -410,12 +382,13 @@ __ixp4xx_ioread16(const void __iomem *addr) #endif } -static inline void -__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) +#define ioread16_rep(p, v, c) ioread16_rep(p, v, c) +static inline void ioread16_rep(const void __iomem *addr, void *vaddr, + u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_insw(port & PIO_MASK, vaddr, count); + insw(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsw(addr, vaddr, count); @@ -424,12 +397,12 @@ __ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) #endif } -static inline unsigned int -__ixp4xx_ioread32(const void __iomem *addr) +#define ioread32(p) ioread32(p) +static inline unsigned int ioread32(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - return (unsigned int)__ixp4xx_inl(port & PIO_MASK); + return (unsigned int)inl(port & PIO_MASK); else { #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le32_to_cpu((__force __le32)__raw_readl(addr)); @@ -439,12 +412,13 @@ __ixp4xx_ioread32(const void __iomem *addr) } } -static inline void -__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) +#define ioread32_rep(p, v, c) ioread32_rep(p, v, c) +static inline void ioread32_rep(const void __iomem *addr, void *vaddr, + u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_insl(port & PIO_MASK, vaddr, count); + insl(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsl(addr, vaddr, count); @@ -453,12 +427,12 @@ __ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) #endif } -static inline void -__ixp4xx_iowrite8(u8 value, void __iomem *addr) +#define iowrite8(v, p) iowrite8(v, p) +static inline void iowrite8(u8 value, void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_outb(value, port & PIO_MASK); + outb(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writeb(value, port); @@ -467,12 +441,13 @@ __ixp4xx_iowrite8(u8 value, void __iomem *addr) #endif } -static inline void -__ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) +#define iowrite8_rep(p, v, c) iowrite8_rep(p, v, c) +static inline void iowrite8_rep(void __iomem *addr, const void *vaddr, + u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_outsb(port & PIO_MASK, vaddr, count); + outsb(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesb(addr, vaddr, count); @@ -481,12 +456,12 @@ __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) #endif } -static inline void -__ixp4xx_iowrite16(u16 value, void __iomem *addr) +#define iowrite16(v, p) iowrite16(v, p) +static inline void iowrite16(u16 value, void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_outw(value, port & PIO_MASK); + outw(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writew(cpu_to_le16(value), addr); @@ -495,12 +470,13 @@ __ixp4xx_iowrite16(u16 value, void __iomem *addr) #endif } -static inline void -__ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) +#define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c) +static inline void iowrite16_rep(void __iomem *addr, const void *vaddr, + u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_outsw(port & PIO_MASK, vaddr, count); + outsw(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesw(addr, vaddr, count); @@ -509,12 +485,12 @@ __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) #endif } -static inline void -__ixp4xx_iowrite32(u32 value, void __iomem *addr) +#define iowrite32(v, p) iowrite32(v, p) +static inline void iowrite32(u32 value, void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_outl(value, port & PIO_MASK); + outl(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writel((u32 __force)cpu_to_le32(value), addr); @@ -523,12 +499,13 @@ __ixp4xx_iowrite32(u32 value, void __iomem *addr) #endif } -static inline void -__ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) +#define iowrite32_rep(p, v, c) iowrite32_rep(p, v, c) +static inline void iowrite32_rep(void __iomem *addr, const void *vaddr, + u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_outsl(port & PIO_MASK, vaddr, count); + outsl(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesl(addr, vaddr, count); @@ -537,25 +514,8 @@ __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) #endif } -#define ioread8(p) __ixp4xx_ioread8(p) -#define ioread16(p) __ixp4xx_ioread16(p) -#define ioread32(p) __ixp4xx_ioread32(p) - -#define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c) -#define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c) -#define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c) - -#define iowrite8(v,p) __ixp4xx_iowrite8(v,p) -#define iowrite16(v,p) __ixp4xx_iowrite16(v,p) -#define iowrite32(v,p) __ixp4xx_iowrite32(v,p) - -#define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c) -#define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c) -#define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c) - #define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET)) #define ioport_unmap(addr) -#endif // !CONFIG_PCI - -#endif // __ASM_ARM_ARCH_IO_H +#endif /* CONFIG_PCI */ +#endif /* __ASM_ARM_ARCH_IO_H */ -- cgit v0.10.2 From cba362221b12b102dff1f21b291fdc7b93e24a18 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Sun, 15 Nov 2009 01:25:06 +0100 Subject: IXP4xx: Fix compilation failure with CONFIG_IXP4XX_INDIRECT_PCI. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of including the heavy linux/mm.h for VMALLOC_START, test the addresses against PCI MIN and MAX addresses. Indirect PCI uses 1:1 mapping for MMIO space making this change possible. Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h index c06d4a2..0e601fe 100644 --- a/arch/arm/mach-ixp4xx/include/mach/io.h +++ b/arch/arm/mach-ixp4xx/include/mach/io.h @@ -55,10 +55,16 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); * access registers. If something outside of PCI is ioremap'd, we * fallback to the default. */ + +static inline int is_pci_memory(u32 addr) +{ + return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF); +} + static inline void __iomem * __indirect_ioremap(unsigned long addr, size_t size, unsigned int mtype) { - if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff)) + if (!is_pci_memory(addr)) return __arm_ioremap(addr, size, mtype); return (void __iomem *)addr; @@ -66,7 +72,7 @@ static inline void __iomem * __indirect_ioremap(unsigned long addr, size_t size, static inline void __indirect_iounmap(void __iomem *addr) { - if ((__force u32)addr >= VMALLOC_START) + if (!is_pci_memory((__force u32)addr)) __iounmap(addr); } @@ -94,7 +100,7 @@ static inline void __indirect_writeb(u8 value, volatile void __iomem *p) u32 addr = (u32)p; u32 n, byte_enables, data; - if (addr >= VMALLOC_START) { + if (!is_pci_memory(addr)) { __raw_writeb(value, addr); return; } @@ -117,7 +123,7 @@ static inline void __indirect_writew(u16 value, volatile void __iomem *p) u32 addr = (u32)p; u32 n, byte_enables, data; - if (addr >= VMALLOC_START) { + if (!is_pci_memory(addr)) { __raw_writew(value, addr); return; } @@ -138,7 +144,8 @@ static inline void __indirect_writesw(volatile void __iomem *bus_addr, static inline void __indirect_writel(u32 value, volatile void __iomem *p) { u32 addr = (__force u32)p; - if (addr >= VMALLOC_START) { + + if (!is_pci_memory(addr)) { __raw_writel(value, p); return; } @@ -158,7 +165,7 @@ static inline unsigned char __indirect_readb(const volatile void __iomem *p) u32 addr = (u32)p; u32 n, byte_enables, data; - if (addr >= VMALLOC_START) + if (!is_pci_memory(addr)) return __raw_readb(addr); n = addr % 4; @@ -181,7 +188,7 @@ static inline unsigned short __indirect_readw(const volatile void __iomem *p) u32 addr = (u32)p; u32 n, byte_enables, data; - if (addr >= VMALLOC_START) + if (!is_pci_memory(addr)) return __raw_readw(addr); n = addr % 4; @@ -204,7 +211,7 @@ static inline unsigned long __indirect_readl(const volatile void __iomem *p) u32 addr = (__force u32)p; u32 data; - if (addr >= VMALLOC_START) + if (!is_pci_memory(addr)) return __raw_readl(p); if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data)) -- cgit v0.10.2 From ed5b9fa0d1c5ad1e01ff56b9acd3ff52bc783f66 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Sun, 15 Nov 2009 18:02:10 +0100 Subject: IXP4xx: Extend PCI MMIO indirect address space to 1 GB. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit IXP4xx CPUs can indirectly access the whole 4 GB PCI MMIO address space (using the non-prefetch registers). Previously the available space depended on the CPU variant, since one of the IXP43x platforms needed more than the usual 128 MB. 1 GB should be enough for everyone, and if not, we can trivially increase it. Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index 264f4d5..9e5070d 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -179,21 +179,21 @@ config IXP4XX_INDIRECT_PCI help IXP4xx provides two methods of accessing PCI memory space: - 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). + 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB). To access PCI via this space, we simply ioremap() the BAR into the kernel and we can use the standard read[bwl]/write[bwl] macros. This is the preferred method due to speed but it - limits the system to just 64MB of PCI memory. This can be + limits the system to just 64MB of PCI memory. This can be problematic if using video cards and other memory-heavy devices. - - 2) If > 64MB of memory space is required, the IXP4xx can be - configured to use indirect registers to access PCI This allows - for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. - The disadvantage of this is that every PCI access requires - three local register accesses plus a spinlock, but in some - cases the performance hit is acceptable. In addition, you cannot - mmap() PCI devices in this case due to the indirect nature - of the PCI window. + + 2) If > 64MB of memory space is required, the IXP4xx can be + configured to use indirect registers to access the whole PCI + memory space. This currently allows for up to 1 GB (0x10000000 + to 0x4FFFFFFF) of memory on the bus. The disadvantage of this + is that every PCI access requires three local register accesses + plus a spinlock, but in some cases the performance hit is + acceptable. In addition, you cannot mmap() PCI devices in this + case due to the indirect nature of the PCI window. By default, the direct method is used. Choose this option if you need to use the indirect method instead. If you don't know diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index 70afcfe..c4a0159 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c @@ -481,11 +481,7 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys) res[1].name = "PCI Memory Space"; res[1].start = PCIBIOS_MIN_MEM; -#ifndef CONFIG_IXP4XX_INDIRECT_PCI - res[1].end = 0x4bffffff; -#else - res[1].end = 0x4fffffff; -#endif + res[1].end = PCIBIOS_MAX_MEM; res[1].flags = IORESOURCE_MEM; request_resource(&ioport_resource, &res[0]); diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h index f58a43a..f822b22 100644 --- a/arch/arm/mach-ixp4xx/include/mach/hardware.h +++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h @@ -18,7 +18,13 @@ #define __ASM_ARCH_HARDWARE_H__ #define PCIBIOS_MIN_IO 0x00001000 -#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000) +#ifdef CONFIG_IXP4XX_INDIRECT_PCI +#define PCIBIOS_MIN_MEM 0x10000000 /* 1 GB of indirect PCI MMIO space */ +#define PCIBIOS_MAX_MEM 0x4FFFFFFF +#else +#define PCIBIOS_MIN_MEM 0x48000000 /* 64 MB of PCI MMIO space */ +#define PCIBIOS_MAX_MEM 0x4BFFFFFF +#endif /* * We override the standard dma-mask routines for bouncing. diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h index 0e601fe..6ea7e2f 100644 --- a/arch/arm/mach-ixp4xx/include/mach/io.h +++ b/arch/arm/mach-ixp4xx/include/mach/io.h @@ -26,22 +26,20 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); /* * IXP4xx provides two methods of accessing PCI memory space: * - * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). + * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB). * To access PCI via this space, we simply ioremap() the BAR * into the kernel and we can use the standard read[bwl]/write[bwl] * macros. This is the preffered method due to speed but it - * limits the system to just 64MB of PCI memory. This can be - * problamatic if using video cards and other memory-heavy - * targets. - * - * 2) If > 64MB of memory space is required, the IXP4xx can be configured - * to use indirect registers to access PCI (as we do below for I/O - * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff) - * of memory on the bus. The disadvantage of this is that every - * PCI access requires three local register accesses plus a spinlock, - * but in some cases the performance hit is acceptable. In addition, - * you cannot mmap() PCI devices in this case. + * limits the system to just 64MB of PCI memory. This can be + * problematic if using video cards and other memory-heavy targets. * + * 2) If > 64MB of memory space is required, the IXP4xx can use indirect + * registers to access the whole 4 GB of PCI memory space (as we do below + * for I/O transactions). This allows currently for up to 1 GB (0x10000000 + * to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that + * every PCI access requires three local register accesses plus a spinlock, + * but in some cases the performance hit is acceptable. In addition, you + * cannot mmap() PCI devices in this case. */ #ifndef CONFIG_IXP4XX_INDIRECT_PCI -- cgit v0.10.2 From 9bf4d676898b1f083a7ee20a0c6aacf2886eb49d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Mon, 16 Nov 2009 15:24:41 +0100 Subject: IXP4xx: move IXDP425 platform macros to the platform code. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h index f822b22..30ca67b 100644 --- a/arch/arm/mach-ixp4xx/include/mach/hardware.h +++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h @@ -44,7 +44,6 @@ #include "platform.h" /* Platform specific details */ -#include "ixdp425.h" #include "avila.h" #include "coyote.h" #include "prpmc1100.h" diff --git a/arch/arm/mach-ixp4xx/include/mach/irqs.h b/arch/arm/mach-ixp4xx/include/mach/irqs.h index f4d74de..4bb6d66 100644 --- a/arch/arm/mach-ixp4xx/include/mach/irqs.h +++ b/arch/arm/mach-ixp4xx/include/mach/irqs.h @@ -71,14 +71,6 @@ #define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU) /* - * IXDP425 board IRQs - */ -#define IRQ_IXDP425_PCI_INTA IRQ_IXP4XX_GPIO11 -#define IRQ_IXDP425_PCI_INTB IRQ_IXP4XX_GPIO10 -#define IRQ_IXDP425_PCI_INTC IRQ_IXP4XX_GPIO9 -#define IRQ_IXDP425_PCI_INTD IRQ_IXP4XX_GPIO8 - -/* * Gateworks Avila board IRQs */ #define IRQ_AVILA_PCI_INTA IRQ_IXP4XX_GPIO11 diff --git a/arch/arm/mach-ixp4xx/include/mach/ixdp425.h b/arch/arm/mach-ixp4xx/include/mach/ixdp425.h deleted file mode 100644 index 2cafe65..0000000 --- a/arch/arm/mach-ixp4xx/include/mach/ixdp425.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * arch/arm/mach-ixp4xx/include/mach/ixdp425.h - * - * IXDP425 platform specific definitions - * - * Author: Deepak Saxena - * - * Copyright 2004 (c) MontaVista, Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_HARDWARE_H__ -#error "Do not include this directly, instead #include " -#endif - -#define IXDP425_SDA_PIN 7 -#define IXDP425_SCL_PIN 6 - -/* - * IXDP425 PCI IRQs - */ -#define IXDP425_PCI_MAX_DEV 4 -#define IXDP425_PCI_IRQ_LINES 4 - - -/* PCI controller GPIO to IRQ pin mappings */ -#define IXDP425_PCI_INTA_PIN 11 -#define IXDP425_PCI_INTB_PIN 10 -#define IXDP425_PCI_INTC_PIN 9 -#define IXDP425_PCI_INTD_PIN 8 - -/* NAND Flash pins */ -#define IXDP425_NAND_NCE_PIN 12 - -#define IXDP425_NAND_CMD_BYTE 0x01 -#define IXDP425_NAND_ADDR_BYTE 0x02 diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c index 64c29aa..dc8b588 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-ixp4xx/ixdp425-pci.c + * arch/arm/mach-ixp4xx/ixdp425-pci.c * * IXDP425 board-level PCI initialization * @@ -19,12 +19,25 @@ #include #include #include - #include #include #include #include +#define IXDP425_PCI_MAX_DEV 4 +#define IXDP425_PCI_IRQ_LINES 4 + +/* PCI controller GPIO to IRQ pin mappings */ +#define IXDP425_PCI_INTA_PIN 11 +#define IXDP425_PCI_INTB_PIN 10 +#define IXDP425_PCI_INTC_PIN 9 +#define IXDP425_PCI_INTD_PIN 8 + +#define IRQ_IXDP425_PCI_INTA IRQ_IXP4XX_GPIO11 +#define IRQ_IXDP425_PCI_INTB IRQ_IXP4XX_GPIO10 +#define IRQ_IXDP425_PCI_INTC IRQ_IXP4XX_GPIO9 +#define IRQ_IXDP425_PCI_INTD IRQ_IXP4XX_GPIO8 + void __init ixdp425_pci_preinit(void) { set_irq_type(IRQ_IXDP425_PCI_INTA, IRQ_TYPE_LEVEL_LOW); diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c index f4a0c1b..bbb7689 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-ixp4xx/ixdp425-setup.c * - * IXDP425/IXCDP1100 board-setup + * IXDP425/IXCDP1100 board-setup * * Copyright (C) 2003-2005 MontaVista Software, Inc. * @@ -21,7 +21,6 @@ #include #include #include - #include #include #include @@ -31,6 +30,15 @@ #include #include +#define IXDP425_SDA_PIN 7 +#define IXDP425_SCL_PIN 6 + +/* NAND Flash pins */ +#define IXDP425_NAND_NCE_PIN 12 + +#define IXDP425_NAND_CMD_BYTE 0x01 +#define IXDP425_NAND_ADDR_BYTE 0x02 + static struct flash_platform_data ixdp425_flash_data = { .map_name = "cfi_probe", .width = 2, -- cgit v0.10.2 From ec66969685ecf04e8a5036369702fa9aec07cc17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Mon, 16 Nov 2009 15:39:11 +0100 Subject: IXP4xx: move AVILA platform macros to the platform code. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c index 08d65dc..14df8cf 100644 --- a/arch/arm/mach-ixp4xx/avila-pci.c +++ b/arch/arm/mach-ixp4xx/avila-pci.c @@ -22,12 +22,26 @@ #include #include #include - #include #include #include #include +#define AVILA_PCI_MAX_DEV 4 +#define LOFT_PCI_MAX_DEV 6 +#define AVILA_PCI_IRQ_LINES 4 + +/* PCI controller GPIO to IRQ pin mappings */ +#define AVILA_PCI_INTA_PIN 11 +#define AVILA_PCI_INTB_PIN 10 +#define AVILA_PCI_INTC_PIN 9 +#define AVILA_PCI_INTD_PIN 8 + +#define IRQ_AVILA_PCI_INTA IRQ_IXP4XX_GPIO11 +#define IRQ_AVILA_PCI_INTB IRQ_IXP4XX_GPIO10 +#define IRQ_AVILA_PCI_INTC IRQ_IXP4XX_GPIO9 +#define IRQ_AVILA_PCI_INTD IRQ_IXP4XX_GPIO8 + void __init avila_pci_preinit(void) { set_irq_type(IRQ_AVILA_PCI_INTA, IRQ_TYPE_LEVEL_LOW); diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c index 797995c..6e558a7 100644 --- a/arch/arm/mach-ixp4xx/avila-setup.c +++ b/arch/arm/mach-ixp4xx/avila-setup.c @@ -19,7 +19,6 @@ #include #include #include - #include #include #include @@ -29,6 +28,9 @@ #include #include +#define AVILA_SDA_PIN 7 +#define AVILA_SCL_PIN 6 + static struct flash_platform_data avila_flash_data = { .map_name = "cfi_probe", .width = 2, diff --git a/arch/arm/mach-ixp4xx/include/mach/avila.h b/arch/arm/mach-ixp4xx/include/mach/avila.h deleted file mode 100644 index 1640cb6..0000000 --- a/arch/arm/mach-ixp4xx/include/mach/avila.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * arch/arm/mach-ixp4xx/include/mach/avila.h - * - * Gateworks Avila platform specific definitions - * - * Author: Michael-Luke Jones - * - * Based on ixdp425.h - * Author: Deepak Saxena - * - * Copyright 2004 (c) MontaVista, Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_HARDWARE_H__ -#error "Do not include this directly, instead #include " -#endif - -#define AVILA_SDA_PIN 7 -#define AVILA_SCL_PIN 6 - -/* - * AVILA PCI IRQs - */ -#define AVILA_PCI_MAX_DEV 4 -#define LOFT_PCI_MAX_DEV 6 -#define AVILA_PCI_IRQ_LINES 4 - - -/* PCI controller GPIO to IRQ pin mappings */ -#define AVILA_PCI_INTA_PIN 11 -#define AVILA_PCI_INTB_PIN 10 -#define AVILA_PCI_INTC_PIN 9 -#define AVILA_PCI_INTD_PIN 8 - - diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h index 30ca67b..72b7543 100644 --- a/arch/arm/mach-ixp4xx/include/mach/hardware.h +++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h @@ -44,7 +44,6 @@ #include "platform.h" /* Platform specific details */ -#include "avila.h" #include "coyote.h" #include "prpmc1100.h" #include "nslu2.h" diff --git a/arch/arm/mach-ixp4xx/include/mach/irqs.h b/arch/arm/mach-ixp4xx/include/mach/irqs.h index 4bb6d66..5cb19fe 100644 --- a/arch/arm/mach-ixp4xx/include/mach/irqs.h +++ b/arch/arm/mach-ixp4xx/include/mach/irqs.h @@ -71,15 +71,6 @@ #define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU) /* - * Gateworks Avila board IRQs - */ -#define IRQ_AVILA_PCI_INTA IRQ_IXP4XX_GPIO11 -#define IRQ_AVILA_PCI_INTB IRQ_IXP4XX_GPIO10 -#define IRQ_AVILA_PCI_INTC IRQ_IXP4XX_GPIO9 -#define IRQ_AVILA_PCI_INTD IRQ_IXP4XX_GPIO8 - - -/* * PrPMC1100 Board IRQs */ #define IRQ_PRPMC1100_PCI_INTA IRQ_IXP4XX_GPIO11 -- cgit v0.10.2 From f89f44902af4b88e12c5d2c888915749362198e7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Mon, 16 Nov 2009 15:57:41 +0100 Subject: IXP4xx: move Coyote platform macros to the platform code. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c index efddf01..624f8fe 100644 --- a/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/arch/arm/mach-ixp4xx/coyote-pci.c @@ -18,13 +18,21 @@ #include #include #include - #include #include #include - #include +#define COYOTE_PCI_SLOT0_DEVID 14 +#define COYOTE_PCI_SLOT1_DEVID 15 + +/* PCI controller GPIO to IRQ pin mappings */ +#define COYOTE_PCI_SLOT0_PIN 6 +#define COYOTE_PCI_SLOT1_PIN 11 + +#define IRQ_COYOTE_PCI_SLOT0 IRQ_IXP4XX_GPIO6 +#define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11 + void __init coyote_pci_preinit(void) { set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQ_TYPE_LEVEL_LOW); diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c index aab1954..25bf5ad 100644 --- a/arch/arm/mach-ixp4xx/coyote-setup.c +++ b/arch/arm/mach-ixp4xx/coyote-setup.c @@ -25,6 +25,15 @@ #include #include +#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3) +#define COYOTE_IDE_BASE_VIRT 0xFFFE1000 +#define COYOTE_IDE_REGION_SIZE 0x1000 + +#define COYOTE_IDE_DATA_PORT 0xFFFE10E0 +#define COYOTE_IDE_CTRL_PORT 0xFFFE10FC +#define COYOTE_IDE_ERROR_PORT 0xFFFE10E2 +#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5 + static struct flash_platform_data coyote_flash_data = { .map_name = "cfi_probe", .width = 2, diff --git a/arch/arm/mach-ixp4xx/include/mach/coyote.h b/arch/arm/mach-ixp4xx/include/mach/coyote.h deleted file mode 100644 index 717ac6d..0000000 --- a/arch/arm/mach-ixp4xx/include/mach/coyote.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * arch/arm/mach-ixp4xx/include/mach/coyote.h - * - * ADI Engineering platform specific definitions - * - * Author: Deepak Saxena - * - * Copyright 2004 (c) MontaVista, Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_HARDWARE_H__ -#error "Do not include this directly, instead #include " -#endif - -/* PCI controller GPIO to IRQ pin mappings */ -#define COYOTE_PCI_SLOT0_PIN 6 -#define COYOTE_PCI_SLOT1_PIN 11 - -#define COYOTE_PCI_SLOT0_DEVID 14 -#define COYOTE_PCI_SLOT1_DEVID 15 - -#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3) -#define COYOTE_IDE_BASE_VIRT 0xFFFE1000 -#define COYOTE_IDE_REGION_SIZE 0x1000 - -#define COYOTE_IDE_DATA_PORT 0xFFFE10E0 -#define COYOTE_IDE_CTRL_PORT 0xFFFE10FC -#define COYOTE_IDE_ERROR_PORT 0xFFFE10E2 - diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h index 72b7543..1fbed65 100644 --- a/arch/arm/mach-ixp4xx/include/mach/hardware.h +++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h @@ -44,7 +44,6 @@ #include "platform.h" /* Platform specific details */ -#include "coyote.h" #include "prpmc1100.h" #include "nslu2.h" #include "nas100d.h" diff --git a/arch/arm/mach-ixp4xx/include/mach/irqs.h b/arch/arm/mach-ixp4xx/include/mach/irqs.h index 5cb19fe..e4c6cca 100644 --- a/arch/arm/mach-ixp4xx/include/mach/irqs.h +++ b/arch/arm/mach-ixp4xx/include/mach/irqs.h @@ -79,13 +79,6 @@ #define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8 /* - * ADI Coyote Board IRQs - */ -#define IRQ_COYOTE_PCI_SLOT0 IRQ_IXP4XX_GPIO6 -#define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11 -#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5 - -/* * NSLU2 board IRQs */ #define IRQ_NSLU2_PCI_INTA IRQ_IXP4XX_GPIO11 -- cgit v0.10.2 From c1117c63d53cc269193d02383b4275ae5c4cbe49 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Mon, 16 Nov 2009 16:02:02 +0100 Subject: IXP4xx: move NSLU2 platform macros to the platform code. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h index 1fbed65..b949cd2 100644 --- a/arch/arm/mach-ixp4xx/include/mach/hardware.h +++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h @@ -45,7 +45,6 @@ /* Platform specific details */ #include "prpmc1100.h" -#include "nslu2.h" #include "nas100d.h" #include "dsmg600.h" #include "fsg.h" diff --git a/arch/arm/mach-ixp4xx/include/mach/irqs.h b/arch/arm/mach-ixp4xx/include/mach/irqs.h index e4c6cca..b7e372e 100644 --- a/arch/arm/mach-ixp4xx/include/mach/irqs.h +++ b/arch/arm/mach-ixp4xx/include/mach/irqs.h @@ -79,13 +79,6 @@ #define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8 /* - * NSLU2 board IRQs - */ -#define IRQ_NSLU2_PCI_INTA IRQ_IXP4XX_GPIO11 -#define IRQ_NSLU2_PCI_INTB IRQ_IXP4XX_GPIO10 -#define IRQ_NSLU2_PCI_INTC IRQ_IXP4XX_GPIO9 - -/* * NAS100D board IRQs */ #define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11 diff --git a/arch/arm/mach-ixp4xx/include/mach/nslu2.h b/arch/arm/mach-ixp4xx/include/mach/nslu2.h deleted file mode 100644 index 85d00ad..0000000 --- a/arch/arm/mach-ixp4xx/include/mach/nslu2.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * arch/arm/mach-ixp4xx/include/mach/nslu2.h - * - * NSLU2 platform specific definitions - * - * Author: Mark Rakes - * Maintainers: http://www.nslu2-linux.org - * - * based on ixdp425.h: - * Copyright 2004 (c) MontaVista, Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_HARDWARE_H__ -#error "Do not include this directly, instead #include " -#endif - -#define NSLU2_SDA_PIN 7 -#define NSLU2_SCL_PIN 6 - -/* - * NSLU2 PCI IRQs - */ -#define NSLU2_PCI_MAX_DEV 3 -#define NSLU2_PCI_IRQ_LINES 3 - - -/* PCI controller GPIO to IRQ pin mappings */ -#define NSLU2_PCI_INTA_PIN 11 -#define NSLU2_PCI_INTB_PIN 10 -#define NSLU2_PCI_INTC_PIN 9 -#define NSLU2_PCI_INTD_PIN 8 - -/* NSLU2 Timer */ -#define NSLU2_FREQ 66000000 - -/* Buttons */ - -#define NSLU2_PB_GPIO 5 /* power button */ -#define NSLU2_PO_GPIO 8 /* power off */ -#define NSLU2_RB_GPIO 12 /* reset button */ - -/* Buzzer */ - -#define NSLU2_GPIO_BUZZ 4 - -/* LEDs */ - -#define NSLU2_LED_RED_GPIO 0 -#define NSLU2_LED_GRN_GPIO 1 -#define NSLU2_LED_DISK1_GPIO 3 -#define NSLU2_LED_DISK2_GPIO 2 diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c index 4429b84..9665bb0 100644 --- a/arch/arm/mach-ixp4xx/nslu2-pci.c +++ b/arch/arm/mach-ixp4xx/nslu2-pci.c @@ -18,10 +18,21 @@ #include #include #include - #include #include +#define NSLU2_PCI_MAX_DEV 3 +#define NSLU2_PCI_IRQ_LINES 3 + +/* PCI controller GPIO to IRQ pin mappings */ +#define NSLU2_PCI_INTA_PIN 11 +#define NSLU2_PCI_INTB_PIN 10 +#define NSLU2_PCI_INTC_PIN 9 +#define NSLU2_PCI_INTD_PIN 8 +#define IRQ_NSLU2_PCI_INTA IRQ_IXP4XX_GPIO11 +#define IRQ_NSLU2_PCI_INTB IRQ_IXP4XX_GPIO10 +#define IRQ_NSLU2_PCI_INTC IRQ_IXP4XX_GPIO9 + void __init nslu2_pci_preinit(void) { set_irq_type(IRQ_NSLU2_PCI_INTA, IRQ_TYPE_LEVEL_LOW); diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c index ff6a08d..c14e003 100644 --- a/arch/arm/mach-ixp4xx/nslu2-setup.c +++ b/arch/arm/mach-ixp4xx/nslu2-setup.c @@ -26,13 +26,32 @@ #include #include #include - #include #include #include #include #include +#define NSLU2_SDA_PIN 7 +#define NSLU2_SCL_PIN 6 + +/* NSLU2 Timer */ +#define NSLU2_FREQ 66000000 + +/* Buttons */ +#define NSLU2_PB_GPIO 5 /* power button */ +#define NSLU2_PO_GPIO 8 /* power off */ +#define NSLU2_RB_GPIO 12 /* reset button */ + +/* Buzzer */ +#define NSLU2_GPIO_BUZZ 4 + +/* LEDs */ +#define NSLU2_LED_RED_GPIO 0 +#define NSLU2_LED_GRN_GPIO 1 +#define NSLU2_LED_DISK1_GPIO 3 +#define NSLU2_LED_DISK2_GPIO 2 + static struct flash_platform_data nslu2_flash_data = { .map_name = "cfi_probe", .width = 2, -- cgit v0.10.2 From 23fa6846a2e2ac6fcb6529f047570244ecbd957c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Mon, 16 Nov 2009 16:06:47 +0100 Subject: IXP4xx: move NAS100D platform macros to the platform code. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h index b949cd2..05db635 100644 --- a/arch/arm/mach-ixp4xx/include/mach/hardware.h +++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h @@ -45,7 +45,6 @@ /* Platform specific details */ #include "prpmc1100.h" -#include "nas100d.h" #include "dsmg600.h" #include "fsg.h" diff --git a/arch/arm/mach-ixp4xx/include/mach/irqs.h b/arch/arm/mach-ixp4xx/include/mach/irqs.h index b7e372e..dff26af 100644 --- a/arch/arm/mach-ixp4xx/include/mach/irqs.h +++ b/arch/arm/mach-ixp4xx/include/mach/irqs.h @@ -79,15 +79,6 @@ #define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8 /* - * NAS100D board IRQs - */ -#define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11 -#define IRQ_NAS100D_PCI_INTB IRQ_IXP4XX_GPIO10 -#define IRQ_NAS100D_PCI_INTC IRQ_IXP4XX_GPIO9 -#define IRQ_NAS100D_PCI_INTD IRQ_IXP4XX_GPIO8 -#define IRQ_NAS100D_PCI_INTE IRQ_IXP4XX_GPIO7 - -/* * D-Link DSM-G600 RevA board IRQs */ #define IRQ_DSMG600_PCI_INTA IRQ_IXP4XX_GPIO11 diff --git a/arch/arm/mach-ixp4xx/include/mach/nas100d.h b/arch/arm/mach-ixp4xx/include/mach/nas100d.h deleted file mode 100644 index 3771d62..0000000 --- a/arch/arm/mach-ixp4xx/include/mach/nas100d.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * arch/arm/mach-ixp4xx/include/mach/nas100d.h - * - * NAS100D platform specific definitions - * - * Copyright (c) 2005 Tower Technologies - * - * Author: Alessandro Zummo - * - * based on ixdp425.h: - * Copyright 2004 (c) MontaVista, Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_HARDWARE_H__ -#error "Do not include this directly, instead #include " -#endif - -#define NAS100D_SDA_PIN 5 -#define NAS100D_SCL_PIN 6 - -/* - * NAS100D PCI IRQs - */ -#define NAS100D_PCI_MAX_DEV 3 -#define NAS100D_PCI_IRQ_LINES 3 - - -/* PCI controller GPIO to IRQ pin mappings */ -#define NAS100D_PCI_INTA_PIN 11 -#define NAS100D_PCI_INTB_PIN 10 -#define NAS100D_PCI_INTC_PIN 9 -#define NAS100D_PCI_INTD_PIN 8 -#define NAS100D_PCI_INTE_PIN 7 - -/* Buttons */ - -#define NAS100D_PB_GPIO 14 /* power button */ -#define NAS100D_RB_GPIO 4 /* reset button */ - -/* Power control */ - -#define NAS100D_PO_GPIO 12 /* power off */ - -/* LEDs */ - -#define NAS100D_LED_WLAN_GPIO 0 -#define NAS100D_LED_DISK_GPIO 3 -#define NAS100D_LED_PWR_GPIO 15 diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c index 1088426..ac04fc1 100644 --- a/arch/arm/mach-ixp4xx/nas100d-pci.c +++ b/arch/arm/mach-ixp4xx/nas100d-pci.c @@ -18,10 +18,25 @@ #include #include #include - #include #include +#define NAS100D_PCI_MAX_DEV 3 +#define NAS100D_PCI_IRQ_LINES 3 + +/* PCI controller GPIO to IRQ pin mappings */ +#define NAS100D_PCI_INTA_PIN 11 +#define NAS100D_PCI_INTB_PIN 10 +#define NAS100D_PCI_INTC_PIN 9 +#define NAS100D_PCI_INTD_PIN 8 +#define NAS100D_PCI_INTE_PIN 7 + +#define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11 +#define IRQ_NAS100D_PCI_INTB IRQ_IXP4XX_GPIO10 +#define IRQ_NAS100D_PCI_INTC IRQ_IXP4XX_GPIO9 +#define IRQ_NAS100D_PCI_INTD IRQ_IXP4XX_GPIO8 +#define IRQ_NAS100D_PCI_INTE IRQ_IXP4XX_GPIO7 + void __init nas100d_pci_preinit(void) { set_irq_type(IRQ_NAS100D_PCI_INTA, IRQ_TYPE_LEVEL_LOW); diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c index 921c947..e3ee880 100644 --- a/arch/arm/mach-ixp4xx/nas100d-setup.c +++ b/arch/arm/mach-ixp4xx/nas100d-setup.c @@ -29,12 +29,26 @@ #include #include #include - #include #include #include #include +#define NAS100D_SDA_PIN 5 +#define NAS100D_SCL_PIN 6 + +/* Buttons */ +#define NAS100D_PB_GPIO 14 /* power button */ +#define NAS100D_RB_GPIO 4 /* reset button */ + +/* Power control */ +#define NAS100D_PO_GPIO 12 /* power off */ + +/* LEDs */ +#define NAS100D_LED_WLAN_GPIO 0 +#define NAS100D_LED_DISK_GPIO 3 +#define NAS100D_LED_PWR_GPIO 15 + static struct flash_platform_data nas100d_flash_data = { .map_name = "cfi_probe", .width = 2, -- cgit v0.10.2 From 395e71276cd394c103931bfb60ceec9a97c0eaee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Mon, 16 Nov 2009 21:56:56 +0100 Subject: IXP4xx: move DSM G600 platform macros to the platform code. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c index 926d15f..29a9e41 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-pci.c +++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c @@ -19,10 +19,27 @@ #include #include #include - #include #include +#define DSMG600_PCI_MAX_DEV 4 +#define DSMG600_PCI_IRQ_LINES 3 + +/* PCI controller GPIO to IRQ pin mappings */ +#define DSMG600_PCI_INTA_PIN 11 +#define DSMG600_PCI_INTB_PIN 10 +#define DSMG600_PCI_INTC_PIN 9 +#define DSMG600_PCI_INTD_PIN 8 +#define DSMG600_PCI_INTE_PIN 7 +#define DSMG600_PCI_INTF_PIN 6 + +#define IRQ_DSMG600_PCI_INTA IRQ_IXP4XX_GPIO11 +#define IRQ_DSMG600_PCI_INTB IRQ_IXP4XX_GPIO10 +#define IRQ_DSMG600_PCI_INTC IRQ_IXP4XX_GPIO9 +#define IRQ_DSMG600_PCI_INTD IRQ_IXP4XX_GPIO8 +#define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7 +#define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6 + void __init dsmg600_pci_preinit(void) { set_irq_type(IRQ_DSMG600_PCI_INTA, IRQ_TYPE_LEVEL_LOW); diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c index a51bfa6..7c1fa54 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-setup.c +++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c @@ -33,6 +33,23 @@ #include #include +#define DSMG600_SDA_PIN 5 +#define DSMG600_SCL_PIN 4 + +/* DSM-G600 Timer Setting */ +#define DSMG600_FREQ 66000000 + +/* Buttons */ +#define DSMG600_PB_GPIO 15 /* power button */ +#define DSMG600_RB_GPIO 3 /* reset button */ + +/* Power control */ +#define DSMG600_PO_GPIO 2 /* power off */ + +/* LEDs */ +#define DSMG600_LED_PWR_GPIO 0 +#define DSMG600_LED_WLAN_GPIO 14 + static struct flash_platform_data dsmg600_flash_data = { .map_name = "cfi_probe", .width = 2, diff --git a/arch/arm/mach-ixp4xx/include/mach/dsmg600.h b/arch/arm/mach-ixp4xx/include/mach/dsmg600.h deleted file mode 100644 index dc087a3..0000000 --- a/arch/arm/mach-ixp4xx/include/mach/dsmg600.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * DSM-G600 platform specific definitions - * - * Copyright (C) 2006 Tower Technologies - * Author: Alessandro Zummo - * - * based on ixdp425.h: - * Copyright 2004 (C) MontaVista, Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_HARDWARE_H__ -#error "Do not include this directly, instead #include " -#endif - -#define DSMG600_SDA_PIN 5 -#define DSMG600_SCL_PIN 4 - -/* - * DSMG600 PCI IRQs - */ -#define DSMG600_PCI_MAX_DEV 4 -#define DSMG600_PCI_IRQ_LINES 3 - - -/* PCI controller GPIO to IRQ pin mappings */ -#define DSMG600_PCI_INTA_PIN 11 -#define DSMG600_PCI_INTB_PIN 10 -#define DSMG600_PCI_INTC_PIN 9 -#define DSMG600_PCI_INTD_PIN 8 -#define DSMG600_PCI_INTE_PIN 7 -#define DSMG600_PCI_INTF_PIN 6 - -/* DSM-G600 Timer Setting */ -#define DSMG600_FREQ 66000000 - -/* Buttons */ - -#define DSMG600_PB_GPIO 15 /* power button */ -#define DSMG600_RB_GPIO 3 /* reset button */ - -/* Power control */ - -#define DSMG600_PO_GPIO 2 /* power off */ - -/* LEDs */ - -#define DSMG600_LED_PWR_GPIO 0 -#define DSMG600_LED_WLAN_GPIO 14 diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h index 05db635..555b8e1 100644 --- a/arch/arm/mach-ixp4xx/include/mach/hardware.h +++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h @@ -45,7 +45,6 @@ /* Platform specific details */ #include "prpmc1100.h" -#include "dsmg600.h" #include "fsg.h" #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-ixp4xx/include/mach/irqs.h b/arch/arm/mach-ixp4xx/include/mach/irqs.h index dff26af..20053be 100644 --- a/arch/arm/mach-ixp4xx/include/mach/irqs.h +++ b/arch/arm/mach-ixp4xx/include/mach/irqs.h @@ -79,16 +79,6 @@ #define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8 /* - * D-Link DSM-G600 RevA board IRQs - */ -#define IRQ_DSMG600_PCI_INTA IRQ_IXP4XX_GPIO11 -#define IRQ_DSMG600_PCI_INTB IRQ_IXP4XX_GPIO10 -#define IRQ_DSMG600_PCI_INTC IRQ_IXP4XX_GPIO9 -#define IRQ_DSMG600_PCI_INTD IRQ_IXP4XX_GPIO8 -#define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7 -#define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6 - -/* * Freecom FSG-3 Board IRQs */ #define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6 -- cgit v0.10.2 From 914e7bc28ee2c7083a7b81ffaa789f703eb5f974 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Mon, 16 Nov 2009 22:53:53 +0100 Subject: IXP4xx: move FSG platform macros to the platform code. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c index ca12a9c..2a1701b 100644 --- a/arch/arm/mach-ixp4xx/fsg-pci.c +++ b/arch/arm/mach-ixp4xx/fsg-pci.c @@ -19,10 +19,20 @@ #include #include #include - #include #include +#define FSG_PCI_MAX_DEV 3 +#define FSG_PCI_IRQ_LINES 3 + +/* PCI controller GPIO to IRQ pin mappings */ +#define FSG_PCI_INTA_PIN 6 +#define FSG_PCI_INTB_PIN 7 +#define FSG_PCI_INTC_PIN 5 +#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6 +#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7 +#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5 + void __init fsg_pci_preinit(void) { set_irq_type(IRQ_FSG_PCI_INTA, IRQ_TYPE_LEVEL_LOW); diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c index 5add22f..e7f4bef 100644 --- a/arch/arm/mach-ixp4xx/fsg-setup.c +++ b/arch/arm/mach-ixp4xx/fsg-setup.c @@ -24,12 +24,18 @@ #include #include #include - #include #include #include #include +#define FSG_SDA_PIN 12 +#define FSG_SCL_PIN 13 + +#define FSG_SB_GPIO 4 /* sync button */ +#define FSG_RB_GPIO 9 /* reset button */ +#define FSG_UB_GPIO 10 /* usb button */ + static struct flash_platform_data fsg_flash_data = { .map_name = "cfi_probe", .width = 2, diff --git a/arch/arm/mach-ixp4xx/include/mach/fsg.h b/arch/arm/mach-ixp4xx/include/mach/fsg.h deleted file mode 100644 index 1f02b7e..0000000 --- a/arch/arm/mach-ixp4xx/include/mach/fsg.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * arch/arm/mach-ixp4xx/include/mach/fsg.h - * - * Freecom FSG-3 platform specific definitions - * - * Author: Rod Whitby - * Author: Tomasz Chmielewski - * Maintainers: http://www.nslu2-linux.org - * - * Based on coyote.h by - * Copyright 2004 (c) MontaVista, Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_HARDWARE_H__ -#error "Do not include this directly, instead #include " -#endif - -#define FSG_SDA_PIN 12 -#define FSG_SCL_PIN 13 - -/* - * FSG PCI IRQs - */ -#define FSG_PCI_MAX_DEV 3 -#define FSG_PCI_IRQ_LINES 3 - - -/* PCI controller GPIO to IRQ pin mappings */ -#define FSG_PCI_INTA_PIN 6 -#define FSG_PCI_INTB_PIN 7 -#define FSG_PCI_INTC_PIN 5 - -/* Buttons */ - -#define FSG_SB_GPIO 4 /* sync button */ -#define FSG_RB_GPIO 9 /* reset button */ -#define FSG_UB_GPIO 10 /* usb button */ - -/* LEDs */ - -#define FSG_LED_WLAN_BIT 0 -#define FSG_LED_WAN_BIT 1 -#define FSG_LED_SATA_BIT 2 -#define FSG_LED_USB_BIT 4 -#define FSG_LED_RING_BIT 5 -#define FSG_LED_SYNC_BIT 7 diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h index 555b8e1..8558073 100644 --- a/arch/arm/mach-ixp4xx/include/mach/hardware.h +++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h @@ -45,6 +45,5 @@ /* Platform specific details */ #include "prpmc1100.h" -#include "fsg.h" #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-ixp4xx/include/mach/irqs.h b/arch/arm/mach-ixp4xx/include/mach/irqs.h index 20053be..e256997 100644 --- a/arch/arm/mach-ixp4xx/include/mach/irqs.h +++ b/arch/arm/mach-ixp4xx/include/mach/irqs.h @@ -78,11 +78,4 @@ #define IRQ_PRPMC1100_PCI_INTC IRQ_IXP4XX_GPIO9 #define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8 -/* - * Freecom FSG-3 Board IRQs - */ -#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6 -#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7 -#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5 - #endif diff --git a/drivers/leds/leds-fsg.c b/drivers/leds/leds-fsg.c index 5f7c9c5..d11d05b 100644 --- a/drivers/leds/leds-fsg.c +++ b/drivers/leds/leds-fsg.c @@ -22,6 +22,13 @@ #include #include +#define FSG_LED_WLAN_BIT 0 +#define FSG_LED_WAN_BIT 1 +#define FSG_LED_SATA_BIT 2 +#define FSG_LED_USB_BIT 4 +#define FSG_LED_RING_BIT 5 +#define FSG_LED_SYNC_BIT 7 + static short __iomem *latch_address; static unsigned short latch_value; -- cgit v0.10.2 From 31bcde37853f2a3795aaac3541d51bd2afc09d66 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Mon, 16 Nov 2009 23:03:36 +0100 Subject: IXP4xx: Remove unused Motorola PrPMC1100 platform macros. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PrPMC1100 is handled by IXDP425 platform code, there is no need for duplicate set of macros. Remove them. Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h index 8558073..f9d1c43 100644 --- a/arch/arm/mach-ixp4xx/include/mach/hardware.h +++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h @@ -43,7 +43,4 @@ /* Platform helper functions and definitions */ #include "platform.h" -/* Platform specific details */ -#include "prpmc1100.h" - #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-ixp4xx/include/mach/irqs.h b/arch/arm/mach-ixp4xx/include/mach/irqs.h index e256997..dbc20bf 100644 --- a/arch/arm/mach-ixp4xx/include/mach/irqs.h +++ b/arch/arm/mach-ixp4xx/include/mach/irqs.h @@ -70,12 +70,4 @@ #define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU) -/* - * PrPMC1100 Board IRQs - */ -#define IRQ_PRPMC1100_PCI_INTA IRQ_IXP4XX_GPIO11 -#define IRQ_PRPMC1100_PCI_INTB IRQ_IXP4XX_GPIO10 -#define IRQ_PRPMC1100_PCI_INTC IRQ_IXP4XX_GPIO9 -#define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8 - #endif diff --git a/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h b/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h deleted file mode 100644 index 17274a2..0000000 --- a/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * arch/arm/mach-ixp4xx/include/mach/prpmc1100.h - * - * Motorolla PrPMC1100 platform specific definitions - * - * Author: Deepak Saxena - * - * Copyright 2004 (c) MontaVista, Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_HARDWARE_H__ -#error "Do not include this directly, instead #include " -#endif - -#define PRPMC1100_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS -#define PRPMC1100_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE - -#define PRPMC1100_PCI_MIN_DEVID 10 -#define PRPMC1100_PCI_MAX_DEVID 16 -#define PRPMC1100_PCI_IRQ_LINES 4 - - -/* PCI controller GPIO to IRQ pin mappings */ -#define PRPMC1100_PCI_INTA_PIN 11 -#define PRPMC1100_PCI_INTB_PIN 10 -#define PRPMC1100_PCI_INTC_PIN 9 -#define PRPMC1100_PCI_INTD_PIN 8 - - -- cgit v0.10.2 From a8b7b34075f693632cd1483b817d4211c7a63257 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Mon, 16 Nov 2009 23:24:57 +0100 Subject: IXP4xx: move Gemtek GTWX5715 platform macros to the platform code. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c index 7b8a2c3..6801185 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c @@ -26,14 +26,26 @@ #include #include #include - #include #include -#include #include +#define GTWX5715_PCI_SLOT0_DEVID 0 +#define GTWX5715_PCI_SLOT0_INTA_GPIO 10 +#define GTWX5715_PCI_SLOT0_INTB_GPIO 11 +#define GTWX5715_PCI_SLOT0_INTA_IRQ IRQ_IXP4XX_GPIO10 +#define GTWX5715_PCI_SLOT0_INTB_IRQ IRQ_IXP4XX_GPIO11 + +#define GTWX5715_PCI_SLOT1_DEVID 1 +#define GTWX5715_PCI_SLOT1_INTA_GPIO 11 +#define GTWX5715_PCI_SLOT1_INTB_GPIO 10 +#define GTWX5715_PCI_SLOT1_INTA_IRQ IRQ_IXP4XX_GPIO11 +#define GTWX5715_PCI_SLOT1_INTB_IRQ IRQ_IXP4XX_GPIO10 + +#define GTWX5715_PCI_SLOT_COUNT 2 +#define GTWX5715_PCI_INT_PIN_COUNT 2 + /* - * The exact GPIO pins and IRQs are defined in arch-ixp4xx/gtwx5715.h * Slot 0 isn't actually populated with a card connector but * we initialize it anyway in case a future version has the * slot populated or someone with good soldering skills has diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c index 25c21d6..0bc7185 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c @@ -28,7 +28,6 @@ #include #include #include - #include #include #include @@ -37,7 +36,34 @@ #include #include #include -#include + +/* GPIO 5,6,7 and 12 are hard wired to the Kendin KS8995M Switch + and operate as an SPI type interface. The details of the interface + are available on Kendin/Micrel's web site. */ + +#define GTWX5715_KSSPI_SELECT 5 +#define GTWX5715_KSSPI_TXD 6 +#define GTWX5715_KSSPI_CLOCK 7 +#define GTWX5715_KSSPI_RXD 12 + +/* The "reset" button is wired to GPIO 3. + The GPIO is brought "low" when the button is pushed. */ + +#define GTWX5715_BUTTON_GPIO 3 + +/* Board Label Front Label + LED1 Power + LED2 Wireless-G + LED3 not populated but could be + LED4 Internet + LED5 - LED8 Controlled by KS8995M Switch + LED9 DMZ */ + +#define GTWX5715_LED1_GPIO 2 +#define GTWX5715_LED2_GPIO 9 +#define GTWX5715_LED3_GPIO 8 +#define GTWX5715_LED4_GPIO 1 +#define GTWX5715_LED9_GPIO 4 /* * Xscale UART registers are 32 bits wide with only the least diff --git a/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h b/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h deleted file mode 100644 index 5d5e201..0000000 --- a/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * arch/arm/mach-ixp4xx/include/mach/gtwx5715.h - * - * Gemtek GTWX5715 Gateway (Linksys WRV54G) - * - * Copyright 2004 (c) George T. Joseph - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#ifndef __ASM_ARCH_HARDWARE_H__ -#error "Do not include this directly, instead #include " -#endif -#include "irqs.h" - -#define GTWX5715_GPIO0 0 -#define GTWX5715_GPIO1 1 -#define GTWX5715_GPIO2 2 -#define GTWX5715_GPIO3 3 -#define GTWX5715_GPIO4 4 -#define GTWX5715_GPIO5 5 -#define GTWX5715_GPIO6 6 -#define GTWX5715_GPIO7 7 -#define GTWX5715_GPIO8 8 -#define GTWX5715_GPIO9 9 -#define GTWX5715_GPIO10 10 -#define GTWX5715_GPIO11 11 -#define GTWX5715_GPIO12 12 -#define GTWX5715_GPIO13 13 -#define GTWX5715_GPIO14 14 - -#define GTWX5715_GPIO0_IRQ IRQ_IXP4XX_GPIO0 -#define GTWX5715_GPIO1_IRQ IRQ_IXP4XX_GPIO1 -#define GTWX5715_GPIO2_IRQ IRQ_IXP4XX_GPIO2 -#define GTWX5715_GPIO3_IRQ IRQ_IXP4XX_GPIO3 -#define GTWX5715_GPIO4_IRQ IRQ_IXP4XX_GPIO4 -#define GTWX5715_GPIO5_IRQ IRQ_IXP4XX_GPIO5 -#define GTWX5715_GPIO6_IRQ IRQ_IXP4XX_GPIO6 -#define GTWX5715_GPIO7_IRQ IRQ_IXP4XX_GPIO7 -#define GTWX5715_GPIO8_IRQ IRQ_IXP4XX_GPIO8 -#define GTWX5715_GPIO9_IRQ IRQ_IXP4XX_GPIO9 -#define GTWX5715_GPIO10_IRQ IRQ_IXP4XX_GPIO10 -#define GTWX5715_GPIO11_IRQ IRQ_IXP4XX_GPIO11 -#define GTWX5715_GPIO12_IRQ IRQ_IXP4XX_GPIO12 -#define GTWX5715_GPIO13_IRQ IRQ_IXP4XX_SW_INT1 -#define GTWX5715_GPIO14_IRQ IRQ_IXP4XX_SW_INT2 - -/* PCI controller GPIO to IRQ pin mappings - - INTA INTB -SLOT 0 10 11 -SLOT 1 11 10 - -*/ - -#define GTWX5715_PCI_SLOT0_DEVID 0 -#define GTWX5715_PCI_SLOT0_INTA_GPIO GTWX5715_GPIO10 -#define GTWX5715_PCI_SLOT0_INTB_GPIO GTWX5715_GPIO11 -#define GTWX5715_PCI_SLOT0_INTA_IRQ GTWX5715_GPIO10_IRQ -#define GTWX5715_PCI_SLOT0_INTB_IRQ GTWX5715_GPIO11_IRQ - -#define GTWX5715_PCI_SLOT1_DEVID 1 -#define GTWX5715_PCI_SLOT1_INTA_GPIO GTWX5715_GPIO11 -#define GTWX5715_PCI_SLOT1_INTB_GPIO GTWX5715_GPIO10 -#define GTWX5715_PCI_SLOT1_INTA_IRQ GTWX5715_GPIO11_IRQ -#define GTWX5715_PCI_SLOT1_INTB_IRQ GTWX5715_GPIO10_IRQ - -#define GTWX5715_PCI_SLOT_COUNT 2 -#define GTWX5715_PCI_INT_PIN_COUNT 2 - -/* - * GPIO 5,6,7 and12 are hard wired to the Kendin KS8995M Switch - * and operate as an SPI type interface. The details of the interface - * are available on Kendin/Micrel's web site. - */ - -#define GTWX5715_KSSPI_SELECT GTWX5715_GPIO5 -#define GTWX5715_KSSPI_TXD GTWX5715_GPIO6 -#define GTWX5715_KSSPI_CLOCK GTWX5715_GPIO7 -#define GTWX5715_KSSPI_RXD GTWX5715_GPIO12 - -/* - * The "reset" button is wired to GPIO 3. - * The GPIO is brought "low" when the button is pushed. - */ - -#define GTWX5715_BUTTON_GPIO GTWX5715_GPIO3 -#define GTWX5715_BUTTON_IRQ GTWX5715_GPIO3_IRQ - -/* - * Board Label Front Label - * LED1 Power - * LED2 Wireless-G - * LED3 not populated but could be - * LED4 Internet - * LED5 - LED8 Controlled by KS8995M Switch - * LED9 DMZ - */ - -#define GTWX5715_LED1_GPIO GTWX5715_GPIO2 -#define GTWX5715_LED2_GPIO GTWX5715_GPIO9 -#define GTWX5715_LED3_GPIO GTWX5715_GPIO8 -#define GTWX5715_LED4_GPIO GTWX5715_GPIO1 -#define GTWX5715_LED9_GPIO GTWX5715_GPIO4 -- cgit v0.10.2 From 8d3fdf31dd2066533861bb57ed7df1ae1b1f5fcc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Tue, 17 Nov 2009 18:48:23 +0100 Subject: IXP4xx: Introduce IXP4XX_GPIO_IRQ(n) macro and convert IXP4xx platform files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c index 14df8cf..845e1b5 100644 --- a/arch/arm/mach-ixp4xx/avila-pci.c +++ b/arch/arm/mach-ixp4xx/avila-pci.c @@ -27,49 +27,40 @@ #include #include -#define AVILA_PCI_MAX_DEV 4 -#define LOFT_PCI_MAX_DEV 6 -#define AVILA_PCI_IRQ_LINES 4 +#define AVILA_MAX_DEV 4 +#define LOFT_MAX_DEV 6 +#define IRQ_LINES 4 /* PCI controller GPIO to IRQ pin mappings */ -#define AVILA_PCI_INTA_PIN 11 -#define AVILA_PCI_INTB_PIN 10 -#define AVILA_PCI_INTC_PIN 9 -#define AVILA_PCI_INTD_PIN 8 - -#define IRQ_AVILA_PCI_INTA IRQ_IXP4XX_GPIO11 -#define IRQ_AVILA_PCI_INTB IRQ_IXP4XX_GPIO10 -#define IRQ_AVILA_PCI_INTC IRQ_IXP4XX_GPIO9 -#define IRQ_AVILA_PCI_INTD IRQ_IXP4XX_GPIO8 +#define INTA 11 +#define INTB 10 +#define INTC 9 +#define INTD 8 void __init avila_pci_preinit(void) { - set_irq_type(IRQ_AVILA_PCI_INTA, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_AVILA_PCI_INTB, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_AVILA_PCI_INTC, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_AVILA_PCI_INTD, IRQ_TYPE_LEVEL_LOW); - + set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init avila_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - static int pci_irq_table[AVILA_PCI_IRQ_LINES] = { - IRQ_AVILA_PCI_INTA, - IRQ_AVILA_PCI_INTB, - IRQ_AVILA_PCI_INTC, - IRQ_AVILA_PCI_INTD + static int pci_irq_table[IRQ_LINES] = { + IXP4XX_GPIO_IRQ(INTA), + IXP4XX_GPIO_IRQ(INTB), + IXP4XX_GPIO_IRQ(INTC), + IXP4XX_GPIO_IRQ(INTD) }; - int irq = -1; - if (slot >= 1 && - slot <= (machine_is_loft() ? LOFT_PCI_MAX_DEV : AVILA_PCI_MAX_DEV) && - pin >= 1 && pin <= AVILA_PCI_IRQ_LINES) { - irq = pci_irq_table[(slot + pin - 2) % 4]; - } + slot <= (machine_is_loft() ? LOFT_MAX_DEV : AVILA_MAX_DEV) && + pin >= 1 && pin <= IRQ_LINES) + return pci_irq_table[(slot + pin - 2) % 4]; - return irq; + return -1; } struct hw_pci avila_pci __initdata = { @@ -89,4 +80,3 @@ int __init avila_pci_init(void) } subsys_initcall(avila_pci_init); - diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c index 624f8fe..b978ea8 100644 --- a/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/arch/arm/mach-ixp4xx/coyote-pci.c @@ -23,30 +23,26 @@ #include #include -#define COYOTE_PCI_SLOT0_DEVID 14 -#define COYOTE_PCI_SLOT1_DEVID 15 +#define SLOT0_DEVID 14 +#define SLOT1_DEVID 15 /* PCI controller GPIO to IRQ pin mappings */ -#define COYOTE_PCI_SLOT0_PIN 6 -#define COYOTE_PCI_SLOT1_PIN 11 - -#define IRQ_COYOTE_PCI_SLOT0 IRQ_IXP4XX_GPIO6 -#define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11 +#define SLOT0_INTA 6 +#define SLOT1_INTA 11 void __init coyote_pci_preinit(void) { - set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQ_TYPE_LEVEL_LOW); - + set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init coyote_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - if (slot == COYOTE_PCI_SLOT0_DEVID) - return IRQ_COYOTE_PCI_SLOT0; - else if (slot == COYOTE_PCI_SLOT1_DEVID) - return IRQ_COYOTE_PCI_SLOT1; + if (slot == SLOT0_DEVID) + return IXP4XX_GPIO_IRQ(SLOT0_INTA); + else if (slot == SLOT1_DEVID) + return IXP4XX_GPIO_IRQ(SLOT1_INTA); else return -1; } diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c index 29a9e41..fa70fed 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-pci.c +++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c @@ -22,53 +22,42 @@ #include #include -#define DSMG600_PCI_MAX_DEV 4 -#define DSMG600_PCI_IRQ_LINES 3 +#define MAX_DEV 4 +#define IRQ_LINES 3 /* PCI controller GPIO to IRQ pin mappings */ -#define DSMG600_PCI_INTA_PIN 11 -#define DSMG600_PCI_INTB_PIN 10 -#define DSMG600_PCI_INTC_PIN 9 -#define DSMG600_PCI_INTD_PIN 8 -#define DSMG600_PCI_INTE_PIN 7 -#define DSMG600_PCI_INTF_PIN 6 - -#define IRQ_DSMG600_PCI_INTA IRQ_IXP4XX_GPIO11 -#define IRQ_DSMG600_PCI_INTB IRQ_IXP4XX_GPIO10 -#define IRQ_DSMG600_PCI_INTC IRQ_IXP4XX_GPIO9 -#define IRQ_DSMG600_PCI_INTD IRQ_IXP4XX_GPIO8 -#define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7 -#define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6 +#define INTA 11 +#define INTB 10 +#define INTC 9 +#define INTD 8 +#define INTE 7 +#define INTF 6 void __init dsmg600_pci_preinit(void) { - set_irq_type(IRQ_DSMG600_PCI_INTA, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_DSMG600_PCI_INTB, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_DSMG600_PCI_INTC, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_DSMG600_PCI_INTD, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_DSMG600_PCI_INTE, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_DSMG600_PCI_INTF, IRQ_TYPE_LEVEL_LOW); - + set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init dsmg600_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - static int pci_irq_table[DSMG600_PCI_MAX_DEV][DSMG600_PCI_IRQ_LINES] = - { - { IRQ_DSMG600_PCI_INTE, -1, -1 }, - { IRQ_DSMG600_PCI_INTA, -1, -1 }, - { IRQ_DSMG600_PCI_INTB, IRQ_DSMG600_PCI_INTC, IRQ_DSMG600_PCI_INTD }, - { IRQ_DSMG600_PCI_INTF, -1, -1 }, + static int pci_irq_table[MAX_DEV][IRQ_LINES] = { + { IXP4XX_GPIO_IRQ(INTE), -1, -1 }, + { IXP4XX_GPIO_IRQ(INTA), -1, -1 }, + { IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC), + IXP4XX_GPIO_IRQ(INTD) }, + { IXP4XX_GPIO_IRQ(INTF), -1, -1 }, }; - int irq = -1; - - if (slot >= 1 && slot <= DSMG600_PCI_MAX_DEV && - pin >= 1 && pin <= DSMG600_PCI_IRQ_LINES) - irq = pci_irq_table[slot-1][pin-1]; + if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) + return pci_irq_table[slot - 1][pin - 1]; - return irq; + return -1; } struct hw_pci __initdata dsmg600_pci = { diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c index 2a1701b..5a810c9 100644 --- a/arch/arm/mach-ixp4xx/fsg-pci.c +++ b/arch/arm/mach-ixp4xx/fsg-pci.c @@ -22,40 +22,35 @@ #include #include -#define FSG_PCI_MAX_DEV 3 -#define FSG_PCI_IRQ_LINES 3 +#define MAX_DEV 3 +#define IRQ_LINES 3 /* PCI controller GPIO to IRQ pin mappings */ -#define FSG_PCI_INTA_PIN 6 -#define FSG_PCI_INTB_PIN 7 -#define FSG_PCI_INTC_PIN 5 -#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6 -#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7 -#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5 +#define INTA 6 +#define INTB 7 +#define INTC 5 void __init fsg_pci_preinit(void) { - set_irq_type(IRQ_FSG_PCI_INTA, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_FSG_PCI_INTB, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_FSG_PCI_INTC, IRQ_TYPE_LEVEL_LOW); - + set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - static int pci_irq_table[FSG_PCI_IRQ_LINES] = { - IRQ_FSG_PCI_INTC, - IRQ_FSG_PCI_INTB, - IRQ_FSG_PCI_INTA, + static int pci_irq_table[IRQ_LINES] = { + IXP4XX_GPIO_IRQ(INTC), + IXP4XX_GPIO_IRQ(INTB), + IXP4XX_GPIO_IRQ(INTA), }; int irq = -1; - slot = slot - 11; + slot -= 11; - if (slot >= 1 && slot <= FSG_PCI_MAX_DEV && - pin >= 1 && pin <= FSG_PCI_IRQ_LINES) - irq = pci_irq_table[(slot - 1)]; + if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) + irq = pci_irq_table[slot - 1]; printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n", __func__, slot, pin, irq); diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c index a733b8f..1c28048 100644 --- a/arch/arm/mach-ixp4xx/goramo_mlr.c +++ b/arch/arm/mach-ixp4xx/goramo_mlr.c @@ -17,29 +17,28 @@ #include #include -#define xgpio_irq(n) (IRQ_IXP4XX_GPIO ## n) -#define gpio_irq(n) xgpio_irq(n) - #define SLOT_ETHA 0x0B /* IDSEL = AD21 */ #define SLOT_ETHB 0x0C /* IDSEL = AD20 */ #define SLOT_MPCI 0x0D /* IDSEL = AD19 */ #define SLOT_NEC 0x0E /* IDSEL = AD18 */ -#define IRQ_ETHA IRQ_IXP4XX_GPIO4 -#define IRQ_ETHB IRQ_IXP4XX_GPIO5 -#define IRQ_NEC IRQ_IXP4XX_GPIO3 -#define IRQ_MPCI IRQ_IXP4XX_GPIO12 - /* GPIO lines */ #define GPIO_SCL 0 #define GPIO_SDA 1 #define GPIO_STR 2 +#define GPIO_IRQ_NEC 3 +#define GPIO_IRQ_ETHA 4 +#define GPIO_IRQ_ETHB 5 #define GPIO_HSS0_DCD_N 6 #define GPIO_HSS1_DCD_N 7 +#define GPIO_UART0_DCD 8 +#define GPIO_UART1_DCD 9 #define GPIO_HSS0_CTS_N 10 #define GPIO_HSS1_CTS_N 11 +#define GPIO_IRQ_MPCI 12 #define GPIO_HSS1_RTS_N 13 #define GPIO_HSS0_RTS_N 14 +/* GPIO15 is not connected */ /* Control outputs from 74HC4094 */ #define CONTROL_HSS0_CLK_INT 0 @@ -152,7 +151,7 @@ static int hss_set_clock(int port, unsigned int clock_type) static irqreturn_t hss_dcd_irq(int irq, void *pdev) { - int i, port = (irq == gpio_irq(GPIO_HSS1_DCD_N)); + int i, port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N)); gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); set_carrier_cb_tab[port](pdev, !i); return IRQ_HANDLED; @@ -165,9 +164,9 @@ static int hss_open(int port, void *pdev, int i, irq; if (!port) - irq = gpio_irq(GPIO_HSS0_DCD_N); + irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N); else - irq = gpio_irq(GPIO_HSS1_DCD_N); + irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N); gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); set_carrier_cb(pdev, !i); @@ -188,8 +187,8 @@ static int hss_open(int port, void *pdev, static void hss_close(int port, void *pdev) { - free_irq(port ? gpio_irq(GPIO_HSS1_DCD_N) : gpio_irq(GPIO_HSS0_DCD_N), - pdev); + free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) : + IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev); set_carrier_cb_tab[!!port] = NULL; /* catch bugs */ set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1); @@ -421,8 +420,8 @@ static void __init gmlr_init(void) gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); - set_irq_type(gpio_irq(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); - set_irq_type(gpio_irq(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); + set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); + set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); set_control(CONTROL_HSS0_DTR_N, 1); set_control(CONTROL_HSS1_DTR_N, 1); @@ -442,10 +441,10 @@ static void __init gmlr_init(void) #ifdef CONFIG_PCI static void __init gmlr_pci_preinit(void) { - set_irq_type(IRQ_ETHA, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_ETHB, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_NEC, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_MPCI, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } @@ -466,10 +465,10 @@ static void __init gmlr_pci_postinit(void) static int __init gmlr_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { switch(slot) { - case SLOT_ETHA: return IRQ_ETHA; - case SLOT_ETHB: return IRQ_ETHB; - case SLOT_NEC: return IRQ_NEC; - default: return IRQ_MPCI; + case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA); + case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB); + case SLOT_NEC: return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC); + default: return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI); } } diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c index 6801185..276c614 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c @@ -30,20 +30,16 @@ #include #include -#define GTWX5715_PCI_SLOT0_DEVID 0 -#define GTWX5715_PCI_SLOT0_INTA_GPIO 10 -#define GTWX5715_PCI_SLOT0_INTB_GPIO 11 -#define GTWX5715_PCI_SLOT0_INTA_IRQ IRQ_IXP4XX_GPIO10 -#define GTWX5715_PCI_SLOT0_INTB_IRQ IRQ_IXP4XX_GPIO11 +#define SLOT0_DEVID 0 +#define SLOT0_INTA 10 +#define SLOT0_INTB 11 -#define GTWX5715_PCI_SLOT1_DEVID 1 -#define GTWX5715_PCI_SLOT1_INTA_GPIO 11 -#define GTWX5715_PCI_SLOT1_INTB_GPIO 10 -#define GTWX5715_PCI_SLOT1_INTA_IRQ IRQ_IXP4XX_GPIO11 -#define GTWX5715_PCI_SLOT1_INTB_IRQ IRQ_IXP4XX_GPIO10 +#define SLOT1_DEVID 1 +#define SLOT1_INTA 11 +#define SLOT1_INTB 10 -#define GTWX5715_PCI_SLOT_COUNT 2 -#define GTWX5715_PCI_INT_PIN_COUNT 2 +#define SLOT_COUNT 2 +#define INT_PIN_COUNT 2 /* * Slot 0 isn't actually populated with a card connector but @@ -53,11 +49,10 @@ */ void __init gtwx5715_pci_preinit(void) { - set_irq_type(GTWX5715_PCI_SLOT0_INTA_IRQ, IRQ_TYPE_LEVEL_LOW); - set_irq_type(GTWX5715_PCI_SLOT0_INTB_IRQ, IRQ_TYPE_LEVEL_LOW); - set_irq_type(GTWX5715_PCI_SLOT1_INTA_IRQ, IRQ_TYPE_LEVEL_LOW); - set_irq_type(GTWX5715_PCI_SLOT1_INTB_IRQ, IRQ_TYPE_LEVEL_LOW); - + set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTB), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTB), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } @@ -65,20 +60,19 @@ void __init gtwx5715_pci_preinit(void) static int __init gtwx5715_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int rc; - static int gtwx5715_irqmap - [GTWX5715_PCI_SLOT_COUNT] - [GTWX5715_PCI_INT_PIN_COUNT] = { - {GTWX5715_PCI_SLOT0_INTA_IRQ, GTWX5715_PCI_SLOT0_INTB_IRQ}, - {GTWX5715_PCI_SLOT1_INTA_IRQ, GTWX5715_PCI_SLOT1_INTB_IRQ}, -}; + static int gtwx5715_irqmap[SLOT_COUNT][INT_PIN_COUNT] = { + {IXP4XX_GPIO_IRQ(SLOT0_INTA), IXP4XX_GPIO_IRQ(SLOT0_INTB)}, + {IXP4XX_GPIO_IRQ(SLOT1_INTA), IXP4XX_GPIO_IRQ(SLOT1_INTB)}, + }; - if (slot >= GTWX5715_PCI_SLOT_COUNT || - pin >= GTWX5715_PCI_INT_PIN_COUNT) rc = -1; + if (slot >= SLOT_COUNT || pin >= INT_PIN_COUNT) + rc = -1; else - rc = gtwx5715_irqmap[slot][pin-1]; + rc = gtwx5715_irqmap[slot][pin - 1]; - printk("%s: Mapped slot %d pin %d to IRQ %d\n", __func__, slot, pin, rc); - return(rc); + printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n", + __func__, slot, pin, rc); + return rc; } struct hw_pci gtwx5715_pci __initdata = { @@ -93,9 +87,7 @@ struct hw_pci gtwx5715_pci __initdata = { int __init gtwx5715_pci_init(void) { if (machine_is_gtwx5715()) - { pci_common_init(>wx5715_pci); - } return 0; } diff --git a/arch/arm/mach-ixp4xx/include/mach/irqs.h b/arch/arm/mach-ixp4xx/include/mach/irqs.h index dbc20bf..7e6d4cc 100644 --- a/arch/arm/mach-ixp4xx/include/mach/irqs.h +++ b/arch/arm/mach-ixp4xx/include/mach/irqs.h @@ -15,7 +15,6 @@ #ifndef _ARCH_IXP4XX_IRQS_H_ #define _ARCH_IXP4XX_IRQS_H_ - #define IRQ_IXP4XX_NPEA 0 #define IRQ_IXP4XX_NPEB 1 #define IRQ_IXP4XX_NPEC 2 @@ -59,6 +58,9 @@ #define IRQ_IXP4XX_MCU_ECC 61 #define IRQ_IXP4XX_EXP_PE 62 +#define _IXP4XX_GPIO_IRQ(n) (IRQ_IXP4XX_GPIO ## n) +#define IXP4XX_GPIO_IRQ(n) _IXP4XX_GPIO_IRQ(n) + /* * Only first 32 sources are valid if running on IXP42x systems */ diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c index dc8b588..1ba165a 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c @@ -24,47 +24,38 @@ #include #include -#define IXDP425_PCI_MAX_DEV 4 -#define IXDP425_PCI_IRQ_LINES 4 +#define MAX_DEV 4 +#define IRQ_LINES 4 /* PCI controller GPIO to IRQ pin mappings */ -#define IXDP425_PCI_INTA_PIN 11 -#define IXDP425_PCI_INTB_PIN 10 -#define IXDP425_PCI_INTC_PIN 9 -#define IXDP425_PCI_INTD_PIN 8 +#define INTA 11 +#define INTB 10 +#define INTC 9 +#define INTD 8 -#define IRQ_IXDP425_PCI_INTA IRQ_IXP4XX_GPIO11 -#define IRQ_IXDP425_PCI_INTB IRQ_IXP4XX_GPIO10 -#define IRQ_IXDP425_PCI_INTC IRQ_IXP4XX_GPIO9 -#define IRQ_IXDP425_PCI_INTD IRQ_IXP4XX_GPIO8 void __init ixdp425_pci_preinit(void) { - set_irq_type(IRQ_IXDP425_PCI_INTA, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_IXDP425_PCI_INTB, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_IXDP425_PCI_INTC, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_IXDP425_PCI_INTD, IRQ_TYPE_LEVEL_LOW); - + set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init ixdp425_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - static int pci_irq_table[IXDP425_PCI_IRQ_LINES] = { - IRQ_IXDP425_PCI_INTA, - IRQ_IXDP425_PCI_INTB, - IRQ_IXDP425_PCI_INTC, - IRQ_IXDP425_PCI_INTD + static int pci_irq_table[IRQ_LINES] = { + IXP4XX_GPIO_IRQ(INTA), + IXP4XX_GPIO_IRQ(INTB), + IXP4XX_GPIO_IRQ(INTC), + IXP4XX_GPIO_IRQ(INTD) }; - int irq = -1; - - if (slot >= 1 && slot <= IXDP425_PCI_MAX_DEV && - pin >= 1 && pin <= IXDP425_PCI_IRQ_LINES) { - irq = pci_irq_table[(slot + pin - 2) % 4]; - } + if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) + return pci_irq_table[(slot + pin - 2) % 4]; - return irq; + return -1; } struct hw_pci ixdp425_pci __initdata = { @@ -85,4 +76,3 @@ int __init ixdp425_pci_init(void) } subsys_initcall(ixdp425_pci_init); - diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c index ac04fc1..d0cea34 100644 --- a/arch/arm/mach-ixp4xx/nas100d-pci.c +++ b/arch/arm/mach-ixp4xx/nas100d-pci.c @@ -21,49 +21,39 @@ #include #include -#define NAS100D_PCI_MAX_DEV 3 -#define NAS100D_PCI_IRQ_LINES 3 +#define MAX_DEV 3 +#define IRQ_LINES 3 /* PCI controller GPIO to IRQ pin mappings */ -#define NAS100D_PCI_INTA_PIN 11 -#define NAS100D_PCI_INTB_PIN 10 -#define NAS100D_PCI_INTC_PIN 9 -#define NAS100D_PCI_INTD_PIN 8 -#define NAS100D_PCI_INTE_PIN 7 - -#define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11 -#define IRQ_NAS100D_PCI_INTB IRQ_IXP4XX_GPIO10 -#define IRQ_NAS100D_PCI_INTC IRQ_IXP4XX_GPIO9 -#define IRQ_NAS100D_PCI_INTD IRQ_IXP4XX_GPIO8 -#define IRQ_NAS100D_PCI_INTE IRQ_IXP4XX_GPIO7 +#define INTA 11 +#define INTB 10 +#define INTC 9 +#define INTD 8 +#define INTE 7 void __init nas100d_pci_preinit(void) { - set_irq_type(IRQ_NAS100D_PCI_INTA, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_NAS100D_PCI_INTB, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_NAS100D_PCI_INTC, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_NAS100D_PCI_INTD, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_NAS100D_PCI_INTE, IRQ_TYPE_LEVEL_LOW); - + set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init nas100d_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - static int pci_irq_table[NAS100D_PCI_MAX_DEV][NAS100D_PCI_IRQ_LINES] = - { - { IRQ_NAS100D_PCI_INTA, -1, -1 }, - { IRQ_NAS100D_PCI_INTB, -1, -1 }, - { IRQ_NAS100D_PCI_INTC, IRQ_NAS100D_PCI_INTD, IRQ_NAS100D_PCI_INTE }, + static int pci_irq_table[MAX_DEV][IRQ_LINES] = { + { IXP4XX_GPIO_IRQ(INTA), -1, -1 }, + { IXP4XX_GPIO_IRQ(INTB), -1, -1 }, + { IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD), + IXP4XX_GPIO_IRQ(INTE) }, }; - int irq = -1; - - if (slot >= 1 && slot <= NAS100D_PCI_MAX_DEV && - pin >= 1 && pin <= NAS100D_PCI_IRQ_LINES) - irq = pci_irq_table[slot-1][pin-1]; + if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) + return pci_irq_table[slot - 1][pin - 1]; - return irq; + return -1; } struct hw_pci __initdata nas100d_pci = { diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c index 9665bb0..1eb5a90 100644 --- a/arch/arm/mach-ixp4xx/nslu2-pci.c +++ b/arch/arm/mach-ixp4xx/nslu2-pci.c @@ -21,43 +21,35 @@ #include #include -#define NSLU2_PCI_MAX_DEV 3 -#define NSLU2_PCI_IRQ_LINES 3 +#define MAX_DEV 3 +#define IRQ_LINES 3 /* PCI controller GPIO to IRQ pin mappings */ -#define NSLU2_PCI_INTA_PIN 11 -#define NSLU2_PCI_INTB_PIN 10 -#define NSLU2_PCI_INTC_PIN 9 -#define NSLU2_PCI_INTD_PIN 8 -#define IRQ_NSLU2_PCI_INTA IRQ_IXP4XX_GPIO11 -#define IRQ_NSLU2_PCI_INTB IRQ_IXP4XX_GPIO10 -#define IRQ_NSLU2_PCI_INTC IRQ_IXP4XX_GPIO9 +#define INTA 11 +#define INTB 10 +#define INTC 9 +#define INTD 8 void __init nslu2_pci_preinit(void) { - set_irq_type(IRQ_NSLU2_PCI_INTA, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_NSLU2_PCI_INTB, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_NSLU2_PCI_INTC, IRQ_TYPE_LEVEL_LOW); - + set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init nslu2_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - static int pci_irq_table[NSLU2_PCI_IRQ_LINES] = { - IRQ_NSLU2_PCI_INTA, - IRQ_NSLU2_PCI_INTB, - IRQ_NSLU2_PCI_INTC, + static int pci_irq_table[IRQ_LINES] = { + IXP4XX_GPIO_IRQ(INTA), + IXP4XX_GPIO_IRQ(INTB), + IXP4XX_GPIO_IRQ(INTC), }; - int irq = -1; - - if (slot >= 1 && slot <= NSLU2_PCI_MAX_DEV && - pin >= 1 && pin <= NSLU2_PCI_IRQ_LINES) { - irq = pci_irq_table[(slot + pin - 2) % NSLU2_PCI_IRQ_LINES]; - } + if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) + return pci_irq_table[(slot + pin - 2) % IRQ_LINES]; - return irq; + return -1; } struct hw_pci __initdata nslu2_pci = { -- cgit v0.10.2 From 0fd7dc7f6c88ba4a46ff472a30d175facc8b6292 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Wed, 18 Nov 2009 00:39:01 +0100 Subject: IXP4xx: GTWX5715 platform only has two PCI IRQ lines, not four. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Hałasa diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c index 276c614..25d2c33 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c @@ -31,15 +31,9 @@ #include #define SLOT0_DEVID 0 -#define SLOT0_INTA 10 -#define SLOT0_INTB 11 - #define SLOT1_DEVID 1 -#define SLOT1_INTA 11 -#define SLOT1_INTB 10 - -#define SLOT_COUNT 2 -#define INT_PIN_COUNT 2 +#define INTA 10 /* slot 1 has INTA and INTB crossed */ +#define INTB 11 /* * Slot 0 isn't actually populated with a card connector but @@ -49,26 +43,22 @@ */ void __init gtwx5715_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTB), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init gtwx5715_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - int rc; - static int gtwx5715_irqmap[SLOT_COUNT][INT_PIN_COUNT] = { - {IXP4XX_GPIO_IRQ(SLOT0_INTA), IXP4XX_GPIO_IRQ(SLOT0_INTB)}, - {IXP4XX_GPIO_IRQ(SLOT1_INTA), IXP4XX_GPIO_IRQ(SLOT1_INTB)}, - }; + int rc = -1; - if (slot >= SLOT_COUNT || pin >= INT_PIN_COUNT) - rc = -1; - else - rc = gtwx5715_irqmap[slot][pin - 1]; + if ((slot == SLOT0_DEVID && pin == 1) || + (slot == SLOT1_DEVID && pin == 2)) + rc = IXP4XX_GPIO_IRQ(INTA); + else if ((slot == SLOT0_DEVID && pin == 2) || + (slot == SLOT1_DEVID && pin == 1)) + rc = IXP4XX_GPIO_IRQ(INTB); printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n", __func__, slot, pin, rc); -- cgit v0.10.2