From 088eec1192a0ae60fc218796027e622008af36c0 Mon Sep 17 00:00:00 2001 From: Roy Huang Date: Thu, 21 Jun 2007 11:34:16 +0800 Subject: Blackfin arch: Add header files for BF548 Signed-off-by: Roy Huang Signed-off-by: Bryan Wu diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h new file mode 100644 index 0000000..ddc150e --- /dev/null +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -0,0 +1,72 @@ + +/* + * File: include/asm-blackfin/mach-bf548/anomaly.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _MACH_ANOMALY_H_ +#define _MACH_ANOMALY_H_ +#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in + slot1 and store of a P register in slot 2 is not + supported */ +#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive + Channel DMA stops */ +#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR + registers. */ +#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the + Shadow of a Conditional Branch */ +#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event + interrupt not functional */ +#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on + SPORT external receive and transmit clocks. */ +#define ANOMALY_05000272 /* Certain data cache write through modes fail for + VDDint <=0.9V */ +#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the + Boundary of Reserved Memory */ +#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and + LC Registers Are Interrupted */ +#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */ +#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */ +#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to + the USB FIFO Simultaneously */ +#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write() + function */ +#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional + */ +#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */ +#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM + Skew */ +#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */ +#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration + of Host DMA Port */ +#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent + Allowed Configuration on Host DMA Port */ +#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ + +#endif /* _MACH_ANOMALY_H_ */ diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h new file mode 100644 index 0000000..0b21102 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/bf548.h @@ -0,0 +1,284 @@ +/* + * File: include/asm-blackfin/mach-bf548/bf548.h + * Based on: + * Author: + * + * Created: + * Description: System MMR register and memory map for ADSP-BF548 + * + * Modified: + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MACH_BF548_H__ +#define __MACH_BF548_H__ + +/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */ + +#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */ +#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORTx_STAT */ +#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */ +#define UART_ERR_MASK_STAT1 (0x4) /* UARTx_IIR */ +#define UART_ERR_MASK_STAT0 (0x2) /* UARTx_IIR */ +#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | \ + RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */ + +#define OFFSET_(x) ((x) & 0x0000FFFF) + +/*some misc defines*/ +#define IMASK_IVG15 0x8000 +#define IMASK_IVG14 0x4000 +#define IMASK_IVG13 0x2000 +#define IMASK_IVG12 0x1000 + +#define IMASK_IVG11 0x0800 +#define IMASK_IVG10 0x0400 +#define IMASK_IVG9 0x0200 +#define IMASK_IVG8 0x0100 + +#define IMASK_IVG7 0x0080 +#define IMASK_IVGTMR 0x0040 +#define IMASK_IVGHW 0x0020 + +/***************************/ + + +#define BLKFIN_DSUBBANKS 4 +#define BLKFIN_DWAYS 2 +#define BLKFIN_DLINES 64 +#define BLKFIN_ISUBBANKS 4 +#define BLKFIN_IWAYS 4 +#define BLKFIN_ILINES 32 + +#define WAY0_L 0x1 +#define WAY1_L 0x2 +#define WAY01_L 0x3 +#define WAY2_L 0x4 +#define WAY02_L 0x5 +#define WAY12_L 0x6 +#define WAY012_L 0x7 + +#define WAY3_L 0x8 +#define WAY03_L 0x9 +#define WAY13_L 0xA +#define WAY013_L 0xB + +#define WAY32_L 0xC +#define WAY320_L 0xD +#define WAY321_L 0xE +#define WAYALL_L 0xF + +#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ + +/********************************* EBIU Settings ************************************/ +#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) +#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) + +#ifdef CONFIG_C_AMBEN_ALL +#define V_AMBEN AMBEN_ALL +#endif +#ifdef CONFIG_C_AMBEN +#define V_AMBEN 0x0 +#endif +#ifdef CONFIG_C_AMBEN_B0 +#define V_AMBEN AMBEN_B0 +#endif +#ifdef CONFIG_C_AMBEN_B0_B1 +#define V_AMBEN AMBEN_B0_B1 +#endif +#ifdef CONFIG_C_AMBEN_B0_B1_B2 +#define V_AMBEN AMBEN_B0_B1_B2 +#endif +#ifdef CONFIG_C_AMCKEN +#define V_AMCKEN AMCKEN +#else +#define V_AMCKEN 0x0 +#endif +#ifdef CONFIG_C_CDPRIO +#define V_CDPRIO 0x100 +#else +#define V_CDPRIO 0x0 +#endif + +#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) + +#define MAX_VC 650000000 +#define MIN_VC 50000000 + +/********************************PLL Settings **************************************/ +#ifdef CONFIG_BFIN_KERNEL_CLOCK +#if (CONFIG_VCO_MULT < 0) +#error "VCO Multiplier is less than 0. Please select a different value" +#endif + +#if (CONFIG_VCO_MULT == 0) +#error "VCO Multiplier should be greater than 0. Please select a different value" +#endif + +#if (CONFIG_VCO_MULT > 64) +#error "VCO Multiplier is more than 64. Please select a different value" +#endif + +#ifndef CONFIG_CLKIN_HALF +#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) +#else +#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) +#endif + +#ifndef CONFIG_PLL_BYPASS +#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) +#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +#if (CONFIG_SCLK_DIV < 1) +#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" +#endif + +#if (CONFIG_SCLK_DIV > 15) +#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" +#endif + +#if (CONFIG_CCLK_DIV != 1) +#if (CONFIG_CCLK_DIV != 2) +#if (CONFIG_CCLK_DIV != 4) +#if (CONFIG_CCLK_DIV != 8) +#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value" +#endif +#endif +#endif +#endif + +#if (CONFIG_VCO_HZ > MAX_VC) +#error "VCO selected is more than maximum value. Please change the VCO multipler" +#endif + +#if (CONFIG_SCLK_HZ > 133000000) +#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier" +#endif + +#if (CONFIG_SCLK_HZ < 27000000) +#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier" +#endif + +#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ) +#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) +#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) +#error "Please select sclk less than cclk" +#endif +#endif +#endif + +#if (CONFIG_CCLK_DIV == 1) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 +#endif +#if (CONFIG_CCLK_DIV == 2) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 +#endif +#if (CONFIG_CCLK_DIV == 4) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 +#endif +#if (CONFIG_CCLK_DIV == 8) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 +#endif +#ifndef CONFIG_CCLK_ACT_DIV +#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly +#endif + +#endif /* CONFIG_BFIN_KERNEL_CLOCK */ + +#ifdef CONFIG_BF542 +#define CPU "BF542" +#define CPUID 0x027c8000 +#endif +#ifdef CONFIG_BF544 +#define CPU "BF544" +#define CPUID 0x027c8000 +#endif +#ifdef CONFIG_BF548 +#define CPU "BF548" +#define CPUID 0x027c6000 +#endif +#ifdef CONFIG_BF549 +#define CPU "BF549" +#endif +#ifndef CPU +#define CPU "UNKNOWN" +#define CPUID 0x0 +#endif + +#if (CONFIG_MEM_SIZE % 4) +#error "SDRAM mem size must be multible of 4MB" +#endif + +#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) +#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) +#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) + +/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ + +#define ANOMALY_05000158_WORKAROUND 0x200 +#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ +#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ + | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#else /*Write Through */ +#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \ + | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) +#endif + + +#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) +#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) +#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) +#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) + +#define SIZE_1K 0x00000400 /* 1K */ +#define SIZE_4K 0x00001000 /* 4K */ +#define SIZE_1M 0x00100000 /* 1M */ +#define SIZE_4M 0x00400000 /* 4M */ + +#define MAX_CPLBS (16 * 2) + +/* +* Number of required data CPLB switchtable entries +* MEMSIZE / 4 (we mostly install 4M page size CPLBs +* approx 16 for smaller 1MB page size CPLBs for allignment purposes +* 1 for L1 Data Memory +* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO +* 1 for ASYNC Memory +*/ + + +#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2) + +/* +* Number of required instruction CPLB switchtable entries +* MEMSIZE / 4 (we mostly install 4M page size CPLBs +* approx 12 for smaller 1MB page size CPLBs for allignment purposes +* 1 for L1 Instruction Memory +* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO +*/ + +#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2) + +#endif /* __MACH_BF48_H__ */ diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h new file mode 100644 index 0000000..8f5d9c4 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h @@ -0,0 +1,147 @@ +#include +#include + +#define NR_PORTS 2 + +#define OFFSET_THR 0x00 /* Transmit Holding register */ +#define OFFSET_RBR 0x00 /* Receive Buffer register */ +#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +#define OFFSET_IER 0x04 /* Interrupt Enable Register */ +#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ +#define OFFSET_LCR 0x0C /* Line Control Register */ +#define OFFSET_MCR 0x10 /* Modem Control Register */ +#define OFFSET_LSR 0x14 /* Line Status Register */ +#define OFFSET_MSR 0x18 /* Modem Status Register */ +#define OFFSET_SCR 0x1C /* SCR Scratch Register */ +#define OFFSET_GCTL 0x24 /* Global Control Register */ + +#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) +#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) +#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) +#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) +#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) +#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) +#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) +#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) + +#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) +#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) +#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) +#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) +#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) +#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) + +#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) +# define CONFIG_SERIAL_BFIN_CTSRTS + +# ifndef CONFIG_UART0_CTS_PIN +# define CONFIG_UART0_CTS_PIN -1 +# endif + +# ifndef CONFIG_UART0_RTS_PIN +# define CONFIG_UART0_RTS_PIN -1 +# endif + +# ifndef CONFIG_UART1_CTS_PIN +# define CONFIG_UART1_CTS_PIN -1 +# endif + +# ifndef CONFIG_UART1_RTS_PIN +# define CONFIG_UART1_RTS_PIN -1 +# endif +#endif +/* + * The pin configuration is different from schematic + */ +struct bfin_serial_port { + struct uart_port port; + unsigned int old_status; +#ifdef CONFIG_SERIAL_BFIN_DMA + int tx_done; + int tx_count; + struct circ_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; + struct work_struct tx_dma_workqueue; +#else + struct work_struct cts_workqueue; +#endif +#ifdef CONFIG_SERIAL_BFIN_CTSRTS + int cts_pin; + int rts_pin; +#endif +}; + +struct bfin_serial_port bfin_serial_ports[NR_PORTS]; +struct bfin_serial_res { + unsigned long uart_base_addr; + int uart_irq; +#ifdef CONFIG_SERIAL_BFIN_DMA + unsigned int uart_tx_dma_channel; + unsigned int uart_rx_dma_channel; +#endif +#ifdef CONFIG_SERIAL_BFIN_CTSRTS + int uart_cts_pin; + int uart_rts_pin; +#endif +}; + +struct bfin_serial_res bfin_serial_resource[] = { +#ifdef CONFIG_SERIAL_BFIN_UART0 + { + 0xFFC00400, + IRQ_UART0_RX, +#ifdef CONFIG_SERIAL_BFIN_DMA + CH_UART0_TX, + CH_UART0_RX, +#endif +#ifdef CONFIG_BFIN_UART0_CTSRTS + CONFIG_UART0_CTS_PIN, + CONFIG_UART0_RTS_PIN, +#endif + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + { + 0xFFC02000, + IRQ_UART1_RX, +#ifdef CONFIG_SERIAL_BFIN_DMA + CH_UART1_TX, + CH_UART1_RX, +#endif +#ifdef CONFIG_BFIN_UART1_CTSRTS + CONFIG_UART1_CTS_PIN, + CONFIG_UART1_RTS_PIN, +#endif + }, +#endif +}; + +int nr_ports = ARRAY_SIZE(bfin_serial_resource); + +static void bfin_serial_hw_init(struct bfin_serial_port *uart) +{ + unsigned short val; + val = bfin_read16(BFIN_PORT_MUX); + val &= ~(PFDE | PFTE); + bfin_write16(BFIN_PORT_MUX, val); + + val = bfin_read16(PORTF_FER); + val |= 0xF; + bfin_write16(PORTF_FER, val); + +#ifdef CONFIG_SERIAL_BFIN_CTSRTS + if (uart->cts_pin >= 0) { + gpio_request(uart->cts_pin, NULL); + gpio_direction_input(uart->cts_pin); + } + + if (uart->rts_pin >= 0) { + gpio_request(uart->rts_pin, NULL); + gpio_direction_output(uart->rts_pin); + } +#endif +} diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h new file mode 100644 index 0000000..094c41a --- /dev/null +++ b/include/asm-blackfin/mach-bf548/blackfin.h @@ -0,0 +1,166 @@ +/* + * File: include/asm-blackfin/mach-bf548/blackfin.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _MACH_BLACKFIN_H_ +#define _MACH_BLACKFIN_H_ + +#define BF548_FAMILY + +#ifdef CONFIG_BF542 +#include "bf542.h" + +#ifdef CONFIG_BF544 +#include "bf544.h" +#endif + +#ifdef CONFIG_BF548 +#include "bf548.h" +#endif + +#ifdef CONFIG_BF549 +#include "bf549.h" +#endif + +#include "mem_map.h" +#include "anomaly.h" + +#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY)) +#ifdef CONFIG_BF542 +#include "cdefBF542.h" +#endif + +#ifdef CONFIG_BF544 +#include "cdefBF544.h" +#endif +#ifdef CONFIG_BF548 +#include "cdefBF548.h" +#endif +#ifdef CONFIG_BF549 +#include "cdefBF549.h" +#endif + +/* UART 1*/ +#define bfin_read_UART_THR() bfin_read_UART1_THR() +#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val) +#define bfin_read_UART_RBR() bfin_read_UART1_RBR() +#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val) +#define bfin_read_UART_DLL() bfin_read_UART1_DLL() +#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val) +#define bfin_read_UART_IER() bfin_read_UART1_IER() +#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val) +#define bfin_read_UART_DLH() bfin_read_UART1_DLH() +#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val) +#define bfin_read_UART_IIR() bfin_read_UART1_IIR() +#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val) +#define bfin_read_UART_LCR() bfin_read_UART1_LCR() +#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val) +#define bfin_read_UART_MCR() bfin_read_UART1_MCR() +#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val) +#define bfin_read_UART_LSR() bfin_read_UART1_LSR() +#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val) +#define bfin_read_UART_SCR() bfin_read_UART1_SCR() +#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) +#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() +#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) + +#endif + +/* MAP used DEFINES from BF533 to BF54x - so we don't need to change + * them in the driver, kernel, etc. */ + +/* UART_IIR Register */ +#define STATUS(x) ((x << 1) & 0x06) +#define STATUS_P1 0x02 +#define STATUS_P0 0x01 + +/* UART 0*/ + +/* DMA Channnel */ +#define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX() +#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val) +#define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX() +#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART1_TX(val) +#define CH_UART_RX CH_UART1_RX +#define CH_UART_TX CH_UART1_TX + +/* System Interrupt Controller */ +#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART1_RX() +#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART1_RX(val) +#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART1_TX() +#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART1_TX(val) +#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART1_ERROR() +#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART1_ERROR(val) +#define IRQ_UART_RX IRQ_UART1_RX +#define IRQ_UART_TX IRQ_UART1_TX +#define IRQ_UART_ERROR IRQ_UART1_ERROR + +/* MMR Registers*/ +#define bfin_read_UART_THR() bfin_read_UART1_THR() +#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val) +#define bfin_read_UART_RBR() bfin_read_UART1_RBR() +#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val) +#define bfin_read_UART_DLL() bfin_read_UART1_DLL() +#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val) +#define bfin_read_UART_IER() bfin_read_UART1_IER() +#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val) +#define bfin_read_UART_DLH() bfin_read_UART1_DLH() +#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val) +#define bfin_read_UART_IIR() bfin_read_UART1_IIR() +#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val) +#define bfin_read_UART_LCR() bfin_read_UART1_LCR() +#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val) +#define bfin_read_UART_MCR() bfin_read_UART1_MCR() +#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val) +#define bfin_read_UART_LSR() bfin_read_UART1_LSR() +#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val) +#define bfin_read_UART_SCR() bfin_read_UART1_SCR() +#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) +#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() +#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) +#define UART_THR UART1_THR +#define UART_RBR UART1_RBR +#define UART_DLL UART1_DLL +#define UART_IER UART1_IER +#define UART_DLH UART1_DLH +#define UART_IIR UART1_IIR +#define UART_LCR UART1_LCR +#define UART_MCR UART1_MCR +#define UART_LSR UART1_LSR +#define UART_SCR UART1_SCR +#define UART_GCTL UART1_GCTL + +/* PLL_DIV Masks */ +#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ + +#endif diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h new file mode 100644 index 0000000..5a334c8 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/dma.h @@ -0,0 +1,63 @@ +/* + * file: include/asm-blackfin/mach-bf548/dma.h + * based on: + * author: + * + * created: + * description: + * system mmr register map + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + +#ifndef _MACH_DMA_H_ +#define _MACH_DMA_H_ + +#define CH_SPORT0_RX 0 +#define CH_SPORT0_TX 1 +#define CH_SPORT1_RX 2 +#define CH_SPORT1_TX 3 +#define CH_SPI0 4 +#define CH_SPI1 5 +#define CH_UART0_RX 6 +#define CH_UART0_TX 7 +#define CH_UART1_RX 8 +#define CH_UART1_TX 9 +#define CH_ATAPI_RX 10 +#define CH_ATAPI_TX 11 + +#define CH_EPPI0 12 +#define CH_EPPI1 13 +#define CH_EPPI2 14 +#define CH_PIXC_IMAGE 15 +#define CH_PIXC_OVERLAY 16 +#define CH_PIXC_OUTPUT 17 +#define CH_SPORT2_RX 18 +#define CH_SPORT2_TX 19 +#define CH_SPORT3_RX 20 +#define CH_SPORT3_TX 21 +#define CH_SDH 22 +#define CH_SPI2 23 + +#define MAX_BLACKFIN_DMA_CHANNEL CH_SPI2 + +#endif diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h new file mode 100644 index 0000000..a7f6703 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/irq.h @@ -0,0 +1,306 @@ +/* + * file: include/asm-blackfin/mach-bf548/irq.h + * based on: include/asm-blackfin/mach-bf537/irq.h + * author: Roy Huang (roy.huang@analog.com) + * + * created: + * description: + * system mmr register map + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + +#ifndef _BF548_IRQ_H_ +#define _BF548_IRQ_H_ + +/* + * Interrupt source definitions + Event Source Core Event Name +Core Emulation ** +Events (highest priority) EMU 0 + Reset RST 1 + NMI NMI 2 + Exception EVX 3 + Reserved -- 4 + Hardware Error IVHW 5 + Core Timer IVTMR 6 * + +..... + + Software Interrupt 1 IVG14 31 + Software Interrupt 2 -- + (lowest priority) IVG15 32 * + */ + +#define NR_PERI_INTS 32 + +/* The ABSTRACT IRQ definitions */ +/** the first seven of the following are fixed, the rest you change if you need to **/ +#define IRQ_EMU 0 /* Emulation */ +#define IRQ_RST 1 /* reset */ +#define IRQ_NMI 2 /* Non Maskable */ +#define IRQ_EVX 3 /* Exception */ +#define IRQ_UNUSED 4 /* - unused interrupt*/ +#define IRQ_HWERR 5 /* Hardware Error */ +#define IRQ_CORETMR 6 /* Core timer */ + +#define BFIN_IRQ(x) ((x) + 7) + +#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ +#define IRQ_DMAC0_ERR BFIN_IRQ(1) /* DMAC0 Status Interrupt */ +#define IRQ_EPPI0_ERR BFIN_IRQ(2) /* EPPI0 Error Interrupt */ +#define IRQ_SPORT0_ERR BFIN_IRQ(3) /* SPORT0 Error Interrupt */ +#define IRQ_SPORT1_ERR BFIN_IRQ(4) /* SPORT1 Error Interrupt */ +#define IRQ_SPI0_ERR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */ +#define IRQ_UART0_ERR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */ +#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */ +#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */ +#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */ +#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */ +#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */ +#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */ +#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */ +#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */ +#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */ +#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */ +#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */ +#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */ +#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */ +#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ +#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ +#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ +#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */ +#define IRQ_DMAC1_ERR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ +#define IRQ_SPORT2_ERR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ +#define IRQ_SPORT3_ERR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ +#define IRQ_MXVR BFIN_IRQ(27) /* SPORT3 Error Interrupt */ +#define IRQ_SPI1_ERR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */ +#define IRQ_SPI2_ERR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */ +#define IRQ_UART1_ERR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */ +#define IRQ_UART2_ERR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ +#define IRQ_CAN0_ERR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ +#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ +#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ +#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ +#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ +#define IRQ_EPP1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ +#define IRQ_EPP2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ +#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ +#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */ +#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */ +#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */ +#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */ +#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */ +#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */ +#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */ +#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */ +#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */ +#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */ +#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */ +#define IRQ_MXVR_ERR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ +#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ +#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ +#define IRQ_EPP1_ERR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ +#define IRQ_EPP2_ERR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ +#define IRQ_UART3_ERR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ +#define IRQ_HOST_ERR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ +#define IRQ_PIXC_ERR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ +#define IRQ_NFC_ERR BFIN_IRQ(60) /* NFC Error Interrupt */ +#define IRQ_ATAPI_ERR BFIN_IRQ(61) /* ATAPI Error Interrupt */ +#define IRQ_CAN1_ERR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */ +#define IRQ_HS_DMA_ERR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */ +#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */ +#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */ +#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */ +#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */ +#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */ +#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */ +#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */ +#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */ +#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */ +#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */ +#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */ +#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */ +#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */ +#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */ +#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */ +#define IRQ_TMR0 BFIN_IRQ(86) /* Timer 0 Interrupt */ +#define IRQ_TMR1 BFIN_IRQ(87) /* Timer 1 Interrupt */ +#define IRQ_TMR2 BFIN_IRQ(88) /* Timer 2 Interrupt */ +#define IRQ_TMR3 BFIN_IRQ(89) /* Timer 3 Interrupt */ +#define IRQ_TMR4 BFIN_IRQ(90) /* Timer 4 Interrupt */ +#define IRQ_TMR5 BFIN_IRQ(91) /* Timer 5 Interrupt */ +#define IRQ_TMR6 BFIN_IRQ(92) /* Timer 6 Interrupt */ +#define IRQ_TMR7 BFIN_IRQ(93) /* Timer 7 Interrupt */ +#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ +#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ + +#define SYS_IRQS IRQ_PINT3 + +#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) +#define IRQ_PA0 BFIN_PA_IRQ(0) +#define IRQ_PA1 BFIN_PA_IRQ(1) +#define IRQ_PA2 BFIN_PA_IRQ(2) +#define IRQ_PA3 BFIN_PA_IRQ(3) +#define IRQ_PA4 BFIN_PA_IRQ(4) +#define IRQ_PA5 BFIN_PA_IRQ(5) +#define IRQ_PA6 BFIN_PA_IRQ(6) +#define IRQ_PA7 BFIN_PA_IRQ(7) +#define IRQ_PA8 BFIN_PA_IRQ(8) +#define IRQ_PA9 BFIN_PA_IRQ(9) +#define IRQ_PA10 BFIN_PA_IRQ(10) +#define IRQ_PA11 BFIN_PA_IRQ(11) +#define IRQ_PA12 BFIN_PA_IRQ(12) +#define IRQ_PA13 BFIN_PA_IRQ(13) +#define IRQ_PA14 BFIN_PA_IRQ(14) +#define IRQ_PA15 BFIN_PA_IRQ(15) + +#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1) +#define IRQ_PB0 BFIN_PB_IRQ(0) +#define IRQ_PB1 BFIN_PB_IRQ(1) +#define IRQ_PB2 BFIN_PB_IRQ(2) +#define IRQ_PB3 BFIN_PB_IRQ(3) +#define IRQ_PB4 BFIN_PB_IRQ(4) +#define IRQ_PB5 BFIN_PB_IRQ(5) +#define IRQ_PB6 BFIN_PB_IRQ(6) +#define IRQ_PB7 BFIN_PB_IRQ(7) +#define IRQ_PB8 BFIN_PB_IRQ(8) +#define IRQ_PB9 BFIN_PB_IRQ(9) +#define IRQ_PB10 BFIN_PB_IRQ(10) +#define IRQ_PB11 BFIN_PB_IRQ(11) +#define IRQ_PB12 BFIN_PB_IRQ(12) +#define IRQ_PB13 BFIN_PB_IRQ(13) +#define IRQ_PB14 BFIN_PB_IRQ(14) +#define IRQ_PB15 BFIN_PB_IRQ(15) + +#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1) +#define IRQ_PC0 BFIN_PC_IRQ(0) +#define IRQ_PC1 BFIN_PC_IRQ(1) +#define IRQ_PC2 BFIN_PC_IRQ(2) +#define IRQ_PC3 BFIN_PC_IRQ(3) +#define IRQ_PC4 BFIN_PC_IRQ(4) +#define IRQ_PC5 BFIN_PC_IRQ(5) +#define IRQ_PC6 BFIN_PC_IRQ(6) +#define IRQ_PC7 BFIN_PC_IRQ(7) +#define IRQ_PC8 BFIN_PC_IRQ(8) +#define IRQ_PC9 BFIN_PC_IRQ(9) +#define IRQ_PC10 BFIN_PC_IRQ(10) +#define IRQ_PC11 BFIN_PC_IRQ(11) +#define IRQ_PC12 BFIN_PC_IRQ(12) +#define IRQ_PC13 BFIN_PC_IRQ(13) +#define IRQ_PC14 BFIN_PC_IRQ(14) +#define IRQ_PC15 BFIN_PC_IRQ(15) + +#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1) +#define IRQ_PD0 BFIN_PD_IRQ(0) +#define IRQ_PD1 BFIN_PD_IRQ(1) +#define IRQ_PD2 BFIN_PD_IRQ(2) +#define IRQ_PD3 BFIN_PD_IRQ(3) +#define IRQ_PD4 BFIN_PD_IRQ(4) +#define IRQ_PD5 BFIN_PD_IRQ(5) +#define IRQ_PD6 BFIN_PD_IRQ(6) +#define IRQ_PD7 BFIN_PD_IRQ(7) +#define IRQ_PD8 BFIN_PD_IRQ(8) +#define IRQ_PD9 BFIN_PD_IRQ(9) +#define IRQ_PD10 BFIN_PD_IRQ(10) +#define IRQ_PD11 BFIN_PD_IRQ(11) +#define IRQ_PD12 BFIN_PD_IRQ(12) +#define IRQ_PD13 BFIN_PD_IRQ(13) +#define IRQ_PD14 BFIN_PD_IRQ(14) +#define IRQ_PD15 BFIN_PD_IRQ(15) + +#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1) +#define IRQ_PE0 BFIN_PE_IRQ(0) +#define IRQ_PE1 BFIN_PE_IRQ(1) +#define IRQ_PE2 BFIN_PE_IRQ(2) +#define IRQ_PE3 BFIN_PE_IRQ(3) +#define IRQ_PE4 BFIN_PE_IRQ(4) +#define IRQ_PE5 BFIN_PE_IRQ(5) +#define IRQ_PE6 BFIN_PE_IRQ(6) +#define IRQ_PE7 BFIN_PE_IRQ(7) +#define IRQ_PE8 BFIN_PE_IRQ(8) +#define IRQ_PE9 BFIN_PE_IRQ(9) +#define IRQ_PE10 BFIN_PE_IRQ(10) +#define IRQ_PE11 BFIN_PE_IRQ(11) +#define IRQ_PE12 BFIN_PE_IRQ(12) +#define IRQ_PE13 BFIN_PE_IRQ(13) +#define IRQ_PE14 BFIN_PE_IRQ(14) +#define IRQ_PE15 BFIN_PE_IRQ(15) + + +#ifdef CONFIG_IRQCHIP_DEMUX_GPIO +#define NR_IRQS (IRQ_PH15+1) +#else +#define NR_IRQS (IRQ_UART1_ERROR+1) +#endif + +#define IVG7 7 +#define IVG8 8 +#define IVG9 9 +#define IVG10 10 +#define IVG11 11 +#define IVG12 12 +#define IVG13 13 +#define IVG14 14 +#define IVG15 15 + +/* IAR0 BIT FIELDS*/ +#define IRQ_PLL_WAKEUP_POS 0 +#define IRQ_DMA_ERROR_POS 4 +#define IRQ_ERROR_POS 8 +#define IRQ_RTC_POS 12 +#define IRQ_PPI_POS 16 +#define IRQ_SPORT0_RX_POS 20 +#define IRQ_SPORT0_TX_POS 24 +#define IRQ_SPORT1_RX_POS 28 + +/* IAR1 BIT FIELDS*/ +#define IRQ_SPORT1_TX_POS 0 +#define IRQ_TWI_POS 4 +#define IRQ_SPI_POS 8 +#define IRQ_UART0_RX_POS 12 +#define IRQ_UART0_TX_POS 16 +#define IRQ_UART1_RX_POS 20 +#define IRQ_UART1_TX_POS 24 +#define IRQ_CAN_RX_POS 28 + +/* IAR2 BIT FIELDS*/ +#define IRQ_CAN_TX_POS 0 +#define IRQ_MAC_RX_POS 4 +#define IRQ_MAC_TX_POS 8 +#define IRQ_TMR0_POS 12 +#define IRQ_TMR1_POS 16 +#define IRQ_TMR2_POS 20 +#define IRQ_TMR3_POS 24 +#define IRQ_TMR4_POS 28 + +/* IAR3 BIT FIELDS*/ +#define IRQ_TMR5_POS 0 +#define IRQ_TMR6_POS 4 +#define IRQ_TMR7_POS 8 +#define IRQ_PROG_INTA_POS 12 +#define IRQ_PORTG_INTB_POS 16 +#define IRQ_MEM_DMA0_POS 20 +#define IRQ_MEM_DMA1_POS 24 +#define IRQ_WATCH_POS 28 + +#endif /* _BF537_IRQ_H_ */ diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h new file mode 100644 index 0000000..0cb279e --- /dev/null +++ b/include/asm-blackfin/mach-bf548/mem_init.h @@ -0,0 +1,189 @@ +/* + * File: include/asm-blackfin/mach-bf548/mem_init.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#if (CONFIG_MEM_MT46V32M16) + +#if defined CONFIG_CLKIN_HALF +#define CLKIN_HALF 1 +#else +#define CLKIN_HALF 0 +#endif + +#if defined CONFIG_PLL_BYPASS +#define PLL_BYPASS 1 +#else +#define PLL_BYPASS 0 +#endif + +/***************************************Currently Not Being Used *********************************/ +#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) +#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 + +#if (flash_EBIU_AMBCTL_TT > 3) +#define flash_EBIU_AMBCTL0_TT B0TT_4 +#endif +#if (flash_EBIU_AMBCTL_TT == 3) +#define flash_EBIU_AMBCTL0_TT B0TT_3 +#endif +#if (flash_EBIU_AMBCTL_TT == 2) +#define flash_EBIU_AMBCTL0_TT B0TT_2 +#endif +#if (flash_EBIU_AMBCTL_TT < 2) +#define flash_EBIU_AMBCTL0_TT B0TT_1 +#endif + +#if (flash_EBIU_AMBCTL_ST > 3) +#define flash_EBIU_AMBCTL0_ST B0ST_4 +#endif +#if (flash_EBIU_AMBCTL_ST == 3) +#define flash_EBIU_AMBCTL0_ST B0ST_3 +#endif +#if (flash_EBIU_AMBCTL_ST == 2) +#define flash_EBIU_AMBCTL0_ST B0ST_2 +#endif +#if (flash_EBIU_AMBCTL_ST < 2) +#define flash_EBIU_AMBCTL0_ST B0ST_1 +#endif + +#if (flash_EBIU_AMBCTL_HT > 2) +#define flash_EBIU_AMBCTL0_HT B0HT_3 +#endif +#if (flash_EBIU_AMBCTL_HT == 2) +#define flash_EBIU_AMBCTL0_HT B0HT_2 +#endif +#if (flash_EBIU_AMBCTL_HT == 1) +#define flash_EBIU_AMBCTL0_HT B0HT_1 +#endif +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) +#define flash_EBIU_AMBCTL0_HT B0HT_0 +#endif +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) +#define flash_EBIU_AMBCTL0_HT B0HT_1 +#endif + +#if (flash_EBIU_AMBCTL_WAT > 14) +#define flash_EBIU_AMBCTL0_WAT B0WAT_15 +#endif +#if (flash_EBIU_AMBCTL_WAT == 14) +#define flash_EBIU_AMBCTL0_WAT B0WAT_14 +#endif +#if (flash_EBIU_AMBCTL_WAT == 13) +#define flash_EBIU_AMBCTL0_WAT B0WAT_13 +#endif +#if (flash_EBIU_AMBCTL_WAT == 12) +#define flash_EBIU_AMBCTL0_WAT B0WAT_12 +#endif +#if (flash_EBIU_AMBCTL_WAT == 11) +#define flash_EBIU_AMBCTL0_WAT B0WAT_11 +#endif +#if (flash_EBIU_AMBCTL_WAT == 10) +#define flash_EBIU_AMBCTL0_WAT B0WAT_10 +#endif +#if (flash_EBIU_AMBCTL_WAT == 9) +#define flash_EBIU_AMBCTL0_WAT B0WAT_9 +#endif +#if (flash_EBIU_AMBCTL_WAT == 8) +#define flash_EBIU_AMBCTL0_WAT B0WAT_8 +#endif +#if (flash_EBIU_AMBCTL_WAT == 7) +#define flash_EBIU_AMBCTL0_WAT B0WAT_7 +#endif +#if (flash_EBIU_AMBCTL_WAT == 6) +#define flash_EBIU_AMBCTL0_WAT B0WAT_6 +#endif +#if (flash_EBIU_AMBCTL_WAT == 5) +#define flash_EBIU_AMBCTL0_WAT B0WAT_5 +#endif +#if (flash_EBIU_AMBCTL_WAT == 4) +#define flash_EBIU_AMBCTL0_WAT B0WAT_4 +#endif +#if (flash_EBIU_AMBCTL_WAT == 3) +#define flash_EBIU_AMBCTL0_WAT B0WAT_3 +#endif +#if (flash_EBIU_AMBCTL_WAT == 2) +#define flash_EBIU_AMBCTL0_WAT B0WAT_2 +#endif +#if (flash_EBIU_AMBCTL_WAT == 1) +#define flash_EBIU_AMBCTL0_WAT B0WAT_1 +#endif + +#if (flash_EBIU_AMBCTL_RAT > 14) +#define flash_EBIU_AMBCTL0_RAT B0RAT_15 +#endif +#if (flash_EBIU_AMBCTL_RAT == 14) +#define flash_EBIU_AMBCTL0_RAT B0RAT_14 +#endif +#if (flash_EBIU_AMBCTL_RAT == 13) +#define flash_EBIU_AMBCTL0_RAT B0RAT_13 +#endif +#if (flash_EBIU_AMBCTL_RAT == 12) +#define flash_EBIU_AMBCTL0_RAT B0RAT_12 +#endif +#if (flash_EBIU_AMBCTL_RAT == 11) +#define flash_EBIU_AMBCTL0_RAT B0RAT_11 +#endif +#if (flash_EBIU_AMBCTL_RAT == 10) +#define flash_EBIU_AMBCTL0_RAT B0RAT_10 +#endif +#if (flash_EBIU_AMBCTL_RAT == 9) +#define flash_EBIU_AMBCTL0_RAT B0RAT_9 +#endif +#if (flash_EBIU_AMBCTL_RAT == 8) +#define flash_EBIU_AMBCTL0_RAT B0RAT_8 +#endif +#if (flash_EBIU_AMBCTL_RAT == 7) +#define flash_EBIU_AMBCTL0_RAT B0RAT_7 +#endif +#if (flash_EBIU_AMBCTL_RAT == 6) +#define flash_EBIU_AMBCTL0_RAT B0RAT_6 +#endif +#if (flash_EBIU_AMBCTL_RAT == 5) +#define flash_EBIU_AMBCTL0_RAT B0RAT_5 +#endif +#if (flash_EBIU_AMBCTL_RAT == 4) +#define flash_EBIU_AMBCTL0_RAT B0RAT_4 +#endif +#if (flash_EBIU_AMBCTL_RAT == 3) +#define flash_EBIU_AMBCTL0_RAT B0RAT_3 +#endif +#if (flash_EBIU_AMBCTL_RAT == 2) +#define flash_EBIU_AMBCTL0_RAT B0RAT_2 +#endif +#if (flash_EBIU_AMBCTL_RAT == 1) +#define flash_EBIU_AMBCTL0_RAT B0RAT_1 +#endif + +#define flash_EBIU_AMBCTL0 \ + (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ + flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h new file mode 100644 index 0000000..72d80e8 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/mem_map.h @@ -0,0 +1,97 @@ +/* + * file: include/asm-blackfin/mach-bf548/mem_map.h + * based on: + * author: + * + * created: + * description: + * Memory MAP Common header file for blackfin BF537/6/4 of processors. + * rev: + * + * modified: + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + +#ifndef _MEM_MAP_548_H_ +#define _MEM_MAP_548_H_ + +#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ +#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ + +/* Async Memory Banks */ +#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ +#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */ +#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */ +#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */ +#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */ +#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */ +#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ +#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ + +/* Boot ROM Memory */ + +#define BOOT_ROM_START 0xEF000000 + +/* Level 1 Memory */ + +/* Memory Map for ADSP-BF548 processors */ +#ifdef CONFIG_BLKFIN_ICACHE +#define BLKFIN_ICACHESIZE (16*1024) +#else +#define BLKFIN_ICACHESIZE (0*1024) +#endif + +#define L1_CODE_START 0xFFA00000 +#define L1_DATA_A_START 0xFF800000 +#define L1_DATA_B_START 0xFF900000 + +#define L1_CODE_LENGTH 0xC000 + +#ifdef CONFIG_BLKFIN_DCACHE + +#ifdef CONFIG_BLKFIN_DCACHE_BANKA +#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) +#define L1_DATA_A_LENGTH (0x8000 - 0x4000) +#define L1_DATA_B_LENGTH 0x8000 +#define BLKFIN_DCACHESIZE (16*1024) +#define BLKFIN_DSUPBANKS 1 +#else +#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) +#define L1_DATA_A_LENGTH (0x8000 - 0x4000) +#define L1_DATA_B_LENGTH (0x8000 - 0x4000) +#define BLKFIN_DCACHESIZE (32*1024) +#define BLKFIN_DSUPBANKS 2 +#endif + +#else +#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) +#define L1_DATA_A_LENGTH 0x8000 +#define L1_DATA_B_LENGTH 0x8000 +#define BLKFIN_DCACHESIZE (0*1024) +#define BLKFIN_DSUPBANKS 0 +#endif /*CONFIG_BLKFIN_DCACHE*/ + +/* Scratch Pad Memory */ + +#if defined(CONFIG_BF54x) +#define L1_SCRATCH_START 0xFFB00000 +#define L1_SCRATCH_LENGTH 0x1000 +#endif + +#endif/* _MEM_MAP_548_H_ */ -- cgit v0.10.2 From 24a07a124198153540f8f43d9e91d16227aba66e Mon Sep 17 00:00:00 2001 From: Roy Huang Date: Thu, 12 Jul 2007 22:41:45 +0800 Subject: Blackfin arch: initial supporting for BF548-EZKIT The ADSP-BF54x was specifically designed to meet the needs of convergent multimedia applications where system performance and cost are essential ingredients. The integration of multimedia, human interface, and connectivity peripherals combined with increased system bandwidth and on-chip memory provides customers a platform to design the most demanding applications. Since now, ADSP-BF54x will be supported in the Linux kernel and bunch of related drivers such as USB OTG, ATAPI, NAND flash controller, LCD framebuffer, sound, touch screen will be submitted later. Please enjoy the show. Signed-off-by: Roy Huang Signed-off-by: Bryan Wu diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index d98bafc..385c262 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -71,6 +71,7 @@ config GENERIC_CALIBRATE_DELAY config IRQCHIP_DEMUX_GPIO bool + depends on (BF53x || BF561) default y source "init/Kconfig" @@ -114,6 +115,26 @@ config BF537 help BF537 Processor Support. +config BF542 + bool "BF542" + help + BF542 Processor Support. + +config BF544 + bool "BF544" + help + BF544 Processor Support. + +config BF548 + bool "BF548" + help + BF548 Processor Support. + +config BF549 + bool "BF549" + help + BF549 Processor Support. + config BF561 bool "BF561" help @@ -125,6 +146,11 @@ choice prompt "Silicon Rev" default BF_REV_0_2 if BF537 default BF_REV_0_3 if BF533 + default BF_REV_0_0 if BF549 + +config BF_REV_0_0 + bool "0.0" + depends on (BF549) config BF_REV_0_2 bool "0.2" @@ -150,6 +176,16 @@ config BF_REV_NONE endchoice +config BF53x + bool + depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) + default y + +config BF54x + bool + depends on (BF542 || BF544 || BF548 || BF549) + default y + config BFIN_DUAL_CORE bool depends on (BF561) @@ -198,6 +234,12 @@ config BFIN537_BLUETECHNIX_CM help CM-BF537 support for EVAL- and DEV-Board. +config BFIN548_EZKIT + bool "BF548-EZKIT" + depends on (BF548 || BF549) + help + BFIN548-EZKIT board Support. + config BFIN561_BLUETECHNIX_CM bool "Bluetechnix CM-BF561" depends on (BF561) @@ -265,6 +307,7 @@ config BFIN_SHARED_FLASH_ENET source "arch/blackfin/mach-bf533/Kconfig" source "arch/blackfin/mach-bf561/Kconfig" source "arch/blackfin/mach-bf537/Kconfig" +source "arch/blackfin/mach-bf548/Kconfig" menu "Board customizations" @@ -543,7 +586,7 @@ source "mm/Kconfig" config BFIN_DMA_5XX bool "Enable DMA Support" - depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561) + depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561 || BF54x) default y help DMA driver for BF5xx. @@ -839,7 +882,7 @@ endchoice endmenu -if (BF537 || BF533) +if (BF537 || BF533 || BF54x) menu "CPU Frequency scaling" diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile index 6971a44..1b75672 100644 --- a/arch/blackfin/Makefile +++ b/arch/blackfin/Makefile @@ -24,6 +24,8 @@ machine-$(CONFIG_BF533) := bf533 machine-$(CONFIG_BF534) := bf537 machine-$(CONFIG_BF536) := bf537 machine-$(CONFIG_BF537) := bf537 +machine-$(CONFIG_BF548) := bf548 +machine-$(CONFIG_BF549) := bf548 machine-$(CONFIG_BF561) := bf561 MACHINE := $(machine-y) export MACHINE diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile index f3b7d2f..93d2140 100644 --- a/arch/blackfin/kernel/Makefile +++ b/arch/blackfin/kernel/Makefile @@ -6,9 +6,10 @@ extra-y := init_task.o vmlinux.lds obj-y := \ entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ - sys_bfin.o time.o traps.o irqchip.o dma-mapping.o bfin_gpio.o \ - flat.o + sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o +obj-$(CONFIG_BF53x) += bfin_gpio.o +obj-$(CONFIG_BF561) += bfin_gpio.o obj-$(CONFIG_MODULES) += module.o obj-$(CONFIG_BFIN_DMA_5XX) += bfin_dma_5xx.o obj-$(CONFIG_DUAL_CORE_TEST_MODULE) += dualcore_test.o diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c index 069a896..8a16c2b 100644 --- a/arch/blackfin/kernel/bfin_dma_5xx.c +++ b/arch/blackfin/kernel/bfin_dma_5xx.c @@ -34,6 +34,7 @@ #include #include +#include #include #include @@ -45,67 +46,6 @@ ***************************************************************************/ static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL]; -#if defined (CONFIG_BF561) -static struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { - (struct dma_register *) DMA1_0_NEXT_DESC_PTR, - (struct dma_register *) DMA1_1_NEXT_DESC_PTR, - (struct dma_register *) DMA1_2_NEXT_DESC_PTR, - (struct dma_register *) DMA1_3_NEXT_DESC_PTR, - (struct dma_register *) DMA1_4_NEXT_DESC_PTR, - (struct dma_register *) DMA1_5_NEXT_DESC_PTR, - (struct dma_register *) DMA1_6_NEXT_DESC_PTR, - (struct dma_register *) DMA1_7_NEXT_DESC_PTR, - (struct dma_register *) DMA1_8_NEXT_DESC_PTR, - (struct dma_register *) DMA1_9_NEXT_DESC_PTR, - (struct dma_register *) DMA1_10_NEXT_DESC_PTR, - (struct dma_register *) DMA1_11_NEXT_DESC_PTR, - (struct dma_register *) DMA2_0_NEXT_DESC_PTR, - (struct dma_register *) DMA2_1_NEXT_DESC_PTR, - (struct dma_register *) DMA2_2_NEXT_DESC_PTR, - (struct dma_register *) DMA2_3_NEXT_DESC_PTR, - (struct dma_register *) DMA2_4_NEXT_DESC_PTR, - (struct dma_register *) DMA2_5_NEXT_DESC_PTR, - (struct dma_register *) DMA2_6_NEXT_DESC_PTR, - (struct dma_register *) DMA2_7_NEXT_DESC_PTR, - (struct dma_register *) DMA2_8_NEXT_DESC_PTR, - (struct dma_register *) DMA2_9_NEXT_DESC_PTR, - (struct dma_register *) DMA2_10_NEXT_DESC_PTR, - (struct dma_register *) DMA2_11_NEXT_DESC_PTR, - (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR, - (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR, - (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR, - (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR, - (struct dma_register *) MDMA2_D0_NEXT_DESC_PTR, - (struct dma_register *) MDMA2_S0_NEXT_DESC_PTR, - (struct dma_register *) MDMA2_D1_NEXT_DESC_PTR, - (struct dma_register *) MDMA2_S1_NEXT_DESC_PTR, - (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR, - (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR, - (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR, - (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR, -}; -#else -static struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { - (struct dma_register *) DMA0_NEXT_DESC_PTR, - (struct dma_register *) DMA1_NEXT_DESC_PTR, - (struct dma_register *) DMA2_NEXT_DESC_PTR, - (struct dma_register *) DMA3_NEXT_DESC_PTR, - (struct dma_register *) DMA4_NEXT_DESC_PTR, - (struct dma_register *) DMA5_NEXT_DESC_PTR, - (struct dma_register *) DMA6_NEXT_DESC_PTR, - (struct dma_register *) DMA7_NEXT_DESC_PTR, -#if (defined(CONFIG_BF537) || defined(CONFIG_BF534) || defined(CONFIG_BF536)) - (struct dma_register *) DMA8_NEXT_DESC_PTR, - (struct dma_register *) DMA9_NEXT_DESC_PTR, - (struct dma_register *) DMA10_NEXT_DESC_PTR, - (struct dma_register *) DMA11_NEXT_DESC_PTR, -#endif - (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, -}; -#endif /*------------------------------------------------------------------------------ * Set the Buffer Clear bit in the Configuration register of specific DMA @@ -138,149 +78,6 @@ static int __init blackfin_dma_init(void) arch_initcall(blackfin_dma_init); -/* - * Form the channel find the irq number for that channel. - */ -#if !defined(CONFIG_BF561) - -static int bf533_channel2irq(unsigned int channel) -{ - int ret_irq = -1; - - switch (channel) { - case CH_PPI: - ret_irq = IRQ_PPI; - break; - -#if (defined(CONFIG_BF537) || defined(CONFIG_BF534) || defined(CONFIG_BF536)) - case CH_EMAC_RX: - ret_irq = IRQ_MAC_RX; - break; - - case CH_EMAC_TX: - ret_irq = IRQ_MAC_TX; - break; - - case CH_UART1_RX: - ret_irq = IRQ_UART1_RX; - break; - - case CH_UART1_TX: - ret_irq = IRQ_UART1_TX; - break; -#endif - - case CH_SPORT0_RX: - ret_irq = IRQ_SPORT0_RX; - break; - - case CH_SPORT0_TX: - ret_irq = IRQ_SPORT0_TX; - break; - - case CH_SPORT1_RX: - ret_irq = IRQ_SPORT1_RX; - break; - - case CH_SPORT1_TX: - ret_irq = IRQ_SPORT1_TX; - break; - - case CH_SPI: - ret_irq = IRQ_SPI; - break; - - case CH_UART_RX: - ret_irq = IRQ_UART_RX; - break; - - case CH_UART_TX: - ret_irq = IRQ_UART_TX; - break; - - case CH_MEM_STREAM0_SRC: - case CH_MEM_STREAM0_DEST: - ret_irq = IRQ_MEM_DMA0; - break; - - case CH_MEM_STREAM1_SRC: - case CH_MEM_STREAM1_DEST: - ret_irq = IRQ_MEM_DMA1; - break; - } - return ret_irq; -} - -# define channel2irq(channel) bf533_channel2irq(channel) - -#else - -static int bf561_channel2irq(unsigned int channel) -{ - int ret_irq = -1; - - switch (channel) { - case CH_PPI0: - ret_irq = IRQ_PPI0; - break; - case CH_PPI1: - ret_irq = IRQ_PPI1; - break; - case CH_SPORT0_RX: - ret_irq = IRQ_SPORT0_RX; - break; - case CH_SPORT0_TX: - ret_irq = IRQ_SPORT0_TX; - break; - case CH_SPORT1_RX: - ret_irq = IRQ_SPORT1_RX; - break; - case CH_SPORT1_TX: - ret_irq = IRQ_SPORT1_TX; - break; - case CH_SPI: - ret_irq = IRQ_SPI; - break; - case CH_UART_RX: - ret_irq = IRQ_UART_RX; - break; - case CH_UART_TX: - ret_irq = IRQ_UART_TX; - break; - - case CH_MEM_STREAM0_SRC: - case CH_MEM_STREAM0_DEST: - ret_irq = IRQ_MEM_DMA0; - break; - case CH_MEM_STREAM1_SRC: - case CH_MEM_STREAM1_DEST: - ret_irq = IRQ_MEM_DMA1; - break; - case CH_MEM_STREAM2_SRC: - case CH_MEM_STREAM2_DEST: - ret_irq = IRQ_MEM_DMA2; - break; - case CH_MEM_STREAM3_SRC: - case CH_MEM_STREAM3_DEST: - ret_irq = IRQ_MEM_DMA3; - break; - - case CH_IMEM_STREAM0_SRC: - case CH_IMEM_STREAM0_DEST: - ret_irq = IRQ_IMEM_DMA0; - break; - case CH_IMEM_STREAM1_SRC: - case CH_IMEM_STREAM1_DEST: - ret_irq = IRQ_IMEM_DMA1; - break; - } - return ret_irq; -} - -# define channel2irq(channel) bf561_channel2irq(channel) - -#endif - /*------------------------------------------------------------------------------ * Request the specific DMA channel from the system. *-----------------------------------------------------------------------------*/ diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 83060f9..76bf2ce 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -500,8 +500,9 @@ static void __fill_code_cplbtab(struct cplb_tab *t, int i, cplb_data[i].end, SIZE_4M, cplb_data[i].i_conf); - } else { + } else #endif + { fill_cplbtab(t, cplb_data[i].start, a_start, diff --git a/arch/blackfin/mach-bf533/Makefile b/arch/blackfin/mach-bf533/Makefile index 76d2c2b..0322546 100644 --- a/arch/blackfin/mach-bf533/Makefile +++ b/arch/blackfin/mach-bf533/Makefile @@ -4,6 +4,6 @@ extra-y := head.o -obj-y := ints-priority.o +obj-y := ints-priority.o dma.o obj-$(CONFIG_CPU_FREQ_BF533) += cpu.o diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c new file mode 100644 index 0000000..c4e4054 --- /dev/null +++ b/arch/blackfin/mach-bf533/dma.c @@ -0,0 +1,95 @@ +/* + * File: arch/blackfin/mach-bf533/dma.c + * Based on: + * Author: + * + * Created: + * Description: This file contains the simple DMA Implementation for Blackfin + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include + +struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { + (struct dma_register *) DMA0_NEXT_DESC_PTR, + (struct dma_register *) DMA1_NEXT_DESC_PTR, + (struct dma_register *) DMA2_NEXT_DESC_PTR, + (struct dma_register *) DMA3_NEXT_DESC_PTR, + (struct dma_register *) DMA4_NEXT_DESC_PTR, + (struct dma_register *) DMA5_NEXT_DESC_PTR, + (struct dma_register *) DMA6_NEXT_DESC_PTR, + (struct dma_register *) DMA7_NEXT_DESC_PTR, + (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, + (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, + (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, + (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, +}; + +int bf533_channel2irq(unsigned int channel) +{ + int ret_irq = -1; + + switch (channel) { + case CH_PPI: + ret_irq = IRQ_PPI; + break; + + case CH_SPORT0_RX: + ret_irq = IRQ_SPORT0_RX; + break; + + case CH_SPORT0_TX: + ret_irq = IRQ_SPORT0_TX; + break; + + case CH_SPORT1_RX: + ret_irq = IRQ_SPORT1_RX; + break; + + case CH_SPORT1_TX: + ret_irq = IRQ_SPORT1_TX; + break; + + case CH_SPI: + ret_irq = IRQ_SPI; + break; + + case CH_UART_RX: + ret_irq = IRQ_UART_RX; + break; + + case CH_UART_TX: + ret_irq = IRQ_UART_TX; + break; + + case CH_MEM_STREAM0_SRC: + case CH_MEM_STREAM0_DEST: + ret_irq = IRQ_MEM_DMA0; + break; + + case CH_MEM_STREAM1_SRC: + case CH_MEM_STREAM1_DEST: + ret_irq = IRQ_MEM_DMA1; + break; + } + return ret_irq; +} diff --git a/arch/blackfin/mach-bf537/Makefile b/arch/blackfin/mach-bf537/Makefile index f32d442..7e7c9c8 100644 --- a/arch/blackfin/mach-bf537/Makefile +++ b/arch/blackfin/mach-bf537/Makefile @@ -4,6 +4,6 @@ extra-y := head.o -obj-y := ints-priority.o +obj-y := ints-priority.o dma.o obj-$(CONFIG_CPU_FREQ) += cpu.o diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c new file mode 100644 index 0000000..706cb97 --- /dev/null +++ b/arch/blackfin/mach-bf537/dma.c @@ -0,0 +1,115 @@ +/* + * File: arch/blackfin/mach-bf537/dma.c + * Based on: + * Author: + * + * Created: + * Description: This file contains the simple DMA Implementation for Blackfin + * + * Modified: + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include + +struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { + (struct dma_register *) DMA0_NEXT_DESC_PTR, + (struct dma_register *) DMA1_NEXT_DESC_PTR, + (struct dma_register *) DMA2_NEXT_DESC_PTR, + (struct dma_register *) DMA3_NEXT_DESC_PTR, + (struct dma_register *) DMA4_NEXT_DESC_PTR, + (struct dma_register *) DMA5_NEXT_DESC_PTR, + (struct dma_register *) DMA6_NEXT_DESC_PTR, + (struct dma_register *) DMA7_NEXT_DESC_PTR, + (struct dma_register *) DMA8_NEXT_DESC_PTR, + (struct dma_register *) DMA9_NEXT_DESC_PTR, + (struct dma_register *) DMA10_NEXT_DESC_PTR, + (struct dma_register *) DMA11_NEXT_DESC_PTR, + (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, + (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, + (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, + (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, +}; + +int channel2irq(unsigned int channel) +{ + int ret_irq = -1; + + switch (channel) { + case CH_PPI: + ret_irq = IRQ_PPI; + break; + + case CH_EMAC_RX: + ret_irq = IRQ_MAC_RX; + break; + + case CH_EMAC_TX: + ret_irq = IRQ_MAC_TX; + break; + + case CH_UART1_RX: + ret_irq = IRQ_UART1_RX; + break; + + case CH_UART1_TX: + ret_irq = IRQ_UART1_TX; + break; + + case CH_SPORT0_RX: + ret_irq = IRQ_SPORT0_RX; + break; + + case CH_SPORT0_TX: + ret_irq = IRQ_SPORT0_TX; + break; + + case CH_SPORT1_RX: + ret_irq = IRQ_SPORT1_RX; + break; + + case CH_SPORT1_TX: + ret_irq = IRQ_SPORT1_TX; + break; + + case CH_SPI: + ret_irq = IRQ_SPI; + break; + + case CH_UART_RX: + ret_irq = IRQ_UART_RX; + break; + + case CH_UART_TX: + ret_irq = IRQ_UART_TX; + break; + + case CH_MEM_STREAM0_SRC: + case CH_MEM_STREAM0_DEST: + ret_irq = IRQ_MEM_DMA0; + break; + + case CH_MEM_STREAM1_SRC: + case CH_MEM_STREAM1_DEST: + ret_irq = IRQ_MEM_DMA1; + break; + } + return ret_irq; +} diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig new file mode 100644 index 0000000..b28625e --- /dev/null +++ b/arch/blackfin/mach-bf548/Kconfig @@ -0,0 +1,282 @@ +if (BF54x) + +menu "BF548 Specific Configuration" + +comment "Interrupt Priority Assignment" +menu "Priority" + +config IRQ_PLL_WAKEUP + int "IRQ_PLL_WAKEUP" + default 7 +config IRQ_DMAC0_ERR + int "IRQ_DMAC0_ERR" + default 7 +config IRQ_EPPI0_ERR + int "IRQ_EPPI0_ERR" + default 7 +config IRQ_SPORT0_ERR + int "IRQ_SPORT0_ERR" + default 7 +config IRQ_SPORT1_ERR + int "IRQ_SPORT1_ERR" + default 7 +config IRQ_SPI0_ERR + int "IRQ_SPI0_ERR" + default 7 +config IRQ_UART0_ERR + int "IRQ_UART0_ERR" + default 7 +config IRQ_RTC + int "IRQ_RTC" + default 8 +config IRQ_EPPI0 + int "IRQ_EPPI0" + default 8 +config IRQ_SPORT0_RX + int "IRQ_SPORT0_RX" + default 9 +config IRQ_SPORT0_TX + int "IRQ_SPORT0_TX" + default 9 +config IRQ_SPORT1_RX + int "IRQ_SPORT1_RX" + default 9 +config IRQ_SPORT1_TX + int "IRQ_SPORT1_TX" + default 9 +config IRQ_SPI0 + int "IRQ_SPI0" + default 10 +config IRQ_UART0_RX + int "IRQ_UART0_RX" + default 10 +config IRQ_UART0_TX + int "IRQ_UART0_TX" + default 10 +config IRQ_TIMER8 + int "IRQ_TIMER8" + default 11 +config IRQ_TIMER9 + int "IRQ_TIMER9" + default 11 +config IRQ_TIMER10 + int "IRQ_TIMER10" + default 11 +config IRQ_PINT0 + int "IRQ_PINT0" + default 12 +config IRQ_PINT1 + int "IRQ_PINT0" + default 12 +config IRQ_MDMAS0 + int "IRQ_MDMAS0" + default 13 +config IRQ_MDMAS1 + int "IRQ_DMDMAS1" + default 13 +config IRQ_WATCHDOG + int "IRQ_WATCHDOG" + default 13 +config IRQ_DMAC1_ERR + int "IRQ_DMAC1_ERR" + default 7 +config IRQ_SPORT2_ERR + int "IRQ_SPORT2_ERR" + default 7 +config IRQ_SPORT3_ERR + int "IRQ_SPORT3_ERR" + default 7 +config IRQ_MXVR_DATA + int "IRQ MXVR Data" + default 7 +config IRQ_SPI1_ERR + int "IRQ_SPI1_ERR" + default 7 +config IRQ_SPI2_ERR + int "IRQ_SPI2_ERR" + default 7 +config IRQ_UART1_ERR + int "IRQ_UART1_ERR" + default 7 +config IRQ_UART2_ERR + int "IRQ_UART2_ERR" + default 7 +config IRQ_CAN0_ERR + int "IRQ_CAN0_ERR" + default 7 +config IRQ_SPORT2_RX + int "IRQ_SPORT2_RX" + default 9 +config IRQ_SPORT2_TX + int "IRQ_SPORT2_TX" + default 9 +config IRQ_SPORT3_RX + int "IRQ_SPORT3_RX" + default 9 +config IRQ_SPORT3_TX + int "IRQ_SPORT3_TX" + default 9 +config IRQ_EPPI1 + int "IRQ_EPPI1" + default 9 +config IRQ_EPPI2 + int "IRQ_EPPI2" + default 9 +config IRQ_SPI1 + int "IRQ_SPI1" + default 10 +config IRQ_SPI2 + int "IRQ_SPI2" + default 10 +config IRQ_UART1_RX + int "IRQ_UART1_RX" + default 10 +config IRQ_UART1_TX + int "IRQ_UART1_TX" + default 10 +config IRQ_ATAPI_RX + int "IRQ_ATAPI_RX" + default 10 +config IRQ_ATAPI_TX + int "IRQ_ATAPI_TX" + default 10 +config IRQ_TWI0 + int "IRQ_TWI0" + default 11 +config IRQ_TWI1 + int "IRQ_TWI1" + default 11 +config IRQ_CAN0_RX + int "IRQ_CAN_RX" + default 11 +config IRQ_CAN0_TX + int "IRQ_CAN_TX" + default 11 +config IRQ_MDMAS2 + int "IRQ_MDMAS2" + default 13 +config IRQ_MDMAS3 + int "IRQ_DMMAS3" + default 13 +config IRQ_MXVR_ERR + int "IRQ_MXVR_ERR" + default 11 +config IRQ_MXVR_MSG + int "IRQ_MXVR_MSG" + default 11 +config IRQ_MXVR_PKT + int "IRQ_MXVR_PKT" + default 11 +config IRQ_EPPI1_ERR + int "IRQ_EPPI1_ERR" + default 7 +config IRQ_EPPI2_ERR + int "IRQ_EPPI2_ERR" + default 7 +config IRQ_UART3_ERR + int "IRQ_UART3_ERR" + default 7 +config IRQ_HOST_ERR + int "IRQ_HOST_ERR" + default 7 +config IRQ_PIXC_ERR + int "IRQ_PIXC_ERR" + default 7 +config IRQ_NFC_ERR + int "IRQ_NFC_ERR" + default 7 +config IRQ_ATAPI_ERR + int "IRQ_ATAPI_ERR" + default 7 +config IRQ_CAN1_ERR + int "IRQ_CAN1_ERR" + default 7 +config IRQ_HS_DMA_ERR + int "IRQ Handshake DMA Status" + default 7 +config IRQ_PIXC_IN0 + int "IRQ PIXC IN0" + default 8 +config IRQ_PIXC_IN1 + int "IRQ PIXC IN1" + default 8 +config IRQ_PIXC_OUT + int "IRQ PIXC OUT" + default 8 +config IRQ_SDH + int "IRQ SDH" + default 8 +config IRQ_CNT + int "IRQ CNT" + default 8 +config IRQ_KEY + int "IRQ KEY" + default 8 +config IRQ_CAN1_RX + int "IRQ CAN1 RX" + default 11 +config IRQ_CAN1_TX + int "IRQ_CAN1_TX" + default 11 +config IRQ_SDH_MASK0 + int "IRQ_SDH_MASK0" + default 11 +config IRQ_SDH_MASK1 + int "IRQ_SDH_MASK1" + default 11 +config IRQ_USB_INT0 + int "IRQ USB INT0" + default 11 +config IRQ_USB_INT1 + int "IRQ USB INT1" + default 11 +config IRQ_USB_INT2 + int "IRQ USB INT2" + default 11 +config IRQ_USB_DMA + int "IRQ USB DMA" + default 11 +config IRQ_OTPSEC + int "IRQ OPTSEC" + default 11 +config IRQ_TIMER0 + int "IRQ_TIMER0" + default 11 +config IRQ_TIMER1 + int "IRQ_TIMER1" + default 11 +config IRQ_TIMER2 + int "IRQ_TIMER2" + default 11 +config IRQ_TIMER3 + int "IRQ_TIMER3" + default 11 +config IRQ_TIMER4 + int "IRQ_TIMER4" + default 11 +config IRQ_TIMER5 + int "IRQ_TIMER5" + default 11 +config IRQ_TIMER6 + int "IRQ_TIMER6" + default 11 +config IRQ_TIMER7 + int "IRQ_TIMER7" + default 11 +config IRQ_PINT2 + int "IRQ_PIN2" + default 11 +config IRQ_PINT3 + int "IRQ_PIN3" + default 11 + + help + Enter the priority numbers between 7-13 ONLY. Others are Reserved. + This applies to all the above. It is not recommended to assign the + highest priority number 7 to UART or any other device. + +endmenu + +endmenu + +endif diff --git a/arch/blackfin/mach-bf548/Makefile b/arch/blackfin/mach-bf548/Makefile new file mode 100644 index 0000000..060ad78 --- /dev/null +++ b/arch/blackfin/mach-bf548/Makefile @@ -0,0 +1,9 @@ +# +# arch/blackfin/mach-bf537/Makefile +# + +extra-y := head.o + +obj-y := ints-priority.o dma.o gpio.o + +obj-$(CONFIG_CPU_FREQ) += cpu.o diff --git a/arch/blackfin/mach-bf548/boards/Makefile b/arch/blackfin/mach-bf548/boards/Makefile new file mode 100644 index 0000000..486e07c --- /dev/null +++ b/arch/blackfin/mach-bf548/boards/Makefile @@ -0,0 +1,5 @@ +# +# arch/blackfin/mach-bf548/boards/Makefile +# + +obj-$(CONFIG_BFIN548_EZKIT) += ezkit.o led.o diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c new file mode 100644 index 0000000..100379c --- /dev/null +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -0,0 +1,114 @@ +/* + * File: arch/blackfin/mach-bf548/boards/ezkit.c + * Based on: arch/blackfin/mach-bf537/boards/ezkit.c + * Author: Aidan Williams + * + * Created: + * Description: + * + * Modified: + * Copyright 2005 National ICT Australia (NICTA) + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Name the Board for the /proc/cpuinfo + */ +char *bfin_board_name = "ADSP-BF548-EZKIT"; + +/* + * Driver needs to know address, irq and flag pin. + */ + +#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) +static struct platform_device rtc_device = { + .name = "rtc-bfin", + .id = -1, +}; +#endif + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) +static struct resource bfin_uart_resources[] = { +#ifdef CONFIG_SERIAL_BFIN_UART0 + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + { + .start = 0xFFC02000, + .end = 0xFFC020FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART2 + { + .start = 0xFFC02100, + .end = 0xFFC021FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART3 + { + .start = 0xFFC03100, + .end = 0xFFC031FF, + }, +#endif +}; + +static struct platform_device bfin_uart_device = { + .name = "bfin-uart", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_uart_resources), + .resource = bfin_uart_resources, +}; +#endif + +static struct platform_device *ezkit_devices[] __initdata = { +#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) + &rtc_device, +#endif + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) + &bfin_uart_device, +#endif +}; + +static int __init stamp_init(void) +{ + printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices)); + return 0; +} + +arch_initcall(stamp_init); diff --git a/arch/blackfin/mach-bf548/boards/led.S b/arch/blackfin/mach-bf548/boards/led.S new file mode 100644 index 0000000..f47daf3 --- /dev/null +++ b/arch/blackfin/mach-bf548/boards/led.S @@ -0,0 +1,172 @@ +/**************************************************** + * LED1 ---- PG6 LED2 ---- PG7 * + * LED3 ---- PG8 LED4 ---- PG9 * + * LED5 ---- PG10 LED6 ---- PG11 * + ****************************************************/ + +#include +#include + +/* All functions in this file save the registers they uses. + So there is no need to save any registers before calling them. */ + + .text; + +/* Initialize LEDs. */ + +ENTRY(_led_init) + LINK 0; + [--SP] = P0; + [--SP] = R0; + [--SP] = R1; + [--SP] = R2; + R1 = (PG6|PG7|PG8|PG9|PG10|PG11)(Z); + R2 = ~R1; + + P0.H = hi(PORTG_FER); + P0.L = lo(PORTG_FER); + R0 = W[P0](Z); + SSYNC; + R0 = R0 & R2; + W[P0] = R0.L; + SSYNC; + + P0.H = hi(PORTG_DIR_SET); + P0.L = lo(PORTG_DIR_SET); + W[P0] = R1.L; + SSYNC; + + P0.H = hi(PORTG_INEN); + P0.L = lo(PORTG_INEN); + R0 = W[P0](Z); + SSYNC; + R0 = R0 & R2; + W[P0] = R0.L; + SSYNC; + + R2 = [SP++]; + R1 = [SP++]; + R0 = [SP++]; + P0 = [SP++]; + RTS; + .size _led_init, .-_led_init + +/* Set one LED on. Leave other LEDs unchanged. + It expects the LED number passed through R0. */ + +ENTRY(_led_on) + LINK 0; + [--SP] = P0; + [--SP] = R1; + CALL _led_init; + R1 = 1; + R0 += 5; + R1 <<= R0; + P0.H = hi(PORTG_SET); + P0.L = lo(PORTG_SET); + W[P0] = R1.L; + SSYNC; + R1 = [SP++]; + P0 = [SP++]; + UNLINK; + RTS; + .size _led_on, .-_led_on + +/* Set one LED off. Leave other LEDs unchanged. */ + +ENTRY(_led_off) + LINK 0; + [--SP] = P0; + [--SP] = R1; + CALL _led_init; + R1 = 1; + R0 += 5; + R1 <<= R0; + P0.H = hi(PORTG_CLEAR); + P0.L = lo(PORTG_CLEAR); + W[P0] = R1.L; + SSYNC; + R1 = [SP++]; + P0 = [SP++]; + UNLINK; + RTS; + .size _led_off, .-_led_off + +/* Toggle one LED. Leave other LEDs unchanged. */ + +ENTRY(_led_toggle) + LINK 0; + [--SP] = P0; + [--SP] = R1; + CALL _led_init; + R1 = 1; + R0 += 5; + R1 <<= R0; + P0.H = hi(PORTG); + P0.L = lo(PORTG); + R0 = W[P0](Z); + SSYNC; + R0 = R0 ^ R1; + W[P0] = R0.L; + SSYNC; + R1 = [SP++]; + P0 = [SP++]; + UNLINK; + RTS; + .size _led_toggle, .-_led_toggle + +/* Display the number using LEDs in binary format. */ + +ENTRY(_led_disp_num) + LINK 0; + [--SP] = P0; + [--SP] = R1; + [--SP] = R2; + CALL _led_init; + R1 = 0x3f(X); + R0 = R0 & R1; + R2 = 6(X); + R0 <<= R2; + R1 <<= R2; + P0.H = hi(PORTG); + P0.L = lo(PORTG); + R2 = W[P0](Z); + SSYNC; + R1 = ~R1; + R2 = R2 & R1; + R2 = R2 | R0; + W[P0] = R2.L; + SSYNC; + R2 = [SP++]; + R1 = [SP++]; + P0 = [SP++]; + UNLINK; + RTS; + .size _led_disp_num, .-_led_disp_num + +/* Toggle the number using LEDs in binary format. */ + +ENTRY(_led_toggle_num) + LINK 0; + [--SP] = P0; + [--SP] = R1; + [--SP] = R2; + CALL _led_init; + R1 = 0x3f(X); + R0 = R0 & R1; + R1 = 6(X); + R0 <<= R1; + P0.H = hi(PORTG); + P0.L = lo(PORTG); + R1 = W[P0](Z); + SSYNC; + R1 = R1 ^ R0; + W[P0] = R1.L; + SSYNC; + R2 = [SP++]; + R1 = [SP++]; + P0 = [SP++]; + UNLINK; + RTS; + .size _led_toggle_num, .-_led_toggle_num + diff --git a/arch/blackfin/mach-bf548/cpu.c b/arch/blackfin/mach-bf548/cpu.c new file mode 100644 index 0000000..4298a3c --- /dev/null +++ b/arch/blackfin/mach-bf548/cpu.c @@ -0,0 +1,159 @@ +/* + * File: arch/blackfin/mach-bf548/cpu.c + * Based on: + * Author: + * + * Created: + * Description: clock scaling for the bf54x + * + * Modified: + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +/* CONFIG_CLKIN_HZ=25000000 */ +#define VCO5 (CONFIG_CLKIN_HZ*45) +#define VCO4 (CONFIG_CLKIN_HZ*36) +#define VCO3 (CONFIG_CLKIN_HZ*27) +#define VCO2 (CONFIG_CLKIN_HZ*18) +#define VCO1 (CONFIG_CLKIN_HZ*9) +#define VCO(x) VCO##x + +#define MFREQ(x) {VCO(x),VCO(x)/4},{VCO(x),VCO(x)/2},{VCO(x),VCO(x)} +/* frequency */ +static struct cpufreq_frequency_table bf548_freq_table[] = { + MFREQ(1), + MFREQ(3), + {VCO4, VCO4 / 2}, {VCO4, VCO4}, + MFREQ(5), + {0, CPUFREQ_TABLE_END}, +}; + +/* + * dpmc_fops->ioctl() + * static int dpmc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) + */ +static int bf548_getfreq(unsigned int cpu) +{ + unsigned long cclk_mhz; + + /* The driver only support single cpu */ + if (cpu == 0) + dpmc_fops.ioctl(NULL, NULL, IOCTL_GET_CORECLOCK, &cclk_mhz); + else + cclk_mhz = -1; + + return cclk_mhz; +} + +static int bf548_target(struct cpufreq_policy *policy, + unsigned int target_freq, unsigned int relation) +{ + unsigned long cclk_mhz; + unsigned long vco_mhz; + unsigned long flags; + unsigned int index; + struct cpufreq_freqs freqs; + + if (cpufreq_frequency_table_target(policy, bf548_freq_table, target_freq, relation, &index)) + return -EINVAL; + + cclk_mhz = bf548_freq_table[index].frequency; + vco_mhz = bf548_freq_table[index].index; + + dpmc_fops.ioctl(NULL, NULL, IOCTL_CHANGE_FREQUENCY, &vco_mhz); + freqs.old = bf548_getfreq(0); + freqs.new = cclk_mhz; + freqs.cpu = 0; + + pr_debug("cclk begin change to cclk %d,vco=%d,index=%d,target=%d,oldfreq=%d\n", + cclk_mhz, vco_mhz, index, target_freq, freqs.old); + + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + local_irq_save(flags); + dpmc_fops.ioctl(NULL, NULL, IOCTL_SET_CCLK, &cclk_mhz); + local_irq_restore(flags); + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + vco_mhz = get_vco(); + cclk_mhz = get_cclk(); + return 0; +} + +/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on + * this platform, anyway. + */ +static int bf548_verify_speed(struct cpufreq_policy *policy) +{ + return cpufreq_frequency_table_verify(policy, &bf548_freq_table); +} + +static int __init __bf548_cpu_init(struct cpufreq_policy *policy) +{ + if (policy->cpu != 0) + return -EINVAL; + + policy->governor = CPUFREQ_DEFAULT_GOVERNOR; + + policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; + /*Now ,only support one cpu */ + policy->cur = bf548_getfreq(0); + cpufreq_frequency_table_get_attr(bf548_freq_table, policy->cpu); + return cpufreq_frequency_table_cpuinfo(policy, bf548_freq_table); +} + +static struct freq_attr *bf548_freq_attr[] = { + &cpufreq_freq_attr_scaling_available_freqs, + NULL, +}; + +static struct cpufreq_driver bf548_driver = { + .verify = bf548_verify_speed, + .target = bf548_target, + .get = bf548_getfreq, + .init = __bf548_cpu_init, + .name = "bf548", + .owner = THIS_MODULE, + .attr = bf548_freq_attr, +}; + +static int __init bf548_cpu_init(void) +{ + return cpufreq_register_driver(&bf548_driver); +} + +static void __exit bf548_cpu_exit(void) +{ + cpufreq_unregister_driver(&bf548_driver); +} + +MODULE_AUTHOR("Mickael Kang"); +MODULE_DESCRIPTION("cpufreq driver for BF548 CPU"); +MODULE_LICENSE("GPL"); + +module_init(bf548_cpu_init); +module_exit(bf548_cpu_exit); diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c new file mode 100644 index 0000000..a818411 --- /dev/null +++ b/arch/blackfin/mach-bf548/dma.c @@ -0,0 +1,156 @@ +/* + * File: arch/blackfin/mach-bf561/dma.c + * Based on: + * Author: + * + * Created: + * Description: This file contains the simple DMA Implementation for Blackfin + * + * Modified: + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + + struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { + (struct dma_register *) DMA0_NEXT_DESC_PTR, + (struct dma_register *) DMA1_NEXT_DESC_PTR, + (struct dma_register *) DMA2_NEXT_DESC_PTR, + (struct dma_register *) DMA3_NEXT_DESC_PTR, + (struct dma_register *) DMA4_NEXT_DESC_PTR, + (struct dma_register *) DMA5_NEXT_DESC_PTR, + (struct dma_register *) DMA6_NEXT_DESC_PTR, + (struct dma_register *) DMA7_NEXT_DESC_PTR, + (struct dma_register *) DMA8_NEXT_DESC_PTR, + (struct dma_register *) DMA9_NEXT_DESC_PTR, + (struct dma_register *) DMA10_NEXT_DESC_PTR, + (struct dma_register *) DMA11_NEXT_DESC_PTR, + (struct dma_register *) DMA12_NEXT_DESC_PTR, + (struct dma_register *) DMA13_NEXT_DESC_PTR, + (struct dma_register *) DMA14_NEXT_DESC_PTR, + (struct dma_register *) DMA15_NEXT_DESC_PTR, + (struct dma_register *) DMA16_NEXT_DESC_PTR, + (struct dma_register *) DMA17_NEXT_DESC_PTR, + (struct dma_register *) DMA18_NEXT_DESC_PTR, + (struct dma_register *) DMA19_NEXT_DESC_PTR, + (struct dma_register *) DMA20_NEXT_DESC_PTR, + (struct dma_register *) DMA21_NEXT_DESC_PTR, + (struct dma_register *) DMA22_NEXT_DESC_PTR, + (struct dma_register *) DMA23_NEXT_DESC_PTR, + (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, + (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, + (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, + (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, + (struct dma_register *) MDMA_D2_NEXT_DESC_PTR, + (struct dma_register *) MDMA_S2_NEXT_DESC_PTR, + (struct dma_register *) MDMA_D3_NEXT_DESC_PTR, + (struct dma_register *) MDMA_S3_NEXT_DESC_PTR, +}; + +int channel2irq(unsigned int channel) +{ + int ret_irq = -1; + + switch (channel) { + case CH_SPORT0_RX: + ret_irq = IRQ_SPORT0_RX; + break; + case CH_SPORT0_TX: + ret_irq = IRQ_SPORT0_TX; + break; + case CH_SPORT1_RX: + ret_irq = IRQ_SPORT1_RX; + break; + case CH_SPORT1_TX: + ret_irq = IRQ_SPORT1_TX; + case CH_SPI0: + ret_irq = IRQ_SPI0; + break; + case CH_SPI1: + ret_irq = IRQ_SPI1; + break; + case CH_UART0_RX: + ret_irq = IRQ_UART_RX; + break; + case CH_UART0_TX: + ret_irq = IRQ_UART_TX; + break; + case CH_UART1_RX: + ret_irq = IRQ_UART_RX; + break; + case CH_UART1_TX: + ret_irq = IRQ_UART_TX; + break; + case CH_EPPI0: + ret_irq = IRQ_EPPI0; + break; + case CH_EPPI1: + ret_irq = IRQ_EPPI1; + break; + case CH_EPPI2: + ret_irq = IRQ_EPPI2; + break; + case CH_PIXC_IMAGE: + ret_irq = IRQ_PIXC_IN0; + break; + case CH_PIXC_OVERLAY: + ret_irq = IRQ_PIXC_IN1; + break; + case CH_PIXC_OUTPUT: + ret_irq = IRQ_PIXC_OUT; + break; + case CH_SPORT2_RX: + ret_irq = IRQ_SPORT2_RX; + break; + case CH_SPORT2_TX: + ret_irq = IRQ_SPORT2_TX; + break; + case CH_SPORT3_RX: + ret_irq = IRQ_SPORT3_RX; + break; + case CH_SPORT3_TX: + ret_irq = IRQ_SPORT3_TX; + break; + case CH_SDH: + ret_irq = IRQ_SDH; + break; + case CH_SPI2: + ret_irq = IRQ_SPI2; + break; + case CH_MEM_STREAM0_SRC: + case CH_MEM_STREAM0_DEST: + ret_irq = IRQ_MDMAS0; + break; + case CH_MEM_STREAM1_SRC: + case CH_MEM_STREAM1_DEST: + ret_irq = IRQ_MDMAS1; + break; + case CH_MEM_STREAM2_SRC: + case CH_MEM_STREAM2_DEST: + ret_irq = IRQ_MDMAS2; + break; + case CH_MEM_STREAM3_SRC: + case CH_MEM_STREAM3_DEST: + ret_irq = IRQ_MDMAS3; + break; + } + return ret_irq; +} diff --git a/arch/blackfin/mach-bf548/gpio.c b/arch/blackfin/mach-bf548/gpio.c new file mode 100644 index 0000000..854896d --- /dev/null +++ b/arch/blackfin/mach-bf548/gpio.c @@ -0,0 +1,175 @@ +/* + * File: arch/blackfin/mach-bf548/gpio.c + * Based on: + * Author: Michael Hennerich (hennerich@blackfin.uclinux.org) + * + * Created: + * Description: GPIO Abstraction Layer + * + * Modified: + * Copyright 2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = { + (struct gpio_port_t *) PORTA_FER, + (struct gpio_port_t *) PORTB_FER, + (struct gpio_port_t *) PORTC_FER, + (struct gpio_port_t *) PORTD_FER, + (struct gpio_port_t *) PORTE_FER, + (struct gpio_port_t *) PORTF_FER, + (struct gpio_port_t *) PORTG_FER, + (struct gpio_port_t *) PORTH_FER, + (struct gpio_port_t *) PORTI_FER, + (struct gpio_port_t *) PORTJ_FER, +}; + +static unsigned short reserved_map[gpio_bank(MAX_BLACKFIN_GPIOS)]; + +inline int check_gpio(unsigned short gpio) +{ + if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 \ + || gpio == GPIO_PH14 || gpio == GPIO_PH15 \ + || gpio > MAX_BLACKFIN_GPIOS) + return -EINVAL; + return 0; +} + +static void port_setup(unsigned short gpio, unsigned short usage) +{ + if (usage == GPIO_USAGE) { + if (gpio_array[gpio_bank(gpio)]->port_fer & gpio_bit(gpio)) + printk(KERN_WARNING "bfin-gpio: Possible Conflict with Peripheral " + "usage and GPIO %d detected!\n", gpio); + gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio); + } else + gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio); + SSYNC(); +} + +static int __init bfin_gpio_init(void) +{ + int i; + + printk(KERN_INFO "Blackfin GPIO Controller\n"); + + for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=GPIO_BANKSIZE) + reserved_map[gpio_bank(i)] = 0; + + return 0; +} + +arch_initcall(bfin_gpio_init); + + +/*********************************************************** +* +* FUNCTIONS: Blackfin GPIO Driver +* +* INPUTS/OUTPUTS: +* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS +* +* +* DESCRIPTION: Blackfin GPIO Driver API +* +* CAUTION: +************************************************************* +* MODIFICATION HISTORY : +**************************************************************/ + +int gpio_request(unsigned short gpio, const char *label) +{ + unsigned long flags; + + if (check_gpio(gpio) < 0) + return -EINVAL; + + local_irq_save(flags); + + if (unlikely(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio))) { + printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved!\n", gpio); + dump_stack(); + local_irq_restore(flags); + return -EBUSY; + } + reserved_map[gpio_bank(gpio)] |= gpio_bit(gpio); + + local_irq_restore(flags); + + port_setup(gpio, GPIO_USAGE); + + return 0; +} +EXPORT_SYMBOL(gpio_request); + + +void gpio_free(unsigned short gpio) +{ + unsigned long flags; + + if (check_gpio(gpio) < 0) + return; + + local_irq_save(flags); + + if (unlikely(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { + printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio); + dump_stack(); + local_irq_restore(flags); + return; + } + + reserved_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); + + local_irq_restore(flags); +} +EXPORT_SYMBOL(gpio_free); + + +void gpio_direction_input(unsigned short gpio) +{ + unsigned long flags; + + BUG_ON(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio))); + + local_irq_save(flags); + gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio); + gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio); + local_irq_restore(flags); +} +EXPORT_SYMBOL(gpio_direction_input); + +void gpio_direction_output(unsigned short gpio) +{ + unsigned long flags; + + BUG_ON(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio))); + + local_irq_save(flags); + gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio); + gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio); + local_irq_restore(flags); +} +EXPORT_SYMBOL(gpio_direction_output); diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S new file mode 100644 index 0000000..0e1a254 --- /dev/null +++ b/arch/blackfin/mach-bf548/head.S @@ -0,0 +1,507 @@ +/* + * File: arch/blackfin/mach-bf548/head.S + * Based on: arch/blackfin/mach-bf537/head.S + * Author: Jeff Dionne COPYRIGHT 1998 D. Jeff Dionne + * + * Created: 1998 + * Description: Startup code for Blackfin BF548 + * + * Modified: + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#if CONFIG_BFIN_KERNEL_CLOCK +#include +#endif + +.global __rambase +.global __ramstart +.global __ramend +.extern ___bss_stop +.extern ___bss_start +.extern _bf53x_relocate_l1_mem + +#define INITIAL_STACK 0xFFB01000 + +.text + +ENTRY(__start) +ENTRY(__stext) + /* R0: argument of command line string, passed from uboot, save it */ + R7 = R0; + /* Set the SYSCFG register */ + R0 = 0x36; + SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/ + R0 = 0; + + /* Clear Out All the data and pointer Registers*/ + R1 = R0; + R2 = R0; + R3 = R0; + R4 = R0; + R5 = R0; + R6 = R0; + + P0 = R0; + P1 = R0; + P2 = R0; + P3 = R0; + P4 = R0; + P5 = R0; + + LC0 = r0; + LC1 = r0; + L0 = r0; + L1 = r0; + L2 = r0; + L3 = r0; + + /* Clear Out All the DAG Registers*/ + B0 = r0; + B1 = r0; + B2 = r0; + B3 = r0; + + I0 = r0; + I1 = r0; + I2 = r0; + I3 = r0; + + M0 = r0; + M1 = r0; + M2 = r0; + M3 = r0; + + /* Turn off the icache */ + p0.l = (IMEM_CONTROL & 0xFFFF); + p0.h = (IMEM_CONTROL >> 16); + R1 = [p0]; + R0 = ~ENICPLB; + R0 = R0 & R1; + [p0] = R0; + SSYNC; + + /* Turn off the dcache */ + p0.l = (DMEM_CONTROL & 0xFFFF); + p0.h = (DMEM_CONTROL >> 16); + R1 = [p0]; + R0 = ~ENDCPLB; + R0 = R0 & R1; + [p0] = R0; + SSYNC; + + /* Initialize stack pointer */ + SP.L = LO(INITIAL_STACK); + SP.H = HI(INITIAL_STACK); + FP = SP; + USP = SP; + + /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */ + call _bf53x_relocate_l1_mem; +#if CONFIG_BFIN_KERNEL_CLOCK + call _start_dma_code; +#endif + /* Code for initializing Async memory banks */ + + p2.h = hi(EBIU_AMBCTL1); + p2.l = lo(EBIU_AMBCTL1); + r0.h = hi(AMBCTL1VAL); + r0.l = lo(AMBCTL1VAL); + [p2] = r0; + ssync; + + p2.h = hi(EBIU_AMBCTL0); + p2.l = lo(EBIU_AMBCTL0); + r0.h = hi(AMBCTL0VAL); + r0.l = lo(AMBCTL0VAL); + [p2] = r0; + ssync; + + p2.h = hi(EBIU_AMGCTL); + p2.l = lo(EBIU_AMGCTL); + r0 = AMGCTLVAL; + w[p2] = r0; + ssync; + + /* This section keeps the processor in supervisor mode + * during kernel boot. Switches to user mode at end of boot. + * See page 3-9 of Hardware Reference manual for documentation. + */ + + /* EVT15 = _real_start */ + + p0.l = lo(EVT15); + p0.h = hi(EVT15); + p1.l = _real_start; + p1.h = _real_start; + [p0] = p1; + csync; + + p0.l = lo(IMASK); + p0.h = hi(IMASK); + p1.l = IMASK_IVG15; + p1.h = 0x0; + [p0] = p1; + csync; + + raise 15; + p0.l = .LWAIT_HERE; + p0.h = .LWAIT_HERE; + reti = p0; +#if defined (ANOMALY_05000281) + nop; + nop; + nop; +#endif + rti; + +.LWAIT_HERE: + jump .LWAIT_HERE; + +ENTRY(_real_start) + [ -- sp ] = reti; + p0.l = lo(WDOG_CTL); + p0.h = hi(WDOG_CTL); + r0 = 0xAD6(z); + w[p0] = r0; /* watchdog off for now */ + ssync; + + /* Code update for BSS size == 0 + * Zero out the bss region. + */ + + p1.l = ___bss_start; + p1.h = ___bss_start; + p2.l = ___bss_stop; + p2.h = ___bss_stop; + r0 = 0; + p2 -= p1; + lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2; +.L_clear_bss: + B[p1++] = r0; + + /* In case there is a NULL pointer reference + * Zero out region before stext + */ + + p1.l = 0x0; + p1.h = 0x0; + r0.l = __stext; + r0.h = __stext; + r0 = r0 >> 1; + p2 = r0; + r0 = 0; + lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2; +.L_clear_zero: + W[p1++] = r0; + + /* pass the uboot arguments to the global value command line */ + R0 = R7; + call _cmdline_init; + + p1.l = __rambase; + p1.h = __rambase; + r0.l = __sdata; + r0.h = __sdata; + [p1] = r0; + + p1.l = __ramstart; + p1.h = __ramstart; + p3.l = ___bss_stop; + p3.h = ___bss_stop; + + r1 = p3; + [p1] = r1; + + + /* + * load the current thread pointer and stack + */ + r1.l = _init_thread_union; + r1.h = _init_thread_union; + + r2.l = 0x2000; + r2.h = 0x0000; + r1 = r1 + r2; + sp = r1; + usp = sp; + fp = sp; + call _start_kernel; +.L_exit: + jump.s .L_exit; + +.section .l1.text +#if CONFIG_BFIN_KERNEL_CLOCK +ENTRY(_start_dma_code) + + /* Enable PHY CLK buffer output */ + p0.h = hi(VR_CTL); + p0.l = lo(VR_CTL); + r0.l = w[p0]; + bitset(r0, 14); + w[p0] = r0.l; + ssync; + + p0.h = hi(SIC_IWR); + p0.l = lo(SIC_IWR); + r0.l = 0x1; + r0.h = 0x0; + [p0] = r0; + SSYNC; + + /* + * Set PLL_CTL + * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors + * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK + * - [7] = output delay (add 200ps of delay to mem signals) + * - [6] = input delay (add 200ps of input delay to mem signals) + * - [5] = PDWN : 1=All Clocks off + * - [3] = STOPCK : 1=Core Clock off + * - [1] = PLL_OFF : 1=Disable Power to PLL + * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL + * all other bits set to zero + */ + + p0.h = hi(PLL_LOCKCNT); + p0.l = lo(PLL_LOCKCNT); + r0 = 0x300(Z); + w[p0] = r0.l; + ssync; + + P2.H = hi(EBIU_SDGCTL); + P2.L = lo(EBIU_SDGCTL); + R0 = [P2]; + BITSET (R0, 24); + [P2] = R0; + SSYNC; + + r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ + r0 = r0 << 9; /* Shift it over, */ + r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ + r0 = r1 | r0; + r1 = PLL_BYPASS; /* Bypass the PLL? */ + r1 = r1 << 8; /* Shift it over */ + r0 = r1 | r0; /* add them all together */ + + p0.h = hi(PLL_CTL); + p0.l = lo(PLL_CTL); /* Load the address */ + cli r2; /* Disable interrupts */ + ssync; + w[p0] = r0.l; /* Set the value */ + idle; /* Wait for the PLL to stablize */ + sti r2; /* Enable interrupts */ + +.Lcheck_again: + p0.h = hi(PLL_STAT); + p0.l = lo(PLL_STAT); + R0 = W[P0](Z); + CC = BITTST(R0,5); + if ! CC jump .Lcheck_again; + + /* Configure SCLK & CCLK Dividers */ + r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); + p0.h = hi(PLL_DIV); + p0.l = lo(PLL_DIV); + w[p0] = r0.l; + ssync; + + p0.l = lo(EBIU_SDRRC); + p0.h = hi(EBIU_SDRRC); + r0 = mem_SDRRC; + w[p0] = r0.l; + ssync; + + p0.l = (EBIU_SDBCTL & 0xFFFF); + p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */ + r0 = mem_SDBCTL; + w[p0] = r0.l; + ssync; + + P2.H = hi(EBIU_SDGCTL); + P2.L = lo(EBIU_SDGCTL); + R0 = [P2]; + BITCLR (R0, 24); + p0.h = hi(EBIU_SDSTAT); + p0.l = lo(EBIU_SDSTAT); + r2.l = w[p0]; + cc = bittst(r2,3); + if !cc jump .Lskip; + NOP; + BITSET (R0, 23); +.Lskip: + [P2] = R0; + SSYNC; + + R0.L = lo(mem_SDGCTL); + R0.H = hi(mem_SDGCTL); + R1 = [p2]; + R1 = R1 | R0; + [P2] = R1; + SSYNC; + + p0.h = hi(SIC_IWR); + p0.l = lo(SIC_IWR); + r0.l = lo(IWR_ENABLE_ALL); + r0.h = hi(IWR_ENABLE_ALL); + [p0] = r0; + SSYNC; + + RTS; +#endif /* CONFIG_BFIN_KERNEL_CLOCK */ + +ENTRY(_bfin_reset) + /* No more interrupts to be handled*/ + CLI R6; + SSYNC; + +#if defined(CONFIG_MTD_M25P80) +/* + * The following code fix the SPI flash reboot issue, + * /CS signal of the chip which is using PF10 return to GPIO mode + */ + p0.h = hi(PORTF_FER); + p0.l = lo(PORTF_FER); + r0.l = 0x0000; + w[p0] = r0.l; + SSYNC; + +/* /CS return to high */ + p0.h = hi(PORTFIO); + p0.l = lo(PORTFIO); + r0.l = 0xFFFF; + w[p0] = r0.l; + SSYNC; + +/* Delay some time, This is necessary */ + r1.h = 0; + r1.l = 0x400; + p1 = r1; + lsetup (_delay_lab1,_delay_lab1_end ) lc1 = p1; +_delay_lab1: + r0.h = 0; + r0.l = 0x8000; + p0 = r0; + lsetup (_delay_lab0,_delay_lab0_end ) lc0 = p0; +_delay_lab0: + nop; +_delay_lab0_end: + nop; +_delay_lab1_end: + nop; +#endif + + /* Clear the bits 13-15 in SWRST if they werent cleared */ + p0.h = hi(SWRST); + p0.l = lo(SWRST); + csync; + r0.l = w[p0]; + + /* Clear the IMASK register */ + p0.h = hi(IMASK); + p0.l = lo(IMASK); + r0 = 0x0; + [p0] = r0; + + /* Clear the ILAT register */ + p0.h = hi(ILAT); + p0.l = lo(ILAT); + r0 = [p0]; + [p0] = r0; + SSYNC; + + /* Disable the WDOG TIMER */ + p0.h = hi(WDOG_CTL); + p0.l = lo(WDOG_CTL); + r0.l = 0xAD6; + w[p0] = r0.l; + SSYNC; + + /* Clear the sticky bit incase it is already set */ + p0.h = hi(WDOG_CTL); + p0.l = lo(WDOG_CTL); + r0.l = 0x8AD6; + w[p0] = r0.l; + SSYNC; + + /* Program the count value */ + R0.l = 0x100; + R0.h = 0x0; + P0.h = hi(WDOG_CNT); + P0.l = lo(WDOG_CNT); + [P0] = R0; + SSYNC; + + /* Program WDOG_STAT if necessary */ + P0.h = hi(WDOG_CTL); + P0.l = lo(WDOG_CTL); + R0 = W[P0](Z); + CC = BITTST(R0,1); + if !CC JUMP .LWRITESTAT; + CC = BITTST(R0,2); + if !CC JUMP .LWRITESTAT; + JUMP .LSKIP_WRITE; + +.LWRITESTAT: + /* When watch dog timer is enabled, + * a write to STAT will load the contents of CNT to STAT + */ + R0 = 0x0000(z); + P0.h = hi(WDOG_STAT); + P0.l = lo(WDOG_STAT) + [P0] = R0; + SSYNC; + +.LSKIP_WRITE: + /* Enable the reset event */ + P0.h = hi(WDOG_CTL); + P0.l = lo(WDOG_CTL); + R0 = W[P0](Z); + BITCLR(R0,1); + BITCLR(R0,2); + W[P0] = R0.L; + SSYNC; + NOP; + + /* Enable the wdog counter */ + R0 = W[P0](Z); + BITCLR(R0,4); + W[P0] = R0.L; + SSYNC; + + IDLE; + + RTS; + +.data + +/* + * Set up the usable of RAM stuff. Size of RAM is determined then + * an initial stack set up at the end. + */ + +.align 4 +__rambase: +.long 0 +__ramstart: +.long 0 +__ramend: +.long 0 diff --git a/arch/blackfin/mach-bf548/ints-priority.c b/arch/blackfin/mach-bf548/ints-priority.c new file mode 100644 index 0000000..dde450f --- /dev/null +++ b/arch/blackfin/mach-bf548/ints-priority.c @@ -0,0 +1,137 @@ +/* + * File: arch/blackfin/mach-bf537/ints-priority.c + * Based on: arch/blackfin/mach-bf533/ints-priority.c + * Author: Michael Hennerich + * + * Created: + * Description: Set up the interupt priorities + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include + +void program_IAR(void) +{ + /* Program the IAR0 Register with the configured priority */ + bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | + ((CONFIG_IRQ_DMAC0_ERR - 7) << IRQ_DMAC0_ERR_POS) | + ((CONFIG_IRQ_EPPI0_ERR - 7) << IRQ_EPPI0_ERR_POS) | + ((CONFIG_IRQ_SPORT0_ERR - 7) << IRQ_SPORT0_ERR_POS) | + ((CONFIG_IRQ_SPORT1_ERR - 7) << IRQ_SPORT1_ERR_POS) | + ((CONFIG_IRQ_SPI0_ERR - 7) << IRQ_SPI0_ERR_POS) | + ((CONFIG_IRQ_UART0_ERR - 7) << IRQ_UART0_ERR_POS) | + ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS)); + + bfin_write_SIC_IAR1(((CONFIG_IRQ_EPPI0 - 7) << IRQ_EPPI0_POS) | + ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) | + ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) | + ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) | + ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) | + ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) | + ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) | + ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS)); + + bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) | + ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) | + ((CONFIG_IRQ_PINT0 - 7) << IRQ_PINT0_POS) | + ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) | + ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) | + ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) | + ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCHDOG_POS)); + + bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) | + ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) | + ((CONFIG_IRQ_SPORT3_ERR - 7) << IRQ_SPORT3_ERR_POS) | + ((CONFIG_IRQ_MXVR_DATA - 7) << IRQ_MXVR_DATA_POS) | + ((CONFIG_IRQ_SPI1_ERR - 7) << IRQ_SPI1_ERR_POS) | + ((CONFIG_IRQ_SPI2_ERR - 7) << IRQ_SPI2_ERR_POS) | + ((CONFIG_IRQ_UART1_ERR - 7) << IRQ_UART1_ERR_POS) | + ((CONFIG_IRQ_UART2_ERR - 7) << IRQ_UART2_ERR_POS)); + + bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN0_ERR - 7) << IRQ_CAN0_ERR_POS) | + ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) | + ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) | + ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) | + ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) | + ((CONFIG_IRQ_EPPI1 - 7) << IRQ_EPPI1_POS) | + ((CONFIG_IRQ_EPPI2 - 7) << IRQ_EPPI2_POS) | + ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS)); + + bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) | + ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) | + ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) | + ((CONFIG_IRQ_ATAPI_RX - 7) << IRQ_ATAPI_RX_POS) | + ((CONFIG_IRQ_ATAPI_TX - 7) << IRQ_ATAPI_TX_POS) | + ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) | + ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) | + ((CONFIG_IRQ_CAN0_RX - 7) << IRQ_CAN0_RX_POS)); + + bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN0_TX - 7) << IRQ_CAN0_TX_POS) | + ((CONFIG_IRQ_MDMAS2 - 7) << IRQ_MDMAS2_POS) | + ((CONFIG_IRQ_MDMAS3 - 7) << IRQ_MDMAS3_POS) | + ((CONFIG_IRQ_MXVR_ERR - 7) << IRQ_MXVR_ERR_POS) | + ((CONFIG_IRQ_MXVR_MSG - 7) << IRQ_MXVR_MSG_POS) | + ((CONFIG_IRQ_MXVR_PKT - 7) << IRQ_MXVR_PKT_POS) | + ((CONFIG_IRQ_EPPI1_ERR - 7) << IRQ_EPPI1_ERR_POS) | + ((CONFIG_IRQ_EPPI2_ERR - 7) << IRQ_EPPI2_ERR_POS)); + + bfin_write_SIC_IAR7(((CONFIG_IRQ_UART3_ERR - 7) << IRQ_UART3_ERR_POS) | + ((CONFIG_IRQ_HOST_ERR - 7) << IRQ_HOST_ERR_POS) | + ((CONFIG_IRQ_PIXC_ERR - 7) << IRQ_PIXC_ERR_POS) | + ((CONFIG_IRQ_NFC_ERR - 7) << IRQ_NFC_ERR_POS) | + ((CONFIG_IRQ_ATAPI_ERR - 7) << IRQ_ATAPI_ERR_POS) | + ((CONFIG_IRQ_CAN1_ERR - 7) << IRQ_CAN1_ERR_POS) | + ((CONFIG_IRQ_HS_DMA_ERR - 7) << IRQ_HS_DMA_ERR_POS)); + + bfin_write_SIC_IAR8(((CONFIG_IRQ_PIXC_IN0 - 7) << IRQ_PIXC_IN1_POS) | + ((CONFIG_IRQ_PIXC_IN1 - 7) << IRQ_PIXC_IN1_POS) | + ((CONFIG_IRQ_PIXC_OUT - 7) << IRQ_PIXC_OUT_POS) | + ((CONFIG_IRQ_SDH - 7) << IRQ_SDH_POS) | + ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) | + ((CONFIG_IRQ_KEY - 7) << IRQ_KEY_POS) | + ((CONFIG_IRQ_CAN1_RX - 7) << IRQ_CAN1_RX_POS) | + ((CONFIG_IRQ_CAN1_TX - 7) << IRQ_CAN1_TX_POS)); + + bfin_write_SIC_IAR9(((CONFIG_IRQ_SDH_MASK0 - 7) << IRQ_SDH_MASK0_POS) | + ((CONFIG_IRQ_SDH_MASK1 - 7) << IRQ_SDH_MASK1_POS) | + ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) | + ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) | + ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) | + ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS) | + ((CONFIG_IRQ_OTPSEC - 7) << IRQ_OTPSEC_POS)); + + bfin_write_SIC_IAR10(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | + ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS)); + + bfin_write_SIC_IAR11(((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) | + ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | + ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) | + ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | + ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | + ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) | + ((CONFIG_IRQ_PINT2 - 7) << IRQ_PINT2_POS) | + ((CONFIG_IRQ_PINT3 - 7) << IRQ_PINT3_POS)); + + SSYNC(); +} diff --git a/arch/blackfin/mach-bf561/Makefile b/arch/blackfin/mach-bf561/Makefile index 57f475a..f39235a 100644 --- a/arch/blackfin/mach-bf561/Makefile +++ b/arch/blackfin/mach-bf561/Makefile @@ -4,6 +4,6 @@ extra-y := head.o -obj-y := ints-priority.o +obj-y := ints-priority.o dma.o obj-$(CONFIG_BF561_COREB) += coreb.o diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c new file mode 100644 index 0000000..89c65bb --- /dev/null +++ b/arch/blackfin/mach-bf561/dma.c @@ -0,0 +1,131 @@ +/* + * File: arch/blackfin/mach-bf561/dma.c + * Based on: + * Author: + * + * Created: + * Description: This file contains the simple DMA Implementation for Blackfin + * + * Modified: + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include + +struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { + (struct dma_register *) DMA1_0_NEXT_DESC_PTR, + (struct dma_register *) DMA1_1_NEXT_DESC_PTR, + (struct dma_register *) DMA1_2_NEXT_DESC_PTR, + (struct dma_register *) DMA1_3_NEXT_DESC_PTR, + (struct dma_register *) DMA1_4_NEXT_DESC_PTR, + (struct dma_register *) DMA1_5_NEXT_DESC_PTR, + (struct dma_register *) DMA1_6_NEXT_DESC_PTR, + (struct dma_register *) DMA1_7_NEXT_DESC_PTR, + (struct dma_register *) DMA1_8_NEXT_DESC_PTR, + (struct dma_register *) DMA1_9_NEXT_DESC_PTR, + (struct dma_register *) DMA1_10_NEXT_DESC_PTR, + (struct dma_register *) DMA1_11_NEXT_DESC_PTR, + (struct dma_register *) DMA2_0_NEXT_DESC_PTR, + (struct dma_register *) DMA2_1_NEXT_DESC_PTR, + (struct dma_register *) DMA2_2_NEXT_DESC_PTR, + (struct dma_register *) DMA2_3_NEXT_DESC_PTR, + (struct dma_register *) DMA2_4_NEXT_DESC_PTR, + (struct dma_register *) DMA2_5_NEXT_DESC_PTR, + (struct dma_register *) DMA2_6_NEXT_DESC_PTR, + (struct dma_register *) DMA2_7_NEXT_DESC_PTR, + (struct dma_register *) DMA2_8_NEXT_DESC_PTR, + (struct dma_register *) DMA2_9_NEXT_DESC_PTR, + (struct dma_register *) DMA2_10_NEXT_DESC_PTR, + (struct dma_register *) DMA2_11_NEXT_DESC_PTR, + (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR, + (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR, + (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR, + (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR, + (struct dma_register *) MDMA2_D0_NEXT_DESC_PTR, + (struct dma_register *) MDMA2_S0_NEXT_DESC_PTR, + (struct dma_register *) MDMA2_D1_NEXT_DESC_PTR, + (struct dma_register *) MDMA2_S1_NEXT_DESC_PTR, + (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR, + (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR, + (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR, + (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR, +}; + +int channel2irq(unsigned int channel) +{ + int ret_irq = -1; + + switch (channel) { + case CH_PPI0: + ret_irq = IRQ_PPI0; + break; + case CH_PPI1: + ret_irq = IRQ_PPI1; + break; + case CH_SPORT0_RX: + ret_irq = IRQ_SPORT0_RX; + break; + case CH_SPORT0_TX: + ret_irq = IRQ_SPORT0_TX; + break; + case CH_SPORT1_RX: + ret_irq = IRQ_SPORT1_RX; + break; + case CH_SPORT1_TX: + ret_irq = IRQ_SPORT1_TX; + break; + case CH_SPI: + ret_irq = IRQ_SPI; + break; + case CH_UART_RX: + ret_irq = IRQ_UART_RX; + break; + case CH_UART_TX: + ret_irq = IRQ_UART_TX; + break; + + case CH_MEM_STREAM0_SRC: + case CH_MEM_STREAM0_DEST: + ret_irq = IRQ_MEM_DMA0; + break; + case CH_MEM_STREAM1_SRC: + case CH_MEM_STREAM1_DEST: + ret_irq = IRQ_MEM_DMA1; + break; + case CH_MEM_STREAM2_SRC: + case CH_MEM_STREAM2_DEST: + ret_irq = IRQ_MEM_DMA2; + break; + case CH_MEM_STREAM3_SRC: + case CH_MEM_STREAM3_DEST: + ret_irq = IRQ_MEM_DMA3; + break; + + case CH_IMEM_STREAM0_SRC: + case CH_IMEM_STREAM0_DEST: + ret_irq = IRQ_IMEM_DMA0; + break; + case CH_IMEM_STREAM1_SRC: + case CH_IMEM_STREAM1_DEST: + ret_irq = IRQ_IMEM_DMA1; + break; + } + return ret_irq; +} diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile index d3a4907..0279ede 100644 --- a/arch/blackfin/mach-common/Makefile +++ b/arch/blackfin/mach-common/Makefile @@ -4,9 +4,9 @@ obj-y := \ cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \ - interrupt.o lock.o dpmc.o irqpanic.o + interrupt.o lock.o irqpanic.o obj-$(CONFIG_CPLB_INFO) += cplbinfo.o obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o -obj-$(CONFIG_PM) += pm.o +obj-$(CONFIG_PM) += pm.o dpmc.o diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c index 2cfc7d5..cec0f84 100644 --- a/arch/blackfin/mach-common/ints-priority-sc.c +++ b/arch/blackfin/mach-common/ints-priority-sc.c @@ -13,7 +13,7 @@ * 2002 Arcturus Networks Inc. MaTed * 2003 Metrowerks/Motorola * 2003 Bas Vermeulen - * Copyright 2004-2006 Analog Devices Inc. + * Copyright 2004-2007 Analog Devices Inc. * * Bugs: Enter bugs at http://blackfin.uclinux.org/ * @@ -65,9 +65,9 @@ atomic_t num_spurious; struct ivgx { /* irq number for request_irq, available in mach-bf533/irq.h */ - int irqno; + unsigned int irqno; /* corresponding bit in the SIC_ISR register */ - int isrflag; + unsigned int isrflag; } ivg_table[NR_PERI_INTS]; struct ivg_slice { @@ -98,7 +98,7 @@ static void __init search_IAR(void) bfin_read32((unsigned long *) SIC_IAR0 + (irqn >> 3)) >> iar_shift)) { ivg_table[irq_pos].irqno = IVG7 + irqn; - ivg_table[irq_pos].isrflag = 1 << irqn; + ivg_table[irq_pos].isrflag = 1 << (irqn % 32); ivg7_13[ivg].istop++; irq_pos++; } @@ -141,15 +141,31 @@ static void bfin_core_unmask_irq(unsigned int irq) static void bfin_internal_mask_irq(unsigned int irq) { +#ifndef CONFIG_BF54x bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & ~(1 << (irq - (IRQ_CORETMR + 1)))); +#else + unsigned mask_bank, mask_bit; + mask_bank = (irq - (IRQ_CORETMR +1))/32; + mask_bit = (irq - (IRQ_CORETMR + 1))%32; + bfin_write_SIC_IMASK( mask_bank, bfin_read_SIC_IMASK(mask_bank) & \ + ~(1 << mask_bit)); +#endif SSYNC(); } static void bfin_internal_unmask_irq(unsigned int irq) { +#ifndef CONFIG_BF54x bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | (1 << (irq - (IRQ_CORETMR + 1)))); +#else + unsigned mask_bank, mask_bit; + mask_bank = (irq - (IRQ_CORETMR +1))/32; + mask_bit = (irq - (IRQ_CORETMR + 1))%32; + bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | \ + ( 1 << mask_bit)); +#endif SSYNC(); } @@ -452,7 +468,14 @@ int __init init_arch_irq(void) int irq; unsigned long ilat = 0; /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ +#ifdef CONFIG_BF54x + bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); + bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); + bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); +#else bfin_write_SIC_IMASK(SIC_UNMASK_ALL); +#endif + SSYNC(); local_irq_disable(); @@ -555,9 +578,25 @@ void do_irq(int vec, struct pt_regs *fp) } else { struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; - unsigned long sic_status; +#ifdef CONFIG_BF54x + unsigned long sic_status[3]; SSYNC(); + sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0); + sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1); + sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2); + SSYNC(); + for(;; ivg++) { + if (ivg >= ivg_stop) { + atomic_inc(&num_spurious); + return; + } + if (sic_status[(ivg->irqno - IVG7)/32] & ivg->isrflag) + break; + } +#else + unsigned long sic_status; + SSYNC(); sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); for (;; ivg++) { @@ -567,6 +606,7 @@ void do_irq(int vec, struct pt_regs *fp) } else if (sic_status & ivg->isrflag) break; } +#endif vec = ivg->irqno; } asm_do_IRQ(vec, fp); diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h index d98d77a..bc0cca0 100644 --- a/include/asm-blackfin/gpio.h +++ b/include/asm-blackfin/gpio.h @@ -204,6 +204,10 @@ #endif +#ifdef BF548_FAMILY +#include +#endif + #ifdef BF561_FAMILY #define MAX_BLACKFIN_GPIOS 48 #define PORT_FIO0 GPIO_0 @@ -264,6 +268,7 @@ unsigned short get_gpiop_maska(unsigned short); unsigned short get_gpiop_maskb(unsigned short); unsigned short get_gpiop_data(unsigned short); +#ifndef BF548_FAMILY struct gpio_port_t { unsigned short data; unsigned short dummy1; @@ -299,6 +304,7 @@ struct gpio_port_t { unsigned short dummy16; unsigned short inen; }; +#endif #ifdef CONFIG_PM #define PM_WAKE_RISING 0x1 diff --git a/include/asm-blackfin/mach-bf533/dma.h b/include/asm-blackfin/mach-bf533/dma.h index bd9d5e9..16c672c 100644 --- a/include/asm-blackfin/mach-bf533/dma.h +++ b/include/asm-blackfin/mach-bf533/dma.h @@ -51,4 +51,7 @@ #define CH_MEM_STREAM1_DEST 10 /* TX */ #define CH_MEM_STREAM1_SRC 11 /* RX */ +extern int channel2irq(unsigned int channel); +extern struct dma_register *base_addr[]; + #endif diff --git a/include/asm-blackfin/mach-bf537/dma.h b/include/asm-blackfin/mach-bf537/dma.h index 7a96404..0219919 100644 --- a/include/asm-blackfin/mach-bf537/dma.h +++ b/include/asm-blackfin/mach-bf537/dma.h @@ -52,4 +52,7 @@ #define CH_MEM_STREAM1_DEST 14 /* TX */ #define CH_MEM_STREAM1_SRC 15 /* RX */ +extern int channel2irq(unsigned int channel); +extern struct dma_register *base_addr[]; + #endif diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index ddc150e..aca1d4b 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -47,6 +47,8 @@ SPORT external receive and transmit clocks. */ #define ANOMALY_05000272 /* Certain data cache write through modes fail for VDDint <=0.9V */ +#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is + not restored */ #define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h index 0b21102..163c79e 100644 --- a/include/asm-blackfin/mach-bf548/bf548.h +++ b/include/asm-blackfin/mach-bf548/bf548.h @@ -30,6 +30,8 @@ #ifndef __MACH_BF548_H__ #define __MACH_BF548_H__ +#define SUPPORTED_REVID 0 + /* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */ #define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */ diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h index 8f5d9c4..2f4afc9 100644 --- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h @@ -1,34 +1,35 @@ #include #include -#define NR_PORTS 2 +#define NR_PORTS 4 -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ #define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ +#define OFFSET_GCTL 0x08 /* Global Control Register */ #define OFFSET_LCR 0x0C /* Line Control Register */ #define OFFSET_MCR 0x10 /* Modem Control Register */ #define OFFSET_LSR 0x14 /* Line Status Register */ #define OFFSET_MSR 0x18 /* Modem Status Register */ #define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ +#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */ +#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */ +#define OFFSET_THR 0x28 /* Transmit Holding register */ +#define OFFSET_RBR 0x2C /* Receive Buffer register */ #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) -#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) -#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) +#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET)) #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) #define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) -#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) +#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v) +#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v) #define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) +#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v) #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) @@ -112,9 +113,29 @@ struct bfin_serial_res bfin_serial_resource[] = { CH_UART1_TX, CH_UART1_RX, #endif -#ifdef CONFIG_BFIN_UART1_CTSRTS - CONFIG_UART1_CTS_PIN, - CONFIG_UART1_RTS_PIN, + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART2 + { + 0xFFC02100, + IRQ_UART2_RX, +#ifdef CONFIG_SERIAL_BFIN_DMA + CH_UART2_TX, + CH_UART2_RX, +#endif +#ifdef CONFIG_BFIN_UART2_CTSRTS + CONFIG_UART2_CTS_PIN, + CONFIG_UART2_RTS_PIN, +#endif + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART3 + { + 0xFFC03100, + IRQ_UART3_RX, +#ifdef CONFIG_SERIAL_BFIN_DMA + CH_UART3_TX, + CH_UART3_RX, #endif }, #endif @@ -124,15 +145,40 @@ int nr_ports = ARRAY_SIZE(bfin_serial_resource); static void bfin_serial_hw_init(struct bfin_serial_port *uart) { - unsigned short val; - val = bfin_read16(BFIN_PORT_MUX); - val &= ~(PFDE | PFTE); - bfin_write16(BFIN_PORT_MUX, val); +#ifdef CONFIG_SERIAL_BFIN_UART0 + /* Enable UART0 RX and TX on pin 7 & 8 of PORT E */ + bfin_write_PORTE_FER(0x180 | bfin_read_PORTE_FER()); + bfin_write_PORTE_MUX(0x3C000 | bfin_read_PORTE_MUX()); +#endif + +#ifdef CONFIG_SERIAL_BFIN_UART1 + /* Enable UART1 RX and TX on pin 0 & 1 of PORT H */ + bfin_write_PORTH_FER(0x3 | bfin_read_PORTH_FER()); + bfin_write_PORTH_MUX(~0xF & bfin_read_PORTH_MUX()); +#ifdef CONFIG_BFIN_UART1_CTSRTS + /* Enable UART1 RTS and CTS on pin 9 & 10 of PORT E */ + bfin_write_PORTE_FER(0x600 | bfin_read_PORTE_FER()); + bfin_write_PORTE_MUX(~0x3C0000 & bfin_read_PORTE_MUX()); +#endif +#endif - val = bfin_read16(PORTF_FER); - val |= 0xF; - bfin_write16(PORTF_FER, val); +#ifdef CONFIG_SERIAL_BFIN_UART2 + /* Enable UART2 RX and TX on pin 4 & 5 of PORT B */ + bfin_write_PORTB_FER(0x30 | bfin_read_PORTB_FER()); + bfin_write_PORTB_MUX(~0xF00 & bfin_read_PORTB_MUX()); +#endif +#ifdef CONFIG_SERIAL_BFIN_UART3 + /* Enable UART3 RX and TX on pin 6 & 7 of PORT B */ + bfin_write_PORTB_FER(0xC0 | bfin_read_PORTB_FER()); + bfin_write_PORTB_MUX(~0xF000 | bfin_read_PORTB_MUX()); +#ifdef CONFIG_BFIN_UART3_CTSRTS + /* Enable UART3 RTS and CTS on pin 2 & 3 of PORT B */ + bfin_write_PORTB_FER(0xC | bfin_read_PORTB_FER()); + bfin_write_PORTB_MUX(~0xF0 | bfin_read_PORTB_MUX()); +#endif +#endif + SSYNC(); #ifdef CONFIG_SERIAL_BFIN_CTSRTS if (uart->cts_pin >= 0) { gpio_request(uart->cts_pin, NULL); diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h index 094c41a..791218f 100644 --- a/include/asm-blackfin/mach-bf548/blackfin.h +++ b/include/asm-blackfin/mach-bf548/blackfin.h @@ -34,24 +34,26 @@ #define BF548_FAMILY +#include "bf548.h" +#include "mem_map.h" +#include "anomaly.h" + #ifdef CONFIG_BF542 -#include "bf542.h" +#include "defBF542.h" +#endif #ifdef CONFIG_BF544 -#include "bf544.h" +#include "defBF544.h" #endif #ifdef CONFIG_BF548 -#include "bf548.h" +#include "defBF548.h" #endif #ifdef CONFIG_BF549 -#include "bf549.h" +#include "defBF549.h" #endif -#include "mem_map.h" -#include "anomaly.h" - #if !(defined(__ASSEMBLY__) || defined(ASSEMBLY)) #ifdef CONFIG_BF542 #include "cdefBF542.h" diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index 6bbcefe..b133800 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h @@ -31,7 +31,7 @@ #ifndef _CDEF_BF54X_H #define _CDEF_BF54X_H -#include +#include "defBF54x_base.h" /* ************************************************************** */ /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ @@ -70,12 +70,18 @@ #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) #define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) +#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2)) +#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val) + #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) #define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) +#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2)) +#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val) + #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) @@ -710,21 +716,21 @@ #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR) #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR) +#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY) +#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY) +#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR) +#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) #define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR) +#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) @@ -734,23 +740,23 @@ #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) #define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR) +#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY) +#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY) +#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR) +#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) #define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR) +#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) @@ -763,9 +769,9 @@ /* MDMA Stream 1 Registers */ #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) #define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR) +#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) @@ -777,9 +783,9 @@ #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY) #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR) +#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR) +#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) @@ -789,9 +795,9 @@ #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) #define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR) +#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) @@ -803,9 +809,9 @@ #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY) #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR) +#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR) +#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h index ac968fc..32d0713 100644 --- a/include/asm-blackfin/mach-bf548/defBF542.h +++ b/include/asm-blackfin/mach-bf548/defBF542.h @@ -362,7 +362,6 @@ /* Bit masks for KPAD_CTL */ #define KPAD_EN 0x1 /* Keypad Enable */ -#define nKPAD_EN 0x0 #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ #define KPAD_COLEN 0xe000 /* Column Enable Width */ @@ -384,29 +383,21 @@ /* Bit masks for KPAD_STAT */ #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ -#define nKPAD_IRQ 0x0 #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ #define KPAD_PRESSED 0x8 /* Key press current status */ -#define nKPAD_PRESSED 0x0 /* Bit masks for KPAD_SOFTEVAL */ #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ -#define nKPAD_SOFTEVAL_E 0x0 /* Bit masks for SDH_COMMAND */ #define CMD_IDX 0x3f /* Command Index */ #define CMD_RSP 0x40 /* Response */ -#define nCMD_RSP 0x0 #define CMD_L_RSP 0x80 /* Long Response */ -#define nCMD_L_RSP 0x0 #define CMD_INT_E 0x100 /* Command Interrupt */ -#define nCMD_INT_E 0x0 #define CMD_PEND_E 0x200 /* Command Pending */ -#define nCMD_PEND_E 0x0 #define CMD_E 0x400 /* Command Enable */ -#define nCMD_E 0x0 /* Bit masks for SDH_PWR_CTL */ @@ -415,21 +406,15 @@ #define TBD 0x3c /* TBD */ #endif #define SD_CMD_OD 0x40 /* Open Drain Output */ -#define nSD_CMD_OD 0x0 #define ROD_CTL 0x80 /* Rod Control */ -#define nROD_CTL 0x0 /* Bit masks for SDH_CLK_CTL */ #define CLKDIV 0xff /* MC_CLK Divisor */ #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ -#define nCLK_E 0x0 #define PWR_SV_E 0x200 /* Power Save Enable */ -#define nPWR_SV_E 0x0 #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ -#define nCLKDIV_BYPASS 0x0 #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ -#define nWIDE_BUS 0x0 /* Bit masks for SDH_RESP_CMD */ @@ -438,133 +423,74 @@ /* Bit masks for SDH_DATA_CTL */ #define DTX_E 0x1 /* Data Transfer Enable */ -#define nDTX_E 0x0 #define DTX_DIR 0x2 /* Data Transfer Direction */ -#define nDTX_DIR 0x0 #define DTX_MODE 0x4 /* Data Transfer Mode */ -#define nDTX_MODE 0x0 #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ -#define nDTX_DMA_E 0x0 #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ /* Bit masks for SDH_STATUS */ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ -#define nCMD_CRC_FAIL 0x0 #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define nDAT_CRC_FAIL 0x0 #define CMD_TIMEOUT 0x4 /* CMD Time Out */ -#define nCMD_TIMEOUT 0x0 #define DAT_TIMEOUT 0x8 /* Data Time Out */ -#define nDAT_TIMEOUT 0x0 #define TX_UNDERRUN 0x10 /* Transmit Underrun */ -#define nTX_UNDERRUN 0x0 #define RX_OVERRUN 0x20 /* Receive Overrun */ -#define nRX_OVERRUN 0x0 #define CMD_RESP_END 0x40 /* CMD Response End */ -#define nCMD_RESP_END 0x0 #define CMD_SENT 0x80 /* CMD Sent */ -#define nCMD_SENT 0x0 #define DAT_END 0x100 /* Data End */ -#define nDAT_END 0x0 #define START_BIT_ERR 0x200 /* Start Bit Error */ -#define nSTART_BIT_ERR 0x0 #define DAT_BLK_END 0x400 /* Data Block End */ -#define nDAT_BLK_END 0x0 #define CMD_ACT 0x800 /* CMD Active */ -#define nCMD_ACT 0x0 #define TX_ACT 0x1000 /* Transmit Active */ -#define nTX_ACT 0x0 #define RX_ACT 0x2000 /* Receive Active */ -#define nRX_ACT 0x0 #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ -#define nTX_FIFO_STAT 0x0 #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ -#define nRX_FIFO_STAT 0x0 #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ -#define nTX_FIFO_FULL 0x0 #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ -#define nRX_FIFO_FULL 0x0 #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ -#define nTX_FIFO_ZERO 0x0 #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ -#define nRX_DAT_ZERO 0x0 #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ -#define nTX_DAT_RDY 0x0 #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ -#define nRX_FIFO_RDY 0x0 /* Bit masks for SDH_STATUS_CLR */ #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ -#define nCMD_CRC_FAIL_STAT 0x0 #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ -#define nDAT_CRC_FAIL_STAT 0x0 #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ -#define nCMD_TIMEOUT_STAT 0x0 #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ -#define nDAT_TIMEOUT_STAT 0x0 #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ -#define nTX_UNDERRUN_STAT 0x0 #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ -#define nRX_OVERRUN_STAT 0x0 #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ -#define nCMD_RESP_END_STAT 0x0 #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ -#define nCMD_SENT_STAT 0x0 #define DAT_END_STAT 0x100 /* Data End Status */ -#define nDAT_END_STAT 0x0 #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ -#define nSTART_BIT_ERR_STAT 0x0 #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ -#define nDAT_BLK_END_STAT 0x0 /* Bit masks for SDH_MASK0 */ #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ -#define nCMD_CRC_FAIL_MASK 0x0 #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ -#define nDAT_CRC_FAIL_MASK 0x0 #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ -#define nCMD_TIMEOUT_MASK 0x0 #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ -#define nDAT_TIMEOUT_MASK 0x0 #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ -#define nTX_UNDERRUN_MASK 0x0 #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ -#define nRX_OVERRUN_MASK 0x0 #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ -#define nCMD_RESP_END_MASK 0x0 #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ -#define nCMD_SENT_MASK 0x0 #define DAT_END_MASK 0x100 /* Data End Mask */ -#define nDAT_END_MASK 0x0 #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ -#define nSTART_BIT_ERR_MASK 0x0 #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ -#define nDAT_BLK_END_MASK 0x0 #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ -#define nCMD_ACT_MASK 0x0 #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ -#define nTX_ACT_MASK 0x0 #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ -#define nRX_ACT_MASK 0x0 #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ -#define nTX_FIFO_STAT_MASK 0x0 #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ -#define nRX_FIFO_STAT_MASK 0x0 #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ -#define nTX_FIFO_FULL_MASK 0x0 #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ -#define nRX_FIFO_FULL_MASK 0x0 #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ -#define nTX_FIFO_ZERO_MASK 0x0 #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ -#define nRX_DAT_ZERO_MASK 0x0 #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ -#define nTX_DAT_RDY_MASK 0x0 #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ -#define nRX_FIFO_RDY_MASK 0x0 /* Bit masks for SDH_FIFO_CNT */ @@ -573,73 +499,47 @@ /* Bit masks for SDH_E_STATUS */ #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ -#define nSDIO_INT_DET 0x0 #define SD_CARD_DET 0x10 /* SD Card Detect */ -#define nSD_CARD_DET 0x0 /* Bit masks for SDH_E_MASK */ #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ -#define nSDIO_MSK 0x0 #define SCD_MSK 0x40 /* Mask Card Detect */ -#define nSCD_MSK 0x0 /* Bit masks for SDH_CFG */ #define CLKS_EN 0x1 /* Clocks Enable */ -#define nCLKS_EN 0x0 #define SD4E 0x4 /* SDIO 4-Bit Enable */ -#define nSD4E 0x0 #define MWE 0x8 /* Moving Window Enable */ -#define nMWE 0x0 #define SD_RST 0x10 /* SDMMC Reset */ -#define nSD_RST 0x0 #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ -#define nPUP_SDDAT 0x0 #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ -#define nPUP_SDDAT3 0x0 #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ -#define nPD_SDDAT3 0x0 /* Bit masks for SDH_RD_WAIT_EN */ #define RWR 0x1 /* Read Wait Request */ -#define nRWR 0x0 /* Bit masks for ATAPI_CONTROL */ #define PIO_START 0x1 /* Start PIO/Reg Op */ -#define nPIO_START 0x0 #define MULTI_START 0x2 /* Start Multi-DMA Op */ -#define nMULTI_START 0x0 #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ -#define nULTRA_START 0x0 #define XFER_DIR 0x8 /* Transfer Direction */ -#define nXFER_DIR 0x0 #define IORDY_EN 0x10 /* IORDY Enable */ -#define nIORDY_EN 0x0 #define FIFO_FLUSH 0x20 /* Flush FIFOs */ -#define nFIFO_FLUSH 0x0 #define SOFT_RST 0x40 /* Soft Reset */ -#define nSOFT_RST 0x0 #define DEV_RST 0x80 /* Device Reset */ -#define nDEV_RST 0x0 #define TFRCNT_RST 0x100 /* Trans Count Reset */ -#define nTFRCNT_RST 0x0 #define END_ON_TERM 0x200 /* End/Terminate Select */ -#define nEND_ON_TERM 0x0 #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ -#define nPIO_USE_DMA 0x0 #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ /* Bit masks for ATAPI_STATUS */ #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ -#define nPIO_XFER_ON 0x0 #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ -#define nMULTI_XFER_ON 0x0 #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ -#define nULTRA_XFER_ON 0x0 #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ /* Bit masks for ATAPI_DEV_ADDR */ @@ -649,66 +549,39 @@ /* Bit masks for ATAPI_INT_MASK */ #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ -#define nATAPI_DEV_INT_MASK 0x0 #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ -#define nPIO_DONE_MASK 0x0 #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ -#define nMULTI_DONE_MASK 0x0 #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ -#define nUDMAIN_DONE_MASK 0x0 #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ -#define nUDMAOUT_DONE_MASK 0x0 #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ -#define nHOST_TERM_XFER_MASK 0x0 #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ -#define nMULTI_TERM_MASK 0x0 #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ -#define nUDMAIN_TERM_MASK 0x0 #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ -#define nUDMAOUT_TERM_MASK 0x0 /* Bit masks for ATAPI_INT_STATUS */ #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ -#define nATAPI_DEV_INT 0x0 #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ -#define nPIO_DONE_INT 0x0 #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ -#define nMULTI_DONE_INT 0x0 #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ -#define nUDMAIN_DONE_INT 0x0 #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ -#define nUDMAOUT_DONE_INT 0x0 #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ -#define nHOST_TERM_XFER_INT 0x0 #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ -#define nMULTI_TERM_INT 0x0 #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ -#define nUDMAIN_TERM_INT 0x0 #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ -#define nUDMAOUT_TERM_INT 0x0 /* Bit masks for ATAPI_LINE_STATUS */ #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ -#define nATAPI_INTR 0x0 #define ATAPI_DASP 0x2 /* Device dasp to host line status */ -#define nATAPI_DASP 0x0 #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ -#define nATAPI_CS0N 0x0 #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ -#define nATAPI_CS1N 0x0 #define ATAPI_ADDR 0x70 /* ATAPI address line status */ #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ -#define nATAPI_DMAREQ 0x0 #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ -#define nATAPI_DMAACKN 0x0 #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ -#define nATAPI_DIOWN 0x0 #define ATAPI_DIORN 0x400 /* ATAPI read line status */ -#define nATAPI_DIORN 0x0 #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ -#define nATAPI_IORDY 0x0 /* Bit masks for ATAPI_SM_STATE */ @@ -720,7 +593,6 @@ /* Bit masks for ATAPI_TERMINATE */ #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ -#define nATAPI_HOST_TERM 0x0 /* Bit masks for ATAPI_REG_TIM_0 */ @@ -779,131 +651,77 @@ /* Bit masks for USB_POWER */ #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ -#define nENABLE_SUSPENDM 0x0 #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ -#define nSUSPEND_MODE 0x0 #define RESUME_MODE 0x4 /* DMA Mode */ -#define nRESUME_MODE 0x0 #define RESET 0x8 /* Reset indicator */ -#define nRESET 0x0 #define HS_MODE 0x10 /* High Speed mode indicator */ -#define nHS_MODE 0x0 #define HS_ENABLE 0x20 /* high Speed Enable */ -#define nHS_ENABLE 0x0 #define SOFT_CONN 0x40 /* Soft connect */ -#define nSOFT_CONN 0x0 #define ISO_UPDATE 0x80 /* Isochronous update */ -#define nISO_UPDATE 0x0 /* Bit masks for USB_INTRTX */ #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ -#define nEP0_TX 0x0 #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ -#define nEP1_TX 0x0 #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ -#define nEP2_TX 0x0 #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ -#define nEP3_TX 0x0 #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ -#define nEP4_TX 0x0 #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ -#define nEP5_TX 0x0 #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ -#define nEP6_TX 0x0 #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ -#define nEP7_TX 0x0 /* Bit masks for USB_INTRRX */ #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ -#define nEP1_RX 0x0 #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ -#define nEP2_RX 0x0 #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ -#define nEP3_RX 0x0 #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ -#define nEP4_RX 0x0 #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ -#define nEP5_RX 0x0 #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ -#define nEP6_RX 0x0 #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ -#define nEP7_RX 0x0 /* Bit masks for USB_INTRTXE */ #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ -#define nEP0_TX_E 0x0 #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ -#define nEP1_TX_E 0x0 #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ -#define nEP2_TX_E 0x0 #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ -#define nEP3_TX_E 0x0 #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ -#define nEP4_TX_E 0x0 #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ -#define nEP5_TX_E 0x0 #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ -#define nEP6_TX_E 0x0 #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ -#define nEP7_TX_E 0x0 /* Bit masks for USB_INTRRXE */ #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ -#define nEP1_RX_E 0x0 #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ -#define nEP2_RX_E 0x0 #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ -#define nEP3_RX_E 0x0 #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ -#define nEP4_RX_E 0x0 #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ -#define nEP5_RX_E 0x0 #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ -#define nEP6_RX_E 0x0 #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ -#define nEP7_RX_E 0x0 /* Bit masks for USB_INTRUSB */ #define SUSPEND_B 0x1 /* Suspend indicator */ -#define nSUSPEND_B 0x0 #define RESUME_B 0x2 /* Resume indicator */ -#define nRESUME_B 0x0 #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ -#define nRESET_OR_BABLE_B 0x0 #define SOF_B 0x8 /* Start of frame */ -#define nSOF_B 0x0 #define CONN_B 0x10 /* Connection indicator */ -#define nCONN_B 0x0 #define DISCON_B 0x20 /* Disconnect indicator */ -#define nDISCON_B 0x0 #define SESSION_REQ_B 0x40 /* Session Request */ -#define nSESSION_REQ_B 0x0 #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ -#define nVBUS_ERROR_B 0x0 /* Bit masks for USB_INTRUSBE */ #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ -#define nSUSPEND_BE 0x0 #define RESUME_BE 0x2 /* Resume indicator int enable */ -#define nRESUME_BE 0x0 #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ -#define nRESET_OR_BABLE_BE 0x0 #define SOF_BE 0x8 /* Start of frame int enable */ -#define nSOF_BE 0x0 #define CONN_BE 0x10 /* Connection indicator int enable */ -#define nCONN_BE 0x0 #define DISCON_BE 0x20 /* Disconnect indicator int enable */ -#define nDISCON_BE 0x0 #define SESSION_REQ_BE 0x40 /* Session Request int enable */ -#define nSESSION_REQ_BE 0x0 #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ -#define nVBUS_ERROR_BE 0x0 /* Bit masks for USB_FRAME */ @@ -916,117 +734,67 @@ /* Bit masks for USB_GLOBAL_CTL */ #define GLOBAL_ENA 0x1 /* enables USB module */ -#define nGLOBAL_ENA 0x0 #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ -#define nEP1_TX_ENA 0x0 #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ -#define nEP2_TX_ENA 0x0 #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ -#define nEP3_TX_ENA 0x0 #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ -#define nEP4_TX_ENA 0x0 #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ -#define nEP5_TX_ENA 0x0 #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ -#define nEP6_TX_ENA 0x0 #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ -#define nEP7_TX_ENA 0x0 #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ -#define nEP1_RX_ENA 0x0 #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ -#define nEP2_RX_ENA 0x0 #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ -#define nEP3_RX_ENA 0x0 #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ -#define nEP4_RX_ENA 0x0 #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ -#define nEP5_RX_ENA 0x0 #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ -#define nEP6_RX_ENA 0x0 #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ -#define nEP7_RX_ENA 0x0 /* Bit masks for USB_OTG_DEV_CTL */ #define SESSION 0x1 /* session indicator */ -#define nSESSION 0x0 #define HOST_REQ 0x2 /* Host negotiation request */ -#define nHOST_REQ 0x0 #define HOST_MODE 0x4 /* indicates USBDRC is a host */ -#define nHOST_MODE 0x0 #define VBUS0 0x8 /* Vbus level indicator[0] */ -#define nVBUS0 0x0 #define VBUS1 0x10 /* Vbus level indicator[1] */ -#define nVBUS1 0x0 #define LSDEV 0x20 /* Low-speed indicator */ -#define nLSDEV 0x0 #define FSDEV 0x40 /* Full or High-speed indicator */ -#define nFSDEV 0x0 #define B_DEVICE 0x80 /* A' or 'B' device indicator */ -#define nB_DEVICE 0x0 /* Bit masks for USB_OTG_VBUS_IRQ */ #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ -#define nDRIVE_VBUS_ON 0x0 #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ -#define nDRIVE_VBUS_OFF 0x0 #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ -#define nCHRG_VBUS_START 0x0 #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ -#define nCHRG_VBUS_END 0x0 #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ -#define nDISCHRG_VBUS_START 0x0 #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ -#define nDISCHRG_VBUS_END 0x0 /* Bit masks for USB_OTG_VBUS_MASK */ #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ -#define nDRIVE_VBUS_ON_ENA 0x0 #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ -#define nDRIVE_VBUS_OFF_ENA 0x0 #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ -#define nCHRG_VBUS_START_ENA 0x0 #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ -#define nCHRG_VBUS_END_ENA 0x0 #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ -#define nDISCHRG_VBUS_START_ENA 0x0 #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ -#define nDISCHRG_VBUS_END_ENA 0x0 /* Bit masks for USB_CSR0 */ #define RXPKTRDY 0x1 /* data packet receive indicator */ -#define nRXPKTRDY 0x0 #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ -#define nTXPKTRDY 0x0 #define STALL_SENT 0x4 /* STALL handshake sent */ -#define nSTALL_SENT 0x0 #define DATAEND 0x8 /* Data end indicator */ -#define nDATAEND 0x0 #define SETUPEND 0x10 /* Setup end */ -#define nSETUPEND 0x0 #define SENDSTALL 0x20 /* Send STALL handshake */ -#define nSENDSTALL 0x0 #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ -#define nSERVICED_RXPKTRDY 0x0 #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ -#define nSERVICED_SETUPEND 0x0 #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ -#define nFLUSHFIFO 0x0 #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ -#define nSTALL_RECEIVED_H 0x0 #define SETUPPKT_H 0x8 /* send Setup token host mode */ -#define nSETUPPKT_H 0x0 #define ERROR_H 0x10 /* timeout error indicator host mode */ -#define nERROR_H 0x0 #define REQPKT_H 0x20 /* Request an IN transaction host mode */ -#define nREQPKT_H 0x0 #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ -#define nSTATUSPKT_H 0x0 #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ -#define nNAK_TIMEOUT_H 0x0 /* Bit masks for USB_COUNT0 */ @@ -1047,37 +815,21 @@ /* Bit masks for USB_TXCSR */ #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ -#define nTXPKTRDY_T 0x0 #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ -#define nFIFO_NOT_EMPTY_T 0x0 #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ -#define nUNDERRUN_T 0x0 #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ -#define nFLUSHFIFO_T 0x0 #define STALL_SEND_T 0x10 /* issue a Stall handshake */ -#define nSTALL_SEND_T 0x0 #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ -#define nSTALL_SENT_T 0x0 #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_T 0x0 #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ -#define nINCOMPTX_T 0x0 #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_T 0x0 #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ -#define nFORCE_DATATOGGLE_T 0x0 #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_T 0x0 #define ISO_T 0x4000 /* enable Isochronous transfers */ -#define nISO_T 0x0 #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOSET_T 0x0 #define ERROR_TH 0x4 /* error condition host mode */ -#define nERROR_TH 0x0 #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_TH 0x0 #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ -#define nNAK_TIMEOUT_TH 0x0 /* Bit masks for USB_TXCOUNT */ @@ -1086,45 +838,25 @@ /* Bit masks for USB_RXCSR */ #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ -#define nRXPKTRDY_R 0x0 #define FIFO_FULL_R 0x2 /* FIFO not empty */ -#define nFIFO_FULL_R 0x0 #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ -#define nOVERRUN_R 0x0 #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ -#define nDATAERROR_R 0x0 #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ -#define nFLUSHFIFO_R 0x0 #define STALL_SEND_R 0x20 /* issue a Stall handshake */ -#define nSTALL_SEND_R 0x0 #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ -#define nSTALL_SENT_R 0x0 #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_R 0x0 #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ -#define nINCOMPRX_R 0x0 #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_R 0x0 #define DISNYET_R 0x1000 /* disable Nyet handshakes */ -#define nDISNYET_R 0x0 #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_R 0x0 #define ISO_R 0x4000 /* enable Isochronous transfers */ -#define nISO_R 0x0 #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOCLEAR_R 0x0 #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ -#define nERROR_RH 0x0 #define REQPKT_RH 0x20 /* request an IN transaction host mode */ -#define nREQPKT_RH 0x0 #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_RH 0x0 #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ -#define nINCOMPRX_RH 0x0 #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ -#define nDMAREQMODE_RH 0x0 #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ -#define nAUTOREQ_RH 0x0 /* Bit masks for USB_RXCOUNT */ @@ -1151,35 +883,22 @@ /* Bit masks for USB_DMA_INTERRUPT */ #define DMA0_INT 0x1 /* DMA0 pending interrupt */ -#define nDMA0_INT 0x0 #define DMA1_INT 0x2 /* DMA1 pending interrupt */ -#define nDMA1_INT 0x0 #define DMA2_INT 0x4 /* DMA2 pending interrupt */ -#define nDMA2_INT 0x0 #define DMA3_INT 0x8 /* DMA3 pending interrupt */ -#define nDMA3_INT 0x0 #define DMA4_INT 0x10 /* DMA4 pending interrupt */ -#define nDMA4_INT 0x0 #define DMA5_INT 0x20 /* DMA5 pending interrupt */ -#define nDMA5_INT 0x0 #define DMA6_INT 0x40 /* DMA6 pending interrupt */ -#define nDMA6_INT 0x0 #define DMA7_INT 0x80 /* DMA7 pending interrupt */ -#define nDMA7_INT 0x0 /* Bit masks for USB_DMAxCONTROL */ #define DMA_ENA 0x1 /* DMA enable */ -#define nDMA_ENA 0x0 #define DIRECTION 0x2 /* direction of DMA transfer */ -#define nDIRECTION 0x0 #define MODE 0x4 /* DMA Bus error */ -#define nMODE 0x0 #define INT_ENA 0x8 /* Interrupt enable */ -#define nINT_ENA 0x0 #define EPNUM 0xf0 /* EP number */ #define BUSERROR 0x100 /* DMA Bus error */ -#define nBUSERROR 0x0 /* Bit masks for USB_DMAxADDRHIGH */ diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h index 8fc77ea..dd955dc 100644 --- a/include/asm-blackfin/mach-bf548/defBF544.h +++ b/include/asm-blackfin/mach-bf548/defBF544.h @@ -538,21 +538,13 @@ /* Bit masks for PIXC_CTL */ #define PIXC_EN 0x1 /* Pixel Compositor Enable */ -#define nPIXC_EN 0x0 #define OVR_A_EN 0x2 /* Overlay A Enable */ -#define nOVR_A_EN 0x0 #define OVR_B_EN 0x4 /* Overlay B Enable */ -#define nOVR_B_EN 0x0 #define IMG_FORM 0x8 /* Image Data Format */ -#define nIMG_FORM 0x0 #define OVR_FORM 0x10 /* Overlay Data Format */ -#define nOVR_FORM 0x0 #define OUT_FORM 0x20 /* Output Data Format */ -#define nOUT_FORM 0x0 #define UDS_MOD 0x40 /* Resampling Mode */ -#define nUDS_MOD 0x0 #define TC_EN 0x80 /* Transparent Color Enable */ -#define nTC_EN 0x0 #define IMG_STAT 0x300 /* Image FIFO Status */ #define OVR_STAT 0xc00 /* Overlay FIFO Status */ #define WM_LVL 0x3000 /* FIFO Watermark Level */ @@ -600,13 +592,9 @@ /* Bit masks for PIXC_INTRSTAT */ #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ -#define nOVR_INT_EN 0x0 #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ -#define nFRM_INT_EN 0x0 #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ -#define nOVR_INT_STAT 0x0 #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ -#define nFRM_INT_STAT 0x0 /* Bit masks for PIXC_RYCON */ @@ -614,7 +602,6 @@ #define A12 0xffc00 /* A12 in the Coefficient Matrix */ #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nRY_MULT4 0x0 /* Bit masks for PIXC_GUCON */ @@ -622,7 +609,6 @@ #define A22 0xffc00 /* A22 in the Coefficient Matrix */ #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nGU_MULT4 0x0 /* Bit masks for PIXC_BVCON */ @@ -630,7 +616,6 @@ #define A32 0xffc00 /* A32 in the Coefficient Matrix */ #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nBV_MULT4 0x0 /* Bit masks for PIXC_CCBIAS */ @@ -647,48 +632,28 @@ /* Bit masks for HOST_CONTROL */ #define HOST_EN 0x1 /* Host Enable */ -#define nHOST_EN 0x0 #define HOST_END 0x2 /* Host Endianess */ -#define nHOST_END 0x0 #define DATA_SIZE 0x4 /* Data Size */ -#define nDATA_SIZE 0x0 #define HOST_RST 0x8 /* Host Reset */ -#define nHOST_RST 0x0 #define HRDY_OVR 0x20 /* Host Ready Override */ -#define nHRDY_OVR 0x0 #define INT_MODE 0x40 /* Interrupt Mode */ -#define nINT_MODE 0x0 #define BT_EN 0x80 /* Bus Timeout Enable */ -#define nBT_EN 0x0 #define EHW 0x100 /* Enable Host Write */ -#define nEHW 0x0 #define EHR 0x200 /* Enable Host Read */ -#define nEHR 0x0 #define BDR 0x400 /* Burst DMA Requests */ -#define nBDR 0x0 /* Bit masks for HOST_STATUS */ #define READY 0x1 /* DMA Ready */ -#define nREADY 0x0 #define FIFOFULL 0x2 /* FIFO Full */ -#define nFIFOFULL 0x0 #define FIFOEMPTY 0x4 /* FIFO Empty */ -#define nFIFOEMPTY 0x0 #define COMPLETE 0x8 /* DMA Complete */ -#define nCOMPLETE 0x0 #define HSHK 0x10 /* Host Handshake */ -#define nHSHK 0x0 #define TIMEOUT 0x20 /* Host Timeout */ -#define nTIMEOUT 0x0 #define HIRQ 0x40 /* Host Interrupt Request */ -#define nHIRQ 0x0 #define ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define nALLOW_CNFG 0x0 #define DMA_DIR 0x100 /* DMA Direction */ -#define nDMA_DIR 0x0 #define BTE 0x200 /* Bus Timeout Enabled */ -#define nBTE 0x0 /* Bit masks for HOST_TIMEOUT */ @@ -697,67 +662,42 @@ /* Bit masks for TIMER_ENABLE1 */ #define TIMEN8 0x1 /* Timer 8 Enable */ -#define nTIMEN8 0x0 #define TIMEN9 0x2 /* Timer 9 Enable */ -#define nTIMEN9 0x0 #define TIMEN10 0x4 /* Timer 10 Enable */ -#define nTIMEN10 0x0 /* Bit masks for TIMER_DISABLE1 */ #define TIMDIS8 0x1 /* Timer 8 Disable */ -#define nTIMDIS8 0x0 #define TIMDIS9 0x2 /* Timer 9 Disable */ -#define nTIMDIS9 0x0 #define TIMDIS10 0x4 /* Timer 10 Disable */ -#define nTIMDIS10 0x0 /* Bit masks for TIMER_STATUS1 */ #define TIMIL8 0x1 /* Timer 8 Interrupt */ -#define nTIMIL8 0x0 #define TIMIL9 0x2 /* Timer 9 Interrupt */ -#define nTIMIL9 0x0 #define TIMIL10 0x4 /* Timer 10 Interrupt */ -#define nTIMIL10 0x0 #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ -#define nTOVF_ERR8 0x0 #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ -#define nTOVF_ERR9 0x0 #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ -#define nTOVF_ERR10 0x0 #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ -#define nTRUN8 0x0 #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ -#define nTRUN9 0x0 #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ -#define nTRUN10 0x0 /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ /* Bit masks for HMDMAx_CONTROL */ #define HMDMAEN 0x1 /* Handshake MDMA Enable */ -#define nHMDMAEN 0x0 #define REP 0x2 /* Handshake MDMA Request Polarity */ -#define nREP 0x0 #define UTE 0x8 /* Urgency Threshold Enable */ -#define nUTE 0x0 #define OIE 0x10 /* Overflow Interrupt Enable */ -#define nOIE 0x0 #define BDIE 0x20 /* Block Done Interrupt Enable */ -#define nBDIE 0x0 #define MBDI 0x40 /* Mask Block Done Interrupt */ -#define nMBDI 0x0 #define DRQ 0x300 /* Handshake MDMA Request Type */ #define RBC 0x1000 /* Force Reload of BCOUNT */ -#define nRBC 0x0 #define PS 0x2000 /* Pin Status */ -#define nPS 0x0 #define OI 0x4000 /* Overflow Interrupt Generated */ -#define nOI 0x0 #define BDI 0x8000 /* Block Done Interrupt Generated */ -#define nBDI 0x0 /* ******************************************* */ /* MULTI BIT MACRO ENUMERATIONS */ diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h index d9e3062..8d4214e 100644 --- a/include/asm-blackfin/mach-bf548/defBF548.h +++ b/include/asm-blackfin/mach-bf548/defBF548.h @@ -899,21 +899,13 @@ /* Bit masks for PIXC_CTL */ #define PIXC_EN 0x1 /* Pixel Compositor Enable */ -#define nPIXC_EN 0x0 #define OVR_A_EN 0x2 /* Overlay A Enable */ -#define nOVR_A_EN 0x0 #define OVR_B_EN 0x4 /* Overlay B Enable */ -#define nOVR_B_EN 0x0 #define IMG_FORM 0x8 /* Image Data Format */ -#define nIMG_FORM 0x0 #define OVR_FORM 0x10 /* Overlay Data Format */ -#define nOVR_FORM 0x0 #define OUT_FORM 0x20 /* Output Data Format */ -#define nOUT_FORM 0x0 #define UDS_MOD 0x40 /* Resampling Mode */ -#define nUDS_MOD 0x0 #define TC_EN 0x80 /* Transparent Color Enable */ -#define nTC_EN 0x0 #define IMG_STAT 0x300 /* Image FIFO Status */ #define OVR_STAT 0xc00 /* Overlay FIFO Status */ #define WM_LVL 0x3000 /* FIFO Watermark Level */ @@ -961,13 +953,9 @@ /* Bit masks for PIXC_INTRSTAT */ #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ -#define nOVR_INT_EN 0x0 #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ -#define nFRM_INT_EN 0x0 #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ -#define nOVR_INT_STAT 0x0 #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ -#define nFRM_INT_STAT 0x0 /* Bit masks for PIXC_RYCON */ @@ -975,7 +963,6 @@ #define A12 0xffc00 /* A12 in the Coefficient Matrix */ #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nRY_MULT4 0x0 /* Bit masks for PIXC_GUCON */ @@ -983,7 +970,6 @@ #define A22 0xffc00 /* A22 in the Coefficient Matrix */ #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nGU_MULT4 0x0 /* Bit masks for PIXC_BVCON */ @@ -991,7 +977,6 @@ #define A32 0xffc00 /* A32 in the Coefficient Matrix */ #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nBV_MULT4 0x0 /* Bit masks for PIXC_CCBIAS */ @@ -1008,48 +993,28 @@ /* Bit masks for HOST_CONTROL */ #define HOST_EN 0x1 /* Host Enable */ -#define nHOST_EN 0x0 #define HOST_END 0x2 /* Host Endianess */ -#define nHOST_END 0x0 #define DATA_SIZE 0x4 /* Data Size */ -#define nDATA_SIZE 0x0 #define HOST_RST 0x8 /* Host Reset */ -#define nHOST_RST 0x0 #define HRDY_OVR 0x20 /* Host Ready Override */ -#define nHRDY_OVR 0x0 #define INT_MODE 0x40 /* Interrupt Mode */ -#define nINT_MODE 0x0 #define BT_EN 0x80 /* Bus Timeout Enable */ -#define nBT_EN 0x0 #define EHW 0x100 /* Enable Host Write */ -#define nEHW 0x0 #define EHR 0x200 /* Enable Host Read */ -#define nEHR 0x0 #define BDR 0x400 /* Burst DMA Requests */ -#define nBDR 0x0 /* Bit masks for HOST_STATUS */ #define READY 0x1 /* DMA Ready */ -#define nREADY 0x0 #define FIFOFULL 0x2 /* FIFO Full */ -#define nFIFOFULL 0x0 #define FIFOEMPTY 0x4 /* FIFO Empty */ -#define nFIFOEMPTY 0x0 #define COMPLETE 0x8 /* DMA Complete */ -#define nCOMPLETE 0x0 #define HSHK 0x10 /* Host Handshake */ -#define nHSHK 0x0 #define TIMEOUT 0x20 /* Host Timeout */ -#define nTIMEOUT 0x0 #define HIRQ 0x40 /* Host Interrupt Request */ -#define nHIRQ 0x0 #define ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define nALLOW_CNFG 0x0 #define DMA_DIR 0x100 /* DMA Direction */ -#define nDMA_DIR 0x0 #define BTE 0x200 /* Bus Timeout Enabled */ -#define nBTE 0x0 /* Bit masks for HOST_TIMEOUT */ @@ -1058,7 +1023,6 @@ /* Bit masks for KPAD_CTL */ #define KPAD_EN 0x1 /* Keypad Enable */ -#define nKPAD_EN 0x0 #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ #define KPAD_COLEN 0xe000 /* Column Enable Width */ @@ -1080,29 +1044,21 @@ /* Bit masks for KPAD_STAT */ #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ -#define nKPAD_IRQ 0x0 #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ #define KPAD_PRESSED 0x8 /* Key press current status */ -#define nKPAD_PRESSED 0x0 /* Bit masks for KPAD_SOFTEVAL */ #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ -#define nKPAD_SOFTEVAL_E 0x0 /* Bit masks for SDH_COMMAND */ #define CMD_IDX 0x3f /* Command Index */ #define CMD_RSP 0x40 /* Response */ -#define nCMD_RSP 0x0 #define CMD_L_RSP 0x80 /* Long Response */ -#define nCMD_L_RSP 0x0 #define CMD_INT_E 0x100 /* Command Interrupt */ -#define nCMD_INT_E 0x0 #define CMD_PEND_E 0x200 /* Command Pending */ -#define nCMD_PEND_E 0x0 #define CMD_E 0x400 /* Command Enable */ -#define nCMD_E 0x0 /* Bit masks for SDH_PWR_CTL */ @@ -1111,21 +1067,15 @@ #define TBD 0x3c /* TBD */ #endif #define SD_CMD_OD 0x40 /* Open Drain Output */ -#define nSD_CMD_OD 0x0 #define ROD_CTL 0x80 /* Rod Control */ -#define nROD_CTL 0x0 /* Bit masks for SDH_CLK_CTL */ #define CLKDIV 0xff /* MC_CLK Divisor */ #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ -#define nCLK_E 0x0 #define PWR_SV_E 0x200 /* Power Save Enable */ -#define nPWR_SV_E 0x0 #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ -#define nCLKDIV_BYPASS 0x0 #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ -#define nWIDE_BUS 0x0 /* Bit masks for SDH_RESP_CMD */ @@ -1134,133 +1084,74 @@ /* Bit masks for SDH_DATA_CTL */ #define DTX_E 0x1 /* Data Transfer Enable */ -#define nDTX_E 0x0 #define DTX_DIR 0x2 /* Data Transfer Direction */ -#define nDTX_DIR 0x0 #define DTX_MODE 0x4 /* Data Transfer Mode */ -#define nDTX_MODE 0x0 #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ -#define nDTX_DMA_E 0x0 #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ /* Bit masks for SDH_STATUS */ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ -#define nCMD_CRC_FAIL 0x0 #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define nDAT_CRC_FAIL 0x0 #define CMD_TIMEOUT 0x4 /* CMD Time Out */ -#define nCMD_TIMEOUT 0x0 #define DAT_TIMEOUT 0x8 /* Data Time Out */ -#define nDAT_TIMEOUT 0x0 #define TX_UNDERRUN 0x10 /* Transmit Underrun */ -#define nTX_UNDERRUN 0x0 #define RX_OVERRUN 0x20 /* Receive Overrun */ -#define nRX_OVERRUN 0x0 #define CMD_RESP_END 0x40 /* CMD Response End */ -#define nCMD_RESP_END 0x0 #define CMD_SENT 0x80 /* CMD Sent */ -#define nCMD_SENT 0x0 #define DAT_END 0x100 /* Data End */ -#define nDAT_END 0x0 #define START_BIT_ERR 0x200 /* Start Bit Error */ -#define nSTART_BIT_ERR 0x0 #define DAT_BLK_END 0x400 /* Data Block End */ -#define nDAT_BLK_END 0x0 #define CMD_ACT 0x800 /* CMD Active */ -#define nCMD_ACT 0x0 #define TX_ACT 0x1000 /* Transmit Active */ -#define nTX_ACT 0x0 #define RX_ACT 0x2000 /* Receive Active */ -#define nRX_ACT 0x0 #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ -#define nTX_FIFO_STAT 0x0 #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ -#define nRX_FIFO_STAT 0x0 #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ -#define nTX_FIFO_FULL 0x0 #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ -#define nRX_FIFO_FULL 0x0 #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ -#define nTX_FIFO_ZERO 0x0 #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ -#define nRX_DAT_ZERO 0x0 #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ -#define nTX_DAT_RDY 0x0 #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ -#define nRX_FIFO_RDY 0x0 /* Bit masks for SDH_STATUS_CLR */ #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ -#define nCMD_CRC_FAIL_STAT 0x0 #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ -#define nDAT_CRC_FAIL_STAT 0x0 #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ -#define nCMD_TIMEOUT_STAT 0x0 #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ -#define nDAT_TIMEOUT_STAT 0x0 #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ -#define nTX_UNDERRUN_STAT 0x0 #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ -#define nRX_OVERRUN_STAT 0x0 #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ -#define nCMD_RESP_END_STAT 0x0 #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ -#define nCMD_SENT_STAT 0x0 #define DAT_END_STAT 0x100 /* Data End Status */ -#define nDAT_END_STAT 0x0 #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ -#define nSTART_BIT_ERR_STAT 0x0 #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ -#define nDAT_BLK_END_STAT 0x0 /* Bit masks for SDH_MASK0 */ #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ -#define nCMD_CRC_FAIL_MASK 0x0 #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ -#define nDAT_CRC_FAIL_MASK 0x0 #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ -#define nCMD_TIMEOUT_MASK 0x0 #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ -#define nDAT_TIMEOUT_MASK 0x0 #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ -#define nTX_UNDERRUN_MASK 0x0 #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ -#define nRX_OVERRUN_MASK 0x0 #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ -#define nCMD_RESP_END_MASK 0x0 #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ -#define nCMD_SENT_MASK 0x0 #define DAT_END_MASK 0x100 /* Data End Mask */ -#define nDAT_END_MASK 0x0 #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ -#define nSTART_BIT_ERR_MASK 0x0 #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ -#define nDAT_BLK_END_MASK 0x0 #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ -#define nCMD_ACT_MASK 0x0 #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ -#define nTX_ACT_MASK 0x0 #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ -#define nRX_ACT_MASK 0x0 #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ -#define nTX_FIFO_STAT_MASK 0x0 #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ -#define nRX_FIFO_STAT_MASK 0x0 #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ -#define nTX_FIFO_FULL_MASK 0x0 #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ -#define nRX_FIFO_FULL_MASK 0x0 #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ -#define nTX_FIFO_ZERO_MASK 0x0 #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ -#define nRX_DAT_ZERO_MASK 0x0 #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ -#define nTX_DAT_RDY_MASK 0x0 #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ -#define nRX_FIFO_RDY_MASK 0x0 /* Bit masks for SDH_FIFO_CNT */ @@ -1269,73 +1160,47 @@ /* Bit masks for SDH_E_STATUS */ #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ -#define nSDIO_INT_DET 0x0 #define SD_CARD_DET 0x10 /* SD Card Detect */ -#define nSD_CARD_DET 0x0 /* Bit masks for SDH_E_MASK */ #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ -#define nSDIO_MSK 0x0 #define SCD_MSK 0x40 /* Mask Card Detect */ -#define nSCD_MSK 0x0 /* Bit masks for SDH_CFG */ #define CLKS_EN 0x1 /* Clocks Enable */ -#define nCLKS_EN 0x0 #define SD4E 0x4 /* SDIO 4-Bit Enable */ -#define nSD4E 0x0 #define MWE 0x8 /* Moving Window Enable */ -#define nMWE 0x0 #define SD_RST 0x10 /* SDMMC Reset */ -#define nSD_RST 0x0 #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ -#define nPUP_SDDAT 0x0 #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ -#define nPUP_SDDAT3 0x0 #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ -#define nPD_SDDAT3 0x0 /* Bit masks for SDH_RD_WAIT_EN */ #define RWR 0x1 /* Read Wait Request */ -#define nRWR 0x0 /* Bit masks for ATAPI_CONTROL */ #define PIO_START 0x1 /* Start PIO/Reg Op */ -#define nPIO_START 0x0 #define MULTI_START 0x2 /* Start Multi-DMA Op */ -#define nMULTI_START 0x0 #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ -#define nULTRA_START 0x0 #define XFER_DIR 0x8 /* Transfer Direction */ -#define nXFER_DIR 0x0 #define IORDY_EN 0x10 /* IORDY Enable */ -#define nIORDY_EN 0x0 #define FIFO_FLUSH 0x20 /* Flush FIFOs */ -#define nFIFO_FLUSH 0x0 #define SOFT_RST 0x40 /* Soft Reset */ -#define nSOFT_RST 0x0 #define DEV_RST 0x80 /* Device Reset */ -#define nDEV_RST 0x0 #define TFRCNT_RST 0x100 /* Trans Count Reset */ -#define nTFRCNT_RST 0x0 #define END_ON_TERM 0x200 /* End/Terminate Select */ -#define nEND_ON_TERM 0x0 #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ -#define nPIO_USE_DMA 0x0 #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ /* Bit masks for ATAPI_STATUS */ #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ -#define nPIO_XFER_ON 0x0 #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ -#define nMULTI_XFER_ON 0x0 #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ -#define nULTRA_XFER_ON 0x0 #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ /* Bit masks for ATAPI_DEV_ADDR */ @@ -1345,66 +1210,39 @@ /* Bit masks for ATAPI_INT_MASK */ #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ -#define nATAPI_DEV_INT_MASK 0x0 #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ -#define nPIO_DONE_MASK 0x0 #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ -#define nMULTI_DONE_MASK 0x0 #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ -#define nUDMAIN_DONE_MASK 0x0 #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ -#define nUDMAOUT_DONE_MASK 0x0 #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ -#define nHOST_TERM_XFER_MASK 0x0 #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ -#define nMULTI_TERM_MASK 0x0 #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ -#define nUDMAIN_TERM_MASK 0x0 #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ -#define nUDMAOUT_TERM_MASK 0x0 /* Bit masks for ATAPI_INT_STATUS */ #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ -#define nATAPI_DEV_INT 0x0 #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ -#define nPIO_DONE_INT 0x0 #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ -#define nMULTI_DONE_INT 0x0 #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ -#define nUDMAIN_DONE_INT 0x0 #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ -#define nUDMAOUT_DONE_INT 0x0 #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ -#define nHOST_TERM_XFER_INT 0x0 #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ -#define nMULTI_TERM_INT 0x0 #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ -#define nUDMAIN_TERM_INT 0x0 #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ -#define nUDMAOUT_TERM_INT 0x0 /* Bit masks for ATAPI_LINE_STATUS */ #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ -#define nATAPI_INTR 0x0 #define ATAPI_DASP 0x2 /* Device dasp to host line status */ -#define nATAPI_DASP 0x0 #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ -#define nATAPI_CS0N 0x0 #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ -#define nATAPI_CS1N 0x0 #define ATAPI_ADDR 0x70 /* ATAPI address line status */ #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ -#define nATAPI_DMAREQ 0x0 #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ -#define nATAPI_DMAACKN 0x0 #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ -#define nATAPI_DIOWN 0x0 #define ATAPI_DIORN 0x400 /* ATAPI read line status */ -#define nATAPI_DIORN 0x0 #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ -#define nATAPI_IORDY 0x0 /* Bit masks for ATAPI_SM_STATE */ @@ -1416,7 +1254,6 @@ /* Bit masks for ATAPI_TERMINATE */ #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ -#define nATAPI_HOST_TERM 0x0 /* Bit masks for ATAPI_REG_TIM_0 */ @@ -1471,41 +1308,26 @@ /* Bit masks for TIMER_ENABLE1 */ #define TIMEN8 0x1 /* Timer 8 Enable */ -#define nTIMEN8 0x0 #define TIMEN9 0x2 /* Timer 9 Enable */ -#define nTIMEN9 0x0 #define TIMEN10 0x4 /* Timer 10 Enable */ -#define nTIMEN10 0x0 /* Bit masks for TIMER_DISABLE1 */ #define TIMDIS8 0x1 /* Timer 8 Disable */ -#define nTIMDIS8 0x0 #define TIMDIS9 0x2 /* Timer 9 Disable */ -#define nTIMDIS9 0x0 #define TIMDIS10 0x4 /* Timer 10 Disable */ -#define nTIMDIS10 0x0 /* Bit masks for TIMER_STATUS1 */ #define TIMIL8 0x1 /* Timer 8 Interrupt */ -#define nTIMIL8 0x0 #define TIMIL9 0x2 /* Timer 9 Interrupt */ -#define nTIMIL9 0x0 #define TIMIL10 0x4 /* Timer 10 Interrupt */ -#define nTIMIL10 0x0 #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ -#define nTOVF_ERR8 0x0 #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ -#define nTOVF_ERR9 0x0 #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ -#define nTOVF_ERR10 0x0 #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ -#define nTRUN8 0x0 #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ -#define nTRUN9 0x0 #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ -#define nTRUN10 0x0 /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ @@ -1516,131 +1338,77 @@ /* Bit masks for USB_POWER */ #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ -#define nENABLE_SUSPENDM 0x0 #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ -#define nSUSPEND_MODE 0x0 #define RESUME_MODE 0x4 /* DMA Mode */ -#define nRESUME_MODE 0x0 #define RESET 0x8 /* Reset indicator */ -#define nRESET 0x0 #define HS_MODE 0x10 /* High Speed mode indicator */ -#define nHS_MODE 0x0 #define HS_ENABLE 0x20 /* high Speed Enable */ -#define nHS_ENABLE 0x0 #define SOFT_CONN 0x40 /* Soft connect */ -#define nSOFT_CONN 0x0 #define ISO_UPDATE 0x80 /* Isochronous update */ -#define nISO_UPDATE 0x0 /* Bit masks for USB_INTRTX */ #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ -#define nEP0_TX 0x0 #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ -#define nEP1_TX 0x0 #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ -#define nEP2_TX 0x0 #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ -#define nEP3_TX 0x0 #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ -#define nEP4_TX 0x0 #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ -#define nEP5_TX 0x0 #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ -#define nEP6_TX 0x0 #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ -#define nEP7_TX 0x0 /* Bit masks for USB_INTRRX */ #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ -#define nEP1_RX 0x0 #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ -#define nEP2_RX 0x0 #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ -#define nEP3_RX 0x0 #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ -#define nEP4_RX 0x0 #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ -#define nEP5_RX 0x0 #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ -#define nEP6_RX 0x0 #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ -#define nEP7_RX 0x0 /* Bit masks for USB_INTRTXE */ #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ -#define nEP0_TX_E 0x0 #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ -#define nEP1_TX_E 0x0 #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ -#define nEP2_TX_E 0x0 #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ -#define nEP3_TX_E 0x0 #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ -#define nEP4_TX_E 0x0 #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ -#define nEP5_TX_E 0x0 #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ -#define nEP6_TX_E 0x0 #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ -#define nEP7_TX_E 0x0 /* Bit masks for USB_INTRRXE */ #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ -#define nEP1_RX_E 0x0 #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ -#define nEP2_RX_E 0x0 #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ -#define nEP3_RX_E 0x0 #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ -#define nEP4_RX_E 0x0 #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ -#define nEP5_RX_E 0x0 #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ -#define nEP6_RX_E 0x0 #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ -#define nEP7_RX_E 0x0 /* Bit masks for USB_INTRUSB */ #define SUSPEND_B 0x1 /* Suspend indicator */ -#define nSUSPEND_B 0x0 #define RESUME_B 0x2 /* Resume indicator */ -#define nRESUME_B 0x0 #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ -#define nRESET_OR_BABLE_B 0x0 #define SOF_B 0x8 /* Start of frame */ -#define nSOF_B 0x0 #define CONN_B 0x10 /* Connection indicator */ -#define nCONN_B 0x0 #define DISCON_B 0x20 /* Disconnect indicator */ -#define nDISCON_B 0x0 #define SESSION_REQ_B 0x40 /* Session Request */ -#define nSESSION_REQ_B 0x0 #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ -#define nVBUS_ERROR_B 0x0 /* Bit masks for USB_INTRUSBE */ #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ -#define nSUSPEND_BE 0x0 #define RESUME_BE 0x2 /* Resume indicator int enable */ -#define nRESUME_BE 0x0 #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ -#define nRESET_OR_BABLE_BE 0x0 #define SOF_BE 0x8 /* Start of frame int enable */ -#define nSOF_BE 0x0 #define CONN_BE 0x10 /* Connection indicator int enable */ -#define nCONN_BE 0x0 #define DISCON_BE 0x20 /* Disconnect indicator int enable */ -#define nDISCON_BE 0x0 #define SESSION_REQ_BE 0x40 /* Session Request int enable */ -#define nSESSION_REQ_BE 0x0 #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ -#define nVBUS_ERROR_BE 0x0 /* Bit masks for USB_FRAME */ @@ -1653,117 +1421,67 @@ /* Bit masks for USB_GLOBAL_CTL */ #define GLOBAL_ENA 0x1 /* enables USB module */ -#define nGLOBAL_ENA 0x0 #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ -#define nEP1_TX_ENA 0x0 #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ -#define nEP2_TX_ENA 0x0 #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ -#define nEP3_TX_ENA 0x0 #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ -#define nEP4_TX_ENA 0x0 #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ -#define nEP5_TX_ENA 0x0 #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ -#define nEP6_TX_ENA 0x0 #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ -#define nEP7_TX_ENA 0x0 #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ -#define nEP1_RX_ENA 0x0 #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ -#define nEP2_RX_ENA 0x0 #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ -#define nEP3_RX_ENA 0x0 #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ -#define nEP4_RX_ENA 0x0 #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ -#define nEP5_RX_ENA 0x0 #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ -#define nEP6_RX_ENA 0x0 #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ -#define nEP7_RX_ENA 0x0 /* Bit masks for USB_OTG_DEV_CTL */ #define SESSION 0x1 /* session indicator */ -#define nSESSION 0x0 #define HOST_REQ 0x2 /* Host negotiation request */ -#define nHOST_REQ 0x0 #define HOST_MODE 0x4 /* indicates USBDRC is a host */ -#define nHOST_MODE 0x0 #define VBUS0 0x8 /* Vbus level indicator[0] */ -#define nVBUS0 0x0 #define VBUS1 0x10 /* Vbus level indicator[1] */ -#define nVBUS1 0x0 #define LSDEV 0x20 /* Low-speed indicator */ -#define nLSDEV 0x0 #define FSDEV 0x40 /* Full or High-speed indicator */ -#define nFSDEV 0x0 #define B_DEVICE 0x80 /* A' or 'B' device indicator */ -#define nB_DEVICE 0x0 /* Bit masks for USB_OTG_VBUS_IRQ */ #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ -#define nDRIVE_VBUS_ON 0x0 #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ -#define nDRIVE_VBUS_OFF 0x0 #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ -#define nCHRG_VBUS_START 0x0 #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ -#define nCHRG_VBUS_END 0x0 #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ -#define nDISCHRG_VBUS_START 0x0 #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ -#define nDISCHRG_VBUS_END 0x0 /* Bit masks for USB_OTG_VBUS_MASK */ #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ -#define nDRIVE_VBUS_ON_ENA 0x0 #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ -#define nDRIVE_VBUS_OFF_ENA 0x0 #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ -#define nCHRG_VBUS_START_ENA 0x0 #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ -#define nCHRG_VBUS_END_ENA 0x0 #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ -#define nDISCHRG_VBUS_START_ENA 0x0 #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ -#define nDISCHRG_VBUS_END_ENA 0x0 /* Bit masks for USB_CSR0 */ #define RXPKTRDY 0x1 /* data packet receive indicator */ -#define nRXPKTRDY 0x0 #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ -#define nTXPKTRDY 0x0 #define STALL_SENT 0x4 /* STALL handshake sent */ -#define nSTALL_SENT 0x0 #define DATAEND 0x8 /* Data end indicator */ -#define nDATAEND 0x0 #define SETUPEND 0x10 /* Setup end */ -#define nSETUPEND 0x0 #define SENDSTALL 0x20 /* Send STALL handshake */ -#define nSENDSTALL 0x0 #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ -#define nSERVICED_RXPKTRDY 0x0 #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ -#define nSERVICED_SETUPEND 0x0 #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ -#define nFLUSHFIFO 0x0 #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ -#define nSTALL_RECEIVED_H 0x0 #define SETUPPKT_H 0x8 /* send Setup token host mode */ -#define nSETUPPKT_H 0x0 #define ERROR_H 0x10 /* timeout error indicator host mode */ -#define nERROR_H 0x0 #define REQPKT_H 0x20 /* Request an IN transaction host mode */ -#define nREQPKT_H 0x0 #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ -#define nSTATUSPKT_H 0x0 #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ -#define nNAK_TIMEOUT_H 0x0 /* Bit masks for USB_COUNT0 */ @@ -1784,37 +1502,21 @@ /* Bit masks for USB_TXCSR */ #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ -#define nTXPKTRDY_T 0x0 #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ -#define nFIFO_NOT_EMPTY_T 0x0 #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ -#define nUNDERRUN_T 0x0 #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ -#define nFLUSHFIFO_T 0x0 #define STALL_SEND_T 0x10 /* issue a Stall handshake */ -#define nSTALL_SEND_T 0x0 #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ -#define nSTALL_SENT_T 0x0 #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_T 0x0 #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ -#define nINCOMPTX_T 0x0 #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_T 0x0 #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ -#define nFORCE_DATATOGGLE_T 0x0 #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_T 0x0 #define ISO_T 0x4000 /* enable Isochronous transfers */ -#define nISO_T 0x0 #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOSET_T 0x0 #define ERROR_TH 0x4 /* error condition host mode */ -#define nERROR_TH 0x0 #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_TH 0x0 #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ -#define nNAK_TIMEOUT_TH 0x0 /* Bit masks for USB_TXCOUNT */ @@ -1823,45 +1525,25 @@ /* Bit masks for USB_RXCSR */ #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ -#define nRXPKTRDY_R 0x0 #define FIFO_FULL_R 0x2 /* FIFO not empty */ -#define nFIFO_FULL_R 0x0 #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ -#define nOVERRUN_R 0x0 #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ -#define nDATAERROR_R 0x0 #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ -#define nFLUSHFIFO_R 0x0 #define STALL_SEND_R 0x20 /* issue a Stall handshake */ -#define nSTALL_SEND_R 0x0 #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ -#define nSTALL_SENT_R 0x0 #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_R 0x0 #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ -#define nINCOMPRX_R 0x0 #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_R 0x0 #define DISNYET_R 0x1000 /* disable Nyet handshakes */ -#define nDISNYET_R 0x0 #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_R 0x0 #define ISO_R 0x4000 /* enable Isochronous transfers */ -#define nISO_R 0x0 #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOCLEAR_R 0x0 #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ -#define nERROR_RH 0x0 #define REQPKT_RH 0x20 /* request an IN transaction host mode */ -#define nREQPKT_RH 0x0 #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_RH 0x0 #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ -#define nINCOMPRX_RH 0x0 #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ -#define nDMAREQMODE_RH 0x0 #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ -#define nAUTOREQ_RH 0x0 /* Bit masks for USB_RXCOUNT */ @@ -1888,35 +1570,22 @@ /* Bit masks for USB_DMA_INTERRUPT */ #define DMA0_INT 0x1 /* DMA0 pending interrupt */ -#define nDMA0_INT 0x0 #define DMA1_INT 0x2 /* DMA1 pending interrupt */ -#define nDMA1_INT 0x0 #define DMA2_INT 0x4 /* DMA2 pending interrupt */ -#define nDMA2_INT 0x0 #define DMA3_INT 0x8 /* DMA3 pending interrupt */ -#define nDMA3_INT 0x0 #define DMA4_INT 0x10 /* DMA4 pending interrupt */ -#define nDMA4_INT 0x0 #define DMA5_INT 0x20 /* DMA5 pending interrupt */ -#define nDMA5_INT 0x0 #define DMA6_INT 0x40 /* DMA6 pending interrupt */ -#define nDMA6_INT 0x0 #define DMA7_INT 0x80 /* DMA7 pending interrupt */ -#define nDMA7_INT 0x0 /* Bit masks for USB_DMAxCONTROL */ #define DMA_ENA 0x1 /* DMA enable */ -#define nDMA_ENA 0x0 #define DIRECTION 0x2 /* direction of DMA transfer */ -#define nDIRECTION 0x0 #define MODE 0x4 /* DMA Bus error */ -#define nMODE 0x0 #define INT_ENA 0x8 /* Interrupt enable */ -#define nINT_ENA 0x0 #define EPNUM 0xf0 /* EP number */ #define BUSERROR 0x100 /* DMA Bus error */ -#define nBUSERROR 0x0 /* Bit masks for USB_DMAxADDRHIGH */ @@ -1937,26 +1606,16 @@ /* Bit masks for HMDMAx_CONTROL */ #define HMDMAEN 0x1 /* Handshake MDMA Enable */ -#define nHMDMAEN 0x0 #define REP 0x2 /* Handshake MDMA Request Polarity */ -#define nREP 0x0 #define UTE 0x8 /* Urgency Threshold Enable */ -#define nUTE 0x0 #define OIE 0x10 /* Overflow Interrupt Enable */ -#define nOIE 0x0 #define BDIE 0x20 /* Block Done Interrupt Enable */ -#define nBDIE 0x0 #define MBDI 0x40 /* Mask Block Done Interrupt */ -#define nMBDI 0x0 #define DRQ 0x300 /* Handshake MDMA Request Type */ #define RBC 0x1000 /* Force Reload of BCOUNT */ -#define nRBC 0x0 #define PS 0x2000 /* Pin Status */ -#define nPS 0x0 #define OI 0x4000 /* Overflow Interrupt Generated */ -#define nOI 0x0 #define BDI 0x8000 /* Block Done Interrupt Generated */ -#define nBDI 0x0 /* ******************************************* */ /* MULTI BIT MACRO ENUMERATIONS */ diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h index b1cc1c0..c2f4734 100644 --- a/include/asm-blackfin/mach-bf548/defBF549.h +++ b/include/asm-blackfin/mach-bf548/defBF549.h @@ -1070,21 +1070,13 @@ /* Bit masks for PIXC_CTL */ #define PIXC_EN 0x1 /* Pixel Compositor Enable */ -#define nPIXC_EN 0x0 #define OVR_A_EN 0x2 /* Overlay A Enable */ -#define nOVR_A_EN 0x0 #define OVR_B_EN 0x4 /* Overlay B Enable */ -#define nOVR_B_EN 0x0 #define IMG_FORM 0x8 /* Image Data Format */ -#define nIMG_FORM 0x0 #define OVR_FORM 0x10 /* Overlay Data Format */ -#define nOVR_FORM 0x0 #define OUT_FORM 0x20 /* Output Data Format */ -#define nOUT_FORM 0x0 #define UDS_MOD 0x40 /* Resampling Mode */ -#define nUDS_MOD 0x0 #define TC_EN 0x80 /* Transparent Color Enable */ -#define nTC_EN 0x0 #define IMG_STAT 0x300 /* Image FIFO Status */ #define OVR_STAT 0xc00 /* Overlay FIFO Status */ #define WM_LVL 0x3000 /* FIFO Watermark Level */ @@ -1132,13 +1124,9 @@ /* Bit masks for PIXC_INTRSTAT */ #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ -#define nOVR_INT_EN 0x0 #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ -#define nFRM_INT_EN 0x0 #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ -#define nOVR_INT_STAT 0x0 #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ -#define nFRM_INT_STAT 0x0 /* Bit masks for PIXC_RYCON */ @@ -1146,7 +1134,6 @@ #define A12 0xffc00 /* A12 in the Coefficient Matrix */ #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nRY_MULT4 0x0 /* Bit masks for PIXC_GUCON */ @@ -1154,7 +1141,6 @@ #define A22 0xffc00 /* A22 in the Coefficient Matrix */ #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nGU_MULT4 0x0 /* Bit masks for PIXC_BVCON */ @@ -1162,7 +1148,6 @@ #define A32 0xffc00 /* A32 in the Coefficient Matrix */ #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nBV_MULT4 0x0 /* Bit masks for PIXC_CCBIAS */ @@ -1179,48 +1164,28 @@ /* Bit masks for HOST_CONTROL */ #define HOST_EN 0x1 /* Host Enable */ -#define nHOST_EN 0x0 #define HOST_END 0x2 /* Host Endianess */ -#define nHOST_END 0x0 #define DATA_SIZE 0x4 /* Data Size */ -#define nDATA_SIZE 0x0 #define HOST_RST 0x8 /* Host Reset */ -#define nHOST_RST 0x0 #define HRDY_OVR 0x20 /* Host Ready Override */ -#define nHRDY_OVR 0x0 #define INT_MODE 0x40 /* Interrupt Mode */ -#define nINT_MODE 0x0 #define BT_EN 0x80 /* Bus Timeout Enable */ -#define nBT_EN 0x0 #define EHW 0x100 /* Enable Host Write */ -#define nEHW 0x0 #define EHR 0x200 /* Enable Host Read */ -#define nEHR 0x0 #define BDR 0x400 /* Burst DMA Requests */ -#define nBDR 0x0 /* Bit masks for HOST_STATUS */ #define READY 0x1 /* DMA Ready */ -#define nREADY 0x0 #define FIFOFULL 0x2 /* FIFO Full */ -#define nFIFOFULL 0x0 #define FIFOEMPTY 0x4 /* FIFO Empty */ -#define nFIFOEMPTY 0x0 -#define COMPLETE 0x8 /* DMA Complete */ -#define nCOMPLETE 0x0 +#define DMA_COMPLETE 0x8 /* DMA Complete */ #define HSHK 0x10 /* Host Handshake */ -#define nHSHK 0x0 #define TIMEOUT 0x20 /* Host Timeout */ -#define nTIMEOUT 0x0 #define HIRQ 0x40 /* Host Interrupt Request */ -#define nHIRQ 0x0 #define ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define nALLOW_CNFG 0x0 #define DMA_DIR 0x100 /* DMA Direction */ -#define nDMA_DIR 0x0 #define BTE 0x200 /* Bus Timeout Enabled */ -#define nBTE 0x0 /* Bit masks for HOST_TIMEOUT */ @@ -1229,71 +1194,41 @@ /* Bit masks for MXVR_CONFIG */ #define MXVREN 0x1 /* MXVR Enable */ -#define nMXVREN 0x0 #define MMSM 0x2 /* MXVR Master/Slave Mode Select */ -#define nMMSM 0x0 #define ACTIVE 0x4 /* Active Mode */ -#define nACTIVE 0x0 #define SDELAY 0x8 /* Synchronous Data Delay */ -#define nSDELAY 0x0 #define NCMRXEN 0x10 /* Normal Control Message Receive Enable */ -#define nNCMRXEN 0x0 #define RWRRXEN 0x20 /* Remote Write Receive Enable */ -#define nRWRRXEN 0x0 #define MTXEN 0x40 /* MXVR Transmit Data Enable */ -#define nMTXEN 0x0 #define MTXONB 0x80 /* MXVR Phy Transmitter On */ -#define nMTXONB 0x0 #define EPARITY 0x100 /* Even Parity Select */ -#define nEPARITY 0x0 #define MSB 0x1e00 /* Master Synchronous Boundary */ #define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */ -#define nAPRXEN 0x0 #define WAKEUP 0x4000 /* Wake-Up */ -#define nWAKEUP 0x0 #define LMECH 0x8000 /* Lock Mechanism Select */ -#define nLMECH 0x0 /* Bit masks for MXVR_STATE_0 */ #define NACT 0x1 /* Network Activity */ -#define nNACT 0x0 #define SBLOCK 0x2 /* Super Block Lock */ -#define nSBLOCK 0x0 #define FMPLLST 0xc /* Frequency Multiply PLL SM State */ #define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */ #define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */ -#define nAPBSY 0x0 #define APARB 0x200 /* Asynchronous Packet Arbitrating */ -#define nAPARB 0x0 #define APTX 0x400 /* Asynchronous Packet Transmitting */ -#define nAPTX 0x0 #define APRX 0x800 /* Receiving Asynchronous Packet */ -#define nAPRX 0x0 #define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */ -#define nCMBSY 0x0 #define CMARB 0x2000 /* Control Message Arbitrating */ -#define nCMARB 0x0 #define CMTX 0x4000 /* Control Message Transmitting */ -#define nCMTX 0x0 #define CMRX 0x8000 /* Receiving Control Message */ -#define nCMRX 0x0 #define MRXONB 0x10000 /* MRXONB Pin State */ -#define nMRXONB 0x0 #define RGSIP 0x20000 /* Remote Get Source In Progress */ -#define nRGSIP 0x0 #define DALIP 0x40000 /* Resource Deallocate In Progress */ -#define nDALIP 0x0 #define ALIP 0x80000 /* Resource Allocate In Progress */ -#define nALIP 0x0 #define RRDIP 0x100000 /* Remote Read In Progress */ -#define nRRDIP 0x0 #define RWRIP 0x200000 /* Remote Write In Progress */ -#define nRWRIP 0x0 #define FLOCK 0x400000 /* Frame Lock */ -#define nFLOCK 0x0 #define BLOCK 0x800000 /* Block Lock */ -#define nBLOCK 0x0 #define RSB 0xf000000 /* Received Synchronous Boundary */ #define DERRNUM 0xf0000000 /* DMA Error Channel Number */ @@ -1302,535 +1237,343 @@ #define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */ #define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */ #define APCONT 0x100 /* Asynchronous Packet Continuation */ -#define nAPCONT 0x0 #define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */ #define DMAACTIVE0 0x10000 /* DMA0 Active */ -#define nDMAACTIVE0 0x0 #define DMAACTIVE1 0x20000 /* DMA1 Active */ -#define nDMAACTIVE1 0x0 #define DMAACTIVE2 0x40000 /* DMA2 Active */ -#define nDMAACTIVE2 0x0 #define DMAACTIVE3 0x80000 /* DMA3 Active */ -#define nDMAACTIVE3 0x0 #define DMAACTIVE4 0x100000 /* DMA4 Active */ -#define nDMAACTIVE4 0x0 #define DMAACTIVE5 0x200000 /* DMA5 Active */ -#define nDMAACTIVE5 0x0 #define DMAACTIVE6 0x400000 /* DMA6 Active */ -#define nDMAACTIVE6 0x0 #define DMAACTIVE7 0x800000 /* DMA7 Active */ -#define nDMAACTIVE7 0x0 #define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */ -#define nDMAPMEN0 0x0 #define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */ -#define nDMAPMEN1 0x0 #define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */ -#define nDMAPMEN2 0x0 #define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */ -#define nDMAPMEN3 0x0 #define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */ -#define nDMAPMEN4 0x0 #define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */ -#define nDMAPMEN5 0x0 #define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */ -#define nDMAPMEN6 0x0 #define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */ -#define nDMAPMEN7 0x0 /* Bit masks for MXVR_INT_STAT_0 */ #define NI2A 0x1 /* Network Inactive to Active */ -#define nNI2A 0x0 #define NA2I 0x2 /* Network Active to Inactive */ -#define nNA2I 0x0 #define SBU2L 0x4 /* Super Block Unlock to Lock */ -#define nSBU2L 0x0 #define SBL2U 0x8 /* Super Block Lock to Unlock */ -#define nSBL2U 0x0 #define PRU 0x10 /* Position Register Updated */ -#define nPRU 0x0 #define MPRU 0x20 /* Maximum Position Register Updated */ -#define nMPRU 0x0 #define DRU 0x40 /* Delay Register Updated */ -#define nDRU 0x0 #define MDRU 0x80 /* Maximum Delay Register Updated */ -#define nMDRU 0x0 #define SBU 0x100 /* Synchronous Boundary Updated */ -#define nSBU 0x0 #define ATU 0x200 /* Allocation Table Updated */ -#define nATU 0x0 #define FCZ0 0x400 /* Frame Counter 0 Zero */ -#define nFCZ0 0x0 #define FCZ1 0x800 /* Frame Counter 1 Zero */ -#define nFCZ1 0x0 #define PERR 0x1000 /* Parity Error */ -#define nPERR 0x0 #define MH2L 0x2000 /* MRXONB High to Low */ -#define nMH2L 0x0 #define ML2H 0x4000 /* MRXONB Low to High */ -#define nML2H 0x0 #define WUP 0x8000 /* Wake-Up Preamble Received */ -#define nWUP 0x0 #define FU2L 0x10000 /* Frame Unlock to Lock */ -#define nFU2L 0x0 #define FL2U 0x20000 /* Frame Lock to Unlock */ -#define nFL2U 0x0 #define BU2L 0x40000 /* Block Unlock to Lock */ -#define nBU2L 0x0 #define BL2U 0x80000 /* Block Lock to Unlock */ -#define nBL2U 0x0 #define OBERR 0x100000 /* DMA Out of Bounds Error */ -#define nOBERR 0x0 #define PFL 0x200000 /* PLL Frequency Locked */ -#define nPFL 0x0 #define SCZ 0x400000 /* System Clock Counter Zero */ -#define nSCZ 0x0 #define FERR 0x800000 /* FIFO Error */ -#define nFERR 0x0 #define CMR 0x1000000 /* Control Message Received */ -#define nCMR 0x0 #define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */ -#define nCMROF 0x0 #define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */ -#define nCMTS 0x0 #define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */ -#define nCMTC 0x0 #define RWRC 0x10000000 /* Remote Write Control Message Completed */ -#define nRWRC 0x0 #define BCZ 0x20000000 /* Block Counter Zero */ -#define nBCZ 0x0 #define BMERR 0x40000000 /* Biphase Mark Coding Error */ -#define nBMERR 0x0 #define DERR 0x80000000 /* DMA Error */ -#define nDERR 0x0 /* Bit masks for MXVR_INT_STAT_1 */ #define HDONE0 0x1 /* DMA0 Half Done */ -#define nHDONE0 0x0 #define DONE0 0x2 /* DMA0 Done */ -#define nDONE0 0x0 #define APR 0x4 /* Asynchronous Packet Received */ -#define nAPR 0x0 #define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */ -#define nAPROF 0x0 #define HDONE1 0x10 /* DMA1 Half Done */ -#define nHDONE1 0x0 #define DONE1 0x20 /* DMA1 Done */ -#define nDONE1 0x0 #define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */ -#define nAPTS 0x0 #define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */ -#define nAPTC 0x0 #define HDONE2 0x100 /* DMA2 Half Done */ -#define nHDONE2 0x0 #define DONE2 0x200 /* DMA2 Done */ -#define nDONE2 0x0 #define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */ -#define nAPRCE 0x0 #define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */ -#define nAPRPE 0x0 #define HDONE3 0x1000 /* DMA3 Half Done */ -#define nHDONE3 0x0 #define DONE3 0x2000 /* DMA3 Done */ -#define nDONE3 0x0 #define HDONE4 0x10000 /* DMA4 Half Done */ -#define nHDONE4 0x0 #define DONE4 0x20000 /* DMA4 Done */ -#define nDONE4 0x0 #define HDONE5 0x100000 /* DMA5 Half Done */ -#define nHDONE5 0x0 #define DONE5 0x200000 /* DMA5 Done */ -#define nDONE5 0x0 #define HDONE6 0x1000000 /* DMA6 Half Done */ -#define nHDONE6 0x0 #define DONE6 0x2000000 /* DMA6 Done */ -#define nDONE6 0x0 #define HDONE7 0x10000000 /* DMA7 Half Done */ -#define nHDONE7 0x0 #define DONE7 0x20000000 /* DMA7 Done */ -#define nDONE7 0x0 /* Bit masks for MXVR_INT_EN_0 */ #define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */ -#define nNI2AEN 0x0 #define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */ -#define nNA2IEN 0x0 #define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */ -#define nSBU2LEN 0x0 #define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */ -#define nSBL2UEN 0x0 #define PRUEN 0x10 /* Position Register Updated Interrupt Enable */ -#define nPRUEN 0x0 #define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */ -#define nMPRUEN 0x0 #define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */ -#define nDRUEN 0x0 #define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */ -#define nMDRUEN 0x0 #define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */ -#define nSBUEN 0x0 #define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */ -#define nATUEN 0x0 #define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */ -#define nFCZ0EN 0x0 #define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */ -#define nFCZ1EN 0x0 #define PERREN 0x1000 /* Parity Error Interrupt Enable */ -#define nPERREN 0x0 #define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */ -#define nMH2LEN 0x0 #define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */ -#define nML2HEN 0x0 #define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */ -#define nWUPEN 0x0 #define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */ -#define nFU2LEN 0x0 #define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */ -#define nFL2UEN 0x0 #define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */ -#define nBU2LEN 0x0 #define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */ -#define nBL2UEN 0x0 #define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */ -#define nOBERREN 0x0 #define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */ -#define nPFLEN 0x0 #define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */ -#define nSCZEN 0x0 #define FERREN 0x800000 /* FIFO Error Interrupt Enable */ -#define nFERREN 0x0 #define CMREN 0x1000000 /* Control Message Received Interrupt Enable */ -#define nCMREN 0x0 #define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */ -#define nCMROFEN 0x0 #define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */ -#define nCMTSEN 0x0 #define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */ -#define nCMTCEN 0x0 #define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */ -#define nRWRCEN 0x0 #define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */ -#define nBCZEN 0x0 #define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */ -#define nBMERREN 0x0 #define DERREN 0x80000000 /* DMA Error Interrupt Enable */ -#define nDERREN 0x0 /* Bit masks for MXVR_INT_EN_1 */ #define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */ -#define nHDONEEN0 0x0 #define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */ -#define nDONEEN0 0x0 #define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */ -#define nAPREN 0x0 #define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */ -#define nAPROFEN 0x0 #define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */ -#define nHDONEEN1 0x0 #define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */ -#define nDONEEN1 0x0 #define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */ -#define nAPTSEN 0x0 #define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */ -#define nAPTCEN 0x0 #define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */ -#define nHDONEEN2 0x0 #define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */ -#define nDONEEN2 0x0 #define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */ -#define nAPRCEEN 0x0 #define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */ -#define nAPRPEEN 0x0 #define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */ -#define nHDONEEN3 0x0 #define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */ -#define nDONEEN3 0x0 #define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */ -#define nHDONEEN4 0x0 #define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */ -#define nDONEEN4 0x0 #define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */ -#define nHDONEEN5 0x0 #define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */ -#define nDONEEN5 0x0 #define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */ -#define nHDONEEN6 0x0 #define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */ -#define nDONEEN6 0x0 #define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */ -#define nHDONEEN7 0x0 #define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */ -#define nDONEEN7 0x0 /* Bit masks for MXVR_POSITION */ #define POSITION 0x3f /* Node Position */ #define PVALID 0x8000 /* Node Position Valid */ -#define nPVALID 0x0 /* Bit masks for MXVR_MAX_POSITION */ #define MPOSITION 0x3f /* Maximum Node Position */ #define MPVALID 0x8000 /* Maximum Node Position Valid */ -#define nMPVALID 0x0 /* Bit masks for MXVR_DELAY */ #define DELAY 0x3f /* Node Frame Delay */ #define DVALID 0x8000 /* Node Frame Delay Valid */ -#define nDVALID 0x0 /* Bit masks for MXVR_MAX_DELAY */ #define MDELAY 0x3f /* Maximum Node Frame Delay */ #define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */ -#define nMDVALID 0x0 /* Bit masks for MXVR_LADDR */ #define LADDR 0xffff /* Logical Address */ #define LVALID 0x80000000 /* Logical Address Valid */ -#define nLVALID 0x0 /* Bit masks for MXVR_GADDR */ #define GADDRL 0xff /* Group Address Lower Byte */ #define GVALID 0x8000 /* Group Address Valid */ -#define nGVALID 0x0 /* Bit masks for MXVR_AADDR */ #define AADDR 0xffff /* Alternate Address */ #define AVALID 0x80000000 /* Alternate Address Valid */ -#define nAVALID 0x0 /* Bit masks for MXVR_ALLOC_0 */ #define CL0 0x7f /* Channel 0 Connection Label */ #define CIU0 0x80 /* Channel 0 In Use */ -#define nCIU0 0x0 #define CL1 0x7f00 /* Channel 0 Connection Label */ #define CIU1 0x8000 /* Channel 0 In Use */ -#define nCIU1 0x0 #define CL2 0x7f0000 /* Channel 0 Connection Label */ #define CIU2 0x800000 /* Channel 0 In Use */ -#define nCIU2 0x0 #define CL3 0x7f000000 /* Channel 0 Connection Label */ #define CIU3 0x80000000 /* Channel 0 In Use */ -#define nCIU3 0x0 /* Bit masks for MXVR_ALLOC_1 */ #define CL4 0x7f /* Channel 4 Connection Label */ #define CIU4 0x80 /* Channel 4 In Use */ -#define nCIU4 0x0 #define CL5 0x7f00 /* Channel 5 Connection Label */ #define CIU5 0x8000 /* Channel 5 In Use */ -#define nCIU5 0x0 #define CL6 0x7f0000 /* Channel 6 Connection Label */ #define CIU6 0x800000 /* Channel 6 In Use */ -#define nCIU6 0x0 #define CL7 0x7f000000 /* Channel 7 Connection Label */ #define CIU7 0x80000000 /* Channel 7 In Use */ -#define nCIU7 0x0 /* Bit masks for MXVR_ALLOC_2 */ #define CL8 0x7f /* Channel 8 Connection Label */ #define CIU8 0x80 /* Channel 8 In Use */ -#define nCIU8 0x0 #define CL9 0x7f00 /* Channel 9 Connection Label */ #define CIU9 0x8000 /* Channel 9 In Use */ -#define nCIU9 0x0 #define CL10 0x7f0000 /* Channel 10 Connection Label */ #define CIU10 0x800000 /* Channel 10 In Use */ -#define nCIU10 0x0 #define CL11 0x7f000000 /* Channel 11 Connection Label */ #define CIU11 0x80000000 /* Channel 11 In Use */ -#define nCIU11 0x0 /* Bit masks for MXVR_ALLOC_3 */ #define CL12 0x7f /* Channel 12 Connection Label */ #define CIU12 0x80 /* Channel 12 In Use */ -#define nCIU12 0x0 #define CL13 0x7f00 /* Channel 13 Connection Label */ #define CIU13 0x8000 /* Channel 13 In Use */ -#define nCIU13 0x0 #define CL14 0x7f0000 /* Channel 14 Connection Label */ #define CIU14 0x800000 /* Channel 14 In Use */ -#define nCIU14 0x0 #define CL15 0x7f000000 /* Channel 15 Connection Label */ #define CIU15 0x80000000 /* Channel 15 In Use */ -#define nCIU15 0x0 /* Bit masks for MXVR_ALLOC_4 */ #define CL16 0x7f /* Channel 16 Connection Label */ #define CIU16 0x80 /* Channel 16 In Use */ -#define nCIU16 0x0 #define CL17 0x7f00 /* Channel 17 Connection Label */ #define CIU17 0x8000 /* Channel 17 In Use */ -#define nCIU17 0x0 #define CL18 0x7f0000 /* Channel 18 Connection Label */ #define CIU18 0x800000 /* Channel 18 In Use */ -#define nCIU18 0x0 #define CL19 0x7f000000 /* Channel 19 Connection Label */ #define CIU19 0x80000000 /* Channel 19 In Use */ -#define nCIU19 0x0 /* Bit masks for MXVR_ALLOC_5 */ #define CL20 0x7f /* Channel 20 Connection Label */ #define CIU20 0x80 /* Channel 20 In Use */ -#define nCIU20 0x0 #define CL21 0x7f00 /* Channel 21 Connection Label */ #define CIU21 0x8000 /* Channel 21 In Use */ -#define nCIU21 0x0 #define CL22 0x7f0000 /* Channel 22 Connection Label */ #define CIU22 0x800000 /* Channel 22 In Use */ -#define nCIU22 0x0 #define CL23 0x7f000000 /* Channel 23 Connection Label */ #define CIU23 0x80000000 /* Channel 23 In Use */ -#define nCIU23 0x0 /* Bit masks for MXVR_ALLOC_6 */ #define CL24 0x7f /* Channel 24 Connection Label */ #define CIU24 0x80 /* Channel 24 In Use */ -#define nCIU24 0x0 #define CL25 0x7f00 /* Channel 25 Connection Label */ #define CIU25 0x8000 /* Channel 25 In Use */ -#define nCIU25 0x0 #define CL26 0x7f0000 /* Channel 26 Connection Label */ #define CIU26 0x800000 /* Channel 26 In Use */ -#define nCIU26 0x0 #define CL27 0x7f000000 /* Channel 27 Connection Label */ #define CIU27 0x80000000 /* Channel 27 In Use */ -#define nCIU27 0x0 /* Bit masks for MXVR_ALLOC_7 */ #define CL28 0x7f /* Channel 28 Connection Label */ #define CIU28 0x80 /* Channel 28 In Use */ -#define nCIU28 0x0 #define CL29 0x7f00 /* Channel 29 Connection Label */ #define CIU29 0x8000 /* Channel 29 In Use */ -#define nCIU29 0x0 #define CL30 0x7f0000 /* Channel 30 Connection Label */ #define CIU30 0x800000 /* Channel 30 In Use */ -#define nCIU30 0x0 #define CL31 0x7f000000 /* Channel 31 Connection Label */ #define CIU31 0x80000000 /* Channel 31 In Use */ -#define nCIU31 0x0 /* Bit masks for MXVR_ALLOC_8 */ #define CL32 0x7f /* Channel 32 Connection Label */ #define CIU32 0x80 /* Channel 32 In Use */ -#define nCIU32 0x0 #define CL33 0x7f00 /* Channel 33 Connection Label */ #define CIU33 0x8000 /* Channel 33 In Use */ -#define nCIU33 0x0 #define CL34 0x7f0000 /* Channel 34 Connection Label */ #define CIU34 0x800000 /* Channel 34 In Use */ -#define nCIU34 0x0 #define CL35 0x7f000000 /* Channel 35 Connection Label */ #define CIU35 0x80000000 /* Channel 35 In Use */ -#define nCIU35 0x0 /* Bit masks for MXVR_ALLOC_9 */ #define CL36 0x7f /* Channel 36 Connection Label */ #define CIU36 0x80 /* Channel 36 In Use */ -#define nCIU36 0x0 #define CL37 0x7f00 /* Channel 37 Connection Label */ #define CIU37 0x8000 /* Channel 37 In Use */ -#define nCIU37 0x0 #define CL38 0x7f0000 /* Channel 38 Connection Label */ #define CIU38 0x800000 /* Channel 38 In Use */ -#define nCIU38 0x0 #define CL39 0x7f000000 /* Channel 39 Connection Label */ #define CIU39 0x80000000 /* Channel 39 In Use */ -#define nCIU39 0x0 /* Bit masks for MXVR_ALLOC_10 */ #define CL40 0x7f /* Channel 40 Connection Label */ #define CIU40 0x80 /* Channel 40 In Use */ -#define nCIU40 0x0 #define CL41 0x7f00 /* Channel 41 Connection Label */ #define CIU41 0x8000 /* Channel 41 In Use */ -#define nCIU41 0x0 #define CL42 0x7f0000 /* Channel 42 Connection Label */ #define CIU42 0x800000 /* Channel 42 In Use */ -#define nCIU42 0x0 #define CL43 0x7f000000 /* Channel 43 Connection Label */ #define CIU43 0x80000000 /* Channel 43 In Use */ -#define nCIU43 0x0 /* Bit masks for MXVR_ALLOC_11 */ #define CL44 0x7f /* Channel 44 Connection Label */ #define CIU44 0x80 /* Channel 44 In Use */ -#define nCIU44 0x0 #define CL45 0x7f00 /* Channel 45 Connection Label */ #define CIU45 0x8000 /* Channel 45 In Use */ -#define nCIU45 0x0 #define CL46 0x7f0000 /* Channel 46 Connection Label */ #define CIU46 0x800000 /* Channel 46 In Use */ -#define nCIU46 0x0 #define CL47 0x7f000000 /* Channel 47 Connection Label */ #define CIU47 0x80000000 /* Channel 47 In Use */ -#define nCIU47 0x0 /* Bit masks for MXVR_ALLOC_12 */ #define CL48 0x7f /* Channel 48 Connection Label */ #define CIU48 0x80 /* Channel 48 In Use */ -#define nCIU48 0x0 #define CL49 0x7f00 /* Channel 49 Connection Label */ #define CIU49 0x8000 /* Channel 49 In Use */ -#define nCIU49 0x0 #define CL50 0x7f0000 /* Channel 50 Connection Label */ #define CIU50 0x800000 /* Channel 50 In Use */ -#define nCIU50 0x0 #define CL51 0x7f000000 /* Channel 51 Connection Label */ #define CIU51 0x80000000 /* Channel 51 In Use */ -#define nCIU51 0x0 /* Bit masks for MXVR_ALLOC_13 */ #define CL52 0x7f /* Channel 52 Connection Label */ #define CIU52 0x80 /* Channel 52 In Use */ -#define nCIU52 0x0 #define CL53 0x7f00 /* Channel 53 Connection Label */ #define CIU53 0x8000 /* Channel 53 In Use */ -#define nCIU53 0x0 #define CL54 0x7f0000 /* Channel 54 Connection Label */ #define CIU54 0x800000 /* Channel 54 In Use */ -#define nCIU54 0x0 #define CL55 0x7f000000 /* Channel 55 Connection Label */ #define CIU55 0x80000000 /* Channel 55 In Use */ -#define nCIU55 0x0 /* Bit masks for MXVR_ALLOC_14 */ #define CL56 0x7f /* Channel 56 Connection Label */ #define CIU56 0x80 /* Channel 56 In Use */ -#define nCIU56 0x0 #define CL57 0x7f00 /* Channel 57 Connection Label */ #define CIU57 0x8000 /* Channel 57 In Use */ -#define nCIU57 0x0 #define CL58 0x7f0000 /* Channel 58 Connection Label */ #define CIU58 0x800000 /* Channel 58 In Use */ -#define nCIU58 0x0 #define CL59 0x7f000000 /* Channel 59 Connection Label */ #define CIU59 0x80000000 /* Channel 59 In Use */ -#define nCIU59 0x0 /* MXVR_SYNC_LCHAN_0 Masks */ @@ -1926,19 +1669,13 @@ /* Bit masks for MXVR_DMAx_CONFIG */ #define MDMAEN 0x1 /* DMA Channel Enable */ -#define nMDMAEN 0x0 #define DD 0x2 /* DMA Channel Direction */ -#define nDD 0x0 #define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */ -#define nBY4SWAPEN 0x0 #define LCHAN 0x3c0 /* DMA Channel Logical Channel */ #define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */ -#define nBITSWAPEN 0x0 #define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */ -#define nBY2SWAPEN 0x0 #define MFLOW 0x7000 /* DMA Channel Operation Flow */ #define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */ -#define nFIXEDPM 0x0 #define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */ #define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */ #define COUNTPOS 0x1c000000 /* DMA Channel Count Position */ @@ -1946,94 +1683,71 @@ /* Bit masks for MXVR_AP_CTL */ #define STARTAP 0x1 /* Start Asynchronous Packet Transmission */ -#define nSTARTAP 0x0 #define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */ -#define nCANCELAP 0x0 #define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */ -#define nRESETAP 0x0 #define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */ -#define nAPRBE0 0x0 #define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */ -#define nAPRBE1 0x0 /* Bit masks for MXVR_APRB_START_ADDR */ -#define MXVR_APRB_START_ADDR 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */ +#define MXVR_APRB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */ /* Bit masks for MXVR_APRB_CURR_ADDR */ -#define MXVR_APRB_CURR_ADDR 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */ +#define MXVR_APRB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */ /* Bit masks for MXVR_APTB_START_ADDR */ -#define MXVR_APTB_START_ADDR 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */ +#define MXVR_APTB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */ /* Bit masks for MXVR_APTB_CURR_ADDR */ -#define MXVR_APTB_CURR_ADDR 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */ +#define MXVR_APTB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */ /* Bit masks for MXVR_CM_CTL */ #define STARTCM 0x1 /* Start Control Message Transmission */ -#define nSTARTCM 0x0 #define CANCELCM 0x2 /* Cancel Control Message Transmission */ -#define nCANCELCM 0x0 #define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */ -#define nCMRBE0 0x0 #define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */ -#define nCMRBE1 0x0 #define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */ -#define nCMRBE2 0x0 #define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */ -#define nCMRBE3 0x0 #define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */ -#define nCMRBE4 0x0 #define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */ -#define nCMRBE5 0x0 #define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */ -#define nCMRBE6 0x0 #define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */ -#define nCMRBE7 0x0 #define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */ -#define nCMRBE8 0x0 #define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */ -#define nCMRBE9 0x0 #define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */ -#define nCMRBE10 0x0 #define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */ -#define nCMRBE11 0x0 #define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */ -#define nCMRBE12 0x0 #define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */ -#define nCMRBE13 0x0 #define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */ -#define nCMRBE14 0x0 #define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */ -#define nCMRBE15 0x0 /* Bit masks for MXVR_CMRB_START_ADDR */ -#define MXVR_CMRB_START_ADDR 0x1fffffe /* Control Message Receive Buffer Start Address */ +#define MXVR_CMRB_START_ADDR_MASK 0x1fffffe /* Control Message Receive Buffer Start Address */ /* Bit masks for MXVR_CMRB_CURR_ADDR */ -#define MXVR_CMRB_CURR_ADDR 0xffffffff /* Control Message Receive Buffer Current Address */ +#define MXVR_CMRB_CURR_ADDR_MASK 0xffffffff /* Control Message Receive Buffer Current Address */ /* Bit masks for MXVR_CMTB_START_ADDR */ -#define MXVR_CMTB_START_ADDR 0x1fffffe /* Control Message Transmit Buffer Start Address */ +#define MXVR_CMTB_START_ADDR_MASK 0x1fffffe /* Control Message Transmit Buffer Start Address */ /* Bit masks for MXVR_CMTB_CURR_ADDR */ -#define MXVR_CMTB_CURR_ADDR 0xffffffff /* Control Message Transmit Buffer Current Address */ +#define MXVR_CMTB_CURR_ADDR_MASK 0xffffffff /* Control Message Transmit Buffer Current Address */ /* Bit masks for MXVR_RRDB_START_ADDR */ -#define MXVR_RRDB_START_ADDR 0x1fffffe /* Remote Read Buffer Start Address */ +#define MXVR_RRDB_START_ADDR_MASK 0x1fffffe /* Remote Read Buffer Start Address */ /* Bit masks for MXVR_RRDB_CURR_ADDR */ -#define MXVR_RRDB_CURR_ADDR 0xffffffff /* Remote Read Buffer Current Address */ +#define MXVR_RRDB_CURR_ADDR_MASK 0xffffffff /* Remote Read Buffer Current Address */ /* Bit masks for MXVR_PAT_DATAx */ @@ -2045,136 +1759,72 @@ /* Bit masks for MXVR_PAT_EN_0 */ #define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ -#define nMATCH_EN_0_0 0x0 #define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ -#define nMATCH_EN_0_1 0x0 #define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ -#define nMATCH_EN_0_2 0x0 #define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ -#define nMATCH_EN_0_3 0x0 #define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ -#define nMATCH_EN_0_4 0x0 #define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ -#define nMATCH_EN_0_5 0x0 #define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ -#define nMATCH_EN_0_6 0x0 #define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ -#define nMATCH_EN_0_7 0x0 #define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ -#define nMATCH_EN_1_0 0x0 #define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ -#define nMATCH_EN_1_1 0x0 #define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ -#define nMATCH_EN_1_2 0x0 #define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ -#define nMATCH_EN_1_3 0x0 #define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ -#define nMATCH_EN_1_4 0x0 #define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ -#define nMATCH_EN_1_5 0x0 #define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ -#define nMATCH_EN_1_6 0x0 #define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ -#define nMATCH_EN_1_7 0x0 #define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ -#define nMATCH_EN_2_0 0x0 #define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ -#define nMATCH_EN_2_1 0x0 #define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ -#define nMATCH_EN_2_2 0x0 #define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ -#define nMATCH_EN_2_3 0x0 #define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ -#define nMATCH_EN_2_4 0x0 #define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ -#define nMATCH_EN_2_5 0x0 #define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ -#define nMATCH_EN_2_6 0x0 #define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ -#define nMATCH_EN_2_7 0x0 #define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ -#define nMATCH_EN_3_0 0x0 #define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ -#define nMATCH_EN_3_1 0x0 #define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ -#define nMATCH_EN_3_2 0x0 #define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ -#define nMATCH_EN_3_3 0x0 #define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ -#define nMATCH_EN_3_4 0x0 #define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ -#define nMATCH_EN_3_5 0x0 #define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ -#define nMATCH_EN_3_6 0x0 #define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ -#define nMATCH_EN_3_7 0x0 /* Bit masks for MXVR_PAT_EN_1 */ #define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ -#define nMATCH_EN_0_0 0x0 #define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ -#define nMATCH_EN_0_1 0x0 #define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ -#define nMATCH_EN_0_2 0x0 #define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ -#define nMATCH_EN_0_3 0x0 #define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ -#define nMATCH_EN_0_4 0x0 #define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ -#define nMATCH_EN_0_5 0x0 #define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ -#define nMATCH_EN_0_6 0x0 #define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ -#define nMATCH_EN_0_7 0x0 #define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ -#define nMATCH_EN_1_0 0x0 #define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ -#define nMATCH_EN_1_1 0x0 #define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ -#define nMATCH_EN_1_2 0x0 #define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ -#define nMATCH_EN_1_3 0x0 #define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ -#define nMATCH_EN_1_4 0x0 #define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ -#define nMATCH_EN_1_5 0x0 #define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ -#define nMATCH_EN_1_6 0x0 #define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ -#define nMATCH_EN_1_7 0x0 #define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ -#define nMATCH_EN_2_0 0x0 #define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ -#define nMATCH_EN_2_1 0x0 #define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ -#define nMATCH_EN_2_2 0x0 #define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ -#define nMATCH_EN_2_3 0x0 #define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ -#define nMATCH_EN_2_4 0x0 #define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ -#define nMATCH_EN_2_5 0x0 #define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ -#define nMATCH_EN_2_6 0x0 #define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ -#define nMATCH_EN_2_7 0x0 #define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ -#define nMATCH_EN_3_0 0x0 #define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ -#define nMATCH_EN_3_1 0x0 #define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ -#define nMATCH_EN_3_2 0x0 #define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ -#define nMATCH_EN_3_3 0x0 #define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ -#define nMATCH_EN_3_4 0x0 #define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ -#define nMATCH_EN_3_5 0x0 #define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ -#define nMATCH_EN_3_6 0x0 #define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ -#define nMATCH_EN_3_7 0x0 /* Bit masks for MXVR_FRAME_CNT_0 */ @@ -2188,226 +1838,166 @@ #define TX_CH0 0x3f /* Transmit Channel 0 */ #define MUTE_CH0 0x80 /* Mute Channel 0 */ -#define nMUTE_CH0 0x0 #define TX_CH1 0x3f00 /* Transmit Channel 0 */ #define MUTE_CH1 0x8000 /* Mute Channel 0 */ -#define nMUTE_CH1 0x0 #define TX_CH2 0x3f0000 /* Transmit Channel 0 */ #define MUTE_CH2 0x800000 /* Mute Channel 0 */ -#define nMUTE_CH2 0x0 #define TX_CH3 0x3f000000 /* Transmit Channel 0 */ #define MUTE_CH3 0x80000000 /* Mute Channel 0 */ -#define nMUTE_CH3 0x0 /* Bit masks for MXVR_ROUTING_1 */ #define TX_CH4 0x3f /* Transmit Channel 4 */ #define MUTE_CH4 0x80 /* Mute Channel 4 */ -#define nMUTE_CH4 0x0 #define TX_CH5 0x3f00 /* Transmit Channel 5 */ #define MUTE_CH5 0x8000 /* Mute Channel 5 */ -#define nMUTE_CH5 0x0 #define TX_CH6 0x3f0000 /* Transmit Channel 6 */ #define MUTE_CH6 0x800000 /* Mute Channel 6 */ -#define nMUTE_CH6 0x0 #define TX_CH7 0x3f000000 /* Transmit Channel 7 */ #define MUTE_CH7 0x80000000 /* Mute Channel 7 */ -#define nMUTE_CH7 0x0 /* Bit masks for MXVR_ROUTING_2 */ #define TX_CH8 0x3f /* Transmit Channel 8 */ #define MUTE_CH8 0x80 /* Mute Channel 8 */ -#define nMUTE_CH8 0x0 #define TX_CH9 0x3f00 /* Transmit Channel 9 */ #define MUTE_CH9 0x8000 /* Mute Channel 9 */ -#define nMUTE_CH9 0x0 #define TX_CH10 0x3f0000 /* Transmit Channel 10 */ #define MUTE_CH10 0x800000 /* Mute Channel 10 */ -#define nMUTE_CH10 0x0 #define TX_CH11 0x3f000000 /* Transmit Channel 11 */ #define MUTE_CH11 0x80000000 /* Mute Channel 11 */ -#define nMUTE_CH11 0x0 /* Bit masks for MXVR_ROUTING_3 */ #define TX_CH12 0x3f /* Transmit Channel 12 */ #define MUTE_CH12 0x80 /* Mute Channel 12 */ -#define nMUTE_CH12 0x0 #define TX_CH13 0x3f00 /* Transmit Channel 13 */ #define MUTE_CH13 0x8000 /* Mute Channel 13 */ -#define nMUTE_CH13 0x0 #define TX_CH14 0x3f0000 /* Transmit Channel 14 */ #define MUTE_CH14 0x800000 /* Mute Channel 14 */ -#define nMUTE_CH14 0x0 #define TX_CH15 0x3f000000 /* Transmit Channel 15 */ #define MUTE_CH15 0x80000000 /* Mute Channel 15 */ -#define nMUTE_CH15 0x0 /* Bit masks for MXVR_ROUTING_4 */ #define TX_CH16 0x3f /* Transmit Channel 16 */ #define MUTE_CH16 0x80 /* Mute Channel 16 */ -#define nMUTE_CH16 0x0 #define TX_CH17 0x3f00 /* Transmit Channel 17 */ #define MUTE_CH17 0x8000 /* Mute Channel 17 */ -#define nMUTE_CH17 0x0 #define TX_CH18 0x3f0000 /* Transmit Channel 18 */ #define MUTE_CH18 0x800000 /* Mute Channel 18 */ -#define nMUTE_CH18 0x0 #define TX_CH19 0x3f000000 /* Transmit Channel 19 */ #define MUTE_CH19 0x80000000 /* Mute Channel 19 */ -#define nMUTE_CH19 0x0 /* Bit masks for MXVR_ROUTING_5 */ #define TX_CH20 0x3f /* Transmit Channel 20 */ #define MUTE_CH20 0x80 /* Mute Channel 20 */ -#define nMUTE_CH20 0x0 #define TX_CH21 0x3f00 /* Transmit Channel 21 */ #define MUTE_CH21 0x8000 /* Mute Channel 21 */ -#define nMUTE_CH21 0x0 #define TX_CH22 0x3f0000 /* Transmit Channel 22 */ #define MUTE_CH22 0x800000 /* Mute Channel 22 */ -#define nMUTE_CH22 0x0 #define TX_CH23 0x3f000000 /* Transmit Channel 23 */ #define MUTE_CH23 0x80000000 /* Mute Channel 23 */ -#define nMUTE_CH23 0x0 /* Bit masks for MXVR_ROUTING_6 */ #define TX_CH24 0x3f /* Transmit Channel 24 */ #define MUTE_CH24 0x80 /* Mute Channel 24 */ -#define nMUTE_CH24 0x0 #define TX_CH25 0x3f00 /* Transmit Channel 25 */ #define MUTE_CH25 0x8000 /* Mute Channel 25 */ -#define nMUTE_CH25 0x0 #define TX_CH26 0x3f0000 /* Transmit Channel 26 */ #define MUTE_CH26 0x800000 /* Mute Channel 26 */ -#define nMUTE_CH26 0x0 #define TX_CH27 0x3f000000 /* Transmit Channel 27 */ #define MUTE_CH27 0x80000000 /* Mute Channel 27 */ -#define nMUTE_CH27 0x0 /* Bit masks for MXVR_ROUTING_7 */ #define TX_CH28 0x3f /* Transmit Channel 28 */ #define MUTE_CH28 0x80 /* Mute Channel 28 */ -#define nMUTE_CH28 0x0 #define TX_CH29 0x3f00 /* Transmit Channel 29 */ #define MUTE_CH29 0x8000 /* Mute Channel 29 */ -#define nMUTE_CH29 0x0 #define TX_CH30 0x3f0000 /* Transmit Channel 30 */ #define MUTE_CH30 0x800000 /* Mute Channel 30 */ -#define nMUTE_CH30 0x0 #define TX_CH31 0x3f000000 /* Transmit Channel 31 */ #define MUTE_CH31 0x80000000 /* Mute Channel 31 */ -#define nMUTE_CH31 0x0 /* Bit masks for MXVR_ROUTING_8 */ #define TX_CH32 0x3f /* Transmit Channel 32 */ #define MUTE_CH32 0x80 /* Mute Channel 32 */ -#define nMUTE_CH32 0x0 #define TX_CH33 0x3f00 /* Transmit Channel 33 */ #define MUTE_CH33 0x8000 /* Mute Channel 33 */ -#define nMUTE_CH33 0x0 #define TX_CH34 0x3f0000 /* Transmit Channel 34 */ #define MUTE_CH34 0x800000 /* Mute Channel 34 */ -#define nMUTE_CH34 0x0 #define TX_CH35 0x3f000000 /* Transmit Channel 35 */ #define MUTE_CH35 0x80000000 /* Mute Channel 35 */ -#define nMUTE_CH35 0x0 /* Bit masks for MXVR_ROUTING_9 */ #define TX_CH36 0x3f /* Transmit Channel 36 */ #define MUTE_CH36 0x80 /* Mute Channel 36 */ -#define nMUTE_CH36 0x0 #define TX_CH37 0x3f00 /* Transmit Channel 37 */ #define MUTE_CH37 0x8000 /* Mute Channel 37 */ -#define nMUTE_CH37 0x0 #define TX_CH38 0x3f0000 /* Transmit Channel 38 */ #define MUTE_CH38 0x800000 /* Mute Channel 38 */ -#define nMUTE_CH38 0x0 #define TX_CH39 0x3f000000 /* Transmit Channel 39 */ #define MUTE_CH39 0x80000000 /* Mute Channel 39 */ -#define nMUTE_CH39 0x0 /* Bit masks for MXVR_ROUTING_10 */ #define TX_CH40 0x3f /* Transmit Channel 40 */ #define MUTE_CH40 0x80 /* Mute Channel 40 */ -#define nMUTE_CH40 0x0 #define TX_CH41 0x3f00 /* Transmit Channel 41 */ #define MUTE_CH41 0x8000 /* Mute Channel 41 */ -#define nMUTE_CH41 0x0 #define TX_CH42 0x3f0000 /* Transmit Channel 42 */ #define MUTE_CH42 0x800000 /* Mute Channel 42 */ -#define nMUTE_CH42 0x0 #define TX_CH43 0x3f000000 /* Transmit Channel 43 */ #define MUTE_CH43 0x80000000 /* Mute Channel 43 */ -#define nMUTE_CH43 0x0 /* Bit masks for MXVR_ROUTING_11 */ #define TX_CH44 0x3f /* Transmit Channel 44 */ #define MUTE_CH44 0x80 /* Mute Channel 44 */ -#define nMUTE_CH44 0x0 #define TX_CH45 0x3f00 /* Transmit Channel 45 */ #define MUTE_CH45 0x8000 /* Mute Channel 45 */ -#define nMUTE_CH45 0x0 #define TX_CH46 0x3f0000 /* Transmit Channel 46 */ #define MUTE_CH46 0x800000 /* Mute Channel 46 */ -#define nMUTE_CH46 0x0 #define TX_CH47 0x3f000000 /* Transmit Channel 47 */ #define MUTE_CH47 0x80000000 /* Mute Channel 47 */ -#define nMUTE_CH47 0x0 /* Bit masks for MXVR_ROUTING_12 */ #define TX_CH48 0x3f /* Transmit Channel 48 */ #define MUTE_CH48 0x80 /* Mute Channel 48 */ -#define nMUTE_CH48 0x0 #define TX_CH49 0x3f00 /* Transmit Channel 49 */ #define MUTE_CH49 0x8000 /* Mute Channel 49 */ -#define nMUTE_CH49 0x0 #define TX_CH50 0x3f0000 /* Transmit Channel 50 */ #define MUTE_CH50 0x800000 /* Mute Channel 50 */ -#define nMUTE_CH50 0x0 #define TX_CH51 0x3f000000 /* Transmit Channel 51 */ #define MUTE_CH51 0x80000000 /* Mute Channel 51 */ -#define nMUTE_CH51 0x0 /* Bit masks for MXVR_ROUTING_13 */ #define TX_CH52 0x3f /* Transmit Channel 52 */ #define MUTE_CH52 0x80 /* Mute Channel 52 */ -#define nMUTE_CH52 0x0 #define TX_CH53 0x3f00 /* Transmit Channel 53 */ #define MUTE_CH53 0x8000 /* Mute Channel 53 */ -#define nMUTE_CH53 0x0 #define TX_CH54 0x3f0000 /* Transmit Channel 54 */ #define MUTE_CH54 0x800000 /* Mute Channel 54 */ -#define nMUTE_CH54 0x0 #define TX_CH55 0x3f000000 /* Transmit Channel 55 */ #define MUTE_CH55 0x80000000 /* Mute Channel 55 */ -#define nMUTE_CH55 0x0 /* Bit masks for MXVR_ROUTING_14 */ #define TX_CH56 0x3f /* Transmit Channel 56 */ #define MUTE_CH56 0x80 /* Mute Channel 56 */ -#define nMUTE_CH56 0x0 #define TX_CH57 0x3f00 /* Transmit Channel 57 */ #define MUTE_CH57 0x8000 /* Mute Channel 57 */ -#define nMUTE_CH57 0x0 #define TX_CH58 0x3f0000 /* Transmit Channel 58 */ #define MUTE_CH58 0x800000 /* Mute Channel 58 */ -#define nMUTE_CH58 0x0 #define TX_CH59 0x3f000000 /* Transmit Channel 59 */ #define MUTE_CH59 0x80000000 /* Mute Channel 59 */ -#define nMUTE_CH59 0x0 /* Bit masks for MXVR_BLOCK_CNT */ @@ -2416,53 +2006,37 @@ /* Bit masks for MXVR_CLK_CTL */ #define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */ -#define nMXTALCEN 0x0 #define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */ -#define nMXTALFEN 0x0 #define MXTALMUL 0x30 /* MXVR Crystal Multiplier */ #define CLKX3SEL 0x80 /* Clock Generation Source Select */ -#define nCLKX3SEL 0x0 #define MMCLKEN 0x100 /* Master Clock Enable */ -#define nMMCLKEN 0x0 #define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */ #define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */ #define MBCLKEN 0x10000 /* Bit Clock Enable */ -#define nMBCLKEN 0x0 #define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */ #define INVRX 0x800000 /* Invert Receive Data */ -#define nINVRX 0x0 #define MFSEN 0x1000000 /* Frame Sync Enable */ -#define nMFSEN 0x0 #define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */ #define MFSSEL 0x60000000 /* Frame Sync Select */ #define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */ -#define nMFSSYNC 0x0 /* Bit masks for MXVR_CDRPLL_CTL */ #define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */ -#define nCDRSMEN 0x0 #define CDRRSTB 0x2 /* MXVR CDRPLL Reset */ -#define nCDRRSTB 0x0 #define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */ -#define nCDRSVCO 0x0 #define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */ -#define nCDRMODE 0x0 #define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */ #define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */ #define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */ #define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */ -#define nCDRSHPEN 0x0 #define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */ /* Bit masks for MXVR_FMPLL_CTL */ #define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */ -#define nFMSMEN 0x0 #define FMRSTB 0x2 /* MXVR FMPLL Reset */ -#define nFMRSTB 0x0 #define FMSVCO 0x4 /* MXVR FMPLL Start VCO */ -#define nFMSVCO 0x0 #define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */ #define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */ #define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */ @@ -2470,15 +2044,10 @@ /* Bit masks for MXVR_PIN_CTL */ #define MTXONBOD 0x1 /* MTXONB Open Drain Select */ -#define nMTXONBOD 0x0 #define MTXONBG 0x2 /* MTXONB Gates MTX Select */ -#define nMTXONBG 0x0 #define MFSOE 0x10 /* MFS Output Enable */ -#define nMFSOE 0x0 #define MFSGPSEL 0x20 /* MFS General Purpose Output Select */ -#define nMFSGPSEL 0x0 #define MFSGPDAT 0x40 /* MFS General Purpose Output Data */ -#define nMFSGPDAT 0x0 /* Bit masks for MXVR_SCLK_CNT */ @@ -2487,7 +2056,6 @@ /* Bit masks for KPAD_CTL */ #define KPAD_EN 0x1 /* Keypad Enable */ -#define nKPAD_EN 0x0 #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ #define KPAD_COLEN 0xe000 /* Column Enable Width */ @@ -2509,29 +2077,21 @@ /* Bit masks for KPAD_STAT */ #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ -#define nKPAD_IRQ 0x0 #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ #define KPAD_PRESSED 0x8 /* Key press current status */ -#define nKPAD_PRESSED 0x0 /* Bit masks for KPAD_SOFTEVAL */ #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ -#define nKPAD_SOFTEVAL_E 0x0 /* Bit masks for SDH_COMMAND */ #define CMD_IDX 0x3f /* Command Index */ #define CMD_RSP 0x40 /* Response */ -#define nCMD_RSP 0x0 #define CMD_L_RSP 0x80 /* Long Response */ -#define nCMD_L_RSP 0x0 #define CMD_INT_E 0x100 /* Command Interrupt */ -#define nCMD_INT_E 0x0 #define CMD_PEND_E 0x200 /* Command Pending */ -#define nCMD_PEND_E 0x0 #define CMD_E 0x400 /* Command Enable */ -#define nCMD_E 0x0 /* Bit masks for SDH_PWR_CTL */ @@ -2540,21 +2100,15 @@ #define TBD 0x3c /* TBD */ #endif #define SD_CMD_OD 0x40 /* Open Drain Output */ -#define nSD_CMD_OD 0x0 #define ROD_CTL 0x80 /* Rod Control */ -#define nROD_CTL 0x0 /* Bit masks for SDH_CLK_CTL */ #define CLKDIV 0xff /* MC_CLK Divisor */ #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ -#define nCLK_E 0x0 #define PWR_SV_E 0x200 /* Power Save Enable */ -#define nPWR_SV_E 0x0 #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ -#define nCLKDIV_BYPASS 0x0 #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ -#define nWIDE_BUS 0x0 /* Bit masks for SDH_RESP_CMD */ @@ -2563,133 +2117,74 @@ /* Bit masks for SDH_DATA_CTL */ #define DTX_E 0x1 /* Data Transfer Enable */ -#define nDTX_E 0x0 #define DTX_DIR 0x2 /* Data Transfer Direction */ -#define nDTX_DIR 0x0 #define DTX_MODE 0x4 /* Data Transfer Mode */ -#define nDTX_MODE 0x0 #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ -#define nDTX_DMA_E 0x0 #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ /* Bit masks for SDH_STATUS */ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ -#define nCMD_CRC_FAIL 0x0 #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define nDAT_CRC_FAIL 0x0 -#define CMD_TIMEOUT 0x4 /* CMD Time Out */ -#define nCMD_TIMEOUT 0x0 -#define DAT_TIMEOUT 0x8 /* Data Time Out */ -#define nDAT_TIMEOUT 0x0 +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ #define TX_UNDERRUN 0x10 /* Transmit Underrun */ -#define nTX_UNDERRUN 0x0 #define RX_OVERRUN 0x20 /* Receive Overrun */ -#define nRX_OVERRUN 0x0 #define CMD_RESP_END 0x40 /* CMD Response End */ -#define nCMD_RESP_END 0x0 #define CMD_SENT 0x80 /* CMD Sent */ -#define nCMD_SENT 0x0 #define DAT_END 0x100 /* Data End */ -#define nDAT_END 0x0 #define START_BIT_ERR 0x200 /* Start Bit Error */ -#define nSTART_BIT_ERR 0x0 #define DAT_BLK_END 0x400 /* Data Block End */ -#define nDAT_BLK_END 0x0 #define CMD_ACT 0x800 /* CMD Active */ -#define nCMD_ACT 0x0 #define TX_ACT 0x1000 /* Transmit Active */ -#define nTX_ACT 0x0 #define RX_ACT 0x2000 /* Receive Active */ -#define nRX_ACT 0x0 #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ -#define nTX_FIFO_STAT 0x0 #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ -#define nRX_FIFO_STAT 0x0 #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ -#define nTX_FIFO_FULL 0x0 #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ -#define nRX_FIFO_FULL 0x0 #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ -#define nTX_FIFO_ZERO 0x0 #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ -#define nRX_DAT_ZERO 0x0 #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ -#define nTX_DAT_RDY 0x0 #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ -#define nRX_FIFO_RDY 0x0 /* Bit masks for SDH_STATUS_CLR */ #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ -#define nCMD_CRC_FAIL_STAT 0x0 #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ -#define nDAT_CRC_FAIL_STAT 0x0 #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ -#define nCMD_TIMEOUT_STAT 0x0 #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ -#define nDAT_TIMEOUT_STAT 0x0 #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ -#define nTX_UNDERRUN_STAT 0x0 #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ -#define nRX_OVERRUN_STAT 0x0 #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ -#define nCMD_RESP_END_STAT 0x0 #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ -#define nCMD_SENT_STAT 0x0 #define DAT_END_STAT 0x100 /* Data End Status */ -#define nDAT_END_STAT 0x0 #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ -#define nSTART_BIT_ERR_STAT 0x0 #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ -#define nDAT_BLK_END_STAT 0x0 /* Bit masks for SDH_MASK0 */ #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ -#define nCMD_CRC_FAIL_MASK 0x0 #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ -#define nDAT_CRC_FAIL_MASK 0x0 #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ -#define nCMD_TIMEOUT_MASK 0x0 #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ -#define nDAT_TIMEOUT_MASK 0x0 #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ -#define nTX_UNDERRUN_MASK 0x0 #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ -#define nRX_OVERRUN_MASK 0x0 #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ -#define nCMD_RESP_END_MASK 0x0 #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ -#define nCMD_SENT_MASK 0x0 #define DAT_END_MASK 0x100 /* Data End Mask */ -#define nDAT_END_MASK 0x0 #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ -#define nSTART_BIT_ERR_MASK 0x0 #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ -#define nDAT_BLK_END_MASK 0x0 #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ -#define nCMD_ACT_MASK 0x0 #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ -#define nTX_ACT_MASK 0x0 #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ -#define nRX_ACT_MASK 0x0 #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ -#define nTX_FIFO_STAT_MASK 0x0 #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ -#define nRX_FIFO_STAT_MASK 0x0 #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ -#define nTX_FIFO_FULL_MASK 0x0 #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ -#define nRX_FIFO_FULL_MASK 0x0 #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ -#define nTX_FIFO_ZERO_MASK 0x0 #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ -#define nRX_DAT_ZERO_MASK 0x0 #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ -#define nTX_DAT_RDY_MASK 0x0 #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ -#define nRX_FIFO_RDY_MASK 0x0 /* Bit masks for SDH_FIFO_CNT */ @@ -2698,73 +2193,47 @@ /* Bit masks for SDH_E_STATUS */ #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ -#define nSDIO_INT_DET 0x0 #define SD_CARD_DET 0x10 /* SD Card Detect */ -#define nSD_CARD_DET 0x0 /* Bit masks for SDH_E_MASK */ #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ -#define nSDIO_MSK 0x0 #define SCD_MSK 0x40 /* Mask Card Detect */ -#define nSCD_MSK 0x0 /* Bit masks for SDH_CFG */ #define CLKS_EN 0x1 /* Clocks Enable */ -#define nCLKS_EN 0x0 #define SD4E 0x4 /* SDIO 4-Bit Enable */ -#define nSD4E 0x0 #define MWE 0x8 /* Moving Window Enable */ -#define nMWE 0x0 #define SD_RST 0x10 /* SDMMC Reset */ -#define nSD_RST 0x0 #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ -#define nPUP_SDDAT 0x0 #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ -#define nPUP_SDDAT3 0x0 #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ -#define nPD_SDDAT3 0x0 /* Bit masks for SDH_RD_WAIT_EN */ #define RWR 0x1 /* Read Wait Request */ -#define nRWR 0x0 /* Bit masks for ATAPI_CONTROL */ #define PIO_START 0x1 /* Start PIO/Reg Op */ -#define nPIO_START 0x0 #define MULTI_START 0x2 /* Start Multi-DMA Op */ -#define nMULTI_START 0x0 #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ -#define nULTRA_START 0x0 #define XFER_DIR 0x8 /* Transfer Direction */ -#define nXFER_DIR 0x0 #define IORDY_EN 0x10 /* IORDY Enable */ -#define nIORDY_EN 0x0 #define FIFO_FLUSH 0x20 /* Flush FIFOs */ -#define nFIFO_FLUSH 0x0 #define SOFT_RST 0x40 /* Soft Reset */ -#define nSOFT_RST 0x0 #define DEV_RST 0x80 /* Device Reset */ -#define nDEV_RST 0x0 #define TFRCNT_RST 0x100 /* Trans Count Reset */ -#define nTFRCNT_RST 0x0 #define END_ON_TERM 0x200 /* End/Terminate Select */ -#define nEND_ON_TERM 0x0 #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ -#define nPIO_USE_DMA 0x0 #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ /* Bit masks for ATAPI_STATUS */ #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ -#define nPIO_XFER_ON 0x0 #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ -#define nMULTI_XFER_ON 0x0 #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ -#define nULTRA_XFER_ON 0x0 #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ /* Bit masks for ATAPI_DEV_ADDR */ @@ -2774,66 +2243,39 @@ /* Bit masks for ATAPI_INT_MASK */ #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ -#define nATAPI_DEV_INT_MASK 0x0 #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ -#define nPIO_DONE_MASK 0x0 #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ -#define nMULTI_DONE_MASK 0x0 #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ -#define nUDMAIN_DONE_MASK 0x0 #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ -#define nUDMAOUT_DONE_MASK 0x0 #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ -#define nHOST_TERM_XFER_MASK 0x0 #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ -#define nMULTI_TERM_MASK 0x0 #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ -#define nUDMAIN_TERM_MASK 0x0 #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ -#define nUDMAOUT_TERM_MASK 0x0 /* Bit masks for ATAPI_INT_STATUS */ #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ -#define nATAPI_DEV_INT 0x0 #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ -#define nPIO_DONE_INT 0x0 #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ -#define nMULTI_DONE_INT 0x0 #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ -#define nUDMAIN_DONE_INT 0x0 #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ -#define nUDMAOUT_DONE_INT 0x0 #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ -#define nHOST_TERM_XFER_INT 0x0 #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ -#define nMULTI_TERM_INT 0x0 #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ -#define nUDMAIN_TERM_INT 0x0 #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ -#define nUDMAOUT_TERM_INT 0x0 /* Bit masks for ATAPI_LINE_STATUS */ #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ -#define nATAPI_INTR 0x0 #define ATAPI_DASP 0x2 /* Device dasp to host line status */ -#define nATAPI_DASP 0x0 #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ -#define nATAPI_CS0N 0x0 #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ -#define nATAPI_CS1N 0x0 #define ATAPI_ADDR 0x70 /* ATAPI address line status */ #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ -#define nATAPI_DMAREQ 0x0 #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ -#define nATAPI_DMAACKN 0x0 #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ -#define nATAPI_DIOWN 0x0 #define ATAPI_DIORN 0x400 /* ATAPI read line status */ -#define nATAPI_DIORN 0x0 #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ -#define nATAPI_IORDY 0x0 /* Bit masks for ATAPI_SM_STATE */ @@ -2845,7 +2287,6 @@ /* Bit masks for ATAPI_TERMINATE */ #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ -#define nATAPI_HOST_TERM 0x0 /* Bit masks for ATAPI_REG_TIM_0 */ @@ -2900,41 +2341,26 @@ /* Bit masks for TIMER_ENABLE1 */ #define TIMEN8 0x1 /* Timer 8 Enable */ -#define nTIMEN8 0x0 #define TIMEN9 0x2 /* Timer 9 Enable */ -#define nTIMEN9 0x0 #define TIMEN10 0x4 /* Timer 10 Enable */ -#define nTIMEN10 0x0 /* Bit masks for TIMER_DISABLE1 */ #define TIMDIS8 0x1 /* Timer 8 Disable */ -#define nTIMDIS8 0x0 #define TIMDIS9 0x2 /* Timer 9 Disable */ -#define nTIMDIS9 0x0 #define TIMDIS10 0x4 /* Timer 10 Disable */ -#define nTIMDIS10 0x0 /* Bit masks for TIMER_STATUS1 */ #define TIMIL8 0x1 /* Timer 8 Interrupt */ -#define nTIMIL8 0x0 #define TIMIL9 0x2 /* Timer 9 Interrupt */ -#define nTIMIL9 0x0 #define TIMIL10 0x4 /* Timer 10 Interrupt */ -#define nTIMIL10 0x0 #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ -#define nTOVF_ERR8 0x0 #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ -#define nTOVF_ERR9 0x0 #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ -#define nTOVF_ERR10 0x0 #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ -#define nTRUN8 0x0 #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ -#define nTRUN9 0x0 #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ -#define nTRUN10 0x0 /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ @@ -2945,131 +2371,77 @@ /* Bit masks for USB_POWER */ #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ -#define nENABLE_SUSPENDM 0x0 #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ -#define nSUSPEND_MODE 0x0 #define RESUME_MODE 0x4 /* DMA Mode */ -#define nRESUME_MODE 0x0 #define RESET 0x8 /* Reset indicator */ -#define nRESET 0x0 #define HS_MODE 0x10 /* High Speed mode indicator */ -#define nHS_MODE 0x0 #define HS_ENABLE 0x20 /* high Speed Enable */ -#define nHS_ENABLE 0x0 #define SOFT_CONN 0x40 /* Soft connect */ -#define nSOFT_CONN 0x0 #define ISO_UPDATE 0x80 /* Isochronous update */ -#define nISO_UPDATE 0x0 /* Bit masks for USB_INTRTX */ #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ -#define nEP0_TX 0x0 #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ -#define nEP1_TX 0x0 #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ -#define nEP2_TX 0x0 #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ -#define nEP3_TX 0x0 #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ -#define nEP4_TX 0x0 #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ -#define nEP5_TX 0x0 #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ -#define nEP6_TX 0x0 #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ -#define nEP7_TX 0x0 /* Bit masks for USB_INTRRX */ #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ -#define nEP1_RX 0x0 #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ -#define nEP2_RX 0x0 #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ -#define nEP3_RX 0x0 #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ -#define nEP4_RX 0x0 #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ -#define nEP5_RX 0x0 #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ -#define nEP6_RX 0x0 #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ -#define nEP7_RX 0x0 /* Bit masks for USB_INTRTXE */ #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ -#define nEP0_TX_E 0x0 #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ -#define nEP1_TX_E 0x0 #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ -#define nEP2_TX_E 0x0 #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ -#define nEP3_TX_E 0x0 #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ -#define nEP4_TX_E 0x0 #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ -#define nEP5_TX_E 0x0 #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ -#define nEP6_TX_E 0x0 #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ -#define nEP7_TX_E 0x0 /* Bit masks for USB_INTRRXE */ #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ -#define nEP1_RX_E 0x0 #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ -#define nEP2_RX_E 0x0 #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ -#define nEP3_RX_E 0x0 #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ -#define nEP4_RX_E 0x0 #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ -#define nEP5_RX_E 0x0 #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ -#define nEP6_RX_E 0x0 #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ -#define nEP7_RX_E 0x0 /* Bit masks for USB_INTRUSB */ #define SUSPEND_B 0x1 /* Suspend indicator */ -#define nSUSPEND_B 0x0 #define RESUME_B 0x2 /* Resume indicator */ -#define nRESUME_B 0x0 #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ -#define nRESET_OR_BABLE_B 0x0 #define SOF_B 0x8 /* Start of frame */ -#define nSOF_B 0x0 #define CONN_B 0x10 /* Connection indicator */ -#define nCONN_B 0x0 #define DISCON_B 0x20 /* Disconnect indicator */ -#define nDISCON_B 0x0 #define SESSION_REQ_B 0x40 /* Session Request */ -#define nSESSION_REQ_B 0x0 #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ -#define nVBUS_ERROR_B 0x0 /* Bit masks for USB_INTRUSBE */ #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ -#define nSUSPEND_BE 0x0 #define RESUME_BE 0x2 /* Resume indicator int enable */ -#define nRESUME_BE 0x0 #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ -#define nRESET_OR_BABLE_BE 0x0 #define SOF_BE 0x8 /* Start of frame int enable */ -#define nSOF_BE 0x0 #define CONN_BE 0x10 /* Connection indicator int enable */ -#define nCONN_BE 0x0 #define DISCON_BE 0x20 /* Disconnect indicator int enable */ -#define nDISCON_BE 0x0 #define SESSION_REQ_BE 0x40 /* Session Request int enable */ -#define nSESSION_REQ_BE 0x0 #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ -#define nVBUS_ERROR_BE 0x0 /* Bit masks for USB_FRAME */ @@ -3082,117 +2454,67 @@ /* Bit masks for USB_GLOBAL_CTL */ #define GLOBAL_ENA 0x1 /* enables USB module */ -#define nGLOBAL_ENA 0x0 #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ -#define nEP1_TX_ENA 0x0 #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ -#define nEP2_TX_ENA 0x0 #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ -#define nEP3_TX_ENA 0x0 #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ -#define nEP4_TX_ENA 0x0 #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ -#define nEP5_TX_ENA 0x0 #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ -#define nEP6_TX_ENA 0x0 #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ -#define nEP7_TX_ENA 0x0 #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ -#define nEP1_RX_ENA 0x0 #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ -#define nEP2_RX_ENA 0x0 #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ -#define nEP3_RX_ENA 0x0 #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ -#define nEP4_RX_ENA 0x0 #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ -#define nEP5_RX_ENA 0x0 #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ -#define nEP6_RX_ENA 0x0 #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ -#define nEP7_RX_ENA 0x0 /* Bit masks for USB_OTG_DEV_CTL */ #define SESSION 0x1 /* session indicator */ -#define nSESSION 0x0 #define HOST_REQ 0x2 /* Host negotiation request */ -#define nHOST_REQ 0x0 #define HOST_MODE 0x4 /* indicates USBDRC is a host */ -#define nHOST_MODE 0x0 #define VBUS0 0x8 /* Vbus level indicator[0] */ -#define nVBUS0 0x0 #define VBUS1 0x10 /* Vbus level indicator[1] */ -#define nVBUS1 0x0 #define LSDEV 0x20 /* Low-speed indicator */ -#define nLSDEV 0x0 #define FSDEV 0x40 /* Full or High-speed indicator */ -#define nFSDEV 0x0 #define B_DEVICE 0x80 /* A' or 'B' device indicator */ -#define nB_DEVICE 0x0 /* Bit masks for USB_OTG_VBUS_IRQ */ #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ -#define nDRIVE_VBUS_ON 0x0 #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ -#define nDRIVE_VBUS_OFF 0x0 #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ -#define nCHRG_VBUS_START 0x0 #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ -#define nCHRG_VBUS_END 0x0 #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ -#define nDISCHRG_VBUS_START 0x0 #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ -#define nDISCHRG_VBUS_END 0x0 /* Bit masks for USB_OTG_VBUS_MASK */ #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ -#define nDRIVE_VBUS_ON_ENA 0x0 #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ -#define nDRIVE_VBUS_OFF_ENA 0x0 #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ -#define nCHRG_VBUS_START_ENA 0x0 #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ -#define nCHRG_VBUS_END_ENA 0x0 #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ -#define nDISCHRG_VBUS_START_ENA 0x0 #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ -#define nDISCHRG_VBUS_END_ENA 0x0 /* Bit masks for USB_CSR0 */ #define RXPKTRDY 0x1 /* data packet receive indicator */ -#define nRXPKTRDY 0x0 #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ -#define nTXPKTRDY 0x0 #define STALL_SENT 0x4 /* STALL handshake sent */ -#define nSTALL_SENT 0x0 #define DATAEND 0x8 /* Data end indicator */ -#define nDATAEND 0x0 #define SETUPEND 0x10 /* Setup end */ -#define nSETUPEND 0x0 #define SENDSTALL 0x20 /* Send STALL handshake */ -#define nSENDSTALL 0x0 #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ -#define nSERVICED_RXPKTRDY 0x0 #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ -#define nSERVICED_SETUPEND 0x0 #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ -#define nFLUSHFIFO 0x0 #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ -#define nSTALL_RECEIVED_H 0x0 #define SETUPPKT_H 0x8 /* send Setup token host mode */ -#define nSETUPPKT_H 0x0 #define ERROR_H 0x10 /* timeout error indicator host mode */ -#define nERROR_H 0x0 #define REQPKT_H 0x20 /* Request an IN transaction host mode */ -#define nREQPKT_H 0x0 #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ -#define nSTATUSPKT_H 0x0 #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ -#define nNAK_TIMEOUT_H 0x0 /* Bit masks for USB_COUNT0 */ @@ -3213,37 +2535,21 @@ /* Bit masks for USB_TXCSR */ #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ -#define nTXPKTRDY_T 0x0 #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ -#define nFIFO_NOT_EMPTY_T 0x0 #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ -#define nUNDERRUN_T 0x0 #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ -#define nFLUSHFIFO_T 0x0 #define STALL_SEND_T 0x10 /* issue a Stall handshake */ -#define nSTALL_SEND_T 0x0 #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ -#define nSTALL_SENT_T 0x0 #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_T 0x0 #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ -#define nINCOMPTX_T 0x0 #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_T 0x0 #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ -#define nFORCE_DATATOGGLE_T 0x0 #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_T 0x0 #define ISO_T 0x4000 /* enable Isochronous transfers */ -#define nISO_T 0x0 #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOSET_T 0x0 #define ERROR_TH 0x4 /* error condition host mode */ -#define nERROR_TH 0x0 #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_TH 0x0 #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ -#define nNAK_TIMEOUT_TH 0x0 /* Bit masks for USB_TXCOUNT */ @@ -3252,45 +2558,25 @@ /* Bit masks for USB_RXCSR */ #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ -#define nRXPKTRDY_R 0x0 #define FIFO_FULL_R 0x2 /* FIFO not empty */ -#define nFIFO_FULL_R 0x0 #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ -#define nOVERRUN_R 0x0 #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ -#define nDATAERROR_R 0x0 #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ -#define nFLUSHFIFO_R 0x0 #define STALL_SEND_R 0x20 /* issue a Stall handshake */ -#define nSTALL_SEND_R 0x0 #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ -#define nSTALL_SENT_R 0x0 #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_R 0x0 #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ -#define nINCOMPRX_R 0x0 #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_R 0x0 #define DISNYET_R 0x1000 /* disable Nyet handshakes */ -#define nDISNYET_R 0x0 #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_R 0x0 #define ISO_R 0x4000 /* enable Isochronous transfers */ -#define nISO_R 0x0 #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOCLEAR_R 0x0 #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ -#define nERROR_RH 0x0 #define REQPKT_RH 0x20 /* request an IN transaction host mode */ -#define nREQPKT_RH 0x0 #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_RH 0x0 #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ -#define nINCOMPRX_RH 0x0 #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ -#define nDMAREQMODE_RH 0x0 #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ -#define nAUTOREQ_RH 0x0 /* Bit masks for USB_RXCOUNT */ @@ -3317,35 +2603,22 @@ /* Bit masks for USB_DMA_INTERRUPT */ #define DMA0_INT 0x1 /* DMA0 pending interrupt */ -#define nDMA0_INT 0x0 #define DMA1_INT 0x2 /* DMA1 pending interrupt */ -#define nDMA1_INT 0x0 #define DMA2_INT 0x4 /* DMA2 pending interrupt */ -#define nDMA2_INT 0x0 #define DMA3_INT 0x8 /* DMA3 pending interrupt */ -#define nDMA3_INT 0x0 #define DMA4_INT 0x10 /* DMA4 pending interrupt */ -#define nDMA4_INT 0x0 #define DMA5_INT 0x20 /* DMA5 pending interrupt */ -#define nDMA5_INT 0x0 #define DMA6_INT 0x40 /* DMA6 pending interrupt */ -#define nDMA6_INT 0x0 #define DMA7_INT 0x80 /* DMA7 pending interrupt */ -#define nDMA7_INT 0x0 /* Bit masks for USB_DMAxCONTROL */ #define DMA_ENA 0x1 /* DMA enable */ -#define nDMA_ENA 0x0 #define DIRECTION 0x2 /* direction of DMA transfer */ -#define nDIRECTION 0x0 #define MODE 0x4 /* DMA Bus error */ -#define nMODE 0x0 #define INT_ENA 0x8 /* Interrupt enable */ -#define nINT_ENA 0x0 #define EPNUM 0xf0 /* EP number */ #define BUSERROR 0x100 /* DMA Bus error */ -#define nBUSERROR 0x0 /* Bit masks for USB_DMAxADDRHIGH */ @@ -3366,26 +2639,16 @@ /* Bit masks for HMDMAx_CONTROL */ #define HMDMAEN 0x1 /* Handshake MDMA Enable */ -#define nHMDMAEN 0x0 #define REP 0x2 /* Handshake MDMA Request Polarity */ -#define nREP 0x0 #define UTE 0x8 /* Urgency Threshold Enable */ -#define nUTE 0x0 #define OIE 0x10 /* Overflow Interrupt Enable */ -#define nOIE 0x0 #define BDIE 0x20 /* Block Done Interrupt Enable */ -#define nBDIE 0x0 #define MBDI 0x40 /* Mask Block Done Interrupt */ -#define nMBDI 0x0 #define DRQ 0x300 /* Handshake MDMA Request Type */ #define RBC 0x1000 /* Force Reload of BCOUNT */ -#define nRBC 0x0 #define PS 0x2000 /* Pin Status */ -#define nPS 0x0 #define OI 0x4000 /* Overflow Interrupt Generated */ -#define nOI 0x0 #define BDI 0x8000 /* Block Done Interrupt Generated */ -#define nBDI 0x0 /* ******************************************* */ /* MULTI BIT MACRO ENUMERATIONS */ diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h index a1b200f..2381ac5 100644 --- a/include/asm-blackfin/mach-bf548/defBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h @@ -46,7 +46,7 @@ /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ -#define CHIPID 0xffc00014 +#define CHIPID 0xffc00014 /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */ @@ -1512,231 +1512,144 @@ /* and MULTI BIT READ MACROS */ /* ********************************************************** */ +/* SIC_IMASK Masks */ +#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ +#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ +#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ +#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ + +/* SIC_IWR Masks */ +#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ +#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ +#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ +#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ + /* Bit masks for SIC_IAR0 */ -#define IRQ_PLL_WAKEUP 0x1 /* PLL Wakeup */ -#define nIRQ_PLL_WAKEUP 0x0 +#define PLL_WAKEUP 0x1 /* PLL Wakeup */ /* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */ -#define IRQ_DMA0_ERR 0x2 /* DMA Controller 0 Error */ -#define nIRQ_DMA0_ERR 0x0 -#define IRQ_EPPI0_ERR 0x4 /* EPPI0 Error */ -#define nIRQ_EPPI0_ERR 0x0 -#define IRQ_SPORT0_ERR 0x8 /* SPORT0 Error */ -#define nIRQ_SPORT0_ERR 0x0 -#define IRQ_SPORT1_ERR 0x10 /* SPORT1 Error */ -#define nIRQ_SPORT1_ERR 0x0 -#define IRQ_SPI0_ERR 0x20 /* SPI0 Error */ -#define nIRQ_SPI0_ERR 0x0 -#define IRQ_UART0_ERR 0x40 /* UART0 Error */ -#define nIRQ_UART0_ERR 0x0 -#define IRQ_RTC 0x80 /* Real-Time Clock */ -#define nIRQ_RTC 0x0 -#define IRQ_DMA12 0x100 /* DMA Channel 12 */ -#define nIRQ_DMA12 0x0 -#define IRQ_DMA0 0x200 /* DMA Channel 0 */ -#define nIRQ_DMA0 0x0 -#define IRQ_DMA1 0x400 /* DMA Channel 1 */ -#define nIRQ_DMA1 0x0 -#define IRQ_DMA2 0x800 /* DMA Channel 2 */ -#define nIRQ_DMA2 0x0 -#define IRQ_DMA3 0x1000 /* DMA Channel 3 */ -#define nIRQ_DMA3 0x0 -#define IRQ_DMA4 0x2000 /* DMA Channel 4 */ -#define nIRQ_DMA4 0x0 -#define IRQ_DMA6 0x4000 /* DMA Channel 6 */ -#define nIRQ_DMA6 0x0 -#define IRQ_DMA7 0x8000 /* DMA Channel 7 */ -#define nIRQ_DMA7 0x0 -#define IRQ_PINT0 0x80000 /* Pin Interrupt 0 */ -#define nIRQ_PINT0 0x0 -#define IRQ_PINT1 0x100000 /* Pin Interrupt 1 */ -#define nIRQ_PINT1 0x0 -#define IRQ_MDMA0 0x200000 /* Memory DMA Stream 0 */ -#define nIRQ_MDMA0 0x0 -#define IRQ_MDMA1 0x400000 /* Memory DMA Stream 1 */ -#define nIRQ_MDMA1 0x0 -#define IRQ_WDOG 0x800000 /* Watchdog Timer */ -#define nIRQ_WDOG 0x0 -#define IRQ_DMA1_ERR 0x1000000 /* DMA Controller 1 Error */ -#define nIRQ_DMA1_ERR 0x0 -#define IRQ_SPORT2_ERR 0x2000000 /* SPORT2 Error */ -#define nIRQ_SPORT2_ERR 0x0 -#define IRQ_SPORT3_ERR 0x4000000 /* SPORT3 Error */ -#define nIRQ_SPORT3_ERR 0x0 -#define IRQ_MXVR_SD 0x8000000 /* MXVR Synchronous Data */ -#define nIRQ_MXVR_SD 0x0 -#define IRQ_SPI1_ERR 0x10000000 /* SPI1 Error */ -#define nIRQ_SPI1_ERR 0x0 -#define IRQ_SPI2_ERR 0x20000000 /* SPI2 Error */ -#define nIRQ_SPI2_ERR 0x0 -#define IRQ_UART1_ERR 0x40000000 /* UART1 Error */ -#define nIRQ_UART1_ERR 0x0 -#define IRQ_UART2_ERR 0x80000000 /* UART2 Error */ -#define nIRQ_UART2_ERR 0x0 +#define DMA0_ERR 0x2 /* DMA Controller 0 Error */ +#define EPPI0_ERR 0x4 /* EPPI0 Error */ +#define SPORT0_ERR 0x8 /* SPORT0 Error */ +#define SPORT1_ERR 0x10 /* SPORT1 Error */ +#define SPI0_ERR 0x20 /* SPI0 Error */ +#define UART0_ERR 0x40 /* UART0 Error */ +#define RTC 0x80 /* Real-Time Clock */ +#define DMA12 0x100 /* DMA Channel 12 */ +#define DMA0 0x200 /* DMA Channel 0 */ +#define DMA1 0x400 /* DMA Channel 1 */ +#define DMA2 0x800 /* DMA Channel 2 */ +#define DMA3 0x1000 /* DMA Channel 3 */ +#define DMA4 0x2000 /* DMA Channel 4 */ +#define DMA6 0x4000 /* DMA Channel 6 */ +#define DMA7 0x8000 /* DMA Channel 7 */ +#define PINT0 0x80000 /* Pin Interrupt 0 */ +#define PINT1 0x100000 /* Pin Interrupt 1 */ +#define MDMA0 0x200000 /* Memory DMA Stream 0 */ +#define MDMA1 0x400000 /* Memory DMA Stream 1 */ +#define WDOG 0x800000 /* Watchdog Timer */ +#define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */ +#define SPORT2_ERR 0x2000000 /* SPORT2 Error */ +#define SPORT3_ERR 0x4000000 /* SPORT3 Error */ +#define MXVR_SD 0x8000000 /* MXVR Synchronous Data */ +#define SPI1_ERR 0x10000000 /* SPI1 Error */ +#define SPI2_ERR 0x20000000 /* SPI2 Error */ +#define UART1_ERR 0x40000000 /* UART1 Error */ +#define UART2_ERR 0x80000000 /* UART2 Error */ /* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */ -#define IRQ_CAN0_ERR 0x1 /* CAN0 Error */ -#define nIRQ_CAN0_ERR 0x0 -#define IRQ_DMA18 0x2 /* DMA Channel 18 */ -#define nIRQ_DMA18 0x0 -#define IRQ_DMA19 0x4 /* DMA Channel 19 */ -#define nIRQ_DMA19 0x0 -#define IRQ_DMA20 0x8 /* DMA Channel 20 */ -#define nIRQ_DMA20 0x0 -#define IRQ_DMA21 0x10 /* DMA Channel 21 */ -#define nIRQ_DMA21 0x0 -#define IRQ_DMA13 0x20 /* DMA Channel 13 */ -#define nIRQ_DMA13 0x0 -#define IRQ_DMA14 0x40 /* DMA Channel 14 */ -#define nIRQ_DMA14 0x0 -#define IRQ_DMA5 0x80 /* DMA Channel 5 */ -#define nIRQ_DMA5 0x0 -#define IRQ_DMA23 0x100 /* DMA Channel 23 */ -#define nIRQ_DMA23 0x0 -#define IRQ_DMA8 0x200 /* DMA Channel 8 */ -#define nIRQ_DMA8 0x0 -#define IRQ_DMA9 0x400 /* DMA Channel 9 */ -#define nIRQ_DMA9 0x0 -#define IRQ_DMA10 0x800 /* DMA Channel 10 */ -#define nIRQ_DMA10 0x0 -#define IRQ_DMA11 0x1000 /* DMA Channel 11 */ -#define nIRQ_DMA11 0x0 -#define IRQ_TWI0 0x2000 /* TWI0 */ -#define nIRQ_TWI0 0x0 -#define IRQ_TWI1 0x4000 /* TWI1 */ -#define nIRQ_TWI1 0x0 -#define IRQ_CAN0_RX 0x8000 /* CAN0 Receive */ -#define nIRQ_CAN0_RX 0x0 -#define IRQ_CAN0_TX 0x10000 /* CAN0 Transmit */ -#define nIRQ_CAN0_TX 0x0 -#define IRQ_MDMA2 0x20000 /* Memory DMA Stream 0 */ -#define nIRQ_MDMA2 0x0 -#define IRQ_MDMA3 0x40000 /* Memory DMA Stream 1 */ -#define nIRQ_MDMA3 0x0 -#define IRQ_MXVR_STAT 0x80000 /* MXVR Status */ -#define nIRQ_MXVR_STAT 0x0 -#define IRQ_MXVR_CM 0x100000 /* MXVR Control Message */ -#define nIRQ_MXVR_CM 0x0 -#define IRQ_MXVR_AP 0x200000 /* MXVR Asynchronous Packet */ -#define nIRQ_MXVR_AP 0x0 -#define IRQ_EPPI1_ERR 0x400000 /* EPPI1 Error */ -#define nIRQ_EPPI1_ERR 0x0 -#define IRQ_EPPI2_ERR 0x800000 /* EPPI2 Error */ -#define nIRQ_EPPI2_ERR 0x0 -#define IRQ_UART3_ERR 0x1000000 /* UART3 Error */ -#define nIRQ_UART3_ERR 0x0 -#define IRQ_HOST_ERR 0x2000000 /* Host DMA Port Error */ -#define nIRQ_HOST_ERR 0x0 -#define IRQ_USB_ERR 0x4000000 /* USB Error */ -#define nIRQ_USB_ERR 0x0 -#define IRQ_PIXC_ERR 0x8000000 /* Pixel Compositor Error */ -#define nIRQ_PIXC_ERR 0x0 -#define IRQ_NFC_ERR 0x10000000 /* Nand Flash Controller Error */ -#define nIRQ_NFC_ERR 0x0 -#define IRQ_ATAPI_ERR 0x20000000 /* ATAPI Error */ -#define nIRQ_ATAPI_ERR 0x0 -#define IRQ_CAN1_ERR 0x40000000 /* CAN1 Error */ -#define nIRQ_CAN1_ERR 0x0 -#define IRQ_DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */ -#define nIRQ_DMAR0_ERR 0x0 -#define IRQ_DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */ -#define nIRQ_DMAR1_ERR 0x0 -#define IRQ_DMAR0 0x80000000 /* DMAR0 Block */ -#define nIRQ_DMAR0 0x0 -#define IRQ_DMAR1 0x80000000 /* DMAR1 Block */ -#define nIRQ_DMAR1 0x0 +#define CAN0_ERR 0x1 /* CAN0 Error */ +#define DMA18 0x2 /* DMA Channel 18 */ +#define DMA19 0x4 /* DMA Channel 19 */ +#define DMA20 0x8 /* DMA Channel 20 */ +#define DMA21 0x10 /* DMA Channel 21 */ +#define DMA13 0x20 /* DMA Channel 13 */ +#define DMA14 0x40 /* DMA Channel 14 */ +#define DMA5 0x80 /* DMA Channel 5 */ +#define DMA23 0x100 /* DMA Channel 23 */ +#define DMA8 0x200 /* DMA Channel 8 */ +#define DMA9 0x400 /* DMA Channel 9 */ +#define DMA10 0x800 /* DMA Channel 10 */ +#define DMA11 0x1000 /* DMA Channel 11 */ +#define TWI0 0x2000 /* TWI0 */ +#define TWI1 0x4000 /* TWI1 */ +#define CAN0_RX 0x8000 /* CAN0 Receive */ +#define CAN0_TX 0x10000 /* CAN0 Transmit */ +#define MDMA2 0x20000 /* Memory DMA Stream 0 */ +#define MDMA3 0x40000 /* Memory DMA Stream 1 */ +#define MXVR_STAT 0x80000 /* MXVR Status */ +#define MXVR_CM 0x100000 /* MXVR Control Message */ +#define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */ +#define EPPI1_ERR 0x400000 /* EPPI1 Error */ +#define EPPI2_ERR 0x800000 /* EPPI2 Error */ +#define UART3_ERR 0x1000000 /* UART3 Error */ +#define HOST_ERR 0x2000000 /* Host DMA Port Error */ +#define USB_ERR 0x4000000 /* USB Error */ +#define PIXC_ERR 0x8000000 /* Pixel Compositor Error */ +#define NFC_ERR 0x10000000 /* Nand Flash Controller Error */ +#define ATAPI_ERR 0x20000000 /* ATAPI Error */ +#define CAN1_ERR 0x40000000 /* CAN1 Error */ +#define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */ +#define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */ +#define DMAR0 0x80000000 /* DMAR0 Block */ +#define DMAR1 0x80000000 /* DMAR1 Block */ /* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */ -#define IRQ_DMA15 0x1 /* DMA Channel 15 */ -#define nIRQ_DMA15 0x0 -#define IRQ_DMA16 0x2 /* DMA Channel 16 */ -#define nIRQ_DMA16 0x0 -#define IRQ_DMA17 0x4 /* DMA Channel 17 */ -#define nIRQ_DMA17 0x0 -#define IRQ_DMA22 0x8 /* DMA Channel 22 */ -#define nIRQ_DMA22 0x0 -#define IRQ_CNT 0x10 /* Counter */ -#define nIRQ_CNT 0x0 -#define IRQ_KEY 0x20 /* Keypad */ -#define nIRQ_KEY 0x0 -#define IRQ_CAN1_RX 0x40 /* CAN1 Receive */ -#define nIRQ_CAN1_RX 0x0 -#define IRQ_CAN1_TX 0x80 /* CAN1 Transmit */ -#define nIRQ_CAN1_TX 0x0 -#define IRQ_SDH_MASK0 0x100 /* SDH Mask 0 */ -#define nIRQ_SDH_MASK0 0x0 -#define IRQ_SDH_MASK1 0x200 /* SDH Mask 1 */ -#define nIRQ_SDH_MASK1 0x0 -#define IRQ_USB_EINT 0x400 /* USB Exception */ -#define nIRQ_USB_EINT 0x0 -#define IRQ_USB_INT0 0x800 /* USB Interrupt 0 */ -#define nIRQ_USB_INT0 0x0 -#define IRQ_USB_INT1 0x1000 /* USB Interrupt 1 */ -#define nIRQ_USB_INT1 0x0 -#define IRQ_USB_INT2 0x2000 /* USB Interrupt 2 */ -#define nIRQ_USB_INT2 0x0 -#define IRQ_USB_DMAINT 0x4000 /* USB DMA */ -#define nIRQ_USB_DMAINT 0x0 -#define IRQ_OTPSEC 0x8000 /* OTP Access Complete */ -#define nIRQ_OTPSEC 0x0 -#define IRQ_TIMER0 0x400000 /* Timer 0 */ -#define nIRQ_TIMER0 0x0 -#define IRQ_TIMER1 0x800000 /* Timer 1 */ -#define nIRQ_TIMER1 0x0 -#define IRQ_TIMER2 0x1000000 /* Timer 2 */ -#define nIRQ_TIMER2 0x0 -#define IRQ_TIMER3 0x2000000 /* Timer 3 */ -#define nIRQ_TIMER3 0x0 -#define IRQ_TIMER4 0x4000000 /* Timer 4 */ -#define nIRQ_TIMER4 0x0 -#define IRQ_TIMER5 0x8000000 /* Timer 5 */ -#define nIRQ_TIMER5 0x0 -#define IRQ_TIMER6 0x10000000 /* Timer 6 */ -#define nIRQ_TIMER6 0x0 -#define IRQ_TIMER7 0x20000000 /* Timer 7 */ -#define nIRQ_TIMER7 0x0 -#define IRQ_PINT2 0x40000000 /* Pin Interrupt 2 */ -#define nIRQ_PINT2 0x0 -#define IRQ_PINT3 0x80000000 /* Pin Interrupt 3 */ -#define nIRQ_PINT3 0x0 +#define DMA15 0x1 /* DMA Channel 15 */ +#define DMA16 0x2 /* DMA Channel 16 */ +#define DMA17 0x4 /* DMA Channel 17 */ +#define DMA22 0x8 /* DMA Channel 22 */ +#define CNT 0x10 /* Counter */ +#define KEY 0x20 /* Keypad */ +#define CAN1_RX 0x40 /* CAN1 Receive */ +#define CAN1_TX 0x80 /* CAN1 Transmit */ +#define SDH_INT_MASK0 0x100 /* SDH Mask 0 */ +#define SDH_INT_MASK1 0x200 /* SDH Mask 1 */ +#define USB_EINT 0x400 /* USB Exception */ +#define USB_INT0 0x800 /* USB Interrupt 0 */ +#define USB_INT1 0x1000 /* USB Interrupt 1 */ +#define USB_INT2 0x2000 /* USB Interrupt 2 */ +#define USB_DMAINT 0x4000 /* USB DMA */ +#define OTPSEC 0x8000 /* OTP Access Complete */ +#define TIMER0 0x400000 /* Timer 0 */ +#define TIMER1 0x800000 /* Timer 1 */ +#define TIMER2 0x1000000 /* Timer 2 */ +#define TIMER3 0x2000000 /* Timer 3 */ +#define TIMER4 0x4000000 /* Timer 4 */ +#define TIMER5 0x8000000 /* Timer 5 */ +#define TIMER6 0x10000000 /* Timer 6 */ +#define TIMER7 0x20000000 /* Timer 7 */ +#define PINT2 0x40000000 /* Pin Interrupt 2 */ +#define PINT3 0x80000000 /* Pin Interrupt 3 */ /* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */ #define DMAEN 0x1 /* DMA Channel Enable */ -#define nDMAEN 0x0 #define WNR 0x2 /* DMA Direction */ -#define nWNR 0x0 -#define WDSIZE 0xc /* Transfer Word Size */ +#define WDSIZE_8 0x0 /* Transfer Word Size = 8 */ +#define WDSIZE_16 0x4 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x8 /* Transfer Word Size = 32 */ #define DMA2D 0x10 /* DMA Mode */ -#define nDMA2D 0x0 #define RESTART 0x20 /* Work Unit Transitions */ -#define nRESTART 0x0 #define DI_SEL 0x40 /* Data Interrupt Timing Select */ -#define nDI_SEL 0x0 #define DI_EN 0x80 /* Data Interrupt Enable */ -#define nDI_EN 0x0 #define NDSIZE 0xf00 /* Flex Descriptor Size */ #define DMAFLOW 0xf000 /* Next Operation */ /* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ #define DMA_DONE 0x1 /* DMA Completion Interrupt Status */ -#define nDMA_DONE 0x0 #define DMA_ERR 0x2 /* DMA Error Interrupt Status */ -#define nDMA_ERR 0x0 #define DFETCH 0x4 /* DMA Descriptor Fetch */ -#define nDFETCH 0x0 #define DMA_RUN 0x8 /* DMA Channel Running */ -#define nDMA_RUN 0x0 /* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ #define CTYPE 0x40 /* DMA Channel Type */ -#define nCTYPE 0x0 #define PMAP 0xf000 /* Peripheral Mapped To This Channel */ /* Bit masks for DMACx_TCPER */ @@ -1756,29 +1669,28 @@ /* Bit masks for DMAC1_PERIMUX */ #define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */ -#define nPMUXSDH 0x0 -/* Bit masks for EBIU_AMGCTL */ +/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ +/* EBIU_AMGCTL Masks */ +#define AMCKEN 0x0001 /* Enable CLKOUT */ +#define AMBEN_NONE 0x0000 /* All Banks Disabled */ +#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ +#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ +#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ +#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ -#define AMCKEN 0x1 /* Async Memory Enable */ -#define nAMCKEN 0x0 -#define AMBEN 0xe /* Async bank enable */ /* Bit masks for EBIU_AMBCTL0 */ #define B0RDYEN 0x1 /* Bank 0 ARDY Enable */ -#define nB0RDYEN 0x0 #define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */ -#define nB0RDYPOL 0x0 #define B0TT 0xc /* Bank 0 transition time */ #define B0ST 0x30 /* Bank 0 Setup time */ #define B0HT 0xc0 /* Bank 0 Hold time */ #define B0RAT 0xf00 /* Bank 0 Read access time */ #define B0WAT 0xf000 /* Bank 0 write access time */ #define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */ -#define nB1RDYEN 0x0 #define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */ -#define nB1RDYPOL 0x0 #define B1TT 0xc0000 /* Bank 1 transition time */ #define B1ST 0x300000 /* Bank 1 Setup time */ #define B1HT 0xc00000 /* Bank 1 Hold time */ @@ -1788,18 +1700,14 @@ /* Bit masks for EBIU_AMBCTL1 */ #define B2RDYEN 0x1 /* Bank 2 ARDY Enable */ -#define nB2RDYEN 0x0 #define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */ -#define nB2RDYPOL 0x0 #define B2TT 0xc /* Bank 2 transition time */ #define B2ST 0x30 /* Bank 2 Setup time */ #define B2HT 0xc0 /* Bank 2 Hold time */ #define B2RAT 0xf00 /* Bank 2 Read access time */ #define B2WAT 0xf000 /* Bank 2 write access time */ #define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */ -#define nB3RDYEN 0x0 #define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */ -#define nB3RDYPOL 0x0 #define B3TT 0xc0000 /* Bank 3 transition time */ #define B3ST 0x300000 /* Bank 3 Setup time */ #define B3HT 0xc00000 /* Bank 3 Hold time */ @@ -1823,19 +1731,15 @@ /* Bit masks for EBIU_FCTL */ #define TESTSETLOCK 0x1 /* Test set lock */ -#define nTESTSETLOCK 0x0 #define BCLK 0x6 /* Burst clock frequency */ #define PGWS 0x38 /* Page wait states */ #define PGSZ 0x40 /* Page size */ -#define nPGSZ 0x0 #define RDDL 0x380 /* Read data delay */ /* Bit masks for EBIU_ARBSTAT */ #define ARBSTAT 0x1 /* Arbitration status */ -#define nARBSTAT 0x0 #define BGSTAT 0x2 /* Bus grant status */ -#define nBGSTAT 0x0 /* Bit masks for EBIU_DDRCTL0 */ @@ -1861,9 +1765,7 @@ #define BURSTLENGTH 0x7 /* Burst length */ #define CASLATENCY 0x70 /* CAS latency */ #define DLLRESET 0x100 /* DLL Reset */ -#define nDLLRESET 0x0 #define REGE 0x1000 /* Register mode enable */ -#define nREGE 0x0 /* Bit masks for EBIU_DDRCTL3 */ @@ -1876,30 +1778,19 @@ #define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */ #define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */ #define DEB1_URGENT 0x1000 /* DEB1 Urgent */ -#define nDEB1_URGENT 0x0 #define DEB2_URGENT 0x2000 /* DEB2 Urgent */ -#define nDEB2_URGENT 0x0 #define DEB3_URGENT 0x4000 /* DEB3 Urgent */ -#define nDEB3_URGENT 0x0 /* Bit masks for EBIU_ERRMST */ #define DEB1_ERROR 0x1 /* DEB1 Error */ -#define nDEB1_ERROR 0x0 #define DEB2_ERROR 0x2 /* DEB2 Error */ -#define nDEB2_ERROR 0x0 #define DEB3_ERROR 0x4 /* DEB3 Error */ -#define nDEB3_ERROR 0x0 #define CORE_ERROR 0x8 /* Core error */ -#define nCORE_ERROR 0x0 #define DEB_MERROR 0x10 /* DEB1 Error (2nd) */ -#define nDEB_MERROR 0x0 #define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */ -#define nDEB2_MERROR 0x0 #define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */ -#define nDEB3_MERROR 0x0 #define CORE_MERROR 0x80 /* Core Error (2nd) */ -#define nCORE_MERROR 0x0 /* Bit masks for EBIU_ERRADD */ @@ -1908,15 +1799,10 @@ /* Bit masks for EBIU_RSTCTL */ #define DDRSRESET 0x1 /* DDR soft reset */ -#define nDDRSRESET 0x0 #define PFTCHSRESET 0x4 /* DDR prefetch reset */ -#define nPFTCHSRESET 0x0 #define SRREQ 0x8 /* Self-refresh request */ -#define nSRREQ 0x0 #define SRACK 0x10 /* Self-refresh acknowledge */ -#define nSRACK 0x0 #define MDDRENABLE 0x20 /* Mobile DDR enable */ -#define nMDDRENABLE 0x0 /* Bit masks for EBIU_DDRBRC0 */ @@ -2013,136 +1899,74 @@ /* Bit masks for EBIU_DDRMCEN */ #define B0WCENABLE 0x1 /* Bank 0 write count enable */ -#define nB0WCENABLE 0x0 #define B1WCENABLE 0x2 /* Bank 1 write count enable */ -#define nB1WCENABLE 0x0 #define B2WCENABLE 0x4 /* Bank 2 write count enable */ -#define nB2WCENABLE 0x0 #define B3WCENABLE 0x8 /* Bank 3 write count enable */ -#define nB3WCENABLE 0x0 #define B4WCENABLE 0x10 /* Bank 4 write count enable */ -#define nB4WCENABLE 0x0 #define B5WCENABLE 0x20 /* Bank 5 write count enable */ -#define nB5WCENABLE 0x0 #define B6WCENABLE 0x40 /* Bank 6 write count enable */ -#define nB6WCENABLE 0x0 #define B7WCENABLE 0x80 /* Bank 7 write count enable */ -#define nB7WCENABLE 0x0 #define B0RCENABLE 0x100 /* Bank 0 read count enable */ -#define nB0RCENABLE 0x0 #define B1RCENABLE 0x200 /* Bank 1 read count enable */ -#define nB1RCENABLE 0x0 #define B2RCENABLE 0x400 /* Bank 2 read count enable */ -#define nB2RCENABLE 0x0 #define B3RCENABLE 0x800 /* Bank 3 read count enable */ -#define nB3RCENABLE 0x0 #define B4RCENABLE 0x1000 /* Bank 4 read count enable */ -#define nB4RCENABLE 0x0 #define B5RCENABLE 0x2000 /* Bank 5 read count enable */ -#define nB5RCENABLE 0x0 #define B6RCENABLE 0x4000 /* Bank 6 read count enable */ -#define nB6RCENABLE 0x0 #define B7RCENABLE 0x8000 /* Bank 7 read count enable */ -#define nB7RCENABLE 0x0 #define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */ -#define nROWACTCENABLE 0x0 #define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */ -#define nRWTCENABLE 0x0 #define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */ -#define nARCENABLE 0x0 #define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */ -#define nGC0ENABLE 0x0 #define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */ -#define nGC1ENABLE 0x0 #define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */ -#define nGC2ENABLE 0x0 #define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */ -#define nGC3ENABLE 0x0 #define GCCONTROL 0x3000000 /* DDR Grant Count Control */ /* Bit masks for EBIU_DDRMCCL */ #define CB0WCOUNT 0x1 /* Clear write count 0 */ -#define nCB0WCOUNT 0x0 #define CB1WCOUNT 0x2 /* Clear write count 1 */ -#define nCB1WCOUNT 0x0 #define CB2WCOUNT 0x4 /* Clear write count 2 */ -#define nCB2WCOUNT 0x0 #define CB3WCOUNT 0x8 /* Clear write count 3 */ -#define nCB3WCOUNT 0x0 #define CB4WCOUNT 0x10 /* Clear write count 4 */ -#define nCB4WCOUNT 0x0 #define CB5WCOUNT 0x20 /* Clear write count 5 */ -#define nCB5WCOUNT 0x0 #define CB6WCOUNT 0x40 /* Clear write count 6 */ -#define nCB6WCOUNT 0x0 #define CB7WCOUNT 0x80 /* Clear write count 7 */ -#define nCB7WCOUNT 0x0 #define CBRCOUNT 0x100 /* Clear read count 0 */ -#define nCBRCOUNT 0x0 #define CB1RCOUNT 0x200 /* Clear read count 1 */ -#define nCB1RCOUNT 0x0 #define CB2RCOUNT 0x400 /* Clear read count 2 */ -#define nCB2RCOUNT 0x0 #define CB3RCOUNT 0x800 /* Clear read count 3 */ -#define nCB3RCOUNT 0x0 #define CB4RCOUNT 0x1000 /* Clear read count 4 */ -#define nCB4RCOUNT 0x0 #define CB5RCOUNT 0x2000 /* Clear read count 5 */ -#define nCB5RCOUNT 0x0 #define CB6RCOUNT 0x4000 /* Clear read count 6 */ -#define nCB6RCOUNT 0x0 #define CB7RCOUNT 0x8000 /* Clear read count 7 */ -#define nCB7RCOUNT 0x0 #define CRACOUNT 0x10000 /* Clear row activation count */ -#define nCRACOUNT 0x0 #define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */ -#define nCRWTACOUNT 0x0 #define CARCOUNT 0x40000 /* Clear auto-refresh count */ -#define nCARCOUNT 0x0 #define CG0COUNT 0x100000 /* Clear grant count 0 */ -#define nCG0COUNT 0x0 #define CG1COUNT 0x200000 /* Clear grant count 1 */ -#define nCG1COUNT 0x0 #define CG2COUNT 0x400000 /* Clear grant count 2 */ -#define nCG2COUNT 0x0 #define CG3COUNT 0x800000 /* Clear grant count 3 */ -#define nCG3COUNT 0x0 /* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */ #define Px0 0x1 /* GPIO 0 */ -#define nPx0 0x0 #define Px1 0x2 /* GPIO 1 */ -#define nPx1 0x0 #define Px2 0x4 /* GPIO 2 */ -#define nPx2 0x0 #define Px3 0x8 /* GPIO 3 */ -#define nPx3 0x0 #define Px4 0x10 /* GPIO 4 */ -#define nPx4 0x0 #define Px5 0x20 /* GPIO 5 */ -#define nPx5 0x0 #define Px6 0x40 /* GPIO 6 */ -#define nPx6 0x0 #define Px7 0x80 /* GPIO 7 */ -#define nPx7 0x0 #define Px8 0x100 /* GPIO 8 */ -#define nPx8 0x0 #define Px9 0x200 /* GPIO 9 */ -#define nPx9 0x0 #define Px10 0x400 /* GPIO 10 */ -#define nPx10 0x0 #define Px11 0x800 /* GPIO 11 */ -#define nPx11 0x0 #define Px12 0x1000 /* GPIO 12 */ -#define nPx12 0x0 #define Px13 0x2000 /* GPIO 13 */ -#define nPx13 0x0 #define Px14 0x4000 /* GPIO 14 */ -#define nPx14 0x0 #define Px15 0x8000 /* GPIO 15 */ -#define nPx15 0x0 /* Bit masks for PORTA_MUX - PORTJ_MUX */ @@ -2167,223 +1991,129 @@ /* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */ #define IB0 0x1 /* Interrupt Bit 0 */ -#define nIB0 0x0 #define IB1 0x2 /* Interrupt Bit 1 */ -#define nIB1 0x0 #define IB2 0x4 /* Interrupt Bit 2 */ -#define nIB2 0x0 #define IB3 0x8 /* Interrupt Bit 3 */ -#define nIB3 0x0 #define IB4 0x10 /* Interrupt Bit 4 */ -#define nIB4 0x0 #define IB5 0x20 /* Interrupt Bit 5 */ -#define nIB5 0x0 #define IB6 0x40 /* Interrupt Bit 6 */ -#define nIB6 0x0 #define IB7 0x80 /* Interrupt Bit 7 */ -#define nIB7 0x0 #define IB8 0x100 /* Interrupt Bit 8 */ -#define nIB8 0x0 #define IB9 0x200 /* Interrupt Bit 9 */ -#define nIB9 0x0 #define IB10 0x400 /* Interrupt Bit 10 */ -#define nIB10 0x0 #define IB11 0x800 /* Interrupt Bit 11 */ -#define nIB11 0x0 #define IB12 0x1000 /* Interrupt Bit 12 */ -#define nIB12 0x0 #define IB13 0x2000 /* Interrupt Bit 13 */ -#define nIB13 0x0 #define IB14 0x4000 /* Interrupt Bit 14 */ -#define nIB14 0x0 #define IB15 0x8000 /* Interrupt Bit 15 */ -#define nIB15 0x0 /* Bit masks for TIMERx_CONFIG */ #define TMODE 0x3 /* Timer Mode */ #define PULSE_HI 0x4 /* Pulse Polarity */ -#define nPULSE_HI 0x0 #define PERIOD_CNT 0x8 /* Period Count */ -#define nPERIOD_CNT 0x0 #define IRQ_ENA 0x10 /* Interrupt Request Enable */ -#define nIRQ_ENA 0x0 #define TIN_SEL 0x20 /* Timer Input Select */ -#define nTIN_SEL 0x0 #define OUT_DIS 0x40 /* Output Pad Disable */ -#define nOUT_DIS 0x0 #define CLK_SEL 0x80 /* Timer Clock Select */ -#define nCLK_SEL 0x0 #define TOGGLE_HI 0x100 /* Toggle Mode */ -#define nTOGGLE_HI 0x0 #define EMU_RUN 0x200 /* Emulation Behavior Select */ -#define nEMU_RUN 0x0 #define ERR_TYP 0xc000 /* Error Type */ /* Bit masks for TIMER_ENABLE0 */ #define TIMEN0 0x1 /* Timer 0 Enable */ -#define nTIMEN0 0x0 #define TIMEN1 0x2 /* Timer 1 Enable */ -#define nTIMEN1 0x0 #define TIMEN2 0x4 /* Timer 2 Enable */ -#define nTIMEN2 0x0 #define TIMEN3 0x8 /* Timer 3 Enable */ -#define nTIMEN3 0x0 #define TIMEN4 0x10 /* Timer 4 Enable */ -#define nTIMEN4 0x0 #define TIMEN5 0x20 /* Timer 5 Enable */ -#define nTIMEN5 0x0 #define TIMEN6 0x40 /* Timer 6 Enable */ -#define nTIMEN6 0x0 #define TIMEN7 0x80 /* Timer 7 Enable */ -#define nTIMEN7 0x0 /* Bit masks for TIMER_DISABLE0 */ #define TIMDIS0 0x1 /* Timer 0 Disable */ -#define nTIMDIS0 0x0 #define TIMDIS1 0x2 /* Timer 1 Disable */ -#define nTIMDIS1 0x0 #define TIMDIS2 0x4 /* Timer 2 Disable */ -#define nTIMDIS2 0x0 #define TIMDIS3 0x8 /* Timer 3 Disable */ -#define nTIMDIS3 0x0 #define TIMDIS4 0x10 /* Timer 4 Disable */ -#define nTIMDIS4 0x0 #define TIMDIS5 0x20 /* Timer 5 Disable */ -#define nTIMDIS5 0x0 #define TIMDIS6 0x40 /* Timer 6 Disable */ -#define nTIMDIS6 0x0 #define TIMDIS7 0x80 /* Timer 7 Disable */ -#define nTIMDIS7 0x0 /* Bit masks for TIMER_STATUS0 */ #define TIMIL0 0x1 /* Timer 0 Interrupt */ -#define nTIMIL0 0x0 #define TIMIL1 0x2 /* Timer 1 Interrupt */ -#define nTIMIL1 0x0 #define TIMIL2 0x4 /* Timer 2 Interrupt */ -#define nTIMIL2 0x0 #define TIMIL3 0x8 /* Timer 3 Interrupt */ -#define nTIMIL3 0x0 #define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */ -#define nTOVF_ERR0 0x0 #define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */ -#define nTOVF_ERR1 0x0 #define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */ -#define nTOVF_ERR2 0x0 #define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */ -#define nTOVF_ERR3 0x0 #define TRUN0 0x1000 /* Timer 0 Slave Enable Status */ -#define nTRUN0 0x0 #define TRUN1 0x2000 /* Timer 1 Slave Enable Status */ -#define nTRUN1 0x0 #define TRUN2 0x4000 /* Timer 2 Slave Enable Status */ -#define nTRUN2 0x0 #define TRUN3 0x8000 /* Timer 3 Slave Enable Status */ -#define nTRUN3 0x0 #define TIMIL4 0x10000 /* Timer 4 Interrupt */ -#define nTIMIL4 0x0 #define TIMIL5 0x20000 /* Timer 5 Interrupt */ -#define nTIMIL5 0x0 #define TIMIL6 0x40000 /* Timer 6 Interrupt */ -#define nTIMIL6 0x0 #define TIMIL7 0x80000 /* Timer 7 Interrupt */ -#define nTIMIL7 0x0 #define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */ -#define nTOVF_ERR4 0x0 #define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */ -#define nTOVF_ERR5 0x0 #define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */ -#define nTOVF_ERR6 0x0 #define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */ -#define nTOVF_ERR7 0x0 #define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ -#define nTRUN4 0x0 #define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ -#define nTRUN5 0x0 #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ -#define nTRUN6 0x0 #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ -#define nTRUN7 0x0 /* Bit masks for WDOG_CTL */ #define WDEV 0x6 /* Watchdog Event */ #define WDEN 0xff0 /* Watchdog Enable */ #define WDRO 0x8000 /* Watchdog Rolled Over */ -#define nWDRO 0x0 /* Bit masks for CNT_CONFIG */ #define CNTE 0x1 /* Counter Enable */ -#define nCNTE 0x0 #define DEBE 0x2 /* Debounce Enable */ -#define nDEBE 0x0 #define CDGINV 0x10 /* CDG Pin Polarity Invert */ -#define nCDGINV 0x0 #define CUDINV 0x20 /* CUD Pin Polarity Invert */ -#define nCUDINV 0x0 #define CZMINV 0x40 /* CZM Pin Polarity Invert */ -#define nCZMINV 0x0 #define CNTMODE 0x700 /* Counter Operating Mode */ #define ZMZC 0x800 /* CZM Zeroes Counter Enable */ -#define nZMZC 0x0 #define BNDMODE 0x3000 /* Boundary register Mode */ #define INPDIS 0x8000 /* CUG and CDG Input Disable */ -#define nINPDIS 0x0 /* Bit masks for CNT_IMASK */ #define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ -#define nICIE 0x0 #define UCIE 0x2 /* Up count Interrupt Enable */ -#define nUCIE 0x0 #define DCIE 0x4 /* Down count Interrupt Enable */ -#define nDCIE 0x0 #define MINCIE 0x8 /* Min Count Interrupt Enable */ -#define nMINCIE 0x0 #define MAXCIE 0x10 /* Max Count Interrupt Enable */ -#define nMAXCIE 0x0 #define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ -#define nCOV31IE 0x0 #define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ -#define nCOV15IE 0x0 #define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ -#define nCZEROIE 0x0 #define CZMIE 0x100 /* CZM Pin Interrupt Enable */ -#define nCZMIE 0x0 #define CZMEIE 0x200 /* CZM Error Interrupt Enable */ -#define nCZMEIE 0x0 #define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ -#define nCZMZIE 0x0 /* Bit masks for CNT_STATUS */ #define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ -#define nICII 0x0 #define UCII 0x2 /* Up count Interrupt Identifier */ -#define nUCII 0x0 #define DCII 0x4 /* Down count Interrupt Identifier */ -#define nDCII 0x0 #define MINCII 0x8 /* Min Count Interrupt Identifier */ -#define nMINCII 0x0 #define MAXCII 0x10 /* Max Count Interrupt Identifier */ -#define nMAXCII 0x0 #define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ -#define nCOV31II 0x0 #define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ -#define nCOV15II 0x0 #define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ -#define nCZEROII 0x0 #define CZMII 0x100 /* CZM Pin Interrupt Identifier */ -#define nCZMII 0x0 #define CZMEII 0x200 /* CZM Error Interrupt Identifier */ -#define nCZMEII 0x0 #define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ -#define nCZMZII 0x0 /* Bit masks for CNT_COMMAND */ @@ -2391,7 +2121,6 @@ #define W1LMIN 0xf0 /* Load Min Register */ #define W1LMAX 0xf00 /* Load Max Register */ #define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ -#define nW1ZMONCE 0x0 /* Bit masks for CNT_DEBOUNCE */ @@ -2407,42 +2136,25 @@ /* Bit masks for RTC_ICTL */ #define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */ -#define nSTOPWATCH_INTERRUPT_ENABLE 0x0 #define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */ -#define nALARM_INTERRUPT_ENABLE 0x0 #define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */ -#define nSECONDS_INTERRUPT_ENABLE 0x0 #define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */ -#define nMINUTES_INTERRUPT_ENABLE 0x0 #define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */ -#define nHOURS_INTERRUPT_ENABLE 0x0 #define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */ -#define nTWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x0 #define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */ -#define nDAY_ALARM_INTERRUPT_ENABLE 0x0 #define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */ -#define nWRITE_COMPLETE_INTERRUPT_ENABLE 0x0 /* Bit masks for RTC_ISTAT */ #define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */ -#define nSTOPWATCH_EVENT_FLAG 0x0 #define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */ -#define nALARM_EVENT_FLAG 0x0 #define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */ -#define nSECONDS_EVENT_FLAG 0x0 #define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */ -#define nMINUTES_EVENT_FLAG 0x0 #define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */ -#define nHOURS_EVENT_FLAG 0x0 #define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */ -#define nTWENTY_FOUR_HOURS_EVENT_FLAG 0x0 #define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */ -#define nDAY_ALARM_EVENT_FLAG 0x0 #define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */ -#define nWRITE_PENDING__STATUS 0x0 #define WRITE_COMPLETE 0x8000 /* Write Complete */ -#define nWRITE_COMPLETE 0x0 /* Bit masks for RTC_SWCNT */ @@ -2458,21 +2170,15 @@ /* Bit masks for RTC_PREN */ #define PREN 0x1 /* Prescaler Enable */ -#define nPREN 0x0 /* Bit masks for OTP_CONTROL */ #define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ #define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ -#define nFIEN 0x0 #define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ -#define nFTESTDEC 0x0 #define FWRTEST 0x2000 /* OTP/Fuse Write Test */ -#define nFWRTEST 0x0 #define FRDEN 0x4000 /* OTP/Fuse Read Enable */ -#define nFRDEN 0x0 #define FWREN 0x8000 /* OTP/Fuse Write Enable */ -#define nFWREN 0x0 /* Bit masks for OTP_BEN */ @@ -2481,15 +2187,10 @@ /* Bit masks for OTP_STATUS */ #define FCOMP 0x1 /* OTP/Fuse Access Complete */ -#define nFCOMP 0x0 #define FERROR 0x2 /* OTP/Fuse Access Error */ -#define nFERROR 0x0 #define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ -#define nMMRGLOAD 0x0 #define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ -#define nMMRGLOCK 0x0 #define FPGMEN 0x40 /* OTP/Fuse Program Enable */ -#define nFPGMEN 0x0 /* Bit masks for OTP_TIMING */ @@ -2503,42 +2204,29 @@ /* Bit masks for SECURE_SYSSWT */ #define EMUDABL 0x1 /* Emulation Disable. */ -#define nEMUDABL 0x0 #define RSTDABL 0x2 /* Reset Disable */ -#define nRSTDABL 0x0 #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ #define DMA0OVR 0x800 /* DMA0 Memory Access Override */ -#define nDMA0OVR 0x0 #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ -#define nDMA1OVR 0x0 #define EMUOVR 0x4000 /* Emulation Override */ -#define nEMUOVR 0x0 #define OTPSEN 0x8000 /* OTP Secrets Enable. */ -#define nOTPSEN 0x0 #define L2DABL 0x70000 /* L2 Memory Disable. */ /* Bit masks for SECURE_CONTROL */ #define SECURE0 0x1 /* SECURE 0 */ -#define nSECURE0 0x0 #define SECURE1 0x2 /* SECURE 1 */ -#define nSECURE1 0x0 #define SECURE2 0x4 /* SECURE 2 */ -#define nSECURE2 0x0 #define SECURE3 0x8 /* SECURE 3 */ -#define nSECURE3 0x0 /* Bit masks for SECURE_STATUS */ #define SECMODE 0x3 /* Secured Mode Control State */ #define NMI 0x4 /* Non Maskable Interrupt */ -#define nNMI 0x0 #define AFVALID 0x8 /* Authentication Firmware Valid */ -#define nAFVALID 0x0 #define AFEXIT 0x10 /* Authentication Firmware Exit */ -#define nAFEXIT 0x0 #define SECSTAT 0xe0 /* Secure Status */ /* Bit masks for PLL_DIV */ @@ -2550,42 +2238,25 @@ #define MSEL 0x7e00 /* Multiplier Select */ #define BYPASS 0x100 /* PLL Bypass Enable */ -#define nBYPASS 0x0 #define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */ -#define nOUTPUT_DELAY 0x0 #define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */ -#define nINPUT_DELAY 0x0 #define PDWN 0x20 /* Power Down */ -#define nPDWN 0x0 #define STOPCK 0x8 /* Stop Clock */ -#define nSTOPCK 0x0 #define PLL_OFF 0x2 /* Disable PLL */ -#define nPLL_OFF 0x0 #define DF 0x1 /* Divide Frequency */ -#define nDF 0x0 /* Bit masks for PLL_STAT */ #define PLL_LOCKED 0x20 /* PLL Locked Status */ -#define nPLL_LOCKED 0x0 #define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */ -#define nACTIVE_PLLDISABLED 0x0 #define FULL_ON 0x2 /* Full-On Mode */ -#define nFULL_ON 0x0 #define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */ -#define nACTIVE_PLLENABLED 0x0 #define RTCWS 0x400 /* RTC/Reset Wake-Up Status */ -#define nRTCWS 0x0 #define CANWS 0x800 /* CAN Wake-Up Status */ -#define nCANWS 0x0 #define USBWS 0x2000 /* USB Wake-Up Status */ -#define nUSBWS 0x0 #define KPADWS 0x4000 /* Keypad Wake-Up Status */ -#define nKPADWS 0x0 #define ROTWS 0x8000 /* Rotary Wake-Up Status */ -#define nROTWS 0x0 #define GPWS 0x1000 /* General-Purpose Wake-Up Status */ -#define nGPWS 0x0 /* Bit masks for VR_CTL */ @@ -2593,79 +2264,52 @@ #define GAIN 0xc /* Voltage Output Level Gain */ #define VLEV 0xf0 /* Internal Voltage Level */ #define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */ -#define nSCKELOW 0x0 #define WAKE 0x100 /* RTC/Reset Wake-Up Enable */ -#define nWAKE 0x0 #define CANWE 0x200 /* CAN0/1 Wake-Up Enable */ -#define nCANWE 0x0 #define GPWE 0x400 /* General-Purpose Wake-Up Enable */ -#define nGPWE 0x0 #define USBWE 0x800 /* USB Wake-Up Enable */ -#define nUSBWE 0x0 #define KPADWE 0x1000 /* Keypad Wake-Up Enable */ -#define nKPADWE 0x0 #define ROTWE 0x2000 /* Rotary Wake-Up Enable */ -#define nROTWE 0x0 /* Bit masks for NFC_CTL */ #define WR_DLY 0xf /* Write Strobe Delay */ #define RD_DLY 0xf0 /* Read Strobe Delay */ #define NWIDTH 0x100 /* NAND Data Width */ -#define nNWIDTH 0x0 #define PG_SIZE 0x200 /* Page Size */ -#define nPG_SIZE 0x0 /* Bit masks for NFC_STAT */ #define NBUSY 0x1 /* Not Busy */ -#define nNBUSY 0x0 #define WB_FULL 0x2 /* Write Buffer Full */ -#define nWB_FULL 0x0 #define PG_WR_STAT 0x4 /* Page Write Pending */ -#define nPG_WR_STAT 0x0 #define PG_RD_STAT 0x8 /* Page Read Pending */ -#define nPG_RD_STAT 0x0 #define WB_EMPTY 0x10 /* Write Buffer Empty */ -#define nWB_EMPTY 0x0 /* Bit masks for NFC_IRQSTAT */ #define NBUSYIRQ 0x1 /* Not Busy IRQ */ -#define nNBUSYIRQ 0x0 #define WB_OVF 0x2 /* Write Buffer Overflow */ -#define nWB_OVF 0x0 #define WB_EDGE 0x4 /* Write Buffer Edge Detect */ -#define nWB_EDGE 0x0 #define RD_RDY 0x8 /* Read Data Ready */ -#define nRD_RDY 0x0 #define WR_DONE 0x10 /* Page Write Done */ -#define nWR_DONE 0x0 /* Bit masks for NFC_IRQMASK */ #define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */ -#define nMASK_BUSYIRQ 0x0 #define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */ -#define nMASK_WBOVF 0x0 #define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */ -#define nMASK_WBEMPTY 0x0 #define MASK_RDRDY 0x8 /* Mask Read Data Ready */ -#define nMASK_RDRDY 0x0 #define MASK_WRDONE 0x10 /* Mask Write Done */ -#define nMASK_WRDONE 0x0 /* Bit masks for NFC_RST */ #define ECC_RST 0x1 /* ECC (and NFC counters) Reset */ -#define nECC_RST 0x0 /* Bit masks for NFC_PGCTL */ #define PG_RD_START 0x1 /* Page Read Start */ -#define nPG_RD_START 0x0 #define PG_WR_START 0x2 /* Page Write Start */ -#define nPG_WR_START 0x0 /* Bit masks for NFC_ECC0 */ @@ -2690,56 +2334,34 @@ /* Bit masks for CAN0_CONTROL */ #define SRS 0x1 /* Software Reset */ -#define nSRS 0x0 #define DNM 0x2 /* DeviceNet Mode */ -#define nDNM 0x0 #define ABO 0x4 /* Auto Bus On */ -#define nABO 0x0 #define WBA 0x10 /* Wakeup On CAN Bus Activity */ -#define nWBA 0x0 #define SMR 0x20 /* Sleep Mode Request */ -#define nSMR 0x0 #define CSR 0x40 /* CAN Suspend Mode Request */ -#define nCSR 0x0 #define CCR 0x80 /* CAN Configuration Mode Request */ -#define nCCR 0x0 /* Bit masks for CAN0_STATUS */ #define WT 0x1 /* CAN Transmit Warning Flag */ -#define nWT 0x0 #define WR 0x2 /* CAN Receive Warning Flag */ -#define nWR 0x0 #define EP 0x4 /* CAN Error Passive Mode */ -#define nEP 0x0 #define EBO 0x8 /* CAN Error Bus Off Mode */ -#define nEBO 0x0 #define CSA 0x40 /* CAN Suspend Mode Acknowledge */ -#define nCSA 0x0 #define CCA 0x80 /* CAN Configuration Mode Acknowledge */ -#define nCCA 0x0 #define MBPTR 0x1f00 /* Mailbox Pointer */ #define TRM 0x4000 /* Transmit Mode Status */ -#define nTRM 0x0 #define REC 0x8000 /* Receive Mode Status */ -#define nREC 0x0 /* Bit masks for CAN0_DEBUG */ #define DEC 0x1 /* Disable Transmit/Receive Error Counters */ -#define nDEC 0x0 #define DRI 0x2 /* Disable CANRX Input Pin */ -#define nDRI 0x0 #define DTO 0x4 /* Disable CANTX Output Pin */ -#define nDTO 0x0 #define DIL 0x8 /* Disable Internal Loop */ -#define nDIL 0x0 #define MAA 0x10 /* Mode Auto-Acknowledge */ -#define nMAA 0x0 #define MRB 0x20 /* Mode Read Back */ -#define nMRB 0x0 #define CDE 0x8000 /* CAN Debug Mode Enable */ -#define nCDE 0x0 /* Bit masks for CAN0_CLOCK */ @@ -2749,111 +2371,69 @@ #define SJW 0x300 /* Synchronization Jump Width */ #define SAM 0x80 /* Sampling */ -#define nSAM 0x0 #define TSEG2 0x70 /* Time Segment 2 */ #define TSEG1 0xf /* Time Segment 1 */ /* Bit masks for CAN0_INTR */ #define CANRX 0x80 /* Serial Input From Transceiver */ -#define nCANRX 0x0 #define CANTX 0x40 /* Serial Output To Transceiver */ -#define nCANTX 0x0 #define SMACK 0x8 /* Sleep Mode Acknowledge */ -#define nSMACK 0x0 #define GIRQ 0x4 /* Global Interrupt Request Status */ -#define nGIRQ 0x0 #define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */ -#define nMBTIRQ 0x0 #define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */ -#define nMBRIRQ 0x0 /* Bit masks for CAN0_GIM */ #define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */ -#define nEWTIM 0x0 #define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */ -#define nEWRIM 0x0 #define EPIM 0x4 /* Error Passive Interrupt Mask */ -#define nEPIM 0x0 #define BOIM 0x8 /* Bus Off Interrupt Mask */ -#define nBOIM 0x0 #define WUIM 0x10 /* Wakeup Interrupt Mask */ -#define nWUIM 0x0 #define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */ -#define nUIAIM 0x0 #define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */ -#define nAAIM 0x0 #define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */ -#define nRMLIM 0x0 #define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */ -#define nUCEIM 0x0 #define ADIM 0x400 /* Access Denied Interrupt Mask */ -#define nADIM 0x0 /* Bit masks for CAN0_GIS */ #define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */ -#define nEWTIS 0x0 #define EWRIS 0x2 /* Error Warning Receive Interrupt Status */ -#define nEWRIS 0x0 #define EPIS 0x4 /* Error Passive Interrupt Status */ -#define nEPIS 0x0 #define BOIS 0x8 /* Bus Off Interrupt Status */ -#define nBOIS 0x0 #define WUIS 0x10 /* Wakeup Interrupt Status */ -#define nWUIS 0x0 #define UIAIS 0x20 /* Unimplemented Address Interrupt Status */ -#define nUIAIS 0x0 #define AAIS 0x40 /* Abort Acknowledge Interrupt Status */ -#define nAAIS 0x0 #define RMLIS 0x80 /* Receive Message Lost Interrupt Status */ -#define nRMLIS 0x0 #define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */ -#define nUCEIS 0x0 #define ADIS 0x400 /* Access Denied Interrupt Status */ -#define nADIS 0x0 /* Bit masks for CAN0_GIF */ #define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */ -#define nEWTIF 0x0 #define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */ -#define nEWRIF 0x0 #define EPIF 0x4 /* Error Passive Interrupt Flag */ -#define nEPIF 0x0 #define BOIF 0x8 /* Bus Off Interrupt Flag */ -#define nBOIF 0x0 #define WUIF 0x10 /* Wakeup Interrupt Flag */ -#define nWUIF 0x0 #define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */ -#define nUIAIF 0x0 #define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */ -#define nAAIF 0x0 #define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */ -#define nRMLIF 0x0 #define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */ -#define nUCEIF 0x0 #define ADIF 0x400 /* Access Denied Interrupt Flag */ -#define nADIF 0x0 /* Bit masks for CAN0_MBTD */ #define TDR 0x80 /* Temporary Disable Request */ -#define nTDR 0x0 #define TDA 0x40 /* Temporary Disable Acknowledge */ -#define nTDA 0x0 #define TDPTR 0x1f /* Temporary Disable Pointer */ /* Bit masks for CAN0_UCCNF */ #define UCCNF 0xf /* Universal Counter Configuration */ #define UCRC 0x20 /* Universal Counter Reload/Clear */ -#define nUCRC 0x0 #define UCCT 0x40 /* Universal Counter CAN Trigger */ -#define nUCCT 0x0 #define UCE 0x80 /* Universal Counter Enable */ -#define nUCE 0x0 /* Bit masks for CAN0_UCCNT */ @@ -2871,17 +2451,11 @@ /* Bit masks for CAN0_ESR */ #define FER 0x80 /* Form Error */ -#define nFER 0x0 #define BEF 0x40 /* Bit Error Flag */ -#define nBEF 0x0 #define SA0 0x20 /* Stuck At Dominant */ -#define nSA0 0x0 #define CRCE 0x10 /* CRC Error */ -#define nCRCE 0x0 #define SER 0x8 /* Stuff Bit Error */ -#define nSER 0x0 #define ACKE 0x4 /* Acknowledge Error */ -#define nACKE 0x0 /* Bit masks for CAN0_EWR */ @@ -2891,11 +2465,8 @@ /* Bit masks for CAN0_AMxx_H */ #define FDF 0x8000 /* Filter On Data Field */ -#define nFDF 0x0 #define FMD 0x4000 /* Full Mask Data */ -#define nFMD 0x0 #define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */ -#define nAMIDE 0x0 #define BASEID 0x1ffc /* Base Identifier */ #define EXTID_HI 0x3 /* Extended Identifier High Bits */ @@ -2907,11 +2478,8 @@ /* Bit masks for CAN0_MBxx_ID1 */ #define AME 0x8000 /* Acceptance Mask Enable */ -#define nAME 0x0 #define RTR 0x4000 /* Remote Transmission Request */ -#define nRTR 0x0 #define IDE 0x2000 /* Identifier Extension */ -#define nIDE 0x0 #define BASEID 0x1ffc /* Base Identifier */ #define EXTID_HI 0x3 /* Extended Identifier High Bits */ @@ -2951,977 +2519,534 @@ /* Bit masks for CAN0_MC1 */ #define MC0 0x1 /* Mailbox 0 Enable */ -#define nMC0 0x0 #define MC1 0x2 /* Mailbox 1 Enable */ -#define nMC1 0x0 #define MC2 0x4 /* Mailbox 2 Enable */ -#define nMC2 0x0 #define MC3 0x8 /* Mailbox 3 Enable */ -#define nMC3 0x0 #define MC4 0x10 /* Mailbox 4 Enable */ -#define nMC4 0x0 #define MC5 0x20 /* Mailbox 5 Enable */ -#define nMC5 0x0 #define MC6 0x40 /* Mailbox 6 Enable */ -#define nMC6 0x0 #define MC7 0x80 /* Mailbox 7 Enable */ -#define nMC7 0x0 #define MC8 0x100 /* Mailbox 8 Enable */ -#define nMC8 0x0 #define MC9 0x200 /* Mailbox 9 Enable */ -#define nMC9 0x0 #define MC10 0x400 /* Mailbox 10 Enable */ -#define nMC10 0x0 #define MC11 0x800 /* Mailbox 11 Enable */ -#define nMC11 0x0 #define MC12 0x1000 /* Mailbox 12 Enable */ -#define nMC12 0x0 #define MC13 0x2000 /* Mailbox 13 Enable */ -#define nMC13 0x0 #define MC14 0x4000 /* Mailbox 14 Enable */ -#define nMC14 0x0 #define MC15 0x8000 /* Mailbox 15 Enable */ -#define nMC15 0x0 /* Bit masks for CAN0_MC2 */ #define MC16 0x1 /* Mailbox 16 Enable */ -#define nMC16 0x0 #define MC17 0x2 /* Mailbox 17 Enable */ -#define nMC17 0x0 #define MC18 0x4 /* Mailbox 18 Enable */ -#define nMC18 0x0 #define MC19 0x8 /* Mailbox 19 Enable */ -#define nMC19 0x0 #define MC20 0x10 /* Mailbox 20 Enable */ -#define nMC20 0x0 #define MC21 0x20 /* Mailbox 21 Enable */ -#define nMC21 0x0 #define MC22 0x40 /* Mailbox 22 Enable */ -#define nMC22 0x0 #define MC23 0x80 /* Mailbox 23 Enable */ -#define nMC23 0x0 #define MC24 0x100 /* Mailbox 24 Enable */ -#define nMC24 0x0 #define MC25 0x200 /* Mailbox 25 Enable */ -#define nMC25 0x0 #define MC26 0x400 /* Mailbox 26 Enable */ -#define nMC26 0x0 #define MC27 0x800 /* Mailbox 27 Enable */ -#define nMC27 0x0 #define MC28 0x1000 /* Mailbox 28 Enable */ -#define nMC28 0x0 #define MC29 0x2000 /* Mailbox 29 Enable */ -#define nMC29 0x0 #define MC30 0x4000 /* Mailbox 30 Enable */ -#define nMC30 0x0 #define MC31 0x8000 /* Mailbox 31 Enable */ -#define nMC31 0x0 /* Bit masks for CAN0_MD1 */ #define MD0 0x1 /* Mailbox 0 Receive Enable */ -#define nMD0 0x0 #define MD1 0x2 /* Mailbox 1 Receive Enable */ -#define nMD1 0x0 #define MD2 0x4 /* Mailbox 2 Receive Enable */ -#define nMD2 0x0 #define MD3 0x8 /* Mailbox 3 Receive Enable */ -#define nMD3 0x0 #define MD4 0x10 /* Mailbox 4 Receive Enable */ -#define nMD4 0x0 #define MD5 0x20 /* Mailbox 5 Receive Enable */ -#define nMD5 0x0 #define MD6 0x40 /* Mailbox 6 Receive Enable */ -#define nMD6 0x0 #define MD7 0x80 /* Mailbox 7 Receive Enable */ -#define nMD7 0x0 #define MD8 0x100 /* Mailbox 8 Receive Enable */ -#define nMD8 0x0 #define MD9 0x200 /* Mailbox 9 Receive Enable */ -#define nMD9 0x0 #define MD10 0x400 /* Mailbox 10 Receive Enable */ -#define nMD10 0x0 #define MD11 0x800 /* Mailbox 11 Receive Enable */ -#define nMD11 0x0 #define MD12 0x1000 /* Mailbox 12 Receive Enable */ -#define nMD12 0x0 #define MD13 0x2000 /* Mailbox 13 Receive Enable */ -#define nMD13 0x0 #define MD14 0x4000 /* Mailbox 14 Receive Enable */ -#define nMD14 0x0 #define MD15 0x8000 /* Mailbox 15 Receive Enable */ -#define nMD15 0x0 /* Bit masks for CAN0_MD2 */ #define MD16 0x1 /* Mailbox 16 Receive Enable */ -#define nMD16 0x0 #define MD17 0x2 /* Mailbox 17 Receive Enable */ -#define nMD17 0x0 #define MD18 0x4 /* Mailbox 18 Receive Enable */ -#define nMD18 0x0 #define MD19 0x8 /* Mailbox 19 Receive Enable */ -#define nMD19 0x0 #define MD20 0x10 /* Mailbox 20 Receive Enable */ -#define nMD20 0x0 #define MD21 0x20 /* Mailbox 21 Receive Enable */ -#define nMD21 0x0 #define MD22 0x40 /* Mailbox 22 Receive Enable */ -#define nMD22 0x0 #define MD23 0x80 /* Mailbox 23 Receive Enable */ -#define nMD23 0x0 #define MD24 0x100 /* Mailbox 24 Receive Enable */ -#define nMD24 0x0 #define MD25 0x200 /* Mailbox 25 Receive Enable */ -#define nMD25 0x0 #define MD26 0x400 /* Mailbox 26 Receive Enable */ -#define nMD26 0x0 #define MD27 0x800 /* Mailbox 27 Receive Enable */ -#define nMD27 0x0 #define MD28 0x1000 /* Mailbox 28 Receive Enable */ -#define nMD28 0x0 #define MD29 0x2000 /* Mailbox 29 Receive Enable */ -#define nMD29 0x0 #define MD30 0x4000 /* Mailbox 30 Receive Enable */ -#define nMD30 0x0 #define MD31 0x8000 /* Mailbox 31 Receive Enable */ -#define nMD31 0x0 /* Bit masks for CAN0_RMP1 */ #define RMP0 0x1 /* Mailbox 0 Receive Message Pending */ -#define nRMP0 0x0 #define RMP1 0x2 /* Mailbox 1 Receive Message Pending */ -#define nRMP1 0x0 #define RMP2 0x4 /* Mailbox 2 Receive Message Pending */ -#define nRMP2 0x0 #define RMP3 0x8 /* Mailbox 3 Receive Message Pending */ -#define nRMP3 0x0 #define RMP4 0x10 /* Mailbox 4 Receive Message Pending */ -#define nRMP4 0x0 #define RMP5 0x20 /* Mailbox 5 Receive Message Pending */ -#define nRMP5 0x0 #define RMP6 0x40 /* Mailbox 6 Receive Message Pending */ -#define nRMP6 0x0 #define RMP7 0x80 /* Mailbox 7 Receive Message Pending */ -#define nRMP7 0x0 #define RMP8 0x100 /* Mailbox 8 Receive Message Pending */ -#define nRMP8 0x0 #define RMP9 0x200 /* Mailbox 9 Receive Message Pending */ -#define nRMP9 0x0 #define RMP10 0x400 /* Mailbox 10 Receive Message Pending */ -#define nRMP10 0x0 #define RMP11 0x800 /* Mailbox 11 Receive Message Pending */ -#define nRMP11 0x0 #define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */ -#define nRMP12 0x0 #define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */ -#define nRMP13 0x0 #define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */ -#define nRMP14 0x0 #define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */ -#define nRMP15 0x0 /* Bit masks for CAN0_RMP2 */ #define RMP16 0x1 /* Mailbox 16 Receive Message Pending */ -#define nRMP16 0x0 #define RMP17 0x2 /* Mailbox 17 Receive Message Pending */ -#define nRMP17 0x0 #define RMP18 0x4 /* Mailbox 18 Receive Message Pending */ -#define nRMP18 0x0 #define RMP19 0x8 /* Mailbox 19 Receive Message Pending */ -#define nRMP19 0x0 #define RMP20 0x10 /* Mailbox 20 Receive Message Pending */ -#define nRMP20 0x0 #define RMP21 0x20 /* Mailbox 21 Receive Message Pending */ -#define nRMP21 0x0 #define RMP22 0x40 /* Mailbox 22 Receive Message Pending */ -#define nRMP22 0x0 #define RMP23 0x80 /* Mailbox 23 Receive Message Pending */ -#define nRMP23 0x0 #define RMP24 0x100 /* Mailbox 24 Receive Message Pending */ -#define nRMP24 0x0 #define RMP25 0x200 /* Mailbox 25 Receive Message Pending */ -#define nRMP25 0x0 #define RMP26 0x400 /* Mailbox 26 Receive Message Pending */ -#define nRMP26 0x0 #define RMP27 0x800 /* Mailbox 27 Receive Message Pending */ -#define nRMP27 0x0 #define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */ -#define nRMP28 0x0 #define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */ -#define nRMP29 0x0 #define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */ -#define nRMP30 0x0 #define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */ -#define nRMP31 0x0 /* Bit masks for CAN0_RML1 */ #define RML0 0x1 /* Mailbox 0 Receive Message Lost */ -#define nRML0 0x0 #define RML1 0x2 /* Mailbox 1 Receive Message Lost */ -#define nRML1 0x0 #define RML2 0x4 /* Mailbox 2 Receive Message Lost */ -#define nRML2 0x0 #define RML3 0x8 /* Mailbox 3 Receive Message Lost */ -#define nRML3 0x0 #define RML4 0x10 /* Mailbox 4 Receive Message Lost */ -#define nRML4 0x0 #define RML5 0x20 /* Mailbox 5 Receive Message Lost */ -#define nRML5 0x0 #define RML6 0x40 /* Mailbox 6 Receive Message Lost */ -#define nRML6 0x0 #define RML7 0x80 /* Mailbox 7 Receive Message Lost */ -#define nRML7 0x0 #define RML8 0x100 /* Mailbox 8 Receive Message Lost */ -#define nRML8 0x0 #define RML9 0x200 /* Mailbox 9 Receive Message Lost */ -#define nRML9 0x0 #define RML10 0x400 /* Mailbox 10 Receive Message Lost */ -#define nRML10 0x0 #define RML11 0x800 /* Mailbox 11 Receive Message Lost */ -#define nRML11 0x0 #define RML12 0x1000 /* Mailbox 12 Receive Message Lost */ -#define nRML12 0x0 #define RML13 0x2000 /* Mailbox 13 Receive Message Lost */ -#define nRML13 0x0 #define RML14 0x4000 /* Mailbox 14 Receive Message Lost */ -#define nRML14 0x0 #define RML15 0x8000 /* Mailbox 15 Receive Message Lost */ -#define nRML15 0x0 /* Bit masks for CAN0_RML2 */ #define RML16 0x1 /* Mailbox 16 Receive Message Lost */ -#define nRML16 0x0 #define RML17 0x2 /* Mailbox 17 Receive Message Lost */ -#define nRML17 0x0 #define RML18 0x4 /* Mailbox 18 Receive Message Lost */ -#define nRML18 0x0 #define RML19 0x8 /* Mailbox 19 Receive Message Lost */ -#define nRML19 0x0 #define RML20 0x10 /* Mailbox 20 Receive Message Lost */ -#define nRML20 0x0 #define RML21 0x20 /* Mailbox 21 Receive Message Lost */ -#define nRML21 0x0 #define RML22 0x40 /* Mailbox 22 Receive Message Lost */ -#define nRML22 0x0 #define RML23 0x80 /* Mailbox 23 Receive Message Lost */ -#define nRML23 0x0 #define RML24 0x100 /* Mailbox 24 Receive Message Lost */ -#define nRML24 0x0 #define RML25 0x200 /* Mailbox 25 Receive Message Lost */ -#define nRML25 0x0 #define RML26 0x400 /* Mailbox 26 Receive Message Lost */ -#define nRML26 0x0 #define RML27 0x800 /* Mailbox 27 Receive Message Lost */ -#define nRML27 0x0 #define RML28 0x1000 /* Mailbox 28 Receive Message Lost */ -#define nRML28 0x0 #define RML29 0x2000 /* Mailbox 29 Receive Message Lost */ -#define nRML29 0x0 #define RML30 0x4000 /* Mailbox 30 Receive Message Lost */ -#define nRML30 0x0 #define RML31 0x8000 /* Mailbox 31 Receive Message Lost */ -#define nRML31 0x0 /* Bit masks for CAN0_OPSS1 */ #define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS0 0x0 #define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS1 0x0 #define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS2 0x0 #define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS3 0x0 #define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS4 0x0 #define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS5 0x0 #define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS6 0x0 #define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS7 0x0 #define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS8 0x0 #define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS9 0x0 #define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS10 0x0 #define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS11 0x0 #define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS12 0x0 #define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS13 0x0 #define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS14 0x0 #define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS15 0x0 /* Bit masks for CAN0_OPSS2 */ #define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS16 0x0 #define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS17 0x0 #define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS18 0x0 #define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS19 0x0 #define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS20 0x0 #define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS21 0x0 #define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS22 0x0 #define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS23 0x0 #define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS24 0x0 #define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS25 0x0 #define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS26 0x0 #define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS27 0x0 #define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS28 0x0 #define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS29 0x0 #define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS30 0x0 #define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS31 0x0 /* Bit masks for CAN0_TRS1 */ #define TRS0 0x1 /* Mailbox 0 Transmit Request Set */ -#define nTRS0 0x0 #define TRS1 0x2 /* Mailbox 1 Transmit Request Set */ -#define nTRS1 0x0 #define TRS2 0x4 /* Mailbox 2 Transmit Request Set */ -#define nTRS2 0x0 #define TRS3 0x8 /* Mailbox 3 Transmit Request Set */ -#define nTRS3 0x0 #define TRS4 0x10 /* Mailbox 4 Transmit Request Set */ -#define nTRS4 0x0 #define TRS5 0x20 /* Mailbox 5 Transmit Request Set */ -#define nTRS5 0x0 #define TRS6 0x40 /* Mailbox 6 Transmit Request Set */ -#define nTRS6 0x0 #define TRS7 0x80 /* Mailbox 7 Transmit Request Set */ -#define nTRS7 0x0 #define TRS8 0x100 /* Mailbox 8 Transmit Request Set */ -#define nTRS8 0x0 #define TRS9 0x200 /* Mailbox 9 Transmit Request Set */ -#define nTRS9 0x0 #define TRS10 0x400 /* Mailbox 10 Transmit Request Set */ -#define nTRS10 0x0 #define TRS11 0x800 /* Mailbox 11 Transmit Request Set */ -#define nTRS11 0x0 #define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */ -#define nTRS12 0x0 #define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */ -#define nTRS13 0x0 #define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */ -#define nTRS14 0x0 #define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */ -#define nTRS15 0x0 /* Bit masks for CAN0_TRS2 */ #define TRS16 0x1 /* Mailbox 16 Transmit Request Set */ -#define nTRS16 0x0 #define TRS17 0x2 /* Mailbox 17 Transmit Request Set */ -#define nTRS17 0x0 #define TRS18 0x4 /* Mailbox 18 Transmit Request Set */ -#define nTRS18 0x0 #define TRS19 0x8 /* Mailbox 19 Transmit Request Set */ -#define nTRS19 0x0 #define TRS20 0x10 /* Mailbox 20 Transmit Request Set */ -#define nTRS20 0x0 #define TRS21 0x20 /* Mailbox 21 Transmit Request Set */ -#define nTRS21 0x0 #define TRS22 0x40 /* Mailbox 22 Transmit Request Set */ -#define nTRS22 0x0 #define TRS23 0x80 /* Mailbox 23 Transmit Request Set */ -#define nTRS23 0x0 #define TRS24 0x100 /* Mailbox 24 Transmit Request Set */ -#define nTRS24 0x0 #define TRS25 0x200 /* Mailbox 25 Transmit Request Set */ -#define nTRS25 0x0 #define TRS26 0x400 /* Mailbox 26 Transmit Request Set */ -#define nTRS26 0x0 #define TRS27 0x800 /* Mailbox 27 Transmit Request Set */ -#define nTRS27 0x0 #define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */ -#define nTRS28 0x0 #define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */ -#define nTRS29 0x0 #define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */ -#define nTRS30 0x0 #define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */ -#define nTRS31 0x0 /* Bit masks for CAN0_TRR1 */ #define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */ -#define nTRR0 0x0 #define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */ -#define nTRR1 0x0 #define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */ -#define nTRR2 0x0 #define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */ -#define nTRR3 0x0 #define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */ -#define nTRR4 0x0 #define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */ -#define nTRR5 0x0 #define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */ -#define nTRR6 0x0 #define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */ -#define nTRR7 0x0 #define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */ -#define nTRR8 0x0 #define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */ -#define nTRR9 0x0 #define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */ -#define nTRR10 0x0 #define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */ -#define nTRR11 0x0 #define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */ -#define nTRR12 0x0 #define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */ -#define nTRR13 0x0 #define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */ -#define nTRR14 0x0 #define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */ -#define nTRR15 0x0 /* Bit masks for CAN0_TRR2 */ #define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */ -#define nTRR16 0x0 #define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */ -#define nTRR17 0x0 #define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */ -#define nTRR18 0x0 #define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */ -#define nTRR19 0x0 #define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */ -#define nTRR20 0x0 #define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */ -#define nTRR21 0x0 #define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */ -#define nTRR22 0x0 #define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */ -#define nTRR23 0x0 #define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */ -#define nTRR24 0x0 #define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */ -#define nTRR25 0x0 #define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */ -#define nTRR26 0x0 #define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */ -#define nTRR27 0x0 #define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */ -#define nTRR28 0x0 #define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */ -#define nTRR29 0x0 #define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */ -#define nTRR30 0x0 #define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */ -#define nTRR31 0x0 /* Bit masks for CAN0_AA1 */ #define AA0 0x1 /* Mailbox 0 Abort Acknowledge */ -#define nAA0 0x0 #define AA1 0x2 /* Mailbox 1 Abort Acknowledge */ -#define nAA1 0x0 #define AA2 0x4 /* Mailbox 2 Abort Acknowledge */ -#define nAA2 0x0 #define AA3 0x8 /* Mailbox 3 Abort Acknowledge */ -#define nAA3 0x0 #define AA4 0x10 /* Mailbox 4 Abort Acknowledge */ -#define nAA4 0x0 #define AA5 0x20 /* Mailbox 5 Abort Acknowledge */ -#define nAA5 0x0 #define AA6 0x40 /* Mailbox 6 Abort Acknowledge */ -#define nAA6 0x0 #define AA7 0x80 /* Mailbox 7 Abort Acknowledge */ -#define nAA7 0x0 #define AA8 0x100 /* Mailbox 8 Abort Acknowledge */ -#define nAA8 0x0 #define AA9 0x200 /* Mailbox 9 Abort Acknowledge */ -#define nAA9 0x0 #define AA10 0x400 /* Mailbox 10 Abort Acknowledge */ -#define nAA10 0x0 #define AA11 0x800 /* Mailbox 11 Abort Acknowledge */ -#define nAA11 0x0 #define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */ -#define nAA12 0x0 #define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */ -#define nAA13 0x0 #define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */ -#define nAA14 0x0 #define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */ -#define nAA15 0x0 /* Bit masks for CAN0_AA2 */ #define AA16 0x1 /* Mailbox 16 Abort Acknowledge */ -#define nAA16 0x0 #define AA17 0x2 /* Mailbox 17 Abort Acknowledge */ -#define nAA17 0x0 #define AA18 0x4 /* Mailbox 18 Abort Acknowledge */ -#define nAA18 0x0 #define AA19 0x8 /* Mailbox 19 Abort Acknowledge */ -#define nAA19 0x0 #define AA20 0x10 /* Mailbox 20 Abort Acknowledge */ -#define nAA20 0x0 #define AA21 0x20 /* Mailbox 21 Abort Acknowledge */ -#define nAA21 0x0 #define AA22 0x40 /* Mailbox 22 Abort Acknowledge */ -#define nAA22 0x0 #define AA23 0x80 /* Mailbox 23 Abort Acknowledge */ -#define nAA23 0x0 #define AA24 0x100 /* Mailbox 24 Abort Acknowledge */ -#define nAA24 0x0 #define AA25 0x200 /* Mailbox 25 Abort Acknowledge */ -#define nAA25 0x0 #define AA26 0x400 /* Mailbox 26 Abort Acknowledge */ -#define nAA26 0x0 #define AA27 0x800 /* Mailbox 27 Abort Acknowledge */ -#define nAA27 0x0 #define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */ -#define nAA28 0x0 #define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */ -#define nAA29 0x0 #define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */ -#define nAA30 0x0 #define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */ -#define nAA31 0x0 /* Bit masks for CAN0_TA1 */ #define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */ -#define nTA0 0x0 #define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */ -#define nTA1 0x0 #define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */ -#define nTA2 0x0 #define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */ -#define nTA3 0x0 #define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */ -#define nTA4 0x0 #define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */ -#define nTA5 0x0 #define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */ -#define nTA6 0x0 #define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */ -#define nTA7 0x0 #define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */ -#define nTA8 0x0 #define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */ -#define nTA9 0x0 #define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */ -#define nTA10 0x0 #define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */ -#define nTA11 0x0 #define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */ -#define nTA12 0x0 #define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */ -#define nTA13 0x0 #define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */ -#define nTA14 0x0 #define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */ -#define nTA15 0x0 /* Bit masks for CAN0_TA2 */ #define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */ -#define nTA16 0x0 #define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */ -#define nTA17 0x0 #define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */ -#define nTA18 0x0 #define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */ -#define nTA19 0x0 #define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */ -#define nTA20 0x0 #define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */ -#define nTA21 0x0 #define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */ -#define nTA22 0x0 #define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */ -#define nTA23 0x0 #define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */ -#define nTA24 0x0 #define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */ -#define nTA25 0x0 #define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */ -#define nTA26 0x0 #define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */ -#define nTA27 0x0 #define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */ -#define nTA28 0x0 #define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */ -#define nTA29 0x0 #define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */ -#define nTA30 0x0 #define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */ -#define nTA31 0x0 /* Bit masks for CAN0_RFH1 */ #define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */ -#define nRFH0 0x0 #define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */ -#define nRFH1 0x0 #define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */ -#define nRFH2 0x0 #define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */ -#define nRFH3 0x0 #define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */ -#define nRFH4 0x0 #define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */ -#define nRFH5 0x0 #define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */ -#define nRFH6 0x0 #define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */ -#define nRFH7 0x0 #define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */ -#define nRFH8 0x0 #define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */ -#define nRFH9 0x0 #define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */ -#define nRFH10 0x0 #define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */ -#define nRFH11 0x0 #define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */ -#define nRFH12 0x0 #define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */ -#define nRFH13 0x0 #define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */ -#define nRFH14 0x0 #define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */ -#define nRFH15 0x0 /* Bit masks for CAN0_RFH2 */ #define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */ -#define nRFH16 0x0 #define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */ -#define nRFH17 0x0 #define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */ -#define nRFH18 0x0 #define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */ -#define nRFH19 0x0 #define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */ -#define nRFH20 0x0 #define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */ -#define nRFH21 0x0 #define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */ -#define nRFH22 0x0 #define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */ -#define nRFH23 0x0 #define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */ -#define nRFH24 0x0 #define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */ -#define nRFH25 0x0 #define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */ -#define nRFH26 0x0 #define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */ -#define nRFH27 0x0 #define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */ -#define nRFH28 0x0 #define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */ -#define nRFH29 0x0 #define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */ -#define nRFH30 0x0 #define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */ -#define nRFH31 0x0 /* Bit masks for CAN0_MBIM1 */ #define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */ -#define nMBIM0 0x0 #define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */ -#define nMBIM1 0x0 #define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */ -#define nMBIM2 0x0 #define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */ -#define nMBIM3 0x0 #define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */ -#define nMBIM4 0x0 #define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */ -#define nMBIM5 0x0 #define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */ -#define nMBIM6 0x0 #define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */ -#define nMBIM7 0x0 #define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */ -#define nMBIM8 0x0 #define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */ -#define nMBIM9 0x0 #define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */ -#define nMBIM10 0x0 #define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */ -#define nMBIM11 0x0 #define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */ -#define nMBIM12 0x0 #define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */ -#define nMBIM13 0x0 #define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */ -#define nMBIM14 0x0 #define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */ -#define nMBIM15 0x0 /* Bit masks for CAN0_MBIM2 */ #define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */ -#define nMBIM16 0x0 #define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */ -#define nMBIM17 0x0 #define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */ -#define nMBIM18 0x0 #define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */ -#define nMBIM19 0x0 #define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */ -#define nMBIM20 0x0 #define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */ -#define nMBIM21 0x0 #define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */ -#define nMBIM22 0x0 #define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */ -#define nMBIM23 0x0 #define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */ -#define nMBIM24 0x0 #define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */ -#define nMBIM25 0x0 #define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */ -#define nMBIM26 0x0 #define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */ -#define nMBIM27 0x0 #define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */ -#define nMBIM28 0x0 #define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */ -#define nMBIM29 0x0 #define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */ -#define nMBIM30 0x0 #define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */ -#define nMBIM31 0x0 /* Bit masks for CAN0_MBTIF1 */ #define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */ -#define nMBTIF0 0x0 #define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */ -#define nMBTIF1 0x0 #define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */ -#define nMBTIF2 0x0 #define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */ -#define nMBTIF3 0x0 #define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */ -#define nMBTIF4 0x0 #define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */ -#define nMBTIF5 0x0 #define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */ -#define nMBTIF6 0x0 #define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */ -#define nMBTIF7 0x0 #define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */ -#define nMBTIF8 0x0 #define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */ -#define nMBTIF9 0x0 #define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */ -#define nMBTIF10 0x0 #define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */ -#define nMBTIF11 0x0 #define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */ -#define nMBTIF12 0x0 #define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */ -#define nMBTIF13 0x0 #define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */ -#define nMBTIF14 0x0 #define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */ -#define nMBTIF15 0x0 /* Bit masks for CAN0_MBTIF2 */ #define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */ -#define nMBTIF16 0x0 #define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */ -#define nMBTIF17 0x0 #define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */ -#define nMBTIF18 0x0 #define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */ -#define nMBTIF19 0x0 #define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */ -#define nMBTIF20 0x0 #define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */ -#define nMBTIF21 0x0 #define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */ -#define nMBTIF22 0x0 #define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */ -#define nMBTIF23 0x0 #define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */ -#define nMBTIF24 0x0 #define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */ -#define nMBTIF25 0x0 #define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */ -#define nMBTIF26 0x0 #define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */ -#define nMBTIF27 0x0 #define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */ -#define nMBTIF28 0x0 #define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */ -#define nMBTIF29 0x0 #define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */ -#define nMBTIF30 0x0 #define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */ -#define nMBTIF31 0x0 /* Bit masks for CAN0_MBRIF1 */ #define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */ -#define nMBRIF0 0x0 #define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */ -#define nMBRIF1 0x0 #define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */ -#define nMBRIF2 0x0 #define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */ -#define nMBRIF3 0x0 #define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */ -#define nMBRIF4 0x0 #define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */ -#define nMBRIF5 0x0 #define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */ -#define nMBRIF6 0x0 #define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */ -#define nMBRIF7 0x0 #define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */ -#define nMBRIF8 0x0 #define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */ -#define nMBRIF9 0x0 #define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */ -#define nMBRIF10 0x0 #define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */ -#define nMBRIF11 0x0 #define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */ -#define nMBRIF12 0x0 #define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */ -#define nMBRIF13 0x0 #define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */ -#define nMBRIF14 0x0 #define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */ -#define nMBRIF15 0x0 /* Bit masks for CAN0_MBRIF2 */ #define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */ -#define nMBRIF16 0x0 #define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */ -#define nMBRIF17 0x0 #define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */ -#define nMBRIF18 0x0 #define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */ -#define nMBRIF19 0x0 #define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */ -#define nMBRIF20 0x0 #define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */ -#define nMBRIF21 0x0 #define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */ -#define nMBRIF22 0x0 #define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */ -#define nMBRIF23 0x0 #define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */ -#define nMBRIF24 0x0 #define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */ -#define nMBRIF25 0x0 #define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */ -#define nMBRIF26 0x0 #define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */ -#define nMBRIF27 0x0 #define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */ -#define nMBRIF28 0x0 #define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */ -#define nMBRIF29 0x0 #define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */ -#define nMBRIF30 0x0 #define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */ -#define nMBRIF31 0x0 /* Bit masks for EPPIx_STATUS */ #define CFIFO_ERR 0x1 /* Chroma FIFO Error */ -#define nCFIFO_ERR 0x0 #define YFIFO_ERR 0x2 /* Luma FIFO Error */ -#define nYFIFO_ERR 0x0 #define LTERR_OVR 0x4 /* Line Track Overflow */ -#define nLTERR_OVR 0x0 #define LTERR_UNDR 0x8 /* Line Track Underflow */ -#define nLTERR_UNDR 0x0 #define FTERR_OVR 0x10 /* Frame Track Overflow */ -#define nFTERR_OVR 0x0 #define FTERR_UNDR 0x20 /* Frame Track Underflow */ -#define nFTERR_UNDR 0x0 #define ERR_NCOR 0x40 /* Preamble Error Not Corrected */ -#define nERR_NCOR 0x0 #define DMA1URQ 0x80 /* DMA1 Urgent Request */ -#define nDMA1URQ 0x0 #define DMA0URQ 0x100 /* DMA0 Urgent Request */ -#define nDMA0URQ 0x0 #define ERR_DET 0x4000 /* Preamble Error Detected */ -#define nERR_DET 0x0 #define FLD 0x8000 /* Field */ -#define nFLD 0x0 /* Bit masks for EPPIx_CONTROL */ #define EPPI_EN 0x1 /* Enable */ -#define nEPPI_EN 0x0 #define EPPI_DIR 0x2 /* Direction */ -#define nEPPI_DIR 0x0 #define XFR_TYPE 0xc /* Operating Mode */ #define FS_CFG 0x30 /* Frame Sync Configuration */ #define FLD_SEL 0x40 /* Field Select/Trigger */ -#define nFLD_SEL 0x0 #define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */ -#define nITU_TYPE 0x0 #define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */ -#define nBLANKGEN 0x0 #define ICLKGEN 0x200 /* Internal Clock Generation */ -#define nICLKGEN 0x0 #define IFSGEN 0x400 /* Internal Frame Sync Generation */ -#define nIFSGEN 0x0 #define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */ #define POLS 0x6000 /* Frame Sync Polarity */ #define DLENGTH 0x38000 /* Data Length */ #define SKIP_EN 0x40000 /* Skip Enable */ -#define nSKIP_EN 0x0 #define SKIP_EO 0x80000 /* Skip Even or Odd */ -#define nSKIP_EO 0x0 #define PACKEN 0x100000 /* Packing/Unpacking Enable */ -#define nPACKEN 0x0 #define SWAPEN 0x200000 /* Swap Enable */ -#define nSWAPEN 0x0 #define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */ -#define nSIGN_EXT 0x0 #define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */ -#define nSPLT_EVEN_ODD 0x0 #define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */ -#define nSUBSPLT_ODD 0x0 #define DMACFG 0x2000000 /* One or Two DMA Channels Mode */ -#define nDMACFG 0x0 #define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */ -#define nRGB_FMT_EN 0x0 #define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */ #define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */ @@ -3951,60 +3076,36 @@ /* Bit masks for SPIx_CTL */ #define SPE 0x4000 /* SPI Enable */ -#define nSPE 0x0 #define WOM 0x2000 /* Write Open Drain Master */ -#define nWOM 0x0 #define MSTR 0x1000 /* Master Mode */ -#define nMSTR 0x0 #define CPOL 0x800 /* Clock Polarity */ -#define nCPOL 0x0 #define CPHA 0x400 /* Clock Phase */ -#define nCPHA 0x0 #define LSBF 0x200 /* LSB First */ -#define nLSBF 0x0 #define SIZE 0x100 /* Size of Words */ -#define nSIZE 0x0 #define EMISO 0x20 /* Enable MISO Output */ -#define nEMISO 0x0 #define PSSE 0x10 /* Slave-Select Enable */ -#define nPSSE 0x0 #define GM 0x8 /* Get More Data */ -#define nGM 0x0 #define SZ 0x4 /* Send Zero */ -#define nSZ 0x0 #define TIMOD 0x3 /* Transfer Initiation Mode */ /* Bit masks for SPIx_FLG */ #define FLS1 0x2 /* Slave Select Enable 1 */ -#define nFLS1 0x0 #define FLS2 0x4 /* Slave Select Enable 2 */ -#define nFLS2 0x0 #define FLS3 0x8 /* Slave Select Enable 3 */ -#define nFLS3 0x0 #define FLG1 0x200 /* Slave Select Value 1 */ -#define nFLG1 0x0 #define FLG2 0x400 /* Slave Select Value 2 */ -#define nFLG2 0x0 #define FLG3 0x800 /* Slave Select Value 3 */ -#define nFLG3 0x0 /* Bit masks for SPIx_STAT */ #define TXCOL 0x40 /* Transmit Collision Error */ -#define nTXCOL 0x0 #define RXS 0x20 /* RDBR Data Buffer Status */ -#define nRXS 0x0 #define RBSY 0x10 /* Receive Error */ -#define nRBSY 0x0 #define TXS 0x8 /* TDBR Data Buffer Status */ -#define nTXS 0x0 #define TXE 0x4 /* Transmission Error */ -#define nTXE 0x0 #define MODF 0x2 /* Mode Fault Error */ -#define nMODF 0x0 #define SPIF 0x1 /* SPI Finished */ -#define nSPIF 0x0 /* Bit masks for SPIx_TDBR */ @@ -4028,9 +3129,7 @@ #define PRESCALE 0x7f /* Prescale Value */ #define TWI_ENA 0x80 /* TWI Enable */ -#define nTWI_ENA 0x0 #define SCCB 0x200 /* Serial Camera Control Bus */ -#define nSCCB 0x0 /* Bit maskes for TWIx_CLKDIV */ @@ -4040,13 +3139,9 @@ /* Bit maskes for TWIx_SLAVE_CTL */ #define SEN 0x1 /* Slave Enable */ -#define nSEN 0x0 #define STDVAL 0x4 /* Slave Transmit Data Valid */ -#define nSTDVAL 0x0 #define NAK 0x8 /* Not Acknowledge */ -#define nNAK 0x0 #define GEN 0x10 /* General Call Enable */ -#define nGEN 0x0 /* Bit maskes for TWIx_SLAVE_ADDR */ @@ -4055,27 +3150,18 @@ /* Bit maskes for TWIx_SLAVE_STAT */ #define SDIR 0x1 /* Slave Transfer Direction */ -#define nSDIR 0x0 #define GCALL 0x2 /* General Call */ -#define nGCALL 0x0 /* Bit maskes for TWIx_MASTER_CTL */ #define MEN 0x1 /* Master Mode Enable */ -#define nMEN 0x0 #define MDIR 0x4 /* Master Transfer Direction */ -#define nMDIR 0x0 #define FAST 0x8 /* Fast Mode */ -#define nFAST 0x0 #define STOP 0x10 /* Issue Stop Condition */ -#define nSTOP 0x0 #define RSTART 0x20 /* Repeat Start */ -#define nRSTART 0x0 #define DCNT 0x3fc0 /* Data Transfer Count */ #define SDAOVR 0x4000 /* Serial Data Override */ -#define nSDAOVR 0x0 #define SCLOVR 0x8000 /* Serial Clock Override */ -#define nSCLOVR 0x0 /* Bit maskes for TWIx_MASTER_ADDR */ @@ -4084,34 +3170,21 @@ /* Bit maskes for TWIx_MASTER_STAT */ #define MPROG 0x1 /* Master Transfer in Progress */ -#define nMPROG 0x0 #define LOSTARB 0x2 /* Lost Arbitration */ -#define nLOSTARB 0x0 #define ANAK 0x4 /* Address Not Acknowledged */ -#define nANAK 0x0 #define DNAK 0x8 /* Data Not Acknowledged */ -#define nDNAK 0x0 #define BUFRDERR 0x10 /* Buffer Read Error */ -#define nBUFRDERR 0x0 #define BUFWRERR 0x20 /* Buffer Write Error */ -#define nBUFWRERR 0x0 #define SDASEN 0x40 /* Serial Data Sense */ -#define nSDASEN 0x0 #define SCLSEN 0x80 /* Serial Clock Sense */ -#define nSCLSEN 0x0 #define BUSBUSY 0x100 /* Bus Busy */ -#define nBUSBUSY 0x0 /* Bit maskes for TWIx_FIFO_CTL */ #define XMTFLUSH 0x1 /* Transmit Buffer Flush */ -#define nXMTFLUSH 0x0 #define RCVFLUSH 0x2 /* Receive Buffer Flush */ -#define nRCVFLUSH 0x0 #define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */ -#define nXMTINTLEN 0x0 #define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */ -#define nRCVINTLEN 0x0 /* Bit maskes for TWIx_FIFO_STAT */ @@ -4121,40 +3194,24 @@ /* Bit maskes for TWIx_INT_MASK */ #define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */ -#define nSINITM 0x0 #define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */ -#define nSCOMPM 0x0 #define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */ -#define nSERRM 0x0 #define SOVFM 0x8 /* Slave Overflow Interrupt Mask */ -#define nSOVFM 0x0 #define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */ -#define nMCOMPM 0x0 #define MERRM 0x20 /* Master Transfer Error Interrupt Mask */ -#define nMERRM 0x0 #define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */ -#define nXMTSERVM 0x0 #define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */ -#define nRCVSERVM 0x0 /* Bit maskes for TWIx_INT_STAT */ #define SINIT 0x1 /* Slave Transfer Initiated */ -#define nSINIT 0x0 #define SCOMP 0x2 /* Slave Transfer Complete */ -#define nSCOMP 0x0 #define SERR 0x4 /* Slave Transfer Error */ -#define nSERR 0x0 #define SOVF 0x8 /* Slave Overflow */ -#define nSOVF 0x0 #define MCOMP 0x10 /* Master Transfer Complete */ -#define nMCOMP 0x0 #define MERR 0x20 /* Master Transfer Error */ -#define nMERR 0x0 #define XMTSERV 0x40 /* Transmit FIFO Service */ -#define nXMTSERV 0x0 #define RCVSERV 0x80 /* Receive FIFO Service */ -#define nRCVSERV 0x0 /* Bit maskes for TWIx_XMT_DATA8 */ @@ -4175,81 +3232,51 @@ /* Bit masks for SPORTx_TCR1 */ #define TCKFE 0x4000 /* Clock Falling Edge Select */ -#define nTCKFE 0x0 #define LATFS 0x2000 /* Late Transmit Frame Sync */ -#define nLATFS 0x0 #define LTFS 0x1000 /* Low Transmit Frame Sync Select */ -#define nLTFS 0x0 #define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */ -#define nDITFS 0x0 #define TFSR 0x400 /* Transmit Frame Sync Required Select */ -#define nTFSR 0x0 #define ITFS 0x200 /* Internal Transmit Frame Sync Select */ -#define nITFS 0x0 #define TLSBIT 0x10 /* Transmit Bit Order */ -#define nTLSBIT 0x0 #define TDTYPE 0xc /* Data Formatting Type Select */ #define ITCLK 0x2 /* Internal Transmit Clock Select */ -#define nITCLK 0x0 #define TSPEN 0x1 /* Transmit Enable */ -#define nTSPEN 0x0 /* Bit masks for SPORTx_TCR2 */ #define TRFST 0x400 /* Left/Right Order */ -#define nTRFST 0x0 #define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */ -#define nTSFSE 0x0 #define TXSE 0x100 /* TxSEC Enable */ -#define nTXSE 0x0 #define SLEN_T 0x1f /* SPORT Word Length */ /* Bit masks for SPORTx_RCR1 */ #define RCKFE 0x4000 /* Clock Falling Edge Select */ -#define nRCKFE 0x0 #define LARFS 0x2000 /* Late Receive Frame Sync */ -#define nLARFS 0x0 #define LRFS 0x1000 /* Low Receive Frame Sync Select */ -#define nLRFS 0x0 #define RFSR 0x400 /* Receive Frame Sync Required Select */ -#define nRFSR 0x0 #define IRFS 0x200 /* Internal Receive Frame Sync Select */ -#define nIRFS 0x0 #define RLSBIT 0x10 /* Receive Bit Order */ -#define nRLSBIT 0x0 #define RDTYPE 0xc /* Data Formatting Type Select */ #define IRCLK 0x2 /* Internal Receive Clock Select */ -#define nIRCLK 0x0 #define RSPEN 0x1 /* Receive Enable */ -#define nRSPEN 0x0 /* Bit masks for SPORTx_RCR2 */ #define RRFST 0x400 /* Left/Right Order */ -#define nRRFST 0x0 #define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */ -#define nRSFSE 0x0 #define RXSE 0x100 /* RxSEC Enable */ -#define nRXSE 0x0 #define SLEN_R 0x1f /* SPORT Word Length */ /* Bit masks for SPORTx_STAT */ #define TXHRE 0x40 /* Transmit Hold Register Empty */ -#define nTXHRE 0x0 #define TOVF 0x20 /* Sticky Transmit Overflow Status */ -#define nTOVF 0x0 #define TUVF 0x10 /* Sticky Transmit Underflow Status */ -#define nTUVF 0x0 #define TXF 0x8 /* Transmit FIFO Full Status */ -#define nTXF 0x0 #define ROVF 0x4 /* Sticky Receive Overflow Status */ -#define nROVF 0x0 #define RUVF 0x2 /* Sticky Receive Underflow Status */ -#define nRUVF 0x0 #define RXNE 0x1 /* Receive FIFO Not Empty Status */ -#define nRXNE 0x0 /* Bit masks for SPORTx_MCMC1 */ @@ -4260,13 +3287,9 @@ #define MFD 0xf000 /* Multi channel Frame Delay */ #define FSDR 0x80 /* Frame Sync to Data Relationship */ -#define nFSDR 0x0 #define MCMEM 0x10 /* Multi channel Frame Mode Enable */ -#define nMCMEM 0x0 #define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */ -#define nMCDRXPE 0x0 #define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */ -#define nMCDTXPE 0x0 #define MCCRM 0x3 /* 2X Clock Recovery Mode */ /* Bit masks for SPORTx_CHNL */ @@ -4280,115 +3303,59 @@ #define WLS 0x3 /* Word Length Select */ #endif #define STB 0x4 /* Stop Bits */ -#define nSTB 0x0 #define PEN 0x8 /* Parity Enable */ -#define nPEN 0x0 #define EPS 0x10 /* Even Parity Select */ -#define nEPS 0x0 #define STP 0x20 /* Sticky Parity */ -#define nSTP 0x0 #define SB 0x40 /* Set Break */ -#define nSB 0x0 /* Bit masks for UARTx_MCR */ #define XOFF 0x1 /* Transmitter Off */ -#define nXOFF 0x0 #define MRTS 0x2 /* Manual Request To Send */ -#define nMRTS 0x0 #define RFIT 0x4 /* Receive FIFO IRQ Threshold */ -#define nRFIT 0x0 #define RFRT 0x8 /* Receive FIFO RTS Threshold */ -#define nRFRT 0x0 #define LOOP_ENA 0x10 /* Loopback Mode Enable */ -#define nLOOP_ENA 0x0 #define FCPOL 0x20 /* Flow Control Pin Polarity */ -#define nFCPOL 0x0 #define ARTS 0x40 /* Automatic Request To Send */ -#define nARTS 0x0 #define ACTS 0x80 /* Automatic Clear To Send */ -#define nACTS 0x0 /* Bit masks for UARTx_LSR */ #define DR 0x1 /* Data Ready */ -#define nDR 0x0 #define OE 0x2 /* Overrun Error */ -#define nOE 0x0 #define PE 0x4 /* Parity Error */ -#define nPE 0x0 #define FE 0x8 /* Framing Error */ -#define nFE 0x0 #define BI 0x10 /* Break Interrupt */ -#define nBI 0x0 #define THRE 0x20 /* THR Empty */ -#define nTHRE 0x0 #define TEMT 0x40 /* Transmitter Empty */ -#define nTEMT 0x0 #define TFI 0x80 /* Transmission Finished Indicator */ -#define nTFI 0x0 /* Bit masks for UARTx_MSR */ #define SCTS 0x1 /* Sticky CTS */ -#define nSCTS 0x0 #define CTS 0x10 /* Clear To Send */ -#define nCTS 0x0 #define RFCS 0x20 /* Receive FIFO Count Status */ -#define nRFCS 0x0 - -/* Bit masks for UARTx_IER_SET */ - -#define ERBFI_S 0x1 /* Enable Receive Buffer Full Interrupt */ -#define nERBFI_S 0x0 -#define ETBEI_S 0x2 /* Enable Transmit Buffer Empty Interrupt */ -#define nETBEI_S 0x0 -#define ELSI_S 0x4 /* Enable Receive Status Interrupt */ -#define nELSI_S 0x0 -#define EDSSI_S 0x8 /* Enable Modem Status Interrupt */ -#define nEDSSI_S 0x0 -#define EDTPTI_S 0x10 /* Enable DMA Transmit PIRQ Interrupt */ -#define nEDTPTI_S 0x0 -#define ETFI_S 0x20 /* Enable Transmission Finished Interrupt */ -#define nETFI_S 0x0 -#define ERFCI_S 0x40 /* Enable Receive FIFO Count Interrupt */ -#define nERFCI_S 0x0 - -/* Bit masks for UARTx_IER_CLEAR */ - -#define ERBFI_C 0x1 /* Enable Receive Buffer Full Interrupt */ -#define nERBFI_C 0x0 -#define ETBEI_C 0x2 /* Enable Transmit Buffer Empty Interrupt */ -#define nETBEI_C 0x0 -#define ELSI_C 0x4 /* Enable Receive Status Interrupt */ -#define nELSI_C 0x0 -#define EDSSI_C 0x8 /* Enable Modem Status Interrupt */ -#define nEDSSI_C 0x0 -#define EDTPTI_C 0x10 /* Enable DMA Transmit PIRQ Interrupt */ -#define nEDTPTI_C 0x0 -#define ETFI_C 0x20 /* Enable Transmission Finished Interrupt */ -#define nETFI_C 0x0 -#define ERFCI_C 0x40 /* Enable Receive FIFO Count Interrupt */ -#define nERFCI_C 0x0 + +/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */ + +#define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */ +#define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */ +#define ELSI 0x4 /* Enable Receive Status Interrupt */ +#define EDSSI 0x8 /* Enable Modem Status Interrupt */ +#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */ +#define ETFI 0x20 /* Enable Transmission Finished Interrupt */ +#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */ /* Bit masks for UARTx_GCTL */ #define UCEN 0x1 /* UART Enable */ -#define nUCEN 0x0 #define IREN 0x2 /* IrDA Mode Enable */ -#define nIREN 0x0 #define TPOLC 0x4 /* IrDA TX Polarity Change */ -#define nTPOLC 0x0 #define RPOLC 0x8 /* IrDA RX Polarity Change */ -#define nRPOLC 0x0 #define FPE 0x10 /* Force Parity Error */ -#define nFPE 0x0 #define FFE 0x20 /* Force Framing Error */ -#define nFFE 0x0 #define EDBO 0x40 /* Enable Divide-by-One */ -#define nEDBO 0x0 #define EGLSI 0x80 /* Enable Global LS Interrupt */ -#define nEGLSI 0x0 /* ******************************************* */ diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h index 5a334c8..fcc8b4c 100644 --- a/include/asm-blackfin/mach-bf548/dma.h +++ b/include/asm-blackfin/mach-bf548/dma.h @@ -44,7 +44,6 @@ #define CH_UART1_TX 9 #define CH_ATAPI_RX 10 #define CH_ATAPI_TX 11 - #define CH_EPPI0 12 #define CH_EPPI1 13 #define CH_EPPI2 14 @@ -58,6 +57,17 @@ #define CH_SDH 22 #define CH_SPI2 23 -#define MAX_BLACKFIN_DMA_CHANNEL CH_SPI2 +#define CH_MEM_STREAM0_DEST 24 +#define CH_MEM_STREAM0_SRC 25 +#define CH_MEM_STREAM1_DEST 26 +#define CH_MEM_STREAM1_SRC 27 +#define CH_MEM_STREAM2_DEST 28 +#define CH_MEM_STREAM2_SRC 29 +#define CH_MEM_STREAM3_DEST 30 +#define CH_MEM_STREAM3_SRC 31 + +#define MAX_BLACKFIN_DMA_CHANNEL 32 +extern int channel2irq(unsigned int channel); +extern struct dma_register *base_addr[]; #endif diff --git a/include/asm-blackfin/mach-bf548/gpio.h b/include/asm-blackfin/mach-bf548/gpio.h new file mode 100644 index 0000000..4528942 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/gpio.h @@ -0,0 +1,212 @@ +/* + * File: include/asm-blackfin/mach-bf548/gpio.h + * Based on: + * Author: Michael Hennerich (hennerich@blackfin.uclinux.org) + * + * Created: + * Description: + * + * Modified: + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + + +#define GPIO_PA0 0 +#define GPIO_PA1 1 +#define GPIO_PA2 2 +#define GPIO_PA3 3 +#define GPIO_PA4 4 +#define GPIO_PA5 5 +#define GPIO_PA6 6 +#define GPIO_PA7 7 +#define GPIO_PA8 8 +#define GPIO_PA9 9 +#define GPIO_PA10 10 +#define GPIO_PA11 11 +#define GPIO_PA12 12 +#define GPIO_PA13 13 +#define GPIO_PA14 14 +#define GPIO_PA15 15 +#define GPIO_PB0 16 +#define GPIO_PB1 17 +#define GPIO_PB2 18 +#define GPIO_PB3 19 +#define GPIO_PB4 20 +#define GPIO_PB5 21 +#define GPIO_PB6 22 +#define GPIO_PB7 23 +#define GPIO_PB8 24 +#define GPIO_PB9 25 +#define GPIO_PB10 26 +#define GPIO_PB11 27 +#define GPIO_PB12 28 +#define GPIO_PB13 29 +#define GPIO_PB14 30 +#define GPIO_PB15 31 /* N/A */ +#define GPIO_PC0 32 +#define GPIO_PC1 33 +#define GPIO_PC2 34 +#define GPIO_PC3 35 +#define GPIO_PC4 36 +#define GPIO_PC5 37 +#define GPIO_PC6 38 +#define GPIO_PC7 39 +#define GPIO_PC8 40 +#define GPIO_PC9 41 +#define GPIO_PC10 42 +#define GPIO_PC11 43 +#define GPIO_PC12 44 +#define GPIO_PC13 45 +#define GPIO_PC14 46 /* N/A */ +#define GPIO_PC15 47 /* N/A */ +#define GPIO_PD0 48 +#define GPIO_PD1 49 +#define GPIO_PD2 50 +#define GPIO_PD3 51 +#define GPIO_PD4 52 +#define GPIO_PD5 53 +#define GPIO_PD6 54 +#define GPIO_PD7 55 +#define GPIO_PD8 56 +#define GPIO_PD9 57 +#define GPIO_PD10 58 +#define GPIO_PD11 59 +#define GPIO_PD12 60 +#define GPIO_PD13 61 +#define GPIO_PD14 62 +#define GPIO_PD15 63 +#define GPIO_PE0 64 +#define GPIO_PE1 65 +#define GPIO_PE2 66 +#define GPIO_PE3 67 +#define GPIO_PE4 68 +#define GPIO_PE5 69 +#define GPIO_PE6 70 +#define GPIO_PE7 71 +#define GPIO_PE8 72 +#define GPIO_PE9 73 +#define GPIO_PE10 74 +#define GPIO_PE11 75 +#define GPIO_PE12 76 +#define GPIO_PE13 77 +#define GPIO_PE14 78 +#define GPIO_PE15 79 +#define GPIO_PF0 80 +#define GPIO_PF1 81 +#define GPIO_PF2 82 +#define GPIO_PF3 83 +#define GPIO_PF4 84 +#define GPIO_PF5 85 +#define GPIO_PF6 86 +#define GPIO_PF7 87 +#define GPIO_PF8 88 +#define GPIO_PF9 89 +#define GPIO_PF10 90 +#define GPIO_PF11 91 +#define GPIO_PF12 92 +#define GPIO_PF13 93 +#define GPIO_PF14 94 +#define GPIO_PF15 95 +#define GPIO_PG0 96 +#define GPIO_PG1 97 +#define GPIO_PG2 98 +#define GPIO_PG3 99 +#define GPIO_PG4 100 +#define GPIO_PG5 101 +#define GPIO_PG6 102 +#define GPIO_PG7 103 +#define GPIO_PG8 104 +#define GPIO_PG9 105 +#define GPIO_PG10 106 +#define GPIO_PG11 107 +#define GPIO_PG12 108 +#define GPIO_PG13 109 +#define GPIO_PG14 110 +#define GPIO_PG15 111 +#define GPIO_PH0 112 +#define GPIO_PH1 113 +#define GPIO_PH2 114 +#define GPIO_PH3 115 +#define GPIO_PH4 116 +#define GPIO_PH5 117 +#define GPIO_PH6 118 +#define GPIO_PH7 119 +#define GPIO_PH8 120 +#define GPIO_PH9 121 +#define GPIO_PH10 122 +#define GPIO_PH11 123 +#define GPIO_PH12 124 +#define GPIO_PH13 125 +#define GPIO_PH14 126 /* N/A */ +#define GPIO_PH15 127 /* N/A */ +#define GPIO_PI0 128 +#define GPIO_PI1 129 +#define GPIO_PI2 130 +#define GPIO_PI3 131 +#define GPIO_PI4 132 +#define GPIO_PI5 133 +#define GPIO_PI6 134 +#define GPIO_PI7 135 +#define GPIO_PI8 136 +#define GPIO_PI9 137 +#define GPIO_PI10 138 +#define GPIO_PI11 139 +#define GPIO_PI12 140 +#define GPIO_PI13 141 +#define GPIO_PI14 142 +#define GPIO_PI15 143 +#define GPIO_PJ0 144 +#define GPIO_PJ1 145 +#define GPIO_PJ2 146 +#define GPIO_PJ3 147 +#define GPIO_PJ4 148 +#define GPIO_PJ5 149 +#define GPIO_PJ6 150 +#define GPIO_PJ7 151 +#define GPIO_PJ8 152 +#define GPIO_PJ9 153 +#define GPIO_PJ10 154 +#define GPIO_PJ11 155 +#define GPIO_PJ12 156 +#define GPIO_PJ13 157 +#define GPIO_PJ14 158 +#define GPIO_PJ15 159 + +#define MAX_BLACKFIN_GPIOS 160 + +struct gpio_port_t { + unsigned short port_fer; + unsigned short dummy1; + unsigned short port_data; + unsigned short dummy2; + unsigned short port_set; + unsigned short dummy3; + unsigned short port_clear; + unsigned short dummy4; + unsigned short port_dir_set; + unsigned short dummy5; + unsigned short port_dir_clear; + unsigned short dummy6; + unsigned short port_inen; + unsigned short dummy7; + unsigned int port_mux; +}; + diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h index a7f6703..93f5db0 100644 --- a/include/asm-blackfin/mach-bf548/irq.h +++ b/include/asm-blackfin/mach-bf548/irq.h @@ -51,7 +51,7 @@ Events (highest priority) EMU 0 (lowest priority) IVG15 32 * */ -#define NR_PERI_INTS 32 +#define NR_PERI_INTS (32 * 3) /* The ABSTRACT IRQ definitions */ /** the first seven of the following are fixed, the rest you change if you need to **/ @@ -92,7 +92,7 @@ Events (highest priority) EMU 0 #define IRQ_DMAC1_ERR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ #define IRQ_SPORT2_ERR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ #define IRQ_SPORT3_ERR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ -#define IRQ_MXVR BFIN_IRQ(27) /* SPORT3 Error Interrupt */ +#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */ #define IRQ_SPI1_ERR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */ #define IRQ_SPI2_ERR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */ #define IRQ_UART1_ERR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */ @@ -102,8 +102,8 @@ Events (highest priority) EMU 0 #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ -#define IRQ_EPP1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ -#define IRQ_EPP2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ +#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ +#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ #define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */ #define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */ @@ -143,14 +143,14 @@ Events (highest priority) EMU 0 #define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */ #define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */ #define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */ -#define IRQ_TMR0 BFIN_IRQ(86) /* Timer 0 Interrupt */ -#define IRQ_TMR1 BFIN_IRQ(87) /* Timer 1 Interrupt */ -#define IRQ_TMR2 BFIN_IRQ(88) /* Timer 2 Interrupt */ -#define IRQ_TMR3 BFIN_IRQ(89) /* Timer 3 Interrupt */ -#define IRQ_TMR4 BFIN_IRQ(90) /* Timer 4 Interrupt */ -#define IRQ_TMR5 BFIN_IRQ(91) /* Timer 5 Interrupt */ -#define IRQ_TMR6 BFIN_IRQ(92) /* Timer 6 Interrupt */ -#define IRQ_TMR7 BFIN_IRQ(93) /* Timer 7 Interrupt */ +#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */ +#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */ +#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */ +#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */ +#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */ +#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */ +#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */ +#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */ #define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ #define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ @@ -248,9 +248,9 @@ Events (highest priority) EMU 0 #ifdef CONFIG_IRQCHIP_DEMUX_GPIO -#define NR_IRQS (IRQ_PH15+1) +#define NR_IRQS (IRQ_PE15+1) #else -#define NR_IRQS (IRQ_UART1_ERROR+1) +#define NR_IRQS (SYS_IRQS+1) #endif #define IVG7 7 @@ -263,44 +263,116 @@ Events (highest priority) EMU 0 #define IVG14 14 #define IVG15 15 -/* IAR0 BIT FIELDS*/ -#define IRQ_PLL_WAKEUP_POS 0 -#define IRQ_DMA_ERROR_POS 4 -#define IRQ_ERROR_POS 8 -#define IRQ_RTC_POS 12 -#define IRQ_PPI_POS 16 -#define IRQ_SPORT0_RX_POS 20 -#define IRQ_SPORT0_TX_POS 24 -#define IRQ_SPORT1_RX_POS 28 +/* IAR0 BIT FIELDS */ +#define IRQ_PLL_WAKEUP_POS 0 +#define IRQ_DMAC0_ERR_POS 4 +#define IRQ_EPPI0_ERR_POS 8 +#define IRQ_SPORT0_ERR_POS 12 +#define IRQ_SPORT1_ERR_POS 16 +#define IRQ_SPI0_ERR_POS 20 +#define IRQ_UART0_ERR_POS 24 +#define IRQ_RTC_POS 28 -/* IAR1 BIT FIELDS*/ -#define IRQ_SPORT1_TX_POS 0 -#define IRQ_TWI_POS 4 -#define IRQ_SPI_POS 8 -#define IRQ_UART0_RX_POS 12 -#define IRQ_UART0_TX_POS 16 -#define IRQ_UART1_RX_POS 20 -#define IRQ_UART1_TX_POS 24 -#define IRQ_CAN_RX_POS 28 +/* IAR1 BIT FIELDS */ +#define IRQ_EPPI0_POS 0 +#define IRQ_SPORT0_RX_POS 4 +#define IRQ_SPORT0_TX_POS 8 +#define IRQ_SPORT1_RX_POS 12 +#define IRQ_SPORT1_TX_POS 16 +#define IRQ_SPI0_POS 20 +#define IRQ_UART0_RX_POS 24 +#define IRQ_UART0_TX_POS 28 -/* IAR2 BIT FIELDS*/ -#define IRQ_CAN_TX_POS 0 -#define IRQ_MAC_RX_POS 4 -#define IRQ_MAC_TX_POS 8 -#define IRQ_TMR0_POS 12 -#define IRQ_TMR1_POS 16 -#define IRQ_TMR2_POS 20 -#define IRQ_TMR3_POS 24 -#define IRQ_TMR4_POS 28 +/* IAR2 BIT FIELDS */ +#define IRQ_TIMER8_POS 0 +#define IRQ_TIMER9_POS 4 +#define IRQ_TIMER10_POS 8 +#define IRQ_PINT0_POS 12 +#define IRQ_PINT1_POS 16 +#define IRQ_MDMAS0_POS 20 +#define IRQ_MDMAS1_POS 24 +#define IRQ_WATCHDOG_POS 28 -/* IAR3 BIT FIELDS*/ -#define IRQ_TMR5_POS 0 -#define IRQ_TMR6_POS 4 -#define IRQ_TMR7_POS 8 -#define IRQ_PROG_INTA_POS 12 -#define IRQ_PORTG_INTB_POS 16 -#define IRQ_MEM_DMA0_POS 20 -#define IRQ_MEM_DMA1_POS 24 -#define IRQ_WATCH_POS 28 +/* IAR3 BIT FIELDS */ +#define IRQ_DMAC1_ERR_POS 0 +#define IRQ_SPORT2_ERR_POS 4 +#define IRQ_SPORT3_ERR_POS 8 +#define IRQ_MXVR_DATA_POS 12 +#define IRQ_SPI1_ERR_POS 16 +#define IRQ_SPI2_ERR_POS 20 +#define IRQ_UART1_ERR_POS 24 +#define IRQ_UART2_ERR_POS 28 -#endif /* _BF537_IRQ_H_ */ +/* IAR4 BIT FILEDS */ +#define IRQ_CAN0_ERR_POS 0 +#define IRQ_SPORT2_RX_POS 4 +#define IRQ_SPORT2_TX_POS 8 +#define IRQ_SPORT3_RX_POS 12 +#define IRQ_SPORT3_TX_POS 16 +#define IRQ_EPPI1_POS 20 +#define IRQ_EPPI2_POS 24 +#define IRQ_SPI1_POS 28 + +/* IAR5 BIT FIELDS */ +#define IRQ_SPI2_POS 0 +#define IRQ_UART1_RX_POS 4 +#define IRQ_UART1_TX_POS 8 +#define IRQ_ATAPI_RX_POS 12 +#define IRQ_ATAPI_TX_POS 16 +#define IRQ_TWI0_POS 20 +#define IRQ_TWI1_POS 24 +#define IRQ_CAN0_RX_POS 28 + +/* IAR6 BIT FIELDS */ +#define IRQ_CAN0_TX_POS 0 +#define IRQ_MDMAS2_POS 4 +#define IRQ_MDMAS3_POS 8 +#define IRQ_MXVR_ERR_POS 12 +#define IRQ_MXVR_MSG_POS 16 +#define IRQ_MXVR_PKT_POS 20 +#define IRQ_EPPI1_ERR_POS 24 +#define IRQ_EPPI2_ERR_POS 28 + +/* IAR7 BIT FIELDS */ +#define IRQ_UART3_ERR_POS 0 +#define IRQ_HOST_ERR_POS 4 +#define IRQ_PIXC_ERR_POS 12 +#define IRQ_NFC_ERR_POS 16 +#define IRQ_ATAPI_ERR_POS 20 +#define IRQ_CAN1_ERR_POS 24 +#define IRQ_HS_DMA_ERR_POS 28 + +/* IAR8 BIT FIELDS */ +#define IRQ_PIXC_IN0_POS 0 +#define IRQ_PIXC_IN1_POS 4 +#define IRQ_PIXC_OUT_POS 8 +#define IRQ_SDH_POS 12 +#define IRQ_CNT_POS 16 +#define IRQ_KEY_POS 20 +#define IRQ_CAN1_RX_POS 24 +#define IRQ_CAN1_TX_POS 28 + +/* IAR9 BIT FIELDS */ +#define IRQ_SDH_MASK0_POS 0 +#define IRQ_SDH_MASK1_POS 4 +#define IRQ_USB_INT0_POS 12 +#define IRQ_USB_INT1_POS 16 +#define IRQ_USB_INT2_POS 20 +#define IRQ_USB_DMA_POS 24 +#define IRQ_OTPSEC_POS 28 + +/* IAR10 BIT FIELDS */ +#define IRQ_TIMER0_POS 24 +#define IRQ_TIMER1_POS 28 + +/* IAR11 BIT FIELDS */ +#define IRQ_TIMER2_POS 0 +#define IRQ_TIMER3_POS 4 +#define IRQ_TIMER4_POS 8 +#define IRQ_TIMER5_POS 12 +#define IRQ_TIMER6_POS 16 +#define IRQ_TIMER7_POS 20 +#define IRQ_PINT2_POS 24 +#define IRQ_PINT3_POS 28 + +#endif /* _BF548_IRQ_H_ */ diff --git a/include/asm-blackfin/mach-bf561/dma.h b/include/asm-blackfin/mach-bf561/dma.h index 21d9820..766334b 100644 --- a/include/asm-blackfin/mach-bf561/dma.h +++ b/include/asm-blackfin/mach-bf561/dma.h @@ -32,4 +32,7 @@ #define CH_IMEM_STREAM1_SRC 34 #define CH_IMEM_STREAM1_DEST 35 +extern int channel2irq(unsigned int channel); +extern struct dma_register *base_addr[]; + #endif -- cgit v0.10.2 From 0ba9e350a2c129ce2878d415cf51e88611cbc0e5 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 2 Jul 2007 13:47:45 +0800 Subject: Blackfin arch: new kernel config for BF548-EZKIT Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig new file mode 100644 index 0000000..ac8390f --- /dev/null +++ b/arch/blackfin/configs/BF548-EZKIT_defconfig @@ -0,0 +1,1100 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.21.5 +# +# CONFIG_MMU is not set +# CONFIG_FPU is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +CONFIG_BLACKFIN=y +CONFIG_ZONE_DMA=y +CONFIG_BFIN=y +CONFIG_SEMAPHORE_SLEEPERS=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_IRQCHIP_DEMUX_GPIO=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 +# CONFIG_NP2 is not set +CONFIG_SLAB=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y +CONFIG_BASE_SMALL=0 +# CONFIG_SLOB is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set + +# +# Blackfin Processor Options +# + +# +# Processor and Board Settings +# +# CONFIG_BF531 is not set +# CONFIG_BF532 is not set +# CONFIG_BF533 is not set +# CONFIG_BF534 is not set +# CONFIG_BF536 is not set +# CONFIG_BF537 is not set +# CONFIG_BF542 is not set +# CONFIG_BF544 is not set +# CONFIG_BF548 is not set +CONFIG_BF549=y +# CONFIG_BF561 is not set +CONFIG_BF_REV_0_0=y +# CONFIG_BF_REV_0_2 is not set +# CONFIG_BF_REV_0_3 is not set +# CONFIG_BF_REV_0_4 is not set +# CONFIG_BF_REV_0_5 is not set +# CONFIG_BF_REV_ANY is not set +# CONFIG_BF_REV_NONE is not set +CONFIG_BF54x=y +CONFIG_BFIN_SINGLE_CORE=y +# CONFIG_BFIN533_EZKIT is not set +# CONFIG_BFIN533_STAMP is not set +# CONFIG_BFIN537_STAMP is not set +# CONFIG_BFIN533_BLUETECHNIX_CM is not set +# CONFIG_BFIN537_BLUETECHNIX_CM is not set +CONFIG_BFIN548_EZKIT=y +# CONFIG_BFIN561_BLUETECHNIX_CM is not set +# CONFIG_BFIN561_EZKIT is not set +# CONFIG_BFIN561_TEPLA is not set +# CONFIG_PNAV10 is not set +# CONFIG_GENERIC_BOARD is not set +CONFIG_IRQ_PLL_WAKEUP=7 +CONFIG_IRQ_TIMER0=11 +CONFIG_IRQ_TIMER1=11 +CONFIG_IRQ_TIMER2=11 +CONFIG_IRQ_TIMER3=11 +CONFIG_IRQ_TIMER4=11 +CONFIG_IRQ_TIMER5=11 +CONFIG_IRQ_TIMER6=11 +CONFIG_IRQ_TIMER7=11 +CONFIG_IRQ_TIMER8=11 +CONFIG_IRQ_TIMER9=11 +CONFIG_IRQ_TIMER10=11 +CONFIG_IRQ_RTC=8 +CONFIG_IRQ_SPORT0_RX=9 +CONFIG_IRQ_SPORT0_TX=9 +CONFIG_IRQ_SPORT1_RX=9 +CONFIG_IRQ_SPORT1_TX=9 +CONFIG_IRQ_UART0_RX=10 +CONFIG_IRQ_UART0_TX=10 +CONFIG_IRQ_UART1_RX=10 +CONFIG_IRQ_UART1_TX=10 + +# +# BF548 Specific Configuration +# + +# +# Interrupt Priority Assignment +# + +# +# Priority +# +CONFIG_IRQ_DMAC0_ERR=7 +CONFIG_IRQ_EPPI0_ERR=7 +CONFIG_IRQ_SPORT0_ERR=7 +CONFIG_IRQ_SPORT1_ERR=7 +CONFIG_IRQ_SPI0_ERR=7 +CONFIG_IRQ_UART0_ERR=7 +CONFIG_IRQ_EPPI0=8 +CONFIG_IRQ_SPI0=10 +CONFIG_IRQ_PINT0=12 +CONFIG_IRQ_PINT1=12 +CONFIG_IRQ_MDMAS0=13 +CONFIG_IRQ_MDMAS1=13 +CONFIG_IRQ_WATCHDOG=13 +CONFIG_IRQ_DMAC1_ERR=7 +CONFIG_IRQ_SPORT2_ERR=7 +CONFIG_IRQ_SPORT3_ERR=7 +CONFIG_IRQ_MXVR_DATA=7 +CONFIG_IRQ_SPI1_ERR=7 +CONFIG_IRQ_SPI2_ERR=7 +CONFIG_IRQ_UART1_ERR=7 +CONFIG_IRQ_UART2_ERR=7 +CONFIG_IRQ_CAN0_ERR=7 +CONFIG_IRQ_SPORT2_RX=9 +CONFIG_IRQ_SPORT2_TX=9 +CONFIG_IRQ_SPORT3_RX=9 +CONFIG_IRQ_SPORT3_TX=9 +CONFIG_IRQ_EPPI1=9 +CONFIG_IRQ_EPPI2=9 +CONFIG_IRQ_SPI1=10 +CONFIG_IRQ_SPI2=10 +CONFIG_IRQ_ATAPI_RX=10 +CONFIG_IRQ_ATAPI_TX=10 +CONFIG_IRQ_TWI0=11 +CONFIG_IRQ_TWI1=11 +CONFIG_IRQ_CAN0_RX=11 +CONFIG_IRQ_CAN0_TX=11 +CONFIG_IRQ_MDMAS2=13 +CONFIG_IRQ_MDMAS3=13 +CONFIG_IRQ_MXVR_ERR=11 +CONFIG_IRQ_MXVR_MSG=11 +CONFIG_IRQ_MXVR_PKT=11 +CONFIG_IRQ_EPPI1_ERR=7 +CONFIG_IRQ_EPPI2_ERR=7 +CONFIG_IRQ_UART3_ERR=7 +CONFIG_IRQ_HOST_ERR=7 +CONFIG_IRQ_PIXC_ERR=7 +CONFIG_IRQ_NFC_ERR=7 +CONFIG_IRQ_ATAPI_ERR=7 +CONFIG_IRQ_CAN1_ERR=7 +CONFIG_IRQ_HS_DMA_ERR=7 +CONFIG_IRQ_PIXC_IN0=8 +CONFIG_IRQ_PIXC_IN1=8 +CONFIG_IRQ_PIXC_OUT=8 +CONFIG_IRQ_SDH=8 +CONFIG_IRQ_CNT=8 +CONFIG_IRQ_KEY=8 +CONFIG_IRQ_CAN1_RX=11 +CONFIG_IRQ_CAN1_TX=11 +CONFIG_IRQ_SDH_MASK0=11 +CONFIG_IRQ_SDH_MASK1=11 +CONFIG_IRQ_USB_INT0=11 +CONFIG_IRQ_USB_INT1=11 +CONFIG_IRQ_USB_INT2=11 +CONFIG_IRQ_USB_DMA=11 +CONFIG_IRQ_OTPSEC=11 +CONFIG_IRQ_PINT2=11 +CONFIG_IRQ_PINT3=11 + +# +# Board customizations +# +# CONFIG_CMDLINE_BOOL is not set + +# +# Board Setup +# +CONFIG_CLKIN_HZ=25000000 +CONFIG_MEM_SIZE=64 +CONFIG_MEM_ADD_WIDTH=10 +CONFIG_BOOT_LOAD=0x1000 + +# +# Blackfin Kernel Optimizations +# + +# +# Timer Tick +# +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 + +# +# Memory Optimizations +# +CONFIG_I_ENTRY_L1=y +CONFIG_EXCPT_IRQ_SYSC_L1=y +CONFIG_DO_IRQ_L1=y +CONFIG_CORE_TIMER_IRQ_L1=y +CONFIG_IDLE_L1=y +CONFIG_SCHEDULE_L1=y +CONFIG_ARITHMETIC_OPS_L1=y +CONFIG_ACCESS_OK_L1=y +CONFIG_MEMSET_L1=y +CONFIG_MEMCPY_L1=y +CONFIG_SYS_BFIN_SPINLOCK_L1=y +# CONFIG_IP_CHECKSUM_L1 is not set +CONFIG_CACHELINE_ALIGNED_L1=y +# CONFIG_SYSCALL_TAB_L1 is not set +# CONFIG_CPLB_SWITCH_TAB_L1 is not set +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LARGE_ALLOCS=y +CONFIG_BFIN_DMA_5XX=y +# CONFIG_DMA_UNCACHED_2M is not set +CONFIG_DMA_UNCACHED_1M=y +# CONFIG_DMA_UNCACHED_NONE is not set + +# +# Cache Support +# +CONFIG_BLKFIN_CACHE=y +CONFIG_BLKFIN_DCACHE=y +# CONFIG_BLKFIN_DCACHE_BANKA is not set +# CONFIG_BLKFIN_CACHE_LOCK is not set +# CONFIG_BLKFIN_WB is not set +CONFIG_BLKFIN_WT=y +CONFIG_L1_MAX_PIECE=16 + +# +# Clock Settings +# +# CONFIG_BFIN_KERNEL_CLOCK is not set + +# +# Asynchonous Memory Configuration +# + +# +# EBIU_AMBCTL Global Control +# +CONFIG_C_AMCKEN=y +CONFIG_C_CDPRIO=y +# CONFIG_C_AMBEN is not set +# CONFIG_C_AMBEN_B0 is not set +# CONFIG_C_AMBEN_B0_B1 is not set +# CONFIG_C_AMBEN_B0_B1_B2 is not set +CONFIG_C_AMBEN_ALL=y + +# +# EBIU_AMBCTL Control +# +CONFIG_BANK_0=0x7BB0 +CONFIG_BANK_1=0x7BB0 +CONFIG_BANK_2=0x7BB0 +CONFIG_BANK_3=0x99B3 + +# +# Bus options (PCI, PCMCIA, EISA, MCA, ISA) +# +# CONFIG_PCI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# PCI Hotplug Support +# + +# +# Executable file formats +# +CONFIG_BINFMT_ELF_FDPIC=y +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +# CONFIG_BINFMT_SHARED_FLAT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_NETDEBUG is not set +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETLABEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set + +# +# TIPC Configuration (EXPERIMENTAL) +# +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_RAM=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +# CONFIG_MTD_BF5xx is not set +CONFIG_MTD_UCLINUX=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# OneNAND Flash Device Drivers +# +# CONFIG_MTD_ONENAND is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# Misc devices +# + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_NETLINK is not set + +# +# Serial ATA (prod) and Parallel ATA (experimental) drivers +# +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# I2O device support +# + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# PHY device support +# +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_SMC91X is not set +# CONFIG_SMSC911X is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# + +# +# Token Ring devices +# + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_UINPUT is not set +# CONFIG_BF53X_PFBUTTONS is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PFLAGS is not set +# CONFIG_BF5xx_PPIFCD is not set +# CONFIG_BF5xx_TIMERS is not set +# CONFIG_BF5xx_PPI is not set +# CONFIG_BFIN_SPORT is not set +# CONFIG_BFIN_TIMER_LATENCY is not set +# CONFIG_BF5xx_FBDMA is not set +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_BFIN=y +CONFIG_SERIAL_BFIN_CONSOLE=y +# CONFIG_SERIAL_BFIN_DMA is not set +CONFIG_SERIAL_BFIN_PIO=y +# CONFIG_SERIAL_BFIN_UART0 is not set +CONFIG_SERIAL_BFIN_UART1=y +# CONFIG_BFIN_UART1_CTSRTS is not set +# CONFIG_SERIAL_BFIN_UART2 is not set +# CONFIG_SERIAL_BFIN_UART3 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_BFIN_SPORT is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set + +# +# CAN, the car bus and industrial fieldbus +# +# CONFIG_CAN4LINUX is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=y +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +# CONFIG_FB is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# InfiniBand support +# + +# +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set + +# +# RTC drivers +# +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_TEST is not set +# CONFIG_RTC_DRV_V3020 is not set +CONFIG_RTC_DRV_BFIN=y + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# Auxiliary Display support +# + +# +# Virtualization +# + +# +# PBX support +# +# CONFIG_PBX is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +CONFIG_FRAME_POINTER=y +CONFIG_FORCED_INLINING=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_DEBUG_HWERR=y +# CONFIG_DEBUG_ICACHE_CHECK is not set +# CONFIG_DEBUG_KERNEL_START is not set +# CONFIG_DEBUG_SERIAL_EARLY_INIT is not set +CONFIG_DEBUG_HUNT_FOR_ZERO=y +# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set +CONFIG_CPLB_INFO=y +CONFIG_ACCESS_CHECK=y + +# +# Security options +# +# CONFIG_KEYS is not set +CONFIG_SECURITY=y +# CONFIG_SECURITY_NETWORK is not set +CONFIG_SECURITY_CAPABILITIES=y + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y -- cgit v0.10.2 From 7adfb58fbd0a27469d26536f99b66391c4c8e2a0 Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Thu, 21 Jun 2007 11:34:16 +0800 Subject: Blackfin arch: defines and provides entry points for certain user space functions at fixed addresses This patch defines (and provides) entry points for certain user space functions at fixed addresses. The Blackfin has no usable atomic instructions, but we can ensure that these code sequences appear atomic from a user space point of view by detecting when we're in the process of executing them during the interrupt handler return path. This allows much more efficient pthread lock implementations than the bfin_spinlock syscall we're currently using. Also provided is a small sys_rt_sigreturn stub which can be used by the signal handler setup code. The signal.c part will be committed separately. Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile index 93d2140..b7b6de8 100644 --- a/arch/blackfin/kernel/Makefile +++ b/arch/blackfin/kernel/Makefile @@ -6,7 +6,8 @@ extra-y := init_task.o vmlinux.lds obj-y := \ entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ - sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o + sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o \ + fixed_code.o obj-$(CONFIG_BF53x) += bfin_gpio.o obj-$(CONFIG_BF561) += bfin_gpio.o diff --git a/arch/blackfin/kernel/fixed_code.S b/arch/blackfin/kernel/fixed_code.S new file mode 100644 index 0000000..99ea296 --- /dev/null +++ b/arch/blackfin/kernel/fixed_code.S @@ -0,0 +1,132 @@ +/* + * This file contains sequences of code that will be copied to a + * fixed location, defined in . The interrupt + * handlers ensure that these sequences appear to be atomic when + * executed from userspace. + * These are aligned to 16 bytes, so that we have some space to replace + * these sequences with something else (e.g. kernel traps if we ever do + * BF561 SMP). + */ +#include +#include +#include + +.text +ENTRY(_fixed_code_start) + +.align 16 +ENTRY(_sigreturn_stub) + P0 = __NR_rt_sigreturn; + EXCPT 0; + /* Speculative execution paranoia. */ +0: JUMP.S 0b; +ENDPROC (_sigreturn_stub) + +.align 16 + /* + * Atomic swap, 8 bit. + * Inputs: P0: memory address to use + * R1: value to store + * Output: R0: old contents of the memory address, zero extended. + */ +ENTRY(_atomic_xchg32) + R0 = [P0]; + [P0] = R1; + rts; +ENDPROC (_atomic_xchg32) + +.align 16 + /* + * Compare and swap, 32 bit. + * Inputs: P0: memory address to use + * R1: compare value + * R2: new value to store + * The new value is stored if the contents of the memory + * address is equal to the compare value. + * Output: R0: old contents of the memory address. + */ +ENTRY(_atomic_cas32) + R0 = [P0]; + CC = R0 == R1; + IF !CC JUMP 1f; + [P0] = R2; +1: + rts; +ENDPROC (_atomic_cas32) + +.align 16 + /* + * Atomic add, 32 bit. + * Inputs: P0: memory address to use + * R0: value to add + * Outputs: R0: new contents of the memory address. + * R1: previous contents of the memory address. + */ +ENTRY(_atomic_add32) + R1 = [P0]; + R0 = R1 + R0; + [P0] = R0; + rts; +ENDPROC (_atomic_add32) + +.align 16 + /* + * Atomic sub, 32 bit. + * Inputs: P0: memory address to use + * R0: value to subtract + * Outputs: R0: new contents of the memory address. + * R1: previous contents of the memory address. + */ +ENTRY(_atomic_sub32) + R1 = [P0]; + R0 = R1 - R0; + [P0] = R0; + rts; +ENDPROC (_atomic_sub32) + +.align 16 + /* + * Atomic ior, 32 bit. + * Inputs: P0: memory address to use + * R0: value to ior + * Outputs: R0: new contents of the memory address. + * R1: previous contents of the memory address. + */ +ENTRY(_atomic_ior32) + R1 = [P0]; + R0 = R1 | R0; + [P0] = R0; + rts; +ENDPROC (_atomic_ior32) + +.align 16 + /* + * Atomic ior, 32 bit. + * Inputs: P0: memory address to use + * R0: value to ior + * Outputs: R0: new contents of the memory address. + * R1: previous contents of the memory address. + */ +ENTRY(_atomic_and32) + R1 = [P0]; + R0 = R1 & R0; + [P0] = R0; + rts; +ENDPROC (_atomic_ior32) + +.align 16 + /* + * Atomic ior, 32 bit. + * Inputs: P0: memory address to use + * R0: value to ior + * Outputs: R0: new contents of the memory address. + * R1: previous contents of the memory address. + */ +ENTRY(_atomic_xor32) + R1 = [P0]; + R0 = R1 ^ R0; + [P0] = R0; + rts; +ENDPROC (_atomic_ior32) + +ENTRY(_fixed_code_end) diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index 3eff743..6b7a94a 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -35,6 +35,7 @@ #include #include +#include #define LED_ON 0 #define LED_OFF 1 @@ -350,6 +351,70 @@ unsigned long get_wchan(struct task_struct *p) return 0; } +void finish_atomic_sections (struct pt_regs *regs) +{ + if (regs->pc < ATOMIC_SEQS_START || regs->pc >= ATOMIC_SEQS_END) + return; + + switch (regs->pc) { + case ATOMIC_XCHG32 + 2: + put_user(regs->r1, (int *)regs->p0); + regs->pc += 2; + break; + + case ATOMIC_CAS32 + 2: + case ATOMIC_CAS32 + 4: + if (regs->r0 == regs->r1) + put_user(regs->r2, (int *)regs->p0); + regs->pc = ATOMIC_CAS32 + 8; + break; + case ATOMIC_CAS32 + 6: + put_user(regs->r2, (int *)regs->p0); + regs->pc += 2; + break; + + case ATOMIC_ADD32 + 2: + regs->r0 = regs->r1 + regs->r0; + /* fall through */ + case ATOMIC_ADD32 + 4: + put_user(regs->r0, (int *)regs->p0); + regs->pc = ATOMIC_ADD32 + 6; + break; + + case ATOMIC_SUB32 + 2: + regs->r0 = regs->r1 - regs->r0; + /* fall through */ + case ATOMIC_SUB32 + 4: + put_user(regs->r0, (int *)regs->p0); + regs->pc = ATOMIC_SUB32 + 6; + break; + + case ATOMIC_IOR32 + 2: + regs->r0 = regs->r1 | regs->r0; + /* fall through */ + case ATOMIC_IOR32 + 4: + put_user(regs->r0, (int *)regs->p0); + regs->pc = ATOMIC_IOR32 + 6; + break; + + case ATOMIC_AND32 + 2: + regs->r0 = regs->r1 & regs->r0; + /* fall through */ + case ATOMIC_AND32 + 4: + put_user(regs->r0, (int *)regs->p0); + regs->pc = ATOMIC_AND32 + 6; + break; + + case ATOMIC_XOR32 + 2: + regs->r0 = regs->r1 ^ regs->r0; + /* fall through */ + case ATOMIC_XOR32 + 4: + put_user(regs->r0, (int *)regs->p0); + regs->pc = ATOMIC_XOR32 + 6; + break; + } +} + #if defined(CONFIG_ACCESS_CHECK) int _access_ok(unsigned long addr, unsigned long size) { diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 76bf2ce..534227f 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -42,6 +42,7 @@ #include #include #include +#include u16 _bfin_swrst; @@ -404,6 +405,27 @@ void __init setup_arch(char **cmdline_p) printk(KERN_INFO "Hardware Trace Enabled\n"); bfin_write_TBUFCTL(0x03); + + /* Copy atomic sequences to their fixed location, and sanity check that + these locations are the ones that we advertise to userspace. */ + memcpy((void *)FIXED_CODE_START, &fixed_code_start, + FIXED_CODE_END - FIXED_CODE_START); + BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start + != SIGRETURN_STUB - FIXED_CODE_START); + BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start + != ATOMIC_XCHG32 - FIXED_CODE_START); + BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start + != ATOMIC_CAS32 - FIXED_CODE_START); + BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start + != ATOMIC_ADD32 - FIXED_CODE_START); + BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start + != ATOMIC_SUB32 - FIXED_CODE_START); + BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start + != ATOMIC_IOR32 - FIXED_CODE_START); + BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start + != ATOMIC_AND32 - FIXED_CODE_START); + BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start + != ATOMIC_XOR32 - FIXED_CODE_START); } static int __init topology_init(void) diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index 40045b1..c4a32ea 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -741,6 +741,10 @@ _schedule_and_signal_from_int: r0 = [p0]; sti r0; + r0 = sp; + sp += -12; + call _finish_atomic_sections; + sp += 12; jump.s .Lresume_userspace; _schedule_and_signal: diff --git a/include/asm-blackfin/Kbuild b/include/asm-blackfin/Kbuild index c68e168..71f8fe7 100644 --- a/include/asm-blackfin/Kbuild +++ b/include/asm-blackfin/Kbuild @@ -1 +1,3 @@ include include/asm-generic/Kbuild.asm + +header-y += fixed_code.h diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h index 57f37cc..c4d6cbb 100644 --- a/include/asm-blackfin/bfin-global.h +++ b/include/asm-blackfin/bfin-global.h @@ -67,6 +67,18 @@ extern void evt14_softirq(void); extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type); +extern asmlinkage void finish_atomic_sections (struct pt_regs *regs); +extern char fixed_code_start; +extern char fixed_code_end; +extern int atomic_xchg32(void); +extern int atomic_cas32(void); +extern int atomic_add32(void); +extern int atomic_sub32(void); +extern int atomic_ior32(void); +extern int atomic_and32(void); +extern int atomic_xor32(void); +extern void sigreturn_stub(void); + extern void *l1_data_A_sram_alloc(size_t); extern void *l1_data_B_sram_alloc(size_t); extern void *l1_inst_sram_alloc(size_t); diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h index 3bad2d1..e14ea39 100644 --- a/include/asm-blackfin/cplbinit.h +++ b/include/asm-blackfin/cplbinit.h @@ -101,8 +101,8 @@ struct s_cplb { static struct cplb_desc cplb_data[] = { { .start = 0, - .end = SIZE_4K, - .psize = SIZE_4K, + .end = SIZE_1K, + .psize = SIZE_1K, .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, .i_conf = SDRAM_OOPS, .d_conf = SDRAM_OOPS, diff --git a/include/asm-blackfin/fixed_code.h b/include/asm-blackfin/fixed_code.h new file mode 100644 index 0000000..e6df84e --- /dev/null +++ b/include/asm-blackfin/fixed_code.h @@ -0,0 +1,20 @@ +/* This file defines the fixed addresses where userspace programs can find + atomic code sequences. */ + +#define FIXED_CODE_START 0x400 + +#define SIGRETURN_STUB 0x400 + +#define ATOMIC_SEQS_START 0x410 + +#define ATOMIC_XCHG32 0x410 +#define ATOMIC_CAS32 0x420 +#define ATOMIC_ADD32 0x430 +#define ATOMIC_SUB32 0x440 +#define ATOMIC_IOR32 0x450 +#define ATOMIC_AND32 0x460 +#define ATOMIC_XOR32 0x470 + +#define ATOMIC_SEQS_END 0x480 + +#define FIXED_CODE_END 0x480 -- cgit v0.10.2 From f8ffe652a01506e85e2dd579c58e50a3ba391921 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 21 Jun 2007 11:34:16 +0800 Subject: Blackfin arch: need to rename function after moving to match new internal dma API Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c index c4e4054..6c909cf 100644 --- a/arch/blackfin/mach-bf533/dma.c +++ b/arch/blackfin/mach-bf533/dma.c @@ -44,7 +44,7 @@ struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, }; -int bf533_channel2irq(unsigned int channel) +int channel2irq(unsigned int channel) { int ret_irq = -1; -- cgit v0.10.2 From 1c5d2265a82f8d3fa0471a60ca98072b3c53c299 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 21 Jun 2007 11:34:16 +0800 Subject: Blackfin arch: add missing implementations SIC_IWR crosses several registers SIC_IWR crosses several registers - add missing implementations - make sure SIC_IWR is SET after boot Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c index 80943bb..e6511db 100644 --- a/arch/blackfin/mach-common/ints-priority-dc.c +++ b/arch/blackfin/mach-common/ints-priority-dc.c @@ -371,6 +371,9 @@ int __init init_arch_irq(void) bfin_write_SICA_IMASK1(SIC_UNMASK_ALL); SSYNC(); + bfin_write_SICA_IWR0(IWR_ENABLE_ALL); + bfin_write_SICA_IWR1(IWR_ENABLE_ALL); + local_irq_disable(); init_exception_buff(); diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c index cec0f84..27838da 100644 --- a/arch/blackfin/mach-common/ints-priority-sc.c +++ b/arch/blackfin/mach-common/ints-priority-sc.c @@ -472,8 +472,12 @@ int __init init_arch_irq(void) bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); + bfin_write_SIC_IWR0(IWR_ENABLE_ALL); + bfin_write_SIC_IWR1(IWR_ENABLE_ALL); + bfin_write_SIC_IWR2(IWR_ENABLE_ALL); #else bfin_write_SIC_IMASK(SIC_UNMASK_ALL); + bfin_write_SIC_IWR(IWR_ENABLE_ALL); #endif SSYNC(); diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index b133800..87f2385 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h @@ -32,6 +32,7 @@ #define _CDEF_BF54X_H #include "defBF54x_base.h" +#include /* ************************************************************** */ /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ @@ -44,7 +45,31 @@ #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) #define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) +/* Writing to VR_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_VR_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1, iwr2; + + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); + iwr2 = bfin_read32(SIC_IWR2); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); + bfin_write32(SIC_IWR2, 0); + + bfin_write16(VR_CTL, val); + __builtin_bfin_ssync(); + + local_irq_save(flags); + asm("IDLE;"); + local_irq_restore(flags); + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); + bfin_write32(SIC_IWR2, iwr2); + +} #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h index b14f872..6e8b816 100644 --- a/include/asm-blackfin/mach-bf561/cdefBF561.h +++ b/include/asm-blackfin/mach-bf561/cdefBF561.h @@ -57,12 +57,14 @@ /* Writing to VR_CTL initiates a PLL relock sequence. */ static __inline__ void bfin_write_VR_CTL(unsigned int val) { - unsigned long flags, iwr; + unsigned long flags, iwr0, iwr1; /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SICA_IWR0); + iwr0 = bfin_read32(SICA_IWR0); + iwr1 = bfin_read32(SICA_IWR1); /* Only allow PPL Wakeup) */ bfin_write32(SICA_IWR0, IWR_ENABLE(0)); + bfin_write32(SICA_IWR1, 0); bfin_write16(VR_CTL, val); __builtin_bfin_ssync(); @@ -70,7 +72,9 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) local_irq_save(flags); asm("IDLE;"); local_irq_restore(flags); - bfin_write32(SICA_IWR0, iwr); + bfin_write32(SICA_IWR0, iwr0); + bfin_write32(SICA_IWR1, iwr1); + } #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) -- cgit v0.10.2 From 474f1a667d4bd40b6dcacc6870b70f4d2ba4e155 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Fri, 29 Jun 2007 16:35:17 +0800 Subject: Blackfin arch: kgdb specific code Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu diff --git a/Documentation/blackfin/kgdb.txt b/Documentation/blackfin/kgdb.txt new file mode 100644 index 0000000..84f6a484 --- /dev/null +++ b/Documentation/blackfin/kgdb.txt @@ -0,0 +1,155 @@ + A Simple Guide to Configure KGDB + + Sonic Zhang + Aug. 24th 2006 + + +This KGDB patch enables the kernel developer to do source level debugging on +the kernel for the Blackfin architecture. The debugging works over either the +ethernet interface or one of the uarts. Both software breakpoints and +hardware breakpoints are supported in this version. +http://docs.blackfin.uclinux.org/doku.php?id=kgdb + + +2 known issues: +1. This bug: + http://blackfin.uclinux.org/tracker/index.php?func=detail&aid=544&group_id=18&atid=145 + The GDB client for Blackfin uClinux causes incorrect values of local + variables to be displayed when the user breaks the running of kernel in GDB. +2. Because of a hardware bug in Blackfin 533 v1.0.3: + 05000067 - Watchpoints (Hardware Breakpoints) are not supported + Hardware breakpoints cannot be set properly. + + +Debug over Ethernet: + +1. Compile and install the cross platform version of gdb for blackfin, which + can be found at $(BINROOT)/bfin-elf-gdb. + +2. Apply this patch to the 2.6.x kernel. Select the menuconfig option under + "Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb". + With this selected, option "Full Symbolic/Source Debugging support" and + "Compile the kernel with frame pointers" are also selected. + +3. Select option "KGDB: connect over (Ethernet)". Add "kgdboe=@target-IP/,@host-IP/" to + the option "Compiled-in Kernel Boot Parameter" under "Kernel hacking". + +4. Connect minicom to the serial port and boot the kernel image. + +5. Configure the IP "/> ifconfig eth0 target-IP" + +6. Start GDB client "bfin-elf-gdb vmlinux". + +7. Connect to the target "(gdb) target remote udp:target-IP:6443". + +8. Set software breakpoint "(gdb) break sys_open". + +9. Continue "(gdb) c". + +10. Run ls in the target console "/> ls". + +11. Breakpoint hits. "Breakpoint 1: sys_open(..." + +12. Display local variables and function paramters. + (*) This operation gives wrong results, see known issue 1. + +13. Single stepping "(gdb) si". + +14. Remove breakpoint 1. "(gdb) del 1" + +15. Set hardware breakpoint "(gdb) hbreak sys_open". + +16. Continue "(gdb) c". + +17. Run ls in the target console "/> ls". + +18. Hardware breakpoint hits. "Breakpoint 1: sys_open(...". + (*) This hardware breakpoint will not be hit, see known issue 2. + +19. Continue "(gdb) c". + +20. Interrupt the target in GDB "Ctrl+C". + +21. Detach from the target "(gdb) detach". + +22. Exit GDB "(gdb) quit". + + +Debug over the UART: + +1. Compile and install the cross platform version of gdb for blackfin, which + can be found at $(BINROOT)/bfin-elf-gdb. + +2. Apply this patch to the 2.6.x kernel. Select the menuconfig option under + "Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb". + With this selected, option "Full Symbolic/Source Debugging support" and + "Compile the kernel with frame pointers" are also selected. + +3. Select option "KGDB: connect over (UART)". Set "KGDB: UART port number" to be + a different one from the console. Don't forget to change the mode of + blackfin serial driver to PIO. Otherwise kgdb works incorrectly on UART. + +4. If you want connect to kgdb when the kernel boots, enable + "KGDB: Wait for gdb connection early" + +5. Compile kernel. + +6. Connect minicom to the serial port of the console and boot the kernel image. + +7. Start GDB client "bfin-elf-gdb vmlinux". + +8. Set the baud rate in GDB "(gdb) set remotebaud 57600". + +9. Connect to the target on the second serial port "(gdb) target remote /dev/ttyS1". + +10. Set software breakpoint "(gdb) break sys_open". + +11. Continue "(gdb) c". + +12. Run ls in the target console "/> ls". + +13. A breakpoint is hit. "Breakpoint 1: sys_open(..." + +14. All other operations are the same as that in KGDB over Ethernet. + + +Debug over the same UART as console: + +1. Compile and install the cross platform version of gdb for blackfin, which + can be found at $(BINROOT)/bfin-elf-gdb. + +2. Apply this patch to the 2.6.x kernel. Select the menuconfig option under + "Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb". + With this selected, option "Full Symbolic/Source Debugging support" and + "Compile the kernel with frame pointers" are also selected. + +3. Select option "KGDB: connect over UART". Set "KGDB: UART port number" to console. + Don't forget to change the mode of blackfin serial driver to PIO. + Otherwise kgdb works incorrectly on UART. + +4. If you want connect to kgdb when the kernel boots, enable + "KGDB: Wait for gdb connection early" + +5. Connect minicom to the serial port and boot the kernel image. + +6. (Optional) Ask target to wait for gdb connection by entering Ctrl+A. In minicom, you should enter Ctrl+A+A. + +7. Start GDB client "bfin-elf-gdb vmlinux". + +8. Set the baud rate in GDB "(gdb) set remotebaud 57600". + +9. Connect to the target "(gdb) target remote /dev/ttyS0". + +10. Set software breakpoint "(gdb) break sys_open". + +11. Continue "(gdb) c". Then enter Ctrl+C twice to stop GDB connection. + +12. Run ls in the target console "/> ls". Dummy string can be seen on the console. + +13. Then connect the gdb to target again. "(gdb) target remote /dev/ttyS0". + Now you will find a breakpoint is hit. "Breakpoint 1: sys_open(..." + +14. All other operations are the same as that in KGDB over Ethernet. The only + difference is that after continue command in GDB, please stop GDB + connection by 2 "Ctrl+C"s and connect again after breakpoints are hit or + Ctrl+A is entered. diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile index b7b6de8..6fac57f 100644 --- a/arch/blackfin/kernel/Makefile +++ b/arch/blackfin/kernel/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_BF561) += bfin_gpio.o obj-$(CONFIG_MODULES) += module.o obj-$(CONFIG_BFIN_DMA_5XX) += bfin_dma_5xx.o obj-$(CONFIG_DUAL_CORE_TEST_MODULE) += dualcore_test.o +obj-$(CONFIG_KGDB) += kgdb.o diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c new file mode 100644 index 0000000..a9c1551 --- /dev/null +++ b/arch/blackfin/kernel/kgdb.c @@ -0,0 +1,421 @@ +/* + * File: arch/blackfin/kernel/kgdb.c + * Based on: + * Author: Sonic Zhang + * + * Created: + * Description: + * + * Rev: $Id: kgdb_bfin_linux-2.6.x.patch 4934 2007-02-13 09:32:11Z sonicz $ + * + * Modified: + * Copyright 2005-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include /* for linux pt_regs struct */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Put the error code here just in case the user cares. */ +int gdb_bf533errcode; +/* Likewise, the vector number here (since GDB only gets the signal + number through the usual means, and that's not very specific). */ +int gdb_bf533vector = -1; + +#if KGDB_MAX_NO_CPUS != 8 +#error change the definition of slavecpulocks +#endif + +void regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) +{ + gdb_regs[BFIN_R0] = regs->r0; + gdb_regs[BFIN_R1] = regs->r1; + gdb_regs[BFIN_R2] = regs->r2; + gdb_regs[BFIN_R3] = regs->r3; + gdb_regs[BFIN_R4] = regs->r4; + gdb_regs[BFIN_R5] = regs->r5; + gdb_regs[BFIN_R6] = regs->r6; + gdb_regs[BFIN_R7] = regs->r7; + gdb_regs[BFIN_P0] = regs->p0; + gdb_regs[BFIN_P1] = regs->p1; + gdb_regs[BFIN_P2] = regs->p2; + gdb_regs[BFIN_P3] = regs->p3; + gdb_regs[BFIN_P4] = regs->p4; + gdb_regs[BFIN_P5] = regs->p5; + gdb_regs[BFIN_SP] = regs->reserved; + gdb_regs[BFIN_FP] = regs->fp; + gdb_regs[BFIN_I0] = regs->i0; + gdb_regs[BFIN_I1] = regs->i1; + gdb_regs[BFIN_I2] = regs->i2; + gdb_regs[BFIN_I3] = regs->i3; + gdb_regs[BFIN_M0] = regs->m0; + gdb_regs[BFIN_M1] = regs->m1; + gdb_regs[BFIN_M2] = regs->m2; + gdb_regs[BFIN_M3] = regs->m3; + gdb_regs[BFIN_B0] = regs->b0; + gdb_regs[BFIN_B1] = regs->b1; + gdb_regs[BFIN_B2] = regs->b2; + gdb_regs[BFIN_B3] = regs->b3; + gdb_regs[BFIN_L0] = regs->l0; + gdb_regs[BFIN_L1] = regs->l1; + gdb_regs[BFIN_L2] = regs->l2; + gdb_regs[BFIN_L3] = regs->l3; + gdb_regs[BFIN_A0_DOT_X] = regs->a0x; + gdb_regs[BFIN_A0_DOT_W] = regs->a0w; + gdb_regs[BFIN_A1_DOT_X] = regs->a1x; + gdb_regs[BFIN_A1_DOT_W] = regs->a1w; + gdb_regs[BFIN_ASTAT] = regs->astat; + gdb_regs[BFIN_RETS] = regs->rets; + gdb_regs[BFIN_LC0] = regs->lc0; + gdb_regs[BFIN_LT0] = regs->lt0; + gdb_regs[BFIN_LB0] = regs->lb0; + gdb_regs[BFIN_LC1] = regs->lc1; + gdb_regs[BFIN_LT1] = regs->lt1; + gdb_regs[BFIN_LB1] = regs->lb1; + gdb_regs[BFIN_CYCLES] = 0; + gdb_regs[BFIN_CYCLES2] = 0; + gdb_regs[BFIN_USP] = regs->usp; + gdb_regs[BFIN_SEQSTAT] = regs->seqstat; + gdb_regs[BFIN_SYSCFG] = regs->syscfg; + gdb_regs[BFIN_RETI] = regs->pc; + gdb_regs[BFIN_RETX] = regs->retx; + gdb_regs[BFIN_RETN] = regs->retn; + gdb_regs[BFIN_RETE] = regs->rete; + gdb_regs[BFIN_PC] = regs->pc; + gdb_regs[BFIN_CC] = 0; + gdb_regs[BFIN_EXTRA1] = 0; + gdb_regs[BFIN_EXTRA2] = 0; + gdb_regs[BFIN_EXTRA3] = 0; + gdb_regs[BFIN_IPEND] = regs->ipend; +} + +/* + * Extracts ebp, esp and eip values understandable by gdb from the values + * saved by switch_to. + * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp + * prior to entering switch_to is 8 greater then the value that is saved. + * If switch_to changes, change following code appropriately. + */ +void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p) +{ + gdb_regs[BFIN_SP] = p->thread.ksp; + gdb_regs[BFIN_PC] = p->thread.pc; + gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat; +} + +void gdb_regs_to_regs(unsigned long *gdb_regs, struct pt_regs *regs) +{ + regs->r0 = gdb_regs[BFIN_R0]; + regs->r1 = gdb_regs[BFIN_R1]; + regs->r2 = gdb_regs[BFIN_R2]; + regs->r3 = gdb_regs[BFIN_R3]; + regs->r4 = gdb_regs[BFIN_R4]; + regs->r5 = gdb_regs[BFIN_R5]; + regs->r6 = gdb_regs[BFIN_R6]; + regs->r7 = gdb_regs[BFIN_R7]; + regs->p0 = gdb_regs[BFIN_P0]; + regs->p1 = gdb_regs[BFIN_P1]; + regs->p2 = gdb_regs[BFIN_P2]; + regs->p3 = gdb_regs[BFIN_P3]; + regs->p4 = gdb_regs[BFIN_P4]; + regs->p5 = gdb_regs[BFIN_P5]; + regs->fp = gdb_regs[BFIN_FP]; + regs->i0 = gdb_regs[BFIN_I0]; + regs->i1 = gdb_regs[BFIN_I1]; + regs->i2 = gdb_regs[BFIN_I2]; + regs->i3 = gdb_regs[BFIN_I3]; + regs->m0 = gdb_regs[BFIN_M0]; + regs->m1 = gdb_regs[BFIN_M1]; + regs->m2 = gdb_regs[BFIN_M2]; + regs->m3 = gdb_regs[BFIN_M3]; + regs->b0 = gdb_regs[BFIN_B0]; + regs->b1 = gdb_regs[BFIN_B1]; + regs->b2 = gdb_regs[BFIN_B2]; + regs->b3 = gdb_regs[BFIN_B3]; + regs->l0 = gdb_regs[BFIN_L0]; + regs->l1 = gdb_regs[BFIN_L1]; + regs->l2 = gdb_regs[BFIN_L2]; + regs->l3 = gdb_regs[BFIN_L3]; + regs->a0x = gdb_regs[BFIN_A0_DOT_X]; + regs->a0w = gdb_regs[BFIN_A0_DOT_W]; + regs->a1x = gdb_regs[BFIN_A1_DOT_X]; + regs->a1w = gdb_regs[BFIN_A1_DOT_W]; + regs->rets = gdb_regs[BFIN_RETS]; + regs->lc0 = gdb_regs[BFIN_LC0]; + regs->lt0 = gdb_regs[BFIN_LT0]; + regs->lb0 = gdb_regs[BFIN_LB0]; + regs->lc1 = gdb_regs[BFIN_LC1]; + regs->lt1 = gdb_regs[BFIN_LT1]; + regs->lb1 = gdb_regs[BFIN_LB1]; + regs->usp = gdb_regs[BFIN_USP]; + regs->syscfg = gdb_regs[BFIN_SYSCFG]; + regs->retx = gdb_regs[BFIN_PC]; + regs->retn = gdb_regs[BFIN_RETN]; + regs->rete = gdb_regs[BFIN_RETE]; + regs->pc = gdb_regs[BFIN_PC]; + +#if 0 /* can't change these */ + regs->astat = gdb_regs[BFIN_ASTAT]; + regs->seqstat = gdb_regs[BFIN_SEQSTAT]; + regs->ipend = gdb_regs[BFIN_IPEND]; +#endif +} + +struct hw_breakpoint { + unsigned int occupied:1; + unsigned int skip:1; + unsigned int enabled:1; + unsigned int type:1; + unsigned int dataacc:2; + unsigned short count; + unsigned int addr; +} breakinfo[HW_BREAKPOINT_NUM]; + +int kgdb_arch_init(void) +{ + kgdb_remove_all_hw_break(); + return 0; +} + +int kgdb_set_hw_break(unsigned long addr) +{ + int breakno; + for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++) + if (!breakinfo[breakno].occupied) { + breakinfo[breakno].occupied = 1; + breakinfo[breakno].enabled = 1; + breakinfo[breakno].type = 1; + breakinfo[breakno].addr = addr; + return 0; + } + + return -ENOSPC; +} + +int kgdb_remove_hw_break(unsigned long addr) +{ + int breakno; + for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++) + if (breakinfo[breakno].addr == addr) + memset(&(breakinfo[breakno]), 0, sizeof(struct hw_breakpoint)); + + return 0; +} + +void kgdb_remove_all_hw_break(void) +{ + memset(breakinfo, 0, sizeof(struct hw_breakpoint)*8); +} + +/* +void kgdb_show_info(void) +{ + printk(KERN_DEBUG "hwd: wpia0=0x%x, wpiacnt0=%d, wpiactl=0x%x, wpstat=0x%x\n", + bfin_read_WPIA0(), bfin_read_WPIACNT0(), + bfin_read_WPIACTL(), bfin_read_WPSTAT()); +} +*/ + +void kgdb_correct_hw_break(void) +{ + int breakno; + int correctit; + uint32_t wpdactl = bfin_read_WPDACTL(); + + correctit = 0; + for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++) { + if (breakinfo[breakno].type == 1) { + switch (breakno) { + case 0: + if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN0)) { + correctit = 1; + wpdactl &= ~(WPIREN01|EMUSW0); + wpdactl |= WPIAEN0|WPICNTEN0; + bfin_write_WPIA0(breakinfo[breakno].addr); + bfin_write_WPIACNT0(breakinfo[breakno].skip); + } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN0)) { + correctit = 1; + wpdactl &= ~WPIAEN0; + } + break; + + case 1: + if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN1)) { + correctit = 1; + wpdactl &= ~(WPIREN01|EMUSW1); + wpdactl |= WPIAEN1|WPICNTEN1; + bfin_write_WPIA1(breakinfo[breakno].addr); + bfin_write_WPIACNT1(breakinfo[breakno].skip); + } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN1)) { + correctit = 1; + wpdactl &= ~WPIAEN1; + } + break; + + case 2: + if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN2)) { + correctit = 1; + wpdactl &= ~(WPIREN23|EMUSW2); + wpdactl |= WPIAEN2|WPICNTEN2; + bfin_write_WPIA2(breakinfo[breakno].addr); + bfin_write_WPIACNT2(breakinfo[breakno].skip); + } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN2)) { + correctit = 1; + wpdactl &= ~WPIAEN2; + } + break; + + case 3: + if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN3)) { + correctit = 1; + wpdactl &= ~(WPIREN23|EMUSW3); + wpdactl |= WPIAEN3|WPICNTEN3; + bfin_write_WPIA3(breakinfo[breakno].addr); + bfin_write_WPIACNT3(breakinfo[breakno].skip); + } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN3)) { + correctit = 1; + wpdactl &= ~WPIAEN3; + } + break; + case 4: + if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN4)) { + correctit = 1; + wpdactl &= ~(WPIREN45|EMUSW4); + wpdactl |= WPIAEN4|WPICNTEN4; + bfin_write_WPIA4(breakinfo[breakno].addr); + bfin_write_WPIACNT4(breakinfo[breakno].skip); + } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN4)) { + correctit = 1; + wpdactl &= ~WPIAEN4; + } + break; + case 5: + if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN5)) { + correctit = 1; + wpdactl &= ~(WPIREN45|EMUSW5); + wpdactl |= WPIAEN5|WPICNTEN5; + bfin_write_WPIA5(breakinfo[breakno].addr); + bfin_write_WPIACNT5(breakinfo[breakno].skip); + } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN5)) { + correctit = 1; + wpdactl &= ~WPIAEN5; + } + break; + } + } + } + if (correctit) { + wpdactl &= ~WPAND; + wpdactl |= WPPWR; + /*printk("correct_hw_break: wpdactl=0x%x\n", wpdactl);*/ + bfin_write_WPDACTL(wpdactl); + CSYNC(); + /*kgdb_show_info();*/ + } +} + +void kgdb_disable_hw_debug(struct pt_regs *regs) +{ + /* Disable hardware debugging while we are in kgdb */ + bfin_write_WPIACTL(bfin_read_WPIACTL() & ~0x1); + CSYNC(); +} + +void kgdb_post_master_code(struct pt_regs *regs, int eVector, int err_code) +{ + /* Master processor is completely in the debugger */ + gdb_bf533vector = eVector; + gdb_bf533errcode = err_code; +} + +int kgdb_arch_handle_exception(int exceptionVector, int signo, + int err_code, char *remcom_in_buffer, + char *remcom_out_buffer, + struct pt_regs *linux_regs) +{ + long addr; + long breakno; + char *ptr; + int newPC; + int wp_status; + + switch (remcom_in_buffer[0]) { + case 'c': + case 's': + if (kgdb_contthread && kgdb_contthread != current) { + strcpy(remcom_out_buffer, "E00"); + break; + } + + kgdb_contthread = NULL; + + /* try to read optional parameter, pc unchanged if no parm */ + ptr = &remcom_in_buffer[1]; + if (kgdb_hex2long(&ptr, &addr)) { + linux_regs->retx = addr; + } + newPC = linux_regs->retx; + + /* clear the trace bit */ + linux_regs->syscfg &= 0xfffffffe; + + /* set the trace bit if we're stepping */ + if (remcom_in_buffer[0] == 's') { + linux_regs->syscfg |= 0x1; + debugger_step = 1; + } + + wp_status = bfin_read_WPSTAT(); + CSYNC(); + + if (exceptionVector == VEC_WATCH) { + for (breakno = 0; breakno < 6; ++breakno) { + if (wp_status & (1 << breakno)) { + breakinfo->skip = 1; + break; + } + } + } + kgdb_correct_hw_break(); + + bfin_write_WPSTAT(0); + + return 0; + } /* switch */ + return -1; /* this means that we do not want to exit from the handler */ +} + +struct kgdb_arch arch_kgdb_ops = { + .gdb_bpt_instr = {0xa1}, + .flags = KGDB_HW_BREAKPOINT, +}; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 315ea99..71a4ac5 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -556,7 +556,7 @@ choice config SERIAL_BFIN_DMA bool "DMA mode" - depends on DMA_UNCACHED_1M + depends on DMA_UNCACHED_1M && !KGDB_UART help This driver works under DMA mode. If this option is selected, the blackfin simple dma driver is also enabled. diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c index 22569bd..f7926dc 100644 --- a/drivers/serial/bfin_5xx.c +++ b/drivers/serial/bfin_5xx.c @@ -41,6 +41,11 @@ #include #include +#ifdef CONFIG_KGDB_UART +#include +#include +#endif + #include #include @@ -119,6 +124,9 @@ static void bfin_serial_stop_rx(struct uart_port *port) unsigned short ier; ier = UART_GET_IER(uart); +#ifdef CONFIG_KGDB_UART + if (uart->port.line != CONFIG_KGDB_UART_PORT) +#endif ier &= ~ERBFI; UART_PUT_IER(uart, ier); } @@ -130,6 +138,49 @@ static void bfin_serial_enable_ms(struct uart_port *port) { } +#ifdef CONFIG_KGDB_UART +static int kgdb_entry_state; + +void kgdb_put_debug_char(int chr) +{ + struct bfin_serial_port *uart; + + if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS) + uart = &bfin_serial_ports[0]; + else + uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT]; + + while (!(UART_GET_LSR(uart) & THRE)) { + __builtin_bfin_ssync(); + } + UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB)); + __builtin_bfin_ssync(); + UART_PUT_CHAR(uart, (unsigned char)chr); + __builtin_bfin_ssync(); +} + +int kgdb_get_debug_char(void) +{ + struct bfin_serial_port *uart; + unsigned char chr; + + if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS) + uart = &bfin_serial_ports[0]; + else + uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT]; + + while(!(UART_GET_LSR(uart) & DR)) { + __builtin_bfin_ssync(); + } + UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB)); + __builtin_bfin_ssync(); + chr = UART_GET_CHAR(uart); + __builtin_bfin_ssync(); + + return chr; +} +#endif + #ifdef CONFIG_SERIAL_BFIN_PIO static void local_put_char(struct bfin_serial_port *uart, char ch) { @@ -152,6 +203,9 @@ static void bfin_serial_rx_chars(struct bfin_serial_port *uart) { struct tty_struct *tty = uart->port.info->tty; unsigned int status, ch, flg; +#ifdef CONFIG_KGDB_UART + struct pt_regs *regs = get_irq_regs(); +#endif #ifdef BF533_FAMILY static int in_break = 0; #endif @@ -160,6 +214,27 @@ static void bfin_serial_rx_chars(struct bfin_serial_port *uart) ch = UART_GET_CHAR(uart); uart->port.icount.rx++; +#ifdef CONFIG_KGDB_UART + if (uart->port.line == CONFIG_KGDB_UART_PORT) { + if (uart->port.cons->index == CONFIG_KGDB_UART_PORT && ch == 0x1) { /* Ctrl + A */ + kgdb_breakkey_pressed(regs); + return; + } else if (kgdb_entry_state == 0 && ch == '$') {/* connection from KGDB */ + kgdb_entry_state = 1; + } else if (kgdb_entry_state == 1 && ch == 'q') { + kgdb_entry_state = 0; + kgdb_breakkey_pressed(regs); + return; + } else if (ch == 0x3) {/* Ctrl + C */ + kgdb_entry_state = 0; + kgdb_breakkey_pressed(regs); + return; + } else { + kgdb_entry_state = 0; + } + } +#endif + #ifdef BF533_FAMILY /* The BF533 family of processors have a nice misbehavior where * they continuously generate characters for a "single" break. @@ -571,7 +646,11 @@ static int bfin_serial_startup(struct uart_port *port) uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; add_timer(&(uart->rx_dma_timer)); #else +# ifdef CONFIG_KGDB_UART + if (uart->port.line != CONFIG_KGDB_UART_PORT && request_irq +# else if (request_irq +# endif (uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED, "BFIN_UART_RX", uart)) { printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n"); @@ -601,6 +680,9 @@ static void bfin_serial_shutdown(struct uart_port *port) free_dma(uart->rx_dma_channel); del_timer(&(uart->rx_dma_timer)); #else +#ifdef CONFIG_KGDB_UART + if (uart->port.line != CONFIG_KGDB_UART_PORT) +#endif free_irq(uart->port.irq, uart); free_irq(uart->port.irq+1, uart); #endif @@ -931,6 +1013,10 @@ static int __init bfin_serial_rs_console_init(void) { bfin_serial_init_ports(); register_console(&bfin_serial_console); +#ifdef CONFIG_KGDB_UART + kgdb_entry_state = 0; + init_kgdb_uart(); +#endif return 0; } console_initcall(bfin_serial_rs_console_init); @@ -1023,6 +1109,10 @@ static struct platform_driver bfin_serial_driver = { static int __init bfin_serial_init(void) { int ret; +#ifdef CONFIG_KGDB_UART + struct bfin_serial_port *uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT]; + struct termios t; +#endif pr_info("Serial: Blackfin serial driver\n"); @@ -1036,6 +1126,21 @@ static int __init bfin_serial_init(void) uart_unregister_driver(&bfin_serial_reg); } } +#ifdef CONFIG_KGDB_UART + if (uart->port.cons->index != CONFIG_KGDB_UART_PORT) { + request_irq(uart->port.irq, bfin_serial_int, + IRQF_DISABLED, "BFIN_UART_RX", uart); + pr_info("Request irq for kgdb uart port\n"); + UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI); + __builtin_bfin_ssync(); + t.c_cflag = CS8|B57600; + t.c_iflag = 0; + t.c_oflag = 0; + t.c_lflag = ICANON; + t.c_line = CONFIG_KGDB_UART_PORT; + bfin_serial_set_termios(&uart->port, &t, &t); + } +#endif return ret; } diff --git a/include/asm-blackfin/kgdb.h b/include/asm-blackfin/kgdb.h new file mode 100644 index 0000000..532bd90 --- /dev/null +++ b/include/asm-blackfin/kgdb.h @@ -0,0 +1,183 @@ +/* + * File: include/asm-blackfin/kgdb.h + * Based on: + * Author: Sonic Zhang + * + * Created: + * Description: + * + * Rev: $Id: kgdb_bfin_linux-2.6.x.patch 4934 2007-02-13 09:32:11Z sonicz $ + * + * Modified: + * Copyright 2005-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ASM_BLACKFIN_KGDB_H__ +#define __ASM_BLACKFIN_KGDB_H__ + +#include + +/* gdb locks */ +#define KGDB_MAX_NO_CPUS 8 + +/************************************************************************/ +/* BUFMAX defines the maximum number of characters in inbound/outbound buffers*/ +/* at least NUMREGBYTES*2 are needed for register packets */ +/* Longer buffer is needed to list all threads */ +#define BUFMAX 2048 + +/* + * Note that this register image is different from + * the register image that Linux produces at interrupt time. + * + * Linux's register image is defined by struct pt_regs in ptrace.h. + */ +enum regnames { + /* Core Registers */ + BFIN_R0 = 0, + BFIN_R1, + BFIN_R2, + BFIN_R3, + BFIN_R4, + BFIN_R5, + BFIN_R6, + BFIN_R7, + BFIN_P0, + BFIN_P1, + BFIN_P2, + BFIN_P3, + BFIN_P4, + BFIN_P5, + BFIN_SP, + BFIN_FP, + BFIN_I0, + BFIN_I1, + BFIN_I2, + BFIN_I3, + BFIN_M0, + BFIN_M1, + BFIN_M2, + BFIN_M3, + BFIN_B0, + BFIN_B1, + BFIN_B2, + BFIN_B3, + BFIN_L0, + BFIN_L1, + BFIN_L2, + BFIN_L3, + BFIN_A0_DOT_X, + BFIN_A0_DOT_W, + BFIN_A1_DOT_X, + BFIN_A1_DOT_W, + BFIN_ASTAT, + BFIN_RETS, + BFIN_LC0, + BFIN_LT0, + BFIN_LB0, + BFIN_LC1, + BFIN_LT1, + BFIN_LB1, + BFIN_CYCLES, + BFIN_CYCLES2, + BFIN_USP, + BFIN_SEQSTAT, + BFIN_SYSCFG, + BFIN_RETI, + BFIN_RETX, + BFIN_RETN, + BFIN_RETE, + + /* Pseudo Registers */ + BFIN_PC, + BFIN_CC, + BFIN_EXTRA1, /* Address of .text section. */ + BFIN_EXTRA2, /* Address of .data section. */ + BFIN_EXTRA3, /* Address of .bss section. */ + BFIN_FDPIC_EXEC, + BFIN_FDPIC_INTERP, + + /* MMRs */ + BFIN_IPEND, + + /* LAST ENTRY SHOULD NOT BE CHANGED. */ + BFIN_NUM_REGS /* The number of all registers. */ +}; + +/* Number of bytes of registers. */ +#define NUMREGBYTES BFIN_NUM_REGS*4 + +#define BREAKPOINT() asm(" EXCPT 2;"); +#define BREAK_INSTR_SIZE 2 +#define HW_BREAKPOINT_NUM 6 + +/* Instruction watchpoint address control register bits mask */ +#define WPPWR 0x1 +#define WPIREN01 0x2 +#define WPIRINV01 0x4 +#define WPIAEN0 0x8 +#define WPIAEN1 0x10 +#define WPICNTEN0 0x20 +#define WPICNTEN1 0x40 +#define EMUSW0 0x80 +#define EMUSW1 0x100 +#define WPIREN23 0x200 +#define WPIRINV23 0x400 +#define WPIAEN2 0x800 +#define WPIAEN3 0x1000 +#define WPICNTEN2 0x2000 +#define WPICNTEN3 0x4000 +#define EMUSW2 0x8000 +#define EMUSW3 0x10000 +#define WPIREN45 0x20000 +#define WPIRINV45 0x40000 +#define WPIAEN4 0x80000 +#define WPIAEN5 0x100000 +#define WPICNTEN4 0x200000 +#define WPICNTEN5 0x400000 +#define EMUSW4 0x800000 +#define EMUSW5 0x1000000 +#define WPAND 0x2000000 + +/* Data watchpoint address control register bits mask */ +#define WPDREN01 0x1 +#define WPDRINV01 0x2 +#define WPDAEN0 0x4 +#define WPDAEN1 0x8 +#define WPDCNTEN0 0x10 +#define WPDCNTEN1 0x20 +#define WPDSRC0 0xc0 +#define WPDACC0 0x300 +#define WPDSRC1 0xc00 +#define WPDACC1 0x3000 + +/* Watchpoint status register bits mask */ +#define STATIA0 0x1 +#define STATIA1 0x2 +#define STATIA2 0x4 +#define STATIA3 0x8 +#define STATIA4 0x10 +#define STATIA5 0x20 +#define STATDA0 0x40 +#define STATDA1 0x80 + +extern void kgdb_print(const char *fmt, ...); + +#endif -- cgit v0.10.2 From 29440a2b4cd37e32dfe0fa60ef1665775b24dab1 Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Thu, 12 Jul 2007 16:25:29 +0800 Subject: Blackfin arch: Start untangling the CPLB handling code. - Move cache initialization to C from assembly. - Move anomaly workaround for writing [ID]MEM_CONTROL to assembly, so that we don't have to mess around with .align directives in C source. - Fix a bug where bfin_write_DMEM_CONTROL would write to IMEM_CONTROL - Break out CPLB related code from kernel/setup.c into their own file. - Don't define variables in header files, only declare them. Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile index 6fac57f..f429ebc 100644 --- a/arch/blackfin/kernel/Makefile +++ b/arch/blackfin/kernel/Makefile @@ -7,7 +7,7 @@ extra-y := init_task.o vmlinux.lds obj-y := \ entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o \ - fixed_code.o + fixed_code.o cplbinit.o cacheinit.o obj-$(CONFIG_BF53x) += bfin_gpio.o obj-$(CONFIG_BF561) += bfin_gpio.o diff --git a/arch/blackfin/kernel/cacheinit.c b/arch/blackfin/kernel/cacheinit.c new file mode 100644 index 0000000..4d41a40 --- /dev/null +++ b/arch/blackfin/kernel/cacheinit.c @@ -0,0 +1,66 @@ +/* + * Copyright 2004-2007 Analog Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include + +#include +#include +#include + +#if defined(CONFIG_BLKFIN_CACHE) +void bfin_icache_init(void) +{ + unsigned long *table = icplb_table; + unsigned long ctrl; + int i; + + for (i = 0; i < MAX_CPLBS; i++) { + unsigned long addr = *table++; + unsigned long data = *table++; + if (addr == (unsigned long)-1) + break; + bfin_write32(ICPLB_ADDR0 + i * 4, addr); + bfin_write32(ICPLB_DATA0 + i * 4, data); + } + ctrl = bfin_read_IMEM_CONTROL(); + ctrl |= IMC | ENICPLB; + bfin_write_IMEM_CONTROL(ctrl); +} +#endif + +#if defined(CONFIG_BLKFIN_DCACHE) +void bfin_dcache_init(void) +{ + unsigned long *table = dcplb_table; + unsigned long ctrl; + int i; + + for (i = 0; i < MAX_CPLBS; i++) { + unsigned long addr = *table++; + unsigned long data = *table++; + if (addr == (unsigned long)-1) + break; + bfin_write32(DCPLB_ADDR0 + i * 4, addr); + bfin_write32(DCPLB_DATA0 + i * 4, data); + } + ctrl = bfin_read_DMEM_CONTROL(); + ctrl |= DMEM_CNTR; + bfin_write_DMEM_CONTROL(ctrl); +} +#endif diff --git a/arch/blackfin/kernel/cplbinit.c b/arch/blackfin/kernel/cplbinit.c new file mode 100644 index 0000000..bbdb403 --- /dev/null +++ b/arch/blackfin/kernel/cplbinit.c @@ -0,0 +1,433 @@ +/* + * Blackfin CPLB initialization + * + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include + +#include +#include + +u_long icplb_table[MAX_CPLBS+1]; +u_long dcplb_table[MAX_CPLBS+1]; + +#ifdef CONFIG_CPLB_SWITCH_TAB_L1 +u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data)); +u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data)); + +#ifdef CONFIG_CPLB_INFO +u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data)); +u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data)); +#endif /* CONFIG_CPLB_INFO */ + +#else + +u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]; +u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]; + +#ifdef CONFIG_CPLB_INFO +u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]; +u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]; +#endif /* CONFIG_CPLB_INFO */ + +#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/ + +struct s_cplb { + struct cplb_tab init_i; + struct cplb_tab init_d; + struct cplb_tab switch_i; + struct cplb_tab switch_d; +}; + +#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE) +static struct cplb_desc cplb_data[] = { + { + .start = 0, + .end = SIZE_1K, + .psize = SIZE_1K, + .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, + .i_conf = SDRAM_OOPS, + .d_conf = SDRAM_OOPS, +#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO) + .valid = 1, +#else + .valid = 0, +#endif + .name = "ZERO Pointer Saveguard", + }, + { + .start = L1_CODE_START, + .end = L1_CODE_START + L1_CODE_LENGTH, + .psize = SIZE_4M, + .attr = INITIAL_T | SWITCH_T | I_CPLB, + .i_conf = L1_IMEMORY, + .d_conf = 0, + .valid = 1, + .name = "L1 I-Memory", + }, + { + .start = L1_DATA_A_START, + .end = L1_DATA_B_START + L1_DATA_B_LENGTH, + .psize = SIZE_4M, + .attr = INITIAL_T | SWITCH_T | D_CPLB, + .i_conf = 0, + .d_conf = L1_DMEMORY, +#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0)) + .valid = 1, +#else + .valid = 0, +#endif + .name = "L1 D-Memory", + }, + { + .start = 0, + .end = 0, /* dynamic */ + .psize = 0, + .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, + .i_conf = SDRAM_IGENERIC, + .d_conf = SDRAM_DGENERIC, + .valid = 1, + .name = "SDRAM Kernel", + }, + { + .start = 0, /* dynamic */ + .end = 0, /* dynamic */ + .psize = 0, + .attr = INITIAL_T | SWITCH_T | D_CPLB, + .i_conf = SDRAM_IGENERIC, + .d_conf = SDRAM_DNON_CHBL, + .valid = 1, + .name = "SDRAM RAM MTD", + }, + { + .start = 0, /* dynamic */ + .end = 0, /* dynamic */ + .psize = SIZE_1M, + .attr = INITIAL_T | SWITCH_T | D_CPLB, + .d_conf = SDRAM_DNON_CHBL, + .valid = 1, + .name = "SDRAM Uncached DMA ZONE", + }, + { + .start = 0, /* dynamic */ + .end = 0, /* dynamic */ + .psize = 0, + .attr = SWITCH_T | D_CPLB, + .i_conf = 0, /* dynamic */ + .d_conf = 0, /* dynamic */ + .valid = 1, + .name = "SDRAM Reserved Memory", + }, + { + .start = ASYNC_BANK0_BASE, + .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE, + .psize = 0, + .attr = SWITCH_T | D_CPLB, + .d_conf = SDRAM_EBIU, + .valid = 1, + .name = "ASYNC Memory", + }, + { +#if defined(CONFIG_BF561) + .start = L2_SRAM, + .end = L2_SRAM_END, + .psize = SIZE_1M, + .attr = SWITCH_T | D_CPLB, + .i_conf = L2_MEMORY, + .d_conf = L2_MEMORY, + .valid = 1, +#else + .valid = 0, +#endif + .name = "L2 Memory", + } +}; + +static u16 __init lock_kernel_check(u32 start, u32 end) +{ + if ((start <= (u32) _stext && end >= (u32) _end) + || (start >= (u32) _stext && end <= (u32) _end)) + return IN_KERNEL; + return 0; +} + +static unsigned short __init +fill_cplbtab(struct cplb_tab *table, + unsigned long start, unsigned long end, + unsigned long block_size, unsigned long cplb_data) +{ + int i; + + switch (block_size) { + case SIZE_4M: + i = 3; + break; + case SIZE_1M: + i = 2; + break; + case SIZE_4K: + i = 1; + break; + case SIZE_1K: + default: + i = 0; + break; + } + + cplb_data = (cplb_data & ~(3 << 16)) | (i << 16); + + while ((start < end) && (table->pos < table->size)) { + + table->tab[table->pos++] = start; + + if (lock_kernel_check(start, start + block_size) == IN_KERNEL) + table->tab[table->pos++] = + cplb_data | CPLB_LOCK | CPLB_DIRTY; + else + table->tab[table->pos++] = cplb_data; + + start += block_size; + } + return 0; +} + +static unsigned short __init +close_cplbtab(struct cplb_tab *table) +{ + + while (table->pos < table->size) { + + table->tab[table->pos++] = 0; + table->tab[table->pos++] = 0; /* !CPLB_VALID */ + } + return 0; +} + +/* helper function */ +static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end) +{ + if (cplb_data[i].psize) { + fill_cplbtab(t, + cplb_data[i].start, + cplb_data[i].end, + cplb_data[i].psize, + cplb_data[i].i_conf); + } else { +#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263)) + if (i == SDRAM_KERN) { + fill_cplbtab(t, + cplb_data[i].start, + cplb_data[i].end, + SIZE_4M, + cplb_data[i].i_conf); + } else +#endif + { + fill_cplbtab(t, + cplb_data[i].start, + a_start, + SIZE_1M, + cplb_data[i].i_conf); + fill_cplbtab(t, + a_start, + a_end, + SIZE_4M, + cplb_data[i].i_conf); + fill_cplbtab(t, a_end, + cplb_data[i].end, + SIZE_1M, + cplb_data[i].i_conf); + } + } +} + +static void __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end) +{ + if (cplb_data[i].psize) { + fill_cplbtab(t, + cplb_data[i].start, + cplb_data[i].end, + cplb_data[i].psize, + cplb_data[i].d_conf); + } else { + fill_cplbtab(t, + cplb_data[i].start, + a_start, SIZE_1M, + cplb_data[i].d_conf); + fill_cplbtab(t, a_start, + a_end, SIZE_4M, + cplb_data[i].d_conf); + fill_cplbtab(t, a_end, + cplb_data[i].end, + SIZE_1M, + cplb_data[i].d_conf); + } +} + +void __init generate_cpl_tables(void) +{ + + u16 i, j, process; + u32 a_start, a_end, as, ae, as_1m; + + struct cplb_tab *t_i = NULL; + struct cplb_tab *t_d = NULL; + struct s_cplb cplb; + + cplb.init_i.size = MAX_CPLBS; + cplb.init_d.size = MAX_CPLBS; + cplb.switch_i.size = MAX_SWITCH_I_CPLBS; + cplb.switch_d.size = MAX_SWITCH_D_CPLBS; + + cplb.init_i.pos = 0; + cplb.init_d.pos = 0; + cplb.switch_i.pos = 0; + cplb.switch_d.pos = 0; + + cplb.init_i.tab = icplb_table; + cplb.init_d.tab = dcplb_table; + cplb.switch_i.tab = ipdt_table; + cplb.switch_d.tab = dpdt_table; + + cplb_data[SDRAM_KERN].end = memory_end; + +#ifdef CONFIG_MTD_UCLINUX + cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start; + cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size; + cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0; +# if defined(CONFIG_ROMFS_FS) + cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB; + + /* + * The ROMFS_FS size is often not multiple of 1MB. + * This can cause multiple CPLB sets covering the same memory area. + * This will then cause multiple CPLB hit exceptions. + * Workaround: We ensure a contiguous memory area by extending the kernel + * memory section over the mtd section. + * For ROMFS_FS memory must be covered with ICPLBs anyways. + * So there is no difference between kernel and mtd memory setup. + */ + + cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;; + cplb_data[SDRAM_RAM_MTD].valid = 0; + +# endif +#else + cplb_data[SDRAM_RAM_MTD].valid = 0; +#endif + + cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION; + cplb_data[SDRAM_DMAZ].end = _ramend; + + cplb_data[RES_MEM].start = _ramend; + cplb_data[RES_MEM].end = physical_mem_end; + + if (reserved_mem_dcache_on) + cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC; + else + cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL; + + if (reserved_mem_icache_on) + cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC; + else + cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL; + + for (i = ZERO_P; i <= L2_MEM; i++) { + if (!cplb_data[i].valid) + continue; + + as_1m = cplb_data[i].start % SIZE_1M; + + /* We need to make sure all sections are properly 1M aligned + * However between Kernel Memory and the Kernel mtd section, depending on the + * rootfs size, there can be overlapping memory areas. + */ + + if (as_1m && i != L1I_MEM && i != L1D_MEM) { +#ifdef CONFIG_MTD_UCLINUX + if (i == SDRAM_RAM_MTD) { + if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start) + cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M; + else + cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)); + } else +#endif + printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n", + cplb_data[i].name, cplb_data[i].start); + } + + as = cplb_data[i].start % SIZE_4M; + ae = cplb_data[i].end % SIZE_4M; + + if (as) + a_start = cplb_data[i].start + (SIZE_4M - (as)); + else + a_start = cplb_data[i].start; + + a_end = cplb_data[i].end - ae; + + for (j = INITIAL_T; j <= SWITCH_T; j++) { + + switch (j) { + case INITIAL_T: + if (cplb_data[i].attr & INITIAL_T) { + t_i = &cplb.init_i; + t_d = &cplb.init_d; + process = 1; + } else + process = 0; + break; + case SWITCH_T: + if (cplb_data[i].attr & SWITCH_T) { + t_i = &cplb.switch_i; + t_d = &cplb.switch_d; + process = 1; + } else + process = 0; + break; + default: + process = 0; + break; + } + + if (!process) + continue; + if (cplb_data[i].attr & I_CPLB) + __fill_code_cplbtab(t_i, i, a_start, a_end); + + if (cplb_data[i].attr & D_CPLB) + __fill_data_cplbtab(t_d, i, a_start, a_end); + } + } + +/* close tables */ + + close_cplbtab(&cplb.init_i); + close_cplbtab(&cplb.init_d); + + cplb.init_i.tab[cplb.init_i.pos] = -1; + cplb.init_d.tab[cplb.init_d.pos] = -1; + cplb.switch_i.tab[cplb.switch_i.pos] = -1; + cplb.switch_d.tab[cplb.switch_d.pos] = -1; + +} + +#endif + diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 534227f..07c1cfd 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -64,10 +64,6 @@ EXPORT_SYMBOL(mtd_size); char __initdata command_line[COMMAND_LINE_SIZE]; -#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE) -static void generate_cpl_tables(void); -#endif - void __init bf53x_cache_init(void) { #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE) @@ -401,8 +397,6 @@ void __init setup_arch(char **cmdline_p) _bfin_swrst = bfin_read_SWRST(); #endif - bf53x_cache_init(); - printk(KERN_INFO "Hardware Trace Enabled\n"); bfin_write_TBUFCTL(0x03); @@ -426,6 +420,8 @@ void __init setup_arch(char **cmdline_p) != ATOMIC_AND32 - FIXED_CODE_START); BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start != ATOMIC_XOR32 - FIXED_CODE_START); + + bf53x_cache_init(); } static int __init topology_init(void) @@ -443,287 +439,6 @@ static int __init topology_init(void) subsys_initcall(topology_init); -#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE) -static u16 __init lock_kernel_check(u32 start, u32 end) -{ - if ((start <= (u32) _stext && end >= (u32) _end) - || (start >= (u32) _stext && end <= (u32) _end)) - return IN_KERNEL; - return 0; -} - -static unsigned short __init -fill_cplbtab(struct cplb_tab *table, - unsigned long start, unsigned long end, - unsigned long block_size, unsigned long cplb_data) -{ - int i; - - switch (block_size) { - case SIZE_4M: - i = 3; - break; - case SIZE_1M: - i = 2; - break; - case SIZE_4K: - i = 1; - break; - case SIZE_1K: - default: - i = 0; - break; - } - - cplb_data = (cplb_data & ~(3 << 16)) | (i << 16); - - while ((start < end) && (table->pos < table->size)) { - - table->tab[table->pos++] = start; - - if (lock_kernel_check(start, start + block_size) == IN_KERNEL) - table->tab[table->pos++] = - cplb_data | CPLB_LOCK | CPLB_DIRTY; - else - table->tab[table->pos++] = cplb_data; - - start += block_size; - } - return 0; -} - -static unsigned short __init -close_cplbtab(struct cplb_tab *table) -{ - - while (table->pos < table->size) { - - table->tab[table->pos++] = 0; - table->tab[table->pos++] = 0; /* !CPLB_VALID */ - } - return 0; -} - -/* helper function */ -static void __fill_code_cplbtab(struct cplb_tab *t, int i, - u32 a_start, u32 a_end) -{ - if (cplb_data[i].psize) { - fill_cplbtab(t, - cplb_data[i].start, - cplb_data[i].end, - cplb_data[i].psize, - cplb_data[i].i_conf); - } else { -#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263)) - if (i == SDRAM_KERN) { - fill_cplbtab(t, - cplb_data[i].start, - cplb_data[i].end, - SIZE_4M, - cplb_data[i].i_conf); - } else -#endif - { - fill_cplbtab(t, - cplb_data[i].start, - a_start, - SIZE_1M, - cplb_data[i].i_conf); - fill_cplbtab(t, - a_start, - a_end, - SIZE_4M, - cplb_data[i].i_conf); - fill_cplbtab(t, a_end, - cplb_data[i].end, - SIZE_1M, - cplb_data[i].i_conf); - } - } -} - -static void __fill_data_cplbtab(struct cplb_tab *t, int i, - u32 a_start, u32 a_end) -{ - if (cplb_data[i].psize) { - fill_cplbtab(t, - cplb_data[i].start, - cplb_data[i].end, - cplb_data[i].psize, - cplb_data[i].d_conf); - } else { - fill_cplbtab(t, - cplb_data[i].start, - a_start, SIZE_1M, - cplb_data[i].d_conf); - fill_cplbtab(t, a_start, - a_end, SIZE_4M, - cplb_data[i].d_conf); - fill_cplbtab(t, a_end, - cplb_data[i].end, - SIZE_1M, - cplb_data[i].d_conf); - } -} -static void __init generate_cpl_tables(void) -{ - - u16 i, j, process; - u32 a_start, a_end, as, ae, as_1m; - - struct cplb_tab *t_i = NULL; - struct cplb_tab *t_d = NULL; - struct s_cplb cplb; - - cplb.init_i.size = MAX_CPLBS; - cplb.init_d.size = MAX_CPLBS; - cplb.switch_i.size = MAX_SWITCH_I_CPLBS; - cplb.switch_d.size = MAX_SWITCH_D_CPLBS; - - cplb.init_i.pos = 0; - cplb.init_d.pos = 0; - cplb.switch_i.pos = 0; - cplb.switch_d.pos = 0; - - cplb.init_i.tab = icplb_table; - cplb.init_d.tab = dcplb_table; - cplb.switch_i.tab = ipdt_table; - cplb.switch_d.tab = dpdt_table; - - cplb_data[SDRAM_KERN].end = memory_end; - -#ifdef CONFIG_MTD_UCLINUX - cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start; - cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size; - cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0; -# if defined(CONFIG_ROMFS_FS) - cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB; - - /* - * The ROMFS_FS size is often not multiple of 1MB. - * This can cause multiple CPLB sets covering the same memory area. - * This will then cause multiple CPLB hit exceptions. - * Workaround: We ensure a contiguous memory area by extending the kernel - * memory section over the mtd section. - * For ROMFS_FS memory must be covered with ICPLBs anyways. - * So there is no difference between kernel and mtd memory setup. - */ - - cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;; - cplb_data[SDRAM_RAM_MTD].valid = 0; - -# endif -#else - cplb_data[SDRAM_RAM_MTD].valid = 0; -#endif - - cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION; - cplb_data[SDRAM_DMAZ].end = _ramend; - - cplb_data[RES_MEM].start = _ramend; - cplb_data[RES_MEM].end = physical_mem_end; - - if (reserved_mem_dcache_on) - cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC; - else - cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL; - - if (reserved_mem_icache_on) - cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC; - else - cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL; - - for (i = ZERO_P; i <= L2_MEM; i++) { - if (!cplb_data[i].valid) - continue; - - as_1m = cplb_data[i].start % SIZE_1M; - - /* - * We need to make sure all sections are properly 1M aligned - * However between Kernel Memory and the Kernel mtd section, - * depending on the rootfs size, there can be overlapping - * memory areas. - */ - - if (as_1m && i != L1I_MEM && i != L1D_MEM) { -#ifdef CONFIG_MTD_UCLINUX - if (i == SDRAM_RAM_MTD) { - if ((cplb_data[SDRAM_KERN].end + 1) > - cplb_data[SDRAM_RAM_MTD].start) - cplb_data[SDRAM_RAM_MTD].start = - (cplb_data[i].start & - (-2*SIZE_1M)) + SIZE_1M; - else - cplb_data[SDRAM_RAM_MTD].start = - (cplb_data[i].start & - (-2*SIZE_1M)); - } else -#endif - printk(KERN_WARNING - "Unaligned Start of %s at 0x%X\n", - cplb_data[i].name, cplb_data[i].start); - } - - as = cplb_data[i].start % SIZE_4M; - ae = cplb_data[i].end % SIZE_4M; - - if (as) - a_start = cplb_data[i].start + (SIZE_4M - (as)); - else - a_start = cplb_data[i].start; - - a_end = cplb_data[i].end - ae; - - for (j = INITIAL_T; j <= SWITCH_T; j++) { - - switch (j) { - case INITIAL_T: - if (cplb_data[i].attr & INITIAL_T) { - t_i = &cplb.init_i; - t_d = &cplb.init_d; - process = 1; - } else - process = 0; - break; - case SWITCH_T: - if (cplb_data[i].attr & SWITCH_T) { - t_i = &cplb.switch_i; - t_d = &cplb.switch_d; - process = 1; - } else - process = 0; - break; - default: - process = 0; - break; - } - - if (!process) - continue; - if (cplb_data[i].attr & I_CPLB) - __fill_code_cplbtab(t_i, i, a_start, a_end); - - if (cplb_data[i].attr & D_CPLB) - __fill_data_cplbtab(t_d, i, a_start, a_end); - } - } - -/* close tables */ - - close_cplbtab(&cplb.init_i); - close_cplbtab(&cplb.init_d); - - cplb.init_i.tab[cplb.init_i.pos] = -1; - cplb.init_d.tab[cplb.init_d.pos] = -1; - cplb.switch_i.tab[cplb.switch_i.pos] = -1; - cplb.switch_d.tab[cplb.switch_d.pos] = -1; - -} - -#endif - static u_long get_vco(void) { u_long msel; diff --git a/arch/blackfin/mach-common/cacheinit.S b/arch/blackfin/mach-common/cacheinit.S index 7924a90..9d47562 100644 --- a/arch/blackfin/mach-common/cacheinit.S +++ b/arch/blackfin/mach-common/cacheinit.S @@ -38,104 +38,37 @@ .text +#ifdef ANOMALY_05000125 #if defined(CONFIG_BLKFIN_CACHE) -ENTRY(_bfin_icache_init) +ENTRY(_bfin_write_IMEM_CONTROL) - /* Initialize Instruction CPLBS */ - - I0.L = (ICPLB_ADDR0 & 0xFFFF); - I0.H = (ICPLB_ADDR0 >> 16); - - I1.L = (ICPLB_DATA0 & 0xFFFF); - I1.H = (ICPLB_DATA0 >> 16); - - I2.L = _icplb_table; - I2.H = _icplb_table; - - r1 = -1; /* end point comparison */ - r3 = 15; /* max counter */ - -/* read entries from table */ - -.Lread_iaddr: - R0 = [I2++]; - CC = R0 == R1; - IF CC JUMP .Lidone; - [I0++] = R0; - -.Lread_idata: - R2 = [I2++]; - [I1++] = R2; - R3 = R3 + R1; - CC = R3 == R1; - IF !CC JUMP .Lread_iaddr; - -.Lidone: /* Enable Instruction Cache */ P0.l = (IMEM_CONTROL & 0xFFFF); P0.h = (IMEM_CONTROL >> 16); - R1 = [P0]; - R0 = (IMC | ENICPLB); - R0 = R0 | R1; /* Anomaly 05000125 */ - CLI R2; + CLI R1; SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ .align 8; [P0] = R0; SSYNC; - STI R2; + STI R1; RTS; -ENDPROC(_bfin_icache_init) +ENDPROC(_bfin_write_IMEM_CONTROL) #endif #if defined(CONFIG_BLKFIN_DCACHE) -ENTRY(_bfin_dcache_init) - - /* Initialize Data CPLBS */ - - I0.L = (DCPLB_ADDR0 & 0xFFFF); - I0.H = (DCPLB_ADDR0 >> 16); - - I1.L = (DCPLB_DATA0 & 0xFFFF); - I1.H = (DCPLB_DATA0 >> 16); - - I2.L = _dcplb_table; - I2.H = _dcplb_table; - - R1 = -1; /* end point comparison */ - R3 = 15; /* max counter */ - - /* read entries from table */ -.Lread_daddr: - R0 = [I2++]; - cc = R0 == R1; - IF CC JUMP .Lddone; - [I0++] = R0; - -.Lread_ddata: - R2 = [I2++]; - [I1++] = R2; - R3 = R3 + R1; - CC = R3 == R1; - IF !CC JUMP .Lread_daddr; -.Lddone: - P0.L = (DMEM_CONTROL & 0xFFFF); - P0.H = (DMEM_CONTROL >> 16); - R1 = [P0]; - - R0 = DMEM_CNTR; - - R0 = R0 | R1; - /* Anomaly 05000125 */ - CLI R2; +ENTRY(_bfin_write_DMEM_CONTROL) + CLI R1; SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ .align 8; [P0] = R0; SSYNC; - STI R2; + STI R1; RTS; -ENDPROC(_bfin_dcache_init) +ENDPROC(_bfin_write_DMEM_CONTROL) +#endif + #endif diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h index e14ea39..bec6ecd 100644 --- a/include/asm-blackfin/cplbinit.h +++ b/include/asm-blackfin/cplbinit.h @@ -57,8 +57,8 @@ struct cplb_tab { u16 size; }; -u_long icplb_table[MAX_CPLBS+1]; -u_long dcplb_table[MAX_CPLBS+1]; +extern u_long icplb_table[MAX_CPLBS+1]; +extern u_long dcplb_table[MAX_CPLBS+1]; /* Till here we are discussing about the static memory management model. * However, the operating envoronments commonly define more CPLB @@ -70,134 +70,27 @@ u_long dcplb_table[MAX_CPLBS+1]; */ #ifdef CONFIG_CPLB_SWITCH_TAB_L1 -u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data)); -u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data)); +extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data)); +extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data)); #ifdef CONFIG_CPLB_INFO -u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data)); -u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data)); +extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data)); +extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data)); #endif /* CONFIG_CPLB_INFO */ #else -u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]; -u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]; +extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]; +extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]; #ifdef CONFIG_CPLB_INFO -u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]; -u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]; +extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]; +extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]; #endif /* CONFIG_CPLB_INFO */ #endif /*CONFIG_CPLB_SWITCH_TAB_L1*/ -struct s_cplb { - struct cplb_tab init_i; - struct cplb_tab init_d; - struct cplb_tab switch_i; - struct cplb_tab switch_d; -}; +extern unsigned long reserved_mem_dcache_on; +extern unsigned long reserved_mem_icache_on; -#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE) -static struct cplb_desc cplb_data[] = { - { - .start = 0, - .end = SIZE_1K, - .psize = SIZE_1K, - .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, - .i_conf = SDRAM_OOPS, - .d_conf = SDRAM_OOPS, -#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO) - .valid = 1, -#else - .valid = 0, -#endif - .name = "ZERO Pointer Saveguard", - }, - { - .start = L1_CODE_START, - .end = L1_CODE_START + L1_CODE_LENGTH, - .psize = SIZE_4M, - .attr = INITIAL_T | SWITCH_T | I_CPLB, - .i_conf = L1_IMEMORY, - .d_conf = 0, - .valid = 1, - .name = "L1 I-Memory", - }, - { - .start = L1_DATA_A_START, - .end = L1_DATA_B_START + L1_DATA_B_LENGTH, - .psize = SIZE_4M, - .attr = INITIAL_T | SWITCH_T | D_CPLB, - .i_conf = 0, - .d_conf = L1_DMEMORY, -#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0)) - .valid = 1, -#else - .valid = 0, -#endif - .name = "L1 D-Memory", - }, - { - .start = 0, - .end = 0, /* dynamic */ - .psize = 0, - .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, - .i_conf = SDRAM_IGENERIC, - .d_conf = SDRAM_DGENERIC, - .valid = 1, - .name = "SDRAM Kernel", - }, - { - .start = 0, /* dynamic */ - .end = 0, /* dynamic */ - .psize = 0, - .attr = INITIAL_T | SWITCH_T | D_CPLB, - .i_conf = SDRAM_IGENERIC, - .d_conf = SDRAM_DNON_CHBL, - .valid = 1, - .name = "SDRAM RAM MTD", - }, - { - .start = 0, /* dynamic */ - .end = 0, /* dynamic */ - .psize = SIZE_1M, - .attr = INITIAL_T | SWITCH_T | D_CPLB, - .d_conf = SDRAM_DNON_CHBL, - .valid = 1,//(DMA_UNCACHED_REGION > 0), - .name = "SDRAM Uncached DMA ZONE", - }, - { - .start = 0, /* dynamic */ - .end = 0, /* dynamic */ - .psize = 0, - .attr = SWITCH_T | D_CPLB, - .i_conf = 0, /* dynamic */ - .d_conf = 0, /* dynamic */ - .valid = 1, - .name = "SDRAM Reserved Memory", - }, - { - .start = ASYNC_BANK0_BASE, - .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE, - .psize = 0, - .attr = SWITCH_T | D_CPLB, - .d_conf = SDRAM_EBIU, - .valid = 1, - .name = "ASYNC Memory", - }, - { -#if defined(CONFIG_BF561) - .start = L2_SRAM, - .end = L2_SRAM_END, - .psize = SIZE_1M, - .attr = SWITCH_T | D_CPLB, - .i_conf = L2_MEMORY, - .d_conf = L2_MEMORY, - .valid = 1, -#else - .valid = 0, -#endif - .name = "L2 Memory", - } -}; -#endif +extern void generate_cpl_tables(void); diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h index 58f8789..94ed381 100644 --- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h +++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h @@ -40,16 +40,7 @@ #define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val) #define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) #ifdef ANOMALY_05000125 -static __inline__ void bfin_write_DMEM_CONTROL(unsigned int val) -{ - unsigned long flags, iwr; - - local_irq_save(flags); - __asm__(".align 8\n"); - bfin_write32(IMEM_CONTROL, val); - __builtin_bfin_ssync(); - local_irq_restore(flags); -} +extern void bfin_write_DMEM_CONTROL(unsigned int val); #else #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val) #endif @@ -139,17 +130,7 @@ static __inline__ void bfin_write_DMEM_CONTROL(unsigned int val) */ #define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) #ifdef ANOMALY_05000125 -static __inline__ void bfin_write_IMEM_CONTROL(unsigned int val) -{ - unsigned long flags, iwr; - - local_irq_save(flags); - __asm__(".align 8\n"); - bfin_write32(IMEM_CONTROL, val); - __builtin_bfin_ssync(); - local_irq_restore(flags); - -} +extern void bfin_write_IMEM_CONTROL(unsigned int val); #else #define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val) #endif -- cgit v0.10.2 From 669b792c77bbc30e9f4d9c95dbc918dc348c49c2 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Thu, 21 Jun 2007 16:34:08 +0800 Subject: Blackfin arch: Clean up trace buffer handling, No major functional changes. Turns on trace earlier, so crashes at kernel start should print out a trace, making things easier to debug. Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 07c1cfd..a86bf65 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -194,6 +194,17 @@ void __init setup_arch(char **cmdline_p) /* this give a chance to get printk() working before crash. */ #endif + printk(KERN_INFO "Hardware Trace "); + if (bfin_read_TBUFCTL() & 0x1 ) + printk("Active "); + else + printk("Off "); + if (bfin_read_TBUFCTL() & 0x2) + printk("and Enabled\n"); + else + printk("and Disabled\n"); + + #if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH) /* we need to initialize the Flashrom device here since we might * do things with flash early on in the boot @@ -397,9 +408,6 @@ void __init setup_arch(char **cmdline_p) _bfin_swrst = bfin_read_SWRST(); #endif - printk(KERN_INFO "Hardware Trace Enabled\n"); - bfin_write_TBUFCTL(0x03); - /* Copy atomic sequences to their fixed location, and sanity check that these locations are the ones that we advertise to userspace. */ memcpy((void *)FIXED_CODE_START, &fixed_code_start, diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index 56058b0..a58d0f5 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -131,16 +132,6 @@ static int printk_address(unsigned long address) return printk("[<0x%p>]", (void*)address); } -#define trace_buffer_save(x) \ - do { \ - (x) = bfin_read_TBUFCTL(); \ - bfin_write_TBUFCTL((x) & ~TBUFEN); \ - } while (0) -#define trace_buffer_restore(x) \ - do { \ - bfin_write_TBUFCTL((x)); \ - } while (0) - asmlinkage void trap_c(struct pt_regs *fp) { int j, sig = 0; diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S index 7e2aa8d..7dd0e9c 100644 --- a/arch/blackfin/mach-bf533/head.S +++ b/arch/blackfin/mach-bf533/head.S @@ -30,6 +30,7 @@ #include #include #include +#include #if CONFIG_BFIN_KERNEL_CLOCK #include #endif @@ -96,6 +97,10 @@ ENTRY(__start) M2 = r0; M3 = r0; + trace_buffer_start(p0,r0); + P0 = R1; + R0 = R1; + #if CONFIG_DEBUG_KERNEL_START /* diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index 7d902bb..429c8a1 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S @@ -30,6 +30,8 @@ #include #include #include +#include + #if CONFIG_BFIN_KERNEL_CLOCK #include #endif @@ -93,6 +95,10 @@ ENTRY(__start) M2 = r0; M3 = r0; + trace_buffer_start(p0,r0); + P0 = R1; + R0 = R1; + /* Turn off the icache */ p0.l = (IMEM_CONTROL & 0xFFFF); p0.h = (IMEM_CONTROL >> 16); diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S index 0e1a254..06751ae 100644 --- a/arch/blackfin/mach-bf548/head.S +++ b/arch/blackfin/mach-bf548/head.S @@ -29,6 +29,7 @@ #include #include +#include #if CONFIG_BFIN_KERNEL_CLOCK #include #endif @@ -91,6 +92,10 @@ ENTRY(__stext) M2 = r0; M3 = r0; + trace_buffer_start(p0,r0); + P0 = R1; + R0 = R1; + /* Turn off the icache */ p0.l = (IMEM_CONTROL & 0xFFFF); p0.h = (IMEM_CONTROL >> 16); diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S index 31cbc75..2f08bcb 100644 --- a/arch/blackfin/mach-bf561/head.S +++ b/arch/blackfin/mach-bf561/head.S @@ -30,6 +30,8 @@ #include #include #include +#include + #if CONFIG_BFIN_KERNEL_CLOCK #include #endif @@ -93,6 +95,10 @@ ENTRY(__start) M2 = r0; M3 = r0; + trace_buffer_start(p0,r0); + P0 = R1; + R0 = R1; + /* Turn off the icache */ p0.l = (IMEM_CONTROL & 0xFFFF); p0.h = (IMEM_CONTROL >> 16); diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index c4a32ea..1560327 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -54,29 +54,10 @@ #include #include /* TIF_NEED_RESCHED */ #include +#include #include -#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE - /* - * TODO: this should be proper save/restore, but for now - * we'll just cheat and use 0x1/0x13 - */ -# define DEBUG_START_HWTRACE \ - P5.l = LO(TBUFCTL); \ - P5.h = HI(TBUFCTL); \ - R7 = 0x13; \ - [P5] = R7; -# define DEBUG_STOP_HWTRACE \ - P5.l = LO(TBUFCTL); \ - P5.h = HI(TBUFCTL); \ - R7 = 0x01; \ - [P5] = R7; -#else -# define DEBUG_START_HWTRACE -# define DEBUG_STOP_HWTRACE -#endif - #ifdef CONFIG_EXCPT_IRQ_SYSC_L1 .section .l1.text #else @@ -110,7 +91,7 @@ ENTRY(_ex_icplb) ASTAT = [sp++]; SAVE_ALL_SYS call __cplb_hdr; - DEBUG_START_HWTRACE + DEBUG_START_HWTRACE(p5, r7) RESTORE_ALL_SYS SP = RETN; rtx; @@ -128,7 +109,7 @@ ENTRY(_ex_spinlock) ENDPROC(_ex_spinlock) ENTRY(_ex_syscall) - DEBUG_START_HWTRACE + DEBUG_START_HWTRACE(p5, r7) (R7:6,P5:4) = [sp++]; ASTAT = [sp++]; raise 15; /* invoked by TRAP #0, for sys call */ @@ -186,7 +167,7 @@ ENTRY(_ex_single_step) if !cc jump _ex_trap_c; _return_from_exception: - DEBUG_START_HWTRACE + DEBUG_START_HWTRACE(p5, r7) #ifdef ANOMALY_05000257 R7=LC0; LC0=R7; @@ -208,7 +189,7 @@ ENTRY(_handle_bad_cplb) * need to make a CPLB exception look like a normal exception */ - DEBUG_START_HWTRACE + DEBUG_START_HWTRACE(p5, r7) RESTORE_ALL_SYS [--sp] = ASTAT; [--sp] = (R7:6, P5:4); @@ -251,7 +232,7 @@ ENTRY(_ex_trap_c) R6 = SEQSTAT; [P5] = R6; - DEBUG_START_HWTRACE + DEBUG_START_HWTRACE(p5, r7) (R7:6,P5:4) = [sp++]; ASTAT = [sp++]; SP = RETN; @@ -335,7 +316,7 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/ /* Try to deal with syscalls quickly. */ [--sp] = ASTAT; [--sp] = (R7:6, P5:4); - DEBUG_STOP_HWTRACE + DEBUG_STOP_HWTRACE(p5, r7) r7 = SEQSTAT; /* reason code is in bit 5:0 */ r6.l = lo(SEQSTAT_EXCAUSE); r6.h = hi(SEQSTAT_EXCAUSE); diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S index 8be548e..203e207 100644 --- a/arch/blackfin/mach-common/interrupt.S +++ b/arch/blackfin/mach-common/interrupt.S @@ -34,6 +34,7 @@ #include #include #include +#include #include @@ -170,10 +171,9 @@ ENTRY(_evt_ivhw) r7.l = W[p5]; 1: #endif - p0.l = lo(TBUFCTL); - p0.h = hi(TBUFCTL); - r0 = 1; - [p0] = r0; + + trace_buffer_stop(p0, r0); + r0 = IRQ_HWERR; r1 = sp; diff --git a/include/asm-blackfin/trace.h b/include/asm-blackfin/trace.h new file mode 100644 index 0000000..9c2474c --- /dev/null +++ b/include/asm-blackfin/trace.h @@ -0,0 +1,52 @@ +/* + * Common header file for blackfin family of processors. + * + */ + +#ifndef _BLACKFIN_TRACE_ +#define _BLACKFIN_TRACE_ + +#ifndef __ASSEMBLY__ +/* Trace Macros for C files */ + +#define trace_buffer_save(x) \ + do { \ + (x) = bfin_read_TBUFCTL(); \ + bfin_write_TBUFCTL((x) & ~TBUFEN); \ + } while (0) + +#define trace_buffer_restore(x) \ + do { \ + bfin_write_TBUFCTL((x)); \ + } while (0) + +#else +/* Trace Macros for Assembly files */ + +#define TRACE_BUFFER_START(preg, dreg) trace_buffer_start(preg, dreg) +#define TRACE_BUFFER_STOP(preg, dreg) trace_buffer_stop(preg, dreg) + +#define trace_buffer_stop(preg, dreg) \ + preg.L = LO(TBUFCTL); \ + preg.H = HI(TBUFCTL); \ + dreg = 0x1; \ + [preg] = dreg; + +#define trace_buffer_start(preg, dreg) \ + preg.L = LO(TBUFCTL); \ + preg.H = HI(TBUFCTL); \ + dreg = 0x13; \ + [preg] = dreg; + +#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE +# define DEBUG_START_HWTRACE(preg, dreg) trace_buffer_start(preg, dreg) +# define DEBUG_STOP_HWTRACE(preg, dreg) trace_buffer_stop(preg, dreg) + +#else +# define DEBUG_START_HWTRACE(preg, dreg) +# define DEBUG_STOP_HWTRACE(preg, dreg) +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* _BLACKFIN_TRACE_ */ -- cgit v0.10.2 From 1f83b8f148a1eb967d2a628cbb741cd56fb54572 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 12 Jul 2007 22:58:21 +0800 Subject: Blackfin arch: cleanup warnings from checkpatch -- no functional changes Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c index e455f45..b56b274 100644 --- a/arch/blackfin/kernel/asm-offsets.c +++ b/arch/blackfin/kernel/asm-offsets.c @@ -32,11 +32,10 @@ #include #include #include -#include -#include +#include +#include -#define DEFINE(sym, val) \ - asm volatile("\n->" #sym " %0 " #val : : "i" (val)) +#define DEFINE(sym, val) asm volatile("\n->" #sym " %0 " #val : : "i" (val)) int main(void) { diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c index 8a16c2b..7cf02f0 100644 --- a/arch/blackfin/kernel/bfin_dma_5xx.c +++ b/arch/blackfin/kernel/bfin_dma_5xx.c @@ -332,7 +332,7 @@ set_bfin_dma_config(char direction, char flow_mode, } EXPORT_SYMBOL(set_bfin_dma_config); -void set_dma_sg(unsigned int channel, struct dmasg * sg, int nr_sg) +void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg) { BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE && channel < MAX_BLACKFIN_DMA_CHANNEL)); @@ -401,7 +401,7 @@ static void *__dma_memcpy(void *dest, const void *src, size_t size) if (size <= 0) return NULL; - + local_irq_save(flags); if ((unsigned long)src < memory_end) @@ -545,7 +545,6 @@ void *dma_memcpy(void *dest, const void *src, size_t size) addr = __dma_memcpy(dest+bulk, src+bulk, rest); return addr; } - EXPORT_SYMBOL(dma_memcpy); void *safe_dma_memcpy(void *dest, const void *src, size_t size) @@ -558,14 +557,13 @@ EXPORT_SYMBOL(safe_dma_memcpy); void dma_outsb(void __iomem *addr, const void *buf, unsigned short len) { - unsigned long flags; - + local_irq_save(flags); - - blackfin_dcache_flush_range((unsigned int)buf,(unsigned int)(buf) + len); - bfin_write_MDMA_D0_START_ADDR(addr); + blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len); + + bfin_write_MDMA_D0_START_ADDR(addr); bfin_write_MDMA_D0_X_COUNT(len); bfin_write_MDMA_D0_X_MODIFY(0); bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); @@ -593,9 +591,9 @@ EXPORT_SYMBOL(dma_outsb); void dma_insb(const void __iomem *addr, void *buf, unsigned short len) { unsigned long flags; - + local_irq_save(flags); - bfin_write_MDMA_D0_START_ADDR(buf); + bfin_write_MDMA_D0_START_ADDR(buf); bfin_write_MDMA_D0_X_COUNT(len); bfin_write_MDMA_D0_X_MODIFY(1); bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); @@ -624,12 +622,12 @@ EXPORT_SYMBOL(dma_insb); void dma_outsw(void __iomem *addr, const void *buf, unsigned short len) { unsigned long flags; - + local_irq_save(flags); - - blackfin_dcache_flush_range((unsigned int)buf,(unsigned int)(buf) + len); - bfin_write_MDMA_D0_START_ADDR(addr); + blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len); + + bfin_write_MDMA_D0_START_ADDR(addr); bfin_write_MDMA_D0_X_COUNT(len); bfin_write_MDMA_D0_X_MODIFY(0); bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); @@ -656,10 +654,10 @@ EXPORT_SYMBOL(dma_outsw); void dma_insw(const void __iomem *addr, void *buf, unsigned short len) { unsigned long flags; - + local_irq_save(flags); - - bfin_write_MDMA_D0_START_ADDR(buf); + + bfin_write_MDMA_D0_START_ADDR(buf); bfin_write_MDMA_D0_X_COUNT(len); bfin_write_MDMA_D0_X_MODIFY(2); bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); @@ -688,12 +686,12 @@ EXPORT_SYMBOL(dma_insw); void dma_outsl(void __iomem *addr, const void *buf, unsigned short len) { unsigned long flags; - + local_irq_save(flags); - - blackfin_dcache_flush_range((unsigned int)buf,(unsigned int)(buf) + len); - bfin_write_MDMA_D0_START_ADDR(addr); + blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len); + + bfin_write_MDMA_D0_START_ADDR(addr); bfin_write_MDMA_D0_X_COUNT(len); bfin_write_MDMA_D0_X_MODIFY(0); bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); @@ -720,10 +718,10 @@ EXPORT_SYMBOL(dma_outsl); void dma_insl(const void __iomem *addr, void *buf, unsigned short len) { unsigned long flags; - + local_irq_save(flags); - - bfin_write_MDMA_D0_START_ADDR(buf); + + bfin_write_MDMA_D0_START_ADDR(buf); bfin_write_MDMA_D0_X_COUNT(len); bfin_write_MDMA_D0_X_MODIFY(4); bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index bb1f4fb..bafcfa5 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -162,7 +162,7 @@ static void port_setup(unsigned short gpio, unsigned short usage) static void default_gpio(unsigned short gpio) { - unsigned short bank,bitmask; + unsigned short bank, bitmask; bank = gpio_bank(gpio); bitmask = gpio_bit(gpio); @@ -183,7 +183,7 @@ static int __init bfin_gpio_init(void) printk(KERN_INFO "Blackfin GPIO Controller\n"); - for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=GPIO_BANKSIZE) + for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) reserved_map[gpio_bank(i)] = 0; #if defined(BF537_FAMILY) && (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) @@ -478,7 +478,7 @@ u32 gpio_pm_setup(void) u32 sic_iwr = 0; u16 bank, mask, i, gpio; - for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=GPIO_BANKSIZE) { + for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { mask = wakeup_map[gpio_bank(i)]; bank = gpio_bank(i); @@ -522,12 +522,11 @@ u32 gpio_pm_setup(void) return IWR_ENABLE_ALL; } - void gpio_pm_restore(void) { u16 bank, mask, i; - for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=GPIO_BANKSIZE) { + for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { mask = wakeup_map[gpio_bank(i)]; bank = gpio_bank(i); @@ -591,7 +590,6 @@ int gpio_request(unsigned short gpio, const char *label) } EXPORT_SYMBOL(gpio_request); - void gpio_free(unsigned short gpio) { unsigned long flags; @@ -616,7 +614,6 @@ void gpio_free(unsigned short gpio) } EXPORT_SYMBOL(gpio_free); - void gpio_direction_input(unsigned short gpio) { unsigned long flags; diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c index f64ecb6..7045594 100644 --- a/arch/blackfin/kernel/bfin_ksyms.c +++ b/arch/blackfin/kernel/bfin_ksyms.c @@ -28,10 +28,11 @@ */ #include -#include +#include +#include + #include #include -#include /* platform dependent support */ diff --git a/arch/blackfin/kernel/dma-mapping.c b/arch/blackfin/kernel/dma-mapping.c index 539eb24..bda57ec 100644 --- a/arch/blackfin/kernel/dma-mapping.c +++ b/arch/blackfin/kernel/dma-mapping.c @@ -34,8 +34,8 @@ #include #include #include +#include #include -#include #include static spinlock_t dma_page_lock; diff --git a/arch/blackfin/kernel/dualcore_test.c b/arch/blackfin/kernel/dualcore_test.c index 8b89c99..0fcba74 100644 --- a/arch/blackfin/kernel/dualcore_test.c +++ b/arch/blackfin/kernel/dualcore_test.c @@ -30,19 +30,19 @@ #include #include -static int *testarg = (int*)0xfeb00000; +static int *testarg = (int *)0xfeb00000; static int test_init(void) { *testarg = 1; - printk("Dual core test module inserted: set testarg = [%d]\n @ [%p]\n", + printk(KERN_INFO "Dual core test module inserted: set testarg = [%d]\n @ [%p]\n", *testarg, testarg); return 0; } static void test_exit(void) { - printk("Dual core test module removed: testarg = [%d]\n", *testarg); + printk(KERN_INFO "Dual core test module removed: testarg = [%d]\n", *testarg); } module_init(test_init); diff --git a/arch/blackfin/kernel/fixed_code.S b/arch/blackfin/kernel/fixed_code.S index 99ea296..d8b1ebc 100644 --- a/arch/blackfin/kernel/fixed_code.S +++ b/arch/blackfin/kernel/fixed_code.S @@ -8,8 +8,8 @@ * BF561 SMP). */ #include +#include #include -#include .text ENTRY(_fixed_code_start) diff --git a/arch/blackfin/kernel/flat.c b/arch/blackfin/kernel/flat.c index a92587b..d188b24 100644 --- a/arch/blackfin/kernel/flat.c +++ b/arch/blackfin/kernel/flat.c @@ -36,24 +36,22 @@ unsigned long bfin_get_addr_from_rp(unsigned long *ptr, unsigned long val; switch (type) { - case FLAT_BFIN_RELOC_TYPE_16_BIT: - case FLAT_BFIN_RELOC_TYPE_16H_BIT: - usptr = (unsigned short *)ptr; - pr_debug("*usptr = %x", get_unaligned(usptr)); - val = get_unaligned(usptr); - val += *persistent; - break; + case FLAT_BFIN_RELOC_TYPE_16_BIT: + case FLAT_BFIN_RELOC_TYPE_16H_BIT: + usptr = (unsigned short *)ptr; + pr_debug("*usptr = %x", get_unaligned(usptr)); + val = get_unaligned(usptr); + val += *persistent; + break; - case FLAT_BFIN_RELOC_TYPE_32_BIT: - pr_debug("*ptr = %lx", get_unaligned(ptr)); - val = get_unaligned(ptr); - break; + case FLAT_BFIN_RELOC_TYPE_32_BIT: + pr_debug("*ptr = %lx", get_unaligned(ptr)); + val = get_unaligned(ptr); + break; - default: - pr_debug("BINFMT_FLAT: Unknown relocation type %x\n", - type); - - return 0; + default: + pr_debug("BINFMT_FLAT: Unknown relocation type %x\n", type); + return 0; } /* @@ -81,21 +79,20 @@ void bfin_put_addr_at_rp(unsigned long *ptr, unsigned long addr, int type = (relval >> 26) & 7; switch (type) { - case FLAT_BFIN_RELOC_TYPE_16_BIT: - put_unaligned(addr, usptr); - pr_debug("new value %x at %p", get_unaligned(usptr), - usptr); - break; + case FLAT_BFIN_RELOC_TYPE_16_BIT: + put_unaligned(addr, usptr); + pr_debug("new value %x at %p", get_unaligned(usptr), usptr); + break; - case FLAT_BFIN_RELOC_TYPE_16H_BIT: - put_unaligned(addr >> 16, usptr); - pr_debug("new value %x", get_unaligned(usptr)); - break; + case FLAT_BFIN_RELOC_TYPE_16H_BIT: + put_unaligned(addr >> 16, usptr); + pr_debug("new value %x", get_unaligned(usptr)); + break; - case FLAT_BFIN_RELOC_TYPE_32_BIT: - put_unaligned(addr, ptr); - pr_debug("new ptr =%lx", get_unaligned(ptr)); - break; + case FLAT_BFIN_RELOC_TYPE_32_BIT: + put_unaligned(addr, ptr); + pr_debug("new ptr =%lx", get_unaligned(ptr)); + break; } } EXPORT_SYMBOL(bfin_put_addr_at_rp); diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c index 80996a1..1fc001c7 100644 --- a/arch/blackfin/kernel/irqchip.c +++ b/arch/blackfin/kernel/irqchip.c @@ -82,7 +82,7 @@ int show_interrupts(struct seq_file *p, void *v) seq_printf(p, ", %s", action->name); seq_putc(p, '\n'); - unlock: + unlock: spin_unlock_irqrestore(&irq_desc[i].lock, flags); } else if (i == NR_IRQS) { seq_printf(p, "Err: %10lu\n", irq_err_count); diff --git a/arch/blackfin/kernel/module.c b/arch/blackfin/kernel/module.c index 372f756..8b9fe29 100644 --- a/arch/blackfin/kernel/module.c +++ b/arch/blackfin/kernel/module.c @@ -165,8 +165,8 @@ module_frob_arch_sections(Elf_Ehdr * hdr, Elf_Shdr * sechdrs, for (s = sechdrs; s < sechdrs_end; ++s) { if ((strcmp(".l1.text", secstrings + s->sh_name) == 0) || - ((strcmp(".text", secstrings + s->sh_name)==0) && - (hdr->e_flags & FLG_CODE_IN_L1) && (s->sh_size > 0))) { + ((strcmp(".text", secstrings + s->sh_name) == 0) && + (hdr->e_flags & FLG_CODE_IN_L1) && (s->sh_size > 0))) { mod->arch.text_l1 = s; dest = l1_inst_sram_alloc(s->sh_size); if (dest == NULL) { @@ -179,9 +179,9 @@ module_frob_arch_sections(Elf_Ehdr * hdr, Elf_Shdr * sechdrs, s->sh_flags &= ~SHF_ALLOC; s->sh_addr = (unsigned long)dest; } - if ((strcmp(".l1.data", secstrings + s->sh_name) == 0)|| - ((strcmp(".data", secstrings + s->sh_name)==0) && - (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) { + if ((strcmp(".l1.data", secstrings + s->sh_name) == 0) || + ((strcmp(".data", secstrings + s->sh_name) == 0) && + (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) { mod->arch.data_a_l1 = s; dest = l1_data_sram_alloc(s->sh_size); if (dest == NULL) { @@ -195,8 +195,8 @@ module_frob_arch_sections(Elf_Ehdr * hdr, Elf_Shdr * sechdrs, s->sh_addr = (unsigned long)dest; } if (strcmp(".l1.bss", secstrings + s->sh_name) == 0 || - ((strcmp(".bss", secstrings + s->sh_name)==0) && - (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) { + ((strcmp(".bss", secstrings + s->sh_name) == 0) && + (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) { mod->arch.bss_a_l1 = s; dest = l1_data_sram_alloc(s->sh_size); if (dest == NULL) { @@ -326,7 +326,7 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab, pr_debug("before %x after %x\n", *location16, (value & 0xffff)); tmp = (value & 0xffff); - if((unsigned long)location16 >= L1_CODE_START) { + if ((unsigned long)location16 >= L1_CODE_START) { dma_memcpy(location16, &tmp, 2); } else *location16 = tmp; @@ -335,7 +335,7 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab, pr_debug("before %x after %x\n", *location16, ((value >> 16) & 0xffff)); tmp = ((value >> 16) & 0xffff); - if((unsigned long)location16 >= L1_CODE_START) { + if ((unsigned long)location16 >= L1_CODE_START) { dma_memcpy(location16, &tmp, 2); } else *location16 = tmp; @@ -404,8 +404,8 @@ module_finalize(const Elf_Ehdr * hdr, continue; if ((sechdrs[i].sh_type == SHT_RELA) && - ((strcmp(".rela.l1.text", secstrings + sechdrs[i].sh_name) == 0)|| - ((strcmp(".rela.text", secstrings + sechdrs[i].sh_name) == 0) && + ((strcmp(".rela.l1.text", secstrings + sechdrs[i].sh_name) == 0) || + ((strcmp(".rela.text", secstrings + sechdrs[i].sh_name) == 0) && (hdr->e_flags & FLG_CODE_IN_L1)))) { apply_relocate_add((Elf_Shdr *) sechdrs, strtab, symindex, i, mod); @@ -417,13 +417,13 @@ module_finalize(const Elf_Ehdr * hdr, void module_arch_cleanup(struct module *mod) { if ((mod->arch.text_l1) && (mod->arch.text_l1->sh_addr)) - l1_inst_sram_free((void*)mod->arch.text_l1->sh_addr); + l1_inst_sram_free((void *)mod->arch.text_l1->sh_addr); if ((mod->arch.data_a_l1) && (mod->arch.data_a_l1->sh_addr)) - l1_data_sram_free((void*)mod->arch.data_a_l1->sh_addr); + l1_data_sram_free((void *)mod->arch.data_a_l1->sh_addr); if ((mod->arch.bss_a_l1) && (mod->arch.bss_a_l1->sh_addr)) - l1_data_sram_free((void*)mod->arch.bss_a_l1->sh_addr); + l1_data_sram_free((void *)mod->arch.bss_a_l1->sh_addr); if ((mod->arch.data_b_l1) && (mod->arch.data_b_l1->sh_addr)) - l1_data_B_sram_free((void*)mod->arch.data_b_l1->sh_addr); + l1_data_B_sram_free((void *)mod->arch.data_b_l1->sh_addr); if ((mod->arch.bss_b_l1) && (mod->arch.bss_b_l1->sh_addr)) - l1_data_B_sram_free((void*)mod->arch.bss_b_l1->sh_addr); + l1_data_B_sram_free((void *)mod->arch.bss_b_l1->sh_addr); } diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index 6b7a94a..5a51dd6 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -32,9 +32,9 @@ #include #include #include +#include #include -#include #include #define LED_ON 0 @@ -174,8 +174,8 @@ void show_regs(struct pt_regs *regs) printk(KERN_NOTICE "R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n", regs->r4, regs->r5, regs->r6, regs->r7); - if (!(regs->ipend)) - printk("USP: %08lx\n", rdusp()); + if (!regs->ipend) + printk(KERN_NOTICE "USP: %08lx\n", rdusp()); } /* Fill in the fpu structure for a core dump. */ @@ -323,7 +323,7 @@ asmlinkage int sys_execve(char *name, char **argv, char **envp) goto out; error = do_execve(filename, argv, envp, regs); putname(filename); - out: + out: unlock_kernel(); return error; } @@ -421,7 +421,7 @@ int _access_ok(unsigned long addr, unsigned long size) if (addr > (addr + size)) return 0; - if (segment_eq(get_fs(),KERNEL_DS)) + if (segment_eq(get_fs(), KERNEL_DS)) return 1; #ifdef CONFIG_MTD_UCLINUX if (addr >= memory_start && (addr + size) <= memory_end) diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c index e718bb4..ed800c7 100644 --- a/arch/blackfin/kernel/ptrace.c +++ b/arch/blackfin/kernel/ptrace.c @@ -36,8 +36,8 @@ #include #include #include +#include -#include #include #include #include @@ -122,7 +122,7 @@ static inline long get_reg(struct task_struct *task, int regno) static inline int put_reg(struct task_struct *task, int regno, unsigned long data) { - char * reg_ptr; + char *reg_ptr; struct pt_regs *regs = (struct pt_regs *)((unsigned long)task_stack_page(task) + @@ -146,7 +146,7 @@ put_reg(struct task_struct *task, int regno, unsigned long data) break; default: if (regno <= 216) - *(long *)(reg_ptr + regno) = data; + *(long *)(reg_ptr + regno) = data; } return 0; } diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index a86bf65..3309238 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -362,15 +362,15 @@ void __init setup_arch(char **cmdline_p) , _stext, _etext, __start_rodata, __end_rodata, _sdata, _edata, - (void*)&init_thread_union, (void*)((int)(&init_thread_union) + 0x2000), + (void *)&init_thread_union, (void *)((int)(&init_thread_union) + 0x2000), __init_begin, __init_end, __bss_start, __bss_stop, - (void*)_ramstart, (void*)memory_end + (void *)_ramstart, (void *)memory_end #ifdef CONFIG_MTD_UCLINUX - , (void*)memory_mtd_start, (void*)(memory_mtd_start + mtd_size) + , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size) #endif #if DMA_UNCACHED_REGION > 0 - , (void*)(_ramend - DMA_UNCACHED_REGION), (void*)(_ramend) + , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend) #endif ); @@ -476,7 +476,6 @@ u_long get_cclk(void) return get_vco() / ssel; return get_vco() >> csel; } - EXPORT_SYMBOL(get_cclk); /* Get the System clock */ @@ -495,7 +494,6 @@ u_long get_sclk(void) return get_vco() / ssel; } - EXPORT_SYMBOL(get_sclk); /* @@ -550,23 +548,23 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "D-CACHE:\tOFF\n"); - switch(bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) { - case ACACHE_BSRAM: - seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n"); - dcache_size = 16; - dsup_banks = 1; - break; - case ACACHE_BCACHE: - seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n"); - dcache_size = 32; - dsup_banks = 2; - break; - case ASRAM_BSRAM: - seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n"); - dcache_size = 0; - dsup_banks = 0; - break; - default: + switch (bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) { + case ACACHE_BSRAM: + seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n"); + dcache_size = 16; + dsup_banks = 1; + break; + case ACACHE_BCACHE: + seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n"); + dcache_size = 32; + dsup_banks = 2; + break; + case ASRAM_BSRAM: + seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n"); + dcache_size = 0; + dsup_banks = 0; + break; + default: break; } diff --git a/arch/blackfin/kernel/signal.c b/arch/blackfin/kernel/signal.c index 316e65c..5564c95 100644 --- a/arch/blackfin/kernel/signal.c +++ b/arch/blackfin/kernel/signal.c @@ -34,8 +34,8 @@ #include #include #include +#include -#include #include #include @@ -124,7 +124,7 @@ asmlinkage int do_rt_sigreturn(unsigned long __unused) return r0; - badframe: + badframe: force_sig(SIGSEGV, current); return 0; } @@ -239,7 +239,7 @@ setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t * info, return 0; - give_sigsegv: + give_sigsegv: if (sig == SIGSEGV) ka->sa.sa_handler = SIG_DFL; force_sig(SIGSEGV, current); @@ -263,7 +263,7 @@ handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler) } /* fallthrough */ case -ERESTARTNOINTR: - do_restart: + do_restart: regs->p0 = regs->orig_p0; regs->r0 = regs->orig_r0; regs->pc -= 2; @@ -341,7 +341,7 @@ asmlinkage void do_signal(struct pt_regs *regs) return; } -no_signal: + no_signal: /* Did we come from a system call? */ if (regs->orig_p0 >= 0) /* Restart the system call - no handlers present */ diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c index f436e67..f5e1ae3 100644 --- a/arch/blackfin/kernel/sys_bfin.c +++ b/arch/blackfin/kernel/sys_bfin.c @@ -37,12 +37,12 @@ #include #include #include +#include +#include +#include #include -#include -#include #include -#include /* * sys_pipe() is the normal C calling standard for creating @@ -83,7 +83,7 @@ do_mmap2(unsigned long addr, unsigned long len, if (file) fput(file); - out: + out: return error; } diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c index f578176..beef057 100644 --- a/arch/blackfin/kernel/time.c +++ b/arch/blackfin/kernel/time.c @@ -87,7 +87,7 @@ void __init init_leds(void) static inline void do_leds(void) { static unsigned int count = 50; - static int flag = 0; + static int flag; unsigned short tmp = 0; if (--count == 0) { @@ -200,7 +200,7 @@ irqreturn_t timer_interrupt(int irq, void *dummy)__attribute__((l1_text)); irqreturn_t timer_interrupt(int irq, void *dummy) { /* last time the cmos clock got updated */ - static long last_rtc_update = 0; + static long last_rtc_update; write_seqlock(&xtime_lock); diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index a58d0f5..114277b 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -27,16 +27,15 @@ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include +#include +#include +#include +#include #include #include #include -#include #include #include -#include -#include -#include #ifdef CONFIG_KGDB # include @@ -77,7 +76,7 @@ static int printk_address(unsigned long address) if (!modname) modname = delim = ""; return printk("<0x%p> { %s%s%s%s + 0x%lx }", - (void*)address, delim, modname, delim, symname, + (void *)address, delim, modname, delim, symname, (unsigned long)offset); } @@ -120,7 +119,7 @@ static int printk_address(unsigned long address) write_unlock_irq(&tasklist_lock); return printk("<0x%p> [ %s + 0x%lx ]", - (void*)address, name, offset); + (void *)address, name, offset); } vml = vml->next; @@ -129,7 +128,7 @@ static int printk_address(unsigned long address) write_unlock_irq(&tasklist_lock); /* we were unable to find this address anywhere */ - return printk("[<0x%p>]", (void*)address); + return printk("[<0x%p>]", (void *)address); } asmlinkage void trap_c(struct pt_regs *fp) @@ -538,29 +537,28 @@ void dump_bfin_regs(struct pt_regs *fp, void *retaddr) printk(KERN_EMERG "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n" KERN_EMERG "BSS = 0x%p-0x%p USER-STACK = 0x%p\n" KERN_EMERG "\n", - (void*)current->mm->start_code, - (void*)current->mm->end_code, - (void*)current->mm->start_data, - (void*)current->mm->end_data, - (void*)current->mm->end_data, - (void*)current->mm->brk, - (void*)current->mm->start_stack); + (void *)current->mm->start_code, + (void *)current->mm->end_code, + (void *)current->mm->start_data, + (void *)current->mm->end_data, + (void *)current->mm->end_data, + (void *)current->mm->brk, + (void *)current->mm->start_stack); } printk(KERN_EMERG "return address: [0x%p]; contents of:", retaddr); - if (retaddr != 0 && retaddr <= (void*)physical_mem_end + if (retaddr != 0 && retaddr <= (void *)physical_mem_end #if L1_CODE_LENGTH != 0 /* FIXME: Copy the code out of L1 Instruction SRAM through dma memcpy. */ - && !(retaddr >= (void*)L1_CODE_START - && retaddr < (void*)(L1_CODE_START + L1_CODE_LENGTH)) + && !(retaddr >= (void *)L1_CODE_START + && retaddr < (void *)(L1_CODE_START + L1_CODE_LENGTH)) #endif ) { int i = ((unsigned int)retaddr & 0xFFFFFFF0) - 32; unsigned short x = 0; - for (; i < ((unsigned int)retaddr & 0xFFFFFFF0 ) + 32 ; - i += 2) { - if ( !(i & 0xF) ) + for (; i < ((unsigned int)retaddr & 0xFFFFFFF0) + 32; i += 2) { + if (!(i & 0xF)) printk(KERN_EMERG "\n" KERN_EMERG "0x%08x: ", i); @@ -579,7 +577,7 @@ void dump_bfin_regs(struct pt_regs *fp, void *retaddr) " The rest of this error" " is meanless\n"); #endif - if ( i == (unsigned int)retaddr ) + if (i == (unsigned int)retaddr) printk("[%04x]", x); else printk(" %04x ", x); @@ -672,8 +670,8 @@ void panic_cplb_error(int cplb_panic, struct pt_regs *fp) break; } - printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n", (void*)bfin_read_DCPLB_FAULT_ADDR()); - printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n", (void*)bfin_read_ICPLB_FAULT_ADDR()); + printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n", (void *)bfin_read_DCPLB_FAULT_ADDR()); + printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n", (void *)bfin_read_ICPLB_FAULT_ADDR()); dump_bfin_regs(fp, (void *)fp->retx); dump_stack(); panic("Unrecoverable event\n"); diff --git a/arch/blackfin/lib/strcmp.c b/arch/blackfin/lib/strcmp.c index 2ad47c4..4eeefd8 100644 --- a/arch/blackfin/lib/strcmp.c +++ b/arch/blackfin/lib/strcmp.c @@ -6,6 +6,5 @@ int strcmp(const char *dest, const char *src) { - return __inline_strcmp(dest, src); + return __inline_strcmp(dest, src); } - diff --git a/arch/blackfin/lib/strcpy.c b/arch/blackfin/lib/strcpy.c index 4dc835a..534589d 100644 --- a/arch/blackfin/lib/strcpy.c +++ b/arch/blackfin/lib/strcpy.c @@ -6,6 +6,5 @@ char *strcpy(char *dest, const char *src) { - return __inline_strcpy(dest, src); + return __inline_strcpy(dest, src); } - diff --git a/arch/blackfin/lib/strncmp.c b/arch/blackfin/lib/strncmp.c index 947bcfe..d791f12 100644 --- a/arch/blackfin/lib/strncmp.c +++ b/arch/blackfin/lib/strncmp.c @@ -6,6 +6,5 @@ int strncmp(const char *cs, const char *ct, size_t count) { - return __inline_strncmp(cs, ct, count); + return __inline_strncmp(cs, ct, count); } - diff --git a/arch/blackfin/lib/strncpy.c b/arch/blackfin/lib/strncpy.c index 77a9b2e..1fecb5c 100644 --- a/arch/blackfin/lib/strncpy.c +++ b/arch/blackfin/lib/strncpy.c @@ -6,6 +6,5 @@ char *strncpy(char *dest, const char *src, size_t n) { - return __inline_strncpy(dest, src, n); + return __inline_strncpy(dest, src, n); } - diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c index edd31ce..4545f36 100644 --- a/arch/blackfin/mach-bf533/boards/cm_bf533.c +++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c @@ -34,7 +34,7 @@ #include #include #include -#include +#include #include /* @@ -51,11 +51,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = { .size = 0x00020000, .offset = 0, .mask_flags = MTD_CAP_ROM - },{ + }, { .name = "kernel", .size = 0xe0000, .offset = 0x20000 - },{ + }, { .name = "file system", .size = 0x700000, .offset = 0x00100000, @@ -98,7 +98,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .platform_data = &bfin_spi_flash_data, .controller_data = &spi_flash_chip_info, .mode = SPI_MODE_3, - },{ + }, { .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ .bus_num = 1, /* Framework bus number */ @@ -145,7 +145,7 @@ static struct resource smc91x_resources[] = { .start = 0x20200300, .end = 0x20200300 + 16, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PF0, .end = IRQ_PF0, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -194,11 +194,11 @@ static struct resource isp1362_hcd_resources[] = { .start = 0x20308000, .end = 0x20308000, .flags = IORESOURCE_MEM, - },{ + }, { .start = 0x20308004, .end = 0x20308004, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PF4, .end = IRQ_PF4, .flags = IORESOURCE_IRQ, diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c index 0b522d9..0000b8f 100644 --- a/arch/blackfin/mach-bf533/boards/ezkit.c +++ b/arch/blackfin/mach-bf533/boards/ezkit.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include /* @@ -61,7 +61,7 @@ static struct resource smc91x_resources[] = { .start = 0x20310300, .end = 0x20310300 + 16, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PF9, .end = IRQ_PF9, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -85,11 +85,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = { .size = 0x00020000, .offset = 0, .mask_flags = MTD_CAP_ROM - },{ + }, { .name = "kernel", .size = 0xe0000, .offset = 0x20000 - },{ + }, { .name = "file system", .size = 0x700000, .offset = 0x00100000, diff --git a/arch/blackfin/mach-bf533/boards/generic_board.c b/arch/blackfin/mach-bf533/boards/generic_board.c index c0f43cc..9bc1f0d 100644 --- a/arch/blackfin/mach-bf533/boards/generic_board.c +++ b/arch/blackfin/mach-bf533/boards/generic_board.c @@ -30,7 +30,7 @@ #include #include -#include +#include /* * Name the Board for the /proc/cpuinfo @@ -53,11 +53,11 @@ static struct resource smc91x_resources[] = { .start = 0x20300300, .end = 0x20300300 + 16, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PROG_INTB, .end = IRQ_PROG_INTB, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - },{ + }, { /* * denotes the flag pin and is used directly if * CONFIG_IRQCHIP_DEMUX_GPIO is defined. diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c index 9a472fe..a9143c4 100644 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ b/arch/blackfin/mach-bf533/boards/stamp.c @@ -37,7 +37,7 @@ #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) #include #endif -#include +#include #include /* @@ -62,7 +62,7 @@ static struct resource smc91x_resources[] = { .start = 0x20300300, .end = 0x20300300 + 16, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PF7, .end = IRQ_PF7, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -83,7 +83,7 @@ static struct resource net2272_bfin_resources[] = { .start = 0x20300000, .end = 0x20300000 + 0x100, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PF10, .end = IRQ_PF10, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -108,11 +108,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = { .size = 0x00020000, .offset = 0, .mask_flags = MTD_CAP_ROM - },{ + }, { .name = "kernel", .size = 0xe0000, .offset = 0x20000 - },{ + }, { .name = "file system", .size = 0x700000, .offset = 0x00100000, @@ -229,19 +229,19 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { #if defined(CONFIG_PBX) { - .modalias = "fxs-spi", - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 1, - .chip_select = 3, - .controller_data= &spi_si3xxx_chip_info, + .modalias = "fxs-spi", + .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 1, + .chip_select = 3, + .controller_data = &spi_si3xxx_chip_info, .mode = SPI_MODE_3, }, { - .modalias = "fxo-spi", - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 1, - .chip_select = 2, - .controller_data= &spi_si3xxx_chip_info, + .modalias = "fxo-spi", + .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 1, + .chip_select = 2, + .controller_data = &spi_si3xxx_chip_info, .mode = SPI_MODE_3, }, #endif diff --git a/arch/blackfin/mach-bf533/cpu.c b/arch/blackfin/mach-bf533/cpu.c index 99547c4..6fd9cfd 100644 --- a/arch/blackfin/mach-bf533/cpu.c +++ b/arch/blackfin/mach-bf533/cpu.c @@ -79,8 +79,7 @@ static int bf533_target(struct cpufreq_policy *policy, int i; struct cpufreq_freqs freqs; - if (cpufreq_frequency_table_target - (policy, bf533_freq_table, target_freq, relation, &index)) + if (cpufreq_frequency_table_target(policy, bf533_freq_table, target_freq, relation, &index)) return -EINVAL; cclk_mhz = bf533_freq_table[index].frequency; vco_mhz = bf533_freq_table[index].index; diff --git a/arch/blackfin/mach-bf533/ints-priority.c b/arch/blackfin/mach-bf533/ints-priority.c index a3e1789..7d79e0f 100644 --- a/arch/blackfin/mach-bf533/ints-priority.c +++ b/arch/blackfin/mach-bf533/ints-priority.c @@ -28,8 +28,8 @@ */ #include +#include #include -#include void program_IAR(void) { diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c index 6a60618..a8f947b 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include /* @@ -53,11 +53,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = { .size = 0x00020000, .offset = 0, .mask_flags = MTD_CAP_ROM - },{ + }, { .name = "kernel", .size = 0xe0000, .offset = 0x20000 - },{ + }, { .name = "file system", .size = 0x700000, .offset = 0x00100000, @@ -202,7 +202,7 @@ static struct resource smc91x_resources[] = { .start = 0x20200300, .end = 0x20200300 + 16, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PF14, .end = IRQ_PF14, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -223,11 +223,11 @@ static struct resource isp1362_hcd_resources[] = { .start = 0x20308000, .end = 0x20308000, .flags = IORESOURCE_MEM, - },{ + }, { .start = 0x20308004, .end = 0x20308004, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PG15, .end = IRQ_PG15, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -262,7 +262,7 @@ static struct resource net2272_bfin_resources[] = { .start = 0x20200000, .end = 0x20200000 + 0x100, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PF7, .end = IRQ_PF7, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -283,7 +283,7 @@ static struct resource bfin_uart_resources[] = { .start = 0xFFC00400, .end = 0xFFC004FF, .flags = IORESOURCE_MEM, - },{ + }, { .start = 0xFFC02000, .end = 0xFFC020FF, .flags = IORESOURCE_MEM, diff --git a/arch/blackfin/mach-bf537/boards/eth_mac.c b/arch/blackfin/mach-bf537/boards/eth_mac.c index e129a08..a725cc8 100644 --- a/arch/blackfin/mach-bf537/boards/eth_mac.c +++ b/arch/blackfin/mach-bf537/boards/eth_mac.c @@ -20,8 +20,7 @@ #include #include -#if defined(CONFIG_GENERIC_BOARD) \ - || defined(CONFIG_BFIN537_STAMP) +#if defined(CONFIG_GENERIC_BOARD) || defined(CONFIG_BFIN537_STAMP) /* * Currently the MAC address is saved in Flash by U-Boot @@ -43,7 +42,7 @@ void get_bf537_ether_addr(char *addr) */ void get_bf537_ether_addr(char *addr) { - printk(KERN_WARNING "%s: No valid Ethernet MAC address found\n",__FILE__); + printk(KERN_WARNING "%s: No valid Ethernet MAC address found\n", __FILE__); } #endif diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c index fd57e74..648d984 100644 --- a/arch/blackfin/mach-bf537/boards/generic_board.c +++ b/arch/blackfin/mach-bf537/boards/generic_board.c @@ -35,9 +35,9 @@ #include #include #include -#include -#include +#include #include +#include /* * Name the Board for the /proc/cpuinfo @@ -54,19 +54,19 @@ static struct resource bfin_pcmcia_cf_resources[] = { .start = 0x20310000, /* IO PORT */ .end = 0x20312000, .flags = IORESOURCE_MEM, - },{ + }, { .start = 0x20311000, /* Attribute Memory */ .end = 0x20311FFF, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PROG_INTA, .end = IRQ_PROG_INTA, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - },{ + }, { .start = IRQ_PF4, .end = IRQ_PF4, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - },{ + }, { .start = 6, /* Card Detect PF6 */ .end = 6, .flags = IORESOURCE_IRQ, @@ -95,11 +95,11 @@ static struct resource smc91x_resources[] = { .start = 0x20300300, .end = 0x20300300 + 16, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PROG_INTB, .end = IRQ_PROG_INTB, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - },{ + }, { /* * denotes the flag pin and is used directly if * CONFIG_IRQCHIP_DEMUX_GPIO is defined. @@ -123,15 +123,15 @@ static struct resource sl811_hcd_resources[] = { .start = 0x20340000, .end = 0x20340000, .flags = IORESOURCE_MEM, - },{ + }, { .start = 0x20340004, .end = 0x20340004, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PROG_INTA, .end = IRQ_PROG_INTA, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - },{ + }, { .start = IRQ_PF0 + CONFIG_USB_SL811_BFIN_GPIO, .end = IRQ_PF0 + CONFIG_USB_SL811_BFIN_GPIO, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -179,15 +179,15 @@ static struct resource isp1362_hcd_resources[] = { .start = 0x20360000, .end = 0x20360000, .flags = IORESOURCE_MEM, - },{ + }, { .start = 0x20360004, .end = 0x20360004, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PROG_INTA, .end = IRQ_PROG_INTA, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - },{ + }, { .start = IRQ_PF0 + CONFIG_USB_ISP1362_BFIN_GPIO, .end = IRQ_PF0 + CONFIG_USB_ISP1362_BFIN_GPIO, .flags = IORESOURCE_IRQ, @@ -228,7 +228,7 @@ static struct resource net2272_bfin_resources[] = { .start = 0x20300000, .end = 0x20300000 + 0x100, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PF7, .end = IRQ_PF7, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -253,11 +253,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = { .size = 0x00020000, .offset = 0, .mask_flags = MTD_CAP_ROM - },{ + }, { .name = "kernel", .size = 0xe0000, .offset = 0x20000 - },{ + }, { .name = "file system", .size = 0x700000, .offset = 0x00100000, @@ -375,7 +375,7 @@ static struct resource bfin_uart_resources[] = { .start = 0xFFC00400, .end = 0xFFC004FF, .flags = IORESOURCE_MEM, - },{ + }, { .start = 0xFFC02000, .end = 0xFFC020FF, .flags = IORESOURCE_MEM, diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c index 8aaf76d..8806f12 100644 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/arch/blackfin/mach-bf537/boards/pnav10.c @@ -37,7 +37,7 @@ #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) #include #endif -#include +#include #include #include @@ -58,15 +58,15 @@ static struct resource bfin_pcmcia_cf_resources[] = { .start = 0x20310000, /* IO PORT */ .end = 0x20312000, .flags = IORESOURCE_MEM, - },{ + }, { .start = 0x20311000, /* Attribute Memory */ .end = 0x20311FFF, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PF4, .end = IRQ_PF4, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - },{ + }, { .start = 6, /* Card Detect PF6 */ .end = 6, .flags = IORESOURCE_IRQ, @@ -95,7 +95,7 @@ static struct resource smc91x_resources[] = { .start = 0x20300300, .end = 0x20300300 + 16, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PF7, .end = IRQ_PF7, @@ -116,11 +116,11 @@ static struct resource sl811_hcd_resources[] = { .start = 0x20340000, .end = 0x20340000, .flags = IORESOURCE_MEM, - },{ + }, { .start = 0x20340004, .end = 0x20340004, .flags = IORESOURCE_MEM, - },{ + }, { .start = CONFIG_USB_SL811_BFIN_IRQ, .end = CONFIG_USB_SL811_BFIN_IRQ, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -167,11 +167,11 @@ static struct resource isp1362_hcd_resources[] = { .start = 0x20360000, .end = 0x20360000, .flags = IORESOURCE_MEM, - },{ + }, { .start = 0x20360004, .end = 0x20360004, .flags = IORESOURCE_MEM, - },{ + }, { .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -212,7 +212,7 @@ static struct resource net2272_bfin_resources[] = { .start = 0x20300000, .end = 0x20300000 + 0x100, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PF7, .end = IRQ_PF7, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -238,11 +238,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = { .size = 0x00020000, .offset = 0, .mask_flags = MTD_CAP_ROM - },{ + }, { .name = "kernel", .size = 0xe0000, .offset = 0x20000 - },{ + }, { .name = "file system", .size = 0x700000, .offset = 0x00100000, @@ -294,16 +294,6 @@ static struct bfin5xx_spi_chip spi_mmc_chip_info = { }; #endif -#if defined(CONFIG_PBX) -static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { - .ctl_reg = 0x4, /* send zero */ - .enable_dma = 0, - .bits_per_word = 8, - .cs_change_per_word = 1, -}; -#endif - - #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) static struct bfin5xx_spi_chip spi_ad7877_chip_info = { .cs_change_per_word = 1, @@ -392,24 +382,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .mode = SPI_MODE_3, }, #endif -#if defined(CONFIG_PBX) - { - .modalias = "fxs-spi", - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 1, - .chip_select = 3, - .controller_data= &spi_si3xxx_chip_info, - .mode = SPI_MODE_3, - }, - { - .modalias = "fxo-spi", - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 1, - .chip_select = 2, - .controller_data= &spi_si3xxx_chip_info, - .mode = SPI_MODE_3, - }, -#endif #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) { .modalias = "ad7877", @@ -451,7 +423,7 @@ static struct resource bfin_uart_resources[] = { .start = 0xFFC00400, .end = 0xFFC004FF, .flags = IORESOURCE_MEM, - },{ + }, { .start = 0xFFC02000, .end = 0xFFC020FF, .flags = IORESOURCE_MEM, diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index 3a29b4d1..c637353 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -37,12 +37,10 @@ #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) #include #endif -#include #include #include -#include #include - +#include #include /* @@ -85,7 +83,7 @@ static struct platform_device *bfin_isp1761_devices[] = { int __init bfin_isp1761_init(void) { - unsigned int num_devices=ARRAY_SIZE(bfin_isp1761_devices); + unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices); printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING); @@ -107,15 +105,15 @@ static struct resource bfin_pcmcia_cf_resources[] = { .start = 0x20310000, /* IO PORT */ .end = 0x20312000, .flags = IORESOURCE_MEM, - },{ + }, { .start = 0x20311000, /* Attribute Memory */ .end = 0x20311FFF, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PF4, .end = IRQ_PF4, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - },{ + }, { .start = 6, /* Card Detect PF6 */ .end = 6, .flags = IORESOURCE_IRQ, @@ -144,7 +142,7 @@ static struct resource smc91x_resources[] = { .start = 0x20300300, .end = 0x20300300 + 16, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PF7, .end = IRQ_PF7, @@ -165,11 +163,11 @@ static struct resource sl811_hcd_resources[] = { .start = 0x20340000, .end = 0x20340000, .flags = IORESOURCE_MEM, - },{ + }, { .start = 0x20340004, .end = 0x20340004, .flags = IORESOURCE_MEM, - },{ + }, { .start = CONFIG_USB_SL811_BFIN_IRQ, .end = CONFIG_USB_SL811_BFIN_IRQ, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -216,11 +214,11 @@ static struct resource isp1362_hcd_resources[] = { .start = 0x20360000, .end = 0x20360000, .flags = IORESOURCE_MEM, - },{ + }, { .start = 0x20360004, .end = 0x20360004, .flags = IORESOURCE_MEM, - },{ + }, { .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -261,7 +259,7 @@ static struct resource net2272_bfin_resources[] = { .start = 0x20300000, .end = 0x20300000 + 0x100, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PF7, .end = IRQ_PF7, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -287,11 +285,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = { .size = 0x00020000, .offset = 0, .mask_flags = MTD_CAP_ROM - },{ + }, { .name = "kernel", .size = 0xe0000, .offset = 0x20000 - },{ + }, { .name = "file system", .size = 0x700000, .offset = 0x00100000, @@ -361,7 +359,6 @@ static struct bfin5xx_spi_chip ad5304_chip_info = { #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) static struct bfin5xx_spi_chip spi_ad7877_chip_info = { -// .cs_change_per_word = 1, .enable_dma = 0, .bits_per_word = 16, }; @@ -449,19 +446,19 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { #endif #if defined(CONFIG_PBX) { - .modalias = "fxs-spi", - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 1, - .chip_select = 3, - .controller_data= &spi_si3xxx_chip_info, + .modalias = "fxs-spi", + .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 1, + .chip_select = 3, + .controller_data = &spi_si3xxx_chip_info, .mode = SPI_MODE_3, }, { - .modalias = "fxo-spi", - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 1, - .chip_select = 2, - .controller_data= &spi_si3xxx_chip_info, + .modalias = "fxo-spi", + .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 1, + .chip_select = 2, + .controller_data = &spi_si3xxx_chip_info, .mode = SPI_MODE_3, }, #endif @@ -516,7 +513,7 @@ static struct resource bfin_uart_resources[] = { .start = 0xFFC00400, .end = 0xFFC004FF, .flags = IORESOURCE_MEM, - },{ + }, { .start = 0xFFC02000, .end = 0xFFC020FF, .flags = IORESOURCE_MEM, diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c index 2dbf3df..a8b915f 100644 --- a/arch/blackfin/mach-bf537/ints-priority.c +++ b/arch/blackfin/mach-bf537/ints-priority.c @@ -28,8 +28,8 @@ */ #include +#include #include -#include void program_IAR(void) { diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 100379c..96ad95f 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -34,7 +34,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/blackfin/mach-bf548/gpio.c b/arch/blackfin/mach-bf548/gpio.c index 854896d..fac7cf3 100644 --- a/arch/blackfin/mach-bf548/gpio.c +++ b/arch/blackfin/mach-bf548/gpio.c @@ -75,7 +75,7 @@ static int __init bfin_gpio_init(void) printk(KERN_INFO "Blackfin GPIO Controller\n"); - for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=GPIO_BANKSIZE) + for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) reserved_map[gpio_bank(i)] = 0; return 0; diff --git a/arch/blackfin/mach-bf548/ints-priority.c b/arch/blackfin/mach-bf548/ints-priority.c index dde450f..cb0ebac 100644 --- a/arch/blackfin/mach-bf548/ints-priority.c +++ b/arch/blackfin/mach-bf548/ints-priority.c @@ -28,8 +28,8 @@ */ #include +#include #include -#include void program_IAR(void) { diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c index 3dc5c04..5b2b544 100644 --- a/arch/blackfin/mach-bf561/boards/cm_bf561.c +++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c @@ -34,7 +34,7 @@ #include #include #include -#include +#include #include /* @@ -52,11 +52,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = { .size = 0x00020000, .offset = 0, .mask_flags = MTD_CAP_ROM - },{ + }, { .name = "kernel", .size = 0xe0000, .offset = 0x20000 - },{ + }, { .name = "file system", .size = 0x700000, .offset = 0x00100000, @@ -186,7 +186,7 @@ static struct resource smc91x_resources[] = { .start = 0x28000300, .end = 0x28000300 + 16, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PF0, .end = IRQ_PF0, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -206,11 +206,11 @@ static struct resource isp1362_hcd_resources[] = { .start = 0x24008000, .end = 0x24008000, .flags = IORESOURCE_MEM, - },{ + }, { .start = 0x24008004, .end = 0x24008004, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PF47, .end = IRQ_PF47, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -241,25 +241,25 @@ static struct platform_device isp1362_hcd_device = { #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) static struct resource bfin_uart_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, }; static struct platform_device bfin_uart_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart_resources), - .resource = bfin_uart_resources, + .name = "bfin-uart", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_uart_resources), + .resource = bfin_uart_resources, }; #endif static struct platform_device *cm_bf561_devices[] __initdata = { #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) - &bfin_uart_device, + &bfin_uart_device, #endif #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index 9720b5c..724191d 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c @@ -30,10 +30,9 @@ #include #include #include -#include -#include -#include #include +#include +#include /* * Name the Board for the /proc/cpuinfo @@ -45,13 +44,13 @@ char *bfin_board_name = "ADDS-BF561-EZKIT"; #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) static struct resource bfin_isp1761_resources[] = { - [0] = { + { .name = "isp1761-regs", .start = ISP1761_BASE + 0x00000000, .end = ISP1761_BASE + 0x000fffff, .flags = IORESOURCE_MEM, }, - [1] = { + { .start = ISP1761_IRQ, .end = ISP1761_IRQ, .flags = IORESOURCE_IRQ, @@ -71,7 +70,7 @@ static struct platform_device *bfin_isp1761_devices[] = { int __init bfin_isp1761_init(void) { - unsigned int num_devices=ARRAY_SIZE(bfin_isp1761_devices); + unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices); printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING); @@ -98,7 +97,7 @@ static struct resource smc91x_resources[] = { .start = 0x2C010300, .end = 0x2C010300 + 16, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PF9, .end = IRQ_PF9, @@ -116,18 +115,18 @@ static struct platform_device smc91x_device = { #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) static struct resource bfin_uart_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, }; static struct platform_device bfin_uart_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart_resources), - .resource = bfin_uart_resources, + .name = "bfin-uart", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_uart_resources), + .resource = bfin_uart_resources, }; #endif @@ -176,7 +175,7 @@ static struct platform_device *ezkit_devices[] __initdata = { &spi_bfin_master_device, #endif #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) - &bfin_uart_device, + &bfin_uart_device, #endif }; diff --git a/arch/blackfin/mach-bf561/boards/generic_board.c b/arch/blackfin/mach-bf561/boards/generic_board.c index 585ecdd..4dfea5d 100644 --- a/arch/blackfin/mach-bf561/boards/generic_board.c +++ b/arch/blackfin/mach-bf561/boards/generic_board.c @@ -30,7 +30,7 @@ #include #include -#include +#include char *bfin_board_name = "UNKNOWN BOARD"; @@ -43,11 +43,11 @@ static struct resource smc91x_resources[] = { .start = 0x2C010300, .end = 0x2C010300 + 16, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PROG_INTB, .end = IRQ_PROG_INTB, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - },{ + }, { /* * denotes the flag pin and is used directly if * CONFIG_IRQCHIP_DEMUX_GPIO is defined. diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c index db308c7..c442eb2 100644 --- a/arch/blackfin/mach-bf561/boards/tepla.c +++ b/arch/blackfin/mach-bf561/boards/tepla.c @@ -14,7 +14,7 @@ #include #include -#include +#include char *bfin_board_name = "Tepla-BF561"; @@ -26,11 +26,11 @@ static struct resource smc91x_resources[] = { .start = 0x2C000300, .end = 0x2C000320, .flags = IORESOURCE_MEM, - },{ + }, { .start = IRQ_PROG_INTB, .end = IRQ_PROG_INTB, .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL, - },{ + }, { /* * denotes the flag pin and is used directly if * CONFIG_IRQCHIP_DEMUX_GPIO is defined. diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c index b28582f..5d1d21b 100644 --- a/arch/blackfin/mach-bf561/coreb.c +++ b/arch/blackfin/mach-bf561/coreb.c @@ -32,8 +32,8 @@ #include #include #include +#include #include -#include #define MODULE_VER "v0.1" @@ -202,7 +202,7 @@ static int coreb_open(struct inode *inode, struct file *file) spin_unlock_irq(&coreb_lock); return 0; - out_busy: + out_busy: spin_unlock_irq(&coreb_lock); return -EBUSY; } @@ -365,19 +365,19 @@ int __init bf561_coreb_init(void) printk(KERN_INFO "BF561 Core B driver %s initialized.\n", MODULE_VER); return 0; - release_dma_src: + release_dma_src: free_dma(CH_MEM_STREAM2_SRC); - release_dma_dest: + release_dma_dest: free_dma(CH_MEM_STREAM2_DEST); - release_data_a_sram: + release_data_a_sram: release_mem_region(0xff400000, 0x8000); - release_data_b_sram: + release_data_b_sram: release_mem_region(0xff500000, 0x8000); - release_instruction_b_sram: + release_instruction_b_sram: release_mem_region(0xff610000, 0x4000); - release_instruction_a_sram: + release_instruction_a_sram: release_mem_region(0xff600000, 0x4000); - exit: + exit: return -ENOMEM; } diff --git a/arch/blackfin/mach-bf561/ints-priority.c b/arch/blackfin/mach-bf561/ints-priority.c index 86e3b0e..09b541b 100644 --- a/arch/blackfin/mach-bf561/ints-priority.c +++ b/arch/blackfin/mach-bf561/ints-priority.c @@ -28,8 +28,8 @@ */ #include +#include #include -#include void program_IAR(void) { diff --git a/arch/blackfin/mach-common/cplbinfo.c b/arch/blackfin/mach-common/cplbinfo.c index caa9623..785ca98 100644 --- a/arch/blackfin/mach-common/cplbinfo.c +++ b/arch/blackfin/mach-common/cplbinfo.c @@ -31,11 +31,10 @@ #include #include #include +#include #include -#include #include - #include #include @@ -92,8 +91,7 @@ static char *cplb_print_entry(char *buf, int type) } else buf += sprintf(buf, "Data CPLB entry:\n"); - buf += sprintf(buf, "Address\t\tData\tSize\tValid\tLocked\tSwapin\ -\tiCount\toCount\n"); + buf += sprintf(buf, "Address\t\tData\tSize\tValid\tLocked\tSwapin\n\tiCount\toCount\n"); while (*p_addr != 0xffffffff) { entry = cplb_find_entry(cplb_addr, cplb_data, *p_addr, *p_data); @@ -144,8 +142,7 @@ static int cplbinfo_proc_output(char *buf) p = buf; - p += sprintf(p, - "------------------ CPLB Information ------------------\n\n"); + p += sprintf(p, "------------------ CPLB Information ------------------\n\n"); if (bfin_read_IMEM_CONTROL() & ENICPLB) p = cplb_print_entry(p, CPLB_I); @@ -191,9 +188,9 @@ static int __init cplbinfo_init(void) { struct proc_dir_entry *entry; - if ((entry = create_proc_entry("cplbinfo", 0, NULL)) == NULL) { + entry = create_proc_entry("cplbinfo", 0, NULL); + if (!entry) return -ENOMEM; - } entry->read_proc = cplbinfo_read_proc; entry->write_proc = cplbinfo_write_proc; diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index 1560327..fa4e633 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -49,8 +49,8 @@ #include +#include #include -#include #include #include /* TIF_NEED_RESCHED */ #include diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c index e6511db..ceb61d9 100644 --- a/arch/blackfin/mach-common/ints-priority-dc.c +++ b/arch/blackfin/mach-common/ints-priority-dc.c @@ -183,7 +183,7 @@ static void bf561_gpio_ack_irq(unsigned int irq) { u16 gpionr = irq - IRQ_PF0; - if(gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { + if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { set_gpio_data(gpionr, 0); SSYNC(); } @@ -193,7 +193,7 @@ static void bf561_gpio_mask_ack_irq(unsigned int irq) { u16 gpionr = irq - IRQ_PF0; - if(gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { + if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { set_gpio_data(gpionr, 0); SSYNC(); } @@ -222,7 +222,7 @@ static unsigned int bf561_gpio_irq_startup(unsigned int irq) if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { ret = gpio_request(gpionr, NULL); - if(ret) + if (ret) return ret; } @@ -262,7 +262,7 @@ static int bf561_gpio_irq_type(unsigned int irq, unsigned int type) if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { ret = gpio_request(gpionr, NULL); - if(ret) + if (ret) return ret; } diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c index 27838da..9f962f9 100644 --- a/arch/blackfin/mach-common/ints-priority-sc.c +++ b/arch/blackfin/mach-common/ints-priority-sc.c @@ -146,8 +146,8 @@ static void bfin_internal_mask_irq(unsigned int irq) ~(1 << (irq - (IRQ_CORETMR + 1)))); #else unsigned mask_bank, mask_bit; - mask_bank = (irq - (IRQ_CORETMR +1))/32; - mask_bit = (irq - (IRQ_CORETMR + 1))%32; + mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; + mask_bit = (irq - (IRQ_CORETMR + 1)) % 32; bfin_write_SIC_IMASK( mask_bank, bfin_read_SIC_IMASK(mask_bank) & \ ~(1 << mask_bit)); #endif @@ -161,7 +161,7 @@ static void bfin_internal_unmask_irq(unsigned int irq) (1 << (irq - (IRQ_CORETMR + 1)))); #else unsigned mask_bank, mask_bit; - mask_bank = (irq - (IRQ_CORETMR +1))/32; + mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; mask_bit = (irq - (IRQ_CORETMR + 1))%32; bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | \ ( 1 << mask_bit)); @@ -439,7 +439,7 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq, { u16 i; - for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=16) { + for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) { int irq = IRQ_PF0 + i; int flag_d = get_gpiop_data(i); int mask = @@ -590,7 +590,7 @@ void do_irq(int vec, struct pt_regs *fp) sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1); sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2); SSYNC(); - for(;; ivg++) { + for (;; ivg++) { if (ivg >= ivg_stop) { atomic_inc(&num_spurious); return; diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index 150ef5d..1772d8d 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c @@ -35,10 +35,10 @@ #include #include #include +#include +#include -#include #include -#include #include #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H diff --git a/arch/blackfin/mm/blackfin_sram.c b/arch/blackfin/mm/blackfin_sram.c index 6810792..16c6169 100644 --- a/arch/blackfin/mm/blackfin_sram.c +++ b/arch/blackfin/mm/blackfin_sram.c @@ -87,7 +87,7 @@ void __init l1sram_init(void) L1_SCRATCH_LENGTH >> 10); memset(&l1_ssram, 0x00, sizeof(l1_ssram)); - l1_ssram[0].paddr = (void*)L1_SCRATCH_START; + l1_ssram[0].paddr = (void *)L1_SCRATCH_START; l1_ssram[0].size = L1_SCRATCH_LENGTH; l1_ssram[0].flag = SRAM_SLT_FREE; @@ -126,7 +126,7 @@ void __init l1_inst_sram_init(void) { #if L1_CODE_LENGTH != 0 memset(&l1_inst_sram, 0x00, sizeof(l1_inst_sram)); - l1_inst_sram[0].paddr = (void*)L1_CODE_START + (_etext_l1 - _stext_l1); + l1_inst_sram[0].paddr = (void *)L1_CODE_START + (_etext_l1 - _stext_l1); l1_inst_sram[0].size = L1_CODE_LENGTH - (_etext_l1 - _stext_l1); l1_inst_sram[0].flag = SRAM_SLT_FREE; diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c index 570356d..2d12449 100644 --- a/arch/blackfin/mm/init.c +++ b/arch/blackfin/mm/init.c @@ -29,8 +29,8 @@ #include #include +#include #include -#include #include #include "blackfin_sram.h" diff --git a/arch/blackfin/oprofile/common.c b/arch/blackfin/oprofile/common.c index 009a170..cb8b8d5 100644 --- a/arch/blackfin/oprofile/common.c +++ b/arch/blackfin/oprofile/common.c @@ -33,12 +33,12 @@ #include #include #include +#include +#include +#include -#include #include #include -#include -#include #include "op_blackfin.h" diff --git a/arch/blackfin/oprofile/op_model_bf533.c b/arch/blackfin/oprofile/op_model_bf533.c index b7a20a0..872dffe 100644 --- a/arch/blackfin/oprofile/op_model_bf533.c +++ b/arch/blackfin/oprofile/op_model_bf533.c @@ -32,12 +32,12 @@ #include #include #include -#include +#include +#include +#include #include #include #include -#include -#include #include "op_blackfin.h" diff --git a/arch/blackfin/oprofile/timer_int.c b/arch/blackfin/oprofile/timer_int.c index 8fba16c..6c6f860 100644 --- a/arch/blackfin/oprofile/timer_int.c +++ b/arch/blackfin/oprofile/timer_int.c @@ -31,8 +31,7 @@ #include #include #include - -#include +#include static void enable_sys_timer0() { -- cgit v0.10.2 From 34e0fc89bdc1e6f50032dc43ed23167f5dbad6da Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 12 Jul 2007 16:17:18 +0800 Subject: Blackfin arch: Enable BF54x PIN/GPIO interrupts Signed-off-bu: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 385c262..e01bfc7 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -71,7 +71,7 @@ config GENERIC_CALIBRATE_DELAY config IRQCHIP_DEMUX_GPIO bool - depends on (BF53x || BF561) + depends on (BF53x || BF561 || BF54x) default y source "init/Kconfig" diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 3309238..f59dcee 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -396,11 +396,11 @@ void __init setup_arch(char **cmdline_p) /* check the size of the l1 area */ l1_length = _etext_l1 - _stext_l1; if (l1_length > L1_CODE_LENGTH) - panic("L1 memory overflow\n"); + panic("L1 code memory overflow\n"); l1_length = _ebss_l1 - _sdata_l1; if (l1_length > L1_DATA_A_LENGTH) - panic("L1 memory overflow\n"); + panic("L1 data memory overflow\n"); #ifdef BF561_FAMILY _bfin_swrst = bfin_read_SICA_SWRST(); diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig index b28625e..e78b03d 100644 --- a/arch/blackfin/mach-bf548/Kconfig +++ b/arch/blackfin/mach-bf548/Kconfig @@ -277,6 +277,40 @@ config IRQ_PINT3 endmenu +comment "Pin Interrupt to Port Assignment" +menu "Assignment" + +config PINTx_REASSIGN + bool "Reprogram PINT Assignment" + default n + help + The interrupt assignment registers controls the pin-to-interrupt + assignment in a byte-wide manner. Each option allows you to select + a set of pins (High/Low Byte) of an specific Port being mapped + to one of the four PIN Interrupts IRQ_PINTx. + + You shouldn't change any of these unless you know exactly what you're doing. + Please consult the Blackfin BF54x Processor Hardware Reference Manual. + +config PINT0_ASSIGN + hex "PINT0_ASSIGN" + depends on PINTx_REASSIGN + default 0x00000101 +config PINT1_ASSIGN + hex "PINT1_ASSIGN" + depends on PINTx_REASSIGN + default 0x01010000 +config PINT2_ASSIGN + hex "PINT2_ASSIGN" + depends on PINTx_REASSIGN + default 0x00000101 +config PINT3_ASSIGN + hex "PINT3_ASSIGN" + depends on PINTx_REASSIGN + default 0x02020303 + +endmenu + endmenu endif diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c index 9f962f9..09373c9 100644 --- a/arch/blackfin/mach-common/ints-priority-sc.c +++ b/arch/blackfin/mach-common/ints-priority-sc.c @@ -88,14 +88,13 @@ static void __init search_IAR(void) for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) { int irqn; - ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = - &ivg_table[irq_pos]; + ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos]; for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { int iar_shift = (irqn & 7) * 4; if (ivg == (0xf & - bfin_read32((unsigned long *) SIC_IAR0 + + bfin_read32((unsigned long *)SIC_IAR0 + (irqn >> 3)) >> iar_shift)) { ivg_table[irq_pos].irqno = IVG7 + irqn; ivg_table[irq_pos].isrflag = 1 << (irqn % 32); @@ -222,7 +221,7 @@ static struct irq_chip bfin_generic_error_irqchip = { }; static void bfin_demux_error_irq(unsigned int int_err_irq, - struct irq_desc *intb_desc) + struct irq_desc *intb_desc) { int irq = 0; @@ -286,8 +285,8 @@ static void bfin_demux_error_irq(unsigned int int_err_irq, } pr_debug("IRQ %d:" - " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n", - irq); + " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n", + irq); } } else printk(KERN_ERR @@ -295,11 +294,10 @@ static void bfin_demux_error_irq(unsigned int int_err_irq, " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n", __FUNCTION__, __FILE__, __LINE__); - } #endif /* BF537_GENERIC_ERROR_INT_DEMUX */ -#ifdef CONFIG_IRQCHIP_DEMUX_GPIO +#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && !defined(CONFIG_BF54x) static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; @@ -377,8 +375,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) } if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | - IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) - { + IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { ret = gpio_request(gpionr, NULL); if (ret) @@ -423,7 +420,6 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) return 0; } - static struct irq_chip bfin_gpio_irqchip = { .ack = bfin_gpio_ack_irq, .mask = bfin_gpio_mask_irq, @@ -435,7 +431,7 @@ static struct irq_chip bfin_gpio_irqchip = { }; static void bfin_demux_gpio_irq(unsigned int intb_irq, - struct irq_desc *intb_desc) + struct irq_desc *intb_desc) { u16 i; @@ -443,8 +439,7 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq, int irq = IRQ_PF0 + i; int flag_d = get_gpiop_data(i); int mask = - flag_d & (gpio_enabled[gpio_bank(i)] & - get_gpiop_maska(i)); + flag_d & (gpio_enabled[gpio_bank(i)] & get_gpiop_maska(i)); while (mask) { if (mask & 1) { @@ -457,6 +452,255 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq, } } +#else /* CONFIG_IRQCHIP_DEMUX_GPIO */ + +#define NR_PINT_SYS_IRQS 4 +#define NR_PINT_BITS 32 +#define NR_PINTS 160 +#define IRQ_NOT_AVAIL 0xFF + +#define PINT_2_BANK(x) ((x) >> 5) +#define PINT_2_BIT(x) ((x) & 0x1F) +#define PINT_BIT(x) (1 << (PINT_2_BIT(x))) + +static unsigned char irq2pint_lut[NR_PINTS]; +static unsigned short pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; + +struct pin_int_t { + unsigned int mask_set; + unsigned int mask_clear; + unsigned int request; + unsigned int assign; + unsigned int edge_set; + unsigned int edge_clear; + unsigned int invert_set; + unsigned int invert_clear; + unsigned int pinstate; + unsigned int latch; +}; + +static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = { + (struct pin_int_t *)PINT0_MASK_SET, + (struct pin_int_t *)PINT1_MASK_SET, + (struct pin_int_t *)PINT2_MASK_SET, + (struct pin_int_t *)PINT3_MASK_SET, +}; + +unsigned short get_irq_base(u8 bank, u8 bmap) +{ + + u16 irq_base; + + if (bank < 2) { /*PA-PB */ + irq_base = IRQ_PA0 + bmap * 16; + } else { /*PC-PJ */ + irq_base = IRQ_PC0 + bmap * 16; + } + + return irq_base; + +} + + /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ +void init_pint_lut(void) +{ + u16 bank, bit, irq_base, bit_pos; + u32 pint_assign; + u8 bmap; + + memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut)); + + for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { + + pint_assign = pint[bank]->assign; + + for (bit = 0; bit < NR_PINT_BITS; bit++) { + + bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF; + + irq_base = get_irq_base(bank, bmap); + + irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0); + bit_pos = bit + bank * NR_PINT_BITS; + + pint2irq_lut[bit_pos] = irq_base; + irq2pint_lut[irq_base - SYS_IRQS] = bit_pos; + + } + + } + +} + +static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; + +static void bfin_gpio_ack_irq(unsigned int irq) +{ + u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; + + pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val); + SSYNC(); +} + +static void bfin_gpio_mask_ack_irq(unsigned int irq) +{ + u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; + + pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val); + pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); + SSYNC(); +} + +static void bfin_gpio_mask_irq(unsigned int irq) +{ + u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; + + pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); + SSYNC(); +} + +static void bfin_gpio_unmask_irq(unsigned int irq) +{ + u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; + + pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val); + pint[PINT_2_BANK(pint_val)]->mask_set = PINT_BIT(pint_val); + SSYNC(); +} + +static unsigned int bfin_gpio_irq_startup(unsigned int irq) +{ + unsigned int ret; + u16 gpionr = irq - IRQ_PA0; + u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; + + if (pint_val == IRQ_NOT_AVAIL) + return -ENODEV; + + if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { + ret = gpio_request(gpionr, NULL); + if (ret) + return ret; + } + + gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); + bfin_gpio_unmask_irq(irq); + + return ret; +} + +static void bfin_gpio_irq_shutdown(unsigned int irq) +{ + bfin_gpio_mask_irq(irq); + gpio_free(irq - IRQ_PA0); + gpio_enabled[gpio_bank(irq - IRQ_PA0)] &= ~gpio_bit(irq - IRQ_PA0); +} + +static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) +{ + + unsigned int ret; + u16 gpionr = irq - IRQ_PA0; + u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; + + if (pint_val == IRQ_NOT_AVAIL) + return -ENODEV; + + if (type == IRQ_TYPE_PROBE) { + /* only probe unenabled GPIO interrupt lines */ + if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)) + return 0; + type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; + } + + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | + IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { + if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { + ret = gpio_request(gpionr, NULL); + if (ret) + return ret; + } + + gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); + } else { + gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); + return 0; + } + + gpio_direction_input(gpionr); + + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { + pint[PINT_2_BANK(pint_val)]->edge_set = PINT_BIT(pint_val); + } else { + pint[PINT_2_BANK(pint_val)]->edge_clear = PINT_BIT(pint_val); + } + + if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) + pint[PINT_2_BANK(pint_val)]->invert_set = PINT_BIT(pint_val); /* low or falling edge denoted by one */ + else + pint[PINT_2_BANK(pint_val)]->invert_set = PINT_BIT(pint_val); /* high or rising edge denoted by zero */ + + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) + pint[PINT_2_BANK(pint_val)]->invert_set = PINT_BIT(pint_val); + else + pint[PINT_2_BANK(pint_val)]->invert_set = PINT_BIT(pint_val); + + SSYNC(); + + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) + set_irq_handler(irq, handle_edge_irq); + else + set_irq_handler(irq, handle_level_irq); + + return 0; +} + +static struct irq_chip bfin_gpio_irqchip = { + .ack = bfin_gpio_ack_irq, + .mask = bfin_gpio_mask_irq, + .mask_ack = bfin_gpio_mask_ack_irq, + .unmask = bfin_gpio_unmask_irq, + .set_type = bfin_gpio_irq_type, + .startup = bfin_gpio_irq_startup, + .shutdown = bfin_gpio_irq_shutdown +}; + +static void bfin_demux_gpio_irq(unsigned int intb_irq, + struct irq_desc *intb_desc) +{ + u8 bank, pint_val; + u32 request, irq; + + switch (intb_irq) { + case IRQ_PINT0: + bank = 0; + break; + case IRQ_PINT2: + bank = 2; + break; + case IRQ_PINT3: + bank = 3; + break; + case IRQ_PINT1: + bank = 1; + break; + } + + pint_val = bank * NR_PINT_BITS; + + request = pint[bank]->request; + + while (request) { + if (request & 1) { + irq = pint2irq_lut[pint_val]; + struct irq_desc *desc = irq_desc + irq; + desc->handle_irq(irq, desc); + } + pint_val++; + request >>= 1; + } + +} #endif /* CONFIG_IRQCHIP_DEMUX_GPIO */ /* @@ -502,7 +746,18 @@ int __init init_arch_irq(void) bfin_write_EVT15(evt_system_call); CSYNC(); - for (irq = 0; irq < SYS_IRQS; irq++) { +#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && defined(CONFIG_BF54x) +#ifdef CONFIG_PINTx_REASSIGN + pint[0]->assign = CONFIG_PINT0_ASSIGN; + pint[1]->assign = CONFIG_PINT1_ASSIGN; + pint[2]->assign = CONFIG_PINT2_ASSIGN; + pint[3]->assign = CONFIG_PINT3_ASSIGN; +#endif + /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ + init_pint_lut(); +#endif + + for (irq = 0; irq <= SYS_IRQS; irq++) { if (irq <= IRQ_CORETMR) set_irq_chip(irq, &bfin_core_irqchip); else @@ -511,20 +766,42 @@ int __init init_arch_irq(void) if (irq != IRQ_GENERIC_ERROR) { #endif + switch (irq) { #ifdef CONFIG_IRQCHIP_DEMUX_GPIO - if ((irq != IRQ_PROG_INTA) /*PORT F & G MASK_A Interrupt*/ -# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) - && (irq != IRQ_MAC_RX) /*PORT H MASK_A Interrupt*/ -# endif - ) { +#ifndef CONFIG_BF54x + case IRQ_PROG_INTA: + set_irq_chained_handler(irq, + bfin_demux_gpio_irq); + break; +#if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) + case IRQ_MAC_RX: + set_irq_chained_handler(irq, + bfin_demux_gpio_irq); + break; #endif - set_irq_handler(irq, handle_simple_irq); -#ifdef CONFIG_IRQCHIP_DEMUX_GPIO - } else { +#else + case IRQ_PINT0: set_irq_chained_handler(irq, bfin_demux_gpio_irq); - } + break; + case IRQ_PINT1: + set_irq_chained_handler(irq, + bfin_demux_gpio_irq); + break; + case IRQ_PINT2: + set_irq_chained_handler(irq, + bfin_demux_gpio_irq); + break; + case IRQ_PINT3: + set_irq_chained_handler(irq, + bfin_demux_gpio_irq); + break; +#endif /*CONFIG_BF54x */ #endif + default: + set_irq_handler(irq, handle_simple_irq); + break; + } #ifdef BF537_GENERIC_ERROR_INT_DEMUX } else { @@ -540,7 +817,11 @@ int __init init_arch_irq(void) #endif #ifdef CONFIG_IRQCHIP_DEMUX_GPIO +#ifndef CONFIG_BF54x for (irq = IRQ_PF0; irq < NR_IRQS; irq++) { +#else + for (irq = IRQ_PA0; irq < NR_IRQS; irq++) { +#endif set_irq_chip(irq, &bfin_gpio_irqchip); /* if configured as edge, then will be changed to do_edge_IRQ */ set_irq_handler(irq, handle_level_irq); @@ -553,8 +834,7 @@ int __init init_arch_irq(void) bfin_write_ILAT(ilat); CSYNC(); - printk(KERN_INFO - "Configuring Blackfin Priority Driven Interrupts\n"); + printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); /* IMASK=xxx is equivalent to STI xx or irq_flags=xx, * local_irq_enable() */ @@ -565,14 +845,13 @@ int __init init_arch_irq(void) /* Enable interrupts IVG7-15 */ irq_flags = irq_flags | IMASK_IVG15 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | - IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | - IMASK_IVGHW; + IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; return 0; } #ifdef CONFIG_DO_IRQ_L1 -void do_irq(int vec, struct pt_regs *fp)__attribute__((l1_text)); +void do_irq(int vec, struct pt_regs *fp) __attribute__((l1_text)); #endif void do_irq(int vec, struct pt_regs *fp) @@ -595,7 +874,7 @@ void do_irq(int vec, struct pt_regs *fp) atomic_inc(&num_spurious); return; } - if (sic_status[(ivg->irqno - IVG7)/32] & ivg->isrflag) + if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) break; } #else diff --git a/include/asm-blackfin/hardirq.h b/include/asm-blackfin/hardirq.h index 0cab0d3..b6b19f1 100644 --- a/include/asm-blackfin/hardirq.h +++ b/include/asm-blackfin/hardirq.h @@ -28,7 +28,11 @@ typedef struct { * SOFTIRQ_MASK: 0x00ff0000 */ +#if NR_IRQS > 256 +#define HARDIRQ_BITS 9 +#else #define HARDIRQ_BITS 8 +#endif #ifdef NR_IRQS # if (1 << HARDIRQ_BITS) < NR_IRQS diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h index 93f5db0..58c87f0 100644 --- a/include/asm-blackfin/mach-bf548/irq.h +++ b/include/asm-blackfin/mach-bf548/irq.h @@ -1,6 +1,6 @@ /* * file: include/asm-blackfin/mach-bf548/irq.h - * based on: include/asm-blackfin/mach-bf537/irq.h + * based on: include/asm-blackfin/mach-bf537/irq.h * author: Roy Huang (roy.huang@analog.com) * * created: @@ -190,7 +190,7 @@ Events (highest priority) EMU 0 #define IRQ_PB12 BFIN_PB_IRQ(12) #define IRQ_PB13 BFIN_PB_IRQ(13) #define IRQ_PB14 BFIN_PB_IRQ(14) -#define IRQ_PB15 BFIN_PB_IRQ(15) +#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */ #define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1) #define IRQ_PC0 BFIN_PC_IRQ(0) @@ -207,8 +207,8 @@ Events (highest priority) EMU 0 #define IRQ_PC11 BFIN_PC_IRQ(11) #define IRQ_PC12 BFIN_PC_IRQ(12) #define IRQ_PC13 BFIN_PC_IRQ(13) -#define IRQ_PC14 BFIN_PC_IRQ(14) -#define IRQ_PC15 BFIN_PC_IRQ(15) +#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */ +#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */ #define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1) #define IRQ_PD0 BFIN_PD_IRQ(0) @@ -246,9 +246,100 @@ Events (highest priority) EMU 0 #define IRQ_PE14 BFIN_PE_IRQ(14) #define IRQ_PE15 BFIN_PE_IRQ(15) +#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1) +#define IRQ_PF0 BFIN_PF_IRQ(0) +#define IRQ_PF1 BFIN_PF_IRQ(1) +#define IRQ_PF2 BFIN_PF_IRQ(2) +#define IRQ_PF3 BFIN_PF_IRQ(3) +#define IRQ_PF4 BFIN_PF_IRQ(4) +#define IRQ_PF5 BFIN_PF_IRQ(5) +#define IRQ_PF6 BFIN_PF_IRQ(6) +#define IRQ_PF7 BFIN_PF_IRQ(7) +#define IRQ_PF8 BFIN_PF_IRQ(8) +#define IRQ_PF9 BFIN_PF_IRQ(9) +#define IRQ_PF10 BFIN_PF_IRQ(10) +#define IRQ_PF11 BFIN_PF_IRQ(11) +#define IRQ_PF12 BFIN_PF_IRQ(12) +#define IRQ_PF13 BFIN_PF_IRQ(13) +#define IRQ_PF14 BFIN_PF_IRQ(14) +#define IRQ_PF15 BFIN_PF_IRQ(15) + +#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1) +#define IRQ_PG0 BFIN_PG_IRQ(0) +#define IRQ_PG1 BFIN_PG_IRQ(1) +#define IRQ_PG2 BFIN_PG_IRQ(2) +#define IRQ_PG3 BFIN_PG_IRQ(3) +#define IRQ_PG4 BFIN_PG_IRQ(4) +#define IRQ_PG5 BFIN_PG_IRQ(5) +#define IRQ_PG6 BFIN_PG_IRQ(6) +#define IRQ_PG7 BFIN_PG_IRQ(7) +#define IRQ_PG8 BFIN_PG_IRQ(8) +#define IRQ_PG9 BFIN_PG_IRQ(9) +#define IRQ_PG10 BFIN_PG_IRQ(10) +#define IRQ_PG11 BFIN_PG_IRQ(11) +#define IRQ_PG12 BFIN_PG_IRQ(12) +#define IRQ_PG13 BFIN_PG_IRQ(13) +#define IRQ_PG14 BFIN_PG_IRQ(14) +#define IRQ_PG15 BFIN_PG_IRQ(15) + +#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1) +#define IRQ_PH0 BFIN_PH_IRQ(0) +#define IRQ_PH1 BFIN_PH_IRQ(1) +#define IRQ_PH2 BFIN_PH_IRQ(2) +#define IRQ_PH3 BFIN_PH_IRQ(3) +#define IRQ_PH4 BFIN_PH_IRQ(4) +#define IRQ_PH5 BFIN_PH_IRQ(5) +#define IRQ_PH6 BFIN_PH_IRQ(6) +#define IRQ_PH7 BFIN_PH_IRQ(7) +#define IRQ_PH8 BFIN_PH_IRQ(8) +#define IRQ_PH9 BFIN_PH_IRQ(9) +#define IRQ_PH10 BFIN_PH_IRQ(10) +#define IRQ_PH11 BFIN_PH_IRQ(11) +#define IRQ_PH12 BFIN_PH_IRQ(12) +#define IRQ_PH13 BFIN_PH_IRQ(13) +#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */ +#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */ + +#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1) +#define IRQ_PI0 BFIN_PI_IRQ(0) +#define IRQ_PI1 BFIN_PI_IRQ(1) +#define IRQ_PI2 BFIN_PI_IRQ(2) +#define IRQ_PI3 BFIN_PI_IRQ(3) +#define IRQ_PI4 BFIN_PI_IRQ(4) +#define IRQ_PI5 BFIN_PI_IRQ(5) +#define IRQ_PI6 BFIN_PI_IRQ(6) +#define IRQ_PI7 BFIN_PI_IRQ(7) +#define IRQ_PI8 BFIN_PI_IRQ(8) +#define IRQ_PI9 BFIN_PI_IRQ(9) +#define IRQ_PI10 BFIN_PI_IRQ(10) +#define IRQ_PI11 BFIN_PI_IRQ(11) +#define IRQ_PI12 BFIN_PI_IRQ(12) +#define IRQ_PI13 BFIN_PI_IRQ(13) +#define IRQ_PI14 BFIN_PI_IRQ(14) +#define IRQ_PI15 BFIN_PI_IRQ(15) + +#if 0 +#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1) +#define IRQ_PJ0 BFIN_PJ_IRQ(0) +#define IRQ_PJ1 BFIN_PJ_IRQ(1) +#define IRQ_PJ2 BFIN_PJ_IRQ(2) +#define IRQ_PJ3 BFIN_PJ_IRQ(3) +#define IRQ_PJ4 BFIN_PJ_IRQ(4) +#define IRQ_PJ5 BFIN_PJ_IRQ(5) +#define IRQ_PJ6 BFIN_PJ_IRQ(6) +#define IRQ_PJ7 BFIN_PJ_IRQ(7) +#define IRQ_PJ8 BFIN_PJ_IRQ(8) +#define IRQ_PJ9 BFIN_PJ_IRQ(9) +#define IRQ_PJ10 BFIN_PJ_IRQ(10) +#define IRQ_PJ11 BFIN_PJ_IRQ(11) +#define IRQ_PJ12 BFIN_PJ_IRQ(12) +#define IRQ_PJ13 BFIN_PJ_IRQ(13) +#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */ +#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */ +#endif #ifdef CONFIG_IRQCHIP_DEMUX_GPIO -#define NR_IRQS (IRQ_PE15+1) +#define NR_IRQS (IRQ_PI15+1) #else #define NR_IRQS (SYS_IRQS+1) #endif -- cgit v0.10.2 From e3f2300036b5e0f60cb64063a9686361b6be8555 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 12 Jul 2007 16:39:29 +0800 Subject: Blackfin arch: Some memory and code optimizations - Fix SYS_IRQS Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c index ceb61d9..7977c2c 100644 --- a/arch/blackfin/mach-common/ints-priority-dc.c +++ b/arch/blackfin/mach-common/ints-priority-dc.c @@ -396,7 +396,7 @@ int __init init_arch_irq(void) bfin_write_EVT15(evt_system_call); CSYNC(); - for (irq = 0; irq < SYS_IRQS; irq++) { + for (irq = 0; irq <= SYS_IRQS; irq++) { if (irq <= IRQ_CORETMR) set_irq_chip(irq, &bf561_core_irqchip); else diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c index 09373c9..c3bb2fb 100644 --- a/arch/blackfin/mach-common/ints-priority-sc.c +++ b/arch/blackfin/mach-common/ints-priority-sc.c @@ -434,6 +434,7 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq, struct irq_desc *intb_desc) { u16 i; + struct irq_desc *desc; for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) { int irq = IRQ_PF0 + i; @@ -443,7 +444,7 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq, while (mask) { if (mask & 1) { - struct irq_desc *desc = irq_desc + irq; + desc = irq_desc + irq; desc->handle_irq(irq, desc); } irq++; @@ -464,7 +465,7 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq, #define PINT_BIT(x) (1 << (PINT_2_BIT(x))) static unsigned char irq2pint_lut[NR_PINTS]; -static unsigned short pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; +static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; struct pin_int_t { unsigned int mask_set; @@ -523,7 +524,7 @@ void init_pint_lut(void) irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0); bit_pos = bit + bank * NR_PINT_BITS; - pint2irq_lut[bit_pos] = irq_base; + pint2irq_lut[bit_pos] = irq_base - SYS_IRQS; irq2pint_lut[irq_base - SYS_IRQS] = bit_pos; } @@ -545,9 +546,11 @@ static void bfin_gpio_ack_irq(unsigned int irq) static void bfin_gpio_mask_ack_irq(unsigned int irq) { u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; + u32 pintbit = PINT_BIT(pint_val); + u8 bank = PINT_2_BANK(pint_val); - pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val); - pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); + pint[bank]->request = pintbit; + pint[bank]->mask_clear = pintbit; SSYNC(); } @@ -562,9 +565,11 @@ static void bfin_gpio_mask_irq(unsigned int irq) static void bfin_gpio_unmask_irq(unsigned int irq) { u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; + u32 pintbit = PINT_BIT(pint_val); + u8 bank = PINT_2_BANK(pint_val); - pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val); - pint[PINT_2_BANK(pint_val)]->mask_set = PINT_BIT(pint_val); + pint[bank]->request = pintbit; + pint[bank]->mask_set = pintbit; SSYNC(); } @@ -602,6 +607,8 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) unsigned int ret; u16 gpionr = irq - IRQ_PA0; u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; + u32 pintbit = PINT_BIT(pint_val); + u8 bank = PINT_2_BANK(pint_val); if (pint_val == IRQ_NOT_AVAIL) return -ENODEV; @@ -630,20 +637,20 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) gpio_direction_input(gpionr); if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { - pint[PINT_2_BANK(pint_val)]->edge_set = PINT_BIT(pint_val); + pint[bank]->edge_set = pintbit; } else { - pint[PINT_2_BANK(pint_val)]->edge_clear = PINT_BIT(pint_val); + pint[bank]->edge_clear = pintbit; } if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) - pint[PINT_2_BANK(pint_val)]->invert_set = PINT_BIT(pint_val); /* low or falling edge denoted by one */ + pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */ else - pint[PINT_2_BANK(pint_val)]->invert_set = PINT_BIT(pint_val); /* high or rising edge denoted by zero */ + pint[bank]->invert_set = pintbit; /* high or rising edge denoted by zero */ if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) - pint[PINT_2_BANK(pint_val)]->invert_set = PINT_BIT(pint_val); + pint[bank]->invert_set = pintbit; else - pint[PINT_2_BANK(pint_val)]->invert_set = PINT_BIT(pint_val); + pint[bank]->invert_set = pintbit; SSYNC(); @@ -670,6 +677,7 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq, { u8 bank, pint_val; u32 request, irq; + struct irq_desc *desc; switch (intb_irq) { case IRQ_PINT0: @@ -684,6 +692,8 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq, case IRQ_PINT1: bank = 1; break; + default: + return; } pint_val = bank * NR_PINT_BITS; @@ -692,8 +702,8 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq, while (request) { if (request & 1) { - irq = pint2irq_lut[pint_val]; - struct irq_desc *desc = irq_desc + irq; + irq = pint2irq_lut[pint_val] + SYS_IRQS; + desc = irq_desc + irq; desc->handle_irq(irq, desc); } pint_val++; @@ -868,7 +878,8 @@ void do_irq(int vec, struct pt_regs *fp) sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0); sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1); sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2); - SSYNC(); + + for (;; ivg++) { if (ivg >= ivg_stop) { atomic_inc(&num_spurious); -- cgit v0.10.2 From cefe658bca9cf1d4af841c45d170ebd0f881889e Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Mon, 2 Jul 2007 11:45:50 +0800 Subject: Blackfin arch: add BF54x missing GPIO access functions Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf548/gpio.c b/arch/blackfin/mach-bf548/gpio.c index fac7cf3..9b1a00a 100644 --- a/arch/blackfin/mach-bf548/gpio.c +++ b/arch/blackfin/mach-bf548/gpio.c @@ -52,6 +52,7 @@ inline int check_gpio(unsigned short gpio) { if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 \ || gpio == GPIO_PH14 || gpio == GPIO_PH15 \ + || gpio == GPIO_PJ14 || gpio == GPIO_PJ15 \ || gpio > MAX_BLACKFIN_GPIOS) return -EINVAL; return 0; @@ -173,3 +174,19 @@ void gpio_direction_output(unsigned short gpio) local_irq_restore(flags); } EXPORT_SYMBOL(gpio_direction_output); + +void gpio_set_value(unsigned short gpio, unsigned short arg) +{ + if (arg) + gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio); + else + gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio); + +} +EXPORT_SYMBOL(gpio_set_value); + +unsigned short gpio_get_value(unsigned short gpio) +{ + return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio))); +} +EXPORT_SYMBOL(gpio_get_value); diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h index bc0cca0..e679703 100644 --- a/include/asm-blackfin/gpio.h +++ b/include/asm-blackfin/gpio.h @@ -234,6 +234,7 @@ * MODIFICATION HISTORY : **************************************************************/ +#ifndef BF548_FAMILY void set_gpio_dir(unsigned short, unsigned short); void set_gpio_inen(unsigned short, unsigned short); void set_gpio_polar(unsigned short, unsigned short); @@ -268,7 +269,6 @@ unsigned short get_gpiop_maska(unsigned short); unsigned short get_gpiop_maskb(unsigned short); unsigned short get_gpiop_data(unsigned short); -#ifndef BF548_FAMILY struct gpio_port_t { unsigned short data; unsigned short dummy1; @@ -363,8 +363,10 @@ void gpio_free(unsigned short); void gpio_set_value(unsigned short gpio, unsigned short arg); unsigned short gpio_get_value(unsigned short gpio); +#ifndef BF548_FAMILY #define gpio_get_value(gpio) get_gpio_data(gpio) #define gpio_set_value(gpio, value) set_gpio_data(gpio, value) +#endif void gpio_direction_input(unsigned short gpio); void gpio_direction_output(unsigned short gpio); diff --git a/include/asm-blackfin/mach-bf548/gpio.h b/include/asm-blackfin/mach-bf548/gpio.h index 4528942..8c5847a 100644 --- a/include/asm-blackfin/mach-bf548/gpio.h +++ b/include/asm-blackfin/mach-bf548/gpio.h @@ -187,8 +187,8 @@ #define GPIO_PJ11 155 #define GPIO_PJ12 156 #define GPIO_PJ13 157 -#define GPIO_PJ14 158 -#define GPIO_PJ15 159 +#define GPIO_PJ14 158 /* N/A */ +#define GPIO_PJ15 159 /* N/A */ #define MAX_BLACKFIN_GPIOS 160 -- cgit v0.10.2 From c9e27ece79f6170fd1cd1a40c5de5d93456606e7 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 12 Jul 2007 11:48:14 +0800 Subject: Blackfin arch: Fix Warning add some defines in BF54x header file Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h index 2381ac5..895ddd4 100644 --- a/include/asm-blackfin/mach-bf548/defBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h @@ -3050,6 +3050,15 @@ #define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */ #define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */ +#define DLEN_8 (0 << 15) /* 000 - 8 bits */ +#define DLEN_10 (1 << 15) /* 001 - 10 bits */ +#define DLEN_12 (2 << 15) /* 010 - 12 bits */ +#define DLEN_14 (3 << 15) /* 011 - 14 bits */ +#define DLEN_16 (4 << 15) /* 100 - 16 bits */ +#define DLEN_18 (5 << 15) /* 101 - 18 bits */ +#define DLEN_24 (6 << 15) /* 110 - 24 bits */ + + /* Bit masks for EPPIx_FS2W_LVB */ #define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */ @@ -3365,32 +3374,32 @@ /* BCODE bit field options (SYSCFG register) */ #define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */ -#define BCODE_FULLBOOT 0x0010 /* always perform full boot */ +#define BCODE_FULLBOOT 0x0010 /* always perform full boot */ #define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */ #define BCODE_NOBOOT 0x0030 /* always perform full boot */ /* CNT_COMMAND bit field options */ - + #define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */ #define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */ #define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */ - + #define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */ #define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */ #define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */ - + #define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */ #define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */ #define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */ - + /* CNT_CONFIG bit field options */ - + #define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */ #define CNTMODE_BINENC 0x0100 /* binary encoder mode */ #define CNTMODE_UDCNT 0x0200 /* up/down counter mode */ #define CNTMODE_DIRCNT 0x0400 /* direction counter mode */ #define CNTMODE_DIRTMR 0x0500 /* direction timer mode */ - + #define BNDMODE_COMP 0x0000 /* boundary compare mode */ #define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */ #define BNDMODE_CAPT 0x2000 /* boundary capture mode */ @@ -3403,7 +3412,7 @@ #define EXT_CLK 0x0003 /* UARTx_LCR bit field options */ - + #define WLS_5 0x0000 /* 5 data bits */ #define WLS_6 0x0001 /* 6 data bits */ #define WLS_7 0x0002 /* 7 data bits */ @@ -3451,7 +3460,7 @@ #define PIQ30 0x40000000 #define PIQ31 0x80000000 -/* PORT A Bit Definitions for the registers +/* PORT A Bit Definitions for the registers PORTA, PORTA_SET, PORTA_CLEAR, PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN, PORTA_FER registers @@ -3474,7 +3483,7 @@ PORTA_FER registers #define PA14 0x4000 #define PA15 0x8000 -/* PORT B Bit Definitions for the registers +/* PORT B Bit Definitions for the registers PORTB, PORTB_SET, PORTB_CLEAR, PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN, PORTB_FER registers @@ -3497,7 +3506,7 @@ PORTB_FER registers #define PB14 0x4000 -/* PORT C Bit Definitions for the registers +/* PORT C Bit Definitions for the registers PORTC, PORTC_SET, PORTC_CLEAR, PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN, PORTC_FER registers @@ -3520,7 +3529,7 @@ PORTC_FER registers #define PC13 0x2000 -/* PORT D Bit Definitions for the registers +/* PORT D Bit Definitions for the registers PORTD, PORTD_SET, PORTD_CLEAR, PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN, PORTD_FER registers @@ -3543,7 +3552,7 @@ PORTD_FER registers #define PD14 0x4000 #define PD15 0x8000 -/* PORT E Bit Definitions for the registers +/* PORT E Bit Definitions for the registers PORTE, PORTE_SET, PORTE_CLEAR, PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN, PORTE_FER registers @@ -3567,7 +3576,7 @@ PORTE_FER registers #define PE14 0x4000 #define PE15 0x8000 -/* PORT F Bit Definitions for the registers +/* PORT F Bit Definitions for the registers PORTF, PORTF_SET, PORTF_CLEAR, PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN, PORTF_FER registers @@ -3591,7 +3600,7 @@ PORTF_FER registers #define PF14 0x4000 #define PF15 0x8000 -/* PORT G Bit Definitions for the registers +/* PORT G Bit Definitions for the registers PORTG, PORTG_SET, PORTG_CLEAR, PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN, PORTG_FER registers @@ -3615,7 +3624,7 @@ PORTG_FER registers #define PG14 0x4000 #define PG15 0x8000 -/* PORT H Bit Definitions for the registers +/* PORT H Bit Definitions for the registers PORTH, PORTH_SET, PORTH_CLEAR, PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN, PORTH_FER registers @@ -3638,7 +3647,7 @@ PORTH_FER registers #define PH13 0x2000 -/* PORT I Bit Definitions for the registers +/* PORT I Bit Definitions for the registers PORTI, PORTI_SET, PORTI_CLEAR, PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN, PORTI_FER registers @@ -3662,7 +3671,7 @@ PORTI_FER registers #define PI14 0x4000 #define PI15 0x8000 -/* PORT J Bit Definitions for the registers +/* PORT J Bit Definitions for the registers PORTJ, PORTJ_SET, PORTJ_CLEAR, PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN, PORTJ_FER registers @@ -3683,7 +3692,7 @@ PORTJ_FER registers #define PJ11 0x0800 #define PJ12 0x1000 #define PJ13 0x2000 - + /* Port Muxing Bit Fields for PORTx_MUX Registers */ @@ -3827,7 +3836,7 @@ PORTJ_FER registers #define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */ #define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */ -#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */ +#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */ #define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */ #define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */ #define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */ @@ -3836,27 +3845,27 @@ PORTJ_FER registers #define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */ #define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */ -#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */ -#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */ -#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */ -#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */ -#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */ -#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */ -#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */ -#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */ - -#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */ -#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */ -#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */ -#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */ -#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */ -#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */ -#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */ -#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */ +#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */ +#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */ +#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */ +#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */ +#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */ +#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */ +#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */ +#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */ + +#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */ +#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */ +#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */ +#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */ +#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */ +#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */ +#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */ +#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */ /* for legacy compatibility */ - + #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ #define W1LMAX_MAX W1LMAX_MIN #define EBIU_AMCBCTL0 EBIU_AMBCTL0 -- cgit v0.10.2 From 9401e618c8f70920f34893946239e24d40a3519a Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 12 Jul 2007 11:50:43 +0800 Subject: Blackfin arch: scrub dead code we converted to using a system call for userspace spinlocks rather than a dedicated exception long ago Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index 114277b..3909f5b 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -193,15 +193,14 @@ asmlinkage void trap_c(struct pt_regs *fp) #else /* 0x02 - User Defined, Caught by default */ #endif - /* 0x03 - Atomic test and set */ + /* 0x03 - User Defined, userspace stack overflow */ case VEC_EXCPT03: info.si_code = SEGV_STACKFLOW; sig = SIGSEGV; printk(KERN_EMERG EXC_0x03); CHK_DEBUGGER_TRAP(); break; - /* 0x04 - spinlock - handled by _ex_spinlock, - getting here is an error */ + /* 0x04 - User Defined, Caught by default */ /* 0x05 - User Defined, Caught by default */ /* 0x06 - User Defined, Caught by default */ /* 0x07 - User Defined, Caught by default */ diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index fa4e633..d61bba9 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -97,17 +97,6 @@ ENTRY(_ex_icplb) rtx; ENDPROC(_ex_icplb) -ENTRY(_ex_spinlock) - /* Transform this into a syscall - twiddle the syscall vector. */ - p5.l = lo(EVT15); - p5.h = hi(EVT15); - r7.l = _spinlock_bh; - r7.h = _spinlock_bh; - [p5] = r7; - csync; - /* Fall through. */ -ENDPROC(_ex_spinlock) - ENTRY(_ex_syscall) DEBUG_START_HWTRACE(p5, r7) (R7:6,P5:4) = [sp++]; @@ -117,26 +106,6 @@ ENTRY(_ex_syscall) rtx ENDPROC(_ex_syscall) -ENTRY(_spinlock_bh) - SAVE_ALL_SYS - /* To end up here, vector 15 was changed - so we have to change it - * back. - */ - p0.l = lo(EVT15); - p0.h = hi(EVT15); - p1.l = _evt_system_call; - p1.h = _evt_system_call; - [p0] = p1; - csync; - r0 = [sp + PT_R0]; - sp += -12; - call _sys_bfin_spinlock; - sp += 12; - [SP + PT_R0] = R0; - RESTORE_ALL_SYS - rti; -ENDPROC(_spinlock_bh) - ENTRY(_ex_soft_bp) r7 = retx; r7 += -2; @@ -775,14 +744,14 @@ ENDPROC(_init_exception_buff) ALIGN _extable: /* entry for each EXCAUSE[5:0] - * This table bmust be in sync with the table in ./kernel/traps.c + * This table must be in sync with the table in ./kernel/traps.c * EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined */ .long _ex_syscall; /* 0x00 - User Defined - Linux Syscall */ .long _ex_soft_bp /* 0x01 - User Defined - Software breakpoint */ .long _ex_trap_c /* 0x02 - User Defined */ - .long _ex_trap_c /* 0x03 - User Defined - Atomic test and set service */ - .long _ex_spinlock /* 0x04 - User Defined */ + .long _ex_trap_c /* 0x03 - User Defined - userspace stack overflow */ + .long _ex_trap_c /* 0x04 - User Defined */ .long _ex_trap_c /* 0x05 - User Defined */ .long _ex_trap_c /* 0x06 - User Defined */ .long _ex_trap_c /* 0x07 - User Defined */ -- cgit v0.10.2 From 9be343c5bcd1cf285c2150f363bc9dd7aab8b7fb Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 12 Jul 2007 11:58:44 +0800 Subject: Blackfin arch: There is no CDPRIO Bit in the EBIU_AMGCTL Register of BF54x arch However there are similar things in the EBIU_DDRQUE Register Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index e01bfc7..6d23bcc 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -729,6 +729,7 @@ config C_AMCKEN config C_CDPRIO bool "DMA has priority over core for ext. accesses" + depends on !BF54x default n config C_B0PEN diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h index 163c79e..9498313 100644 --- a/include/asm-blackfin/mach-bf548/bf548.h +++ b/include/asm-blackfin/mach-bf548/bf548.h @@ -32,16 +32,6 @@ #define SUPPORTED_REVID 0 -/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */ - -#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */ -#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORTx_STAT */ -#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */ -#define UART_ERR_MASK_STAT1 (0x4) /* UARTx_IIR */ -#define UART_ERR_MASK_STAT0 (0x2) /* UARTx_IIR */ -#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | \ - RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */ - #define OFFSET_(x) ((x) & 0x0000FFFF) /*some misc defines*/ @@ -113,13 +103,8 @@ #else #define V_AMCKEN 0x0 #endif -#ifdef CONFIG_C_CDPRIO -#define V_CDPRIO 0x100 -#else -#define V_CDPRIO 0x0 -#endif -#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) +#define AMGCTLVAL (V_AMBEN | V_AMCKEN) #define MAX_VC 650000000 #define MIN_VC 50000000 -- cgit v0.10.2 From f40d24d909ad99c802a6813ff32b6feb20ab8c71 Mon Sep 17 00:00:00 2001 From: Alex Landau Date: Thu, 12 Jul 2007 12:11:48 +0800 Subject: Blackfin arch: Port the dm9000 driver to Blackfin by using the correct low-level io routines Signed-off-by: Alex Landau Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index c637353..9c43d77 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -157,6 +157,28 @@ static struct platform_device smc91x_device = { }; #endif +#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) +static struct resource dm9000_resources[] = { + [0] = { + .start = 0x203FB800, + .end = 0x203FB800 + 8, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PF9, + .end = IRQ_PF9, + .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE), + }, +}; + +static struct platform_device dm9000_device = { + .name = "dm9000", + .id = -1, + .num_resources = ARRAY_SIZE(dm9000_resources), + .resource = dm9000_resources, +}; +#endif + #if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE) static struct resource sl811_hcd_resources[] = { { @@ -568,6 +590,10 @@ static struct platform_device *stamp_devices[] __initdata = { &smc91x_device, #endif +#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) + &dm9000_device, +#endif + #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) &bfin_mac_device, #endif diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index b941c74..80572e2 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -877,7 +877,7 @@ config NET_NETX config DM9000 tristate "DM9000 support" - depends on ARM || MIPS + depends on ARM || BLACKFIN || MIPS select CRC32 select MII ---help--- diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c index 264fa0e..c3de81b 100644 --- a/drivers/net/dm9000.c +++ b/drivers/net/dm9000.c @@ -104,6 +104,18 @@ #define PRINTK(args...) printk(KERN_DEBUG args) #endif +#ifdef CONFIG_BLACKFIN +#define readsb insb +#define readsw insw +#define readsl insl +#define writesb outsb +#define writesw outsw +#define writesl outsl +#define DM9000_IRQ_FLAGS (IRQF_SHARED | IRQF_TRIGGER_HIGH) +#else +#define DM9000_IRQ_FLAGS IRQF_SHARED +#endif + /* * Transmit timeout, default 5 seconds. */ @@ -431,6 +443,9 @@ dm9000_probe(struct platform_device *pdev) db->io_addr = (void __iomem *)base; db->io_data = (void __iomem *)(base + 4); + /* ensure at least we have a default set of IO routines */ + dm9000_set_io(db, 2); + } else { db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); @@ -614,7 +629,7 @@ dm9000_open(struct net_device *dev) PRINTK2("entering dm9000_open\n"); - if (request_irq(dev->irq, &dm9000_interrupt, IRQF_SHARED, dev->name, dev)) + if (request_irq(dev->irq, &dm9000_interrupt, DM9000_IRQ_FLAGS, dev->name, dev)) return -EAGAIN; /* Initialize DM9000 board */ -- cgit v0.10.2 From 157cc5aad94fb7025c41a60788c1bfb5299010aa Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 12 Jul 2007 16:20:21 +0800 Subject: Blackfin arch: Disable CACHELINE_ALIGNED_L1 for BF54x by default Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 6d23bcc..2372b03 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -540,7 +540,8 @@ config IP_CHECKSUM_L1 config CACHELINE_ALIGNED_L1 bool "Locate cacheline_aligned data to L1 Data Memory" - default y + default y if !BF54x + default n if BF54x depends on !BF531 help If enabled cacheline_anligned data is linked -- cgit v0.10.2 From b07af760c9bd8e87c3aa9275298566379ec4e9c1 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Thu, 12 Jul 2007 12:18:08 +0800 Subject: Blackfin arch: fix bug set dma_address properly in dma_map_sg Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/dma-mapping.c b/arch/blackfin/kernel/dma-mapping.c index bda57ec..ea48d5b1 100644 --- a/arch/blackfin/kernel/dma-mapping.c +++ b/arch/blackfin/kernel/dma-mapping.c @@ -159,10 +159,13 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, BUG_ON(direction == DMA_NONE); - for (i = 0; i < nents; i++) - invalidate_dcache_range(sg_dma_address(&sg[i]), - sg_dma_address(&sg[i]) + - sg_dma_len(&sg[i])); + for (i = 0; i < nents; i++, sg++) { + sg->dma_address = page_address(sg->page) + sg->offset; + + invalidate_dcache_range(sg_dma_address(sg), + sg_dma_address(sg) + + sg_dma_len(sg)); + } return nents; } -- cgit v0.10.2 From 520473b0775ce046d179afa686fb3222884c389d Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 12 Jul 2007 12:20:20 +0800 Subject: Blackfin arch: use PAGE_SIZE when doing aligns rather than hardcoded values Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S index 1ef1e36..d06f860 100644 --- a/arch/blackfin/kernel/vmlinux.lds.S +++ b/arch/blackfin/kernel/vmlinux.lds.S @@ -31,6 +31,7 @@ #include #include +#include OUTPUT_FORMAT("elf32-bfin") ENTRY(__start) @@ -63,8 +64,8 @@ SECTIONS .data : { + . = ALIGN(PAGE_SIZE); __sdata = .; - . = ALIGN(0x2000); *(.data.init_task) DATA_DATA CONSTRUCTORS @@ -72,14 +73,14 @@ SECTIONS . = ALIGN(32); *(.data.cacheline_aligned) - . = ALIGN(0x2000); + . = ALIGN(PAGE_SIZE); __edata = .; } + . = ALIGN(PAGE_SIZE); ___init_begin = .; .init : { - . = ALIGN(4096); __sinittext = .; *(.init.text) __einittext = .; @@ -152,9 +153,10 @@ SECTIONS __ebss_b_l1 = .; } - ___init_end = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1); + . = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1); + ___init_end = ALIGN(PAGE_SIZE); - .bss LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1) : + .bss ___init_end : { . = ALIGN(4); ___bss_start = .; diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h index ffad947..8bc8671 100644 --- a/include/asm-blackfin/page.h +++ b/include/asm-blackfin/page.h @@ -4,7 +4,11 @@ /* PAGE_SHIFT determines the page size */ #define PAGE_SHIFT 12 +#ifdef __ASSEMBLY__ +#define PAGE_SIZE (1 << PAGE_SHIFT) +#else #define PAGE_SIZE (1UL << PAGE_SHIFT) +#endif #define PAGE_MASK (~(PAGE_SIZE-1)) #ifdef __KERNEL__ -- cgit v0.10.2 From 5610db61cf2945a5e74667e952f2792c96ba53a1 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 12 Jul 2007 12:32:52 +0800 Subject: Blackfin arch: Add Support for Peripheral PortMux and resouce allocation Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf548/gpio.c b/arch/blackfin/mach-bf548/gpio.c index 9b1a00a..0da5f00 100644 --- a/arch/blackfin/mach-bf548/gpio.c +++ b/arch/blackfin/mach-bf548/gpio.c @@ -31,38 +31,64 @@ #include #include #include +#include #include static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = { - (struct gpio_port_t *) PORTA_FER, - (struct gpio_port_t *) PORTB_FER, - (struct gpio_port_t *) PORTC_FER, - (struct gpio_port_t *) PORTD_FER, - (struct gpio_port_t *) PORTE_FER, - (struct gpio_port_t *) PORTF_FER, - (struct gpio_port_t *) PORTG_FER, - (struct gpio_port_t *) PORTH_FER, - (struct gpio_port_t *) PORTI_FER, - (struct gpio_port_t *) PORTJ_FER, + (struct gpio_port_t *)PORTA_FER, + (struct gpio_port_t *)PORTB_FER, + (struct gpio_port_t *)PORTC_FER, + (struct gpio_port_t *)PORTD_FER, + (struct gpio_port_t *)PORTE_FER, + (struct gpio_port_t *)PORTF_FER, + (struct gpio_port_t *)PORTG_FER, + (struct gpio_port_t *)PORTH_FER, + (struct gpio_port_t *)PORTI_FER, + (struct gpio_port_t *)PORTJ_FER, }; -static unsigned short reserved_map[gpio_bank(MAX_BLACKFIN_GPIOS)]; +static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)]; +static unsigned short reserved_peri_map[gpio_bank(MAX_BLACKFIN_GPIOS)]; inline int check_gpio(unsigned short gpio) { - if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 \ - || gpio == GPIO_PH14 || gpio == GPIO_PH15 \ - || gpio == GPIO_PJ14 || gpio == GPIO_PJ15 \ - || gpio > MAX_BLACKFIN_GPIOS) + if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 + || gpio == GPIO_PH14 || gpio == GPIO_PH15 + || gpio == GPIO_PJ14 || gpio == GPIO_PJ15 + || gpio > MAX_BLACKFIN_GPIOS) return -EINVAL; return 0; } +inline void portmux_setup(unsigned short portno, unsigned short function) +{ + u32 pmux; + + pmux = gpio_array[gpio_bank(portno)]->port_mux; + + pmux &= ~(0x3 << (2 * gpio_sub_n(portno))); + pmux |= (function & 0x3) << (2 * gpio_sub_n(portno)); + + gpio_array[gpio_bank(portno)]->port_mux = pmux; + +} + +inline u16 get_portmux(unsigned short portno) +{ + u32 pmux; + + pmux = gpio_array[gpio_bank(portno)]->port_mux; + + return (pmux >> (2 * gpio_sub_n(portno)) & 0x3); + +} + static void port_setup(unsigned short gpio, unsigned short usage) { if (usage == GPIO_USAGE) { if (gpio_array[gpio_bank(gpio)]->port_fer & gpio_bit(gpio)) - printk(KERN_WARNING "bfin-gpio: Possible Conflict with Peripheral " + printk(KERN_WARNING + "bfin-gpio: Possible Conflict with Peripheral " "usage and GPIO %d detected!\n", gpio); gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio); } else @@ -72,18 +98,116 @@ static void port_setup(unsigned short gpio, unsigned short usage) static int __init bfin_gpio_init(void) { - int i; - printk(KERN_INFO "Blackfin GPIO Controller\n"); - for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) - reserved_map[gpio_bank(i)] = 0; - return 0; } arch_initcall(bfin_gpio_init); +int peripheral_request(unsigned short per, const char *label) +{ + unsigned long flags; + unsigned short ident = P_IDENT(per); + + if (!(per & P_DEFINED)) + return -ENODEV; + + if (check_gpio(ident) < 0) + return -EINVAL; + + local_irq_save(flags); + + if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) { + printk(KERN_ERR + "%s: Peripheral %d is already reserved as GPIO!\n", + __FUNCTION__, per); + dump_stack(); + local_irq_restore(flags); + return -EBUSY; + } + + if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) { + + u16 funct = get_portmux(ident); + + if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) { + printk(KERN_ERR + "%s: Peripheral %d is already reserved!\n", + __FUNCTION__, per); + dump_stack(); + local_irq_restore(flags); + return -EBUSY; + } + } + + reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident); + + portmux_setup(ident, P_FUNCT2MUX(per)); + port_setup(ident, PERIPHERAL_USAGE); + + local_irq_restore(flags); + + return 0; +} +EXPORT_SYMBOL(peripheral_request); + +int peripheral_request_list(unsigned short per[], const char *label) +{ + + u16 cnt; + int ret; + + for (cnt = 0; per[cnt] != 0; cnt++) { + ret = peripheral_request(per[cnt], label); + if (ret < 0) + return ret; + } + + return 0; +} +EXPORT_SYMBOL(peripheral_request_list); + +void peripheral_free(unsigned short per) +{ + unsigned long flags; + unsigned short ident = P_IDENT(per); + + if (!(per & P_DEFINED)) + return; + + if (check_gpio(ident) < 0) + return; + + local_irq_save(flags); + + if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) { + printk(KERN_ERR "bfin-gpio: Peripheral %d wasn't reserved!\n", per); + dump_stack(); + local_irq_restore(flags); + return; + } + + if (!(per & P_MAYSHARE)) { + port_setup(ident, GPIO_USAGE); + } + + reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident); + + local_irq_restore(flags); +} +EXPORT_SYMBOL(peripheral_free); + +void peripheral_free_list(unsigned short per[]) +{ + u16 cnt; + + for (cnt = 0; per[cnt] != 0; cnt++) { + peripheral_free(per[cnt]); + } + +} +EXPORT_SYMBOL(peripheral_free_list); /*********************************************************** * @@ -109,13 +233,22 @@ int gpio_request(unsigned short gpio, const char *label) local_irq_save(flags); - if (unlikely(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio))) { + if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved!\n", gpio); dump_stack(); local_irq_restore(flags); return -EBUSY; } - reserved_map[gpio_bank(gpio)] |= gpio_bit(gpio); + + if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) { + printk(KERN_ERR + "bfin-gpio: GPIO %d is already reserved as Peripheral!\n", gpio); + dump_stack(); + local_irq_restore(flags); + return -EBUSY; + } + + reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio); local_irq_restore(flags); @@ -125,7 +258,6 @@ int gpio_request(unsigned short gpio, const char *label) } EXPORT_SYMBOL(gpio_request); - void gpio_free(unsigned short gpio) { unsigned long flags; @@ -135,25 +267,24 @@ void gpio_free(unsigned short gpio) local_irq_save(flags); - if (unlikely(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { + if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio); dump_stack(); local_irq_restore(flags); return; } - reserved_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); + reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); local_irq_restore(flags); } EXPORT_SYMBOL(gpio_free); - void gpio_direction_input(unsigned short gpio) { unsigned long flags; - BUG_ON(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio))); + BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); local_irq_save(flags); gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio); @@ -166,7 +297,7 @@ void gpio_direction_output(unsigned short gpio) { unsigned long flags; - BUG_ON(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio))); + BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); local_irq_save(flags); gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio); diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h index e679703..7480cfa 100644 --- a/include/asm-blackfin/gpio.h +++ b/include/asm-blackfin/gpio.h @@ -210,6 +210,56 @@ #ifdef BF561_FAMILY #define MAX_BLACKFIN_GPIOS 48 + +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 +#define GPIO_PF16 16 +#define GPIO_PF17 17 +#define GPIO_PF18 18 +#define GPIO_PF19 19 +#define GPIO_PF20 20 +#define GPIO_PF21 21 +#define GPIO_PF22 22 +#define GPIO_PF23 23 +#define GPIO_PF24 24 +#define GPIO_PF25 25 +#define GPIO_PF26 26 +#define GPIO_PF27 27 +#define GPIO_PF28 28 +#define GPIO_PF29 29 +#define GPIO_PF30 30 +#define GPIO_PF31 31 +#define GPIO_PF32 32 +#define GPIO_PF33 33 +#define GPIO_PF34 34 +#define GPIO_PF35 35 +#define GPIO_PF36 36 +#define GPIO_PF37 37 +#define GPIO_PF38 38 +#define GPIO_PF39 39 +#define GPIO_PF40 40 +#define GPIO_PF41 41 +#define GPIO_PF42 42 +#define GPIO_PF43 43 +#define GPIO_PF44 44 +#define GPIO_PF45 45 +#define GPIO_PF46 46 +#define GPIO_PF47 47 + #define PORT_FIO0 GPIO_0 #define PORT_FIO1 GPIO_16 #define PORT_FIO2 GPIO_32 diff --git a/include/asm-blackfin/mach-bf533/portmux.h b/include/asm-blackfin/mach-bf533/portmux.h new file mode 100644 index 0000000..b88d7a0 --- /dev/null +++ b/include/asm-blackfin/mach-bf533/portmux.h @@ -0,0 +1,65 @@ +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define P_PPI0_CLK (P_DONTCARE) +#define P_PPI0_FS1 (P_DONTCARE) +#define P_PPI0_FS2 (P_DONTCARE) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11)) +#define P_PPI0_D0 (P_DONTCARE) +#define P_PPI0_D1 (P_DONTCARE) +#define P_PPI0_D2 (P_DONTCARE) +#define P_PPI0_D3 (P_DONTCARE) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12)) + +#define P_SPORT1_TSCLK (P_DONTCARE) +#define P_SPORT1_RSCLK (P_DONTCARE) +#define P_SPORT0_TSCLK (P_DONTCARE) +#define P_SPORT0_RSCLK (P_DONTCARE) +#define P_UART0_RX (P_DONTCARE) +#define P_UART0_TX (P_DONTCARE) +#define P_SPORT1_DRSEC (P_DONTCARE) +#define P_SPORT1_RFS (P_DONTCARE) +#define P_SPORT1_DTPRI (P_DONTCARE) +#define P_SPORT1_DTSEC (P_DONTCARE) +#define P_SPORT1_TFS (P_DONTCARE) +#define P_SPORT1_DRPRI (P_DONTCARE) +#define P_SPORT0_DRSEC (P_DONTCARE) +#define P_SPORT0_RFS (P_DONTCARE) +#define P_SPORT0_DTPRI (P_DONTCARE) +#define P_SPORT0_DTSEC (P_DONTCARE) +#define P_SPORT0_TFS (P_DONTCARE) +#define P_SPORT0_DRPRI (P_DONTCARE) + +#define P_SPI0_MOSI (P_DONTCARE) +#define P_SPI0_MIS0 (P_DONTCARE) +#define P_SPI0_SCK (P_DONTCARE) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) + +#define P_TMR2 (P_DONTCARE) +#define P_TMR1 (P_DONTCARE) +#define P_TMR0 (P_DONTCARE) +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1)) + + + + + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h new file mode 100644 index 0000000..23e13c5 --- /dev/null +++ b/include/asm-blackfin/mach-bf537/portmux.h @@ -0,0 +1,109 @@ +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) +#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) +#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) +#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) +#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) +#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) +#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) +#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) +#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) +#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) + +#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) +#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) +#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) +#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) +#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) + +#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) +#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) +#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) +#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) +#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) +#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) +#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) +#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) +#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0)) +#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0)) +#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0)) +#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0)) +#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0)) +#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0)) +#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0)) +#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0)) +#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1)) +#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) +#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1)) + +#define PORT_PJ0 (GPIO_PH15 + 1) +#define PORT_PJ1 (GPIO_PH15 + 2) +#define PORT_PJ2 (GPIO_PH15 + 3) +#define PORT_PJ3 (GPIO_PH15 + 4) +#define PORT_PJ4 (GPIO_PH15 + 5) +#define PORT_PJ5 (GPIO_PH15 + 6) +#define PORT_PJ6 (GPIO_PH15 + 7) +#define PORT_PJ7 (GPIO_PH15 + 8) +#define PORT_PJ8 (GPIO_PH15 + 9) +#define PORT_PJ9 (GPIO_PH15 + 10) +#define PORT_PJ10 (GPIO_PH15 + 11) +#define PORT_PJ11 (GPIO_PH15 + 12) + +#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0)) +#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0)) +#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0)) +#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0)) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0)) +#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0)) +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1)) +#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1)) +#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1)) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2)) + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h new file mode 100644 index 0000000..b382deb --- /dev/null +++ b/include/asm-blackfin/mach-bf548/portmux.h @@ -0,0 +1,270 @@ +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) +#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) +#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) +#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0)) +#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0)) +#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0)) +#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0)) +#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0)) +#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0)) +#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0)) +#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0)) +#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0)) +#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0)) +#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0)) +#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0)) +#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1)) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1)) + +#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0)) +#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0)) +#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0)) +#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0)) +#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0)) +#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0)) +#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0)) +#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0)) +#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0)) +#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0)) +#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0)) +#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0)) +#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0)) +#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0)) +#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1)) + +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0)) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0)) +#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0)) +#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0)) +#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0)) +#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0)) +#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0)) +#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0)) +#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0)) +#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1)) +#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1)) + +#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0)) +#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0)) +#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0)) +#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0)) +#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0)) +#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0)) +#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0)) +#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0)) +#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0)) +#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0)) +#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0)) +#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0)) +#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0)) +#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0)) +#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0)) +#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0)) + +#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1)) +#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1)) +#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1)) +#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1)) +#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1)) +#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1)) +#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1)) +#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1)) +#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1)) +#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1)) +#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1)) +#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1)) +#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1)) +#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1)) +#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1)) +#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2)) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2)) +#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2)) +#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2)) +#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2)) +#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2)) +#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2)) +#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2)) +#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2)) +#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2)) +#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2)) +#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3)) +#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3)) +#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3)) +#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3)) +#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3)) +#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3)) +#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3)) +#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3)) +#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3)) +#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3)) +#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3)) +#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3)) +#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3)) +#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3)) + +#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0)) +#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0)) +#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0)) +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0)) +#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0)) +#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0)) +#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0)) +#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0)) +#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0)) +#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0)) +#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0)) +#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1)) +#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1)) +#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1)) +#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1)) +#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1)) +#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1)) +#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1)) +#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1)) + +#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) +#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) +#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) +#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) +#define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) +#define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) +#define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) +#define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) +#define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) +#define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) +#define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) +#define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) +#define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) +#define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) +#define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) +#define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) +#define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) +#define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) +#define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) +#define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) + +#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) +#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) +#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) +#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) +#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) +#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) +#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) +#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) +#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) +#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) +#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) +#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) +#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) +#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) +#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) +#define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1)) +#define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) +#define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) +#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) +#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) +#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) +#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) +#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2)) +#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) +#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2)) +#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3)) + +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) +#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) +#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) +#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) +#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) +#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) +#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) +#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0)) +#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0)) +#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0)) +#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0)) +#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0)) +#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0)) +#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) +#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1)) +#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1)) +#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1)) +#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1)) +#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1)) +#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2)) +#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2)) +#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2)) + +#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0)) +#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0)) +#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0)) +#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0)) +#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0)) +#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0)) +#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0)) +#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0)) +#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0)) +#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0)) +#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0)) +#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0)) +#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0)) +#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0)) +#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0)) +#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0)) +#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1)) + +#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0)) +#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0)) +#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0)) +#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0)) +#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0)) +#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0)) +#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0)) +#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0)) +#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0)) +#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0)) +#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0)) +#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0)) +#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0)) +#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0)) + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h new file mode 100644 index 0000000..10d11d5 --- /dev/null +++ b/include/asm-blackfin/mach-bf561/portmux.h @@ -0,0 +1,87 @@ +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define P_PPI0_CLK (P_DONTCARE) +#define P_PPI0_FS1 (P_DONTCARE) +#define P_PPI0_FS2 (P_DONTCARE) +#define P_PPI0_FS3 (P_DONTCARE) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40)) +#define P_PPI0_D0 (P_DONTCARE) +#define P_PPI0_D1 (P_DONTCARE) +#define P_PPI0_D2 (P_DONTCARE) +#define P_PPI0_D3 (P_DONTCARE) +#define P_PPI0_D4 (P_DONTCARE) +#define P_PPI0_D5 (P_DONTCARE) +#define P_PPI0_D6 (P_DONTCARE) +#define P_PPI0_D7 (P_DONTCARE) +#define P_PPI1_CLK (P_DONTCARE) +#define P_PPI1_FS1 (P_DONTCARE) +#define P_PPI1_FS2 (P_DONTCARE) +#define P_PPI1_FS3 (P_DONTCARE) +#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39)) +#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38)) +#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37)) +#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36)) +#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35)) +#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34)) +#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33)) +#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32)) +#define P_PPI1_D0 (P_DONTCARE) +#define P_PPI1_D1 (P_DONTCARE) +#define P_PPI1_D2 (P_DONTCARE) +#define P_PPI1_D3 (P_DONTCARE) +#define P_PPI1_D4 (P_DONTCARE) +#define P_PPI1_D5 (P_DONTCARE) +#define P_PPI1_D6 (P_DONTCARE) +#define P_PPI1_D7 (P_DONTCARE) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27)) +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21)) +#define P_SPORT1_DRPRI (P_DONTCARE) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17)) +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16)) +#define P_SPORT0_DRPRI (P_DONTCARE) +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15)) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) +#define P_TMR11 (P_DONTCARE) +#define P_TMR10 (P_DONTCARE) +#define P_TMR9 (P_DONTCARE) +#define P_TMR8 (P_DONTCARE) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0)) +#define P_SPI0_MOSI (P_DONTCARE) +#define P_SPI0_MIS0 (P_DONTCARE) +#define P_SPI0_SCK (P_DONTCARE) + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/include/asm-blackfin/portmux.h b/include/asm-blackfin/portmux.h new file mode 100644 index 0000000..9d3681e --- /dev/null +++ b/include/asm-blackfin/portmux.h @@ -0,0 +1,1133 @@ +/* + * Common header file for blackfin family of processors. + * + */ + +#ifndef _PORTMUX_H_ +#define _PORTMUX_H_ + +#define P_IDENT(x) ((x) & 0x1FF) +#define P_FUNCT(x) (((x) & 0x3) << 9) +#define P_FUNCT2MUX(x) (((x) >> 9) & 0x3) +#define P_DEFINED 0x8000 +#define P_UNDEF 0x4000 +#define P_MAYSHARE 0x2000 +#define P_DONTCARE 0x1000 + +#include +#include + +#ifndef P_SPORT2_TFS +#define P_SPORT2_TFS P_UNDEF +#endif + +#ifndef P_SPORT2_DTSEC +#define P_SPORT2_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT2_DTPRI +#define P_SPORT2_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT2_TSCLK +#define P_SPORT2_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT2_RFS +#define P_SPORT2_RFS P_UNDEF +#endif + +#ifndef P_SPORT2_DRSEC +#define P_SPORT2_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT2_DRPRI +#define P_SPORT2_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT2_RSCLK +#define P_SPORT2_RSCLK P_UNDEF +#endif + +#ifndef P_SPORT3_TFS +#define P_SPORT3_TFS P_UNDEF +#endif + +#ifndef P_SPORT3_DTSEC +#define P_SPORT3_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT3_DTPRI +#define P_SPORT3_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT3_TSCLK +#define P_SPORT3_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT3_RFS +#define P_SPORT3_RFS P_UNDEF +#endif + +#ifndef P_SPORT3_DRSEC +#define P_SPORT3_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT3_DRPRI +#define P_SPORT3_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT3_RSCLK +#define P_SPORT3_RSCLK P_UNDEF +#endif + +#ifndef P_TMR4 +#define P_TMR4 P_UNDEF +#endif + +#ifndef P_TMR5 +#define P_TMR5 P_UNDEF +#endif + +#ifndef P_TMR6 +#define P_TMR6 P_UNDEF +#endif + +#ifndef P_TMR7 +#define P_TMR7 P_UNDEF +#endif + +#ifndef P_TWI1_SCL +#define P_TWI1_SCL P_UNDEF +#endif + +#ifndef P_TWI1_SDA +#define P_TWI1_SDA P_UNDEF +#endif + +#ifndef P_UART3_RTS +#define P_UART3_RTS P_UNDEF +#endif + +#ifndef P_UART3_CTS +#define P_UART3_CTS P_UNDEF +#endif + +#ifndef P_UART2_TX +#define P_UART2_TX P_UNDEF +#endif + +#ifndef P_UART2_RX +#define P_UART2_RX P_UNDEF +#endif + +#ifndef P_UART3_TX +#define P_UART3_TX P_UNDEF +#endif + +#ifndef P_UART3_RX +#define P_UART3_RX P_UNDEF +#endif + +#ifndef P_SPI2_SS +#define P_SPI2_SS P_UNDEF +#endif + +#ifndef P_SPI2_SSEL1 +#define P_SPI2_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL2 +#define P_SPI2_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL3 +#define P_SPI2_SSEL3 P_UNDEF +#endif + +#ifndef P_SPI2_SCK +#define P_SPI2_SCK P_UNDEF +#endif + +#ifndef P_SPI2_MOSI +#define P_SPI2_MOSI P_UNDEF +#endif + +#ifndef P_SPI2_MISO +#define P_SPI2_MISO P_UNDEF +#endif + +#ifndef P_TMR0 +#define P_TMR0 P_UNDEF +#endif + +#ifndef P_TMR1 +#define P_TMR1 P_UNDEF +#endif + +#ifndef P_TMR2 +#define P_TMR2 P_UNDEF +#endif + +#ifndef P_TMR3 +#define P_TMR3 P_UNDEF +#endif + +#ifndef P_SPORT0_TFS +#define P_SPORT0_TFS P_UNDEF +#endif + +#ifndef P_SPORT0_DTSEC +#define P_SPORT0_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT0_DTPRI +#define P_SPORT0_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT0_TSCLK +#define P_SPORT0_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT0_RFS +#define P_SPORT0_RFS P_UNDEF +#endif + +#ifndef P_SPORT0_DRSEC +#define P_SPORT0_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT0_DRPRI +#define P_SPORT0_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT0_RSCLK +#define P_SPORT0_RSCLK P_UNDEF +#endif + +#ifndef P_SD_D0 +#define P_SD_D0 P_UNDEF +#endif + +#ifndef P_SD_D1 +#define P_SD_D1 P_UNDEF +#endif + +#ifndef P_SD_D2 +#define P_SD_D2 P_UNDEF +#endif + +#ifndef P_SD_D3 +#define P_SD_D3 P_UNDEF +#endif + +#ifndef P_SD_CLK +#define P_SD_CLK P_UNDEF +#endif + +#ifndef P_SD_CMD +#define P_SD_CMD P_UNDEF +#endif + +#ifndef P_MMCLK +#define P_MMCLK P_UNDEF +#endif + +#ifndef P_MBCLK +#define P_MBCLK P_UNDEF +#endif + +#ifndef P_PPI1_D0 +#define P_PPI1_D0 P_UNDEF +#endif + +#ifndef P_PPI1_D1 +#define P_PPI1_D1 P_UNDEF +#endif + +#ifndef P_PPI1_D2 +#define P_PPI1_D2 P_UNDEF +#endif + +#ifndef P_PPI1_D3 +#define P_PPI1_D3 P_UNDEF +#endif + +#ifndef P_PPI1_D4 +#define P_PPI1_D4 P_UNDEF +#endif + +#ifndef P_PPI1_D5 +#define P_PPI1_D5 P_UNDEF +#endif + +#ifndef P_PPI1_D6 +#define P_PPI1_D6 P_UNDEF +#endif + +#ifndef P_PPI1_D7 +#define P_PPI1_D7 P_UNDEF +#endif + +#ifndef P_PPI1_D8 +#define P_PPI1_D8 P_UNDEF +#endif + +#ifndef P_PPI1_D9 +#define P_PPI1_D9 P_UNDEF +#endif + +#ifndef P_PPI1_D10 +#define P_PPI1_D10 P_UNDEF +#endif + +#ifndef P_PPI1_D11 +#define P_PPI1_D11 P_UNDEF +#endif + +#ifndef P_PPI1_D12 +#define P_PPI1_D12 P_UNDEF +#endif + +#ifndef P_PPI1_D13 +#define P_PPI1_D13 P_UNDEF +#endif + +#ifndef P_PPI1_D14 +#define P_PPI1_D14 P_UNDEF +#endif + +#ifndef P_PPI1_D15 +#define P_PPI1_D15 P_UNDEF +#endif + +#ifndef P_HOST_D8 +#define P_HOST_D8 P_UNDEF +#endif + +#ifndef P_HOST_D9 +#define P_HOST_D9 P_UNDEF +#endif + +#ifndef P_HOST_D10 +#define P_HOST_D10 P_UNDEF +#endif + +#ifndef P_HOST_D11 +#define P_HOST_D11 P_UNDEF +#endif + +#ifndef P_HOST_D12 +#define P_HOST_D12 P_UNDEF +#endif + +#ifndef P_HOST_D13 +#define P_HOST_D13 P_UNDEF +#endif + +#ifndef P_HOST_D14 +#define P_HOST_D14 P_UNDEF +#endif + +#ifndef P_HOST_D15 +#define P_HOST_D15 P_UNDEF +#endif + +#ifndef P_HOST_D0 +#define P_HOST_D0 P_UNDEF +#endif + +#ifndef P_HOST_D1 +#define P_HOST_D1 P_UNDEF +#endif + +#ifndef P_HOST_D2 +#define P_HOST_D2 P_UNDEF +#endif + +#ifndef P_HOST_D3 +#define P_HOST_D3 P_UNDEF +#endif + +#ifndef P_HOST_D4 +#define P_HOST_D4 P_UNDEF +#endif + +#ifndef P_HOST_D5 +#define P_HOST_D5 P_UNDEF +#endif + +#ifndef P_HOST_D6 +#define P_HOST_D6 P_UNDEF +#endif + +#ifndef P_HOST_D7 +#define P_HOST_D7 P_UNDEF +#endif + +#ifndef P_SPORT1_TFS +#define P_SPORT1_TFS P_UNDEF +#endif + +#ifndef P_SPORT1_DTSEC +#define P_SPORT1_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT1_DTPRI +#define P_SPORT1_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT1_TSCLK +#define P_SPORT1_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT1_RFS +#define P_SPORT1_RFS P_UNDEF +#endif + +#ifndef P_SPORT1_DRSEC +#define P_SPORT1_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT1_DRPRI +#define P_SPORT1_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT1_RSCLK +#define P_SPORT1_RSCLK P_UNDEF +#endif + +#ifndef P_PPI2_D0 +#define P_PPI2_D0 P_UNDEF +#endif + +#ifndef P_PPI2_D1 +#define P_PPI2_D1 P_UNDEF +#endif + +#ifndef P_PPI2_D2 +#define P_PPI2_D2 P_UNDEF +#endif + +#ifndef P_PPI2_D3 +#define P_PPI2_D3 P_UNDEF +#endif + +#ifndef P_PPI2_D4 +#define P_PPI2_D4 P_UNDEF +#endif + +#ifndef P_PPI2_D5 +#define P_PPI2_D5 P_UNDEF +#endif + +#ifndef P_PPI2_D6 +#define P_PPI2_D6 P_UNDEF +#endif + +#ifndef P_PPI2_D7 +#define P_PPI2_D7 P_UNDEF +#endif + +#ifndef P_PPI0_D18 +#define P_PPI0_D18 P_UNDEF +#endif + +#ifndef P_PPI0_D19 +#define P_PPI0_D19 P_UNDEF +#endif + +#ifndef P_PPI0_D20 +#define P_PPI0_D20 P_UNDEF +#endif + +#ifndef P_PPI0_D21 +#define P_PPI0_D21 P_UNDEF +#endif + +#ifndef P_PPI0_D22 +#define P_PPI0_D22 P_UNDEF +#endif + +#ifndef P_PPI0_D23 +#define P_PPI0_D23 P_UNDEF +#endif + +#ifndef P_KEY_ROW0 +#define P_KEY_ROW0 P_UNDEF +#endif + +#ifndef P_KEY_ROW1 +#define P_KEY_ROW1 P_UNDEF +#endif + +#ifndef P_KEY_ROW2 +#define P_KEY_ROW2 P_UNDEF +#endif + +#ifndef P_KEY_ROW3 +#define P_KEY_ROW3 P_UNDEF +#endif + +#ifndef P_KEY_COL0 +#define P_KEY_COL0 P_UNDEF +#endif + +#ifndef P_KEY_COL1 +#define P_KEY_COL1 P_UNDEF +#endif + +#ifndef P_KEY_COL2 +#define P_KEY_COL2 P_UNDEF +#endif + +#ifndef P_KEY_COL3 +#define P_KEY_COL3 P_UNDEF +#endif + +#ifndef P_SPI0_SCK +#define P_SPI0_SCK P_UNDEF +#endif + +#ifndef P_SPI0_MISO +#define P_SPI0_MISO P_UNDEF +#endif + +#ifndef P_SPI0_MOSI +#define P_SPI0_MOSI P_UNDEF +#endif + +#ifndef P_SPI0_SS +#define P_SPI0_SS P_UNDEF +#endif + +#ifndef P_SPI0_SSEL1 +#define P_SPI0_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL2 +#define P_SPI0_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL3 +#define P_SPI0_SSEL3 P_UNDEF +#endif + +#ifndef P_UART0_TX +#define P_UART0_TX P_UNDEF +#endif + +#ifndef P_UART0_RX +#define P_UART0_RX P_UNDEF +#endif + +#ifndef P_UART1_RTS +#define P_UART1_RTS P_UNDEF +#endif + +#ifndef P_UART1_CTS +#define P_UART1_CTS P_UNDEF +#endif + +#ifndef P_PPI1_CLK +#define P_PPI1_CLK P_UNDEF +#endif + +#ifndef P_PPI1_FS1 +#define P_PPI1_FS1 P_UNDEF +#endif + +#ifndef P_PPI1_FS2 +#define P_PPI1_FS2 P_UNDEF +#endif + +#ifndef P_TWI0_SCL +#define P_TWI0_SCL P_UNDEF +#endif + +#ifndef P_TWI0_SDA +#define P_TWI0_SDA P_UNDEF +#endif + +#ifndef P_KEY_COL7 +#define P_KEY_COL7 P_UNDEF +#endif + +#ifndef P_KEY_ROW6 +#define P_KEY_ROW6 P_UNDEF +#endif + +#ifndef P_KEY_COL6 +#define P_KEY_COL6 P_UNDEF +#endif + +#ifndef P_KEY_ROW5 +#define P_KEY_ROW5 P_UNDEF +#endif + +#ifndef P_KEY_COL5 +#define P_KEY_COL5 P_UNDEF +#endif + +#ifndef P_KEY_ROW4 +#define P_KEY_ROW4 P_UNDEF +#endif + +#ifndef P_KEY_COL4 +#define P_KEY_COL4 P_UNDEF +#endif + +#ifndef P_KEY_ROW7 +#define P_KEY_ROW7 P_UNDEF +#endif + +#ifndef P_PPI0_D0 +#define P_PPI0_D0 P_UNDEF +#endif + +#ifndef P_PPI0_D1 +#define P_PPI0_D1 P_UNDEF +#endif + +#ifndef P_PPI0_D2 +#define P_PPI0_D2 P_UNDEF +#endif + +#ifndef P_PPI0_D3 +#define P_PPI0_D3 P_UNDEF +#endif + +#ifndef P_PPI0_D4 +#define P_PPI0_D4 P_UNDEF +#endif + +#ifndef P_PPI0_D5 +#define P_PPI0_D5 P_UNDEF +#endif + +#ifndef P_PPI0_D6 +#define P_PPI0_D6 P_UNDEF +#endif + +#ifndef P_PPI0_D7 +#define P_PPI0_D7 P_UNDEF +#endif + +#ifndef P_PPI0_D8 +#define P_PPI0_D8 P_UNDEF +#endif + +#ifndef P_PPI0_D9 +#define P_PPI0_D9 P_UNDEF +#endif + +#ifndef P_PPI0_D10 +#define P_PPI0_D10 P_UNDEF +#endif + +#ifndef P_PPI0_D11 +#define P_PPI0_D11 P_UNDEF +#endif + +#ifndef P_PPI0_D12 +#define P_PPI0_D12 P_UNDEF +#endif + +#ifndef P_PPI0_D13 +#define P_PPI0_D13 P_UNDEF +#endif + +#ifndef P_PPI0_D14 +#define P_PPI0_D14 P_UNDEF +#endif + +#ifndef P_PPI0_D15 +#define P_PPI0_D15 P_UNDEF +#endif + +#ifndef P_ATAPI_D0A +#define P_ATAPI_D0A P_UNDEF +#endif + +#ifndef P_ATAPI_D1A +#define P_ATAPI_D1A P_UNDEF +#endif + +#ifndef P_ATAPI_D2A +#define P_ATAPI_D2A P_UNDEF +#endif + +#ifndef P_ATAPI_D3A +#define P_ATAPI_D3A P_UNDEF +#endif + +#ifndef P_ATAPI_D4A +#define P_ATAPI_D4A P_UNDEF +#endif + +#ifndef P_ATAPI_D5A +#define P_ATAPI_D5A P_UNDEF +#endif + +#ifndef P_ATAPI_D6A +#define P_ATAPI_D6A P_UNDEF +#endif + +#ifndef P_ATAPI_D7A +#define P_ATAPI_D7A P_UNDEF +#endif + +#ifndef P_ATAPI_D8A +#define P_ATAPI_D8A P_UNDEF +#endif + +#ifndef P_ATAPI_D9A +#define P_ATAPI_D9A P_UNDEF +#endif + +#ifndef P_ATAPI_D10A +#define P_ATAPI_D10A P_UNDEF +#endif + +#ifndef P_ATAPI_D11A +#define P_ATAPI_D11A P_UNDEF +#endif + +#ifndef P_ATAPI_D12A +#define P_ATAPI_D12A P_UNDEF +#endif + +#ifndef P_ATAPI_D13A +#define P_ATAPI_D13A P_UNDEF +#endif + +#ifndef P_ATAPI_D14A +#define P_ATAPI_D14A P_UNDEF +#endif + +#ifndef P_ATAPI_D15A +#define P_ATAPI_D15A P_UNDEF +#endif + +#ifndef P_PPI0_CLK +#define P_PPI0_CLK P_UNDEF +#endif + +#ifndef P_PPI0_FS1 +#define P_PPI0_FS1 P_UNDEF +#endif + +#ifndef P_PPI0_FS2 +#define P_PPI0_FS2 P_UNDEF +#endif + +#ifndef P_PPI0_D16 +#define P_PPI0_D16 P_UNDEF +#endif + +#ifndef P_PPI0_D17 +#define P_PPI0_D17 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL1 +#define P_SPI1_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL2 +#define P_SPI1_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL3 +#define P_SPI1_SSEL3 P_UNDEF +#endif + +#ifndef P_SPI1_SCK +#define P_SPI1_SCK P_UNDEF +#endif + +#ifndef P_SPI1_MISO +#define P_SPI1_MISO P_UNDEF +#endif + +#ifndef P_SPI1_MOSI +#define P_SPI1_MOSI P_UNDEF +#endif + +#ifndef P_SPI1_SS +#define P_SPI1_SS P_UNDEF +#endif + +#ifndef P_CAN0_TX +#define P_CAN0_TX P_UNDEF +#endif + +#ifndef P_CAN0_RX +#define P_CAN0_RX P_UNDEF +#endif + +#ifndef P_CAN1_TX +#define P_CAN1_TX P_UNDEF +#endif + +#ifndef P_CAN1_RX +#define P_CAN1_RX P_UNDEF +#endif + +#ifndef P_ATAPI_A0A +#define P_ATAPI_A0A P_UNDEF +#endif + +#ifndef P_ATAPI_A1A +#define P_ATAPI_A1A P_UNDEF +#endif + +#ifndef P_ATAPI_A2A +#define P_ATAPI_A2A P_UNDEF +#endif + +#ifndef P_HOST_CE +#define P_HOST_CE P_UNDEF +#endif + +#ifndef P_HOST_RD +#define P_HOST_RD P_UNDEF +#endif + +#ifndef P_HOST_WR +#define P_HOST_WR P_UNDEF +#endif + +#ifndef P_MTXONB +#define P_MTXONB P_UNDEF +#endif + +#ifndef P_PPI2_FS2 +#define P_PPI2_FS2 P_UNDEF +#endif + +#ifndef P_PPI2_FS1 +#define P_PPI2_FS1 P_UNDEF +#endif + +#ifndef P_PPI2_CLK +#define P_PPI2_CLK P_UNDEF +#endif + +#ifndef P_CNT_CZM +#define P_CNT_CZM P_UNDEF +#endif + +#ifndef P_UART1_TX +#define P_UART1_TX P_UNDEF +#endif + +#ifndef P_UART1_RX +#define P_UART1_RX P_UNDEF +#endif + +#ifndef P_ATAPI_RESET +#define P_ATAPI_RESET P_UNDEF +#endif + +#ifndef P_HOST_ADDR +#define P_HOST_ADDR P_UNDEF +#endif + +#ifndef P_HOST_ACK +#define P_HOST_ACK P_UNDEF +#endif + +#ifndef P_MTX +#define P_MTX P_UNDEF +#endif + +#ifndef P_MRX +#define P_MRX P_UNDEF +#endif + +#ifndef P_MRXONB +#define P_MRXONB P_UNDEF +#endif + +#ifndef P_A4 +#define P_A4 P_UNDEF +#endif + +#ifndef P_A5 +#define P_A5 P_UNDEF +#endif + +#ifndef P_A6 +#define P_A6 P_UNDEF +#endif + +#ifndef P_A7 +#define P_A7 P_UNDEF +#endif + +#ifndef P_A8 +#define P_A8 P_UNDEF +#endif + +#ifndef P_A9 +#define P_A9 P_UNDEF +#endif + +#ifndef P_PPI1_FS3 +#define P_PPI1_FS3 P_UNDEF +#endif + +#ifndef P_PPI2_FS3 +#define P_PPI2_FS3 P_UNDEF +#endif + +#ifndef P_TMR8 +#define P_TMR8 P_UNDEF +#endif + +#ifndef P_TMR9 +#define P_TMR9 P_UNDEF +#endif + +#ifndef P_TMR10 +#define P_TMR10 P_UNDEF +#endif +#ifndef P_TMR11 +#define P_TMR11 P_UNDEF +#endif + +#ifndef P_DMAR0 +#define P_DMAR0 P_UNDEF +#endif + +#ifndef P_DMAR1 +#define P_DMAR1 P_UNDEF +#endif + +#ifndef P_PPI0_FS3 +#define P_PPI0_FS3 P_UNDEF +#endif + +#ifndef P_CNT_CDG +#define P_CNT_CDG P_UNDEF +#endif + +#ifndef P_CNT_CUD +#define P_CNT_CUD P_UNDEF +#endif + +#ifndef P_A10 +#define P_A10 P_UNDEF +#endif + +#ifndef P_A11 +#define P_A11 P_UNDEF +#endif + +#ifndef P_A12 +#define P_A12 P_UNDEF +#endif + +#ifndef P_A13 +#define P_A13 P_UNDEF +#endif + +#ifndef P_A14 +#define P_A14 P_UNDEF +#endif + +#ifndef P_A15 +#define P_A15 P_UNDEF +#endif + +#ifndef P_A16 +#define P_A16 P_UNDEF +#endif + +#ifndef P_A17 +#define P_A17 P_UNDEF +#endif + +#ifndef P_A18 +#define P_A18 P_UNDEF +#endif + +#ifndef P_A19 +#define P_A19 P_UNDEF +#endif + +#ifndef P_A20 +#define P_A20 P_UNDEF +#endif + +#ifndef P_A21 +#define P_A21 P_UNDEF +#endif + +#ifndef P_A22 +#define P_A22 P_UNDEF +#endif + +#ifndef P_A23 +#define P_A23 P_UNDEF +#endif + +#ifndef P_A24 +#define P_A24 P_UNDEF +#endif + +#ifndef P_A25 +#define P_A25 P_UNDEF +#endif + +#ifndef P_NOR_CLK +#define P_NOR_CLK P_UNDEF +#endif + +#ifndef P_TMRCLK +#define P_TMRCLK P_UNDEF +#endif + +#ifndef P_AMC_ARDY_NOR_WAIT +#define P_AMC_ARDY_NOR_WAIT P_UNDEF +#endif + +#ifndef P_NAND_CE +#define P_NAND_CE P_UNDEF +#endif + +#ifndef P_NAND_RB +#define P_NAND_RB P_UNDEF +#endif + +#ifndef P_ATAPI_DIOR +#define P_ATAPI_DIOR P_UNDEF +#endif + +#ifndef P_ATAPI_DIOW +#define P_ATAPI_DIOW P_UNDEF +#endif + +#ifndef P_ATAPI_CS0 +#define P_ATAPI_CS0 P_UNDEF +#endif + +#ifndef P_ATAPI_CS1 +#define P_ATAPI_CS1 P_UNDEF +#endif + +#ifndef P_ATAPI_DMACK +#define P_ATAPI_DMACK P_UNDEF +#endif + +#ifndef P_ATAPI_DMARQ +#define P_ATAPI_DMARQ P_UNDEF +#endif + +#ifndef P_ATAPI_INTRQ +#define P_ATAPI_INTRQ P_UNDEF +#endif + +#ifndef P_ATAPI_IORDY +#define P_ATAPI_IORDY P_UNDEF +#endif + +#ifndef P_AMC_BR +#define P_AMC_BR P_UNDEF +#endif + +#ifndef P_AMC_BG +#define P_AMC_BG P_UNDEF +#endif + +#ifndef P_AMC_BGH +#define P_AMC_BGH P_UNDEF +#endif + +/* EMAC */ + +#ifndef P_MII0_ETxD0 +#define P_MII0_ETxD0 P_UNDEF +#endif + +#ifndef P_MII0_ETxD1 +#define P_MII0_ETxD1 P_UNDEF +#endif + +#ifndef P_MII0_ETxD2 +#define P_MII0_ETxD2 P_UNDEF +#endif + +#ifndef P_MII0_ETxD3 +#define P_MII0_ETxD3 P_UNDEF +#endif + +#ifndef P_MII0_ETxEN +#define P_MII0_ETxEN P_UNDEF +#endif + +#ifndef P_MII0_TxCLK +#define P_MII0_TxCLK P_UNDEF +#endif + +#ifndef P_MII0_PHYINT +#define P_MII0_PHYINT P_UNDEF +#endif + +#ifndef P_MII0_COL +#define P_MII0_COL P_UNDEF +#endif + +#ifndef P_MII0_ERxD0 +#define P_MII0_ERxD0 P_UNDEF +#endif + +#ifndef P_MII0_ERxD1 +#define P_MII0_ERxD1 P_UNDEF +#endif + +#ifndef P_MII0_ERxD2 +#define P_MII0_ERxD2 P_UNDEF +#endif + +#ifndef P_MII0_ERxD3 +#define P_MII0_ERxD3 P_UNDEF +#endif + +#ifndef P_MII0_ERxDV +#define P_MII0_ERxDV P_UNDEF +#endif + +#ifndef P_MII0_ERxCLK +#define P_MII0_ERxCLK P_UNDEF +#endif + +#ifndef P_MII0_ERxER +#define P_MII0_ERxER P_UNDEF +#endif + +#ifndef P_MII0_CRS +#define P_MII0_CRS P_UNDEF +#endif + +#ifndef P_RMII0_REF_CLK +#define P_RMII0_REF_CLK P_UNDEF +#endif + +#ifndef P_RMII0_MDINT +#define P_RMII0_MDINT P_UNDEF +#endif + +#ifndef P_RMII0_CRS_DV +#define P_RMII0_CRS_DV P_UNDEF +#endif + +#ifndef P_MDC +#define P_MDC P_UNDEF +#endif + +#ifndef P_MDIO +#define P_MDIO P_UNDEF +#endif + +#endif /* _PORTMUX_H_ */ -- cgit v0.10.2 From 1d1894749cca89f4bb013364524199b3015d7b00 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 12 Jul 2007 12:32:00 +0800 Subject: Blackfin arch: combine the common code of free_initrd_mem and free_initmem Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c index 2d12449..68459cc 100644 --- a/arch/blackfin/mm/init.c +++ b/arch/blackfin/mm/init.c @@ -168,42 +168,31 @@ void __init mem_init(void) } } -#ifdef CONFIG_BLK_DEV_INITRD -void __init free_initrd_mem(unsigned long start, unsigned long end) +static __init void free_init_pages(const char *what, unsigned long begin, unsigned long end) { - int pages = 0; - for (; start < end; start += PAGE_SIZE) { - ClearPageReserved(virt_to_page(start)); - init_page_count(virt_to_page(start)); - free_page(start); + unsigned long addr; + /* next to check that the page we free is not a partial page */ + for (addr = begin; addr + PAGE_SIZE <= end; addr += PAGE_SIZE) { + ClearPageReserved(virt_to_page(addr)); + init_page_count(virt_to_page(addr)); + free_page(addr); totalram_pages++; - pages++; } - printk(KERN_NOTICE "Freeing initrd memory: %dk freed\n", pages); + printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10); +} + +#ifdef CONFIG_BLK_DEV_INITRD +void __init free_initrd_mem(unsigned long start, unsigned long end) +{ + free_init_pages("initrd memory", start, end); } #endif void __init free_initmem(void) { #ifdef CONFIG_RAMKERNEL - unsigned long addr; - /* - * the following code should be cool even if these sections - * are not page aligned. - */ - addr = PAGE_ALIGN((unsigned long)(__init_begin)); - /* next to check that the page we free is not a partial page */ - for (; addr + PAGE_SIZE < (unsigned long)(__init_end); - addr += PAGE_SIZE) { - ClearPageReserved(virt_to_page(addr)); - init_page_count(virt_to_page(addr)); - free_page(addr); - totalram_pages++; - } - printk(KERN_NOTICE - "Freeing unused kernel memory: %ldk freed (0x%x - 0x%x)\n", - (addr - PAGE_ALIGN((long)__init_begin)) >> 10, - (int)(PAGE_ALIGN((unsigned long)(__init_begin))), - (int)(addr - PAGE_SIZE)); + free_init_pages("unused kernel memory", + (unsigned long)(&__init_begin), + (unsigned long)(&__init_end)); #endif } -- cgit v0.10.2 From c04d66bbbdbbc7b5d55c42795f29e494190f8fb3 Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Thu, 12 Jul 2007 17:26:31 +0800 Subject: Blackfin arch: clean up some coding style issues Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c index 7977c2c..6b9fd03 100644 --- a/arch/blackfin/mach-common/ints-priority-dc.c +++ b/arch/blackfin/mach-common/ints-priority-dc.c @@ -371,8 +371,8 @@ int __init init_arch_irq(void) bfin_write_SICA_IMASK1(SIC_UNMASK_ALL); SSYNC(); - bfin_write_SICA_IWR0(IWR_ENABLE_ALL); - bfin_write_SICA_IWR1(IWR_ENABLE_ALL); + bfin_write_SICA_IWR0(IWR_ENABLE_ALL); + bfin_write_SICA_IWR1(IWR_ENABLE_ALL); local_irq_disable(); diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c index c3bb2fb..28a878c 100644 --- a/arch/blackfin/mach-common/ints-priority-sc.c +++ b/arch/blackfin/mach-common/ints-priority-sc.c @@ -147,8 +147,8 @@ static void bfin_internal_mask_irq(unsigned int irq) unsigned mask_bank, mask_bit; mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; mask_bit = (irq - (IRQ_CORETMR + 1)) % 32; - bfin_write_SIC_IMASK( mask_bank, bfin_read_SIC_IMASK(mask_bank) & \ - ~(1 << mask_bit)); + bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & + ~(1 << mask_bit)); #endif SSYNC(); } @@ -161,9 +161,9 @@ static void bfin_internal_unmask_irq(unsigned int irq) #else unsigned mask_bank, mask_bit; mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; - mask_bit = (irq - (IRQ_CORETMR + 1))%32; - bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | \ - ( 1 << mask_bit)); + mask_bit = (irq - (IRQ_CORETMR + 1)) % 32; + bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | + (1 << mask_bit)); #endif SSYNC(); } @@ -728,7 +728,7 @@ int __init init_arch_irq(void) bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); bfin_write_SIC_IWR0(IWR_ENABLE_ALL); bfin_write_SIC_IWR1(IWR_ENABLE_ALL); - bfin_write_SIC_IWR2(IWR_ENABLE_ALL); + bfin_write_SIC_IWR2(IWR_ENABLE_ALL); #else bfin_write_SIC_IMASK(SIC_UNMASK_ALL); bfin_write_SIC_IWR(IWR_ENABLE_ALL); @@ -878,7 +878,6 @@ void do_irq(int vec, struct pt_regs *fp) sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0); sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1); sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2); - for (;; ivg++) { if (ivg >= ivg_stop) { diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index 87f2385..98d35a9 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h @@ -68,7 +68,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write32(SIC_IWR0, iwr0); bfin_write32(SIC_IWR1, iwr1); bfin_write32(SIC_IWR2, iwr2); - } #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h index 6e8b816..1a8ec9e 100644 --- a/include/asm-blackfin/mach-bf561/cdefBF561.h +++ b/include/asm-blackfin/mach-bf561/cdefBF561.h @@ -74,7 +74,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) local_irq_restore(flags); bfin_write32(SICA_IWR0, iwr0); bfin_write32(SICA_IWR1, iwr1); - } #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) diff --git a/include/asm-blackfin/mman.h b/include/asm-blackfin/mman.h index 4d504f9..b58f5ad 100644 --- a/include/asm-blackfin/mman.h +++ b/include/asm-blackfin/mman.h @@ -22,8 +22,6 @@ #define MAP_NORESERVE 0x4000 /* don't check for reservations */ #define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ #define MAP_NONBLOCK 0x10000 /* do not block on IO */ -#define MAP_UNINITIALIZE 0x4000000 /* For anonymous mmap, memory could - be uninitialized. */ #define MS_ASYNC 1 /* sync memory asynchronously */ #define MS_INVALIDATE 2 /* invalidate the caches */ -- cgit v0.10.2 From 5cf77a5fd03c65b9dd33c283ce308a3abc4cb375 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 12 Jul 2007 14:26:26 +0800 Subject: Blackfin arch: extract the entry point from the linked kernel extract the entry point from the linked kernel rather than assuming entry point == load address Signed-off-by: Bryan Wu diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile index 49e8098..8cd3356 100644 --- a/arch/blackfin/boot/Makefile +++ b/arch/blackfin/boot/Makefile @@ -13,7 +13,8 @@ extra-y += vmlinux.bin vmlinux.gz quiet_cmd_uimage = UIMAGE $@ cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \ - -C gzip -a $(CONFIG_BOOT_LOAD) -e $(CONFIG_BOOT_LOAD) -n 'Linux-$(KERNELRELEASE)' \ + -C gzip -n 'Linux-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \ + -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \ -d $< $@ $(obj)/vmlinux.bin: vmlinux FORCE -- cgit v0.10.2 From 798b77095dea2f89e42f5aaa0e5b18833fea5358 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 12 Jul 2007 14:35:15 +0800 Subject: Blackfin arch: as pointed out by Robert P. J. Day, update the CPU_FREQ name to match current Kconfig Cc: Robert P. J. Day Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf533/Makefile b/arch/blackfin/mach-bf533/Makefile index 0322546..8cce173 100644 --- a/arch/blackfin/mach-bf533/Makefile +++ b/arch/blackfin/mach-bf533/Makefile @@ -6,4 +6,4 @@ extra-y := head.o obj-y := ints-priority.o dma.o -obj-$(CONFIG_CPU_FREQ_BF533) += cpu.o +obj-$(CONFIG_CPU_FREQ) += cpu.o -- cgit v0.10.2 From db0fa2064585a099e0c652983bd38d71ee7830f3 Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Thu, 12 Jul 2007 14:55:05 +0800 Subject: Blackfin arch: add missing CONFIG_LARGE_ALLOCS when upstream merging Signed-off-by: Bryan Wu diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 2372b03..017defa 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -585,6 +585,14 @@ endchoice source "mm/Kconfig" +config LARGE_ALLOCS + bool "Allow allocating large blocks (> 1MB) of memory" + help + Allow the slab memory allocator to keep chains for very large + memory sizes - upto 32MB. You may need this if your system has + a lot of RAM, and you need to able to allocate very large + contiguous chunks. If unsure, say N. + config BFIN_DMA_5XX bool "Enable DMA Support" depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561 || BF54x) -- cgit v0.10.2 From e745106ce34553171a5d8d2450be07c0cffe39d5 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Thu, 12 Jul 2007 15:20:25 +0800 Subject: Blackfin arch: set up gpio interrupt IRQ_PJ9 for BF54x ATAPI PATA driver Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h index 58c87f0..0b3325b 100644 --- a/include/asm-blackfin/mach-bf548/irq.h +++ b/include/asm-blackfin/mach-bf548/irq.h @@ -318,7 +318,6 @@ Events (highest priority) EMU 0 #define IRQ_PI14 BFIN_PI_IRQ(14) #define IRQ_PI15 BFIN_PI_IRQ(15) -#if 0 #define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1) #define IRQ_PJ0 BFIN_PJ_IRQ(0) #define IRQ_PJ1 BFIN_PJ_IRQ(1) @@ -336,10 +335,9 @@ Events (highest priority) EMU 0 #define IRQ_PJ13 BFIN_PJ_IRQ(13) #define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */ #define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */ -#endif #ifdef CONFIG_IRQCHIP_DEMUX_GPIO -#define NR_IRQS (IRQ_PI15+1) +#define NR_IRQS (IRQ_PJ15+1) #else #define NR_IRQS (SYS_IRQS+1) #endif -- cgit v0.10.2 From 61b59563266aa6bedaf5d45b9b25bc48bb4d3ed3 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Thu, 12 Jul 2007 17:06:45 +0800 Subject: Blackfin arch: Add peripheral io API to gpio header file Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu diff --git a/include/asm-blackfin/mach-bf548/gpio.h b/include/asm-blackfin/mach-bf548/gpio.h index 8c5847a..dbf66bc 100644 --- a/include/asm-blackfin/mach-bf548/gpio.h +++ b/include/asm-blackfin/mach-bf548/gpio.h @@ -210,3 +210,7 @@ struct gpio_port_t { unsigned int port_mux; }; +int gpio_request(unsigned short gpio, const char *label); +void peripheral_free(unsigned short per); +int peripheral_request_list(unsigned short per[], const char *label); +void peripheral_free_list(unsigned short per[]); -- cgit v0.10.2 From db83b991bce1b4792125d4b23bb108e8cfd5d366 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 12 Jul 2007 12:07:40 +0800 Subject: Video Console: Blackfin doesnt support VGA console Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig index 63b85bf..d3b8a6b 100644 --- a/drivers/video/console/Kconfig +++ b/drivers/video/console/Kconfig @@ -6,7 +6,7 @@ menu "Console display driver support" config VGA_CONSOLE bool "VGA text console" if EMBEDDED || !X86 - depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH + depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH && !BFIN default y help Saying Y here will allow you to use Linux in text mode through a -- cgit v0.10.2 From f4d640c9be1979a603ed017e1e03a16ba3a4d7a1 Mon Sep 17 00:00:00 2001 From: Roy Huang Date: Thu, 12 Jul 2007 16:43:46 +0800 Subject: Blackfin serial driver: supporting BF548-EZKIT serial port Signed-off-by: Roy Huang Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 71a4ac5..2adbed4 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -599,7 +599,7 @@ config UART0_RTS_PIN config SERIAL_BFIN_UART1 bool "Enable UART1" - depends on SERIAL_BFIN && (BF534 || BF536 || BF537) + depends on SERIAL_BFIN && (BF534 || BF536 || BF537 || BF54x) help Enable UART1 @@ -612,18 +612,58 @@ config BFIN_UART1_CTSRTS config UART1_CTS_PIN int "UART1 CTS pin" - depends on BFIN_UART1_CTSRTS + depends on BFIN_UART1_CTSRTS && (BF53x || BF561) default -1 help Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. config UART1_RTS_PIN int "UART1 RTS pin" - depends on BFIN_UART1_CTSRTS + depends on BFIN_UART1_CTSRTS && (BF53x || BF561) default -1 help Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. +config SERIAL_BFIN_UART2 + bool "Enable UART2" + depends on SERIAL_BFIN && (BF54x) + help + Enable UART2 + +config BFIN_UART2_CTSRTS + bool "Enable UART2 hardware flow control" + depends on SERIAL_BFIN_UART2 + help + Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS + signal. + +config UART2_CTS_PIN + int "UART2 CTS pin" + depends on BFIN_UART2_CTSRTS + default -1 + help + Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. + +config UART2_RTS_PIN + int "UART2 RTS pin" + depends on BFIN_UART2_CTSRTS + default -1 + help + Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. + +config SERIAL_BFIN_UART3 + bool "Enable UART3" + depends on SERIAL_BFIN && (BF54x) + help + Enable UART3 + +config BFIN_UART3_CTSRTS + bool "Enable UART3 hardware flow control" + depends on SERIAL_BFIN_UART3 + help + Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS + signal. + config SERIAL_IMX bool "IMX serial port support" depends on ARM && ARCH_IMX diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c index f7926dc..66c92bc 100644 --- a/drivers/serial/bfin_5xx.c +++ b/drivers/serial/bfin_5xx.c @@ -86,15 +86,29 @@ static void bfin_serial_stop_tx(struct uart_port *port) { struct bfin_serial_port *uart = (struct bfin_serial_port *)port; +#ifdef CONFIG_BF54x + while (!(UART_GET_LSR(uart) & TEMT)) + continue; +#endif + #ifdef CONFIG_SERIAL_BFIN_DMA disable_dma(uart->tx_dma_channel); #else +#ifdef CONFIG_BF54x + /* Waiting for Transmission Finished */ + while (!(UART_GET_LSR(uart) & TFI)) + continue; + /* Clear TFI bit */ + UART_PUT_LSR(uart, TFI); + UART_CLEAR_IER(uart, ETBEI); +#else unsigned short ier; ier = UART_GET_IER(uart); ier &= ~ETBEI; UART_PUT_IER(uart, ier); #endif +#endif } /* @@ -107,12 +121,16 @@ static void bfin_serial_start_tx(struct uart_port *port) #ifdef CONFIG_SERIAL_BFIN_DMA bfin_serial_dma_tx_chars(uart); #else +#ifdef CONFIG_BF54x + UART_SET_IER(uart, ETBEI); +#else unsigned short ier; ier = UART_GET_IER(uart); ier |= ETBEI; UART_PUT_IER(uart, ier); bfin_serial_tx_chars(uart); #endif +#endif } /* @@ -121,6 +139,9 @@ static void bfin_serial_start_tx(struct uart_port *port) static void bfin_serial_stop_rx(struct uart_port *port) { struct bfin_serial_port *uart = (struct bfin_serial_port *)port; +#ifdef CONFIG_BF54x + UART_CLEAR_IER(uart, ERBFI); +#else unsigned short ier; ier = UART_GET_IER(uart); @@ -129,6 +150,7 @@ static void bfin_serial_stop_rx(struct uart_port *port) #endif ier &= ~ERBFI; UART_PUT_IER(uart, ier); +#endif } /* @@ -325,10 +347,21 @@ static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id) { struct bfin_serial_port *uart = dev_id; +#ifdef CONFIG_BF54x + unsigned short status; + spin_lock(&uart->port.lock); + status = UART_GET_LSR(uart); + while ((UART_GET_IER(uart) & ERBFI) && (status & DR)) { + bfin_serial_rx_chars(uart); + status = UART_GET_LSR(uart); + } + spin_unlock(&uart->port.lock); +#else spin_lock(&uart->port.lock); while ((UART_GET_IIR(uart) & IIR_STATUS) == IIR_RX_READY) bfin_serial_rx_chars(uart); spin_unlock(&uart->port.lock); +#endif return IRQ_HANDLED; } @@ -336,10 +369,21 @@ static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id) { struct bfin_serial_port *uart = dev_id; +#ifdef CONFIG_BF54x + unsigned short status; + spin_lock(&uart->port.lock); + status = UART_GET_LSR(uart); + while ((UART_GET_IER(uart) & ETBEI) && (status & THRE)) { + bfin_serial_tx_chars(uart); + status = UART_GET_LSR(uart); + } + spin_unlock(&uart->port.lock); +#else spin_lock(&uart->port.lock); while ((UART_GET_IIR(uart) & IIR_STATUS) == IIR_TX_READY) bfin_serial_tx_chars(uart); spin_unlock(&uart->port.lock); +#endif return IRQ_HANDLED; } @@ -350,7 +394,6 @@ static void bfin_serial_do_work(struct work_struct *work) bfin_serial_mctrl_check(uart); } - #endif #ifdef CONFIG_SERIAL_BFIN_DMA @@ -399,9 +442,13 @@ static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) set_dma_x_count(uart->tx_dma_channel, uart->tx_count); set_dma_x_modify(uart->tx_dma_channel, 1); enable_dma(uart->tx_dma_channel); +#ifdef CONFIG_BF54x + UART_SET_IER(uart, ETBEI); +#else ier = UART_GET_IER(uart); ier |= ETBEI; UART_PUT_IER(uart, ier); +#endif spin_unlock_irqrestore(&uart->port.lock, flags); } @@ -481,9 +528,13 @@ static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id) if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) { clear_dma_irqstat(uart->tx_dma_channel); disable_dma(uart->tx_dma_channel); +#ifdef CONFIG_BF54x + UART_CLEAR_IER(uart, ETBEI); +#else ier = UART_GET_IER(uart); ier &= ~ETBEI; UART_PUT_IER(uart, ier); +#endif xmit->tail = (xmit->tail+uart->tx_count) &(UART_XMIT_SIZE -1); uart->port.icount.tx+=uart->tx_count; @@ -665,7 +716,11 @@ static int bfin_serial_startup(struct uart_port *port) return -EBUSY; } #endif +#ifdef CONFIG_BF54x + UART_SET_IER(uart, ERBFI); +#else UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI); +#endif return 0; } @@ -756,29 +811,41 @@ bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios, /* Disable UART */ ier = UART_GET_IER(uart); +#ifdef CONFIG_BF54x + UART_CLEAR_IER(uart, 0xF); +#else UART_PUT_IER(uart, 0); +#endif +#ifndef CONFIG_BF54x /* Set DLAB in LCR to Access DLL and DLH */ val = UART_GET_LCR(uart); val |= DLAB; UART_PUT_LCR(uart, val); SSYNC(); +#endif UART_PUT_DLL(uart, quot & 0xFF); SSYNC(); UART_PUT_DLH(uart, (quot >> 8) & 0xFF); SSYNC(); +#ifndef CONFIG_BF54x /* Clear DLAB in LCR to Access THR RBR IER */ val = UART_GET_LCR(uart); val &= ~DLAB; UART_PUT_LCR(uart, val); SSYNC(); +#endif UART_PUT_LCR(uart, lcr); /* Enable UART */ +#ifdef CONFIG_BF54x + UART_SET_IER(uart, ier); +#else UART_PUT_IER(uart, ier); +#endif val = UART_GET_GCTL(uart); val |= UCEN; @@ -890,15 +957,15 @@ static void __init bfin_serial_init_ports(void) bfin_serial_resource[i].uart_rts_pin; #endif bfin_serial_hw_init(&bfin_serial_ports[i]); - } + } #ifdef CONFIG_SERIAL_BFIN_CONSOLE static void bfin_serial_console_putchar(struct uart_port *port, int ch) { struct bfin_serial_port *uart = (struct bfin_serial_port *)port; - while (!(UART_GET_LSR(uart))) + while (!(UART_GET_LSR(uart) & THRE)) barrier(); UART_PUT_CHAR(uart, ch); SSYNC(); @@ -950,18 +1017,22 @@ bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud, case 2: *bits = 7; break; case 3: *bits = 8; break; } +#ifndef CONFIG_BF54x /* Set DLAB in LCR to Access DLL and DLH */ val = UART_GET_LCR(uart); val |= DLAB; UART_PUT_LCR(uart, val); +#endif dll = UART_GET_DLL(uart); dlh = UART_GET_DLH(uart); +#ifndef CONFIG_BF54x /* Clear DLAB in LCR to Access THR RBR IER */ val = UART_GET_LCR(uart); val &= ~DLAB; UART_PUT_LCR(uart, val); +#endif *baud = get_sclk() / (16*(dll | dlh << 8)); } -- cgit v0.10.2