From b848f6224554afd621c92abcf7948796a214772c Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 18 Jun 2013 15:37:41 +0200 Subject: arm: mvebu: enable mini-PCIe connectors on Armada 370 RD The Armada 370 RD board has two internal mini-PCIe connectors. This commit adds the necessary Device Tree informations to enable the usage of those mini-PCIe connectors. Signed-off-by: Thomas Petazzoni Cc: Florian Fainelli Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 89c2110..a3a2fed 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -85,6 +85,22 @@ gpios = <&gpio0 6 1>; }; }; + + pcie-controller { + status = "okay"; + + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Internal mini-PCIe connector */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; }; }; }; -- cgit v0.10.2 From 01db527e657d6cf646c6e6f059ad41e7023a25e7 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Tue, 18 Jun 2013 12:31:19 -0300 Subject: ARM: Kirkwood: Fix the internal register ranges translation Although the internal register window size is 1 MiB, the previous ranges translation for the internal register space had a size of 0x4000000. This was done to allow the crypto and nand node to access the corresponding 'sram' and 'nand' decoding windows. In order to describe the hardware more accurately, we declare the real 1 MiB internal register space in the ranges, and add a translation entry for the nand node to access the 'nand' window. This commit will make future improvements on the MBus DT binding easier. Signed-off-by: Ezequiel Garcia Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 5d7b759..1ae3eb2 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -30,7 +30,8 @@ ocp@f1000000 { compatible = "simple-bus"; - ranges = <0x00000000 0xf1000000 0x4000000 + ranges = <0x00000000 0xf1000000 0x0100000 + 0xf4000000 0xf4000000 0x0000400 0xf5000000 0xf5000000 0x0000400>; #address-cells = <1>; #size-cells = <1>; @@ -163,7 +164,7 @@ ale = <1>; bank-width = <1>; compatible = "marvell,orion-nand"; - reg = <0x3000000 0x400>; + reg = <0xf4000000 0x400>; chip-delay = <25>; /* set partition map and/or chip-delay in board dts */ clocks = <&gate_clk 7>; -- cgit v0.10.2