From faf1ce807ddc8b3d017be39c1bc68a31f5833d82 Mon Sep 17 00:00:00 2001
From: Tang Yuantian <Yuantian.Tang@freescale.com>
Date: Mon, 20 Oct 2014 17:17:02 +0800
Subject: dts: ls1021a: updated the clockgen node

Fixed some error in clockgen node.

This patch also added clock source to CPU nodes to support
CPU frequency switch dynamically.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Change-Id: I2d40c3bc9c766d62d9cb8a3c00b9d5e1c2e65f41
Reviewed-on: http://git.am.freescale.net:8181/21689
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 2818298..eeddae1 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -47,12 +47,14 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <0xf00>;
+			clocks = <&cluster1_clk>;
 		};
 
 		cpu@f01 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <0xf01>;
+			clocks = <&cluster1_clk>;
 		};
 	};
 
@@ -194,16 +196,7 @@
 				reg = <0x800>;
 				clocks = <&sysclk>;
 				clock-output-names = "cga-pll1", "cga-pll1-div2",
-						"cga-pll1-div3", "cga-pll1-div4";
-			};
-
-			cga_pll2: pll2@820 {
-				compatible = "fsl,core-pll-clock";
-				#clock-cells = <1>;
-				reg = <0x820>;
-				clocks = <&sysclk>;
-				clock-output-names = "cga-pll2", "cga-pll2-div2",
-						"cga-pll2-div3", "cga-pll2-div4";
+						"cga-pll1-div4";
 			};
 
 			platform_clk: pll@c00 {
@@ -214,15 +207,13 @@
 				clock-output-names = "platform-clk", "platform-clk-div2";
 			};
 
-
 			cluster1_clk: clk0c0@0 {
 				compatible = "fsl,core-mux-clock";
-				#clock-cells = <1>;
+				#clock-cells = <0>;
 				reg = <0x0>;
-				clock-names = "pll1cga", "pll1cga-div2";
-				clocks = <&cga_pll1 0>, <&cga_pll1 2>;
+				clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
+				clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
 				clock-output-names = "cluster1-clk";
-
 			};
 
 		};
-- 
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