From 2efd65d4645ef265bc7748f684ae677f7edd916b Mon Sep 17 00:00:00 2001
From: Chenhui Zhao <chenhui.zhao@freescale.com>
Date: Tue, 2 Dec 2014 14:45:49 +0800
Subject: arm: ls1: make the workaround more stable

Increase the delay time to 15ms, which is more stable.

The delay is added in the commit:
commit cd20fed09d426bcc38348e8d1dd32ad828239170
Author: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com>
Date:   Wed Nov 19 15:49:53 2014 +0800

    arm: ls1: provide a workaround for core soft reset

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Change-Id: Ic7c57346bedab74d5161c36435373af7bc41fb48
Reviewed-on: http://git.am.freescale.net:8181/25423
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>

diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 3f554e9..22f9814 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -218,7 +218,7 @@ static int ls1021a_reset_secondary(unsigned int cpu)
 	iowrite32be(0x80000000, scfg_base + SCFG_CORESRENCR);
 	iowrite32be(0x80000000, scfg_base +
 				SCFG_CORE0_SFT_RST + STRIDE_4B * cpu);
-	mdelay(6);
+	mdelay(15);
 
 	/* LS1021a errata. after reset, core state machine registers
 	 * need to force release manually.
-- 
cgit v0.10.2