From e73486b8c9d8d649dd080eb1b810e5b0c11a955a Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Wed, 23 Sep 2009 12:59:07 +0900 Subject: ARM: S3C64XX: Fix S3C64XX_CLKDIV0_ARM_MASK value Fix the values of S3C6400_CLKDIV0_ARM_MASK and S3C6410_CLKDIV0_ARM_MASK. Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h index a8777a7..ff46e7f 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h @@ -51,8 +51,8 @@ #define S3C6400_CLKDIV0_HCLK_SHIFT (8) #define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4) #define S3C6400_CLKDIV0_MPLL_SHIFT (4) -#define S3C6400_CLKDIV0_ARM_MASK (0x3 << 0) -#define S3C6410_CLKDIV0_ARM_MASK (0x7 << 0) +#define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0) +#define S3C6410_CLKDIV0_ARM_MASK (0xf << 0) #define S3C6400_CLKDIV0_ARM_SHIFT (0) /* CLKDIV1 */ -- cgit v0.10.2 From e179ac0f4ea4f1e989fa754bada366f88fd81d27 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 21 Oct 2009 18:17:58 +0100 Subject: ARM: S3C64XX: Set rate of crystal mux The current code assumes that the external clock mux will be set to the crystal. Set this up explicitly within the clock API. Signed-off-by: Mark Brown Signed-off-by: Ben Dooks diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index 9745852..6ffa21e 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c @@ -677,6 +677,9 @@ void __init_or_cpufreq s3c6400_setup_clocks(void) printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); + /* For now assume the mux always selects the crystal */ + clk_ext_xtal_mux.parent = xtal_clk; + epll = s3c6400_get_epll(xtal); mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON)); apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON)); -- cgit v0.10.2