From 699efdd2d34c535f415516e06d3d9f0bed131664 Mon Sep 17 00:00:00 2001 From: JeongHyeon Kim Date: Thu, 21 Jul 2011 16:19:19 +0900 Subject: ARM: EXYNOS4: Add support for ORIGEN board Insignal's ORIGEN board is based Samsung EXYNOS4210 SoC. Signed-off-by: JeongHyeon Kim Signed-off-by: Tushar Behera [kgene.kim@samsung.com: Fixed SoC name to EXYNOS4210] [kgene.kim@samsung.com: Selected MACH_ORIGEN in exynos4_defconfig] Signed-off-by: Kukjin Kim diff --git a/arch/arm/configs/exynos4_defconfig b/arch/arm/configs/exynos4_defconfig index da53ff3..cd40bb5 100644 --- a/arch/arm/configs/exynos4_defconfig +++ b/arch/arm/configs/exynos4_defconfig @@ -11,6 +11,7 @@ CONFIG_MACH_SMDKV310=y CONFIG_MACH_ARMLEX4210=y CONFIG_MACH_UNIVERSAL_C210=y CONFIG_MACH_NURI=y +CONFIG_MACH_ORIGEN=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_SMP=y diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig index 1435fc3..3ab0f18 100644 --- a/arch/arm/mach-exynos4/Kconfig +++ b/arch/arm/mach-exynos4/Kconfig @@ -186,6 +186,16 @@ config MACH_NURI help Machine support for Samsung Mobile NURI Board. +config MACH_ORIGEN + bool "ORIGEN" + select CPU_EXYNOS4210 + select S3C_DEV_RTC + select S3C_DEV_WDT + select S3C_DEV_HSMMC2 + select EXYNOS4_SETUP_SDHCI + help + Machine support for ORIGEN based on Samsung EXYNOS4210 + endmenu comment "Configuration for HSMMC bus width" diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile index 60fe5ec..4b22dc5 100644 --- a/arch/arm/mach-exynos4/Makefile +++ b/arch/arm/mach-exynos4/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o obj-$(CONFIG_MACH_NURI) += mach-nuri.o +obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o # device support diff --git a/arch/arm/mach-exynos4/mach-origen.c b/arch/arm/mach-exynos4/mach-origen.c new file mode 100644 index 0000000..ed59f86 --- /dev/null +++ b/arch/arm/mach-exynos4/mach-origen.c @@ -0,0 +1,108 @@ +/* linux/arch/arm/mach-exynos4/mach-origen.c + * + * Copyright (c) 2011 Insignal Co., Ltd. + * http://www.insignal.co.kr/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define ORIGEN_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define ORIGEN_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + +static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = ORIGEN_UCON_DEFAULT, + .ulcon = ORIGEN_ULCON_DEFAULT, + .ufcon = ORIGEN_UFCON_DEFAULT, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = ORIGEN_UCON_DEFAULT, + .ulcon = ORIGEN_ULCON_DEFAULT, + .ufcon = ORIGEN_UFCON_DEFAULT, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = ORIGEN_UCON_DEFAULT, + .ulcon = ORIGEN_ULCON_DEFAULT, + .ufcon = ORIGEN_UFCON_DEFAULT, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = ORIGEN_UCON_DEFAULT, + .ulcon = ORIGEN_ULCON_DEFAULT, + .ufcon = ORIGEN_UFCON_DEFAULT, + }, +}; + +static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = EXYNOS4_GPK2(2), + .ext_cd_gpio_invert = 1, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, +}; + +static struct platform_device *origen_devices[] __initdata = { + &s3c_device_hsmmc2, + &s3c_device_rtc, + &s3c_device_wdt, +}; + +static void __init origen_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(24000000); + s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); +} + +static void __init origen_machine_init(void) +{ + s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata); + platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices)); +} + +MACHINE_START(ORIGEN, "ORIGEN") + /* Maintainer: JeongHyeon Kim */ + .boot_params = S5P_PA_SDRAM + 0x100, + .init_irq = exynos4_init_irq, + .map_io = origen_map_io, + .init_machine = origen_machine_init, + .timer = &exynos4_timer, +MACHINE_END -- cgit v0.10.2 From dd58bdbceb087238bead08e05226c0cef20aab4d Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 8 Aug 2011 14:35:13 -0600 Subject: ARM: Tegra: Harmony: Add USB device The Tegra USB port is attached an an SMSC9514; a combination USB hub and Ethernet controller. This change is extracted from a change in the ChromeOS 2.6.38 kernel. Signed-off-by: Olof Johansson Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c index 846cd7d..f528a5a 100644 --- a/arch/arm/mach-tegra/board-harmony.c +++ b/arch/arm/mach-tegra/board-harmony.c @@ -117,6 +117,7 @@ static struct platform_device *harmony_devices[] __initdata = { &tegra_sdhci_device1, &tegra_sdhci_device2, &tegra_sdhci_device4, + &tegra_ehci3_device, &tegra_i2s_device1, &tegra_das_device, &tegra_pcm_device, @@ -140,6 +141,7 @@ static __initdata struct tegra_clk_init_table harmony_clk_init_table[] = { { "pll_a_out0", "pll_a", 11289600, true }, { "cdev1", NULL, 0, true }, { "i2s1", "pll_a_out0", 11289600, false}, + { "usb3", "clk_m", 12000000, true }, { NULL, NULL, 0, 0}, }; -- cgit v0.10.2 From a697e694aeb82f2643825c45dc0214666172c540 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 8 Aug 2011 14:35:14 -0600 Subject: ARM: Tegra: Seaboard board updates for audio * Initialize clock tree for audio * Add GPIO base definitions * Add audio GPIO definitions * Define platform data for WM8903 and ASoC machine driver * Add special case for Kaen to handle HP_MUTE GPIO * Register platform devices for audio * Update pinmux to cater for new GPIOs used for audio Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c index 0bda495..7879750 100644 --- a/arch/arm/mach-tegra/board-seaboard-pinmux.c +++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c @@ -49,7 +49,7 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = { {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, - {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, @@ -133,7 +133,7 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = { {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, - {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, @@ -167,6 +167,7 @@ static struct tegra_gpio_table gpio_table[] = { { .gpio = TEGRA_GPIO_LIDSWITCH, .enable = true }, { .gpio = TEGRA_GPIO_POWERKEY, .enable = true }, { .gpio = TEGRA_GPIO_ISL29018_IRQ, .enable = true }, + { .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true }, }; void __init seaboard_pinmux_init(void) diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c index 56cbabf..07cd8e4 100644 --- a/arch/arm/mach-tegra/board-seaboard.c +++ b/arch/arm/mach-tegra/board-seaboard.c @@ -25,9 +25,12 @@ #include #include +#include + #include #include #include +#include #include #include @@ -62,6 +65,10 @@ static __initdata struct tegra_clk_init_table seaboard_clk_init_table[] = { /* name parent rate enabled */ { "uartb", "pll_p", 216000000, true}, { "uartd", "pll_p", 216000000, true}, + { "pll_a", "pll_p_out1", 56448000, true }, + { "pll_a_out0", "pll_a", 11289600, true }, + { "cdev1", NULL, 0, true }, + { "i2s1", "pll_a_out0", 11289600, false}, { NULL, NULL, 0, 0}, }; @@ -117,6 +124,22 @@ static struct tegra_sdhci_platform_data sdhci_pdata4 = { .is_8bit = 1, }; +static struct tegra_wm8903_platform_data seaboard_audio_pdata = { + .gpio_spkr_en = TEGRA_GPIO_SPKR_EN, + .gpio_hp_det = TEGRA_GPIO_HP_DET, + .gpio_hp_mute = -1, + .gpio_int_mic_en = -1, + .gpio_ext_mic_en = -1, +}; + +static struct platform_device seaboard_audio_device = { + .name = "tegra-snd-wm8903", + .id = 0, + .dev = { + .platform_data = &seaboard_audio_pdata, + }, +}; + static struct platform_device *seaboard_devices[] __initdata = { &debug_uart, &tegra_pmu_device, @@ -124,6 +147,10 @@ static struct platform_device *seaboard_devices[] __initdata = { &tegra_sdhci_device3, &tegra_sdhci_device1, &seaboard_gpio_keys_device, + &tegra_i2s_device1, + &tegra_das_device, + &tegra_pcm_device, + &seaboard_audio_device, }; static struct i2c_board_info __initdata isl29018_device = { @@ -135,12 +162,33 @@ static struct i2c_board_info __initdata adt7461_device = { I2C_BOARD_INFO("adt7461", 0x4c), }; +static struct wm8903_platform_data wm8903_pdata = { + .irq_active_low = 0, + .micdet_cfg = 0, + .micdet_delay = 100, + .gpio_base = SEABOARD_GPIO_WM8903(0), + .gpio_cfg = { + WM8903_GPIO_NO_CONFIG, + WM8903_GPIO_NO_CONFIG, + 0, + WM8903_GPIO_NO_CONFIG, + WM8903_GPIO_NO_CONFIG, + }, +}; + +static struct i2c_board_info __initdata wm8903_device = { + I2C_BOARD_INFO("wm8903", 0x1a), + .platform_data = &wm8903_pdata, + .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ), +}; + static void __init seaboard_i2c_init(void) { gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018"); gpio_direction_input(TEGRA_GPIO_ISL29018_IRQ); i2c_register_board_info(0, &isl29018_device, 1); + i2c_register_board_info(0, &wm8903_device, 1); i2c_register_board_info(3, &adt7461_device, 1); @@ -182,6 +230,9 @@ static void __init tegra_kaen_init(void) debug_uart_platform_data[0].mapbase = TEGRA_UARTB_BASE; debug_uart_platform_data[0].irq = INT_UARTB; + seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE; + tegra_gpio_enable(TEGRA_GPIO_KAEN_HP_MUTE); + seaboard_common_init(); seaboard_i2c_init(); diff --git a/arch/arm/mach-tegra/board-seaboard.h b/arch/arm/mach-tegra/board-seaboard.h index d8415e1..d06c334 100644 --- a/arch/arm/mach-tegra/board-seaboard.h +++ b/arch/arm/mach-tegra/board-seaboard.h @@ -17,6 +17,9 @@ #ifndef _MACH_TEGRA_BOARD_SEABOARD_H #define _MACH_TEGRA_BOARD_SEABOARD_H +#define SEABOARD_GPIO_TPS6586X(_x_) (TEGRA_NR_GPIOS + (_x_)) +#define SEABOARD_GPIO_WM8903(_x_) (SEABOARD_GPIO_TPS6586X(4) + (_x_)) + #define TEGRA_GPIO_SD2_CD TEGRA_GPIO_PI5 #define TEGRA_GPIO_SD2_WP TEGRA_GPIO_PH1 #define TEGRA_GPIO_SD2_POWER TEGRA_GPIO_PI6 @@ -31,10 +34,11 @@ #define TEGRA_GPIO_MAGNETOMETER TEGRA_GPIO_PN5 #define TEGRA_GPIO_ISL29018_IRQ TEGRA_GPIO_PZ2 #define TEGRA_GPIO_AC_ONLINE TEGRA_GPIO_PV3 - -#define TPS_GPIO_BASE TEGRA_NR_GPIOS - -#define TPS_GPIO_WWAN_PWR (TPS_GPIO_BASE + 2) +#define TEGRA_GPIO_WWAN_PWR SEABOARD_GPIO_TPS6586X(2) +#define TEGRA_GPIO_CDC_IRQ TEGRA_GPIO_PX3 +#define TEGRA_GPIO_SPKR_EN SEABOARD_GPIO_WM8903(2) +#define TEGRA_GPIO_HP_DET TEGRA_GPIO_PX1 +#define TEGRA_GPIO_KAEN_HP_MUTE TEGRA_GPIO_PA5 void seaboard_pinmux_init(void); -- cgit v0.10.2 From bc24ed4f21c0ef6d99b653077747c3104f5f9b60 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 8 Aug 2011 14:35:15 -0600 Subject: ARM: Tegra: Seaboard: Add USB devices Seaboard has a couple of external USB ports. Add the platform devices and GPIO infra-structure to enable these. I tested both ports with a mouse on Seaboard non-clamshell. This change is extracted from code in the ChromeOS 2.6.38 kernel. Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c index 7879750..74f78b7 100644 --- a/arch/arm/mach-tegra/board-seaboard-pinmux.c +++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c @@ -168,6 +168,7 @@ static struct tegra_gpio_table gpio_table[] = { { .gpio = TEGRA_GPIO_POWERKEY, .enable = true }, { .gpio = TEGRA_GPIO_ISL29018_IRQ, .enable = true }, { .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true }, + { .gpio = TEGRA_GPIO_USB1, .enable = true }, }; void __init seaboard_pinmux_init(void) diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c index 07cd8e4..237a94a 100644 --- a/arch/arm/mach-tegra/board-seaboard.c +++ b/arch/arm/mach-tegra/board-seaboard.c @@ -69,6 +69,8 @@ static __initdata struct tegra_clk_init_table seaboard_clk_init_table[] = { { "pll_a_out0", "pll_a", 11289600, true }, { "cdev1", NULL, 0, true }, { "i2s1", "pll_a_out0", 11289600, false}, + { "usbd", "clk_m", 12000000, true}, + { "usb3", "clk_m", 12000000, true}, { NULL, NULL, 0, 0}, }; @@ -182,6 +184,29 @@ static struct i2c_board_info __initdata wm8903_device = { .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ), }; +static int seaboard_ehci_init(void) +{ + int gpio_status; + + gpio_status = gpio_request(TEGRA_GPIO_USB1, "VBUS_USB1"); + if (gpio_status < 0) { + pr_err("VBUS_USB1 request GPIO FAILED\n"); + WARN_ON(1); + } + + gpio_status = gpio_direction_output(TEGRA_GPIO_USB1, 1); + if (gpio_status < 0) { + pr_err("VBUS_USB1 request GPIO DIRECTION FAILED\n"); + WARN_ON(1); + } + gpio_set_value(TEGRA_GPIO_USB1, 1); + + platform_device_register(&tegra_ehci1_device); + platform_device_register(&tegra_ehci3_device); + + return 0; +} + static void __init seaboard_i2c_init(void) { gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018"); @@ -209,6 +234,8 @@ static void __init seaboard_common_init(void) tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4; platform_add_devices(seaboard_devices, ARRAY_SIZE(seaboard_devices)); + + seaboard_ehci_init(); } static void __init tegra_seaboard_init(void) -- cgit v0.10.2 From de7164db70af94e58dca84426374138cd3a18f34 Mon Sep 17 00:00:00 2001 From: Marc Dietrich Date: Sun, 7 Aug 2011 21:00:51 +0200 Subject: ARM: tegra: paz00: add support serial port on JP1 UART-A is connected to JP1 and used by the bootloader for debugging output while UART-D is connected to the mini-pcie expansion slot. Signed-off-by: Marc Dietrich Signed-off-by: Olof Johansson diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index ea2f79c..f3b7376 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -45,6 +45,16 @@ static struct plat_serial8250_port debug_uart_platform_data[] = { { + /* serial port on JP1 */ + .membase = IO_ADDRESS(TEGRA_UARTA_BASE), + .mapbase = TEGRA_UARTA_BASE, + .irq = INT_UARTA, + .flags = UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 216000000, + }, { + /* serial port on mini-pcie */ .membase = IO_ADDRESS(TEGRA_UARTD_BASE), .mapbase = TEGRA_UARTD_BASE, .irq = INT_UARTD, @@ -94,6 +104,7 @@ static void __init tegra_paz00_fixup(struct machine_desc *desc, static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { /* name parent rate enabled */ + { "uarta", "pll_p", 216000000, true }, { "uartd", "pll_p", 216000000, true }, { NULL, NULL, 0, 0}, }; -- cgit v0.10.2 From 9aaa15a739a0a3880922a850573493daa4ee4bcc Mon Sep 17 00:00:00 2001 From: Marc Dietrich Date: Sun, 7 Aug 2011 21:00:52 +0200 Subject: ARM: tegra: paz00: enable rfkill for internal wifi card This patch adds support for controlling the rfkill gpios for the internal WIFI card via the rfkill_gpio driver. Signed-off-by: Marc Dietrich Signed-off-by: Olof Johansson diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c index bdd2627..70c5710 100644 --- a/arch/arm/mach-tegra/board-paz00-pinmux.c +++ b/arch/arm/mach-tegra/board-paz00-pinmux.c @@ -145,6 +145,8 @@ static struct tegra_gpio_table gpio_table[] = { { .gpio = TEGRA_GPIO_SD1_WP, .enable = true }, { .gpio = TEGRA_GPIO_SD1_POWER, .enable = true }, { .gpio = TEGRA_ULPI_RST, .enable = true }, + { .gpio = TEGRA_WIFI_PWRN, .enable = true }, + { .gpio = TEGRA_WIFI_RST, .enable = true }, }; void paz00_pinmux_init(void) diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index f3b7376..6b798e7 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -75,10 +76,26 @@ static struct platform_device debug_uart = { }, }; +static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = { + .name = "wifi_rfkill", + .reset_gpio = TEGRA_WIFI_RST, + .shutdown_gpio = TEGRA_WIFI_PWRN, + .type = RFKILL_TYPE_WLAN, +}; + +static struct platform_device wifi_rfkill_device = { + .name = "rfkill_gpio", + .id = -1, + .dev = { + .platform_data = &wifi_rfkill_platform_data, + }, +}; + static struct platform_device *paz00_devices[] __initdata = { &debug_uart, &tegra_sdhci_device1, &tegra_sdhci_device4, + &wifi_rfkill_device, }; static void paz00_i2c_init(void) diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h index d4ff39d..e780f30 100644 --- a/arch/arm/mach-tegra/board-paz00.h +++ b/arch/arm/mach-tegra/board-paz00.h @@ -17,10 +17,17 @@ #ifndef _MACH_TEGRA_BOARD_PAZ00_H #define _MACH_TEGRA_BOARD_PAZ00_H -#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5 -#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1 -#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PT3 -#define TEGRA_ULPI_RST TEGRA_GPIO_PV0 +/* SDCARD */ +#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5 +#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1 +#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PT3 + +/* ULPI */ +#define TEGRA_ULPI_RST TEGRA_GPIO_PV0 + +/* WIFI */ +#define TEGRA_WIFI_PWRN TEGRA_GPIO_PK5 +#define TEGRA_WIFI_RST TEGRA_GPIO_PD1 void paz00_pinmux_init(void); -- cgit v0.10.2 From 8e219ebfa0e3f5d99f01cc57c6b84023343ff22a Mon Sep 17 00:00:00 2001 From: Marc Dietrich Date: Sun, 7 Aug 2011 21:00:53 +0200 Subject: ARM: tegra: paz00: enable wifi led This adds support for the wifi led. It is automaticly triggered by the rfkill0 event. Signed-off-by: Marc Dietrich Signed-off-by: Olof Johansson diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c index 70c5710..2225769 100644 --- a/arch/arm/mach-tegra/board-paz00-pinmux.c +++ b/arch/arm/mach-tegra/board-paz00-pinmux.c @@ -147,6 +147,7 @@ static struct tegra_gpio_table gpio_table[] = { { .gpio = TEGRA_ULPI_RST, .enable = true }, { .gpio = TEGRA_WIFI_PWRN, .enable = true }, { .gpio = TEGRA_WIFI_RST, .enable = true }, + { .gpio = TEGRA_WIFI_LED, .enable = true }, }; void paz00_pinmux_init(void) diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index 6b798e7..45111f6 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -91,11 +91,33 @@ static struct platform_device wifi_rfkill_device = { }, }; +static struct gpio_led gpio_leds[] = { + { + .name = "wifi-led", + .default_trigger = "rfkill0", + .gpio = TEGRA_WIFI_LED, + }, +}; + +static struct gpio_led_platform_data gpio_led_info = { + .leds = gpio_leds, + .num_leds = ARRAY_SIZE(gpio_leds), +}; + +static struct platform_device leds_gpio = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &gpio_led_info, + }, +}; + static struct platform_device *paz00_devices[] __initdata = { &debug_uart, &tegra_sdhci_device1, &tegra_sdhci_device4, &wifi_rfkill_device, + &leds_gpio, }; static void paz00_i2c_init(void) diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h index e780f30..86057c3 100644 --- a/arch/arm/mach-tegra/board-paz00.h +++ b/arch/arm/mach-tegra/board-paz00.h @@ -28,6 +28,7 @@ /* WIFI */ #define TEGRA_WIFI_PWRN TEGRA_GPIO_PK5 #define TEGRA_WIFI_RST TEGRA_GPIO_PD1 +#define TEGRA_WIFI_LED TEGRA_GPIO_PD0 void paz00_pinmux_init(void); -- cgit v0.10.2 From 24810cb53c0c66eb2922117c6a53c64c3f7a07a6 Mon Sep 17 00:00:00 2001 From: Marc Dietrich Date: Sun, 7 Aug 2011 21:00:55 +0200 Subject: ARM: tegra: paz00: reorder the SDHCI channel init This reorders the SDHCI channel init order. With this patch, the internal emmc gets the mmcblk0 device while the external sdmmc port gets mmcblk1. This change is only for convenience. Signed-off-by: Marc Dietrich Signed-off-by: Olof Johansson diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index 45111f6..51d847f 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -114,8 +114,8 @@ static struct platform_device leds_gpio = { static struct platform_device *paz00_devices[] __initdata = { &debug_uart, - &tegra_sdhci_device1, &tegra_sdhci_device4, + &tegra_sdhci_device1, &wifi_rfkill_device, &leds_gpio, }; -- cgit v0.10.2 From 11b3adb45da636a839bd2b7c300c616e0e2c38d6 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 8 Aug 2011 15:01:05 -0600 Subject: ARM: Tegra: Force PORT_TEGRA as the UART type 8250.c recently gained an explicit PORT_TEGRA port type. Specifically request this in all Tegra boards' UART platform data. Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c index f528a5a..987dab5 100644 --- a/arch/arm/mach-tegra/board-harmony.c +++ b/arch/arm/mach-tegra/board-harmony.c @@ -49,7 +49,8 @@ static struct plat_serial8250_port debug_uart_platform_data[] = { .membase = IO_ADDRESS(TEGRA_UARTD_BASE), .mapbase = TEGRA_UARTD_BASE, .irq = INT_UARTD, - .flags = UPF_BOOT_AUTOCONF, + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, + .type = PORT_TEGRA, .iotype = UPIO_MEM, .regshift = 2, .uartclk = 216000000, diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index 51d847f..7630c23 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -50,7 +50,8 @@ static struct plat_serial8250_port debug_uart_platform_data[] = { .membase = IO_ADDRESS(TEGRA_UARTA_BASE), .mapbase = TEGRA_UARTA_BASE, .irq = INT_UARTA, - .flags = UPF_BOOT_AUTOCONF, + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, + .type = PORT_TEGRA, .iotype = UPIO_MEM, .regshift = 2, .uartclk = 216000000, @@ -59,7 +60,8 @@ static struct plat_serial8250_port debug_uart_platform_data[] = { .membase = IO_ADDRESS(TEGRA_UARTD_BASE), .mapbase = TEGRA_UARTD_BASE, .irq = INT_UARTD, - .flags = UPF_BOOT_AUTOCONF, + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, + .type = PORT_TEGRA, .iotype = UPIO_MEM, .regshift = 2, .uartclk = 216000000, diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c index 237a94a..25446df 100644 --- a/arch/arm/mach-tegra/board-seaboard.c +++ b/arch/arm/mach-tegra/board-seaboard.c @@ -44,7 +44,8 @@ static struct plat_serial8250_port debug_uart_platform_data[] = { { /* Memory and IRQ filled in before registration */ - .flags = UPF_BOOT_AUTOCONF, + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, + .type = PORT_TEGRA, .iotype = UPIO_MEM, .regshift = 2, .uartclk = 216000000, diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c index 89a6d2a..91875b9 100644 --- a/arch/arm/mach-tegra/board-trimslice.c +++ b/arch/arm/mach-tegra/board-trimslice.c @@ -46,7 +46,8 @@ static struct plat_serial8250_port debug_uart_platform_data[] = { .membase = IO_ADDRESS(TEGRA_UARTA_BASE), .mapbase = TEGRA_UARTA_BASE, .irq = INT_UARTA, - .flags = UPF_BOOT_AUTOCONF, + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, + .type = PORT_TEGRA, .iotype = UPIO_MEM, .regshift = 2, .uartclk = 216000000, -- cgit v0.10.2 From ad9f6677575e80ce23cb491d5ffb7b536772552e Mon Sep 17 00:00:00 2001 From: Marc Dietrich Date: Wed, 10 Aug 2011 19:21:56 +0200 Subject: ARM: tegra: paz00: add clocks required for usb operation These clocks are required for usb operation. pll_p_out4 needs to be set to 24 MHz. The other clocks default to "off" in order to save some energy. Signed-off-by: Marc Dietrich Acked-by: Stephen Warren Signed-off-by: Olof Johansson diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index 7630c23..d161590 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -147,6 +147,12 @@ static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { /* name parent rate enabled */ { "uarta", "pll_p", 216000000, true }, { "uartd", "pll_p", 216000000, true }, + + { "pll_p_out4", "pll_p", 24000000, true }, + { "usbd", "clk_m", 12000000, false }, + { "usb2", "clk_m", 12000000, false }, + { "usb3", "clk_m", 12000000, false }, + { NULL, NULL, 0, 0}, }; -- cgit v0.10.2 From c06af3cc6a27991187fd513765fed943684d41bf Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Sat, 20 Aug 2011 02:18:18 +0900 Subject: ARM: SAMSUNG: Add support for detecting CPU at runtime The soc_is_[name]() can be used to distinguish cpu at runtime. This patch was originally from Changhwan Youn Acked-by: Changhwan Youn Cc: Ben Dooks Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-s3c64xx/cpu.c b/arch/arm/mach-s3c64xx/cpu.c index 374e45e..7b665f3 100644 --- a/arch/arm/mach-s3c64xx/cpu.c +++ b/arch/arm/mach-s3c64xx/cpu.c @@ -43,16 +43,16 @@ static const char name_s3c6410[] = "S3C6410"; static struct cpu_table cpu_ids[] __initdata = { { - .idcode = 0x36400000, - .idmask = 0xfffff000, + .idcode = S3C6400_CPU_ID, + .idmask = S3C64XX_CPU_MASK, .map_io = s3c6400_map_io, .init_clocks = s3c6400_init_clocks, .init_uarts = s3c6400_init_uarts, .init = s3c6400_init, .name = name_s3c6400, }, { - .idcode = 0x36410100, - .idmask = 0xffffff00, + .idcode = S3C6410_CPU_ID, + .idmask = S3C64XX_CPU_MASK, .map_io = s3c6410_map_io, .init_clocks = s3c6410_init_clocks, .init_uarts = s3c6410_init_uarts, @@ -140,22 +140,20 @@ void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) { - unsigned long idcode; - /* initialise the io descriptors we need for initialisation */ iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); iotable_init(mach_desc, size); - idcode = __raw_readl(S3C_VA_SYS + 0x118); - if (!idcode) { + samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0x118); + if (!samsung_cpu_id) { /* S3C6400 has the ID register in a different place, * and needs a write before it can be read. */ __raw_writel(0x0, S3C_VA_SYS + 0xA1C); - idcode = __raw_readl(S3C_VA_SYS + 0xA1C); + samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0xA1C); } - s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); + s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); } static __init int s3c64xx_sysdev_init(void) diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index c1fc6c6..ead21a4 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c @@ -215,19 +215,17 @@ static void s3c24xx_pm_restart(char mode, const char *cmd) void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) { - unsigned long idcode = 0x0; - /* initialise the io descriptors we need for initialisation */ iotable_init(mach_desc, size); iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); if (cpu_architecture() >= CPU_ARCH_ARMv5) { - idcode = s3c24xx_read_idcode_v5(); + samsung_cpu_id = s3c24xx_read_idcode_v5(); } else { - idcode = s3c24xx_read_idcode_v4(); + samsung_cpu_id = s3c24xx_read_idcode_v4(); } arm_pm_restart = s3c24xx_pm_restart; - s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); + s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); } diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c index bbc2aa7..3ef6734 100644 --- a/arch/arm/plat-s5p/cpu.c +++ b/arch/arm/plat-s5p/cpu.c @@ -36,40 +36,40 @@ static const char name_exynos4210[] = "EXYNOS4210"; static struct cpu_table cpu_ids[] __initdata = { { - .idcode = 0x56440100, - .idmask = 0xfffff000, + .idcode = S5P6440_CPU_ID, + .idmask = S5P64XX_CPU_MASK, .map_io = s5p6440_map_io, .init_clocks = s5p6440_init_clocks, .init_uarts = s5p6440_init_uarts, .init = s5p64x0_init, .name = name_s5p6440, }, { - .idcode = 0x36450000, - .idmask = 0xfffff000, + .idcode = S5P6450_CPU_ID, + .idmask = S5P64XX_CPU_MASK, .map_io = s5p6450_map_io, .init_clocks = s5p6450_init_clocks, .init_uarts = s5p6450_init_uarts, .init = s5p64x0_init, .name = name_s5p6450, }, { - .idcode = 0x43100000, - .idmask = 0xfffff000, + .idcode = S5PC100_CPU_ID, + .idmask = S5PC100_CPU_MASK, .map_io = s5pc100_map_io, .init_clocks = s5pc100_init_clocks, .init_uarts = s5pc100_init_uarts, .init = s5pc100_init, .name = name_s5pc100, }, { - .idcode = 0x43110000, - .idmask = 0xfffff000, + .idcode = S5PV210_CPU_ID, + .idmask = S5PV210_CPU_MASK, .map_io = s5pv210_map_io, .init_clocks = s5pv210_init_clocks, .init_uarts = s5pv210_init_uarts, .init = s5pv210_init, .name = name_s5pv210, }, { - .idcode = 0x43210000, - .idmask = 0xfffe0000, + .idcode = EXYNOS4210_CPU_ID, + .idmask = EXYNOS4_CPU_MASK, .map_io = exynos4_map_io, .init_clocks = exynos4_init_clocks, .init_uarts = exynos4_init_uarts, @@ -114,13 +114,11 @@ static struct map_desc s5p_iodesc[] __initdata = { void __init s5p_init_io(struct map_desc *mach_desc, int size, void __iomem *cpuid_addr) { - unsigned long idcode; - /* initialize the io descriptors we need for initialization */ iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc)); if (mach_desc) iotable_init(mach_desc, size); - idcode = __raw_readl(cpuid_addr); - s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); + samsung_cpu_id = __raw_readl(cpuid_addr); + s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); } diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index c0a5741..bdf43ad 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -1,9 +1,12 @@ /* linux/arch/arm/plat-samsung/include/plat/cpu.h * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * * Copyright (c) 2004-2005 Simtec Electronics * Ben Dooks * - * Header file for S3C24XX CPU support + * Header file for Samsung CPU support * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -15,6 +18,88 @@ #ifndef __SAMSUNG_PLAT_CPU_H #define __SAMSUNG_PLAT_CPU_H +extern unsigned long samsung_cpu_id; + +#define S3C24XX_CPU_ID 0x32400000 +#define S3C24XX_CPU_MASK 0xFFF00000 + +#define S3C6400_CPU_ID 0x36400000 +#define S3C6410_CPU_ID 0x36410000 +#define S3C64XX_CPU_ID (S3C6400_CPU_ID & S3C6410_CPU_ID) +#define S3C64XX_CPU_MASK 0x1FF40000 + +#define S5P6440_CPU_ID 0x56440000 +#define S5P6450_CPU_ID 0x36450000 +#define S5P64XX_CPU_MASK 0x1FF40000 + +#define S5PC100_CPU_ID 0x43100000 +#define S5PC100_CPU_MASK 0xFFFFF000 + +#define S5PV210_CPU_ID 0x43110000 +#define S5PV210_CPU_MASK 0xFFFFF000 + +#define EXYNOS4210_CPU_ID 0x43210000 +#define EXYNOS4_CPU_MASK 0xFFFE0000 + +#define IS_SAMSUNG_CPU(name, id, mask) \ +static inline int is_samsung_##name(void) \ +{ \ + return ((samsung_cpu_id & mask) == (id & mask)); \ +} + +IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK) +IS_SAMSUNG_CPU(s3c64xx, S3C64XX_CPU_ID, S3C64XX_CPU_MASK) +IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK) +IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK) +IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK) +IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK) +IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) + +#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ + defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \ + defined(CONFIG_CPU_S3C2442) || defined(CONFIG_CPU_S3C244X) || \ + defined(CONFIG_CPU_S3C2443) +# define soc_is_s3c24xx() is_samsung_s3c24xx() +#else +# define soc_is_s3c24xx() 0 +#endif + +#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) +# define soc_is_s3c64xx() is_samsung_s3c64xx() +#else +# define soc_is_s3c64xx() 0 +#endif + +#if defined(CONFIG_CPU_S5P6440) +# define soc_is_s5p6440() is_samsung_s5p6440() +#else +# define soc_is_s5p6440() 0 +#endif + +#if defined(CONFIG_CPU_S5P6450) +# define soc_is_s5p6450() is_samsung_s5p6450() +#else +# define soc_is_s5p6450() 0 +#endif + +#if defined(CONFIG_CPU_S5PC100) +# define soc_is_s5pc100() is_samsung_s5pc100() +#else +# define soc_is_s5pc100() 0 +#endif + +#if defined(CONFIG_CPU_S5PV210) +# define soc_is_s5pv210() is_samsung_s5pv210() +#else +# define soc_is_s5pv210() 0 +#endif + +#if defined(CONFIG_CPU_EXYNOS4210) +# define soc_is_exynos4210() is_samsung_exynos4210() +#else +# define soc_is_exynos4210() 0 +#endif + #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } #ifndef MHZ diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c index 79d10fc..40b1228 100644 --- a/arch/arm/plat-samsung/init.c +++ b/arch/arm/plat-samsung/init.c @@ -30,6 +30,7 @@ #include static struct cpu_table *cpu; +unsigned long samsung_cpu_id; static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode, struct cpu_table *tab, -- cgit v0.10.2 From a3d9358406b7529373ccafbf6d264f811884959c Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Sat, 20 Aug 2011 02:30:08 +0900 Subject: ARM: S5P64X0: Use soc_is_s5p64x0() to distinguish cpu at runtime Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c index ac825e8..1fd9c79 100644 --- a/arch/arm/mach-s5p64x0/dev-spi.c +++ b/arch/arm/mach-s5p64x0/dev-spi.c @@ -21,6 +21,7 @@ #include #include +#include #include #include @@ -185,11 +186,8 @@ struct platform_device s5p64x0_device_spi1 = { void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) { - unsigned int id; struct s3c64xx_spi_info *pd; - id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000; - /* Reject invalid configuration */ if (!num_cs || src_clk_nr < 0 || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) { @@ -199,7 +197,7 @@ void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) switch (cntrlr) { case 0: - if (id == 0x50000) + if (soc_is_s5p6450()) pd = &s5p6450_spi0_pdata; else pd = &s5p6440_spi0_pdata; @@ -207,7 +205,7 @@ void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) s5p64x0_device_spi0.dev.platform_data = pd; break; case 1: - if (id == 0x50000) + if (soc_is_s5p6450()) pd = &s5p6450_spi1_pdata; else pd = &s5p6440_spi1_pdata; diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c index d7ad944..0e5b3e6 100644 --- a/arch/arm/mach-s5p64x0/dma.c +++ b/arch/arm/mach-s5p64x0/dma.c @@ -28,6 +28,7 @@ #include #include +#include #include #include @@ -133,11 +134,7 @@ static struct platform_device s5p64x0_device_pdma = { static int __init s5p64x0_dma_init(void) { - unsigned int id; - - id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000; - - if (id == 0x50000) + if (soc_is_s5p6450()) s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata; else s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata; diff --git a/arch/arm/mach-s5p64x0/gpiolib.c b/arch/arm/mach-s5p64x0/gpiolib.c index e7fb3b0..700dac6 100644 --- a/arch/arm/mach-s5p64x0/gpiolib.c +++ b/arch/arm/mach-s5p64x0/gpiolib.c @@ -19,6 +19,7 @@ #include #include +#include #include #include #include @@ -473,14 +474,10 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip, static int __init s5p64x0_gpiolib_init(void) { - unsigned int chipid; - - chipid = __raw_readl(S5P64X0_SYS_ID); - s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs, ARRAY_SIZE(s5p64x0_gpio_cfgs)); - if ((chipid & 0xff000) == 0x50000) { + if (soc_is_s5p6450()) { samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit, ARRAY_SIZE(s5p6450_gpio_2bit)); diff --git a/arch/arm/mach-s5p64x0/irq-eint.c b/arch/arm/mach-s5p64x0/irq-eint.c index 69ed454..94104c4 100644 --- a/arch/arm/mach-s5p64x0/irq-eint.c +++ b/arch/arm/mach-s5p64x0/irq-eint.c @@ -17,6 +17,7 @@ #include #include +#include #include #include @@ -67,7 +68,7 @@ static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type) __raw_writel(ctrl, S5P64X0_EINT0CON0); /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */ - if (0x50000 == (__raw_readl(S5P64X0_SYS_ID) & 0xFF000)) + if (soc_is_s5p6450()) s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2)); else s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2)); -- cgit v0.10.2 From e6d1cb9f1fffd7e300af6d8f6731a486d6255e3f Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Sat, 20 Aug 2011 12:18:07 +0900 Subject: ARM: SAMSUNG: Add support for handling of cpu revision This patch adds plat-samsung/cpu.c for detecting of cpu id and silicon revision. This patch was originally from Changhwan Youn Acked-by: Changhwan Youn Cc: Ben Dooks Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-s3c64xx/cpu.c b/arch/arm/mach-s3c64xx/cpu.c index 7b665f3..6c498f9 100644 --- a/arch/arm/mach-s3c64xx/cpu.c +++ b/arch/arm/mach-s3c64xx/cpu.c @@ -144,14 +144,8 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); iotable_init(mach_desc, size); - samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0x118); - if (!samsung_cpu_id) { - /* S3C6400 has the ID register in a different place, - * and needs a write before it can be read. */ - - __raw_writel(0x0, S3C_VA_SYS + 0xA1C); - samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0xA1C); - } + /* detect cpu id */ + s3c64xx_init_cpu(); s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); } diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index ead21a4..3c63353 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c @@ -224,6 +224,7 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) } else { samsung_cpu_id = s3c24xx_read_idcode_v4(); } + s3c24xx_init_cpu(); arm_pm_restart = s3c24xx_pm_restart; diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c index 3ef6734..04392c7 100644 --- a/arch/arm/plat-s5p/cpu.c +++ b/arch/arm/plat-s5p/cpu.c @@ -119,6 +119,8 @@ void __init s5p_init_io(struct map_desc *mach_desc, if (mach_desc) iotable_init(mach_desc, size); - samsung_cpu_id = __raw_readl(cpuid_addr); + /* detect cpu id and rev. */ + s5p_init_cpu(cpuid_addr); + s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); } diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 853764b..3de756d 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -11,7 +11,7 @@ obj- := # Objects we always build independent of SoC choice -obj-y += init.o +obj-y += init.o cpu.o obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o obj-y += clock.o obj-y += pwm-clock.o diff --git a/arch/arm/plat-samsung/cpu.c b/arch/arm/plat-samsung/cpu.c new file mode 100644 index 0000000..81c06d4 --- /dev/null +++ b/arch/arm/plat-samsung/cpu.c @@ -0,0 +1,58 @@ +/* linux/arch/arm/plat-samsung/cpu.c + * + * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung CPU Support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +#include + +#include +#include + +unsigned long samsung_cpu_id; +static unsigned int samsung_cpu_rev; + +unsigned int samsung_rev(void) +{ + return samsung_cpu_rev; +} +EXPORT_SYMBOL(samsung_rev); + +void __init s3c24xx_init_cpu(void) +{ + /* nothing here yet */ + + samsung_cpu_rev = 0; +} + +void __init s3c64xx_init_cpu(void) +{ + samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0x118); + if (!samsung_cpu_id) { + /* + * S3C6400 has the ID register in a different place, + * and needs a write before it can be read. + */ + __raw_writel(0x0, S3C_VA_SYS + 0xA1C); + samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0xA1C); + } + + samsung_cpu_rev = 0; +} + +void __init s5p_init_cpu(void __iomem *cpuid_addr) +{ + samsung_cpu_id = __raw_readl(cpuid_addr); + samsung_cpu_rev = samsung_cpu_id & 0xFF; +} diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index bdf43ad..c22d110 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -140,6 +140,10 @@ extern void s3c64xx_init_io(struct map_desc *mach_desc, int size); extern void s5p_init_io(struct map_desc *mach_desc, int size, void __iomem *cpuid_addr); +extern void s3c24xx_init_cpu(void); +extern void s3c64xx_init_cpu(void); +extern void s5p_init_cpu(void __iomem *cpuid_addr); + extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); extern void s3c24xx_init_clocks(int xtal); diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c index 40b1228..79d10fc 100644 --- a/arch/arm/plat-samsung/init.c +++ b/arch/arm/plat-samsung/init.c @@ -30,7 +30,6 @@ #include static struct cpu_table *cpu; -unsigned long samsung_cpu_id; static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode, struct cpu_table *tab, -- cgit v0.10.2 From 56b209227a87b718450e917df904e627ddfca146 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Sat, 20 Aug 2011 13:41:21 +0900 Subject: ARM: EXYNOS4: Use samsung_rev() to distinguish silicon revision This patch uses samsung_rev() to support variable silicon revision of EXYNOS4210 so that can support for EXYNOS4210 REV0, REV1.0 and REV1.1. Note: Need to change timer setting on REV0. Acked-by: Changhwan Youn Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index 2d8a40c..dbc358d 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c @@ -43,11 +43,6 @@ static struct map_desc exynos4_iodesc[] __initdata = { .length = SZ_4K, .type = MT_DEVICE, }, { - .virtual = (unsigned long)S5P_VA_SYSRAM, - .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM), - .length = SZ_4K, - .type = MT_DEVICE, - }, { .virtual = (unsigned long)S5P_VA_CMU, .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), .length = SZ_128K, @@ -120,6 +115,24 @@ static struct map_desc exynos4_iodesc[] __initdata = { }, }; +static struct map_desc exynos4_iodesc0[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSRAM, + .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +static struct map_desc exynos4_iodesc1[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSRAM, + .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + static void exynos4_idle(void) { if (!need_resched()) @@ -137,6 +150,11 @@ void __init exynos4_map_io(void) { iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); + if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0) + iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0)); + else + iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1)); + /* initialize device information early */ exynos4_default_sdhci0(); exynos4_default_sdhci1(); diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h index d32296d..7073ac7 100644 --- a/arch/arm/mach-exynos4/include/mach/map.h +++ b/arch/arm/mach-exynos4/include/mach/map.h @@ -23,7 +23,8 @@ #include -#define EXYNOS4_PA_SYSRAM 0x02020000 +#define EXYNOS4_PA_SYSRAM0 0x02025000 +#define EXYNOS4_PA_SYSRAM1 0x02020000 #define EXYNOS4_PA_FIMC0 0x11800000 #define EXYNOS4_PA_FIMC1 0x11810000 diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c index 7c2282c..96cc651 100644 --- a/arch/arm/mach-exynos4/platsmp.c +++ b/arch/arm/mach-exynos4/platsmp.c @@ -30,9 +30,12 @@ #include #include +#include + extern void exynos4_secondary_startup(void); -#define CPU1_BOOT_REG S5P_VA_SYSRAM +#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ + S5P_INFORM5 : S5P_VA_SYSRAM) /* * control for which core is the next to come out of the secondary @@ -216,5 +219,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) * until it receives a soft interrupt, and then the * secondary CPU branches to this address. */ - __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM); + __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), + CPU1_BOOT_REG); } diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index c22d110..6fdd5ef 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -100,6 +100,10 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) # define soc_is_exynos4210() 0 #endif +#define EXYNOS4210_REV_0 (0x0) +#define EXYNOS4210_REV_1_0 (0x10) +#define EXYNOS4210_REV_1_1 (0x11) + #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } #ifndef MHZ @@ -144,6 +148,8 @@ extern void s3c24xx_init_cpu(void); extern void s3c64xx_init_cpu(void); extern void s5p_init_cpu(void __iomem *cpuid_addr); +extern unsigned int samsung_rev(void); + extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); extern void s3c24xx_init_clocks(int xtal); -- cgit v0.10.2 From 2747f5e56564e715810038a1a2d8f4041f866558 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 5 Sep 2011 19:11:40 +0900 Subject: ARM: SAMSUNG: Fix mask for S3C64xx CPU IDs The difference in CPU ID between S3C6400 and S3C6410 is a single bit and that bit wasn't included in the mask causing the S3C6410 to be misdetected as a S3C6400. Signed-off-by: Mark Brown [kgene.kim@samsung.com: changed the value] Signed-off-by: Kukjin Kim diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 6fdd5ef..6070c6b 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -26,7 +26,7 @@ extern unsigned long samsung_cpu_id; #define S3C6400_CPU_ID 0x36400000 #define S3C6410_CPU_ID 0x36410000 #define S3C64XX_CPU_ID (S3C6400_CPU_ID & S3C6410_CPU_ID) -#define S3C64XX_CPU_MASK 0x1FF40000 +#define S3C64XX_CPU_MASK 0xFFFFF000 #define S5P6440_CPU_ID 0x56440000 #define S5P6450_CPU_ID 0x36450000 -- cgit v0.10.2 From b02b5da4d15d7f7a250888d003121e1b5b69d00b Mon Sep 17 00:00:00 2001 From: Ajay Kumar Date: Mon, 5 Sep 2011 19:12:47 +0900 Subject: ARM: SAMSUNG: Fix mask value for S5P64X0 CPU IDs The current value for S5P64XX_CPU_MASK does not include the necessary bits, which causes detection failure. Signed-off-by: Ajay Kumar [kgene.kim@samsung.com: changed the value] Signed-off-by: Kukjin Kim diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 6070c6b..efd920e 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -30,7 +30,7 @@ extern unsigned long samsung_cpu_id; #define S5P6440_CPU_ID 0x56440000 #define S5P6450_CPU_ID 0x36450000 -#define S5P64XX_CPU_MASK 0x1FF40000 +#define S5P64XX_CPU_MASK 0xFFFFF000 #define S5PC100_CPU_ID 0x43100000 #define S5PC100_CPU_MASK 0xFFFFF000 -- cgit v0.10.2 From 82cb86548259a71c154b1c2df728d8526b79846a Mon Sep 17 00:00:00 2001 From: Josef Holzmayr Date: Tue, 2 Aug 2011 13:28:42 +0200 Subject: at91: add support for RSIs EWS board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds support for the RSI EWS machine (at91rm9200-based), machine type 1609. Includes fixes as suggested by Uwe Kleine-König and cleanups as suggested by Russell and R.Schwebel. Signed-off-by: Josef Holzmayr [nicolas.ferre@atmel.com: simplify board file header, move to at91_init_irq_default] Signed-off-by: Nicolas Ferre diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 2248467..1555c55 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -182,6 +182,11 @@ config MACH_ECO920 help Select this if you are using the eco920 board +config MACH_RSI_EWS + bool "RSI Embedded Webserver" + depends on ARCH_AT91RM9200 + help + Select this if you are using RSIs EWS board. endif # ---------------------------------------------------------- diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index bf57e8b..ecd6479 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o obj-$(CONFIG_MACH_YL9200) += board-yl-9200.o obj-$(CONFIG_MACH_CPUAT91) += board-cpuat91.o obj-$(CONFIG_MACH_ECO920) += board-eco920.o +obj-$(CONFIG_MACH_RSI_EWS) += board-rsi-ews.o # AT91SAM9260 board-specific support obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c new file mode 100644 index 0000000..e927df0 --- /dev/null +++ b/arch/arm/mach-at91/board-rsi-ews.c @@ -0,0 +1,233 @@ +/* + * board-rsi-ews.c + * + * Copyright (C) + * 2005 SAN People, + * 2008-2011 R-S-I Elektrotechnik GmbH & Co. KG + * + * Licensed under GPLv2 or later. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include + +#include "generic.h" + +static void __init rsi_ews_init_early(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); + + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB6, AT91_PIN_PB9); + + /* DBGU on ttyS0. (Rx & Tx only) */ + /* This one is for debugging */ + at91_register_uart(0, 0, 0); + + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + /* Dialin/-out modem interface */ + at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART3 on ttyS4. (Rx, Tx, RTS) */ + /* RS485 communication */ + at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_RTS); + + /* set serial console to ttyS0 (ie, DBGU) */ + at91_set_serial_console(0); +} + +/* + * Ethernet + */ +static struct at91_eth_data rsi_ews_eth_data __initdata = { + .phy_irq_pin = AT91_PIN_PC4, + .is_rmii = 1, +}; + +/* + * USB Host + */ +static struct at91_usbh_data rsi_ews_usbh_data __initdata = { + .ports = 1, +}; + +/* + * SD/MC + */ +static struct at91_mmc_data rsi_ews_mmc_data __initdata = { + .slot_b = 0, + .wire4 = 1, + .det_pin = AT91_PIN_PB27, + .wp_pin = AT91_PIN_PB29, +}; + +/* + * I2C + */ +static struct i2c_board_info rsi_ews_i2c_devices[] __initdata = { + { + I2C_BOARD_INFO("ds1337", 0x68), + }, + { + I2C_BOARD_INFO("24c01", 0x50), + } +}; + +/* + * LEDs + */ +static struct gpio_led rsi_ews_leds[] = { + { + .name = "led0", + .gpio = AT91_PIN_PB6, + .active_low = 0, + }, + { + .name = "led1", + .gpio = AT91_PIN_PB7, + .active_low = 0, + }, + { + .name = "led2", + .gpio = AT91_PIN_PB8, + .active_low = 0, + }, + { + .name = "led3", + .gpio = AT91_PIN_PB9, + .active_low = 0, + }, +}; + +/* + * DataFlash + */ +static struct spi_board_info rsi_ews_spi_devices[] = { + { /* DataFlash chip 1*/ + .modalias = "mtd_dataflash", + .chip_select = 0, + .max_speed_hz = 5 * 1000 * 1000, + }, + { /* DataFlash chip 2*/ + .modalias = "mtd_dataflash", + .chip_select = 1, + .max_speed_hz = 5 * 1000 * 1000, + }, +}; + +/* + * NOR flash + */ +static struct mtd_partition rsiews_nor_partitions[] = { + { + .name = "boot", + .offset = 0, + .size = 3 * SZ_128K, + .mask_flags = MTD_WRITEABLE + }, + { + .name = "kernel", + .offset = MTDPART_OFS_NXTBLK, + .size = SZ_2M - (3 * SZ_128K) + }, + { + .name = "root", + .offset = MTDPART_OFS_NXTBLK, + .size = SZ_8M + }, + { + .name = "kernelupd", + .offset = MTDPART_OFS_NXTBLK, + .size = 3 * SZ_512K, + .mask_flags = MTD_WRITEABLE + }, + { + .name = "rootupd", + .offset = MTDPART_OFS_NXTBLK, + .size = 9 * SZ_512K, + .mask_flags = MTD_WRITEABLE + }, +}; + +static struct physmap_flash_data rsiews_nor_data = { + .width = 2, + .parts = rsiews_nor_partitions, + .nr_parts = ARRAY_SIZE(rsiews_nor_partitions), +}; + +#define NOR_BASE AT91_CHIPSELECT_0 +#define NOR_SIZE SZ_16M + +static struct resource nor_flash_resources[] = { + { + .start = NOR_BASE, + .end = NOR_BASE + NOR_SIZE - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device rsiews_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &rsiews_nor_data, + }, + .resource = nor_flash_resources, + .num_resources = ARRAY_SIZE(nor_flash_resources), +}; + +/* + * Init Func + */ +static void __init rsi_ews_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + at91_set_gpio_output(AT91_PIN_PA21, 0); + /* Ethernet */ + at91_add_device_eth(&rsi_ews_eth_data); + /* USB Host */ + at91_add_device_usbh(&rsi_ews_usbh_data); + /* I2C */ + at91_add_device_i2c(rsi_ews_i2c_devices, + ARRAY_SIZE(rsi_ews_i2c_devices)); + /* SPI */ + at91_add_device_spi(rsi_ews_spi_devices, + ARRAY_SIZE(rsi_ews_spi_devices)); + /* MMC */ + at91_add_device_mmc(0, &rsi_ews_mmc_data); + /* NOR Flash */ + platform_device_register(&rsiews_nor_flash); + /* LEDs */ + at91_gpio_leds(rsi_ews_leds, ARRAY_SIZE(rsi_ews_leds)); +} + +MACHINE_START(RSI_EWS, "RSI EWS") + /* Maintainer: Josef Holzmayr */ + .timer = &at91rm9200_timer, + .map_io = at91_map_io, + .init_early = rsi_ews_init_early, + .init_irq = at91_init_irq_default, + .init_machine = rsi_ews_board_init, +MACHINE_END -- cgit v0.10.2 From 6939fd49787e233fd0d7640a4de72815bc8c649a Mon Sep 17 00:00:00 2001 From: Nico Erfurth Date: Tue, 30 Aug 2011 18:25:52 +0200 Subject: at91: merge board USB-A9260 and USB-A9263 together Merge boards together as they are barely the same. Signed-off-by: Nico Erfurth Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD [nicolas.ferre@atmel.com: updated to new machine_desc structure] Signed-off-by: Nicolas Ferre Cc: Gregory Hermant diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index ecd6479..0b1b379 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -42,7 +42,7 @@ obj-$(CONFIG_MACH_RSI_EWS) += board-rsi-ews.o obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o obj-$(CONFIG_MACH_CAM60) += board-cam60.o obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o -obj-$(CONFIG_MACH_USB_A9260) += board-usb-a9260.o +obj-$(CONFIG_MACH_USB_A9260) += board-usb-a926x.o obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o obj-$(CONFIG_MACH_AFEB9260) += board-afeb-9260v1.o obj-$(CONFIG_MACH_CPU9260) += board-cpu9krea.o @@ -54,7 +54,7 @@ obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o # AT91SAM9263 board-specific support obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o -obj-$(CONFIG_MACH_USB_A9263) += board-usb-a9263.o +obj-$(CONFIG_MACH_USB_A9263) += board-usb-a926x.o obj-$(CONFIG_MACH_NEOCORE926) += board-neocore926.o # AT91SAM9RL board-specific support diff --git a/arch/arm/mach-at91/board-usb-a9260.c b/arch/arm/mach-at91/board-usb-a9260.c deleted file mode 100644 index 8c4c1a0..0000000 --- a/arch/arm/mach-at91/board-usb-a9260.c +++ /dev/null @@ -1,230 +0,0 @@ -/* - * linux/arch/arm/mach-at91/board-usb-a9260.c - * - * Copyright (C) 2005 SAN People - * Copyright (C) 2006 Atmel - * Copyright (C) 2007 Calao-systems - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "sam9_smc.h" -#include "generic.h" - - -static void __init ek_init_early(void) -{ - /* Initialize processor: 12.000 MHz crystal */ - at91_initialize(12000000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); -} - -/* - * USB Host port - */ -static struct at91_usbh_data __initdata ek_usbh_data = { - .ports = 2, -}; - -/* - * USB Device port - */ -static struct at91_udc_data __initdata ek_udc_data = { - .vbus_pin = AT91_PIN_PC5, - .pullup_pin = 0, /* pull-up driven by UDC */ -}; - -/* - * MACB Ethernet device - */ -static struct at91_eth_data __initdata ek_macb_data = { - .phy_irq_pin = AT91_PIN_PA31, - .is_rmii = 1, -}; - -/* - * NAND flash - */ -static struct mtd_partition __initdata ek_nand_partition[] = { - { - .name = "Uboot & Kernel", - .offset = 0, - .size = SZ_16M, - }, - { - .name = "Root FS", - .offset = MTDPART_OFS_NXTBLK, - .size = 120 * SZ_1M, - }, - { - .name = "FS", - .offset = MTDPART_OFS_NXTBLK, - .size = 120 * SZ_1M, - } -}; - -static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) -{ - *num_partitions = ARRAY_SIZE(ek_nand_partition); - return ek_nand_partition; -} - -static struct atmel_nand_data __initdata ek_nand_data = { - .ale = 21, - .cle = 22, -// .det_pin = ... not connected - .rdy_pin = AT91_PIN_PC13, - .enable_pin = AT91_PIN_PC14, - .partition_info = nand_partitions, -}; - -static struct sam9_smc_config __initdata ek_nand_smc_config = { - .ncs_read_setup = 0, - .nrd_setup = 1, - .ncs_write_setup = 0, - .nwe_setup = 1, - - .ncs_read_pulse = 3, - .nrd_pulse = 3, - .ncs_write_pulse = 3, - .nwe_pulse = 3, - - .read_cycle = 5, - .write_cycle = 5, - - .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, - .tdf_cycles = 2, -}; - -static void __init ek_add_device_nand(void) -{ - /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &ek_nand_smc_config); - - at91_add_device_nand(&ek_nand_data); -} - -/* - * GPIO Buttons - */ - -#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) -static struct gpio_keys_button ek_buttons[] = { - { /* USER PUSH BUTTON */ - .code = KEY_ENTER, - .gpio = AT91_PIN_PB10, - .active_low = 1, - .desc = "user_pb", - .wakeup = 1, - } -}; - -static struct gpio_keys_platform_data ek_button_data = { - .buttons = ek_buttons, - .nbuttons = ARRAY_SIZE(ek_buttons), -}; - -static struct platform_device ek_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &ek_button_data, - } -}; - -static void __init ek_add_device_buttons(void) -{ - at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */ - at91_set_deglitch(AT91_PIN_PB10, 1); - - platform_device_register(&ek_button_device); -} -#else -static void __init ek_add_device_buttons(void) {} -#endif - -/* - * LEDs - */ -static struct gpio_led ek_leds[] = { - { /* user_led (green) */ - .name = "user_led", - .gpio = AT91_PIN_PB21, - .active_low = 0, - .default_trigger = "heartbeat", - } -}; - -static void __init ek_board_init(void) -{ - /* Serial */ - at91_add_device_serial(); - /* USB Host */ - at91_add_device_usbh(&ek_usbh_data); - /* USB Device */ - at91_add_device_udc(&ek_udc_data); - /* NAND */ - ek_add_device_nand(); - /* I2C */ - at91_add_device_i2c(NULL, 0); - /* Ethernet */ - at91_add_device_eth(&ek_macb_data); - /* Push Buttons */ - ek_add_device_buttons(); - /* LEDs */ - at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); - /* shutdown controller, wakeup button (5 msec low) */ - at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW - | AT91_SHDW_RTTWKEN); -} - -MACHINE_START(USB_A9260, "CALAO USB_A9260") - /* Maintainer: calao-systems */ - .timer = &at91sam926x_timer, - .map_io = at91_map_io, - .init_early = ek_init_early, - .init_irq = at91_init_irq_default, - .init_machine = ek_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91/board-usb-a9263.c b/arch/arm/mach-at91/board-usb-a9263.c deleted file mode 100644 index 25e7937..0000000 --- a/arch/arm/mach-at91/board-usb-a9263.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - * linux/arch/arm/mach-at91/board-usb-a9263.c - * - * Copyright (C) 2005 SAN People - * Copyright (C) 2007 Atmel Corporation. - * Copyright (C) 2007 Calao-systems - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "sam9_smc.h" -#include "generic.h" - - -static void __init ek_init_early(void) -{ - /* Initialize processor: 12.00 MHz crystal */ - at91_initialize(12000000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); -} - -/* - * USB Host port - */ -static struct at91_usbh_data __initdata ek_usbh_data = { - .ports = 2, -}; - -/* - * USB Device port - */ -static struct at91_udc_data __initdata ek_udc_data = { - .vbus_pin = AT91_PIN_PB11, - .pullup_pin = 0, /* pull-up driven by UDC */ -}; - -/* - * SPI devices. - */ -static struct spi_board_info ek_spi_devices[] = { -#if !defined(CONFIG_MMC_AT91) - { /* DataFlash chip */ - .modalias = "mtd_dataflash", - .chip_select = 0, - .max_speed_hz = 15 * 1000 * 1000, - .bus_num = 0, - } -#endif -}; - -/* - * MACB Ethernet device - */ -static struct at91_eth_data __initdata ek_macb_data = { - .phy_irq_pin = AT91_PIN_PE31, - .is_rmii = 1, -}; - -/* - * NAND flash - */ -static struct mtd_partition __initdata ek_nand_partition[] = { - { - .name = "Linux Kernel", - .offset = 0, - .size = SZ_16M, - }, - { - .name = "Root FS", - .offset = MTDPART_OFS_NXTBLK, - .size = 120 * SZ_1M, - }, - { - .name = "FS", - .offset = MTDPART_OFS_NXTBLK, - .size = 120 * SZ_1M, - } -}; - -static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) -{ - *num_partitions = ARRAY_SIZE(ek_nand_partition); - return ek_nand_partition; -} - -static struct atmel_nand_data __initdata ek_nand_data = { - .ale = 21, - .cle = 22, -// .det_pin = ... not connected - .rdy_pin = AT91_PIN_PA22, - .enable_pin = AT91_PIN_PD15, - .partition_info = nand_partitions, -}; - -static struct sam9_smc_config __initdata ek_nand_smc_config = { - .ncs_read_setup = 0, - .nrd_setup = 1, - .ncs_write_setup = 0, - .nwe_setup = 1, - - .ncs_read_pulse = 3, - .nrd_pulse = 3, - .ncs_write_pulse = 3, - .nwe_pulse = 3, - - .read_cycle = 5, - .write_cycle = 5, - - .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, - .tdf_cycles = 2, -}; - -static void __init ek_add_device_nand(void) -{ - /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &ek_nand_smc_config); - - at91_add_device_nand(&ek_nand_data); -} - - -/* - * GPIO Buttons - */ -#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) -static struct gpio_keys_button ek_buttons[] = { - { /* USER PUSH BUTTON */ - .code = KEY_ENTER, - .gpio = AT91_PIN_PB10, - .active_low = 1, - .desc = "user_pb", - .wakeup = 1, - } -}; - -static struct gpio_keys_platform_data ek_button_data = { - .buttons = ek_buttons, - .nbuttons = ARRAY_SIZE(ek_buttons), -}; - -static struct platform_device ek_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &ek_button_data, - } -}; - -static void __init ek_add_device_buttons(void) -{ - at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */ - at91_set_deglitch(AT91_PIN_PB10, 1); - - platform_device_register(&ek_button_device); -} -#else -static void __init ek_add_device_buttons(void) {} -#endif - -/* - * LEDs - */ -static struct gpio_led ek_leds[] = { - { /* user_led (green) */ - .name = "user_led", - .gpio = AT91_PIN_PB21, - .active_low = 1, - .default_trigger = "heartbeat", - } -}; - - -static void __init ek_board_init(void) -{ - /* Serial */ - at91_add_device_serial(); - /* USB Host */ - at91_add_device_usbh(&ek_usbh_data); - /* USB Device */ - at91_add_device_udc(&ek_udc_data); - /* SPI */ - at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); - /* Ethernet */ - at91_add_device_eth(&ek_macb_data); - /* NAND */ - ek_add_device_nand(); - /* I2C */ - at91_add_device_i2c(NULL, 0); - /* Push Buttons */ - ek_add_device_buttons(); - /* LEDs */ - at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); - /* shutdown controller, wakeup button (5 msec low) */ - at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW - | AT91_SHDW_RTTWKEN); -} - -MACHINE_START(USB_A9263, "CALAO USB_A9263") - /* Maintainer: calao-systems */ - .timer = &at91sam926x_timer, - .map_io = at91_map_io, - .init_early = ek_init_early, - .init_irq = at91_init_irq_default, - .init_machine = ek_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c new file mode 100644 index 0000000..b9b9847 --- /dev/null +++ b/arch/arm/mach-at91/board-usb-a926x.c @@ -0,0 +1,290 @@ +/* + * linux/arch/arm/mach-at91/board-usb-a926x.c + * + * Copyright (C) 2005 SAN People + * Copyright (C) 2007 Atmel Corporation. + * Copyright (C) 2007 Calao-systems + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "sam9_smc.h" +#include "generic.h" + + +static void __init ek_init_early(void) +{ + /* Initialize processor: 12.00 MHz crystal */ + at91_initialize(12000000); + + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* set serial console to ttyS0 (ie, DBGU) */ + at91_set_serial_console(0); +} + +/* + * USB Host port + */ +static struct at91_usbh_data __initdata ek_usbh_data = { + .ports = 2, +}; + +/* + * USB Device port + */ +static struct at91_udc_data __initdata ek_udc_data = { + .vbus_pin = AT91_PIN_PB11, + .pullup_pin = 0, /* pull-up driven by UDC */ +}; + +void ek_add_device_udc(void) +{ + if (machine_is_usb_a9260()) + ek_udc_data.vbus_pin = AT91_PIN_PC5; + + at91_add_device_udc(&ek_udc_data); +} + +/* + * SPI devices. + */ +static struct spi_board_info ek_spi_devices[] = { +#if !defined(CONFIG_MMC_AT91) + { /* DataFlash chip */ + .modalias = "mtd_dataflash", + .chip_select = 0, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + } +#endif +}; + +void ek_add_device_spi(void) +{ + if (machine_is_usb_a9263()) + at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); +} + +/* + * MACB Ethernet device + */ +static struct at91_eth_data __initdata ek_macb_data = { + .phy_irq_pin = AT91_PIN_PE31, + .is_rmii = 1, +}; + +void ek_add_device_eth(void) +{ + if (machine_is_usb_a9260()) + ek_macb_data.phy_irq_pin = AT91_PIN_PA31; + + at91_add_device_eth(&ek_macb_data); +} + +/* + * NAND flash + */ +static struct mtd_partition __initdata ek_nand_partition[] = { + { + .name = "Uboot & Kernel", + .offset = 0, + .size = SZ_16M, + }, + { + .name = "Root FS", + .offset = MTDPART_OFS_NXTBLK, + .size = 120 * SZ_1M, + }, + { + .name = "FS", + .offset = MTDPART_OFS_NXTBLK, + .size = 120 * SZ_1M, + } +}; + +static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) +{ + *num_partitions = ARRAY_SIZE(ek_nand_partition); + return ek_nand_partition; +} + +static struct atmel_nand_data __initdata ek_nand_data = { + .ale = 21, + .cle = 22, +// .det_pin = ... not connected + .rdy_pin = AT91_PIN_PA22, + .enable_pin = AT91_PIN_PD15, + .partition_info = nand_partitions, +}; + +static struct sam9_smc_config __initdata ek_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 2, +}; + +static void __init ek_add_device_nand(void) +{ + if (machine_is_usb_a9260()) { + ek_nand_data.rdy_pin = AT91_PIN_PC13; + ek_nand_data.enable_pin = AT91_PIN_PC14; + } + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &ek_nand_smc_config); + + at91_add_device_nand(&ek_nand_data); +} + + +/* + * GPIO Buttons + */ +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +static struct gpio_keys_button ek_buttons[] = { + { /* USER PUSH BUTTON */ + .code = KEY_ENTER, + .gpio = AT91_PIN_PB10, + .active_low = 1, + .desc = "user_pb", + .wakeup = 1, + } +}; + +static struct gpio_keys_platform_data ek_button_data = { + .buttons = ek_buttons, + .nbuttons = ARRAY_SIZE(ek_buttons), +}; + +static struct platform_device ek_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &ek_button_data, + } +}; + +static void __init ek_add_device_buttons(void) +{ + at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */ + at91_set_deglitch(AT91_PIN_PB10, 1); + + platform_device_register(&ek_button_device); +} +#else +static void __init ek_add_device_buttons(void) {} +#endif + +/* + * LEDs + */ +static struct gpio_led ek_leds[] = { + { /* user_led (green) */ + .name = "user_led", + .gpio = AT91_PIN_PB21, + .active_low = 1, + .default_trigger = "heartbeat", + } +}; + +void ek_add_device_leds(void) +{ + if (machine_is_usb_a9260()) + ek_leds[0].active_low = 0; + + at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); +} + + +static void __init ek_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&ek_usbh_data); + /* USB Device */ + ek_add_device_udc(); + /* SPI */ + ek_add_device_spi(); + /* Ethernet */ + ek_add_device_eth(); + /* NAND */ + ek_add_device_nand(); + /* I2C */ + at91_add_device_i2c(NULL, 0); + /* Push Buttons */ + ek_add_device_buttons(); + /* LEDs */ + ek_add_device_leds(); + /* shutdown controller, wakeup button (5 msec low) */ + at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW + | AT91_SHDW_RTTWKEN); +} + +MACHINE_START(USB_A9263, "CALAO USB_A9263") + /* Maintainer: calao-systems */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, + .init_early = ek_init_early, + .init_irq = at91_init_irq_default, + .init_machine = ek_board_init, +MACHINE_END + +MACHINE_START(USB_A9260, "CALAO USB_A9260") + /* Maintainer: calao-systems */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, + .init_early = ek_init_early, + .init_irq = at91_init_irq_default, + .init_machine = ek_board_init, +MACHINE_END -- cgit v0.10.2 From 0a072a247fa79979dd31813decb6b118d7d511fd Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 30 Aug 2011 18:25:53 +0200 Subject: at91: USB-A9G20 C01 & C11 board support Add support for Calao USB-A9G20 boards. It will be integrated in existing support for board of same form factor using at91sam9260 or at91sam9263. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nicolas Ferre diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 1555c55..04a85c5 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -386,6 +386,14 @@ config MACH_GSIA18S This enables support for the GS_IA18_S board produced by GeoSIG Ltd company. This is an internet accelerograph. + +config MACH_USB_A9G20 + bool "CALAO USB-A9G20" + depends on ARCH_AT91SAM9G20 + help + Select this if you are using a Calao Systems USB-A9G20. + + endif if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 0b1b379..d992dd5 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -68,6 +68,7 @@ obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o obj-$(CONFIG_MACH_GSIA18S) += board-gsia18s.o board-stamp9g20.o +obj-$(CONFIG_MACH_USB_A9G20) += board-usb-a926x.o # AT91SAM9260/AT91SAM9G20 board-specific support obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c index b9b9847..260260b 100644 --- a/arch/arm/mach-at91/board-usb-a926x.c +++ b/arch/arm/mach-at91/board-usb-a926x.c @@ -4,6 +4,7 @@ * Copyright (C) 2005 SAN People * Copyright (C) 2007 Atmel Corporation. * Copyright (C) 2007 Calao-systems + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,6 +29,7 @@ #include #include #include +#include #include #include @@ -74,18 +76,42 @@ static struct at91_udc_data __initdata ek_udc_data = { .pullup_pin = 0, /* pull-up driven by UDC */ }; -void ek_add_device_udc(void) +static void __init ek_add_device_udc(void) { - if (machine_is_usb_a9260()) + if (machine_is_usb_a9260() || machine_is_usb_a9g20()) ek_udc_data.vbus_pin = AT91_PIN_PC5; at91_add_device_udc(&ek_udc_data); } +#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) +#define MMC_SPI_CARD_DETECT_INT AT91_PIN_PC4 +static int at91_mmc_spi_init(struct device *dev, + irqreturn_t (*detect_int)(int, void *), void *data) +{ + /* Configure Interrupt pin as input, no pull-up */ + at91_set_gpio_input(MMC_SPI_CARD_DETECT_INT, 0); + return request_irq(gpio_to_irq(MMC_SPI_CARD_DETECT_INT), detect_int, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, + "mmc-spi-detect", data); +} + +static void at91_mmc_spi_exit(struct device *dev, void *data) +{ + free_irq(gpio_to_irq(MMC_SPI_CARD_DETECT_INT), data); +} + +static struct mmc_spi_platform_data at91_mmc_spi_pdata = { + .init = at91_mmc_spi_init, + .exit = at91_mmc_spi_exit, + .detect_delay = 100, /* msecs */ +}; +#endif + /* * SPI devices. */ -static struct spi_board_info ek_spi_devices[] = { +static struct spi_board_info usb_a9263_spi_devices[] = { #if !defined(CONFIG_MMC_AT91) { /* DataFlash chip */ .modalias = "mtd_dataflash", @@ -96,10 +122,25 @@ static struct spi_board_info ek_spi_devices[] = { #endif }; -void ek_add_device_spi(void) +static struct spi_board_info usb_a9g20_spi_devices[] = { +#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) + { + .modalias = "mmc_spi", + .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 1, + .chip_select = 0, + .platform_data = &at91_mmc_spi_pdata, + .mode = SPI_MODE_3, + }, +#endif +}; + +static void __init ek_add_device_spi(void) { if (machine_is_usb_a9263()) - at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); + at91_add_device_spi(usb_a9263_spi_devices, ARRAY_SIZE(usb_a9263_spi_devices)); + else if (machine_is_usb_a9g20()) + at91_add_device_spi(usb_a9g20_spi_devices, ARRAY_SIZE(usb_a9g20_spi_devices)); } /* @@ -110,9 +151,9 @@ static struct at91_eth_data __initdata ek_macb_data = { .is_rmii = 1, }; -void ek_add_device_eth(void) +static void __init ek_add_device_eth(void) { - if (machine_is_usb_a9260()) + if (machine_is_usb_a9260() || machine_is_usb_a9g20()) ek_macb_data.phy_irq_pin = AT91_PIN_PA31; at91_add_device_eth(&ek_macb_data); @@ -123,19 +164,29 @@ void ek_add_device_eth(void) */ static struct mtd_partition __initdata ek_nand_partition[] = { { - .name = "Uboot & Kernel", + .name = "barebox", .offset = 0, - .size = SZ_16M, - }, - { - .name = "Root FS", + .size = 3 * SZ_128K, + }, { + .name = "bareboxenv", .offset = MTDPART_OFS_NXTBLK, - .size = 120 * SZ_1M, - }, - { - .name = "FS", + .size = SZ_128K, + }, { + .name = "bareboxenv2", + .offset = MTDPART_OFS_NXTBLK, + .size = SZ_128K, + }, { + .name = "kernel", + .offset = MTDPART_OFS_NXTBLK, + .size = 4 * SZ_1M, + }, { + .name = "rootfs", .offset = MTDPART_OFS_NXTBLK, .size = 120 * SZ_1M, + }, { + .name = "data", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, } }; @@ -154,7 +205,7 @@ static struct atmel_nand_data __initdata ek_nand_data = { .partition_info = nand_partitions, }; -static struct sam9_smc_config __initdata ek_nand_smc_config = { +static struct sam9_smc_config __initdata usb_a9260_nand_smc_config = { .ncs_read_setup = 0, .nrd_setup = 1, .ncs_write_setup = 0, @@ -172,15 +223,36 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = { .tdf_cycles = 2, }; +static struct sam9_smc_config __initdata usb_a9g20_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 2, + .ncs_write_setup = 0, + .nwe_setup = 2, + + .ncs_read_pulse = 4, + .nrd_pulse = 4, + .ncs_write_pulse = 4, + .nwe_pulse = 4, + + .read_cycle = 7, + .write_cycle = 7, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 3, +}; + static void __init ek_add_device_nand(void) { - if (machine_is_usb_a9260()) { + if (machine_is_usb_a9260() || machine_is_usb_a9g20()) { ek_nand_data.rdy_pin = AT91_PIN_PC13; ek_nand_data.enable_pin = AT91_PIN_PC14; } /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &ek_nand_smc_config); + if (machine_is_usb_a9g20()) + sam9_smc_configure(3, &usb_a9g20_nand_smc_config); + else + sam9_smc_configure(3, &usb_a9260_nand_smc_config); at91_add_device_nand(&ek_nand_data); } @@ -237,15 +309,20 @@ static struct gpio_led ek_leds[] = { } }; -void ek_add_device_leds(void) +static struct i2c_board_info __initdata ek_i2c_devices[] = { + { + I2C_BOARD_INFO("rv3029c2", 0x56), + }, +}; + +static void __init ek_add_device_leds(void) { - if (machine_is_usb_a9260()) + if (machine_is_usb_a9260() || machine_is_usb_a9g20()) ek_leds[0].active_low = 0; at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); } - static void __init ek_board_init(void) { /* Serial */ @@ -260,15 +337,22 @@ static void __init ek_board_init(void) ek_add_device_eth(); /* NAND */ ek_add_device_nand(); - /* I2C */ - at91_add_device_i2c(NULL, 0); /* Push Buttons */ ek_add_device_buttons(); /* LEDs */ ek_add_device_leds(); - /* shutdown controller, wakeup button (5 msec low) */ - at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW + + if (machine_is_usb_a9g20()) { + /* I2C */ + at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices)); + } else { + /* I2C */ + at91_add_device_i2c(NULL, 0); + /* shutdown controller, wakeup button (5 msec low) */ + at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) + | AT91_SHDW_WKMODE0_LOW | AT91_SHDW_RTTWKEN); + } } MACHINE_START(USB_A9263, "CALAO USB_A9263") @@ -288,3 +372,12 @@ MACHINE_START(USB_A9260, "CALAO USB_A9260") .init_irq = at91_init_irq_default, .init_machine = ek_board_init, MACHINE_END + +MACHINE_START(USB_A9G20, "CALAO USB_A92G0") + /* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, + .init_early = ek_init_early, + .init_irq = at91_init_irq_default, + .init_machine = ek_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h index 31ac2d9..85820ad 100644 --- a/arch/arm/mach-at91/include/mach/timex.h +++ b/arch/arm/mach-at91/include/mach/timex.h @@ -64,7 +64,12 @@ #elif defined(CONFIG_ARCH_AT91SAM9G20) +#if defined(CONFIG_MACH_USB_A9G20) +#define AT91SAM9_MASTER_CLOCK 133000000 +#else #define AT91SAM9_MASTER_CLOCK 132096000 +#endif + #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) #elif defined(CONFIG_ARCH_AT91SAM9G45) -- cgit v0.10.2 From 684653842b65b98538e5d6198998e68c879bd45e Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Wed, 24 Aug 2011 17:25:09 +0900 Subject: ARM: EXYNOS4: Add support new EXYNOS4212 SoC This patch adds Samsung EXYNOS4212 SoC support. The EXYNOS4212 integrates a ARM Cortex A9 multi-core. Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig index bee8f77..0b40289 100644 --- a/arch/arm/mach-exynos4/Kconfig +++ b/arch/arm/mach-exynos4/Kconfig @@ -15,6 +15,11 @@ config CPU_EXYNOS4210 help Enable EXYNOS4210 CPU support +config SOC_EXYNOS4212 + bool + help + Enable EXYNOS4212 SoC support + config EXYNOS4_MCT bool default y diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile index e3e93ea..4624457 100644 --- a/arch/arm/mach-exynos4/Makefile +++ b/arch/arm/mach-exynos4/Makefile @@ -12,8 +12,10 @@ obj- := # Core support for EXYNOS4 system -obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o -obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o +obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o +obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o irq-eint.o dma.o pmu.o +obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o +obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o obj-$(CONFIG_PM) += pm.o sleep.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index 0d281bb..1e1a7a9 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c @@ -241,7 +241,11 @@ static int __init exynos4_l2x0_cache_init(void) { /* TAG, Data Latency Control: 2cycle */ __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); - __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); + + if (soc_is_exynos4210()) + __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); + else if (soc_is_exynos4212()) + __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); /* L2X0 Prefetch Control */ __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c index 04392c7..909507b 100644 --- a/arch/arm/plat-s5p/cpu.c +++ b/arch/arm/plat-s5p/cpu.c @@ -33,6 +33,7 @@ static const char name_s5p6450[] = "S5P6450"; static const char name_s5pc100[] = "S5PC100"; static const char name_s5pv210[] = "S5PV210/S5PC110"; static const char name_exynos4210[] = "EXYNOS4210"; +static const char name_exynos4212[] = "EXYNOS4212"; static struct cpu_table cpu_ids[] __initdata = { { @@ -75,6 +76,14 @@ static struct cpu_table cpu_ids[] __initdata = { .init_uarts = exynos4_init_uarts, .init = exynos4_init, .name = name_exynos4210, + }, { + .idcode = EXYNOS4212_CPU_ID, + .idmask = EXYNOS4_CPU_MASK, + .map_io = exynos4_map_io, + .init_clocks = exynos4_init_clocks, + .init_uarts = exynos4_init_uarts, + .init = exynos4_init, + .name = name_exynos4212, }, }; diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-s5p/include/plat/exynos4.h index 907caab..4aed130 100644 --- a/arch/arm/plat-s5p/include/plat/exynos4.h +++ b/arch/arm/plat-s5p/include/plat/exynos4.h @@ -16,8 +16,7 @@ extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); extern void exynos4_register_clocks(void); extern void exynos4_setup_clocks(void); -#ifdef CONFIG_CPU_EXYNOS4210 - +#ifdef CONFIG_ARCH_EXYNOS4 extern int exynos4_init(void); extern void exynos4_init_irq(void); extern void exynos4_map_io(void); diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index efd920e..1bbbbb4 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -39,6 +39,7 @@ extern unsigned long samsung_cpu_id; #define S5PV210_CPU_MASK 0xFFFFF000 #define EXYNOS4210_CPU_ID 0x43210000 +#define EXYNOS4212_CPU_ID 0x43220000 #define EXYNOS4_CPU_MASK 0xFFFE0000 #define IS_SAMSUNG_CPU(name, id, mask) \ @@ -54,6 +55,7 @@ IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK) IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK) IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK) IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) +IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \ @@ -100,6 +102,12 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) # define soc_is_exynos4210() 0 #endif +#if defined(CONFIG_SOC_EXYNOS4212) +# define soc_is_exynos4212() is_samsung_exynos4212() +#else +# define soc_is_exynos4212() 0 +#endif + #define EXYNOS4210_REV_0 (0x0) #define EXYNOS4210_REV_1_0 (0x10) #define EXYNOS4210_REV_1_1 (0x11) -- cgit v0.10.2 From 2bc02c0daae146283ce1b20da6864a27c848812e Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Wed, 24 Aug 2011 17:25:09 +0900 Subject: ARM: EXYNOS4: Add support clock for EXYNOS4212 This patch splits EXYNOS4 clock code to EXYNOS4 common, EXYNOS4210 and EXYNOS4212 for supporting new EXYNOS4212 SoC with one kernel image. Of course, this patch adds some clock codes for EXYNOS4212 SoC. Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-exynos4/clock-exynos4210.c new file mode 100644 index 0000000..fe74b91 --- /dev/null +++ b/arch/arm/mach-exynos4/clock-exynos4210.c @@ -0,0 +1,101 @@ +/* + * linux/arch/arm/mach-exynos4/clock-exynos4210.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4210 - Clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static struct clksrc_clk *sysclks[] = { + /* nothing here yet */ +}; + +static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable); +} + +static struct clksrc_clk clksrcs[] = { + { + .clk = { + .name = "sclk_sata", + .id = -1, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &clkset_mout_corebus, + .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 }, + .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimd", + .devname = "exynos4-fb.1", + .enable = exynos4_clksrc_mask_lcd1_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 }, + }, +}; + +static struct clk init_clocks_off[] = { + { + .name = "sataphy", + .id = -1, + .parent = &clk_aclk_133.clk, + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "sata", + .id = -1, + .parent = &clk_aclk_133.clk, + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 10), + }, { + .name = "fimd", + .devname = "exynos4-fb.1", + .enable = exynos4_clk_ip_lcd1_ctrl, + .ctrlbit = (1 << 0), + }, +}; + +void __init exynos4210_register_clocks(void) +{ + int ptr; + + clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU; + clk_mout_mpll.reg_src.shift = 8; + clk_mout_mpll.reg_src.size = 1; + + for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) + s3c_register_clksrc(sysclks[ptr], 1); + + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); + + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); +} diff --git a/arch/arm/mach-exynos4/clock-exynos4212.c b/arch/arm/mach-exynos4/clock-exynos4212.c new file mode 100644 index 0000000..5a47a3f --- /dev/null +++ b/arch/arm/mach-exynos4/clock-exynos4212.c @@ -0,0 +1,84 @@ +/* + * linux/arch/arm/mach-exynos4/clock-exynos4212.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4212 - Clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static struct clk *clk_src_mpll_user_list[] = { + [0] = &clk_fin_mpll, + [1] = &clk_mout_mpll.clk, +}; + +static struct clksrc_sources clk_src_mpll_user = { + .sources = clk_src_mpll_user_list, + .nr_sources = ARRAY_SIZE(clk_src_mpll_user_list), +}; + +static struct clksrc_clk clk_mout_mpll_user = { + .clk = { + .name = "mout_mpll_user", + }, + .sources = &clk_src_mpll_user, + .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 }, +}; + +static struct clksrc_clk *sysclks[] = { + &clk_mout_mpll_user, +}; + +static struct clksrc_clk clksrcs[] = { + /* nothing here yet */ +}; + +static struct clk init_clocks_off[] = { + /* nothing here yet */ +}; + +void __init exynos4212_register_clocks(void) +{ + int ptr; + + /* usbphy1 is removed */ + clkset_group_list[4] = NULL; + + /* mout_mpll_user is used */ + clkset_group_list[6] = &clk_mout_mpll_user.clk; + clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk; + + clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC; + clk_mout_mpll.reg_src.shift = 12; + clk_mout_mpll.reg_src.size = 1; + + for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) + s3c_register_clksrc(sysclks[ptr], 1); + + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); + + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); +} diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index 79d6cd0..eb99467 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c @@ -20,26 +20,28 @@ #include #include #include +#include #include #include #include +#include -static struct clk clk_sclk_hdmi27m = { +struct clk clk_sclk_hdmi27m = { .name = "sclk_hdmi27m", .rate = 27000000, }; -static struct clk clk_sclk_hdmiphy = { +struct clk clk_sclk_hdmiphy = { .name = "sclk_hdmiphy", }; -static struct clk clk_sclk_usbphy0 = { +struct clk clk_sclk_usbphy0 = { .name = "sclk_usbphy0", .rate = 27000000, }; -static struct clk clk_sclk_usbphy1 = { +struct clk clk_sclk_usbphy1 = { .name = "sclk_usbphy1", }; @@ -58,12 +60,7 @@ static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable); } -static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable); -} - -static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) +int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable); } @@ -103,12 +100,12 @@ static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable); } -static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable) +int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable); } -static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable) +int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable); } @@ -133,7 +130,7 @@ static struct clksrc_clk clk_mout_apll = { .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, }; -static struct clksrc_clk clk_sclk_apll = { +struct clksrc_clk clk_sclk_apll = { .clk = { .name = "sclk_apll", .parent = &clk_mout_apll.clk, @@ -141,7 +138,7 @@ static struct clksrc_clk clk_sclk_apll = { .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, }; -static struct clksrc_clk clk_mout_epll = { +struct clksrc_clk clk_mout_epll = { .clk = { .name = "mout_epll", }, @@ -149,12 +146,13 @@ static struct clksrc_clk clk_mout_epll = { .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, }; -static struct clksrc_clk clk_mout_mpll = { +struct clksrc_clk clk_mout_mpll = { .clk = { .name = "mout_mpll", }, .sources = &clk_src_mpll, - .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, + + /* reg_src will be added in each SoCs' clock */ }; static struct clk *clkset_moutcore_list[] = { @@ -224,12 +222,12 @@ static struct clksrc_clk clk_periphclk = { /* Core list of CMU_CORE side */ -static struct clk *clkset_corebus_list[] = { +struct clk *clkset_corebus_list[] = { [0] = &clk_mout_mpll.clk, [1] = &clk_sclk_apll.clk, }; -static struct clksrc_sources clkset_mout_corebus = { +struct clksrc_sources clkset_mout_corebus = { .sources = clkset_corebus_list, .nr_sources = ARRAY_SIZE(clkset_corebus_list), }; @@ -284,12 +282,12 @@ static struct clksrc_clk clk_pclk_acp = { /* Core list of CMU_TOP side */ -static struct clk *clkset_aclk_top_list[] = { +struct clk *clkset_aclk_top_list[] = { [0] = &clk_mout_mpll.clk, [1] = &clk_sclk_apll.clk, }; -static struct clksrc_sources clkset_aclk = { +struct clksrc_sources clkset_aclk = { .sources = clkset_aclk_top_list, .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), }; @@ -321,7 +319,7 @@ static struct clksrc_clk clk_aclk_160 = { .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 }, }; -static struct clksrc_clk clk_aclk_133 = { +struct clksrc_clk clk_aclk_133 = { .clk = { .name = "aclk_133", }, @@ -360,7 +358,7 @@ static struct clksrc_sources clkset_sclk_vpll = { .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list), }; -static struct clksrc_clk clk_sclk_vpll = { +struct clksrc_clk clk_sclk_vpll = { .clk = { .name = "sclk_vpll", }, @@ -410,16 +408,6 @@ static struct clk init_clocks_off[] = { .enable = exynos4_clk_ip_lcd0_ctrl, .ctrlbit = (1 << 0), }, { - .name = "fimd", - .devname = "exynos4-fb.1", - .enable = exynos4_clk_ip_lcd1_ctrl, - .ctrlbit = (1 << 0), - }, { - .name = "sataphy", - .parent = &clk_aclk_133.clk, - .enable = exynos4_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 3), - }, { .name = "hsmmc", .devname = "s3c-sdhci.0", .parent = &clk_aclk_133.clk, @@ -449,11 +437,6 @@ static struct clk init_clocks_off[] = { .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 9), }, { - .name = "sata", - .parent = &clk_aclk_133.clk, - .enable = exynos4_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 10), - }, { .name = "pdma", .devname = "s3c-pl330.0", .enable = exynos4_clk_ip_fsys_ctrl, @@ -673,7 +656,7 @@ static struct clk init_clocks[] = { } }; -static struct clk *clkset_group_list[] = { +struct clk *clkset_group_list[] = { [0] = &clk_ext_xtal_mux, [1] = &clk_xusbxti, [2] = &clk_sclk_hdmi27m, @@ -685,7 +668,7 @@ static struct clk *clkset_group_list[] = { [8] = &clk_sclk_vpll.clk, }; -static struct clksrc_sources clkset_group = { +struct clksrc_sources clkset_group = { .sources = clkset_group_list, .nr_sources = ARRAY_SIZE(clkset_group_list), }; @@ -969,25 +952,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 }, }, { .clk = { - .name = "sclk_fimd", - .devname = "exynos4-fb.1", - .enable = exynos4_clksrc_mask_lcd1_ctrl, - .ctrlbit = (1 << 0), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_sata", - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 24), - }, - .sources = &clkset_mout_corebus, - .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 }, - .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 }, - }, { - .clk = { .name = "sclk_spi", .devname = "s3c64xx-spi.0", .enable = exynos4_clksrc_mask_peril1_ctrl, @@ -1116,7 +1080,13 @@ static int xtal_rate; static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) { - return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508); + if (soc_is_exynos4210()) + return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), + pll_4508); + else if (soc_is_exynos4212()) + return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0)); + else + return 0; } static struct clk_ops exynos4_fout_apll_ops = { @@ -1126,10 +1096,10 @@ static struct clk_ops exynos4_fout_apll_ops = { void __init_or_cpufreq exynos4_setup_clocks(void) { struct clk *xtal_clk; - unsigned long apll; - unsigned long mpll; - unsigned long epll; - unsigned long vpll; + unsigned long apll = 0; + unsigned long mpll = 0; + unsigned long epll = 0; + unsigned long vpll = 0; unsigned long vpllsrc; unsigned long xtal; unsigned long armclk; @@ -1153,14 +1123,29 @@ void __init_or_cpufreq exynos4_setup_clocks(void) printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); - apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508); - mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508); - epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0), - __raw_readl(S5P_EPLL_CON1), pll_4600); - - vpllsrc = clk_get_rate(&clk_vpllsrc.clk); - vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), - __raw_readl(S5P_VPLL_CON1), pll_4650c); + if (soc_is_exynos4210()) { + apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), + pll_4508); + mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), + pll_4508); + epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0), + __raw_readl(S5P_EPLL_CON1), pll_4600); + + vpllsrc = clk_get_rate(&clk_vpllsrc.clk); + vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), + __raw_readl(S5P_VPLL_CON1), pll_4650c); + } else if (soc_is_exynos4212()) { + apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0)); + mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0)); + epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0), + __raw_readl(S5P_EPLL_CON1)); + + vpllsrc = clk_get_rate(&clk_vpllsrc.clk); + vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), + __raw_readl(S5P_VPLL_CON1)); + } else { + /* nothing */ + } clk_fout_apll.ops = &exynos4_fout_apll_ops; clk_fout_mpll.rate = mpll; diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index 1e1a7a9..02ec52a 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c @@ -188,6 +188,12 @@ void __init exynos4_init_clocks(int xtal) s3c24xx_register_baseclocks(xtal); s5p_register_clocks(xtal); + + if (soc_is_exynos4210()) + exynos4210_register_clocks(); + else if (soc_is_exynos4212()) + exynos4212_register_clocks(); + exynos4_register_clocks(); exynos4_setup_clocks(); } diff --git a/arch/arm/mach-exynos4/include/mach/exynos4-clock.h b/arch/arm/mach-exynos4/include/mach/exynos4-clock.h new file mode 100644 index 0000000..a07fcbf --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/exynos4-clock.h @@ -0,0 +1,43 @@ +/* + * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Header file for exynos4 clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H __FILE__ + +#include + +extern struct clk clk_sclk_hdmi27m; +extern struct clk clk_sclk_usbphy0; +extern struct clk clk_sclk_usbphy1; +extern struct clk clk_sclk_hdmiphy; + +extern struct clksrc_clk clk_sclk_apll; +extern struct clksrc_clk clk_mout_mpll; +extern struct clksrc_clk clk_aclk_133; +extern struct clksrc_clk clk_mout_epll; +extern struct clksrc_clk clk_sclk_vpll; + +extern struct clk *clkset_corebus_list[]; +extern struct clksrc_sources clkset_mout_corebus; + +extern struct clk *clkset_aclk_top_list[]; +extern struct clksrc_sources clkset_aclk; + +extern struct clk *clkset_group_list[]; +extern struct clksrc_sources clkset_group; + +extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable); +extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable); +extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable); + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h index d493fdb..e75d0f8 100644 --- a/arch/arm/mach-exynos4/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h @@ -13,6 +13,7 @@ #ifndef __ASM_ARCH_REGS_CLOCK_H #define __ASM_ARCH_REGS_CLOCK_H __FILE__ +#include #include #define S5P_CLKREG(x) (S5P_VA_CMU + (x)) @@ -41,12 +42,20 @@ #define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C) #define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) #define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) -#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) #define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C) #define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240) #define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) #define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254) +#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) +#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) +#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324) +#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334) +#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C) +#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340) +#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) +#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) + #define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) #define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520) #define S5P_CLKDIV_TV S5P_CLKREG(0x0C524) @@ -54,7 +63,6 @@ #define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C) #define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530) #define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534) -#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538) #define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C) #define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540) #define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544) @@ -68,16 +76,6 @@ #define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) #define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580) -#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) -#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) -#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324) -#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334) -#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338) -#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C) -#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340) -#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) -#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) - #define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610) #define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820) @@ -85,13 +83,16 @@ #define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924) #define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928) #define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C) -#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930) +#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \ + S5P_CLKREG(0x0C930) : \ + S5P_CLKREG(0x04930)) #define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) -#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938) #define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) #define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C) #define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) -#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960) +#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \ + S5P_CLKREG(0x0C960) : \ + S5P_CLKREG(0x08960)) #define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970) #define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300) @@ -102,11 +103,17 @@ #define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900) #define S5P_APLL_LOCK S5P_CLKREG(0x14000) -#define S5P_MPLL_LOCK S5P_CLKREG(0x14004) +#define S5P_MPLL_LOCK (soc_is_exynos4210() ? \ + S5P_CLKREG(0x14004) : \ + S5P_CLKREG(0x10008)) #define S5P_APLL_CON0 S5P_CLKREG(0x14100) #define S5P_APLL_CON1 S5P_CLKREG(0x14104) -#define S5P_MPLL_CON0 S5P_CLKREG(0x14108) -#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C) +#define S5P_MPLL_CON0 (soc_is_exynos4210() ? \ + S5P_CLKREG(0x14108) : \ + S5P_CLKREG(0x10108)) +#define S5P_MPLL_CON1 (soc_is_exynos4210() ? \ + S5P_CLKREG(0x1410C) : \ + S5P_CLKREG(0x1010C)) #define S5P_CLKSRC_CPU S5P_CLKREG(0x14200) #define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400) @@ -183,6 +190,13 @@ #define S5P_CLKDIV_BUS_GPLR_SHIFT (4) #define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT) +/* Only for EXYNOS4210 */ + +#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) +#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338) +#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538) +#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938) + /* Compatibility defines and inclusion */ #include diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-s5p/include/plat/exynos4.h index 4aed130..f680a14 100644 --- a/arch/arm/plat-s5p/include/plat/exynos4.h +++ b/arch/arm/plat-s5p/include/plat/exynos4.h @@ -14,6 +14,8 @@ extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); extern void exynos4_register_clocks(void); +extern void exynos4210_register_clocks(void); +extern void exynos4212_register_clocks(void); extern void exynos4_setup_clocks(void); #ifdef CONFIG_ARCH_EXYNOS4 diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h index bf28fad..1bfd61a 100644 --- a/arch/arm/plat-s5p/include/plat/pll.h +++ b/arch/arm/plat-s5p/include/plat/pll.h @@ -12,6 +12,59 @@ * published by the Free Software Foundation. */ +#include + +#define PLL35XX_MDIV_MASK (0x3FF) +#define PLL35XX_PDIV_MASK (0x3F) +#define PLL35XX_SDIV_MASK (0x7) +#define PLL35XX_MDIV_SHIFT (16) +#define PLL35XX_PDIV_SHIFT (8) +#define PLL35XX_SDIV_SHIFT (0) + +static inline unsigned long s5p_get_pll35xx(unsigned long baseclk, u32 pll_con) +{ + u32 mdiv, pdiv, sdiv; + u64 fvco = baseclk; + + mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; + pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; + sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned long)fvco; +} + +#define PLL36XX_KDIV_MASK (0xFFFF) +#define PLL36XX_MDIV_MASK (0x1FF) +#define PLL36XX_PDIV_MASK (0x3F) +#define PLL36XX_SDIV_MASK (0x7) +#define PLL36XX_MDIV_SHIFT (16) +#define PLL36XX_PDIV_SHIFT (8) +#define PLL36XX_SDIV_SHIFT (0) + +static inline unsigned long s5p_get_pll36xx(unsigned long baseclk, + u32 pll_con0, u32 pll_con1) +{ + unsigned long result; + u32 mdiv, pdiv, sdiv, kdiv; + u64 tmp; + + mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; + pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; + sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK; + kdiv = pll_con1 & PLL36XX_KDIV_MASK; + + tmp = baseclk; + + tmp *= (mdiv << 16) + kdiv; + do_div(tmp, (pdiv << sdiv)); + result = tmp >> 16; + + return result; +} + #define PLL45XX_MDIV_MASK (0x3FF) #define PLL45XX_PDIV_MASK (0x3F) #define PLL45XX_SDIV_MASK (0x7) @@ -19,8 +72,6 @@ #define PLL45XX_PDIV_SHIFT (8) #define PLL45XX_SDIV_SHIFT (0) -#include - enum pll45xx_type_t { pll_4500, pll_4502, -- cgit v0.10.2 From acd35616c7a30130d3b43ae1c1bb0b7fd121ffb9 Mon Sep 17 00:00:00 2001 From: Jonghwan Choi Date: Wed, 24 Aug 2011 21:52:45 +0900 Subject: ARM: EXYNOS4: Add support PM for EXYNOS4212 This patch moves regarding clock stuff of PM into clock file to support PM on EXYNOS4210 and EXYNOS4212 with one single kernel image. Because some clock registers are different on each SoCs. Signed-off-by: Jonghwan Choi [kgene.kim@samsung.com: use CONFIG_PM_SLEEP instead of CONFIG_PM] Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-exynos4/clock-exynos4210.c index fe74b91..b9d5ef6 100644 --- a/arch/arm/mach-exynos4/clock-exynos4210.c +++ b/arch/arm/mach-exynos4/clock-exynos4210.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -23,12 +24,24 @@ #include #include #include +#include #include #include #include #include +static struct sleep_save exynos4210_clock_save[] = { + SAVE_ITEM(S5P_CLKSRC_IMAGE), + SAVE_ITEM(S5P_CLKSRC_LCD1), + SAVE_ITEM(S5P_CLKDIV_IMAGE), + SAVE_ITEM(S5P_CLKDIV_LCD1), + SAVE_ITEM(S5P_CLKSRC_MASK_LCD1), + SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210), + SAVE_ITEM(S5P_CLKGATE_IP_LCD1), + SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210), +}; + static struct clksrc_clk *sysclks[] = { /* nothing here yet */ }; @@ -83,6 +96,29 @@ static struct clk init_clocks_off[] = { }, }; +#ifdef CONFIG_PM_SLEEP +static int exynos4210_clock_suspend(void) +{ + s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save)); + + return 0; +} + +static void exynos4210_clock_resume(void) +{ + s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save)); +} + +#else +#define exynos4210_clock_suspend NULL +#define exynos4210_clock_resume NULL +#endif + +struct syscore_ops exynos4210_clock_syscore_ops = { + .suspend = exynos4210_clock_suspend, + .resume = exynos4210_clock_resume, +}; + void __init exynos4210_register_clocks(void) { int ptr; @@ -98,4 +134,6 @@ void __init exynos4210_register_clocks(void) s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + + register_syscore_ops(&exynos4210_clock_syscore_ops); } diff --git a/arch/arm/mach-exynos4/clock-exynos4212.c b/arch/arm/mach-exynos4/clock-exynos4212.c index 5a47a3f..77d5dec 100644 --- a/arch/arm/mach-exynos4/clock-exynos4212.c +++ b/arch/arm/mach-exynos4/clock-exynos4212.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -23,12 +24,20 @@ #include #include #include +#include #include #include #include #include +static struct sleep_save exynos4212_clock_save[] = { + SAVE_ITEM(S5P_CLKSRC_IMAGE), + SAVE_ITEM(S5P_CLKDIV_IMAGE), + SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212), + SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212), +}; + static struct clk *clk_src_mpll_user_list[] = { [0] = &clk_fin_mpll, [1] = &clk_mout_mpll.clk, @@ -59,6 +68,29 @@ static struct clk init_clocks_off[] = { /* nothing here yet */ }; +#ifdef CONFIG_PM_SLEEP +static int exynos4212_clock_suspend(void) +{ + s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save)); + + return 0; +} + +static void exynos4212_clock_resume(void) +{ + s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save)); +} + +#else +#define exynos4212_clock_suspend NULL +#define exynos4212_clock_resume NULL +#endif + +struct syscore_ops exynos4212_clock_syscore_ops = { + .suspend = exynos4212_clock_suspend, + .resume = exynos4212_clock_resume, +}; + void __init exynos4212_register_clocks(void) { int ptr; @@ -81,4 +113,6 @@ void __init exynos4212_register_clocks(void) s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + + register_syscore_ops(&exynos4212_clock_syscore_ops); } diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index eb99467..f26aea3 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -21,12 +22,77 @@ #include #include #include +#include #include #include #include #include +static struct sleep_save exynos4_clock_save[] = { + SAVE_ITEM(S5P_CLKDIV_LEFTBUS), + SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), + SAVE_ITEM(S5P_CLKDIV_RIGHTBUS), + SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS), + SAVE_ITEM(S5P_CLKSRC_TOP0), + SAVE_ITEM(S5P_CLKSRC_TOP1), + SAVE_ITEM(S5P_CLKSRC_CAM), + SAVE_ITEM(S5P_CLKSRC_TV), + SAVE_ITEM(S5P_CLKSRC_MFC), + SAVE_ITEM(S5P_CLKSRC_G3D), + SAVE_ITEM(S5P_CLKSRC_LCD0), + SAVE_ITEM(S5P_CLKSRC_MAUDIO), + SAVE_ITEM(S5P_CLKSRC_FSYS), + SAVE_ITEM(S5P_CLKSRC_PERIL0), + SAVE_ITEM(S5P_CLKSRC_PERIL1), + SAVE_ITEM(S5P_CLKDIV_CAM), + SAVE_ITEM(S5P_CLKDIV_TV), + SAVE_ITEM(S5P_CLKDIV_MFC), + SAVE_ITEM(S5P_CLKDIV_G3D), + SAVE_ITEM(S5P_CLKDIV_LCD0), + SAVE_ITEM(S5P_CLKDIV_MAUDIO), + SAVE_ITEM(S5P_CLKDIV_FSYS0), + SAVE_ITEM(S5P_CLKDIV_FSYS1), + SAVE_ITEM(S5P_CLKDIV_FSYS2), + SAVE_ITEM(S5P_CLKDIV_FSYS3), + SAVE_ITEM(S5P_CLKDIV_PERIL0), + SAVE_ITEM(S5P_CLKDIV_PERIL1), + SAVE_ITEM(S5P_CLKDIV_PERIL2), + SAVE_ITEM(S5P_CLKDIV_PERIL3), + SAVE_ITEM(S5P_CLKDIV_PERIL4), + SAVE_ITEM(S5P_CLKDIV_PERIL5), + SAVE_ITEM(S5P_CLKDIV_TOP), + SAVE_ITEM(S5P_CLKSRC_MASK_TOP), + SAVE_ITEM(S5P_CLKSRC_MASK_CAM), + SAVE_ITEM(S5P_CLKSRC_MASK_TV), + SAVE_ITEM(S5P_CLKSRC_MASK_LCD0), + SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO), + SAVE_ITEM(S5P_CLKSRC_MASK_FSYS), + SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0), + SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1), + SAVE_ITEM(S5P_CLKDIV2_RATIO), + SAVE_ITEM(S5P_CLKGATE_SCLKCAM), + SAVE_ITEM(S5P_CLKGATE_IP_CAM), + SAVE_ITEM(S5P_CLKGATE_IP_TV), + SAVE_ITEM(S5P_CLKGATE_IP_MFC), + SAVE_ITEM(S5P_CLKGATE_IP_G3D), + SAVE_ITEM(S5P_CLKGATE_IP_LCD0), + SAVE_ITEM(S5P_CLKGATE_IP_FSYS), + SAVE_ITEM(S5P_CLKGATE_IP_GPS), + SAVE_ITEM(S5P_CLKGATE_IP_PERIL), + SAVE_ITEM(S5P_CLKGATE_BLOCK), + SAVE_ITEM(S5P_CLKSRC_MASK_DMC), + SAVE_ITEM(S5P_CLKSRC_DMC), + SAVE_ITEM(S5P_CLKDIV_DMC0), + SAVE_ITEM(S5P_CLKDIV_DMC1), + SAVE_ITEM(S5P_CLKGATE_IP_DMC), + SAVE_ITEM(S5P_CLKSRC_CPU), + SAVE_ITEM(S5P_CLKDIV_CPU), + SAVE_ITEM(S5P_CLKDIV_CPU + 0x4), + SAVE_ITEM(S5P_CLKGATE_SCLKCPU), + SAVE_ITEM(S5P_CLKGATE_IP_CPU), +}; + struct clk clk_sclk_hdmi27m = { .name = "sclk_hdmi27m", .rate = 27000000, @@ -1180,6 +1246,28 @@ static struct clk *clks[] __initdata = { /* Nothing here yet */ }; +#ifdef CONFIG_PM_SLEEP +static int exynos4_clock_suspend(void) +{ + s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save)); + return 0; +} + +static void exynos4_clock_resume(void) +{ + s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save)); +} + +#else +#define exynos4_clock_suspend NULL +#define exynos4_clock_resume NULL +#endif + +struct syscore_ops exynos4_clock_syscore_ops = { + .suspend = exynos4_clock_suspend, + .resume = exynos4_clock_resume, +}; + void __init exynos4_register_clocks(void) { int ptr; @@ -1195,5 +1283,6 @@ void __init exynos4_register_clocks(void) s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + register_syscore_ops(&exynos4_clock_syscore_ops); s3c_pwmclk_init(); } diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h index e75d0f8..6c37ebe 100644 --- a/arch/arm/mach-exynos4/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h @@ -86,6 +86,8 @@ #define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \ S5P_CLKREG(0x0C930) : \ S5P_CLKREG(0x04930)) +#define S5P_CLKGATE_IP_IMAGE_4210 S5P_CLKREG(0x0C930) +#define S5P_CLKGATE_IP_IMAGE_4212 S5P_CLKREG(0x04930) #define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) #define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) #define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C) @@ -93,6 +95,8 @@ #define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \ S5P_CLKREG(0x0C960) : \ S5P_CLKREG(0x08960)) +#define S5P_CLKGATE_IP_PERIR_4210 S5P_CLKREG(0x0C960) +#define S5P_CLKGATE_IP_PERIR_4212 S5P_CLKREG(0x08960) #define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970) #define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300) diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c index bc6ca94..62e4f43 100644 --- a/arch/arm/mach-exynos4/pm.c +++ b/arch/arm/mach-exynos4/pm.c @@ -41,7 +41,6 @@ static struct sleep_save exynos4_set_clksrc[] = { { .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, }, { .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, }, { .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, }, - { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, { .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, }, { .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, }, { .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, }, @@ -49,6 +48,10 @@ static struct sleep_save exynos4_set_clksrc[] = { { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, }, }; +static struct sleep_save exynos4210_set_clksrc[] = { + { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, +}; + static struct sleep_save exynos4_epll_save[] = { SAVE_ITEM(S5P_EPLL_CON0), SAVE_ITEM(S5P_EPLL_CON1), @@ -60,77 +63,6 @@ static struct sleep_save exynos4_vpll_save[] = { }; static struct sleep_save exynos4_core_save[] = { - /* CMU side */ - SAVE_ITEM(S5P_CLKDIV_LEFTBUS), - SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), - SAVE_ITEM(S5P_CLKDIV_RIGHTBUS), - SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS), - SAVE_ITEM(S5P_CLKSRC_TOP0), - SAVE_ITEM(S5P_CLKSRC_TOP1), - SAVE_ITEM(S5P_CLKSRC_CAM), - SAVE_ITEM(S5P_CLKSRC_TV), - SAVE_ITEM(S5P_CLKSRC_MFC), - SAVE_ITEM(S5P_CLKSRC_G3D), - SAVE_ITEM(S5P_CLKSRC_IMAGE), - SAVE_ITEM(S5P_CLKSRC_LCD0), - SAVE_ITEM(S5P_CLKSRC_LCD1), - SAVE_ITEM(S5P_CLKSRC_MAUDIO), - SAVE_ITEM(S5P_CLKSRC_FSYS), - SAVE_ITEM(S5P_CLKSRC_PERIL0), - SAVE_ITEM(S5P_CLKSRC_PERIL1), - SAVE_ITEM(S5P_CLKDIV_CAM), - SAVE_ITEM(S5P_CLKDIV_TV), - SAVE_ITEM(S5P_CLKDIV_MFC), - SAVE_ITEM(S5P_CLKDIV_G3D), - SAVE_ITEM(S5P_CLKDIV_IMAGE), - SAVE_ITEM(S5P_CLKDIV_LCD0), - SAVE_ITEM(S5P_CLKDIV_LCD1), - SAVE_ITEM(S5P_CLKDIV_MAUDIO), - SAVE_ITEM(S5P_CLKDIV_FSYS0), - SAVE_ITEM(S5P_CLKDIV_FSYS1), - SAVE_ITEM(S5P_CLKDIV_FSYS2), - SAVE_ITEM(S5P_CLKDIV_FSYS3), - SAVE_ITEM(S5P_CLKDIV_PERIL0), - SAVE_ITEM(S5P_CLKDIV_PERIL1), - SAVE_ITEM(S5P_CLKDIV_PERIL2), - SAVE_ITEM(S5P_CLKDIV_PERIL3), - SAVE_ITEM(S5P_CLKDIV_PERIL4), - SAVE_ITEM(S5P_CLKDIV_PERIL5), - SAVE_ITEM(S5P_CLKDIV_TOP), - SAVE_ITEM(S5P_CLKSRC_MASK_TOP), - SAVE_ITEM(S5P_CLKSRC_MASK_CAM), - SAVE_ITEM(S5P_CLKSRC_MASK_TV), - SAVE_ITEM(S5P_CLKSRC_MASK_LCD0), - SAVE_ITEM(S5P_CLKSRC_MASK_LCD1), - SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO), - SAVE_ITEM(S5P_CLKSRC_MASK_FSYS), - SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0), - SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1), - SAVE_ITEM(S5P_CLKDIV2_RATIO), - SAVE_ITEM(S5P_CLKGATE_SCLKCAM), - SAVE_ITEM(S5P_CLKGATE_IP_CAM), - SAVE_ITEM(S5P_CLKGATE_IP_TV), - SAVE_ITEM(S5P_CLKGATE_IP_MFC), - SAVE_ITEM(S5P_CLKGATE_IP_G3D), - SAVE_ITEM(S5P_CLKGATE_IP_IMAGE), - SAVE_ITEM(S5P_CLKGATE_IP_LCD0), - SAVE_ITEM(S5P_CLKGATE_IP_LCD1), - SAVE_ITEM(S5P_CLKGATE_IP_FSYS), - SAVE_ITEM(S5P_CLKGATE_IP_GPS), - SAVE_ITEM(S5P_CLKGATE_IP_PERIL), - SAVE_ITEM(S5P_CLKGATE_IP_PERIR), - SAVE_ITEM(S5P_CLKGATE_BLOCK), - SAVE_ITEM(S5P_CLKSRC_MASK_DMC), - SAVE_ITEM(S5P_CLKSRC_DMC), - SAVE_ITEM(S5P_CLKDIV_DMC0), - SAVE_ITEM(S5P_CLKDIV_DMC1), - SAVE_ITEM(S5P_CLKGATE_IP_DMC), - SAVE_ITEM(S5P_CLKSRC_CPU), - SAVE_ITEM(S5P_CLKDIV_CPU), - SAVE_ITEM(S5P_CLKDIV_CPU + 0x4), - SAVE_ITEM(S5P_CLKGATE_SCLKCPU), - SAVE_ITEM(S5P_CLKGATE_IP_CPU), - /* GIC side */ SAVE_ITEM(S5P_VA_GIC_CPU + 0x000), SAVE_ITEM(S5P_VA_GIC_CPU + 0x004), @@ -268,6 +200,9 @@ static void exynos4_pm_prepare(void) s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc)); + if (soc_is_exynos4210()) + s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc)); + } static int exynos4_pm_add(struct sys_device *sysdev) -- cgit v0.10.2 From be4ab3616839c26caf914449de3a22458f53f6e5 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Wed, 24 Aug 2011 17:25:09 +0900 Subject: ARM: EXYNOS4: Add support SMDK4212 Board This patch adds mach-smdk4212.c to support SMDK4212 board. Now it can support HSMMCs, I2Cs, RTC, WDT and Keypad. Other features will be supported next time. Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig index 0b40289..f4ec583 100644 --- a/arch/arm/mach-exynos4/Kconfig +++ b/arch/arm/mach-exynos4/Kconfig @@ -116,6 +116,8 @@ config EXYNOS4_SETUP_USB_PHY menu "EXYNOS4 Machines" +comment "EXYNOS4210 Boards" + config MACH_SMDKC210 bool "SMDKC210" select MACH_SMDKV310 @@ -208,6 +210,29 @@ config MACH_NURI help Machine support for Samsung Mobile NURI Board. +comment "EXYNOS4212 Boards" + +config MACH_SMDK4212 + bool "SMDK4212" + select SOC_EXYNOS4212 + select S3C_DEV_HSMMC2 + select S3C_DEV_HSMMC3 + select S3C_DEV_I2C1 + select S3C_DEV_I2C3 + select S3C_DEV_I2C7 + select S3C_DEV_RTC + select S3C_DEV_WDT + select SAMSUNG_DEV_BACKLIGHT + select SAMSUNG_DEV_KEYPAD + select SAMSUNG_DEV_PWM + select EXYNOS4_SETUP_I2C1 + select EXYNOS4_SETUP_I2C3 + select EXYNOS4_SETUP_I2C7 + select EXYNOS4_SETUP_KEYPAD + select EXYNOS4_SETUP_SDHCI + help + Machine support for Samsung SMDK4212 + endmenu comment "Configuration for HSMMC bus width" diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile index 4624457..64ffad4 100644 --- a/arch/arm/mach-exynos4/Makefile +++ b/arch/arm/mach-exynos4/Makefile @@ -33,6 +33,8 @@ obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o obj-$(CONFIG_MACH_NURI) += mach-nuri.o +obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4212.o + # device support obj-y += dev-audio.o diff --git a/arch/arm/mach-exynos4/mach-smdk4212.c b/arch/arm/mach-exynos4/mach-smdk4212.c new file mode 100644 index 0000000..3479a93 --- /dev/null +++ b/arch/arm/mach-exynos4/mach-smdk4212.c @@ -0,0 +1,292 @@ +/* + * linux/arch/arm/mach-exynos4/mach-smdk4212.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define SMDK4212_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define SMDK4212_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define SMDK4212_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + +static struct s3c2410_uartcfg smdk4212_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = SMDK4212_UCON_DEFAULT, + .ulcon = SMDK4212_ULCON_DEFAULT, + .ufcon = SMDK4212_UFCON_DEFAULT, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = SMDK4212_UCON_DEFAULT, + .ulcon = SMDK4212_ULCON_DEFAULT, + .ufcon = SMDK4212_UFCON_DEFAULT, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = SMDK4212_UCON_DEFAULT, + .ulcon = SMDK4212_ULCON_DEFAULT, + .ufcon = SMDK4212_UFCON_DEFAULT, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = SMDK4212_UCON_DEFAULT, + .ulcon = SMDK4212_ULCON_DEFAULT, + .ufcon = SMDK4212_UFCON_DEFAULT, + }, +}; + +static struct s3c_sdhci_platdata smdk4212_hsmmc2_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_INTERNAL, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, +#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA, +#endif +}; + +static struct s3c_sdhci_platdata smdk4212_hsmmc3_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_INTERNAL, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, +}; + +static struct regulator_consumer_supply max8997_buck1 = + REGULATOR_SUPPLY("vdd_arm", NULL); + +static struct regulator_consumer_supply max8997_buck2 = + REGULATOR_SUPPLY("vdd_int", NULL); + +static struct regulator_consumer_supply max8997_buck3 = + REGULATOR_SUPPLY("vdd_g3d", NULL); + +static struct regulator_init_data max8997_buck1_data = { + .constraints = { + .name = "VDD_ARM_SMDK4212", + .min_uV = 925000, + .max_uV = 1350000, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8997_buck1, +}; + +static struct regulator_init_data max8997_buck2_data = { + .constraints = { + .name = "VDD_INT_SMDK4212", + .min_uV = 950000, + .max_uV = 1150000, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8997_buck2, +}; + +static struct regulator_init_data max8997_buck3_data = { + .constraints = { + .name = "VDD_G3D_SMDK4212", + .min_uV = 950000, + .max_uV = 1150000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8997_buck3, +}; + +static struct max8997_regulator_data smdk4212_max8997_regulators[] = { + { MAX8997_BUCK1, &max8997_buck1_data }, + { MAX8997_BUCK2, &max8997_buck2_data }, + { MAX8997_BUCK3, &max8997_buck3_data }, +}; + +static struct max8997_platform_data smdk4212_max8997_pdata = { + .num_regulators = ARRAY_SIZE(smdk4212_max8997_regulators), + .regulators = smdk4212_max8997_regulators, + + .buck1_voltage[0] = 1100000, /* 1.1V */ + .buck1_voltage[1] = 1100000, /* 1.1V */ + .buck1_voltage[2] = 1100000, /* 1.1V */ + .buck1_voltage[3] = 1100000, /* 1.1V */ + .buck1_voltage[4] = 1100000, /* 1.1V */ + .buck1_voltage[5] = 1100000, /* 1.1V */ + .buck1_voltage[6] = 1000000, /* 1.0V */ + .buck1_voltage[7] = 950000, /* 0.95V */ + + .buck2_voltage[0] = 1100000, /* 1.1V */ + .buck2_voltage[1] = 1000000, /* 1.0V */ + .buck2_voltage[2] = 950000, /* 0.95V */ + .buck2_voltage[3] = 900000, /* 0.9V */ + .buck2_voltage[4] = 1100000, /* 1.1V */ + .buck2_voltage[5] = 1000000, /* 1.0V */ + .buck2_voltage[6] = 950000, /* 0.95V */ + .buck2_voltage[7] = 900000, /* 0.9V */ + + .buck5_voltage[0] = 1100000, /* 1.1V */ + .buck5_voltage[1] = 1100000, /* 1.1V */ + .buck5_voltage[2] = 1100000, /* 1.1V */ + .buck5_voltage[3] = 1100000, /* 1.1V */ + .buck5_voltage[4] = 1100000, /* 1.1V */ + .buck5_voltage[5] = 1100000, /* 1.1V */ + .buck5_voltage[6] = 1100000, /* 1.1V */ + .buck5_voltage[7] = 1100000, /* 1.1V */ +}; + +static struct i2c_board_info smdk4212_i2c_devs0[] __initdata = { + { + I2C_BOARD_INFO("max8997", 0x66), + .platform_data = &smdk4212_max8997_pdata, + } +}; + +static struct i2c_board_info smdk4212_i2c_devs1[] __initdata = { + { I2C_BOARD_INFO("wm8994", 0x1a), } +}; + +static struct i2c_board_info smdk4212_i2c_devs3[] __initdata = { + /* nothing here yet */ +}; + +static struct i2c_board_info smdk4212_i2c_devs7[] __initdata = { + /* nothing here yet */ +}; + +static struct samsung_bl_gpio_info smdk4212_bl_gpio_info = { + .no = EXYNOS4_GPD0(1), + .func = S3C_GPIO_SFN(2), +}; + +static struct platform_pwm_backlight_data smdk4212_bl_data = { + .pwm_id = 1, + .pwm_period_ns = 1000, +}; + +static uint32_t smdk4212_keymap[] __initdata = { + /* KEY(row, col, keycode) */ + KEY(1, 0, KEY_D), KEY(1, 1, KEY_A), KEY(1, 2, KEY_B), + KEY(1, 3, KEY_E), KEY(1, 4, KEY_C) +}; + +static struct matrix_keymap_data smdk4212_keymap_data __initdata = { + .keymap = smdk4212_keymap, + .keymap_size = ARRAY_SIZE(smdk4212_keymap), +}; + +static struct samsung_keypad_platdata smdk4212_keypad_data __initdata = { + .keymap_data = &smdk4212_keymap_data, + .rows = 2, + .cols = 5, +}; + +static struct platform_device *smdk4212_devices[] __initdata = { + &s3c_device_hsmmc2, + &s3c_device_hsmmc3, + &s3c_device_i2c0, + &s3c_device_i2c1, + &s3c_device_i2c3, + &s3c_device_i2c7, + &s3c_device_rtc, + &s3c_device_wdt, + &samsung_device_keypad, +}; + +static void __init smdk4212_map_io(void) +{ + clk_xusbxti.rate = 24000000; + + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(clk_xusbxti.rate); + s3c24xx_init_uarts(smdk4212_uartcfgs, ARRAY_SIZE(smdk4212_uartcfgs)); +} + +static void __init smdk4212_machine_init(void) +{ + s3c_i2c0_set_platdata(NULL); + i2c_register_board_info(0, smdk4212_i2c_devs0, + ARRAY_SIZE(smdk4212_i2c_devs0)); + + s3c_i2c1_set_platdata(NULL); + i2c_register_board_info(1, smdk4212_i2c_devs1, + ARRAY_SIZE(smdk4212_i2c_devs1)); + + s3c_i2c3_set_platdata(NULL); + i2c_register_board_info(3, smdk4212_i2c_devs3, + ARRAY_SIZE(smdk4212_i2c_devs3)); + + s3c_i2c7_set_platdata(NULL); + i2c_register_board_info(7, smdk4212_i2c_devs7, + ARRAY_SIZE(smdk4212_i2c_devs7)); + + samsung_bl_set(&smdk4212_bl_gpio_info, &smdk4212_bl_data); + + samsung_keypad_set_platdata(&smdk4212_keypad_data); + + s3c_sdhci2_set_platdata(&smdk4212_hsmmc2_pdata); + s3c_sdhci3_set_platdata(&smdk4212_hsmmc3_pdata); + + platform_add_devices(smdk4212_devices, ARRAY_SIZE(smdk4212_devices)); +} + +MACHINE_START(SMDK4212, "SMDK4212") + /* Maintainer: Kukjin Kim */ + .boot_params = S5P_PA_SDRAM + 0x100, + .init_irq = exynos4_init_irq, + .map_io = smdk4212_map_io, + .init_machine = smdk4212_machine_init, + .timer = &exynos4_timer, +MACHINE_END -- cgit v0.10.2 From 2b8f0119b857d32f827641a9f7b31fe8d31bfde6 Mon Sep 17 00:00:00 2001 From: Richard Cochran Date: Wed, 28 Sep 2011 15:16:41 +0200 Subject: ixp4xx: support omicron ixp425 based boards This patch adds board support for the DEVIXP, the MICCPT, and the MIC256, which are three IXP425 based boards produced by OMICRON electronics, GmbH. Signed-off-by: Richard Cochran Signed-off-by: Arnd Bergmann diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index 6f991c5..fd5e7b6 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -179,6 +179,25 @@ config MACH_GTWX5715 "High Speed" UART is n/c (as far as I can tell) 20 Pin ARM/Xscale JTAG interface on J2 +config MACH_DEVIXP + bool "Omicron DEVIXP" + help + Say 'Y' here if you want your kernel to support the DEVIXP + board from OMICRON electronics GmbH. + +config MACH_MICCPT + bool "Omicron MICCPT" + select PCI + help + Say 'Y' here if you want your kernel to support the MICCPT + board from OMICRON electronics GmbH. + +config MACH_MIC256 + bool "Omicron MIC256" + help + Say 'Y' here if you want your kernel to support the MIC256 + board from OMICRON electronics GmbH. + comment "IXP4xx Options" config IXP4XX_INDIRECT_PCI diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile index d807fc3..eded94c 100644 --- a/arch/arm/mach-ixp4xx/Makefile +++ b/arch/arm/mach-ixp4xx/Makefile @@ -10,6 +10,7 @@ obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o +obj-pci-$(CONFIG_MACH_MICCPT) += miccpt-pci.o obj-pci-$(CONFIG_MACH_NSLU2) += nslu2-pci.o obj-pci-$(CONFIG_MACH_NAS100D) += nas100d-pci.o obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o @@ -25,6 +26,9 @@ obj-$(CONFIG_MACH_AVILA) += avila-setup.o obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o +obj-$(CONFIG_MACH_DEVIXP) += omixp-setup.o +obj-$(CONFIG_MACH_MICCPT) += omixp-setup.o +obj-$(CONFIG_MACH_MIC256) += omixp-setup.o obj-$(CONFIG_MACH_NSLU2) += nslu2-setup.o obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h index 219d7c1..eb945a9 100644 --- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h +++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h @@ -41,7 +41,8 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) * Some boards are using UART2 as console */ if (machine_is_adi_coyote() || machine_is_gtwx5715() || - machine_is_gateway7001() || machine_is_wg302v2()) + machine_is_gateway7001() || machine_is_wg302v2() || + machine_is_devixp() || machine_is_miccpt() || machine_is_mic256()) uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; else uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; diff --git a/arch/arm/mach-ixp4xx/miccpt-pci.c b/arch/arm/mach-ixp4xx/miccpt-pci.c new file mode 100644 index 0000000..ca0bae7 --- /dev/null +++ b/arch/arm/mach-ixp4xx/miccpt-pci.c @@ -0,0 +1,78 @@ +/* + * arch/arm/mach-ixp4xx/miccpt-pci.c + * + * MICCPT board-level PCI initialization + * + * Copyright (C) 2002 Intel Corporation. + * Copyright (C) 2003-2004 MontaVista Software, Inc. + * Copyright (C) 2006 OMICRON electronics GmbH + * + * Author: Michael Jochum + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_DEV 4 +#define IRQ_LINES 4 + +/* PCI controller GPIO to IRQ pin mappings */ +#define INTA 1 +#define INTB 2 +#define INTC 3 +#define INTD 4 + + +void __init miccpt_pci_preinit(void) +{ + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); + ixp4xx_pci_preinit(); +} + +static int __init miccpt_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + static int pci_irq_table[IRQ_LINES] = { + IXP4XX_GPIO_IRQ(INTA), + IXP4XX_GPIO_IRQ(INTB), + IXP4XX_GPIO_IRQ(INTC), + IXP4XX_GPIO_IRQ(INTD) + }; + + if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) + return pci_irq_table[(slot + pin - 2) % 4]; + + return -1; +} + +struct hw_pci miccpt_pci __initdata = { + .nr_controllers = 1, + .preinit = miccpt_pci_preinit, + .swizzle = pci_std_swizzle, + .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, + .map_irq = miccpt_map_irq, +}; + +int __init miccpt_pci_init(void) +{ + if (machine_is_miccpt()) + pci_common_init(&miccpt_pci); + return 0; +} + +subsys_initcall(miccpt_pci_init); diff --git a/arch/arm/mach-ixp4xx/omixp-setup.c b/arch/arm/mach-ixp4xx/omixp-setup.c new file mode 100644 index 0000000..4dfdc69 --- /dev/null +++ b/arch/arm/mach-ixp4xx/omixp-setup.c @@ -0,0 +1,273 @@ +/* + * arch/arm/mach-ixp4xx/omixp-setup.c + * + * omicron ixp4xx board setup + * Copyright (C) 2009 OMICRON electronics GmbH + * + * based nslu2-setup.c, ixdp425-setup.c: + * Copyright (C) 2003-2004 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#ifdef CONFIG_LEDS_CLASS +#include +#endif + +#include +#include +#include +#include +#include + +static struct resource omixp_flash_resources[] = { + { + .flags = IORESOURCE_MEM, + }, { + .flags = IORESOURCE_MEM, + }, +}; + +static struct mtd_partition omixp_partitions[] = { + { + .name = "Recovery Bootloader", + .size = 0x00020000, + .offset = 0, + }, { + .name = "Calibration Data", + .size = 0x00020000, + .offset = 0x00020000, + }, { + .name = "Recovery FPGA", + .size = 0x00020000, + .offset = 0x00040000, + }, { + .name = "Release Bootloader", + .size = 0x00020000, + .offset = 0x00060000, + }, { + .name = "Release FPGA", + .size = 0x00020000, + .offset = 0x00080000, + }, { + .name = "Kernel", + .size = 0x00160000, + .offset = 0x000a0000, + }, { + .name = "Filesystem", + .size = 0x00C00000, + .offset = 0x00200000, + }, { + .name = "Persistent Storage", + .size = 0x00200000, + .offset = 0x00E00000, + }, +}; + +static struct flash_platform_data omixp_flash_data[] = { + { + .map_name = "cfi_probe", + .parts = omixp_partitions, + .nr_parts = ARRAY_SIZE(omixp_partitions), + }, { + .map_name = "cfi_probe", + .parts = NULL, + .nr_parts = 0, + }, +}; + +static struct platform_device omixp_flash_device[] = { + { + .name = "IXP4XX-Flash", + .id = 0, + .dev = { + .platform_data = &omixp_flash_data[0], + }, + .resource = &omixp_flash_resources[0], + .num_resources = 1, + }, { + .name = "IXP4XX-Flash", + .id = 1, + .dev = { + .platform_data = &omixp_flash_data[1], + }, + .resource = &omixp_flash_resources[1], + .num_resources = 1, + }, +}; + +/* Swap UART's - These boards have the console on UART2. The following + * configuration is used: + * ttyS0 .. UART2 + * ttyS1 .. UART1 + * This way standard images can be used with the kernel that expect + * the console on ttyS0. + */ +static struct resource omixp_uart_resources[] = { + { + .start = IXP4XX_UART2_BASE_PHYS, + .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, + .flags = IORESOURCE_MEM, + }, { + .start = IXP4XX_UART1_BASE_PHYS, + .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct plat_serial8250_port omixp_uart_data[] = { + { + .mapbase = IXP4XX_UART2_BASE_PHYS, + .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, + .irq = IRQ_IXP4XX_UART2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = IXP4XX_UART_XTAL, + }, { + .mapbase = IXP4XX_UART1_BASE_PHYS, + .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, + .irq = IRQ_IXP4XX_UART1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = IXP4XX_UART_XTAL, + }, { + /* list termination */ + } +}; + +static struct platform_device omixp_uart = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev.platform_data = omixp_uart_data, + .num_resources = 2, + .resource = omixp_uart_resources, +}; + +static struct gpio_led mic256_led_pins[] = { + { + .name = "LED-A", + .gpio = 7, + }, +}; + +static struct gpio_led_platform_data mic256_led_data = { + .num_leds = ARRAY_SIZE(mic256_led_pins), + .leds = mic256_led_pins, +}; + +static struct platform_device mic256_leds = { + .name = "leds-gpio", + .id = -1, + .dev.platform_data = &mic256_led_data, +}; + +/* Built-in 10/100 Ethernet MAC interfaces */ +static struct eth_plat_info ixdp425_plat_eth[] = { + { + .phy = 0, + .rxq = 3, + .txreadyq = 20, + }, { + .phy = 1, + .rxq = 4, + .txreadyq = 21, + }, +}; + +static struct platform_device ixdp425_eth[] = { + { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEB, + .dev.platform_data = ixdp425_plat_eth, + }, { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEC, + .dev.platform_data = ixdp425_plat_eth + 1, + }, +}; + + +static struct platform_device *devixp_pldev[] __initdata = { + &omixp_uart, + &omixp_flash_device[0], + &ixdp425_eth[0], + &ixdp425_eth[1], +}; + +static struct platform_device *mic256_pldev[] __initdata = { + &omixp_uart, + &omixp_flash_device[0], + &mic256_leds, + &ixdp425_eth[0], + &ixdp425_eth[1], +}; + +static struct platform_device *miccpt_pldev[] __initdata = { + &omixp_uart, + &omixp_flash_device[0], + &omixp_flash_device[1], + &ixdp425_eth[0], + &ixdp425_eth[1], +}; + +static void __init omixp_init(void) +{ + ixp4xx_sys_init(); + + /* 16MiB Boot Flash */ + omixp_flash_resources[0].start = IXP4XX_EXP_BUS_BASE(0); + omixp_flash_resources[0].end = IXP4XX_EXP_BUS_END(0); + + /* 32 MiB Data Flash */ + omixp_flash_resources[1].start = IXP4XX_EXP_BUS_BASE(2); + omixp_flash_resources[1].end = IXP4XX_EXP_BUS_END(2); + + if (machine_is_devixp()) + platform_add_devices(devixp_pldev, ARRAY_SIZE(devixp_pldev)); + else if (machine_is_miccpt()) + platform_add_devices(miccpt_pldev, ARRAY_SIZE(miccpt_pldev)); + else if (machine_is_mic256()) + platform_add_devices(mic256_pldev, ARRAY_SIZE(mic256_pldev)); +} + +#ifdef CONFIG_MACH_DEVIXP +MACHINE_START(DEVIXP, "Omicron DEVIXP") + .boot_params = 0x100, + .map_io = ixp4xx_map_io, + .init_irq = ixp4xx_init_irq, + .timer = &ixp4xx_timer, + .init_machine = omixp_init, +MACHINE_END +#endif + +#ifdef CONFIG_MACH_MICCPT +MACHINE_START(MICCPT, "Omicron MICCPT") + .boot_params = 0x100, + .map_io = ixp4xx_map_io, + .init_irq = ixp4xx_init_irq, + .timer = &ixp4xx_timer, + .init_machine = omixp_init, +#if defined(CONFIG_PCI) + .dma_zone_size = SZ_64M, +#endif +MACHINE_END +#endif + +#ifdef CONFIG_MACH_MIC256 +MACHINE_START(MIC256, "Omicron MIC256") + .boot_params = 0x100, + .map_io = ixp4xx_map_io, + .init_irq = ixp4xx_init_irq, + .timer = &ixp4xx_timer, + .init_machine = omixp_init, +MACHINE_END +#endif -- cgit v0.10.2 From 1abd328ee5e2e870fa035e7882e7a278127b4ccf Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Mon, 19 Sep 2011 20:09:01 +0900 Subject: ARM: EXYNOS4: convert boot_params to atag_offset Based on "ARM: introduce atag_offset to replace boot_params" by Nicolas Pitre (2bb9839e312ed55a6d5824ffa6077ce3d7d63b1e). Since boot_params variable is deleted from machine_desc, the variable is modified in the newer board files. Cc: Nicolas Pitre Signed-off-by: Tushar Behera [kgene.kim@samsung.com: added fixing for smdkv310] Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos4/mach-origen.c b/arch/arm/mach-exynos4/mach-origen.c index ed59f86..b5f6f38 100644 --- a/arch/arm/mach-exynos4/mach-origen.c +++ b/arch/arm/mach-exynos4/mach-origen.c @@ -100,7 +100,7 @@ static void __init origen_machine_init(void) MACHINE_START(ORIGEN, "ORIGEN") /* Maintainer: JeongHyeon Kim */ - .boot_params = S5P_PA_SDRAM + 0x100, + .atag_offset = 0x100, .init_irq = exynos4_init_irq, .map_io = origen_map_io, .init_machine = origen_machine_init, diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c index a16eb56..2c1a076 100644 --- a/arch/arm/mach-exynos4/mach-smdkv310.c +++ b/arch/arm/mach-exynos4/mach-smdkv310.c @@ -324,7 +324,7 @@ static void __init smdkv310_machine_init(void) MACHINE_START(SMDKV310, "SMDKV310") /* Maintainer: Kukjin Kim */ /* Maintainer: Changhwan Youn */ - .boot_params = S5P_PA_SDRAM + 0x100, + .atag_offset = 0x100, .init_irq = exynos4_init_irq, .map_io = smdkv310_map_io, .init_machine = smdkv310_machine_init, @@ -333,7 +333,7 @@ MACHINE_END MACHINE_START(SMDKC210, "SMDKC210") /* Maintainer: Kukjin Kim */ - .boot_params = S5P_PA_SDRAM + 0x100, + .atag_offset = 0x100, .init_irq = exynos4_init_irq, .map_io = smdkv310_map_io, .init_machine = smdkv310_machine_init, -- cgit v0.10.2 From 637c2afa57ec9cd0ddc8879ea0cda4d8835ba71d Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Tue, 4 Oct 2011 17:02:58 +0900 Subject: ARM: EXYNOS4: Add support PPI in external GIC To support PPI in external GIC of EXYNOS4 SoCs, gic_arch_extn.irq_eoi, irq_unmask and irq_mask are fixed. This patch is necessary because external GIC of EXYNOS4 cannot support register banking. Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index 02ec52a..35fe842 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c @@ -198,20 +198,25 @@ void __init exynos4_init_clocks(int xtal) exynos4_setup_clocks(); } -static void exynos4_gic_irq_eoi(struct irq_data *d) +static void exynos4_gic_irq_fix_base(struct irq_data *d) { struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); gic_data->cpu_base = S5P_VA_GIC_CPU + (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); + + gic_data->dist_base = S5P_VA_GIC_DIST + + (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); } void __init exynos4_init_irq(void) { int irq; - gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); - gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi; + gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); + gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base; + gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base; + gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base; for (irq = 0; irq < MAX_COMBINER_NR; irq++) { -- cgit v0.10.2 From 3a062281129229b50e06547af3110f8eccd2f4e4 Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Tue, 4 Oct 2011 17:02:58 +0900 Subject: ARM: EXYNOS4: Add support MCT PPI for EXYNOS4212 This patch implements clock event timer using MCT PPI and make EXYNOS4212 use MCT PPI instead of MCT SPI. Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S index d7a1e28..61393dc 100644 --- a/arch/arm/mach-exynos4/include/mach/entry-macro.S +++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S @@ -80,4 +80,10 @@ /* As above, this assumes that irqstat and base are preserved.. */ .macro test_for_ltirq, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + mov \tmp, #0 + cmp \irqnr, #28 + moveq \tmp, #1 + streq \irqstat, [\base, #GIC_CPU_EOI] + cmp \tmp, #0 .endm diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h index f8952f8..2d3f6bc 100644 --- a/arch/arm/mach-exynos4/include/mach/irqs.h +++ b/arch/arm/mach-exynos4/include/mach/irqs.h @@ -19,6 +19,8 @@ #define IRQ_PPI(x) S5P_IRQ(x+16) +#define IRQ_MCT_LOCALTIMER IRQ_PPI(12) + /* SPI: Shared Peripheral Interrupt */ #define IRQ_SPI(x) S5P_IRQ(x+32) diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c index ddd8686..f43f3fa 100644 --- a/arch/arm/mach-exynos4/mct.c +++ b/arch/arm/mach-exynos4/mct.c @@ -20,12 +20,23 @@ #include #include +#include + +#include + #include +#include #include #include +enum { + MCT_INT_SPI, + MCT_INT_PPI +}; + static unsigned long clk_cnt_per_tick; static unsigned long clk_rate; +static unsigned int mct_int_type; struct mct_clock_event_device { struct clock_event_device *evt; @@ -321,9 +332,8 @@ static inline void exynos4_tick_set_mode(enum clock_event_mode mode, } } -static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id) +static inline int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) { - struct mct_clock_event_device *mevt = dev_id; struct clock_event_device *evt = mevt->evt; /* @@ -335,7 +345,20 @@ static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id) exynos4_mct_tick_stop(mevt); /* Clear the MCT tick interrupt */ - exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); + if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) { + exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); + return 1; + } else { + return 0; + } +} + +static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id) +{ + struct mct_clock_event_device *mevt = dev_id; + struct clock_event_device *evt = mevt->evt; + + exynos4_mct_tick_clear(mevt); evt->event_handler(evt); @@ -384,13 +407,17 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt) exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET); - if (cpu == 0) { - mct_tick0_event_irq.dev_id = &mct_tick[cpu]; - setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq); + if (mct_int_type == MCT_INT_SPI) { + if (cpu == 0) { + mct_tick0_event_irq.dev_id = &mct_tick[cpu]; + setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq); + } else { + mct_tick1_event_irq.dev_id = &mct_tick[cpu]; + setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq); + irq_set_affinity(IRQ_MCT_L1, cpumask_of(1)); + } } else { - mct_tick1_event_irq.dev_id = &mct_tick[cpu]; - setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq); - irq_set_affinity(IRQ_MCT_L1, cpumask_of(1)); + gic_enable_ppi(IRQ_MCT_LOCALTIMER); } } @@ -404,7 +431,10 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt) int local_timer_ack(void) { - return 0; + unsigned int cpu = smp_processor_id(); + struct mct_clock_event_device *mevt = &mct_tick[cpu]; + + return exynos4_mct_tick_clear(mevt); } #endif /* CONFIG_LOCAL_TIMERS */ @@ -419,6 +449,11 @@ static void __init exynos4_timer_resources(void) static void __init exynos4_timer_init(void) { + if (soc_is_exynos4210()) + mct_int_type = MCT_INT_SPI; + else + mct_int_type = MCT_INT_PPI; + exynos4_timer_resources(); exynos4_clocksource_init(); exynos4_clockevent_init(); -- cgit v0.10.2 From e6a275a8f92392f27e3accd6182d52627ef37258 Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Tue, 4 Oct 2011 17:08:56 +0900 Subject: ARM: EXYNOS4: Add support new EXYNOS4412 SoC This patch adds Samsung EXYNOS4412 SoC support. The EXYNOS4412 integrates a ARM Cortex A9 quad-core. Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig index c595bb0..c255d6f 100644 --- a/arch/arm/mach-exynos4/Kconfig +++ b/arch/arm/mach-exynos4/Kconfig @@ -20,6 +20,11 @@ config SOC_EXYNOS4212 help Enable EXYNOS4212 SoC support +config SOC_EXYNOS4412 + bool + help + Enable EXYNOS4412 SoC support + config EXYNOS4_MCT bool default y diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index 35fe842..940bc12 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c @@ -191,7 +191,7 @@ void __init exynos4_init_clocks(int xtal) if (soc_is_exynos4210()) exynos4210_register_clocks(); - else if (soc_is_exynos4212()) + else if (soc_is_exynos4212() || soc_is_exynos4412()) exynos4212_register_clocks(); exynos4_register_clocks(); @@ -255,7 +255,7 @@ static int __init exynos4_l2x0_cache_init(void) if (soc_is_exynos4210()) __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); - else if (soc_is_exynos4212()) + else if (soc_is_exynos4212() || soc_is_exynos4412()) __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); /* L2X0 Prefetch Control */ diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c index 909507b..7b0a28f 100644 --- a/arch/arm/plat-s5p/cpu.c +++ b/arch/arm/plat-s5p/cpu.c @@ -34,6 +34,7 @@ static const char name_s5pc100[] = "S5PC100"; static const char name_s5pv210[] = "S5PV210/S5PC110"; static const char name_exynos4210[] = "EXYNOS4210"; static const char name_exynos4212[] = "EXYNOS4212"; +static const char name_exynos4412[] = "EXYNOS4412"; static struct cpu_table cpu_ids[] __initdata = { { @@ -84,6 +85,14 @@ static struct cpu_table cpu_ids[] __initdata = { .init_uarts = exynos4_init_uarts, .init = exynos4_init, .name = name_exynos4212, + }, { + .idcode = EXYNOS4412_CPU_ID, + .idmask = EXYNOS4_CPU_MASK, + .map_io = exynos4_map_io, + .init_clocks = exynos4_init_clocks, + .init_uarts = exynos4_init_uarts, + .init = exynos4_init, + .name = name_exynos4412, }, }; diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 1bbbbb4..54f370f 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -40,6 +40,7 @@ extern unsigned long samsung_cpu_id; #define EXYNOS4210_CPU_ID 0x43210000 #define EXYNOS4212_CPU_ID 0x43220000 +#define EXYNOS4412_CPU_ID 0xE4412200 #define EXYNOS4_CPU_MASK 0xFFFE0000 #define IS_SAMSUNG_CPU(name, id, mask) \ @@ -56,6 +57,7 @@ IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK) IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK) IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) +IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \ @@ -108,6 +110,12 @@ IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) # define soc_is_exynos4212() 0 #endif +#if defined(CONFIG_SOC_EXYNOS4412) +# define soc_is_exynos4412() is_samsung_exynos4412() +#else +# define soc_is_exynos4412() 0 +#endif + #define EXYNOS4210_REV_0 (0x0) #define EXYNOS4210_REV_1_0 (0x10) #define EXYNOS4210_REV_1_1 (0x11) -- cgit v0.10.2 From b88b1cc72e2bbb55c56f2df55b5ad59a18ad1464 Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Tue, 4 Oct 2011 17:08:56 +0900 Subject: ARM: EXYNOS4: Add support clock for EXYNOS4412 This patch makes EXYNOS4412 use same clock code for EXYNOS4212 because the clock hierarchy of both SoCs are same. Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index f26aea3..2a037cc 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c @@ -1149,7 +1149,7 @@ static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) if (soc_is_exynos4210()) return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508); - else if (soc_is_exynos4212()) + else if (soc_is_exynos4212() || soc_is_exynos4412()) return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0)); else return 0; @@ -1200,7 +1200,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void) vpllsrc = clk_get_rate(&clk_vpllsrc.clk); vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), __raw_readl(S5P_VPLL_CON1), pll_4650c); - } else if (soc_is_exynos4212()) { + } else if (soc_is_exynos4212() || soc_is_exynos4412()) { apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0)); mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0)); epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0), -- cgit v0.10.2 From 90a454b4c5ef16ec71797b3dcaf454e604c786a3 Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Tue, 4 Oct 2011 17:08:57 +0900 Subject: ARM: EXYNOS4: Add functions for gic interrupt handling This patch adds two functions for gic interrupt handling. 1. Add interrupt handling of 4 cores. 2. Dynamically set gic bank offset according to the type of soc. Gic bank offset of EXYNOS4412 is 0x4000 while the offset of EXYNOS4210 and EXYNOS4212 is 0x8000. This patch is necessary because EXYNOS4 socs cannot support GIC register banking as described in commit aab74d3e75364. Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index 940bc12..a348434 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c @@ -32,6 +32,8 @@ #include #include +unsigned int gic_bank_offset __read_mostly; + extern int combiner_init(unsigned int combiner_nr, void __iomem *base, unsigned int irq_start); extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); @@ -203,16 +205,18 @@ static void exynos4_gic_irq_fix_base(struct irq_data *d) struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); gic_data->cpu_base = S5P_VA_GIC_CPU + - (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); + (gic_bank_offset * smp_processor_id()); gic_data->dist_base = S5P_VA_GIC_DIST + - (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); + (gic_bank_offset * smp_processor_id()); } void __init exynos4_init_irq(void) { int irq; + gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; + gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base; gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base; diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S index 61393dc..4c9adbd 100644 --- a/arch/arm/mach-exynos4/include/mach/entry-macro.S +++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S @@ -17,12 +17,25 @@ .endm .macro get_irqnr_preamble, base, tmp - ldr \base, =gic_cpu_base_addr + mov \tmp, #0 + + mrc p15, 0, \base, c0, c0, 5 + and \base, \base, #3 + cmp \base, #0 + beq 1f + + ldr \tmp, =gic_bank_offset + ldr \tmp, [\tmp] + cmp \base, #1 + beq 1f + + cmp \base, #2 + addeq \tmp, \tmp, \tmp + addne \tmp, \tmp, \tmp, LSL #1 + +1: ldr \base, =gic_cpu_base_addr ldr \base, [\base] - mrc p15, 0, \tmp, c0, c0, 5 - and \tmp, \tmp, #3 - cmp \tmp, #1 - addeq \base, \base, #EXYNOS4_GIC_BANK_OFFSET + add \base, \base, \tmp .endm .macro arch_ret_to_user, tmp1, tmp2 diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h index 7073ac7..9f97eb8 100644 --- a/arch/arm/mach-exynos4/include/mach/map.h +++ b/arch/arm/mach-exynos4/include/mach/map.h @@ -62,7 +62,6 @@ #define EXYNOS4_PA_GIC_CPU 0x10480000 #define EXYNOS4_PA_GIC_DIST 0x10490000 -#define EXYNOS4_GIC_BANK_OFFSET 0x8000 #define EXYNOS4_PA_COREPERI 0x10500000 #define EXYNOS4_PA_TWD 0x10500600 diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c index a3346e3..d5f0f29 100644 --- a/arch/arm/mach-exynos4/platsmp.c +++ b/arch/arm/mach-exynos4/platsmp.c @@ -32,6 +32,7 @@ #include +extern unsigned int gic_bank_offset; extern void exynos4_secondary_startup(void); #define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ @@ -67,9 +68,9 @@ static DEFINE_SPINLOCK(boot_lock); static void __cpuinit exynos4_gic_secondary_init(void) { void __iomem *dist_base = S5P_VA_GIC_DIST + - (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); + (gic_bank_offset * smp_processor_id()); void __iomem *cpu_base = S5P_VA_GIC_CPU + - (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); + (gic_bank_offset * smp_processor_id()); int i; /* -- cgit v0.10.2 From c8987470a3a3e56295ee8c9130f5298e807bf4f7 Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Tue, 4 Oct 2011 17:09:26 +0900 Subject: ARM: EXYNOS4: Add MCT support for EXYNOS4412 Current MCT implementation only provide 2 event timers, thus cannot support EXYNOS4412 which has 4 CPU cores. This patch fixes MCT implementation to support SoCs with 4 cores. Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos4/include/mach/regs-mct.h b/arch/arm/mach-exynos4/include/mach/regs-mct.h index ca9c843..80dd02a 100644 --- a/arch/arm/mach-exynos4/include/mach/regs-mct.h +++ b/arch/arm/mach-exynos4/include/mach/regs-mct.h @@ -31,8 +31,9 @@ #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) -#define EXYNOS4_MCT_L0_BASE EXYNOS4_MCTREG(0x300) -#define EXYNOS4_MCT_L1_BASE EXYNOS4_MCTREG(0x400) +#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) +#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) +#define EXYNOS4_MCT_L_MASK (0xffffff00) #define MCT_L_TCNTB_OFFSET (0x00) #define MCT_L_ICNTB_OFFSET (0x08) diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c index f43f3fa..eb182f2 100644 --- a/arch/arm/mach-exynos4/mct.c +++ b/arch/arm/mach-exynos4/mct.c @@ -41,9 +41,10 @@ static unsigned int mct_int_type; struct mct_clock_event_device { struct clock_event_device *evt; void __iomem *base; + char name[10]; }; -struct mct_clock_event_device mct_tick[2]; +struct mct_clock_event_device mct_tick[NR_CPUS]; static void exynos4_mct_write(unsigned int value, void *addr) { @@ -53,57 +54,53 @@ static void exynos4_mct_write(unsigned int value, void *addr) __raw_writel(value, addr); - switch ((u32) addr) { - case (u32) EXYNOS4_MCT_G_TCON: - stat_addr = EXYNOS4_MCT_G_WSTAT; - mask = 1 << 16; /* G_TCON write status */ - break; - case (u32) EXYNOS4_MCT_G_COMP0_L: - stat_addr = EXYNOS4_MCT_G_WSTAT; - mask = 1 << 0; /* G_COMP0_L write status */ - break; - case (u32) EXYNOS4_MCT_G_COMP0_U: - stat_addr = EXYNOS4_MCT_G_WSTAT; - mask = 1 << 1; /* G_COMP0_U write status */ - break; - case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR: - stat_addr = EXYNOS4_MCT_G_WSTAT; - mask = 1 << 2; /* G_COMP0_ADD_INCR write status */ - break; - case (u32) EXYNOS4_MCT_G_CNT_L: - stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; - mask = 1 << 0; /* G_CNT_L write status */ - break; - case (u32) EXYNOS4_MCT_G_CNT_U: - stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; - mask = 1 << 1; /* G_CNT_U write status */ - break; - case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCON_OFFSET): - stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET; - mask = 1 << 3; /* L0_TCON write status */ - break; - case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCON_OFFSET): - stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET; - mask = 1 << 3; /* L1_TCON write status */ - break; - case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCNTB_OFFSET): - stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET; - mask = 1 << 0; /* L0_TCNTB write status */ - break; - case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCNTB_OFFSET): - stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET; - mask = 1 << 0; /* L1_TCNTB write status */ - break; - case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_ICNTB_OFFSET): - stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET; - mask = 1 << 1; /* L0_ICNTB write status */ - break; - case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_ICNTB_OFFSET): - stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET; - mask = 1 << 1; /* L1_ICNTB write status */ - break; - default: - return; + if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) { + u32 base = (u32) addr & EXYNOS4_MCT_L_MASK; + switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) { + case (u32) MCT_L_TCON_OFFSET: + stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET; + mask = 1 << 3; /* L_TCON write status */ + break; + case (u32) MCT_L_ICNTB_OFFSET: + stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET; + mask = 1 << 1; /* L_ICNTB write status */ + break; + case (u32) MCT_L_TCNTB_OFFSET: + stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET; + mask = 1 << 0; /* L_TCNTB write status */ + break; + default: + return; + } + } else { + switch ((u32) addr) { + case (u32) EXYNOS4_MCT_G_TCON: + stat_addr = EXYNOS4_MCT_G_WSTAT; + mask = 1 << 16; /* G_TCON write status */ + break; + case (u32) EXYNOS4_MCT_G_COMP0_L: + stat_addr = EXYNOS4_MCT_G_WSTAT; + mask = 1 << 0; /* G_COMP0_L write status */ + break; + case (u32) EXYNOS4_MCT_G_COMP0_U: + stat_addr = EXYNOS4_MCT_G_WSTAT; + mask = 1 << 1; /* G_COMP0_U write status */ + break; + case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR: + stat_addr = EXYNOS4_MCT_G_WSTAT; + mask = 1 << 2; /* G_COMP0_ADD_INCR w status */ + break; + case (u32) EXYNOS4_MCT_G_CNT_L: + stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; + mask = 1 << 0; /* G_CNT_L write status */ + break; + case (u32) EXYNOS4_MCT_G_CNT_U: + stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; + mask = 1 << 1; /* G_CNT_U write status */ + break; + default: + return; + } } /* Wait maximum 1 ms until written values are applied */ @@ -332,7 +329,7 @@ static inline void exynos4_tick_set_mode(enum clock_event_mode mode, } } -static inline int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) +static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) { struct clock_event_device *evt = mevt->evt; @@ -383,14 +380,10 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt) mct_tick[cpu].evt = evt; - if (cpu == 0) { - mct_tick[cpu].base = EXYNOS4_MCT_L0_BASE; - evt->name = "mct_tick0"; - } else { - mct_tick[cpu].base = EXYNOS4_MCT_L1_BASE; - evt->name = "mct_tick1"; - } + mct_tick[cpu].base = EXYNOS4_MCT_L_BASE(cpu); + sprintf(mct_tick[cpu].name, "mct_tick%d", cpu); + evt->name = mct_tick[cpu].name; evt->cpumask = cpumask_of(cpu); evt->set_next_event = exynos4_tick_set_next_event; evt->set_mode = exynos4_tick_set_mode; -- cgit v0.10.2 From 31451afd2480caf3ae15da56cf9fc3cb3fb821cb Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Tue, 4 Oct 2011 17:09:26 +0900 Subject: ARM: EXYNOS4: Add support SMDK4412 Board SMDK4412 board is same as a SMDK4212 board except that it has EXYNOS4412 SoC, thus it can share machine code with SMDK4212. This patch renames mach-smdk4212.c to mach-smdk4x12.c to support both SMDK4212 and SMDK4412 board with one machine file. Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig index c255d6f..fec2385 100644 --- a/arch/arm/mach-exynos4/Kconfig +++ b/arch/arm/mach-exynos4/Kconfig @@ -248,6 +248,15 @@ config MACH_SMDK4212 help Machine support for Samsung SMDK4212 +comment "EXYNOS4412 Boards" + +config MACH_SMDK4412 + bool "SMDK4412" + select SOC_EXYNOS4412 + select MACH_SMDK4212 + help + Machine support for Samsung SMDK4412 + endmenu comment "Configuration for HSMMC bus width" diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile index e19cd12..c9b2e1f 100644 --- a/arch/arm/mach-exynos4/Makefile +++ b/arch/arm/mach-exynos4/Makefile @@ -34,7 +34,8 @@ obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o obj-$(CONFIG_MACH_NURI) += mach-nuri.o obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o -obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4212.o +obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o +obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o # device support diff --git a/arch/arm/mach-exynos4/mach-smdk4212.c b/arch/arm/mach-exynos4/mach-smdk4212.c deleted file mode 100644 index 3479a93..0000000 --- a/arch/arm/mach-exynos4/mach-smdk4212.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/mach-smdk4212.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -/* Following are default values for UCON, ULCON and UFCON UART registers */ -#define SMDK4212_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI | \ - S3C2443_UCON_RXERR_IRQEN) - -#define SMDK4212_ULCON_DEFAULT S3C2410_LCON_CS8 - -#define SMDK4212_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG4 | \ - S5PV210_UFCON_RXTRIG4) - -static struct s3c2410_uartcfg smdk4212_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = SMDK4212_UCON_DEFAULT, - .ulcon = SMDK4212_ULCON_DEFAULT, - .ufcon = SMDK4212_UFCON_DEFAULT, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = SMDK4212_UCON_DEFAULT, - .ulcon = SMDK4212_ULCON_DEFAULT, - .ufcon = SMDK4212_UFCON_DEFAULT, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = SMDK4212_UCON_DEFAULT, - .ulcon = SMDK4212_ULCON_DEFAULT, - .ufcon = SMDK4212_UFCON_DEFAULT, - }, - [3] = { - .hwport = 3, - .flags = 0, - .ucon = SMDK4212_UCON_DEFAULT, - .ulcon = SMDK4212_ULCON_DEFAULT, - .ufcon = SMDK4212_UFCON_DEFAULT, - }, -}; - -static struct s3c_sdhci_platdata smdk4212_hsmmc2_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_INTERNAL, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, -#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT - .max_width = 8, - .host_caps = MMC_CAP_8_BIT_DATA, -#endif -}; - -static struct s3c_sdhci_platdata smdk4212_hsmmc3_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_INTERNAL, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, -}; - -static struct regulator_consumer_supply max8997_buck1 = - REGULATOR_SUPPLY("vdd_arm", NULL); - -static struct regulator_consumer_supply max8997_buck2 = - REGULATOR_SUPPLY("vdd_int", NULL); - -static struct regulator_consumer_supply max8997_buck3 = - REGULATOR_SUPPLY("vdd_g3d", NULL); - -static struct regulator_init_data max8997_buck1_data = { - .constraints = { - .name = "VDD_ARM_SMDK4212", - .min_uV = 925000, - .max_uV = 1350000, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max8997_buck1, -}; - -static struct regulator_init_data max8997_buck2_data = { - .constraints = { - .name = "VDD_INT_SMDK4212", - .min_uV = 950000, - .max_uV = 1150000, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max8997_buck2, -}; - -static struct regulator_init_data max8997_buck3_data = { - .constraints = { - .name = "VDD_G3D_SMDK4212", - .min_uV = 950000, - .max_uV = 1150000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max8997_buck3, -}; - -static struct max8997_regulator_data smdk4212_max8997_regulators[] = { - { MAX8997_BUCK1, &max8997_buck1_data }, - { MAX8997_BUCK2, &max8997_buck2_data }, - { MAX8997_BUCK3, &max8997_buck3_data }, -}; - -static struct max8997_platform_data smdk4212_max8997_pdata = { - .num_regulators = ARRAY_SIZE(smdk4212_max8997_regulators), - .regulators = smdk4212_max8997_regulators, - - .buck1_voltage[0] = 1100000, /* 1.1V */ - .buck1_voltage[1] = 1100000, /* 1.1V */ - .buck1_voltage[2] = 1100000, /* 1.1V */ - .buck1_voltage[3] = 1100000, /* 1.1V */ - .buck1_voltage[4] = 1100000, /* 1.1V */ - .buck1_voltage[5] = 1100000, /* 1.1V */ - .buck1_voltage[6] = 1000000, /* 1.0V */ - .buck1_voltage[7] = 950000, /* 0.95V */ - - .buck2_voltage[0] = 1100000, /* 1.1V */ - .buck2_voltage[1] = 1000000, /* 1.0V */ - .buck2_voltage[2] = 950000, /* 0.95V */ - .buck2_voltage[3] = 900000, /* 0.9V */ - .buck2_voltage[4] = 1100000, /* 1.1V */ - .buck2_voltage[5] = 1000000, /* 1.0V */ - .buck2_voltage[6] = 950000, /* 0.95V */ - .buck2_voltage[7] = 900000, /* 0.9V */ - - .buck5_voltage[0] = 1100000, /* 1.1V */ - .buck5_voltage[1] = 1100000, /* 1.1V */ - .buck5_voltage[2] = 1100000, /* 1.1V */ - .buck5_voltage[3] = 1100000, /* 1.1V */ - .buck5_voltage[4] = 1100000, /* 1.1V */ - .buck5_voltage[5] = 1100000, /* 1.1V */ - .buck5_voltage[6] = 1100000, /* 1.1V */ - .buck5_voltage[7] = 1100000, /* 1.1V */ -}; - -static struct i2c_board_info smdk4212_i2c_devs0[] __initdata = { - { - I2C_BOARD_INFO("max8997", 0x66), - .platform_data = &smdk4212_max8997_pdata, - } -}; - -static struct i2c_board_info smdk4212_i2c_devs1[] __initdata = { - { I2C_BOARD_INFO("wm8994", 0x1a), } -}; - -static struct i2c_board_info smdk4212_i2c_devs3[] __initdata = { - /* nothing here yet */ -}; - -static struct i2c_board_info smdk4212_i2c_devs7[] __initdata = { - /* nothing here yet */ -}; - -static struct samsung_bl_gpio_info smdk4212_bl_gpio_info = { - .no = EXYNOS4_GPD0(1), - .func = S3C_GPIO_SFN(2), -}; - -static struct platform_pwm_backlight_data smdk4212_bl_data = { - .pwm_id = 1, - .pwm_period_ns = 1000, -}; - -static uint32_t smdk4212_keymap[] __initdata = { - /* KEY(row, col, keycode) */ - KEY(1, 0, KEY_D), KEY(1, 1, KEY_A), KEY(1, 2, KEY_B), - KEY(1, 3, KEY_E), KEY(1, 4, KEY_C) -}; - -static struct matrix_keymap_data smdk4212_keymap_data __initdata = { - .keymap = smdk4212_keymap, - .keymap_size = ARRAY_SIZE(smdk4212_keymap), -}; - -static struct samsung_keypad_platdata smdk4212_keypad_data __initdata = { - .keymap_data = &smdk4212_keymap_data, - .rows = 2, - .cols = 5, -}; - -static struct platform_device *smdk4212_devices[] __initdata = { - &s3c_device_hsmmc2, - &s3c_device_hsmmc3, - &s3c_device_i2c0, - &s3c_device_i2c1, - &s3c_device_i2c3, - &s3c_device_i2c7, - &s3c_device_rtc, - &s3c_device_wdt, - &samsung_device_keypad, -}; - -static void __init smdk4212_map_io(void) -{ - clk_xusbxti.rate = 24000000; - - s5p_init_io(NULL, 0, S5P_VA_CHIPID); - s3c24xx_init_clocks(clk_xusbxti.rate); - s3c24xx_init_uarts(smdk4212_uartcfgs, ARRAY_SIZE(smdk4212_uartcfgs)); -} - -static void __init smdk4212_machine_init(void) -{ - s3c_i2c0_set_platdata(NULL); - i2c_register_board_info(0, smdk4212_i2c_devs0, - ARRAY_SIZE(smdk4212_i2c_devs0)); - - s3c_i2c1_set_platdata(NULL); - i2c_register_board_info(1, smdk4212_i2c_devs1, - ARRAY_SIZE(smdk4212_i2c_devs1)); - - s3c_i2c3_set_platdata(NULL); - i2c_register_board_info(3, smdk4212_i2c_devs3, - ARRAY_SIZE(smdk4212_i2c_devs3)); - - s3c_i2c7_set_platdata(NULL); - i2c_register_board_info(7, smdk4212_i2c_devs7, - ARRAY_SIZE(smdk4212_i2c_devs7)); - - samsung_bl_set(&smdk4212_bl_gpio_info, &smdk4212_bl_data); - - samsung_keypad_set_platdata(&smdk4212_keypad_data); - - s3c_sdhci2_set_platdata(&smdk4212_hsmmc2_pdata); - s3c_sdhci3_set_platdata(&smdk4212_hsmmc3_pdata); - - platform_add_devices(smdk4212_devices, ARRAY_SIZE(smdk4212_devices)); -} - -MACHINE_START(SMDK4212, "SMDK4212") - /* Maintainer: Kukjin Kim */ - .boot_params = S5P_PA_SDRAM + 0x100, - .init_irq = exynos4_init_irq, - .map_io = smdk4212_map_io, - .init_machine = smdk4212_machine_init, - .timer = &exynos4_timer, -MACHINE_END diff --git a/arch/arm/mach-exynos4/mach-smdk4x12.c b/arch/arm/mach-exynos4/mach-smdk4x12.c new file mode 100644 index 0000000..fcf2e0e --- /dev/null +++ b/arch/arm/mach-exynos4/mach-smdk4x12.c @@ -0,0 +1,302 @@ +/* + * linux/arch/arm/mach-exynos4/mach-smdk4x12.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define SMDK4X12_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define SMDK4X12_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + +static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = SMDK4X12_UCON_DEFAULT, + .ulcon = SMDK4X12_ULCON_DEFAULT, + .ufcon = SMDK4X12_UFCON_DEFAULT, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = SMDK4X12_UCON_DEFAULT, + .ulcon = SMDK4X12_ULCON_DEFAULT, + .ufcon = SMDK4X12_UFCON_DEFAULT, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = SMDK4X12_UCON_DEFAULT, + .ulcon = SMDK4X12_ULCON_DEFAULT, + .ufcon = SMDK4X12_UFCON_DEFAULT, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = SMDK4X12_UCON_DEFAULT, + .ulcon = SMDK4X12_ULCON_DEFAULT, + .ufcon = SMDK4X12_UFCON_DEFAULT, + }, +}; + +static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_INTERNAL, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, +#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA, +#endif +}; + +static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_INTERNAL, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, +}; + +static struct regulator_consumer_supply max8997_buck1 = + REGULATOR_SUPPLY("vdd_arm", NULL); + +static struct regulator_consumer_supply max8997_buck2 = + REGULATOR_SUPPLY("vdd_int", NULL); + +static struct regulator_consumer_supply max8997_buck3 = + REGULATOR_SUPPLY("vdd_g3d", NULL); + +static struct regulator_init_data max8997_buck1_data = { + .constraints = { + .name = "VDD_ARM_SMDK4X12", + .min_uV = 925000, + .max_uV = 1350000, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8997_buck1, +}; + +static struct regulator_init_data max8997_buck2_data = { + .constraints = { + .name = "VDD_INT_SMDK4X12", + .min_uV = 950000, + .max_uV = 1150000, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8997_buck2, +}; + +static struct regulator_init_data max8997_buck3_data = { + .constraints = { + .name = "VDD_G3D_SMDK4X12", + .min_uV = 950000, + .max_uV = 1150000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8997_buck3, +}; + +static struct max8997_regulator_data smdk4x12_max8997_regulators[] = { + { MAX8997_BUCK1, &max8997_buck1_data }, + { MAX8997_BUCK2, &max8997_buck2_data }, + { MAX8997_BUCK3, &max8997_buck3_data }, +}; + +static struct max8997_platform_data smdk4x12_max8997_pdata = { + .num_regulators = ARRAY_SIZE(smdk4x12_max8997_regulators), + .regulators = smdk4x12_max8997_regulators, + + .buck1_voltage[0] = 1100000, /* 1.1V */ + .buck1_voltage[1] = 1100000, /* 1.1V */ + .buck1_voltage[2] = 1100000, /* 1.1V */ + .buck1_voltage[3] = 1100000, /* 1.1V */ + .buck1_voltage[4] = 1100000, /* 1.1V */ + .buck1_voltage[5] = 1100000, /* 1.1V */ + .buck1_voltage[6] = 1000000, /* 1.0V */ + .buck1_voltage[7] = 950000, /* 0.95V */ + + .buck2_voltage[0] = 1100000, /* 1.1V */ + .buck2_voltage[1] = 1000000, /* 1.0V */ + .buck2_voltage[2] = 950000, /* 0.95V */ + .buck2_voltage[3] = 900000, /* 0.9V */ + .buck2_voltage[4] = 1100000, /* 1.1V */ + .buck2_voltage[5] = 1000000, /* 1.0V */ + .buck2_voltage[6] = 950000, /* 0.95V */ + .buck2_voltage[7] = 900000, /* 0.9V */ + + .buck5_voltage[0] = 1100000, /* 1.1V */ + .buck5_voltage[1] = 1100000, /* 1.1V */ + .buck5_voltage[2] = 1100000, /* 1.1V */ + .buck5_voltage[3] = 1100000, /* 1.1V */ + .buck5_voltage[4] = 1100000, /* 1.1V */ + .buck5_voltage[5] = 1100000, /* 1.1V */ + .buck5_voltage[6] = 1100000, /* 1.1V */ + .buck5_voltage[7] = 1100000, /* 1.1V */ +}; + +static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = { + { + I2C_BOARD_INFO("max8997", 0x66), + .platform_data = &smdk4x12_max8997_pdata, + } +}; + +static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = { + { I2C_BOARD_INFO("wm8994", 0x1a), } +}; + +static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = { + /* nothing here yet */ +}; + +static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = { + /* nothing here yet */ +}; + +static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = { + .no = EXYNOS4_GPD0(1), + .func = S3C_GPIO_SFN(2), +}; + +static struct platform_pwm_backlight_data smdk4x12_bl_data = { + .pwm_id = 1, + .pwm_period_ns = 1000, +}; + +static uint32_t smdk4x12_keymap[] __initdata = { + /* KEY(row, col, keycode) */ + KEY(1, 0, KEY_D), KEY(1, 1, KEY_A), KEY(1, 2, KEY_B), + KEY(1, 3, KEY_E), KEY(1, 4, KEY_C) +}; + +static struct matrix_keymap_data smdk4x12_keymap_data __initdata = { + .keymap = smdk4x12_keymap, + .keymap_size = ARRAY_SIZE(smdk4x12_keymap), +}; + +static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = { + .keymap_data = &smdk4x12_keymap_data, + .rows = 2, + .cols = 5, +}; + +static struct platform_device *smdk4x12_devices[] __initdata = { + &s3c_device_hsmmc2, + &s3c_device_hsmmc3, + &s3c_device_i2c0, + &s3c_device_i2c1, + &s3c_device_i2c3, + &s3c_device_i2c7, + &s3c_device_rtc, + &s3c_device_wdt, + &samsung_device_keypad, +}; + +static void __init smdk4x12_map_io(void) +{ + clk_xusbxti.rate = 24000000; + + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(clk_xusbxti.rate); + s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs)); +} + +static void __init smdk4x12_machine_init(void) +{ + s3c_i2c0_set_platdata(NULL); + i2c_register_board_info(0, smdk4x12_i2c_devs0, + ARRAY_SIZE(smdk4x12_i2c_devs0)); + + s3c_i2c1_set_platdata(NULL); + i2c_register_board_info(1, smdk4x12_i2c_devs1, + ARRAY_SIZE(smdk4x12_i2c_devs1)); + + s3c_i2c3_set_platdata(NULL); + i2c_register_board_info(3, smdk4x12_i2c_devs3, + ARRAY_SIZE(smdk4x12_i2c_devs3)); + + s3c_i2c7_set_platdata(NULL); + i2c_register_board_info(7, smdk4x12_i2c_devs7, + ARRAY_SIZE(smdk4x12_i2c_devs7)); + + samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data); + + samsung_keypad_set_platdata(&smdk4x12_keypad_data); + + s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata); + s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata); + + platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices)); +} + +MACHINE_START(SMDK4212, "SMDK4212") + /* Maintainer: Kukjin Kim */ + .atag_offset = 0x100, + .init_irq = exynos4_init_irq, + .map_io = smdk4x12_map_io, + .init_machine = smdk4x12_machine_init, + .timer = &exynos4_timer, +MACHINE_END + +MACHINE_START(SMDK4412, "SMDK4412") + /* Maintainer: Kukjin Kim */ + /* Maintainer: Changhwan Youn */ + .atag_offset = 0x100, + .init_irq = exynos4_init_irq, + .map_io = smdk4x12_map_io, + .init_machine = smdk4x12_machine_init, + .timer = &exynos4_timer, +MACHINE_END -- cgit v0.10.2 From ea42a0d058428845047206ff895e60520a7ff256 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 7 Sep 2011 08:45:31 +0200 Subject: ARM: mxs: Add initial support for DENX MX28 Added initial support for DENX M28 module and M28EVK board. Ethernet(FEC), SDHC, Display are supported. Signed-off-by: Stefano Babic Reviewed-by: Wolfram Sang Signed-off-by: Sascha Hauer diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index db2cb7d..6ee781b 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig @@ -26,6 +26,7 @@ CONFIG_MACH_MX23EVK=y CONFIG_MACH_MX28EVK=y CONFIG_MACH_STMP378X_DEVB=y CONFIG_MACH_TX28=y +CONFIG_MACH_M28EVK=y # CONFIG_ARM_THUMB is not set CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 4cd0231..ea5ec0f 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -64,8 +64,25 @@ config MODULE_TX28 select MXS_HAVE_PLATFORM_MXS_MMC select MXS_HAVE_PLATFORM_MXS_PWM +config MODULE_M28 + bool + select SOC_IMX28 + select LEDS_GPIO_REGISTER + select MXS_HAVE_AMBA_DUART + select MXS_HAVE_PLATFORM_AUART + select MXS_HAVE_PLATFORM_FEC + select MXS_HAVE_PLATFORM_FLEXCAN + select MXS_HAVE_PLATFORM_MXS_I2C + select MXS_HAVE_PLATFORM_MXS_MMC + select MXS_HAVE_PLATFORM_MXSFB + select MXS_OCOTP + config MACH_TX28 bool "Ka-Ro TX28 module" select MODULE_TX28 +config MACH_M28EVK + bool "Support DENX M28EVK Platform" + select MODULE_M28 + endif diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile index 6c38262..adcfb4e 100644 --- a/arch/arm/mach-mxs/Makefile +++ b/arch/arm/mach-mxs/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o +obj-$(CONFIG_MACH_M28EVK) += mach-m28evk.o obj-$(CONFIG_MODULE_TX28) += module-tx28.o obj-$(CONFIG_MACH_TX28) += mach-tx28.o diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 5dcc59d..3122310 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -738,11 +738,17 @@ static int clk_misc_init(void) __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET); - /* Extra fec clock setting */ - reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); - reg &= ~BM_CLKCTRL_ENET_SLEEP; - reg |= BM_CLKCTRL_ENET_CLK_OUT_EN; - __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); + /* + * Extra fec clock setting + * The DENX M28 uses an external clock source + * and the clock output must not be enabled + */ + if (!machine_is_m28evk()) { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); + reg &= ~BM_CLKCTRL_ENET_SLEEP; + reg |= BM_CLKCTRL_ENET_CLK_OUT_EN; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); + } /* * 480 MHz seems too high to be ssp clock source directly, diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h index 35a89dd..0582318 100644 --- a/arch/arm/mach-mxs/include/mach/mxs.h +++ b/arch/arm/mach-mxs/include/mach/mxs.h @@ -33,6 +33,7 @@ 0) #define cpu_is_mx28() ( \ machine_is_mx28evk() || \ + machine_is_m28evk() || \ machine_is_tx28() || \ 0) diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h index 7f8bf65..6777674 100644 --- a/arch/arm/mach-mxs/include/mach/uncompress.h +++ b/arch/arm/mach-mxs/include/mach/uncompress.h @@ -63,6 +63,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id) mxs_duart_base = MX23_DUART_BASE_ADDR; break; case MACH_TYPE_MX28EVK: + case MACH_TYPE_M28EVK: case MACH_TYPE_TX28: mxs_duart_base = MX28_DUART_BASE_ADDR; break; diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c new file mode 100644 index 0000000..3b1681e --- /dev/null +++ b/arch/arm/mach-mxs/mach-m28evk.c @@ -0,0 +1,366 @@ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, + * + * based on: mach-mx28_evk.c + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "devices-mx28.h" + +#define M28EVK_GPIO_USERLED1 MXS_GPIO_NR(3, 16) +#define M28EVK_GPIO_USERLED2 MXS_GPIO_NR(3, 17) + +#define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18) +#define M28EVK_LCD_ENABLE MXS_GPIO_NR(3, 28) + +#define MX28EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(2, 12) +#define MX28EVK_MMC1_WRITE_PROTECT MXS_GPIO_NR(0, 28) + +static const iomux_cfg_t m28evk_pads[] __initconst = { + /* duart */ + MX28_PAD_AUART0_CTS__DUART_RX | MXS_PAD_CTRL, + MX28_PAD_AUART0_RTS__DUART_TX | MXS_PAD_CTRL, + + /* auart0 */ + MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL, + MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL, + + /* auart3 */ + MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL, + MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL, + MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL, + MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL, + +#define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP) + /* fec0 */ + MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC, + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC, + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC, + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC, + /* fec1 */ + MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC, + MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC, + MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC, + MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC, + MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC, + MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC, + + /* flexcan0 */ + MX28_PAD_GPMI_RDY2__CAN0_TX, + MX28_PAD_GPMI_RDY3__CAN0_RX, + + /* flexcan1 */ + MX28_PAD_GPMI_CE2N__CAN1_TX, + MX28_PAD_GPMI_CE3N__CAN1_RX, + + /* I2C */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + + /* mxsfb (lcdif) */ + MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL, + MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL, + MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL, + MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL, + MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL, + MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL, + MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL, + MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL, + MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL, + MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL, + MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL, + MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL, + MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL, + MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL, + MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL, + MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL, + MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL, + MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL, + MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL, + MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL, + MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL, + MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL, + MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL, + MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL, + + MX28_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL, + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL, + + /* mmc0 */ + MX28_PAD_SSP0_DATA0__SSP0_D0 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA1__SSP0_D1 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA2__SSP0_D2 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA3__SSP0_D3 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA4__SSP0_D4 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA5__SSP0_D5 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA6__SSP0_D6 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA7__SSP0_D7 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_CMD__SSP0_CMD | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_SSP0_SCK__SSP0_SCK | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + + /* mmc1 */ + MX28_PAD_GPMI_D00__SSP1_D0 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D01__SSP1_D1 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D02__SSP1_D2 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D03__SSP1_D3 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D04__SSP1_D4 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D05__SSP1_D5 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D06__SSP1_D6 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D07__SSP1_D7 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_RDY1__SSP1_CMD | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_GPMI_WRN__SSP1_SCK | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* write protect */ + MX28_PAD_GPMI_RESETN__GPIO_0_28 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* slot power enable */ + MX28_PAD_PWM4__GPIO_3_29 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + + /* led */ + MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL, + MX28_PAD_PWM1__GPIO_3_17 | MXS_PAD_CTRL, + + /* nand */ + MX28_PAD_GPMI_D00__GPMI_D0 | + (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), + MX28_PAD_GPMI_D01__GPMI_D1 | + (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), + MX28_PAD_GPMI_D02__GPMI_D2 | + (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), + MX28_PAD_GPMI_D03__GPMI_D3 | + (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), + MX28_PAD_GPMI_D04__GPMI_D4 | + (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), + MX28_PAD_GPMI_D05__GPMI_D5 | + (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), + MX28_PAD_GPMI_D06__GPMI_D6 | + (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), + MX28_PAD_GPMI_D07__GPMI_D7 | + (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), + MX28_PAD_GPMI_CE0N__GPMI_CE0N | + (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), + MX28_PAD_GPMI_RDY0__GPMI_READY0 | + (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), + MX28_PAD_GPMI_RDN__GPMI_RDN | + (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_WRN__GPMI_WRN | + (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_ALE__GPMI_ALE | + (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_CLE__GPMI_CLE | + (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_RESETN__GPMI_RESETN | + (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), + + /* Backlight */ + MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL, +}; + +/* led */ +static const struct gpio_led m28evk_leds[] __initconst = { + { + .name = "user-led1", + .default_trigger = "heartbeat", + .gpio = M28EVK_GPIO_USERLED1, + }, + { + .name = "user-led2", + .default_trigger = "heartbeat", + .gpio = M28EVK_GPIO_USERLED2, + }, +}; + +static const struct gpio_led_platform_data m28evk_led_data __initconst = { + .leds = m28evk_leds, + .num_leds = ARRAY_SIZE(m28evk_leds), +}; + +static struct fec_platform_data mx28_fec_pdata[] __initdata = { + { + /* fec0 */ + .phy = PHY_INTERFACE_MODE_RMII, + }, { + /* fec1 */ + .phy = PHY_INTERFACE_MODE_RMII, + }, +}; + +static int __init m28evk_fec_get_mac(void) +{ + int i; + u32 val; + const u32 *ocotp = mxs_get_ocotp(); + + if (!ocotp) { + pr_err("%s: timeout when reading fec mac from OCOTP\n", + __func__); + return -ETIMEDOUT; + } + + /* + * OCOTP only stores the last 4 octets for each mac address, + * so hard-code DENX OUI (C0:E5:4E) here. + */ + for (i = 0; i < 2; i++) { + val = ocotp[i * 4]; + mx28_fec_pdata[i].mac[0] = 0xC0; + mx28_fec_pdata[i].mac[1] = 0xE5; + mx28_fec_pdata[i].mac[2] = 0x4E; + mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff; + mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff; + mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff; + } + + return 0; +} + +/* mxsfb (lcdif) */ +static struct fb_videomode m28evk_video_modes[] = { + { + .name = "Ampire AM-800480R2TMQW-T01H", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 30066, /* picosecond (33.26 MHz) */ + .left_margin = 0, + .right_margin = 256, + .upper_margin = 0, + .lower_margin = 45, + .hsync_len = 1, + .vsync_len = 1, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, + }, +}; + +static const struct mxsfb_platform_data m28evk_mxsfb_pdata __initconst = { + .mode_list = m28evk_video_modes, + .mode_count = ARRAY_SIZE(m28evk_video_modes), + .default_bpp = 16, + .ld_intf_width = STMLCDIF_18BIT, +}; + +static struct at24_platform_data m28evk_eeprom = { + .byte_len = 16384, + .page_size = 32, + .flags = AT24_FLAG_ADDR16, +}; + +static struct i2c_board_info m28_stk5v3_i2c_boardinfo[] __initdata = { + { + I2C_BOARD_INFO("at24", 0x51), /* E0=1, E1=0, E2=0 */ + .platform_data = &m28evk_eeprom, + }, +}; + +static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = { + { + /* mmc0 */ + .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT, + .flags = SLOTF_8_BIT_CAPABLE, + }, { + /* mmc1 */ + .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT, + .flags = SLOTF_8_BIT_CAPABLE, + }, +}; + +static void __init m28evk_init(void) +{ + mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads)); + + mx28_add_duart(); + mx28_add_auart0(); + mx28_add_auart3(); + + if (!m28evk_fec_get_mac()) { + mx28_add_fec(0, &mx28_fec_pdata[0]); + mx28_add_fec(1, &mx28_fec_pdata[1]); + } + + mx28_add_flexcan(0, NULL); + mx28_add_flexcan(1, NULL); + + mx28_add_mxsfb(&m28evk_mxsfb_pdata); + + mx28_add_mxs_mmc(0, &m28evk_mmc_pdata[0]); + mx28_add_mxs_mmc(1, &m28evk_mmc_pdata[1]); + + gpio_led_register_device(0, &m28evk_led_data); + + /* I2C */ + mx28_add_mxs_i2c(0); + i2c_register_board_info(0, m28_stk5v3_i2c_boardinfo, + ARRAY_SIZE(m28_stk5v3_i2c_boardinfo)); +} + +static void __init m28evk_timer_init(void) +{ + mx28_clocks_init(); +} + +static struct sys_timer m28evk_timer = { + .init = m28evk_timer_init, +}; + +MACHINE_START(M28EVK, "DENX M28 EVK") + .map_io = mx28_map_io, + .init_irq = mx28_init_irq, + .init_machine = m28evk_init, + .timer = &m28evk_timer, +MACHINE_END -- cgit v0.10.2 From 1cb17e2dbd09436069733500ea48e0c9b1f0a1cc Mon Sep 17 00:00:00 2001 From: Hartley Sweeten Date: Sat, 8 Oct 2011 23:04:34 +0100 Subject: ep93xx: add support Vision EP9307 SoM Add support for Vision Engraving Systems EP9307 based SoM. Signed-off-by: Hartley Sweeten Acked-by: Ryan Mallon Signed-off-by: Arnd Bergmann diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index 3a08b18..97a2493 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig @@ -182,6 +182,13 @@ config MACH_TS72XX Say 'Y' here if you want your kernel to support the Technologic Systems TS-72xx board. +config MACH_VISION_EP9307 + bool "Support Vision Engraving Systems EP9307 SoM" + depends on EP93XX_SDCE0_PHYS_OFFSET + help + Say 'Y' here if you want your kernel to support the + Vision Engraving Systems EP9307 SoM. + choice prompt "Select a UART for early kernel messages" diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile index 3cedcf2..574209d 100644 --- a/arch/arm/mach-ep93xx/Makefile +++ b/arch/arm/mach-ep93xx/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_MACH_MICRO9) += micro9.o obj-$(CONFIG_MACH_SIM_ONE) += simone.o obj-$(CONFIG_MACH_SNAPPER_CL15) += snappercl15.o obj-$(CONFIG_MACH_TS72XX) += ts72xx.o +obj-$(CONFIG_MACH_VISION_EP9307)+= vision_ep9307.o diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c new file mode 100644 index 0000000..10f6488 --- /dev/null +++ b/arch/arm/mach-ep93xx/vision_ep9307.c @@ -0,0 +1,364 @@ +/* + * arch/arm/mach-ep93xx/vision_ep9307.c + * Vision Engraving Systems EP9307 SoM support. + * + * Copyright (C) 2008-2011 Vision Engraving Systems + * H Hartley Sweeten + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +/************************************************************************* + * Static I/O mappings for the FPGA + *************************************************************************/ +#define VISION_PHYS_BASE EP93XX_CS7_PHYS_BASE +#define VISION_VIRT_BASE 0xfebff000 + +static struct map_desc vision_io_desc[] __initdata = { + { + .virtual = VISION_VIRT_BASE, + .pfn = __phys_to_pfn(VISION_PHYS_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +static void __init vision_map_io(void) +{ + ep93xx_map_io(); + + iotable_init(vision_io_desc, ARRAY_SIZE(vision_io_desc)); +} + +/************************************************************************* + * Ethernet + *************************************************************************/ +static struct ep93xx_eth_data vision_eth_data __initdata = { + .phy_id = 1, +}; + +/************************************************************************* + * Framebuffer + *************************************************************************/ +#define VISION_LCD_ENABLE EP93XX_GPIO_LINE_EGPIO1 + +static int vision_lcd_setup(struct platform_device *pdev) +{ + int err; + + err = gpio_request_one(VISION_LCD_ENABLE, GPIOF_INIT_HIGH, + dev_name(&pdev->dev)); + if (err) + return err; + + ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_RAS | + EP93XX_SYSCON_DEVCFG_RASONP3 | + EP93XX_SYSCON_DEVCFG_EXVC); + + return 0; +} + +static void vision_lcd_teardown(struct platform_device *pdev) +{ + gpio_free(VISION_LCD_ENABLE); +} + +static void vision_lcd_blank(int blank_mode, struct fb_info *info) +{ + if (blank_mode) + gpio_set_value(VISION_LCD_ENABLE, 0); + else + gpio_set_value(VISION_LCD_ENABLE, 1); +} + +static struct ep93xxfb_mach_info ep93xxfb_info __initdata = { + .num_modes = EP93XXFB_USE_MODEDB, + .bpp = 16, + .flags = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING, + .setup = vision_lcd_setup, + .teardown = vision_lcd_teardown, + .blank = vision_lcd_blank, +}; + + +/************************************************************************* + * GPIO Expanders + *************************************************************************/ +#define PCA9539_74_GPIO_BASE (EP93XX_GPIO_LINE_MAX + 1) +#define PCA9539_75_GPIO_BASE (PCA9539_74_GPIO_BASE + 16) +#define PCA9539_76_GPIO_BASE (PCA9539_75_GPIO_BASE + 16) +#define PCA9539_77_GPIO_BASE (PCA9539_76_GPIO_BASE + 16) + +static struct pca953x_platform_data pca953x_74_gpio_data = { + .gpio_base = PCA9539_74_GPIO_BASE, + .irq_base = EP93XX_BOARD_IRQ(0), +}; + +static struct pca953x_platform_data pca953x_75_gpio_data = { + .gpio_base = PCA9539_75_GPIO_BASE, + .irq_base = -1, +}; + +static struct pca953x_platform_data pca953x_76_gpio_data = { + .gpio_base = PCA9539_76_GPIO_BASE, + .irq_base = -1, +}; + +static struct pca953x_platform_data pca953x_77_gpio_data = { + .gpio_base = PCA9539_77_GPIO_BASE, + .irq_base = -1, +}; + +/************************************************************************* + * I2C Bus + *************************************************************************/ +static struct i2c_gpio_platform_data vision_i2c_gpio_data __initdata = { + .sda_pin = EP93XX_GPIO_LINE_EEDAT, + .scl_pin = EP93XX_GPIO_LINE_EECLK, +}; + +static struct i2c_board_info vision_i2c_info[] __initdata = { + { + I2C_BOARD_INFO("isl1208", 0x6f), + .irq = IRQ_EP93XX_EXT1, + }, { + I2C_BOARD_INFO("pca9539", 0x74), + .platform_data = &pca953x_74_gpio_data, + .irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7)), + }, { + I2C_BOARD_INFO("pca9539", 0x75), + .platform_data = &pca953x_75_gpio_data, + }, { + I2C_BOARD_INFO("pca9539", 0x76), + .platform_data = &pca953x_76_gpio_data, + }, { + I2C_BOARD_INFO("pca9539", 0x77), + .platform_data = &pca953x_77_gpio_data, + }, +}; + +/************************************************************************* + * SPI Flash + *************************************************************************/ +#define VISION_SPI_FLASH_CS EP93XX_GPIO_LINE_EGPIO7 + +static struct mtd_partition vision_spi_flash_partitions[] = { + { + .name = "SPI bootstrap", + .offset = 0, + .size = SZ_4K, + }, { + .name = "Bootstrap config", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4K, + }, { + .name = "System config", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct flash_platform_data vision_spi_flash_data = { + .name = "SPI Flash", + .parts = vision_spi_flash_partitions, + .nr_parts = ARRAY_SIZE(vision_spi_flash_partitions), +}; + +static int vision_spi_flash_hw_setup(struct spi_device *spi) +{ + return gpio_request_one(VISION_SPI_FLASH_CS, GPIOF_INIT_HIGH, + spi->modalias); +} + +static void vision_spi_flash_hw_cleanup(struct spi_device *spi) +{ + gpio_free(VISION_SPI_FLASH_CS); +} + +static void vision_spi_flash_hw_cs_control(struct spi_device *spi, int value) +{ + gpio_set_value(VISION_SPI_FLASH_CS, value); +} + +static struct ep93xx_spi_chip_ops vision_spi_flash_hw = { + .setup = vision_spi_flash_hw_setup, + .cleanup = vision_spi_flash_hw_cleanup, + .cs_control = vision_spi_flash_hw_cs_control, +}; + +/************************************************************************* + * SPI SD/MMC host + *************************************************************************/ +#define VISION_SPI_MMC_CS EP93XX_GPIO_LINE_G(2) +#define VISION_SPI_MMC_WP EP93XX_GPIO_LINE_F(0) +#define VISION_SPI_MMC_CD EP93XX_GPIO_LINE_EGPIO15 + +static struct gpio vision_spi_mmc_gpios[] = { + { VISION_SPI_MMC_WP, GPIOF_DIR_IN, "mmc_spi:wp" }, + { VISION_SPI_MMC_CD, GPIOF_DIR_IN, "mmc_spi:cd" }, +}; + +static int vision_spi_mmc_init(struct device *pdev, + irqreturn_t (*func)(int, void *), void *pdata) +{ + int err; + + err = gpio_request_array(vision_spi_mmc_gpios, + ARRAY_SIZE(vision_spi_mmc_gpios)); + if (err) + return err; + + err = gpio_set_debounce(VISION_SPI_MMC_CD, 1); + if (err) + goto exit_err; + + err = request_irq(gpio_to_irq(VISION_SPI_MMC_CD), func, + IRQ_TYPE_EDGE_BOTH, "mmc_spi:cd", pdata); + if (err) + goto exit_err; + + return 0; + +exit_err: + gpio_free_array(vision_spi_mmc_gpios, ARRAY_SIZE(vision_spi_mmc_gpios)); + return err; + +} + +static void vision_spi_mmc_exit(struct device *pdev, void *pdata) +{ + free_irq(gpio_to_irq(VISION_SPI_MMC_CD), pdata); + gpio_free_array(vision_spi_mmc_gpios, ARRAY_SIZE(vision_spi_mmc_gpios)); +} + +static int vision_spi_mmc_get_ro(struct device *pdev) +{ + return !!gpio_get_value(VISION_SPI_MMC_WP); +} + +static int vision_spi_mmc_get_cd(struct device *pdev) +{ + return !gpio_get_value(VISION_SPI_MMC_CD); +} + +static struct mmc_spi_platform_data vision_spi_mmc_data = { + .init = vision_spi_mmc_init, + .exit = vision_spi_mmc_exit, + .get_ro = vision_spi_mmc_get_ro, + .get_cd = vision_spi_mmc_get_cd, + .detect_delay = 100, + .powerup_msecs = 100, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, +}; + +static int vision_spi_mmc_hw_setup(struct spi_device *spi) +{ + return gpio_request_one(VISION_SPI_MMC_CS, GPIOF_INIT_HIGH, + spi->modalias); +} + +static void vision_spi_mmc_hw_cleanup(struct spi_device *spi) +{ + gpio_free(VISION_SPI_MMC_CS); +} + +static void vision_spi_mmc_hw_cs_control(struct spi_device *spi, int value) +{ + gpio_set_value(VISION_SPI_MMC_CS, value); +} + +static struct ep93xx_spi_chip_ops vision_spi_mmc_hw = { + .setup = vision_spi_mmc_hw_setup, + .cleanup = vision_spi_mmc_hw_cleanup, + .cs_control = vision_spi_mmc_hw_cs_control, +}; + +/************************************************************************* + * SPI Bus + *************************************************************************/ +static struct spi_board_info vision_spi_board_info[] __initdata = { + { + .modalias = "sst25l", + .platform_data = &vision_spi_flash_data, + .controller_data = &vision_spi_flash_hw, + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 0, + .mode = SPI_MODE_3, + }, { + .modalias = "mmc_spi", + .platform_data = &vision_spi_mmc_data, + .controller_data = &vision_spi_mmc_hw, + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 1, + .mode = SPI_MODE_3, + }, +}; + +static struct ep93xx_spi_info vision_spi_master __initdata = { + .num_chipselect = ARRAY_SIZE(vision_spi_board_info), +}; + +/************************************************************************* + * Machine Initialization + *************************************************************************/ +static void __init vision_init_machine(void) +{ + ep93xx_init_devices(); + ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_64M); + ep93xx_register_eth(&vision_eth_data, 1); + ep93xx_register_fb(&ep93xxfb_info); + ep93xx_register_pwm(1, 0); + + /* + * Request the gpio expander's interrupt gpio line now to prevent + * the kernel from doing a WARN in gpiolib:gpio_ensure_requested(). + */ + if (gpio_request_one(EP93XX_GPIO_LINE_F(7), GPIOF_DIR_IN, + "pca9539:74")) + pr_warn("cannot request interrupt gpio for pca9539:74\n"); + + ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info, + ARRAY_SIZE(vision_i2c_info)); + ep93xx_register_spi(&vision_spi_master, vision_spi_board_info, + ARRAY_SIZE(vision_spi_board_info)); +} + +MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307") + /* Maintainer: H Hartley Sweeten */ + .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, + .map_io = vision_map_io, + .init_irq = ep93xx_init_irq, + .timer = &ep93xx_timer, + .init_machine = vision_init_machine, +MACHINE_END -- cgit v0.10.2