From 7bb71a6c3241b8e20b54fe9978cc9af5eddfd428 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Sun, 1 Jul 2012 21:04:17 +0200 Subject: ARM: LPC32xx: Update DTS file for EA3250 board This DTS file update adds: * 3-channel ADC (for AD-IN on AD2, or 3-axis-accelerometer) * Interrupt key Signed-off-by: Roland Stigge Acked-by: Alexandre Pereira da Silva diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts index c07ba8c..d79b28d 100644 --- a/arch/arm/boot/dts/ea3250.dts +++ b/arch/arm/boot/dts/ea3250.dts @@ -152,6 +152,23 @@ uart1: serial@40014000 { status = "okay"; }; + + /* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */ + adc@40048000 { + status = "okay"; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@21 { + label = "GPIO Key UP"; + linux,code = <103>; + gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ }; }; }; -- cgit v0.10.2 From e5d0f9f57ef213c3a6e21a599c942c4eb7ca2729 Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Wed, 6 Jun 2012 21:22:57 -0400 Subject: ARM: imx6q: add DT node for apbh-dma add DT node for apbh-dma. Signed-off-by: Huang Shijie Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 8c90cba..3197744 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -87,6 +87,11 @@ interrupt-parent = <&intc>; ranges; + dma-apbh@00110000 { + compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x00110000 0x2000>; + }; + timer@00a00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>; -- cgit v0.10.2 From 10a81378ee79977e6d4b70ce576bbd781a335e5b Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Wed, 6 Jun 2012 21:22:58 -0400 Subject: ARM: imx6q: add clock for apbh-dma add clock for apbh-dma. Signed-off-by: Huang Shijie Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index e1a17ac..b2a76d2 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -318,7 +318,7 @@ int __init mx6q_clocks_init(void) clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); /* name parent_name reg shift */ - clk[apbh_dma] = imx_clk_gate2("apbh_dma", "ahb", base + 0x68, 4); + clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); @@ -394,6 +394,7 @@ int __init mx6q_clocks_init(void) clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); clk_register_clkdev(clk[twd], NULL, "smp_twd"); clk_register_clkdev(clk[usboh3], NULL, "usboh3"); + clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh"); clk_register_clkdev(clk[uart_serial], "per", "2020000.serial"); clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial"); clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial"); -- cgit v0.10.2 From cf922fa8816c6294507e4d4b04c4c0dfc8f7a16a Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Sun, 1 Jul 2012 23:38:46 -0400 Subject: ARM: imx6q: add DT node for gpmi nand Add the DT node for gpmi nand. Add the pinmux support for gpmi nand. The gpmi nand may conflicts with other modules, such as MMC. So we do not enable the gpmi nand for mx6q-arm2 board, just add the node for the board. Acked-by: Dong Aisheng Signed-off-by: Huang Shijie Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index db4c609..d792581 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -22,6 +22,12 @@ }; soc { + gpmi-nand@00112000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; /* gpmi nand conflicts with SD */ + }; + aips-bus@02100000 { /* AIPS2 */ ethernet@02188000 { phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 3197744..16a3884 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -92,6 +92,18 @@ reg = <0x00110000 0x2000>; }; + gpmi-nand@00112000 { + compatible = "fsl,imx6q-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00112000 0x2000>, <0x00114000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <0 13 0x04>, <0 15 0x04>; + interrupt-names = "gpmi-dma", "bch"; + fsl,gpmi-dma-channel = <0>; + status = "disabled"; + }; + timer@00a00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>; @@ -500,6 +512,30 @@ }; }; + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ + 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ + 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ + 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ + 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ + 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ + 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ + 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ + 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ + 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ + 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ + 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ + 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ + 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ + 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ + 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ + 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ + 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ + 1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ + }; + }; + i2c1 { pinctrl_i2c1_1: i2c1grp-1 { fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ -- cgit v0.10.2 From 3d3f4983ac1a03e5ef56b98bc24a8ff1bc16e070 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Mon, 2 Jul 2012 01:26:00 -0700 Subject: arm/dts: OMAP2: Add support for OMAP2420H4 Board Simple DTS file for OMAP2420H4 board adding memory information to allow device-tree testing on an OMAP2420. OMAP2420H4 board has 64MB of RAM. Verified that kernel boots with DT using a simple RAMDISK file-system on OMAP2420H4. Signed-off-by: Jon Hunter Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts new file mode 100644 index 0000000..25b50b7 --- /dev/null +++ b/arch/arm/boot/dts/omap2420-h4.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap2.dtsi" + +/ { + model = "TI OMAP2420 H4 board"; + compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x84000000>; /* 64 MB */ + }; +}; -- cgit v0.10.2 From fe12f0e15fa50f250873039269ae65cb84ead4a2 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Mon, 2 Jul 2012 01:26:39 -0700 Subject: arm/dts: Add support for TI AM3517/05 EVM board Add AM3517 EVM (AM3517/05) DTS file to use the omap3.dtsi SoC file, along with memory node and basic i2c information. Signed-off-by: Vaibhav Hiremath Signed-off-by: Benoit Cousson Cc: Grant Likely Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts new file mode 100644 index 0000000..474f760 --- /dev/null +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap3.dtsi" + +/ { + model = "TI AM3517 EVM (AM3517/05)"; + compatible = "ti,am3517-evm", "ti,omap3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; +}; + +&i2c1 { + clock-frequency = <400000>; +}; + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <400000>; +}; -- cgit v0.10.2 From c7d0effa49e05df0881469a72cb381ac5e009e92 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Mon, 2 Jul 2012 01:26:44 -0700 Subject: arm/dts: omap3-evm: Add i2c and twl4030 support Add support for TWL4030, which is interfaced on i2c1 bus. Also add clock frequencies for other i2c instances (2 & 3) required for client-device exist on OMAP3EVM board. Signed-off-by: Vaibhav Hiremath Signed-off-by: Benoit Cousson Cc: Grant Likely Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts index 2eee16e..f349ee9 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/omap3-evm.dts @@ -18,3 +18,31 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; }; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +/include/ "twl4030.dtsi" + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <400000>; + + /* + * TVP5146 Video decoder-in for analog input support. + */ + tvp5146@5c { + compatible = "ti,tvp5146m2"; + reg = <0x5c>; + }; +}; -- cgit v0.10.2 From 610578a3abec7839a56d9dc058c37f6cd2982e10 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Mon, 2 Jul 2012 11:03:00 +0200 Subject: ARM: imx: enable flexcan on imx25, imx35, imx53, imx6q Aas the flexcan driver has DT binding for some time now. This patch makes the flexcan driver available in the can drivers menu if a SOC with flexcan is enabled. Signed-off-by: Marc Kleine-Budde Acked-by: Sascha Hauer Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index eff4db5..c296851 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -52,6 +52,7 @@ config SOC_IMX25 select ARCH_MX25 select COMMON_CLK select CPU_ARM926T + select HAVE_CAN_FLEXCAN if CAN select ARCH_MXC_IOMUX_V3 select MXC_AVIC @@ -79,6 +80,7 @@ config SOC_IMX35 select HAVE_EPIT select MXC_AVIC select SMP_ON_UP if SMP + select HAVE_CAN_FLEXCAN if CAN config SOC_IMX5 select CPU_V7 @@ -105,6 +107,7 @@ config SOC_IMX53 select SOC_IMX5 select ARCH_MX5 select ARCH_MX53 + select HAVE_CAN_FLEXCAN if CAN if ARCH_IMX_V4_V5 @@ -826,6 +829,7 @@ config SOC_IMX6Q select COMMON_CLK select CPU_V7 select HAVE_ARM_SCU + select HAVE_CAN_FLEXCAN if CAN select HAVE_IMX_GPC select HAVE_IMX_MMDC select HAVE_IMX_SRC -- cgit v0.10.2 From 77ac32ad2b03baa7638aadda1650200287ca6f5d Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Mon, 2 Jul 2012 21:39:31 -0400 Subject: ARM: imx6q: add clocks for gpmi-nand Add clocks for gpmi-nand. Signed-off-by: Huang Shijie Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index b2a76d2..0bb8555 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -147,7 +147,7 @@ enum mx6q_clks { esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb, hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2, ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi, - mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, + mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch, gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, @@ -357,6 +357,7 @@ int __init mx6q_clocks_init(void) clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); + clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); @@ -395,6 +396,11 @@ int __init mx6q_clocks_init(void) clk_register_clkdev(clk[twd], NULL, "smp_twd"); clk_register_clkdev(clk[usboh3], NULL, "usboh3"); clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh"); + clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand"); + clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand"); + clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand"); + clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand"); + clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand"); clk_register_clkdev(clk[uart_serial], "per", "2020000.serial"); clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial"); clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial"); -- cgit v0.10.2 From 7a8e5149efd4e20e329beec47e3bb57ce2c5938a Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Fri, 25 May 2012 17:25:35 +0800 Subject: ARM: mx28: add gpmi-nand support add gpmi-nand device tree support. add gpmi-nand pinctrl support. Also enable the gpmi support for mx28-evk board. Signed-off-by: Huang Shijie Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index ee520a5..e53cf67 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -22,6 +22,12 @@ apb@80000000 { apbh@80000000 { + gpmi-nand@8000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; + }; + ssp0: ssp@80010000 { compatible = "fsl,imx28-mmc"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 4634cb8..a89da5a 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -68,15 +68,15 @@ status = "disabled"; }; - bch@8000a000 { - reg = <0x8000a000 2000>; - interrupts = <41>; - status = "disabled"; - }; - - gpmi@8000c000 { - reg = <0x8000c000 2000>; - interrupts = <42 88>; + gpmi-nand@8000c000 { + compatible = "fsl,imx28-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x8000c000 2000>, <0x8000a000 2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <88>, <41>; + interrupt-names = "gpmi-dma", "bch"; + fsl,gpmi-dma-channel = <4>; status = "disabled"; }; @@ -167,6 +167,23 @@ fsl,pull-up = <0>; }; + gpmi_pins_a: gpmi-nand@0 { + reg = <0>; + fsl,pinmux-ids = <0x0000 0x0010 0x0020 + 0x0030 0x0040 0x0050 0x0060 + 0x0070 0x0100 0x0110 0x0140 + 0x0150 0x0180 0x0190 0x01a0 + 0x01b0 0x01c0>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + gpmi_status_cfg: gpmi-status-cfg { + fsl,pinmux-ids = <0x0180 0x0190 0x01c0>; + fsl,drive-strength = <2>; + }; + mac0_pins_a: mac0@0 { reg = <0>; fsl,pinmux-ids = <0x4000 0x4010 0x4020 -- cgit v0.10.2 From a217c46c2ed65d4cde5c7c72290deebc2303116e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 Jun 2012 01:21:55 +0200 Subject: ARM: dts: imx23: Fix the gpmi/gpmi-nand DT name Replace "gpmi" with "gpmi-nand" to get the GPMI interface probing with DT instead of failing to get clock. Signed-off-by: Marek Vasut Cc: Detlev Zundel CC: Dong Aisheng CC: Fabio Estevam Cc: Linux ARM kernel Cc: Stefano Babic Cc: Wolfgang Denk Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 8c5f999..0af43c0 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -62,7 +62,7 @@ status = "disabled"; }; - gpmi@8000c000 { + gpmi-nand@8000c000 { reg = <0x8000c000 2000>; status = "disabled"; }; -- cgit v0.10.2 From 1ea6607d4cdc917987e7e6cfaafc4a630d97a297 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 18 Jun 2012 10:06:09 -0300 Subject: serial: mxs-auart: Allow device tree probing Allow device tree probing. Cc: Grant Likely Cc: Rob Herring Cc: Alan Cox Cc: Signed-off-by: Fabio Estevam Signed-off-by: Subodh Nijsure Acked-by: Greg Kroah-Hartman Signed-off-by: Shawn Guo diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt new file mode 100644 index 0000000..2ee903f --- /dev/null +++ b/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt @@ -0,0 +1,27 @@ +* Freescale MXS Application UART (AUART) + +Required properties: +- compatible : Should be "fsl,-auart". The supported SoCs include + imx23 and imx28. +- reg : Address and length of the register set for the device +- interrupts : Should contain the auart interrupt numbers + +Example: +auart0: serial@8006a000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x8006a000 0x2000>; + interrupts = <112 70 71>; +}; + +Note: Each auart port should have an alias correctly numbered in "aliases" +node. + +Example: + +aliases { + serial0 = &auart0; + serial1 = &auart1; + serial2 = &auart2; + serial3 = &auart3; + serial4 = &auart4; +}; diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c index ec56d83..2e341b8 100644 --- a/drivers/tty/serial/mxs-auart.c +++ b/drivers/tty/serial/mxs-auart.c @@ -33,6 +33,7 @@ #include #include #include +#include #include @@ -675,6 +676,30 @@ static struct uart_driver auart_driver = { #endif }; +/* + * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it + * could successfully get all information from dt or a negative errno. + */ +static int serial_mxs_probe_dt(struct mxs_auart_port *s, + struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + int ret; + + if (!np) + /* no device tree device */ + return 1; + + ret = of_alias_get_id(np, "serial"); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get alias id: %d\n", ret); + return ret; + } + s->port.line = ret; + + return 0; +} + static int __devinit mxs_auart_probe(struct platform_device *pdev) { struct mxs_auart_port *s; @@ -689,6 +714,12 @@ static int __devinit mxs_auart_probe(struct platform_device *pdev) goto out; } + ret = serial_mxs_probe_dt(s, pdev); + if (ret > 0) + s->port.line = pdev->id < 0 ? 0 : pdev->id; + else if (ret < 0) + goto out_free; + pinctrl = devm_pinctrl_get_select_default(&pdev->dev); if (IS_ERR(pinctrl)) { ret = PTR_ERR(pinctrl); @@ -711,7 +742,6 @@ static int __devinit mxs_auart_probe(struct platform_device *pdev) s->port.membase = ioremap(r->start, resource_size(r)); s->port.ops = &mxs_auart_ops; s->port.iotype = UPIO_MEM; - s->port.line = pdev->id < 0 ? 0 : pdev->id; s->port.fifosize = 16; s->port.uartclk = clk_get_rate(s->clk); s->port.type = PORT_IMX; @@ -728,7 +758,7 @@ static int __devinit mxs_auart_probe(struct platform_device *pdev) platform_set_drvdata(pdev, s); - auart_port[pdev->id] = s; + auart_port[s->port.line] = s; mxs_auart_reset(&s->port); @@ -769,12 +799,19 @@ static int __devexit mxs_auart_remove(struct platform_device *pdev) return 0; } +static struct of_device_id mxs_auart_dt_ids[] = { + { .compatible = "fsl,imx23-auart", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids); + static struct platform_driver mxs_auart_driver = { .probe = mxs_auart_probe, .remove = __devexit_p(mxs_auart_remove), .driver = { .name = "mxs-auart", .owner = THIS_MODULE, + .of_match_table = mxs_auart_dt_ids, }, }; @@ -807,3 +844,4 @@ module_init(mxs_auart_init); module_exit(mxs_auart_exit); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Freescale MXS application uart driver"); +MODULE_ALIAS("platform:mxs-auart"); -- cgit v0.10.2 From 80d969e491b514f8179ef354b7cf8b372610d01b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 15 Jun 2012 12:35:56 -0300 Subject: ARM: dts: mx28evk: Add auart0 and auart3 support Add auart0 and auart3 support. Signed-off-by: Fabio Estevam Reviewed-by: Marek Vasut Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index e53cf67..319c75a 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -79,6 +79,18 @@ pinctrl-0 = <&duart_pins_a>; status = "okay"; }; + + auart0: serial@8006a000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; + }; + + auart3: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_pins_a>; + status = "okay"; + }; }; }; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index a89da5a..ee3778a 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -22,6 +22,11 @@ gpio4 = &gpio4; saif0 = &saif0; saif1 = &saif1; + serial0 = &auart0; + serial1 = &auart1; + serial2 = &auart2; + serial3 = &auart3; + serial4 = &auart4; }; cpus { @@ -184,6 +189,22 @@ fsl,drive-strength = <2>; }; + auart0_pins_a: auart0@0 { + reg = <0>; + fsl,pinmux-ids = <0x3000 0x3010 0x3020 0x3030>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + auart3_pins_a: auart3@0 { + reg = <0>; + fsl,pinmux-ids = <0x30c0 0x30d0 0x30e0 0x30f0>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + mac0_pins_a: mac0@0 { reg = <0>; fsl,pinmux-ids = <0x4000 0x4010 0x4020 @@ -421,30 +442,35 @@ }; auart0: serial@8006a000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006a000 0x2000>; interrupts = <112 70 71>; status = "disabled"; }; auart1: serial@8006c000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006c000 0x2000>; interrupts = <113 72 73>; status = "disabled"; }; auart2: serial@8006e000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006e000 0x2000>; interrupts = <114 74 75>; status = "disabled"; }; auart3: serial@80070000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x80070000 0x2000>; interrupts = <115 76 77>; status = "disabled"; }; auart4: serial@80072000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x80072000 0x2000>; interrupts = <116 78 79>; status = "disabled"; -- cgit v0.10.2 From 5653acc24c13e8b272e16a194b26465330753118 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 19 Jun 2012 22:38:14 +0800 Subject: ARM: mxs: store mac address read from OTP in device tree The non-DT boot reads the mac from OTP and pass it to fec driver via platform data. The patch provides an equivalent support for device tree boot, with reading mac from OTP and store it in device tree, and fec driver can get the mac from device tree at its probe time. Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 8cac94b..167f649 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -71,6 +71,68 @@ static struct sys_timer imx28_timer = { .init = imx28_timer_init, }; +enum mac_oui { + OUI_FSL, + OUI_DENX, +}; + +static void __init update_fec_mac_prop(enum mac_oui oui) +{ + struct device_node *np, *from = NULL; + struct property *oldmac, *newmac; + const u32 *ocotp = mxs_get_ocotp(); + u8 *macaddr; + u32 val; + int i; + + for (i = 0; i < 2; i++) { + np = of_find_compatible_node(from, NULL, "fsl,imx28-fec"); + if (!np) + return; + from = np; + + newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL); + if (!newmac) + return; + newmac->value = newmac + 1; + newmac->length = 6; + + newmac->name = kstrdup("local-mac-address", GFP_KERNEL); + if (!newmac->name) { + kfree(newmac); + return; + } + + /* + * OCOTP only stores the last 4 octets for each mac address, + * so hard-code OUI here. + */ + macaddr = newmac->value; + switch (oui) { + case OUI_FSL: + macaddr[0] = 0x00; + macaddr[1] = 0x04; + macaddr[2] = 0x9f; + break; + case OUI_DENX: + macaddr[0] = 0xc0; + macaddr[1] = 0xe5; + macaddr[2] = 0x4e; + break; + } + val = ocotp[i]; + macaddr[3] = (val >> 16) & 0xff; + macaddr[4] = (val >> 8) & 0xff; + macaddr[5] = (val >> 0) & 0xff; + + oldmac = of_find_property(np, newmac->name, NULL); + if (oldmac) + prom_update_property(np, newmac, oldmac); + else + prom_add_property(np, newmac); + } +} + static void __init imx28_evk_init(void) { struct clk *clk; @@ -79,6 +141,8 @@ static void __init imx28_evk_init(void) clk = clk_get_sys("enet_out", NULL); if (!IS_ERR(clk)) clk_prepare_enable(clk); + + update_fec_mac_prop(OUI_FSL); } static void __init mxs_machine_init(void) -- cgit v0.10.2 From 8385e7c1db749f526e04854b48c12f1bd079b65e Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 27 Jun 2012 10:18:11 +0200 Subject: ARM: dts: imx28: Add additionnal muxing options to iMX28 DTSI Signed-off-by: Maxime Ripard Cc: Brian Lily Reviewed-by: Marek Vasut Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index ee3778a..65d6a53 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -172,6 +172,14 @@ fsl,pull-up = <0>; }; + duart_pins_b: duart@1 { + reg = <1>; + fsl,pinmux-ids = <0x3022 0x3032>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + gpmi_pins_a: gpmi-nand@0 { reg = <0>; fsl,pinmux-ids = <0x0000 0x0010 0x0020 @@ -234,6 +242,15 @@ fsl,pull-up = <1>; }; + mmc0_4bit_pins_a: mmc0-4bit@0 { + reg = <0>; + fsl,pinmux-ids = <0x2000 0x2010 0x2020 + 0x2030 0x2080 0x2090 0x20a0>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + mmc0_cd_cfg: mmc0-cd-cfg { fsl,pinmux-ids = <0x2090>; fsl,pull-up = <0>; -- cgit v0.10.2 From 330eaaf947abe81b020ed23e9b46d1e620e55457 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 27 Jun 2012 10:18:12 +0200 Subject: ARM: mxs: Add Crystalfontz CFA-10036 DTS Signed-off-by: Maxime Ripard Cc: Brian Lily Reviewed-by: Marek Vasut Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/cfa10036.dts b/arch/arm/boot/dts/cfa10036.dts new file mode 100644 index 0000000..28b9326 --- /dev/null +++ b/arch/arm/boot/dts/cfa10036.dts @@ -0,0 +1,43 @@ +/* + * Copyright 2012 Free Electrons + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx28.dtsi" + +/ { + model = "Crystalfontz CFA-10036 Board"; + compatible = "crystalfontz,cfa10036", "fsl,imx28"; + + memory { + reg = <0x40000000 0x08000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg &mmc0_sck_cfg>; + bus-width = <4>; + status = "okay"; + }; + }; + + apbx@80040000 { + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_b>; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 167f649..8d764f2 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -161,6 +161,7 @@ static const char *imx23_dt_compat[] __initdata = { }; static const char *imx28_dt_compat[] __initdata = { + "crystalfontz,cfa10036", "fsl,imx28-evk", "fsl,imx28", NULL, -- cgit v0.10.2 From f34ffc9efc9f916c2594c6e86e813acacbd7572f Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 29 Jun 2012 09:39:29 +0200 Subject: ARM: dts: cfa10036: Add Power LED to the CFA-10036 board Signed-off-by: Maxime Ripard Cc: Brian Lilly Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/cfa10036.dts b/arch/arm/boot/dts/cfa10036.dts index 28b9326..c03a577 100644 --- a/arch/arm/boot/dts/cfa10036.dts +++ b/arch/arm/boot/dts/cfa10036.dts @@ -40,4 +40,13 @@ }; }; }; + + leds { + compatible = "gpio-leds"; + + power { + gpios = <&gpio3 4 1>; + default-state = "on"; + }; + }; }; -- cgit v0.10.2 From e1d4f23ec0688f58b7d60265f38e1cbe8c3a4432 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Mon, 2 Jul 2012 11:03:01 +0200 Subject: ARM: mxs: enable flexcan on imx28 As the flexcan driver has DT binding for some time now. This patch makes the flexcan driver available in the can drivers menu if a SOC with flexcan is enabled. Signed-off-by: Marc Kleine-Budde Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 91cf062..ccdf83b 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -16,6 +16,7 @@ config SOC_IMX28 bool select ARM_AMBA select CPU_ARM926T + select HAVE_CAN_FLEXCAN if CAN select HAVE_PWM select PINCTRL_IMX28 -- cgit v0.10.2 From dd8d20a3f32a7ba37526f5b4dfd4d35a93e5342f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 26 Jun 2012 16:29:27 +0800 Subject: rtc: stmp3xxx: Add simple binding for the stmp3xxx-rtc Signed-off-by: Marek Vasut Cc: Alessandro Zummo Cc: devicetree-discuss@lists.ozlabs.org Cc: Grant Likely Cc: rtc-linux@googlegroups.com Acked-by: Rob Herring Signed-off-by: Shawn Guo diff --git a/Documentation/devicetree/bindings/rtc/stmp3xxx-rtc.txt b/Documentation/devicetree/bindings/rtc/stmp3xxx-rtc.txt new file mode 100644 index 0000000..b800070 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/stmp3xxx-rtc.txt @@ -0,0 +1,16 @@ +* STMP3xxx/i.MX28 Time Clock controller + +Required properties: +- compatible: should be one of the following. + * "fsl,stmp3xxx-rtc" +- reg: physical base address of the controller and length of memory mapped + region. +- interrupts: rtc alarm interrupt + +Example: + +rtc@80056000 { + compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; + reg = <0x80056000 2000>; + interrupts = <29>; +}; diff --git a/drivers/rtc/rtc-stmp3xxx.c b/drivers/rtc/rtc-stmp3xxx.c index 1028786..739ef556 100644 --- a/drivers/rtc/rtc-stmp3xxx.c +++ b/drivers/rtc/rtc-stmp3xxx.c @@ -25,6 +25,7 @@ #include #include #include +#include #include @@ -265,6 +266,12 @@ static int stmp3xxx_rtc_resume(struct platform_device *dev) #define stmp3xxx_rtc_resume NULL #endif +static const struct of_device_id rtc_dt_ids[] = { + { .compatible = "fsl,stmp3xxx-rtc", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtc_dt_ids); + static struct platform_driver stmp3xxx_rtcdrv = { .probe = stmp3xxx_rtc_probe, .remove = stmp3xxx_rtc_remove, @@ -273,6 +280,7 @@ static struct platform_driver stmp3xxx_rtcdrv = { .driver = { .name = "stmp3xxx-rtc", .owner = THIS_MODULE, + .of_match_table = rtc_dt_ids, }, }; -- cgit v0.10.2 From ce4409b5821f170c018b94bacb36df1ffadb751f Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 25 Jun 2012 19:22:09 +0800 Subject: video: mxsfb: move mxsfb.h into include/linux Move mxsfb.h into include/linux, so that mxsfb driver does not have to include header. Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h index 9acdd63..9ee5ced 100644 --- a/arch/arm/mach-mxs/devices-mx23.h +++ b/arch/arm/mach-mxs/devices-mx23.h @@ -10,7 +10,7 @@ */ #include #include -#include +#include #include static inline int mx23_add_duart(void) diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h index 84b2960..fcab431 100644 --- a/arch/arm/mach-mxs/devices-mx28.h +++ b/arch/arm/mach-mxs/devices-mx28.h @@ -10,7 +10,7 @@ */ #include #include -#include +#include #include static inline int mx28_add_duart(void) diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c index 5a75b71..76b53f73 100644 --- a/arch/arm/mach-mxs/devices/platform-mxsfb.c +++ b/arch/arm/mach-mxs/devices/platform-mxsfb.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #ifdef CONFIG_SOC_IMX23 struct platform_device *__init mx23_add_mxsfb( diff --git a/arch/arm/mach-mxs/include/mach/mxsfb.h b/arch/arm/mach-mxs/include/mach/mxsfb.h deleted file mode 100644 index e4d7979..0000000 --- a/arch/arm/mach-mxs/include/mach/mxsfb.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_FB_H -#define __MACH_FB_H - -#include - -#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */ -#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */ -#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */ -#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */ - -#define FB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6) -#define FB_SYNC_DOTCLK_FAILING_ACT (1 << 7) /* failing/negtive edge sampling */ - -struct mxsfb_platform_data { - struct fb_videomode *mode_list; - unsigned mode_count; - - unsigned default_bpp; - - unsigned dotclk_delay; /* refer manual HW_LCDIF_VDCTRL4 register */ - unsigned ld_intf_width; /* refer STMLCDIF_* macros */ - - unsigned fb_size; /* Size of the video memory. If zero a - * default will be used - */ - unsigned long fb_phys; /* physical address for the video memory. If - * zero the framebuffer memory will be dynamically - * allocated. If specified,fb_size must also be specified. - * fb_phys must be unused by Linux. - */ -}; - -#endif /* __MACH_FB_H */ diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index abbe691..08dad8d 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -46,7 +46,7 @@ #include #include #include -#include +#include #define REG_SET 4 #define REG_CLR 8 diff --git a/include/linux/mxsfb.h b/include/linux/mxsfb.h new file mode 100644 index 0000000..f14943d --- /dev/null +++ b/include/linux/mxsfb.h @@ -0,0 +1,49 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __LINUX_MXSFB_H +#define __LINUX_MXSFB_H + +#include + +#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */ +#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */ +#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */ +#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */ + +#define FB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6) +#define FB_SYNC_DOTCLK_FAILING_ACT (1 << 7) /* failing/negtive edge sampling */ + +struct mxsfb_platform_data { + struct fb_videomode *mode_list; + unsigned mode_count; + + unsigned default_bpp; + + unsigned dotclk_delay; /* refer manual HW_LCDIF_VDCTRL4 register */ + unsigned ld_intf_width; /* refer STMLCDIF_* macros */ + + unsigned fb_size; /* Size of the video memory. If zero a + * default will be used + */ + unsigned long fb_phys; /* physical address for the video memory. If + * zero the framebuffer memory will be dynamically + * allocated. If specified,fb_size must also be specified. + * fb_phys must be unused by Linux. + */ +}; + +#endif /* __LINUX_MXSFB_H */ -- cgit v0.10.2 From 73fc610f9a891fd777040bbb1854ae0b58edee9c Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 25 Jun 2012 19:54:35 +0800 Subject: video: mxsfb: add simple device tree probe Add a simple device tree probe support for mxsfb driver. Before a common binding for struct fb_videomode is available, the driver will keep using struct mxsfb_platform_data. That said, platform code will use auxdata to attach mxsfb_platform_data for device tree boot. Signed-off-by: Shawn Guo diff --git a/Documentation/devicetree/bindings/fb/mxsfb.txt b/Documentation/devicetree/bindings/fb/mxsfb.txt new file mode 100644 index 0000000..b41e5e52 --- /dev/null +++ b/Documentation/devicetree/bindings/fb/mxsfb.txt @@ -0,0 +1,19 @@ +* Freescale MXS LCD Interface (LCDIF) + +Required properties: +- compatible: Should be "fsl,-lcdif". Supported chips include + imx23 and imx28. +- reg: Address and length of the register set for lcdif +- interrupts: Should contain lcdif interrupts + +Optional properties: +- panel-enable-gpios : Should specify the gpio for panel enable + +Examples: + +lcdif@80030000 { + compatible = "fsl,imx28-lcdif"; + reg = <0x80030000 2000>; + interrupts = <38 86>; + panel-enable-gpios = <&gpio3 30 0>; +}; diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 08dad8d..49619b4 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -41,6 +41,8 @@ #include #include +#include +#include #include #include #include @@ -750,16 +752,43 @@ static void __devexit mxsfb_free_videomem(struct mxsfb_info *host) } } +static struct platform_device_id mxsfb_devtype[] = { + { + .name = "imx23-fb", + .driver_data = MXSFB_V3, + }, { + .name = "imx28-fb", + .driver_data = MXSFB_V4, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(platform, mxsfb_devtype); + +static const struct of_device_id mxsfb_dt_ids[] = { + { .compatible = "fsl,imx23-lcdif", .data = &mxsfb_devtype[0], }, + { .compatible = "fsl,imx28-lcdif", .data = &mxsfb_devtype[1], }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mxsfb_dt_ids); + static int __devinit mxsfb_probe(struct platform_device *pdev) { + const struct of_device_id *of_id = + of_match_device(mxsfb_dt_ids, &pdev->dev); struct mxsfb_platform_data *pdata = pdev->dev.platform_data; struct resource *res; struct mxsfb_info *host; struct fb_info *fb_info; struct fb_modelist *modelist; struct pinctrl *pinctrl; + int panel_enable; + enum of_gpio_flags flags; int i, ret; + if (of_id) + pdev->id_entry = of_id->data; + if (!pdata) { dev_err(&pdev->dev, "No platformdata. Giving up\n"); return -ENODEV; @@ -807,6 +836,22 @@ static int __devinit mxsfb_probe(struct platform_device *pdev) goto error_getclock; } + panel_enable = of_get_named_gpio_flags(pdev->dev.of_node, + "panel-enable-gpios", 0, &flags); + if (gpio_is_valid(panel_enable)) { + unsigned long f = GPIOF_OUT_INIT_HIGH; + if (flags == OF_GPIO_ACTIVE_LOW) + f = GPIOF_OUT_INIT_LOW; + ret = devm_gpio_request_one(&pdev->dev, panel_enable, + f, "panel-enable"); + if (ret) { + dev_err(&pdev->dev, + "failed to request gpio %d: %d\n", + panel_enable, ret); + goto error_panel_enable; + } + } + fb_info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL); if (!fb_info->pseudo_palette) { ret = -ENOMEM; @@ -854,6 +899,7 @@ error_register: error_init_fb: kfree(fb_info->pseudo_palette); error_pseudo_pallette: +error_panel_enable: clk_put(host->clk); error_getclock: error_getpin: @@ -901,19 +947,6 @@ static void mxsfb_shutdown(struct platform_device *pdev) writel(CTRL_RUN, host->base + LCDC_CTRL + REG_CLR); } -static struct platform_device_id mxsfb_devtype[] = { - { - .name = "imx23-fb", - .driver_data = MXSFB_V3, - }, { - .name = "imx28-fb", - .driver_data = MXSFB_V4, - }, { - /* sentinel */ - } -}; -MODULE_DEVICE_TABLE(platform, mxsfb_devtype); - static struct platform_driver mxsfb_driver = { .probe = mxsfb_probe, .remove = __devexit_p(mxsfb_remove), @@ -921,6 +954,7 @@ static struct platform_driver mxsfb_driver = { .id_table = mxsfb_devtype, .driver = { .name = DRIVER_NAME, + .of_match_table = mxsfb_dt_ids, }, }; -- cgit v0.10.2 From ab2815c3997b179f043a747264d155ab0bc181ad Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 25 Jun 2012 21:21:46 +0800 Subject: ARM: mxs: use auxdata to attach mxsfb_platform_data Use auxdata to attach mxsfb_platform_data for imx23-evk and imx28-evk. We take this as a temporary solution for removing those board files, and it should be updated to use common bindings for struct fb_videomode when it becomes available. Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 8d764f2..87a4829 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -16,12 +16,57 @@ #include #include #include +#include #include #include #include #include #include +static struct fb_videomode mx23evk_video_modes[] = { + { + .name = "Samsung-LMS430HF02", + .refresh = 60, + .xres = 480, + .yres = 272, + .pixclock = 108096, /* picosecond (9.2 MHz) */ + .left_margin = 15, + .right_margin = 8, + .upper_margin = 12, + .lower_margin = 4, + .hsync_len = 1, + .vsync_len = 1, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | + FB_SYNC_DOTCLK_FAILING_ACT, + }, +}; + +static struct fb_videomode mx28evk_video_modes[] = { + { + .name = "Seiko-43WVF1G", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 29851, /* picosecond (33.5 MHz) */ + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | + FB_SYNC_DOTCLK_FAILING_ACT, + }, +}; + +static struct mxsfb_platform_data mxsfb_pdata __initdata; + +static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata), + OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata), + { /* sentinel */ } +}; + static int __init mxs_icoll_add_irq_domain(struct device_node *np, struct device_node *interrupt_parent) { @@ -133,6 +178,14 @@ static void __init update_fec_mac_prop(enum mac_oui oui) } } +static void __init imx23_evk_init(void) +{ + mxsfb_pdata.mode_list = mx23evk_video_modes; + mxsfb_pdata.mode_count = ARRAY_SIZE(mx23evk_video_modes); + mxsfb_pdata.default_bpp = 32; + mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; +} + static void __init imx28_evk_init(void) { struct clk *clk; @@ -143,15 +196,22 @@ static void __init imx28_evk_init(void) clk_prepare_enable(clk); update_fec_mac_prop(OUI_FSL); + + mxsfb_pdata.mode_list = mx28evk_video_modes; + mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes); + mxsfb_pdata.default_bpp = 32; + mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; } static void __init mxs_machine_init(void) { if (of_machine_is_compatible("fsl,imx28-evk")) imx28_evk_init(); + else if (of_machine_is_compatible("fsl,imx23-evk")) + imx23_evk_init(); of_platform_populate(NULL, of_default_bus_match_table, - NULL, NULL); + mxs_auxdata_lookup, NULL); } static const char *imx23_dt_compat[] __initdata = { -- cgit v0.10.2 From f14da767880722f6150b617f1ddcb3a3970d7848 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 28 Jun 2012 11:44:57 +0800 Subject: ARM: dts: mxs: add comments for pinmux-ids Add comments for pinmux-ids so that we do not have to keep looking at Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt to read all these pinmux-ids. Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 0af43c0..7274273 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -114,7 +114,10 @@ duart_pins_a: duart@0 { reg = <0>; - fsl,pinmux-ids = <0x11a2 0x11b2>; + fsl,pinmux-ids = < + 0x11a2 /* MX23_PAD_PWM0__DUART_RX */ + 0x11b2 /* MX23_PAD_PWM1__DUART_TX */ + >; fsl,drive-strength = <0>; fsl,voltage = <1>; fsl,pull-up = <0>; @@ -122,16 +125,29 @@ mmc0_8bit_pins_a: mmc0-8bit@0 { reg = <0>; - fsl,pinmux-ids = <0x2020 0x2030 0x2040 - 0x2050 0x0082 0x0092 0x00a2 - 0x00b2 0x2000 0x2010 0x2060>; + fsl,pinmux-ids = < + 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */ + 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */ + 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ + 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ + 0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */ + 0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */ + 0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */ + 0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */ + 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ + 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ + 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ + >; fsl,drive-strength = <1>; fsl,voltage = <1>; fsl,pull-up = <1>; }; mmc0_pins_fixup: mmc0-pins-fixup { - fsl,pinmux-ids = <0x2010 0x2060>; + fsl,pinmux-ids = < + 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ + 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ + >; fsl,pull-up = <0>; }; }; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 65d6a53..42d6078 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -166,7 +166,10 @@ duart_pins_a: duart@0 { reg = <0>; - fsl,pinmux-ids = <0x3102 0x3112>; + fsl,pinmux-ids = < + 0x3102 /* MX28_PAD_PWM0__DUART_RX */ + 0x3112 /* MX28_PAD_PWM1__DUART_TX */ + >; fsl,drive-strength = <0>; fsl,voltage = <1>; fsl,pull-up = <0>; @@ -174,7 +177,10 @@ duart_pins_b: duart@1 { reg = <1>; - fsl,pinmux-ids = <0x3022 0x3032>; + fsl,pinmux-ids = < + 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ + 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ + >; fsl,drive-strength = <0>; fsl,voltage = <1>; fsl,pull-up = <0>; @@ -182,24 +188,47 @@ gpmi_pins_a: gpmi-nand@0 { reg = <0>; - fsl,pinmux-ids = <0x0000 0x0010 0x0020 - 0x0030 0x0040 0x0050 0x0060 - 0x0070 0x0100 0x0110 0x0140 - 0x0150 0x0180 0x0190 0x01a0 - 0x01b0 0x01c0>; + fsl,pinmux-ids = < + 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */ + 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */ + 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */ + 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */ + 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */ + 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */ + 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */ + 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */ + 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */ + 0x0110 /* MX28_PAD_GPMI_CE1N__GPMI_CE1N */ + 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */ + 0x0150 /* MX28_PAD_GPMI_RDY1__GPMI_READY1 */ + 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ + 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ + 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */ + 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */ + 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ + >; fsl,drive-strength = <0>; fsl,voltage = <1>; fsl,pull-up = <0>; }; gpmi_status_cfg: gpmi-status-cfg { - fsl,pinmux-ids = <0x0180 0x0190 0x01c0>; + fsl,pinmux-ids = < + 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ + 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ + 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ + >; fsl,drive-strength = <2>; }; auart0_pins_a: auart0@0 { reg = <0>; - fsl,pinmux-ids = <0x3000 0x3010 0x3020 0x3030>; + fsl,pinmux-ids = < + 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ + 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ + 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */ + 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */ + >; fsl,drive-strength = <0>; fsl,voltage = <1>; fsl,pull-up = <0>; @@ -207,7 +236,12 @@ auart3_pins_a: auart3@0 { reg = <0>; - fsl,pinmux-ids = <0x30c0 0x30d0 0x30e0 0x30f0>; + fsl,pinmux-ids = < + 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */ + 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */ + 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */ + 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */ + >; fsl,drive-strength = <0>; fsl,voltage = <1>; fsl,pull-up = <0>; @@ -215,9 +249,17 @@ mac0_pins_a: mac0@0 { reg = <0>; - fsl,pinmux-ids = <0x4000 0x4010 0x4020 - 0x4030 0x4040 0x4060 0x4070 - 0x4080 0x4100>; + fsl,pinmux-ids = < + 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */ + 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */ + 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */ + 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */ + 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */ + 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */ + 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */ + 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */ + 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */ + >; fsl,drive-strength = <1>; fsl,voltage = <1>; fsl,pull-up = <1>; @@ -225,8 +267,14 @@ mac1_pins_a: mac1@0 { reg = <0>; - fsl,pinmux-ids = <0x40f1 0x4091 0x40a1 - 0x40e1 0x40b1 0x40c1>; + fsl,pinmux-ids = < + 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */ + 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */ + 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */ + 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */ + 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */ + 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */ + >; fsl,drive-strength = <1>; fsl,voltage = <1>; fsl,pull-up = <1>; @@ -234,9 +282,19 @@ mmc0_8bit_pins_a: mmc0-8bit@0 { reg = <0>; - fsl,pinmux-ids = <0x2000 0x2010 0x2020 - 0x2030 0x2040 0x2050 0x2060 - 0x2070 0x2080 0x2090 0x20a0>; + fsl,pinmux-ids = < + 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ + 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ + 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ + 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ + 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */ + 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */ + 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */ + 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */ + 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ + 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ + 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ + >; fsl,drive-strength = <1>; fsl,voltage = <1>; fsl,pull-up = <1>; @@ -244,27 +302,41 @@ mmc0_4bit_pins_a: mmc0-4bit@0 { reg = <0>; - fsl,pinmux-ids = <0x2000 0x2010 0x2020 - 0x2030 0x2080 0x2090 0x20a0>; + fsl,pinmux-ids = < + 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ + 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ + 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ + 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ + 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ + 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ + 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ + >; fsl,drive-strength = <1>; fsl,voltage = <1>; fsl,pull-up = <1>; }; mmc0_cd_cfg: mmc0-cd-cfg { - fsl,pinmux-ids = <0x2090>; + fsl,pinmux-ids = < + 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ + >; fsl,pull-up = <0>; }; mmc0_sck_cfg: mmc0-sck-cfg { - fsl,pinmux-ids = <0x20a0>; + fsl,pinmux-ids = < + 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ + >; fsl,drive-strength = <2>; fsl,pull-up = <0>; }; i2c0_pins_a: i2c0@0 { reg = <0>; - fsl,pinmux-ids = <0x3180 0x3190>; + fsl,pinmux-ids = < + 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */ + 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */ + >; fsl,drive-strength = <1>; fsl,voltage = <1>; fsl,pull-up = <1>; @@ -272,8 +344,12 @@ saif0_pins_a: saif0@0 { reg = <0>; - fsl,pinmux-ids = - <0x3140 0x3150 0x3160 0x3170>; + fsl,pinmux-ids = < + 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */ + 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */ + 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */ + 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */ + >; fsl,drive-strength = <2>; fsl,voltage = <1>; fsl,pull-up = <1>; @@ -281,7 +357,9 @@ saif1_pins_a: saif1@0 { reg = <0>; - fsl,pinmux-ids = <0x31a0>; + fsl,pinmux-ids = < + 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */ + >; fsl,drive-strength = <2>; fsl,voltage = <1>; fsl,pull-up = <1>; -- cgit v0.10.2 From d54dbb5000fca9863e8a2cb0e6467a424a1eb6e0 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 28 Jun 2012 11:44:58 +0800 Subject: ARM: dts: mxs: add hog-gpios for imx23-evk and imx28-evk Before gpio_request can directly ask pinctrl system to configure the requested pin into gpio mode, we use "hog" entry (pinctrl state of pin controller itself) to configure gpios. Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index 70bffa9..6a0912b 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -30,6 +30,23 @@ wp-gpios = <&gpio1 30 0>; status = "okay"; }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */ + 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ + 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; }; apbx@80040000 { diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 319c75a..505ae5e 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -44,6 +44,27 @@ wp-gpios = <&gpio0 28 0>; status = "okay"; }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */ + 0x20f3 /* MX28_PAD_SSP1_DATA3__GPIO_2_15 */ + 0x40d3 /* MX28_PAD_ENET0_RX_CLK__GPIO_4_13 */ + 0x20c3 /* MX28_PAD_SSP1_SCK__GPIO_2_12 */ + 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ + 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ + 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; }; apbx@80040000 { -- cgit v0.10.2 From 72beabae635b9485510ccf8093df319f59eb6688 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 28 Jun 2012 11:44:59 +0800 Subject: ARM: dts: imx23-evk: updates for mmc device The 8-bit mode mmc has pin conflicts with display. Let's use 4-bit mode by default, so that display can be enabled together later. Also add vmmc-supply for mmc device. Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index 6a0912b..8321fa3 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -25,9 +25,10 @@ ssp0: ssp@80010000 { compatible = "fsl,imx23-mmc"; pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a &mmc0_pins_fixup>; - bus-width = <8>; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; + bus-width = <4>; wp-gpios = <&gpio1 30 0>; + vmmc-supply = <®_vddio_sd0>; status = "okay"; }; @@ -57,4 +58,16 @@ }; }; }; + + regulators { + compatible = "simple-bus"; + + reg_vddio_sd0: vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 29 0>; + }; + }; }; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 7274273..daade4f 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -123,6 +123,22 @@ fsl,pull-up = <0>; }; + mmc0_4bit_pins_a: mmc0-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */ + 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */ + 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ + 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ + 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ + 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ + 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + mmc0_8bit_pins_a: mmc0-8bit@0 { reg = <0>; fsl,pinmux-ids = < -- cgit v0.10.2 From a450839432519beda04ffc286428b7e44b9dd488 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 28 Jun 2012 11:45:00 +0800 Subject: ARM: dts: imx23-evk: add auart device Add auart device for imx23-evk board. Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index 8321fa3..9eca34f 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -51,6 +51,12 @@ }; apbx@80040000 { + auart0: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; + }; + duart: serial@80070000 { pinctrl-names = "default"; pinctrl-0 = <&duart_pins_a>; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index daade4f..e78c1f4 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -18,6 +18,8 @@ gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; + serial0 = &auart0; + serial1 = &auart1; }; cpus { @@ -123,6 +125,19 @@ fsl,pull-up = <0>; }; + auart0_pins_a: auart0@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */ + 0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */ + 0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */ + 0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + mmc0_4bit_pins_a: mmc0-4bit@0 { reg = <0>; fsl,pinmux-ids = < @@ -289,12 +304,16 @@ }; auart0: serial@8006c000 { + compatible = "fsl,imx23-auart"; reg = <0x8006c000 0x2000>; + interrupts = <24 25 23>; status = "disabled"; }; auart1: serial@8006e000 { + compatible = "fsl,imx23-auart"; reg = <0x8006e000 0x2000>; + interrupts = <59 60 58>; status = "disabled"; }; -- cgit v0.10.2 From 64edbcdd9c8d2aac36bead7f8cdafe0ec02bab40 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 28 Jun 2012 11:45:01 +0800 Subject: ARM: dts: imx28-evk: add vmmc-supply for mmc device Add vmmc-supply for mmc device, so that the power to mmc slot can be turned on by mmc driver if bootloader hasn't done it. Also remove "okay" status for mmc1/ssp1, as the device has pin conflict with gpmi-nand. Actually the device is already disabled since the mxs-mmc driver adopts pinctrl support because there is no pinctrl setup for the device in dts. Make this explicit by removing "okay" status. Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 505ae5e..28b94d3 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -35,6 +35,7 @@ &mmc0_cd_cfg &mmc0_sck_cfg>; bus-width = <8>; wp-gpios = <&gpio2 12 0>; + vmmc-supply = <®_vddio_sd0>; status = "okay"; }; @@ -42,7 +43,6 @@ compatible = "fsl,imx28-mmc"; bus-width = <8>; wp-gpios = <&gpio0 28 0>; - status = "okay"; }; pinctrl@80018000 { @@ -141,6 +141,14 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + reg_vddio_sd0: vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 28 0>; + }; }; sound { -- cgit v0.10.2 From c9987c8106ac535bf207199be6ed4174d04dc679 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 28 Jun 2012 11:45:02 +0800 Subject: ARM: dts: imx28-evk: add missing properties for fec Add missing properties for fec, phy-supply, phy-reset-gpios and phy-reset-duration, which are required by fec driver for successfully probe fec from device tree, if bootloader hasn't set those things up. Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 28b94d3..cf2ab2e 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -120,6 +120,9 @@ phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&mac0_pins_a>; + phy-supply = <®_fec_3v3>; + phy-reset-gpios = <&gpio4 13 0>; + phy-reset-duration = <100>; status = "okay"; }; @@ -149,6 +152,14 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio3 28 0>; }; + + reg_fec_3v3: fec-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fec-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 15 0>; + }; }; sound { -- cgit v0.10.2 From a600e3335bad7d666eaebd2b18abd1bb7585a28a Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 28 Jun 2012 11:45:04 +0800 Subject: ARM: dts: imx28-evk: add heartbeat gpio-leds Add heartbeat gpio-leds for imx28-evk board. Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index cf2ab2e..856b26a 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -169,4 +169,14 @@ saif-controllers = <&saif0 &saif1>; audio-codec = <&sgtl5000>; }; + + leds { + compatible = "gpio-leds"; + + user { + label = "Heartbeat"; + gpios = <&gpio3 5 0>; + linux,default-trigger = "heartbeat"; + }; + }; }; -- cgit v0.10.2 From f98c990c18fb6df88bfd8f3131215604a87d26b1 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 28 Jun 2012 11:45:05 +0800 Subject: ARM: dts: mxs: enable rtc for imx23 and imx28 Enable rtc for imx23 and imx28. Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index e78c1f4..a94ba1d 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -289,8 +289,9 @@ }; rtc@8005c000 { + compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc"; reg = <0x8005c000 2000>; - status = "disabled"; + interrupts = <22>; }; pwm@80064000 { diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 42d6078..669c1d0 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -503,9 +503,9 @@ }; rtc@80056000 { + compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; reg = <0x80056000 2000>; - interrupts = <28 29>; - status = "disabled"; + interrupts = <29>; }; i2c0: i2c@80058000 { -- cgit v0.10.2 From 52f7176bd2a35ae712754d80c1206c69074a0a42 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 28 Jun 2012 11:45:06 +0800 Subject: ARM: dts: mxs: add pwm-backlight for imx23-evk and imx28-evk Add pwm device and pwm-backlight for imx23-evk and imx28-evk. Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index 9eca34f..3974959d 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -51,6 +51,12 @@ }; apbx@80040000 { + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pins_a>; + status = "okay"; + }; + auart0: serial@8006c000 { pinctrl-names = "default"; pinctrl-0 = <&auart0_pins_a>; @@ -76,4 +82,11 @@ gpio = <&gpio1 29 0>; }; }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 2 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; }; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index a94ba1d..22e1617 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -181,6 +181,16 @@ >; fsl,pull-up = <0>; }; + + pwm2_pins_a: pwm2@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x11c0 /* MX23_PAD_PWM2__PWM2 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; }; digctl@8001c000 { @@ -294,8 +304,11 @@ interrupts = <22>; }; - pwm@80064000 { + pwm: pwm@80064000 { + compatible = "fsl,imx23-pwm"; reg = <0x80064000 2000>; + #pwm-cells = <2>; + fsl,pwm-number = <5>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 856b26a..fba7292 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -95,6 +95,12 @@ }; }; + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pins_a>; + status = "okay"; + }; + duart: serial@80074000 { pinctrl-names = "default"; pinctrl-0 = <&duart_pins_a>; @@ -179,4 +185,11 @@ linux,default-trigger = "heartbeat"; }; }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 2 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; }; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 669c1d0..0ad7b56 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -364,6 +364,16 @@ fsl,voltage = <1>; fsl,pull-up = <1>; }; + + pwm2_pins_a: pwm2@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3120 /* MX28_PAD_PWM2__PWM_2 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; }; digctl@8001c000 { @@ -526,8 +536,11 @@ status = "disabled"; }; - pwm@80064000 { + pwm: pwm@80064000 { + compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; reg = <0x80064000 2000>; + #pwm-cells = <2>; + fsl,pwm-number = <8>; status = "disabled"; }; -- cgit v0.10.2 From a915ee4218f1c2416837b112945154c9c72670c0 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 28 Jun 2012 11:45:07 +0800 Subject: ARM: dts: mxs: add lcd support for imx23-evk and imx28-evk Add lcd support for imx23-evk and imx28-evk. Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index 3974959d..9d674ca 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -48,6 +48,13 @@ fsl,pull-up = <0>; }; }; + + lcdif@80030000 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a>; + panel-enable-gpios = <&gpio1 18 0>; + status = "okay"; + }; }; apbx@80040000 { diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 22e1617..7662134 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -191,6 +191,43 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; + + lcdif_24bit_pins_a: lcdif-24bit@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1000 /* MX23_PAD_LCD_D00__LCD_D0 */ + 0x1010 /* MX23_PAD_LCD_D01__LCD_D1 */ + 0x1020 /* MX23_PAD_LCD_D02__LCD_D2 */ + 0x1030 /* MX23_PAD_LCD_D03__LCD_D3 */ + 0x1040 /* MX23_PAD_LCD_D04__LCD_D4 */ + 0x1050 /* MX23_PAD_LCD_D05__LCD_D5 */ + 0x1060 /* MX23_PAD_LCD_D06__LCD_D6 */ + 0x1070 /* MX23_PAD_LCD_D07__LCD_D7 */ + 0x1080 /* MX23_PAD_LCD_D08__LCD_D8 */ + 0x1090 /* MX23_PAD_LCD_D09__LCD_D9 */ + 0x10a0 /* MX23_PAD_LCD_D10__LCD_D10 */ + 0x10b0 /* MX23_PAD_LCD_D11__LCD_D11 */ + 0x10c0 /* MX23_PAD_LCD_D12__LCD_D12 */ + 0x10d0 /* MX23_PAD_LCD_D13__LCD_D13 */ + 0x10e0 /* MX23_PAD_LCD_D14__LCD_D14 */ + 0x10f0 /* MX23_PAD_LCD_D15__LCD_D15 */ + 0x1100 /* MX23_PAD_LCD_D16__LCD_D16 */ + 0x1110 /* MX23_PAD_LCD_D17__LCD_D17 */ + 0x0081 /* MX23_PAD_GPMI_D08__LCD_D18 */ + 0x0091 /* MX23_PAD_GPMI_D09__LCD_D19 */ + 0x00a1 /* MX23_PAD_GPMI_D10__LCD_D20 */ + 0x00b1 /* MX23_PAD_GPMI_D11__LCD_D21 */ + 0x00c1 /* MX23_PAD_GPMI_D12__LCD_D22 */ + 0x00d1 /* MX23_PAD_GPMI_D13__LCD_D23 */ + 0x1160 /* MX23_PAD_LCD_DOTCK__LCD_DOTCK */ + 0x1170 /* MX23_PAD_LCD_ENABLE__LCD_ENABLE */ + 0x1180 /* MX23_PAD_LCD_HSYNC__LCD_HSYNC */ + 0x1190 /* MX23_PAD_LCD_VSYNC__LCD_VSYNC */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; }; digctl@8001c000 { @@ -229,7 +266,9 @@ }; lcdif@80030000 { + compatible = "fsl,imx23-lcdif"; reg = <0x80030000 2000>; + interrupts = <46 45>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index fba7292..ea7c51f 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -65,6 +65,13 @@ fsl,pull-up = <0>; }; }; + + lcdif@80030000 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a>; + panel-enable-gpios = <&gpio3 30 0>; + status = "okay"; + }; }; apbx@80040000 { diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 0ad7b56..44df2e6 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -374,6 +374,43 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; + + lcdif_24bit_pins_a: lcdif-24bit@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ + 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ + 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ + 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ + 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ + 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ + 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ + 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ + 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ + 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ + 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ + 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ + 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ + 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ + 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ + 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ + 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ + 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ + 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */ + 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */ + 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */ + 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */ + 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */ + 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */ + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; }; digctl@8001c000 { @@ -415,6 +452,7 @@ }; lcdif@80030000 { + compatible = "fsl,imx28-lcdif"; reg = <0x80030000 2000>; interrupts = <38 86>; status = "disabled"; -- cgit v0.10.2 From b9f25f86320f129fc9440426f5db29fd62a1c072 Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Tue, 3 Jul 2012 12:58:13 +0800 Subject: ARM: dts: mx23: add gpmi nand support Add DT node for gpmi nand. Also add pinctrl for gpmi nand. Enable the gpmi-nand in mx23-evk board. Signed-off-by: Huang Shijie Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index 9d674ca..e3486f4 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -22,6 +22,12 @@ apb@80000000 { apbh@80000000 { + gpmi-nand@8000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>; + status = "okay"; + }; + ssp0: ssp@80010000 { compatible = "fsl,imx23-mmc"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 7662134..a874dbf 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -59,13 +59,15 @@ status = "disabled"; }; - bch@8000a000 { - reg = <0x8000a000 2000>; - status = "disabled"; - }; - gpmi-nand@8000c000 { - reg = <0x8000c000 2000>; + compatible = "fsl,imx23-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x8000c000 2000>, <0x8000a000 2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <13>, <56>; + interrupt-names = "gpmi-dma", "bch"; + fsl,gpmi-dma-channel = <4>; status = "disabled"; }; @@ -138,6 +140,41 @@ fsl,pull-up = <0>; }; + gpmi_pins_a: gpmi-nand@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0000 /* MX23_PAD_GPMI_D00__GPMI_D00 */ + 0x0010 /* MX23_PAD_GPMI_D01__GPMI_D01 */ + 0x0020 /* MX23_PAD_GPMI_D02__GPMI_D02 */ + 0x0030 /* MX23_PAD_GPMI_D03__GPMI_D03 */ + 0x0040 /* MX23_PAD_GPMI_D04__GPMI_D04 */ + 0x0050 /* MX23_PAD_GPMI_D05__GPMI_D05 */ + 0x0060 /* MX23_PAD_GPMI_D06__GPMI_D06 */ + 0x0070 /* MX23_PAD_GPMI_D07__GPMI_D07 */ + 0x0100 /* MX23_PAD_GPMI_CLE__GPMI_CLE */ + 0x0110 /* MX23_PAD_GPMI_ALE__GPMI_ALE */ + 0x0130 /* MX23_PAD_GPMI_RDY0__GPMI_RDY0 */ + 0x0140 /* MX23_PAD_GPMI_RDY1__GPMI_RDY1 */ + 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */ + 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */ + 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */ + 0x21b0 /* MX23_PAD_GPMI_CE1N__GPMI_CE1N */ + 0x21c0 /* MX23_PAD_GPMI_CE0N__GPMI_CE0N */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + gpmi_pins_fixup: gpmi-pins-fixup { + fsl,pinmux-ids = < + 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */ + 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */ + 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */ + >; + fsl,drive-strength = <2>; + }; + mmc0_4bit_pins_a: mmc0-4bit@0 { reg = <0>; fsl,pinmux-ids = < -- cgit v0.10.2 From 5fc0b42a98556bd9f01cecc6a64fcbd15ec363f0 Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Fri, 22 Jun 2012 15:10:48 +0530 Subject: arm/dts: Add initial DT support for AM33XX SoC family Add device tree source include file for the AM33XX SoC family. An additional .dtsi file is created to describe the generic AM33XX CPU module like intc, ocp. Actual selection of available peripherals is handled in seperate .dts files using this am33xx.dtsi generic header file. Signed-off-by: AnilKumar Ch Reviewed-by: Vaibhav Hiremath Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi new file mode 100644 index 0000000..f46e353 --- /dev/null +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -0,0 +1,189 @@ +/* + * Device Tree Source for AM33XX SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "ti,am33xx"; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a8"; + }; + }; + + /* + * The soc node represents the soc top level view. It is uses for IPs + * that are not memory mapped in the MPU view or for the MPU itself. + */ + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; + }; + }; + + /* + * XXX: Use a flat representation of the AM33XX interconnect. + * The real AM33XX interconnect network is quite complex.Since + * that will not bring real advantage to represent that in DT + * for the moment, just use a fake OCP bus entry to represent + * the whole bus hierarchy. + */ + ocp { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main"; + + intc: interrupt-controller@48200000 { + compatible = "ti,omap2-intc"; + interrupt-controller; + #interrupt-cells = <1>; + ti,intc-size = <128>; + reg = <0x48200000 0x1000>; + }; + + gpio1: gpio@44e07000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio1"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio2: gpio@4804C000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio2"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio3: gpio@481AC000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio3"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio4: gpio@481AE000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio4"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + uart1: serial@44E09000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart2: serial@48022000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart3: serial@48024000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + + uart4: serial@481A6000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; + + uart5: serial@481A8000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart5"; + clock-frequency = <48000000>; + }; + + uart6: serial@481AA000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart6"; + clock-frequency = <48000000>; + }; + + i2c1: i2c@44E0B000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c1"; + }; + + i2c2: i2c@4802A000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c2"; + }; + + i2c3: i2c@4819C000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c3"; + }; + + mcspi1: spi@48030000 { + compatible = "ti,omap2-mcspi"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "spi0"; + ti,spi-num-cs = <4>; + }; + + mcspi2: spi@481Aa000 { + compatible = "ti,omap2-mcspi"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "spi1"; + ti,spi-num-cs = <2>; + }; + + mmc1: mmc@48060000 { + compatible = "ti,omap3-hsmmc"; + ti,hwmods = "mmc1"; + }; + + mmc2: mmc@481D8000 { + compatible = "ti,omap3-hsmmc"; + ti,hwmods = "mmc2"; + }; + + mmc3: mmc@47810000 { + compatible = "ti,omap3-hsmmc"; + ti,hwmods = "mmc3"; + }; + }; +}; -- cgit v0.10.2 From 32bb00e01d5590510e1d94f35a904b9e8d421d0b Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Fri, 22 Jun 2012 15:10:49 +0530 Subject: arm/dts: Add support for AM335x EVM Add AM335X EVM device tree source (am335x-evm.dts) file to use the am33xx.dtsi SoC file, along with the memory node information. Signed-off-by: AnilKumar Ch Reviewed-by: Vaibhav Hiremath Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts new file mode 100644 index 0000000..d6a97d9 --- /dev/null +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "am33xx.dtsi" + +/ { + model = "TI AM335x EVM"; + compatible = "ti,am335x-evm", "ti,am33xx"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; +}; -- cgit v0.10.2 From 6a66a8b29d3c72dcf30f805eceb9c1367ae6212b Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Fri, 22 Jun 2012 15:10:50 +0530 Subject: arm/dts: Add support for AM335x BeagleBone Add AM335X BeagleBone device tree source (am335x-evm.dts) file to use the am33xx.dtsi SoC file, along with the memory node information. Signed-off-by: AnilKumar Ch Reviewed-by: Vaibhav Hiremath Signed-off-by: Tony Lindgren diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt index e78e8bc..f186167 100644 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt @@ -47,3 +47,6 @@ Boards: - AM335X EVM : Software Developement Board for AM335x compatible = "ti,am335x-evm", "ti,am33xx", "ti,omap3" + +- AM335X Bone : Low cost community board + compatible = "ti,am335x-bone", "ti,am33xx", "ti,omap3" diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts new file mode 100644 index 0000000..a9af4db --- /dev/null +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "am33xx.dtsi" + +/ { + model = "TI AM335x BeagleBone"; + compatible = "ti,am335x-bone", "ti,am33xx"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; +}; -- cgit v0.10.2 From 3319f697154dfd1b44ab5da73970db9206da14db Mon Sep 17 00:00:00 2001 From: Uri Yosef Date: Mon, 2 Jul 2012 01:26:00 -0700 Subject: arm/dts: OMAP4: Add Variscite OMAP4 System-On-Modeule support Add Variscite OMAP4 System-On-Modeule support Signed-off-by: Uri Yosef [tony@atomide.com: updated to use disabled instead of disable] Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4-var_som.dts b/arch/arm/boot/dts/omap4-var_som.dts new file mode 100644 index 0000000..6601e6a --- /dev/null +++ b/arch/arm/boot/dts/omap4-var_som.dts @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap4.dtsi" + +/ { + model = "Variscite OMAP4 SOM"; + compatible = "var,omap4-var_som", "ti,omap4430", "ti,omap4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + vdd_eth: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "VDD_ETH"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + + twl: twl@48 { + reg = <0x48>; + /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ + interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ + interrupt-parent = <&gic>; + }; +}; + +/include/ "twl6030.dtsi" + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <400000>; + + /* + * Temperature Sensor + * http://www.ti.com/lit/ds/symlink/tmp105.pdf + */ + tmp105@49 { + compatible = "ti,tmp105"; + reg = <0x49>; + }; +}; + +&i2c4 { + clock-frequency = <400000>; +}; + +&mcspi1 { + eth@0 { + compatible = "ks8851"; + spi-max-frequency = <24000000>; + reg = <0>; + interrupt-parent = <&gpio6>; + interrupts = <11>; /* gpio line 171 */ + vdd-supply = <&vdd_eth>; + }; +}; + +&mmc1 { + vmmc-supply = <&vmmc>; + ti,bus-width = <8>; + ti,non-removable; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + ti,bus-width = <4>; +}; -- cgit v0.10.2 From b9df44919cd0a776abab442b59c8bf9a8b7301fc Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 4 Jul 2012 13:22:53 -0300 Subject: ARM: mx23: Add initial support for olinuxino board mx23-olinuxino is a low cost board designed by Olimex. It has the following features: - Freescale iMX233 ARM926J processor at 454MHz -64 MB RAM -SD-card connector -TV PAL/NTSC video output -2 USB High Speed Hosts -Ethernet 100 Mbit -Stereo Audio Input -Stereo Headphones Audio Output More information at: http://www.olimex.com/dev/imx233-olinuxino-maxi.html Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/Documentation/devicetree/bindings/arm/olimex.txt b/Documentation/devicetree/bindings/arm/olimex.txt new file mode 100644 index 0000000..007fb5c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/olimex.txt @@ -0,0 +1,6 @@ +Olimex i.MX Platforms Device Tree Bindings +------------------------------------------ + +i.MX23 Olinuxino Low Cost Board +Required root node properties: + - compatible = "olimex,imx23-olinuxino", "fsl,imx23"; diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts new file mode 100644 index 0000000..20912b1 --- /dev/null +++ b/arch/arm/boot/dts/imx23-olinuxino.dts @@ -0,0 +1,44 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx23.dtsi" + +/ { + model = "i.MX23 Olinuxino Low Cost Board"; + compatible = "olimex,imx23-olinuxino", "fsl,imx23"; + + memory { + reg = <0x40000000 0x04000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; + bus-width = <4>; + status = "okay"; + }; + }; + + apbx@80040000 { + duart: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 87a4829..7bbb961 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -216,6 +216,7 @@ static void __init mxs_machine_init(void) static const char *imx23_dt_compat[] __initdata = { "fsl,imx23-evk", + "olimex,imx23-olinuxino", "fsl,imx23", NULL, }; -- cgit v0.10.2 From 961e657f5a34e3f4ce2cb74cfab11f5c666b03e5 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 30 May 2012 12:18:58 +0200 Subject: ARM: davinci: cp_intc: Add OF support for TI interrupt controller Add a function to initialize the Common Platform Interrupt Controller (cp_intc) from TI used on OMAP-L1x SoCs using a device tree node. Signed-off-by: Heiko Schocher Cc: davinci-linux-open-source@linux.davincidsp.com Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree-discuss@lists.ozlabs.org Cc: Grant Likely Cc: Sekhar Nori Cc: Wolfgang Denk Cc: Sergei Shtylyov Signed-off-by: Sekhar Nori diff --git a/Documentation/devicetree/bindings/arm/davinci/cp-intc.txt b/Documentation/devicetree/bindings/arm/davinci/cp-intc.txt new file mode 100644 index 0000000..597e8a0 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/davinci/cp-intc.txt @@ -0,0 +1,27 @@ +* TI Common Platform Interrupt Controller + +Common Platform Interrupt Controller (cp_intc) is used on +OMAP-L1x SoCs and can support several configurable number +of interrupts. + +Main node required properties: + +- compatible : should be: + "ti,cp-intc" +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The type shall be a and the value shall be 1. + + The cell contains the interrupt number in the range [0-128]. +- ti,intc-size: Number of interrupts handled by the interrupt controller. +- reg: physical base address and size of the intc registers map. + +Example: + + intc: interrupt-controller@1 { + compatible = "ti,cp-intc"; + interrupt-controller; + #interrupt-cells = <1>; + ti,intc-size = <101>; + reg = <0xfffee000 0x2000>; + }; diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c index 45d5256..006dae8 100644 --- a/arch/arm/mach-davinci/cp_intc.c +++ b/arch/arm/mach-davinci/cp_intc.c @@ -14,6 +14,9 @@ #include #include #include +#include +#include +#include #include #include @@ -119,7 +122,7 @@ static const struct irq_domain_ops cp_intc_host_ops = { .xlate = irq_domain_xlate_onetwocell, }; -int __init __cp_intc_init(struct device_node *node) +int __init cp_intc_of_init(struct device_node *node, struct device_node *parent) { u32 num_irq = davinci_soc_info.intc_irq_num; u8 *irq_prio = davinci_soc_info.intc_irq_prios; @@ -128,7 +131,14 @@ int __init __cp_intc_init(struct device_node *node) int i, irq_base; davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC; - davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K); + if (node) { + davinci_intc_base = of_iomap(node, 0); + if (of_property_read_u32(node, "ti,intc-size", &num_irq)) + pr_warn("unable to get intc-size, default to %d\n", + num_irq); + } else { + davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K); + } if (WARN_ON(!davinci_intc_base)) return -EINVAL; @@ -208,5 +218,5 @@ int __init __cp_intc_init(struct device_node *node) void __init cp_intc_init(void) { - __cp_intc_init(NULL); + cp_intc_of_init(NULL, NULL); } diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h index 4e8190e..d13d8df 100644 --- a/arch/arm/mach-davinci/include/mach/cp_intc.h +++ b/arch/arm/mach-davinci/include/mach/cp_intc.h @@ -52,5 +52,6 @@ #define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2)) void __init cp_intc_init(void); +int __init cp_intc_of_init(struct device_node *, struct device_node *); #endif /* __ASM_HARDWARE_CP_INTC_H */ -- cgit v0.10.2 From 6ca44acfc31ad485b18e2fca0428479b7d4f141d Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 28 Jun 2012 11:45:03 +0800 Subject: ARM: dts: imx28-evk: add flexan devices Add flexan devices for imx28-evk board. Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index ea7c51f..0d8739d 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -72,6 +72,18 @@ panel-enable-gpios = <&gpio3 30 0>; status = "okay"; }; + + can0: can@80032000 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + status = "okay"; + }; + + can1: can@80034000 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + status = "okay"; + }; }; apbx@80040000 { diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 44df2e6..adb5ffc 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -411,6 +411,28 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; + + can0_pins_a: can0@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */ + 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + can1_pins_a: can1@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */ + 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; }; digctl@8001c000 { @@ -459,12 +481,14 @@ }; can0: can@80032000 { + compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; reg = <0x80032000 2000>; interrupts = <8>; status = "disabled"; }; can1: can@80034000 { + compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; reg = <0x80034000 2000>; interrupts = <9>; status = "disabled"; -- cgit v0.10.2 From c1cb438522f2cd62fb3a261d66a549606c131c93 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 28 Jun 2012 11:15:37 +0800 Subject: bindings: update imx and mxs #gpio-cells The of_get_named_gpio_flags can retrieve the second cell of gpio-specifier as the "flags". The imx and mxs gpio driver do not have their own .xlate callback, which means of_gpio_simple_xlate is used and it's a 1:1 mapping between gpio controller flags and Linux "enum of_gpio_flags". Update imx and mxs bindings document to make it clear. Signed-off-by: Shawn Guo diff --git a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt b/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt index 4363ae4..5f360e7 100644 --- a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt +++ b/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt @@ -8,8 +8,9 @@ Required properties: by low 16 pins and the second one is for high 16 pins. - gpio-controller : Marks the device node as a gpio controller. - #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify optional parameters (currently - unused). + the second cell is used to specify the gpio polarity: + 0 = active high + 1 = active low Example: diff --git a/Documentation/devicetree/bindings/gpio/gpio-mxs.txt b/Documentation/devicetree/bindings/gpio/gpio-mxs.txt index 0c35673..1e677a4 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mxs.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-mxs.txt @@ -13,8 +13,9 @@ Required properties for GPIO node: - interrupts : Should be the port interrupt shared by all 32 pins. - gpio-controller : Marks the device node as a gpio controller. - #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify optional parameters (currently - unused). + the second cell is used to specify the gpio polarity: + 0 = active high + 1 = active low - interrupt-controller: Marks the device node as an interrupt controller. - #interrupt-cells : Should be 2. The first cell is the GPIO number. The second cell bits[3:0] is used to specify trigger type and level flags: -- cgit v0.10.2 From c80efbae6a53d9702630fc5f96662f96a45ca56a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 20 Apr 2012 16:57:38 -0600 Subject: ARM: dt: tegra: add Whistler device tree file Whistler is a highly configurable Tegra evaluation and development board. This change adds support for the following specific configuration: E1120 motherboard E1108 CPU board E1116 PMU board The motherboard configuration switches are set as follows: SW1=0 SW2=0 SW3=5 S1/S2/S3/S4 all on, except S3 7/8 are off. Other combinations of daugher boards may work to varying degrees, but will likely require some SW adjustment. Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts new file mode 100644 index 0000000..6916310 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -0,0 +1,301 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "NVIDIA Tegra2 Whistler evaluation board"; + compatible = "nvidia,whistler", "nvidia,tegra20"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata", "atb", "ate", "gma", "gmb", + "gmc", "gmd", "gpu"; + nvidia,function = "gmi"; + }; + atc { + nvidia,pins = "atc", "atd"; + nvidia,function = "sdio4"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "osc"; + }; + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd"; + nvidia,function = "vi"; + }; + dte { + nvidia,pins = "dte"; + nvidia,function = "rsvd1"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gme { + nvidia,pins = "gme"; + nvidia,function = "dap5"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint", "pta"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uartb"; + }; + kbca { + nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + kbcb { + nvidia,pins = "kbcb", "kbcd"; + nvidia,function = "sdio2"; + }; + lcsn { + nvidia,pins = "lcsn", "lsck", "lsda", "lsdi", + "spia", "spib", "spic"; + nvidia,function = "spi3"; + }; + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldc", "ldi", + "lhp0", "lhp1", "lhp2", "lhs", "lm0", + "lm1", "lpp", "lpw0", "lpw1", "lpw2", + "lsc0", "lsc1", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "uac"; + nvidia,function = "owr"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd", "slxa", + "slxc", "slxd", "slxk"; + nvidia,function = "sdio3"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + spdi { + nvidia,pins = "spdi", "spdo"; + nvidia,function = "rsvd2"; + }; + spid { + nvidia,pins = "spid", "spie", "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + spif { + nvidia,pins = "spif"; + nvidia,function = "spi2"; + }; + uaa { + nvidia,pins = "uaa", "uab"; + nvidia,function = "uarta"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + uda { + nvidia,pins = "uda"; + nvidia,function = "spi1"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "ddc", "gma", + "gmb", "gmc", "gmd", "irrx", "irtx", + "kbca", "kbcb", "kbcc", "kbcd", "kbce", + "kbcf", "sdc", "sdd", "spie", "spig", + "spih", "uaa", "uab", "uad", "uca", + "ucb"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; + conf_atd { + nvidia,pins = "atd", "ate", "cdev1", "csus", + "dap1", "dap2", "dap3", "dap4", "dte", + "dtf", "gpu", "gpu7", "gpv", "i2cp", + "rm", "sdio1", "slxa", "slxc", "slxd", + "slxk", "spdi", "spdo", "uac", "uda"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + conf_cdev2 { + nvidia,pins = "cdev2", "spia", "spib"; + nvidia,pull = <1>; + nvidia,tristate = <1>; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "lc", "pmca", + "pmcb", "pmcc", "pmcd", "xm2c", + "xm2d"; + nvidia,pull = <0>; + }; + conf_crtp { + nvidia,pins = "crtp"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + conf_dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", + "spid", "spif"; + nvidia,pull = <1>; + nvidia,tristate = <0>; + }; + conf_gme { + nvidia,pins = "gme", "owc", "pta", "spic"; + nvidia,pull = <2>; + nvidia,tristate = <1>; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = <1>; + }; + conf_ls { + nvidia,pins = "ls", "pmce"; + nvidia,pull = <2>; + }; + drive_dap1 { + nvidia,pins = "drive_dap1"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <1>; + nvidia,low-power-mode = <0>; + nvidia,pull-down-strength = <0>; + nvidia,pull-up-strength = <0>; + nvidia,slew-rate-rising = <0>; + nvidia,slew-rate-falling = <0>; + }; + }; + }; + + i2s@70002800 { + status = "okay"; + }; + + serial@70006000 { + status = "okay"; + clock-frequency = <216000000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + codec: codec@1a { + compatible = "wlf,wm8753"; + reg = <0x1a>; + }; + + tca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + usb@c5000000 { + status = "okay"; + nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */ + }; + + usb@c5008000 { + status = "okay"; + nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */ + }; + + sdhci@c8000400 { + status = "okay"; + wp-gpios = <&gpio 173 0>; /* gpio PV5 */ + bus-width = <8>; + }; + + sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8753-whistler", + "nvidia,tegra-audio-wm8753"; + nvidia,model = "NVIDIA Tegra Whistler"; + + nvidia,audio-routing = + "Headphone Jack", "LOUT1", + "Headphone Jack", "ROUT1", + "MIC2", "Mic Jack", + "MIC2N", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&codec>; + }; +}; diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index 8040345..435f00c 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot @@ -7,4 +7,5 @@ dtb-$(CONFIG_MACH_PAZ00) += tegra20-paz00.dtb dtb-$(CONFIG_MACH_SEABOARD) += tegra20-seaboard.dtb dtb-$(CONFIG_MACH_TRIMSLICE) += tegra20-trimslice.dtb dtb-$(CONFIG_MACH_VENTANA) += tegra20-ventana.dtb +dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu.dtb -- cgit v0.10.2 From a18cf6dcbf6160fe4b39449f996f9f3ed37198cc Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 16 Apr 2012 17:41:17 -0600 Subject: ARM: dt: tegra: seaboard: instantiate pinctrl-based I2C bus mux Tegra's I2C2 controller can be routed to either the PTA or DDC pin group on Seaboard. Define the pinctrl state nodes required to allow runtime control of this routing. Instantiate a pinctrl-i2cmux I2C bus mux that uses these pinctrl states. Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index b797901..1e1939f 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -64,11 +64,6 @@ nvidia,pins = "dap4"; nvidia,function = "dap4"; }; - ddc { - nvidia,pins = "ddc", "owc", "spdi", "spdo", - "uac"; - nvidia,function = "rsvd2"; - }; dta { nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; nvidia,function = "vi"; @@ -129,14 +124,14 @@ "lspi", "lvp1", "lvs"; nvidia,function = "displaya"; }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; pmc { nvidia,pins = "pmc"; nvidia,function = "pwr_on"; }; - pta { - nvidia,pins = "pta"; - nvidia,function = "i2c2"; - }; rm { nvidia,pins = "rm"; nvidia,function = "i2c1"; @@ -176,7 +171,7 @@ conf_ata { nvidia,pins = "ata", "atb", "atc", "atd", "cdev1", "cdev2", "dap1", "dap2", - "dap4", "dtf", "gma", "gmc", "gmd", + "dap4", "ddc", "dtf", "gma", "gmc", "gmd", "gme", "gpu", "gpu7", "i2cp", "irrx", "irtx", "pta", "rm", "sdc", "sdd", "slxd", "slxk", "spdi", "spdo", "uac", @@ -185,7 +180,7 @@ nvidia,tristate = <0>; }; conf_ate { - nvidia,pins = "ate", "csus", "dap3", "ddc", + nvidia,pins = "ate", "csus", "dap3", "gpv", "owc", "slxc", "spib", "spid", "spie"; nvidia,pull = <0>; @@ -255,6 +250,39 @@ nvidia,slew-rate-falling = <3>; }; }; + + state_i2cmux_ddc: pinmux_i2cmux_ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux_i2cmux_pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + + state_i2cmux_idle: pinmux_i2cmux_idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; }; i2s@70002800 { @@ -312,6 +340,31 @@ }; }; + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + i2c@7000c500 { status = "okay"; clock-frequency = <400000>; -- cgit v0.10.2 From 0879c5f72f0a3905d08081e8a2c38e69896b0d5e Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 25 Apr 2012 16:57:28 -0600 Subject: ARM: dt: tegra seaboard: move battery monitor to mux'd I2C bus. Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 1e1939f..85e621a 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -331,13 +331,6 @@ i2c@7000c400 { status = "okay"; clock-frequency = <100000>; - - smart-battery@b { - compatible = "ti,bq20z75", "smart-battery-1.1"; - reg = <0xb>; - ti,i2c-retry-count = <2>; - ti,poll-retry-count = <10>; - }; }; i2cmux { @@ -362,6 +355,13 @@ reg = <1>; #address-cells = <1>; #size-cells = <0>; + + smart-battery@b { + compatible = "ti,bq20z75", "smart-battery-1.1"; + reg = <0xb>; + ti,i2c-retry-count = <2>; + ti,poll-retry-count = <10>; + }; }; }; -- cgit v0.10.2 From 88cde8b78f6914ce542949e5a8dd9031e3035996 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Fri, 6 Jul 2012 20:03:37 +0800 Subject: ARM: dts: imx: update #interrupt-cells for gpio nodes Change the value of #interrupt-cells of gpio nodes from 1 to 2, so that the gpio irq type can be specified in device tree. Also update binding document to make it clear. Reported-by: Sascha Hauer Acked-by: Sascha Hauer Signed-off-by: Shawn Guo diff --git a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt b/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt index 5f360e7..4f39297 100644 --- a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt +++ b/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt @@ -11,6 +11,13 @@ Required properties: the second cell is used to specify the gpio polarity: 0 = active high 1 = active low +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells : Should be 2. The first cell is the GPIO number. + The second cell bits[3:0] is used to specify trigger type and level flags: + 1 = low-to-high edge triggered. + 2 = high-to-low edge triggered. + 4 = active high level-sensitive. + 8 = active low level-sensitive. Example: @@ -20,4 +27,6 @@ gpio0: gpio@73f84000 { interrupts = <50 51>; gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 386c769..00bae3a 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -121,7 +121,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio2: gpio@10015100 { @@ -131,7 +131,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio3: gpio@10015200 { @@ -141,7 +141,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio4: gpio@10015300 { @@ -151,7 +151,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio5: gpio@10015400 { @@ -161,7 +161,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio6: gpio@10015500 { @@ -171,7 +171,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; cspi3: cspi@10017000 { diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index bfa65ab..922adef 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -133,7 +133,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio2: gpio@73f88000 { @@ -143,7 +143,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio3: gpio@73f8c000 { @@ -153,7 +153,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio4: gpio@73f90000 { @@ -163,7 +163,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; wdog@73f98000 { /* WDOG1 */ diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index e3e8694..4e735ed 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -135,7 +135,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio2: gpio@53f88000 { @@ -145,7 +145,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio3: gpio@53f8c000 { @@ -155,7 +155,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio4: gpio@53f90000 { @@ -165,7 +165,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; wdog@53f98000 { /* WDOG1 */ @@ -203,7 +203,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio6: gpio@53fe0000 { @@ -213,7 +213,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio7: gpio@53fe4000 { @@ -223,7 +223,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; i2c@53fec000 { /* I2C3 */ diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 16a3884..bf88fb7 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -283,7 +283,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio2: gpio@020a0000 { @@ -293,7 +293,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio3: gpio@020a4000 { @@ -303,7 +303,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio4: gpio@020a8000 { @@ -313,7 +313,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio5: gpio@020ac000 { @@ -323,7 +323,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio6: gpio@020b0000 { @@ -333,7 +333,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio7: gpio@020b4000 { @@ -343,7 +343,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; kpp@020b8000 { -- cgit v0.10.2 From 5349f2a89e6a31c8d39c4ec2618b9dd6e421c415 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 11 Apr 2012 22:12:11 -0300 Subject: ARM: dts: Add basic support for mx27_3ds board Add a very basic dt support for mx27_3ds (also known as mx27pdk). Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/boot/dts/imx27-3ds.dts b/arch/arm/boot/dts/imx27-3ds.dts new file mode 100644 index 0000000..d3f8296 --- /dev/null +++ b/arch/arm/boot/dts/imx27-3ds.dts @@ -0,0 +1,41 @@ +/* + * Copyright 2012 Sascha Hauer, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx27.dtsi" + +/ { + model = "mx27_3ds"; + compatible = "freescale,imx27-3ds", "fsl,imx27"; + + memory { + reg = <0x0 0x0>; + }; + + soc { + aipi@10000000 { /* aipi */ + + wdog@10002000 { + status = "okay"; + }; + + uart@1000a000 { + fsl,uart-has-rtscts; + status = "okay"; + }; + + fec@1002b000 { + status = "okay"; + }; + }; + }; + +}; -- cgit v0.10.2 From 94c30732944a03c5d4249abefbea09147579fb92 Mon Sep 17 00:00:00 2001 From: Xiao Jiang Date: Fri, 1 Jun 2012 12:44:14 +0800 Subject: arm/dts: add wdt node for omap3 and omap4 Add wdt node to support dt. Signed-off-by: Xiao Jiang Signed-off-by: Tony Lindgren diff --git a/Documentation/devicetree/bindings/watchdog/omap-wdt.txt b/Documentation/devicetree/bindings/watchdog/omap-wdt.txt new file mode 100644 index 0000000..c227970 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/omap-wdt.txt @@ -0,0 +1,14 @@ +TI Watchdog Timer (WDT) Controller for OMAP + +Required properties: +compatible: +- "ti,omap3-wdt" for OMAP3 +- "ti,omap4-wdt" for OMAP4 +- ti,hwmods: Name of the hwmod associated to the WDT + +Examples: + +wdt2: wdt@4a314000 { + compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + ti,hwmods = "wd_timer2"; +}; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 99474fa..8109471 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -215,5 +215,10 @@ compatible = "ti,omap3-hsmmc"; ti,hwmods = "mmc3"; }; + + wdt2: wdt@48314000 { + compatible = "ti,omap3-wdt"; + ti,hwmods = "wd_timer2"; + }; }; }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 359c497..3664641 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -272,5 +272,10 @@ ti,hwmods = "mmc5"; ti,needs-special-reset; }; + + wdt2: wdt@4a314000 { + compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + ti,hwmods = "wd_timer2"; + }; }; }; -- cgit v0.10.2 From 6e152231995aa4ed5eafd87a6a8348563248f843 Mon Sep 17 00:00:00 2001 From: Xiao Jiang Date: Fri, 1 Jun 2012 12:44:15 +0800 Subject: ARM: OMAP: avoid build wdt platform device if with dt support If provided dt support, then skip add wdt platform device as usual. Signed-off-by: Xiao Jiang Reviewed-by: Jon Hunter Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 7b4b932..527c004 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -772,7 +772,7 @@ static int __init omap_init_wdt(void) char *oh_name = "wd_timer2"; char *dev_name = "omap_wdt"; - if (!cpu_class_is_omap2()) + if (!cpu_class_is_omap2() || of_have_populated_dt()) return 0; oh = omap_hwmod_lookup(oh_name); -- cgit v0.10.2 From e6ca04eaabbd5599b79c54db9a4dd8e9bfb424ec Mon Sep 17 00:00:00 2001 From: Xiao Jiang Date: Fri, 1 Jun 2012 12:44:16 +0800 Subject: watchdog: omap_wdt: add device tree support Add device table for omap_wdt to support dt. Signed-off-by: Xiao Jiang Acked-by: Wim Van Sebroeck Signed-off-by: Tony Lindgren diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 8285d65..02ebfd5 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -430,6 +430,12 @@ static int omap_wdt_resume(struct platform_device *pdev) #define omap_wdt_resume NULL #endif +static const struct of_device_id omap_wdt_of_match[] = { + { .compatible = "ti,omap3-wdt", }, + {}, +}; +MODULE_DEVICE_TABLE(of, omap_wdt_of_match); + static struct platform_driver omap_wdt_driver = { .probe = omap_wdt_probe, .remove = __devexit_p(omap_wdt_remove), @@ -439,6 +445,7 @@ static struct platform_driver omap_wdt_driver = { .driver = { .owner = THIS_MODULE, .name = "omap_wdt", + .of_match_table = omap_wdt_of_match, }, }; -- cgit v0.10.2 From b7e0683d74c36b6477e2c53baf045202b9d2054a Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Mon, 9 Jul 2012 11:54:09 +0530 Subject: arm/dts: remove MMC/SD and SPI related entries from am33xx.dtsi The MMC/SD and SPI entries in this file are not tested yet. They inadvertently came into the patch because of some work in progress stuff I had in my repo. These entries should not have been sent out in the first place and I am sorry for the trouble and will be extra careful in future. Since the offending commit is not sent upstream yet, I hope this can be merged into the commit 5fc0b42a98556bd9f01cecc6a64fcbd15ec363f0 (arm/dts: Add initial DT support for AM33XX SoC family) on the devel-dt branch of linux-omap tree. Signed-off-by: AnilKumar Ch Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index f46e353..59509c4 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -154,36 +154,5 @@ #size-cells = <0>; ti,hwmods = "i2c3"; }; - - mcspi1: spi@48030000 { - compatible = "ti,omap2-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "spi0"; - ti,spi-num-cs = <4>; - }; - - mcspi2: spi@481Aa000 { - compatible = "ti,omap2-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "spi1"; - ti,spi-num-cs = <2>; - }; - - mmc1: mmc@48060000 { - compatible = "ti,omap3-hsmmc"; - ti,hwmods = "mmc1"; - }; - - mmc2: mmc@481D8000 { - compatible = "ti,omap3-hsmmc"; - ti,hwmods = "mmc2"; - }; - - mmc3: mmc@47810000 { - compatible = "ti,omap3-hsmmc"; - ti,hwmods = "mmc3"; - }; }; }; -- cgit v0.10.2 -- cgit v0.10.2 From 4f4b5c7418692342551d38e28e8a686b1bb311db Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 8 Jun 2012 17:01:59 +0300 Subject: arm/dts: omap4: Add entry for OMAP McPDM IP McPDM is used on OMAP4 based boards to communicate with an external audio codec (twl6040). Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 3664641..5a5b5e8 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -277,5 +277,14 @@ compatible = "ti,omap4-wdt", "ti,omap3-wdt"; ti,hwmods = "wd_timer2"; }; + + mcpdm: mcpdm@40132000 { + compatible = "ti,omap4-mcpdm"; + reg = <0x40132000 0x7f>, /* MPU private access */ + <0x49032000 0x7f>; /* L3 Interconnect */ + interrupts = <0 112 0x4>; + interrupt-parent = <&gic>; + ti,hwmods = "mcpdm"; + }; }; }; -- cgit v0.10.2 From a4c383196ed11283f26411dc152b7553a1f0ee9b Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 8 Jun 2012 17:02:00 +0300 Subject: arm/dts: omap4: Add entry for OMAP DMIC IP DMIC IP is used to connect up to 6 digital microphones directly to OMAP. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 5a5b5e8..04cbbcb 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -286,5 +286,14 @@ interrupt-parent = <&gic>; ti,hwmods = "mcpdm"; }; + + dmic: dmic@4012e000 { + compatible = "ti,omap4-dmic"; + reg = <0x4012e000 0x7f>, /* MPU private access */ + <0x4902e000 0x7f>; /* L3 Interconnect */ + interrupts = <0 114 0x4>; + interrupt-parent = <&gic>; + ti,hwmods = "dmic"; + }; }; }; -- cgit v0.10.2 From 4814f2f7a9b09866527c1e95a8947e47b348133e Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 8 Jun 2012 17:02:01 +0300 Subject: arm/dts: omap4-sdp: Add fixed regulator to represent VBAT There are devices connected to VBAT. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index d08c4d1..b33f261 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -28,6 +28,14 @@ regulator-boot-on; }; + vbat: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "VBAT"; + regulator-min-microvolt = <3750000>; + regulator-max-microvolt = <3750000>; + regulator-boot-on; + }; + leds { compatible = "gpio-leds"; debug0 { -- cgit v0.10.2 From efd2af55b40d9f8fc12dc0187a1e0cbe4d9f42d1 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 8 Jun 2012 17:02:02 +0300 Subject: arm/dts: omap4-sdp: Add support for twl6040 The twl6040 provides the audio and vibra support on OMAP4 SDP boards. It is connected to i2c1 bus with 0x4b address. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index b33f261..e54f481 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -89,6 +89,31 @@ interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ interrupt-parent = <&gic>; }; + + twl6040: twl@4b { + compatible = "ti,twl6040"; + reg = <0x4b>; + /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ + interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */ + interrupt-parent = <&gic>; + ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */ + + vio-supply = <&v1v8>; + v2v1-supply = <&v2v1>; + enable-active-high; + + /* regulators for vibra motor */ + vddvibl-supply = <&vbat>; + vddvibr-supply = <&vbat>; + + vibra { + /* Vibra driver, motor resistance parameters */ + ti,vibldrv-res = <8>; + ti,vibrdrv-res = <3>; + ti,viblmotor-res = <10>; + ti,vibrmotor-res = <10>; + }; + }; }; /include/ "twl6030.dtsi" -- cgit v0.10.2 From b15bb2c066dc96291e993dde62ec71f74fd44313 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 8 Jun 2012 17:02:03 +0300 Subject: arm/dts: omap4-sdp: Enable audio support via device tree On OMAP4 SDP the audio setup includes the twl6040 codec and digital microphones. Since OMAP4 SDP is a reference board it has all possible audio interfaces connected. This information is passed via the ti,audio-routing property. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index e54f481..a18cf10 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -78,6 +78,41 @@ gpios = <&gpio5 11 0>; /* 139 */ }; }; + + sound { + compatible = "ti,abe-twl6040"; + ti,model = "SDP4430"; + + ti,jack-detection = <1>; + ti,mclk-freq = <38400000>; + + ti,mcpdm = <&mcpdm>; + ti,dmic = <&dmic>; + + ti,twl6040 = <&twl6040>; + + /* Audio routing */ + ti,audio-routing = + "Headset Stereophone", "HSOL", + "Headset Stereophone", "HSOR", + "Earphone Spk", "EP", + "Ext Spk", "HFL", + "Ext Spk", "HFR", + "Line Out", "AUXL", + "Line Out", "AUXR", + "Vibrator", "VIBRAL", + "Vibrator", "VIBRAR", + "HSMIC", "Headset Mic", + "Headset Mic", "Headset Mic Bias", + "MAINMIC", "Main Handset Mic", + "Main Handset Mic", "Main Mic Bias", + "SUBMIC", "Sub Handset Mic", + "Sub Handset Mic", "Main Mic Bias", + "AFML", "Line In", + "AFMR", "Line In", + "DMic", "Digital Mic", + "Digital Mic", "Digital Mic1 Bias"; + }; }; &i2c1 { -- cgit v0.10.2 From 6cd3bc398401f533b299e06da80c0e939f9988db Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 8 Jun 2012 17:02:04 +0300 Subject: arm/dts: omap4-panda: Audio support for PandaBoard 4430 PandaBoard uses twl6040 connected via McPDM for audio. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts index 1efe0c5..f57f5e8 100644 --- a/arch/arm/boot/dts/omap4-panda.dts +++ b/arch/arm/boot/dts/omap4-panda.dts @@ -32,6 +32,30 @@ linux,default-trigger = "mmc0"; }; }; + + sound: sound { + compatible = "ti,abe-twl6040"; + ti,model = "PandaBoard"; + + ti,mclk-freq = <38400000>; + + ti,mcpdm = <&mcpdm>; + + ti,twl6040 = <&twl6040>; + + /* Audio routing */ + ti,audio-routing = + "Headset Stereophone", "HSOL", + "Headset Stereophone", "HSOR", + "Ext Spk", "HFL", + "Ext Spk", "HFR", + "Line Out", "AUXL", + "Line Out", "AUXR", + "HSMIC", "Headset Mic", + "Headset Mic", "Headset Mic Bias", + "AFML", "Line In", + "AFMR", "Line In"; + }; }; &i2c1 { @@ -43,6 +67,19 @@ interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ interrupt-parent = <&gic>; }; + + twl6040: twl@4b { + compatible = "ti,twl6040"; + reg = <0x4b>; + /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ + interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */ + interrupt-parent = <&gic>; + ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */ + + vio-supply = <&v1v8>; + v2v1-supply = <&v2v1>; + enable-active-high; + }; }; /include/ "twl6030.dtsi" -- cgit v0.10.2 From f700c4d780f14125f61b70e86d805908efe3fb89 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 8 Jun 2012 17:02:05 +0300 Subject: arm/dts: New dts file for PandaBoardES (4460) The 4430 and 4460 version of PandaBoard mostly the same with exception at least in audio setup. Use the omap4-panda.dts file as a base and only override the differences between the revisions. For audio it is the name of the sound card and the routing information. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4-pandaES.dts b/arch/arm/boot/dts/omap4-pandaES.dts new file mode 100644 index 0000000..d4ba43a --- /dev/null +++ b/arch/arm/boot/dts/omap4-pandaES.dts @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/include/ "omap4-panda.dts" + +/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */ +&sound { + ti,model = "PandaBoardES"; + + /* Audio routing */ + ti,audio-routing = + "Headset Stereophone", "HSOL", + "Headset Stereophone", "HSOR", + "Ext Spk", "HFL", + "Ext Spk", "HFR", + "Line Out", "AUXL", + "Line Out", "AUXR", + "AFML", "Line In", + "AFMR", "Line In"; +}; -- cgit v0.10.2 From 2e8e4711fed439fc5642e80ee5797d285c11c7d3 Mon Sep 17 00:00:00 2001 From: Fabio Porcedda Date: Wed, 27 Jun 2012 11:08:19 +0200 Subject: ARM: at91: add support for Telit EVK-PRO3 with Telit GE863-PRO3 Signed-off-by: Fabio Porcedda Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts new file mode 100644 index 0000000..b7354e6 --- /dev/null +++ b/arch/arm/boot/dts/evk-pro3.dts @@ -0,0 +1,41 @@ +/* + * evk-pro3.dts - Device Tree file for Telit EVK-PRO3 with Telit GE863-PRO3 + * + * Copyright (C) 2012 Telit, + * 2012 Fabio Porcedda + * + * Licensed under GPLv2 or later. + */ + +/dts-v1/; + +/include/ "ge863-pro3.dtsi" + +/ { + model = "Telit EVK-PRO3 for Telit GE863-PRO3"; + compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9"; + + ahb { + apb { + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 0>; + status = "okay"; + }; + }; + + usb0: ohci@00500000 { + num-ports = <2>; + status = "okay"; + }; + }; + + i2c@0 { + status = "okay"; + }; + +}; \ No newline at end of file diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi new file mode 100644 index 0000000..17136fc --- /dev/null +++ b/arch/arm/boot/dts/ge863-pro3.dtsi @@ -0,0 +1,52 @@ +/* + * ge863_pro3.dtsi - Device Tree file for Telit GE863-PRO3 + * + * Copyright (C) 2012 Telit, + * 2012 Fabio Porcedda + * + * Licensed under GPLv2 or later. + */ + +/include/ "at91sam9260.dtsi" + +/ { + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <6000000>; + }; + }; + + ahb { + apb { + dbgu: serial@fffff200 { + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + boot@0 { + label = "boot"; + reg = <0x0 0x7c0000>; + }; + + root@07c0000 { + label = "root"; + reg = <0x7c0000 0x7840000>; + }; + }; + }; + + chosen { + bootargs = "console=ttyS0,115200 root=ubi0:rootfs ubi.mtd=1 rootfstype=ubifs"; + }; +}; diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot index 9e84fe4..11c3ca7 100644 --- a/arch/arm/mach-at91/Makefile.boot +++ b/arch/arm/mach-at91/Makefile.boot @@ -16,6 +16,7 @@ endif # Keep dtb files sorted alphabetically for each SoC # sam9260 dtb-$(CONFIG_MACH_AT91SAM_DT) += ethernut5.dtb +dtb-$(CONFIG_MACH_AT91SAM_DT) += evk-pro3.dtb dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb # sam9263 -- cgit v0.10.2 From 3c68bb48214f87562b6956195178d991403d66d4 Mon Sep 17 00:00:00 2001 From: Jiri Prchal Date: Mon, 9 Jul 2012 10:05:18 +0200 Subject: ARM: at91: Add support for board aks-cdu Add support for our "aks-cdu" board based up on Telit's module GE863 Pro3. It has more uarts, leds, another nand partitioning. Signed-off-by: Jiri Prchal [nicolas.ferre@atmel.com: correction of the dts file] Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts new file mode 100644 index 0000000..29b9f15 --- /dev/null +++ b/arch/arm/boot/dts/aks-cdu.dts @@ -0,0 +1,113 @@ +/* + * aks-cdu.dts - Device Tree file for AK signal CDU + * + * Copyright (C) 2012 AK signal Brno a.s. + * 2012 Jiri Prchal + * + * Licensed under GPLv2 or later. + */ + +/dts-v1/; + +/include/ "ge863-pro3.dtsi" + +/ { + chosen { + bootargs = "console=ttyS0,115200 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs"; + }; + + ahb { + apb { + usart0: serial@fffb0000 { + status = "okay"; + }; + + usart1: serial@fffb4000 { + status = "okay"; + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <0 0>; + }; + + usart2: serial@fffb8000 { + status = "okay"; + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <0 0>; + }; + + usart3: serial@fffd0000 { + status = "okay"; + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <0 0>; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 15 0>; + status = "okay"; + }; + }; + + usb0: ohci@00500000 { + num-ports = <2>; + status = "okay"; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + bootstrap@0 { + label = "bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "uboot"; + reg = <0x40000 0x80000>; + }; + ubootenv@c0000 { + label = "ubootenv"; + reg = <0xc0000 0x40000>; + }; + kernel@100000 { + label = "kernel"; + reg = <0x100000 0x400000>; + }; + rootfs@500000 { + label = "rootfs"; + reg = <0x500000 0x7b00000>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + red { + gpios = <&pioC 10 0>; + linux,default-trigger = "none"; + }; + + green { + gpios = <&pioA 5 1>; + linux,default-trigger = "none"; + default-state = "on"; + }; + + yellow { + gpios = <&pioB 20 1>; + linux,default-trigger = "none"; + }; + + blue { + gpios = <&pioB 21 1>; + linux,default-trigger = "none"; + }; + }; +}; diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot index 11c3ca7..30bb733 100644 --- a/arch/arm/mach-at91/Makefile.boot +++ b/arch/arm/mach-at91/Makefile.boot @@ -15,6 +15,7 @@ endif # Keep dtb files sorted alphabetically for each SoC # sam9260 +dtb-$(CONFIG_MACH_AT91SAM_DT) += aks-cdu.dtb dtb-$(CONFIG_MACH_AT91SAM_DT) += ethernut5.dtb dtb-$(CONFIG_MACH_AT91SAM_DT) += evk-pro3.dtb dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb -- cgit v0.10.2 From d2a37b3d91f46da25e7ff34f582e914a4cc0bfee Mon Sep 17 00:00:00 2001 From: Denis 'GNUtoo' Carikli Date: Mon, 9 Jul 2012 21:39:12 +0200 Subject: ARM i.MX31: Add devicetree support This patch adds basic devicetree support for i.MX31 based SoCs. Only the UART and interrupts bindings are added. Signed-off-by: Denis 'GNUtoo' Carikli Signed-off-by: Sascha Hauer diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi new file mode 100644 index 0000000..eef7099 --- /dev/null +++ b/arch/arm/boot/dts/imx31.dtsi @@ -0,0 +1,88 @@ +/* + * Copyright 2012 Denis 'GNUtoo' Carikli + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + }; + + avic: avic-interrupt-controller@60000000 { + compatible = "fsl,imx31-avic", "fsl,avic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x60000000 0x100000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&avic>; + ranges; + + aips@43f00000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x43f00000 0x100000>; + ranges; + + uart1: serial@43f90000 { + compatible = "fsl,imx31-uart", "fsl,imx21-uart"; + reg = <0x43f90000 0x4000>; + interrupts = <45>; + status = "disabled"; + }; + + uart2: serial@43f94000 { + compatible = "fsl,imx31-uart", "fsl,imx21-uart"; + reg = <0x43f94000 0x4000>; + interrupts = <32>; + status = "disabled"; + }; + + uart4: serial@43fb0000 { + compatible = "fsl,imx31-uart", "fsl,imx21-uart"; + reg = <0x43fb0000 0x4000>; + interrupts = <46>; + status = "disabled"; + }; + + uart5: serial@43fb4000 { + compatible = "fsl,imx31-uart", "fsl,imx21-uart"; + reg = <0x43fb4000 0x4000>; + interrupts = <47>; + status = "disabled"; + }; + }; + + spba@50000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x100000>; + ranges; + + uart3: serial@5000c000 { + compatible = "fsl,imx31-uart", "fsl,imx21-uart"; + reg = <0x5000c000 0x4000>; + interrupts = <18>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index eff4db5..46f5c3f 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -557,6 +557,14 @@ config MACH_BUG Include support for BUGBase 1.3 platform. This includes specific configurations for the board and its peripherals. +config MACH_IMX31_DT + bool "Support i.MX31 platforms from device tree" + select SOC_IMX31 + select USE_OF + help + Include support for Freescale i.MX31 based platforms + using the device tree for discovery. + comment "MX35 platforms:" config MACH_PCM043 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index ff29421..07f7c22 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_MACH_QONG) += mach-qong.o obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o obj-$(CONFIG_MACH_BUG) += mach-bug.o +obj-$(CONFIG_MACH_IMX31_DT) += imx31-dt.o # i.MX35 based machines obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c index c9a06d8..f87a48f 100644 --- a/arch/arm/mach-imx/clk-imx31.c +++ b/arch/arm/mach-imx/clk-imx31.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -179,3 +180,21 @@ int __init mx31_clocks_init(unsigned long fref) return 0; } + +#ifdef CONFIG_OF +int __init mx31_clocks_init_dt(void) +{ + struct device_node *np; + u32 fref = 26000000; /* default */ + + for_each_compatible_node(np, NULL, "fixed-clock") { + if (!of_device_is_compatible(np, "fsl,imx-osc26m")) + continue; + + if (!of_property_read_u32(np, "clock-frequency", &fref)) + break; + } + + return mx31_clocks_init(fref); +} +#endif diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c new file mode 100644 index 0000000..a68ba20 --- /dev/null +++ b/arch/arm/mach-imx/imx31-dt.c @@ -0,0 +1,63 @@ +/* + * Copyright 2012 Sascha Hauer, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include + +static const struct of_dev_auxdata imx31_auxdata_lookup[] __initconst = { + OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART1_BASE_ADDR, + "imx21-uart.0", NULL), + OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART2_BASE_ADDR, + "imx21-uart.1", NULL), + OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART3_BASE_ADDR, + "imx21-uart.2", NULL), + OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART4_BASE_ADDR, + "imx21-uart.3", NULL), + OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART5_BASE_ADDR, + "imx21-uart.4", NULL), + { /* sentinel */ } +}; + +static void __init imx31_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + imx31_auxdata_lookup, NULL); +} + +static void __init imx31_timer_init(void) +{ + mx31_clocks_init_dt(); +} + +static struct sys_timer imx31_timer = { + .init = imx31_timer_init, +}; + +static const char *imx31_dt_board_compat[] __initdata = { + "fsl,imx31", + NULL +}; + +DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)") + .map_io = mx31_map_io, + .init_early = imx31_init_early, + .init_irq = mx31_init_irq, + .handle_irq = imx31_handle_irq, + .timer = &imx31_timer, + .init_machine = imx31_dt_init, + .dt_compat = imx31_dt_board_compat, + .restart = mxc_restart, +MACHINE_END diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index e429ca1..7cfcc44 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -67,6 +67,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); extern int mx27_clocks_init_dt(void); +extern int mx31_clocks_init_dt(void); extern int mx51_clocks_init_dt(void); extern int mx53_clocks_init_dt(void); extern int mx6q_clocks_init(void); -- cgit v0.10.2 From 0767211bea2f2062b1d5620eed6a279fa2b4330e Mon Sep 17 00:00:00 2001 From: Denis 'GNUtoo' Carikli Date: Mon, 9 Jul 2012 21:39:13 +0200 Subject: arm/dts: Add support for i.MX31 bug 1.x board from buglabs. Only the main UART and the memory node information are added. Signed-off-by: Denis 'GNUtoo' Carikli Signed-off-by: Sascha Hauer diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts new file mode 100644 index 0000000..24731cb --- /dev/null +++ b/arch/arm/boot/dts/imx31-bug.dts @@ -0,0 +1,31 @@ +/* + * Copyright 2012 Denis 'GNUtoo' Carikli + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx31.dtsi" + +/ { + model = "Buglabs i.MX31 Bug 1.x"; + compatible = "fsl,imx31-bug", "fsl,imx31"; + + memory { + reg = <0x80000000 0x8000000>; /* 128M */ + }; + + soc { + aips@43f00000 { /* AIPS1 */ + uart5: serial@43fb4000 { + fsl,uart-has-rtscts; + status = "okay"; + }; + }; + }; +}; -- cgit v0.10.2 From daefb6961cc64745c285b279d938b1854f74f870 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sat, 7 Jul 2012 20:59:09 +0800 Subject: ARM: dts: imx28: move extra gpmi-nand pins into board dts Only pins GPMI_CE0N and GPMI_READY0 are generally used by other boards. Move GPMI_CE1N and GPMI_READY1 into imx28-evk.dts to make gpmi_pins_a more general, and can be used by other boards. Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 0d8739d..0444964 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -24,7 +24,8 @@ apbh@80000000 { gpmi-nand@8000c000 { pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg + &gpmi_pins_evk>; status = "okay"; }; @@ -64,6 +65,17 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; + + gpmi_pins_evk: gpmi-nand-evk@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0110 /* MX28_PAD_GPMI_CE1N__GPMI_CE1N */ + 0x0150 /* MX28_PAD_GPMI_RDY1__GPMI_READY1 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; }; lcdif@80030000 { diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index adb5ffc..2874adc 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -198,9 +198,7 @@ 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */ 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */ 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */ - 0x0110 /* MX28_PAD_GPMI_CE1N__GPMI_CE1N */ 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */ - 0x0150 /* MX28_PAD_GPMI_RDY1__GPMI_READY1 */ 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */ -- cgit v0.10.2 From 3dba2596730709fdec65491455a66a7df1ca67db Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sat, 7 Jul 2012 21:09:51 +0800 Subject: ARM: dts: imx28: move lcdif control pins into board dts The presence and muxing of lcdif control pins can vary much on different boards. Move them into imx28-evk.dts to make lcdif_24bit_pins_a only about data pins, so that it can be reused by other boards. Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 0444964..0fcc7ea 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -76,11 +76,25 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; + + lcdif_pins_evk: lcdif-evk@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; }; lcdif@80030000 { pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a>; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_evk>; panel-enable-gpios = <&gpio3 30 0>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 2874adc..02e778b 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -400,10 +400,6 @@ 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */ 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */ 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */ - 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ - 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ - 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ - 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ >; fsl,drive-strength = <0>; fsl,voltage = <1>; -- cgit v0.10.2 From 8fa62e11283faa203b360c4ebdbd186b2c8dd844 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 7 Jul 2012 21:21:38 +0800 Subject: ARM: mxs: convert m28evk board to device tree Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 02e778b..895a072 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -232,6 +232,17 @@ fsl,pull-up = <0>; }; + auart0_2pins_a: auart0-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ + 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + auart3_pins_a: auart3@0 { reg = <0>; fsl,pinmux-ids = < diff --git a/arch/arm/boot/dts/m28evk.dts b/arch/arm/boot/dts/m28evk.dts new file mode 100644 index 0000000..183a3fd --- /dev/null +++ b/arch/arm/boot/dts/m28evk.dts @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2012 Marek Vasut + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx28.dtsi" + +/ { + model = "DENX M28EVK"; + compatible = "denx,m28evk", "fsl,imx28"; + + memory { + reg = <0x40000000 0x08000000>; + }; + + apb@80000000 { + apbh@80000000 { + gpmi-nand@8000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; + + partition@0 { + label = "bootloader"; + reg = <0x00000000 0x00300000>; + read-only; + }; + + partition@1 { + label = "environment"; + reg = <0x00300000 0x00080000>; + }; + + partition@2 { + label = "redundant-environment"; + reg = <0x00380000 0x00080000>; + }; + + partition@3 { + label = "kernel"; + reg = <0x00400000 0x00400000>; + }; + + partition@4 { + label = "filesystem"; + reg = <0x00800000 0x0f800000>; + }; + }; + + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_8bit_pins_a + &mmc0_cd_cfg + &mmc0_sck_cfg>; + bus-width = <8>; + wp-gpios = <&gpio3 10 1>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */ + 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + lcdif_pins_m28: lcdif-m28@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x11e0 /* MX28_PAD_LCD_DOTCLK__LCD_DOTCLK */ + 0x11f0 /* MX28_PAD_LCD_ENABLE__LCD_ENABLE */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + + lcdif@80030000 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_m28>; + status = "okay"; + }; + + can0: can@80032000 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + status = "okay"; + }; + + can1: can@80034000 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + status = "okay"; + }; + }; + + apbx@80040000 { + saif0: saif@80042000 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + status = "okay"; + }; + + saif1: saif@80046000 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + status = "okay"; + }; + + i2c0: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + + }; + + eeprom: eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc: rtc@68 { + compatible = "stm,mt41t62"; + reg = <0x68>; + }; + }; + + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + auart0: serial@8006a000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; + }; + + auart3: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_pins_a>; + status = "okay"; + }; + }; + }; + + ahb@80080000 { + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio3 11 0>; + status = "okay"; + }; + + mac1: ethernet@800f4000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + sound { + compatible = "denx,m28evk-sgtl5000", + "fsl,mxs-audio-sgtl5000"; + model = "m28evk-sgtl5000"; + saif-controllers = <&saif0 &saif1>; + audio-codec = <&sgtl5000>; + }; +}; diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 7bbb961..d3fc8ba 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -59,6 +59,23 @@ static struct fb_videomode mx28evk_video_modes[] = { }, }; +static struct fb_videomode m28evk_video_modes[] = { + { + .name = "Ampire AM-800480R2TMQW-T01H", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 30066, /* picosecond (33.26 MHz) */ + .left_margin = 0, + .right_margin = 256, + .upper_margin = 0, + .lower_margin = 45, + .hsync_len = 1, + .vsync_len = 1, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, + }, +}; + static struct mxsfb_platform_data mxsfb_pdata __initdata; static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = { @@ -186,15 +203,17 @@ static void __init imx23_evk_init(void) mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; } -static void __init imx28_evk_init(void) +static inline void enable_clk_enet_out(void) { - struct clk *clk; + struct clk *clk = clk_get_sys("enet_out", NULL); - /* Enable fec phy clock */ - clk = clk_get_sys("enet_out", NULL); if (!IS_ERR(clk)) clk_prepare_enable(clk); +} +static void __init imx28_evk_init(void) +{ + enable_clk_enet_out(); update_fec_mac_prop(OUI_FSL); mxsfb_pdata.mode_list = mx28evk_video_modes; @@ -203,12 +222,25 @@ static void __init imx28_evk_init(void) mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; } +static void __init m28evk_init(void) +{ + enable_clk_enet_out(); + update_fec_mac_prop(OUI_DENX); + + mxsfb_pdata.mode_list = m28evk_video_modes; + mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes); + mxsfb_pdata.default_bpp = 16; + mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT; +} + static void __init mxs_machine_init(void) { if (of_machine_is_compatible("fsl,imx28-evk")) imx28_evk_init(); else if (of_machine_is_compatible("fsl,imx23-evk")) imx23_evk_init(); + else if (of_machine_is_compatible("denx,m28evk")) + m28evk_init(); of_platform_populate(NULL, of_default_bus_match_table, mxs_auxdata_lookup, NULL); @@ -223,6 +255,7 @@ static const char *imx23_dt_compat[] __initdata = { static const char *imx28_dt_compat[] __initdata = { "crystalfontz,cfa10036", + "denx,m28evk", "fsl,imx28-evk", "fsl,imx28", NULL, -- cgit v0.10.2 From 3143bbb42b3d27a5f799c97c84fb7a4a1de88f91 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sat, 7 Jul 2012 23:12:03 +0800 Subject: ARM: mxs: convert apx4devkit board to device tree Tested-by: Lauri Hintsala Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/apx4devkit.dts b/arch/arm/boot/dts/apx4devkit.dts new file mode 100644 index 0000000..04664bc --- /dev/null +++ b/arch/arm/boot/dts/apx4devkit.dts @@ -0,0 +1,143 @@ +/dts-v1/; +/include/ "imx28.dtsi" + +/ { + model = "Bluegiga APX4 Development Kit"; + compatible = "bluegiga,apx4devkit", "fsl,imx28"; + + memory { + reg = <0x40000000 0x04000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_8bit_pins_a + &mmc0_cd_cfg + &mmc0_sck_cfg>; + bus-width = <8>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + }; + + apbx@80040000 { + saif0: saif@80042000 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + status = "okay"; + }; + + saif1: saif@80046000 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + status = "okay"; + }; + + i2c0: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + + }; + + pcf8563: rtc@51 { + compatible = "phg,pcf8563"; + reg = <0x51>; + }; + }; + + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + auart0: serial@8006a000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; + }; + + auart1: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_2pins_a>; + status = "okay"; + }; + + auart2: serial@8006e000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart2_2pins_a>; + status = "okay"; + }; + + auart3: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_2pins_a>; + status = "okay"; + }; + }; + }; + + ahb@80080000 { + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + sound { + compatible = "bluegiga,apx4devkit-sgtl5000", + "fsl,mxs-audio-sgtl5000"; + model = "apx4devkit-sgtl5000"; + saif-controllers = <&saif0 &saif1>; + audio-codec = <&sgtl5000>; + }; + + leds { + compatible = "gpio-leds"; + + user { + label = "Heartbeat"; + gpios = <&gpio3 28 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 895a072..8595977 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -243,6 +243,28 @@ fsl,pull-up = <0>; }; + auart1_2pins_a: auart1-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ + 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + auart2_2pins_a: auart2-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */ + 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + auart3_pins_a: auart3@0 { reg = <0>; fsl,pinmux-ids = < @@ -256,6 +278,17 @@ fsl,pull-up = <0>; }; + auart3_2pins_a: auart3-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */ + 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + mac0_pins_a: mac0@0 { reg = <0>; fsl,pinmux-ids = < diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index d3fc8ba..d0bf414 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -16,9 +16,11 @@ #include #include #include +#include #include #include #include +#include #include #include #include @@ -233,6 +235,21 @@ static void __init m28evk_init(void) mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT; } +static int apx4devkit_phy_fixup(struct phy_device *phy) +{ + phy->dev_flags |= MICREL_PHY_50MHZ_CLK; + return 0; +} + +static void __init apx4devkit_init(void) +{ + enable_clk_enet_out(); + + if (IS_BUILTIN(CONFIG_PHYLIB)) + phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK, + apx4devkit_phy_fixup); +} + static void __init mxs_machine_init(void) { if (of_machine_is_compatible("fsl,imx28-evk")) @@ -241,6 +258,8 @@ static void __init mxs_machine_init(void) imx23_evk_init(); else if (of_machine_is_compatible("denx,m28evk")) m28evk_init(); + else if (of_machine_is_compatible("bluegiga,apx4devkit")) + apx4devkit_init(); of_platform_populate(NULL, of_default_bus_match_table, mxs_auxdata_lookup, NULL); @@ -254,6 +273,7 @@ static const char *imx23_dt_compat[] __initdata = { }; static const char *imx28_dt_compat[] __initdata = { + "bluegiga,apx4devkit", "crystalfontz,cfa10036", "denx,m28evk", "fsl,imx28-evk", -- cgit v0.10.2 From e1a4d18f6c74cf3df59c73f526ede607196f2257 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 9 Jul 2012 12:34:35 +0800 Subject: ARM: mxs: convert tx28 board to device tree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit FEC support is missing because we need to find a proper way to rewrite tx28_add_fec0 for device tree boot. Cc: Lothar Waßmann Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 8595977..e906ec1 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -186,6 +186,19 @@ fsl,pull-up = <0>; }; + duart_4pins_a: duart-4pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ + 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ + 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */ + 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + gpmi_pins_a: gpmi-nand@0 { reg = <0>; fsl,pinmux-ids = < @@ -243,6 +256,19 @@ fsl,pull-up = <0>; }; + auart1_pins_a: auart1@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ + 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ + 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */ + 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + auart1_2pins_a: auart1-2pins@0 { reg = <0>; fsl,pinmux-ids = < @@ -407,6 +433,16 @@ fsl,pull-up = <1>; }; + pwm0_pins_a: pwm0@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3100 /* MX28_PAD_PWM0__PWM_0 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + pwm2_pins_a: pwm2@0 { reg = <0>; fsl,pinmux-ids = < diff --git a/arch/arm/boot/dts/tx28.dts b/arch/arm/boot/dts/tx28.dts new file mode 100644 index 0000000..62bf767 --- /dev/null +++ b/arch/arm/boot/dts/tx28.dts @@ -0,0 +1,97 @@ +/dts-v1/; +/include/ "imx28.dtsi" + +/ { + model = "Ka-Ro electronics TX28 module"; + compatible = "karo,tx28", "fsl,imx28"; + + memory { + reg = <0x40000000 0x08000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg + &mmc0_sck_cfg>; + bus-width = <4>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + }; + + apbx@80040000 { + i2c0: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + ds1339: rtc@68 { + compatible = "mxim,ds1339"; + reg = <0x68>; + }; + }; + + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>; + status = "okay"; + }; + + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_4pins_a>; + status = "okay"; + }; + + auart1: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_pins_a>; + status = "okay"; + }; + }; + }; + + ahb@80080000 { + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + + user { + label = "Heartbeat"; + gpios = <&gpio4 10 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; +}; diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index d0bf414..a04bec8 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -277,6 +277,7 @@ static const char *imx28_dt_compat[] __initdata = { "crystalfontz,cfa10036", "denx,m28evk", "fsl,imx28-evk", + "karo,tx28", "fsl,imx28", NULL, }; -- cgit v0.10.2 From dd852aa5215b9a976b8949378e8f3b6fcb8c5291 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 9 Jul 2012 13:33:02 +0800 Subject: ARM: mxs: convert stmp378x_devb board to device tree The enc28j60 spi device does not get converted to dts file, because there is no mxs spi driver on mainline so far. The enc28j60 spi in mach-stmp378x_devb.c does not work anyway. Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/stmp378x_devb.dts b/arch/arm/boot/dts/stmp378x_devb.dts new file mode 100644 index 0000000..757a327 --- /dev/null +++ b/arch/arm/boot/dts/stmp378x_devb.dts @@ -0,0 +1,78 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx23.dtsi" + +/ { + model = "Freescale STMP378x Development Board"; + compatible = "fsl,stmp378x-devb", "fsl,imx23"; + + memory { + reg = <0x40000000 0x04000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; + bus-width = <4>; + wp-gpios = <&gpio1 30 0>; + vmmc-supply = <®_vddio_sd0>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ + 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + }; + + apbx@80040000 { + auart0: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; + }; + + duart: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_vddio_sd0: vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 29 0>; + }; + }; +}; diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index a04bec8..bd8db7b 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -267,6 +267,7 @@ static void __init mxs_machine_init(void) static const char *imx23_dt_compat[] __initdata = { "fsl,imx23-evk", + "fsl,stmp378x_devb" "olimex,imx23-olinuxino", "fsl,imx23", NULL, -- cgit v0.10.2 From 841730e74393a9f6b10fb22cb1d5047de6246119 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 9 Jul 2012 13:45:01 +0800 Subject: ARM: mxs: add dtb-y target into Makefile.boot Add dtb-y target into Makefile.boot, so that "make ARCH=arm dtbs" can build out all the dtbs listed there. It's very useful for build-testing all the .dts when imx28.dtsi changes. Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot index 07b11fe..58733cc 100644 --- a/arch/arm/mach-mxs/Makefile.boot +++ b/arch/arm/mach-mxs/Makefile.boot @@ -1 +1,10 @@ zreladdr-y += 0x40008000 + +dtb-y += apx4devkit.dtb \ + cfa10036.dtb \ + imx23-evk.dtb \ + imx23-olinuxino.dtb \ + imx28-evk.dtb \ + m28evk.dtb \ + stmp378x_devb.dtb \ + tx28.dtb \ -- cgit v0.10.2 From 3317d99e444988e71a32edbca092b1aed098c2f1 Mon Sep 17 00:00:00 2001 From: Lauri Hintsala Date: Tue, 10 Jul 2012 10:08:07 +0300 Subject: ARM: apx4devkit: add NAND support Signed-off-by: Lauri Hintsala Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/apx4devkit.dts b/arch/arm/boot/dts/apx4devkit.dts index 04664bc..51ed36a 100644 --- a/arch/arm/boot/dts/apx4devkit.dts +++ b/arch/arm/boot/dts/apx4devkit.dts @@ -11,6 +11,12 @@ apb@80000000 { apbh@80000000 { + gpmi-nand@8000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; + }; + ssp0: ssp@80010000 { compatible = "fsl,imx28-mmc"; pinctrl-names = "default"; -- cgit v0.10.2 From d8bb823d31a1405e42aa4a2162d3c00e657b6516 Mon Sep 17 00:00:00 2001 From: Lauri Hintsala Date: Tue, 10 Jul 2012 10:08:08 +0300 Subject: ARM: apx4devkit: add display support Add HannStar display and device tree configuration. Signed-off-by: Lauri Hintsala Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/apx4devkit.dts b/arch/arm/boot/dts/apx4devkit.dts index 51ed36a..03de5b8 100644 --- a/arch/arm/boot/dts/apx4devkit.dts +++ b/arch/arm/boot/dts/apx4devkit.dts @@ -35,11 +35,32 @@ reg = <0>; fsl,pinmux-ids = < 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ + 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ >; fsl,drive-strength = <0>; fsl,voltage = <1>; fsl,pull-up = <0>; }; + + lcdif_pins_apx4: lcdif-apx4@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + + lcdif@80030000 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_apx4>; + status = "okay"; }; }; diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index bd8db7b..648bdd0 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -78,6 +78,25 @@ static struct fb_videomode m28evk_video_modes[] = { }, }; +static struct fb_videomode apx4devkit_video_modes[] = { + { + .name = "HannStar PJ70112A", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 33333, /* picosecond (30.00 MHz) */ + .left_margin = 88, + .right_margin = 40, + .upper_margin = 32, + .lower_margin = 13, + .hsync_len = 48, + .vsync_len = 3, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | + FB_SYNC_DATA_ENABLE_HIGH_ACT | + FB_SYNC_DOTCLK_FAILING_ACT, + }, +}; + static struct mxsfb_platform_data mxsfb_pdata __initdata; static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = { @@ -248,6 +267,11 @@ static void __init apx4devkit_init(void) if (IS_BUILTIN(CONFIG_PHYLIB)) phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK, apx4devkit_phy_fixup); + + mxsfb_pdata.mode_list = apx4devkit_video_modes; + mxsfb_pdata.mode_count = ARRAY_SIZE(apx4devkit_video_modes); + mxsfb_pdata.default_bpp = 32; + mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; } static void __init mxs_machine_init(void) -- cgit v0.10.2 From 1eb73ca0b5b0b26a829471c5e8bb8ccf9a05a7bd Mon Sep 17 00:00:00 2001 From: Lauri Hintsala Date: Tue, 10 Jul 2012 10:08:09 +0300 Subject: ARM: apx4devkit: fix the bus-width of SSP0 to 4 bits Signed-off-by: Lauri Hintsala Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/apx4devkit.dts b/arch/arm/boot/dts/apx4devkit.dts index 03de5b8..35b7513 100644 --- a/arch/arm/boot/dts/apx4devkit.dts +++ b/arch/arm/boot/dts/apx4devkit.dts @@ -20,10 +20,8 @@ ssp0: ssp@80010000 { compatible = "fsl,imx28-mmc"; pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg - &mmc0_sck_cfg>; - bus-width = <8>; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; + bus-width = <4>; status = "okay"; }; -- cgit v0.10.2 From 557763b31cf1019a6f26fe86a586609d9ada3d96 Mon Sep 17 00:00:00 2001 From: Lauri Hintsala Date: Tue, 10 Jul 2012 10:08:10 +0300 Subject: ARM: apx4devkit: add SSP2 support Signed-off-by: Lauri Hintsala Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/apx4devkit.dts b/arch/arm/boot/dts/apx4devkit.dts index 35b7513..d3fed0b 100644 --- a/arch/arm/boot/dts/apx4devkit.dts +++ b/arch/arm/boot/dts/apx4devkit.dts @@ -25,6 +25,14 @@ status = "okay"; }; + ssp2: ssp@80014000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>; + bus-width = <4>; + status = "okay"; + }; + pinctrl@80018000 { pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; @@ -52,6 +60,29 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; + + mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2041 /* MX28_PAD_SSP0_DATA4__SSP2_D0 */ + 0x2051 /* MX28_PAD_SSP0_DATA5__SSP2_D3 */ + 0x2061 /* MX28_PAD_SSP0_DATA6__SSP2_CMD */ + 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */ + 0x2141 /* MX28_PAD_SSP2_SS1__SSP2_D1 */ + 0x2151 /* MX28_PAD_SSP2_SS2__SSP2_D2 */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 { + fsl,pinmux-ids = < + 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */ + >; + fsl,drive-strength = <2>; + fsl,pull-up = <0>; + }; }; lcdif@80030000 { -- cgit v0.10.2 From 78771f05c8211782f4af162cd1ef10de114f8786 Mon Sep 17 00:00:00 2001 From: Lauri Hintsala Date: Tue, 10 Jul 2012 10:08:11 +0300 Subject: ARM: apx4devkit: remove AUART3 AUART3 is not available anymore. Pins are used as GPIOs. Signed-off-by: Lauri Hintsala Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/apx4devkit.dts b/arch/arm/boot/dts/apx4devkit.dts index d3fed0b..ee988b7 100644 --- a/arch/arm/boot/dts/apx4devkit.dts +++ b/arch/arm/boot/dts/apx4devkit.dts @@ -149,12 +149,6 @@ pinctrl-0 = <&auart2_2pins_a>; status = "okay"; }; - - auart3: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart3_2pins_a>; - status = "okay"; - }; }; }; -- cgit v0.10.2 From 1ad0ceacb4cdb2d5eac320bea166ff728fadadeb Mon Sep 17 00:00:00 2001 From: Lauri Hintsala Date: Tue, 10 Jul 2012 10:08:12 +0300 Subject: ARM: apx4devkit: add pin muxing for GPIOs Some pins are used as GPIOs in user space. Signed-off-by: Lauri Hintsala Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/apx4devkit.dts b/arch/arm/boot/dts/apx4devkit.dts index ee988b7..b383417 100644 --- a/arch/arm/boot/dts/apx4devkit.dts +++ b/arch/arm/boot/dts/apx4devkit.dts @@ -40,8 +40,13 @@ hog_pins_a: hog-gpios@0 { reg = <0>; fsl,pinmux-ids = < + 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ + 0x0153 /* MX28_PAD_GPMI_RDY1__GPIO_0_21 */ + 0x2123 /* MX28_PAD_SSP2_MISO__GPIO_2_18 */ + 0x2131 /* MX28_PAD_SSP2_SS0__GPIO_2_19 */ 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ + 0x4143 /* MX28_PAD_JTAG_RTCK__GPIO_4_20 */ >; fsl,drive-strength = <0>; fsl,voltage = <1>; -- cgit v0.10.2 From ce9b9febe1cf3e01a7dcb0d3772734addb96606c Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 11 Jul 2012 12:25:22 +0800 Subject: ARM: mxs: rename dts files with soc name being the prefix Rename mxs dts files with soc name being the prefix, so that the board dts file can be located easily by soc name, and we also gain the consistency of naming. Suggested-by: Marek Vasut Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/apx4devkit.dts b/arch/arm/boot/dts/apx4devkit.dts deleted file mode 100644 index b383417..0000000 --- a/arch/arm/boot/dts/apx4devkit.dts +++ /dev/null @@ -1,198 +0,0 @@ -/dts-v1/; -/include/ "imx28.dtsi" - -/ { - model = "Bluegiga APX4 Development Kit"; - compatible = "bluegiga,apx4devkit", "fsl,imx28"; - - memory { - reg = <0x40000000 0x04000000>; - }; - - apb@80000000 { - apbh@80000000 { - gpmi-nand@8000c000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; - }; - - ssp0: ssp@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; - bus-width = <4>; - status = "okay"; - }; - - ssp2: ssp@80014000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>; - bus-width = <4>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog-gpios@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ - 0x0153 /* MX28_PAD_GPMI_RDY1__GPIO_0_21 */ - 0x2123 /* MX28_PAD_SSP2_MISO__GPIO_2_18 */ - 0x2131 /* MX28_PAD_SSP2_SS0__GPIO_2_19 */ - 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ - 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ - 0x4143 /* MX28_PAD_JTAG_RTCK__GPIO_4_20 */ - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - - lcdif_pins_apx4: lcdif-apx4@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ - 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ - 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ - 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - - mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x2041 /* MX28_PAD_SSP0_DATA4__SSP2_D0 */ - 0x2051 /* MX28_PAD_SSP0_DATA5__SSP2_D3 */ - 0x2061 /* MX28_PAD_SSP0_DATA6__SSP2_CMD */ - 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */ - 0x2141 /* MX28_PAD_SSP2_SS1__SSP2_D1 */ - 0x2151 /* MX28_PAD_SSP2_SS2__SSP2_D2 */ - >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; - }; - - mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 { - fsl,pinmux-ids = < - 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */ - >; - fsl,drive-strength = <2>; - fsl,pull-up = <0>; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_apx4>; - status = "okay"; - }; - }; - - apbx@80040000 { - saif0: saif@80042000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; - }; - - saif1: saif@80046000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - - }; - - pcf8563: rtc@51 { - compatible = "phg,pcf8563"; - reg = <0x51>; - }; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; - }; - - auart1: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_2pins_a>; - status = "okay"; - }; - - auart2: serial@8006e000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart2_2pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - sound { - compatible = "bluegiga,apx4devkit-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "apx4devkit-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; - - leds { - compatible = "gpio-leds"; - - user { - label = "Heartbeat"; - gpios = <&gpio3 28 0>; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/arch/arm/boot/dts/cfa10036.dts b/arch/arm/boot/dts/cfa10036.dts deleted file mode 100644 index c03a577..0000000 --- a/arch/arm/boot/dts/cfa10036.dts +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright 2012 Free Electrons - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "imx28.dtsi" - -/ { - model = "Crystalfontz CFA-10036 Board"; - compatible = "crystalfontz,cfa10036", "fsl,imx28"; - - memory { - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: ssp@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <4>; - status = "okay"; - }; - }; - - apbx@80040000 { - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_b>; - status = "okay"; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - power { - gpios = <&gpio3 4 1>; - default-state = "on"; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts new file mode 100644 index 0000000..757a327 --- /dev/null +++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts @@ -0,0 +1,78 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx23.dtsi" + +/ { + model = "Freescale STMP378x Development Board"; + compatible = "fsl,stmp378x-devb", "fsl,imx23"; + + memory { + reg = <0x40000000 0x04000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; + bus-width = <4>; + wp-gpios = <&gpio1 30 0>; + vmmc-supply = <®_vddio_sd0>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ + 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + }; + + apbx@80040000 { + auart0: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; + }; + + duart: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_vddio_sd0: vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 29 0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts new file mode 100644 index 0000000..b383417 --- /dev/null +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -0,0 +1,198 @@ +/dts-v1/; +/include/ "imx28.dtsi" + +/ { + model = "Bluegiga APX4 Development Kit"; + compatible = "bluegiga,apx4devkit", "fsl,imx28"; + + memory { + reg = <0x40000000 0x04000000>; + }; + + apb@80000000 { + apbh@80000000 { + gpmi-nand@8000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; + }; + + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; + bus-width = <4>; + status = "okay"; + }; + + ssp2: ssp@80014000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>; + bus-width = <4>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ + 0x0153 /* MX28_PAD_GPMI_RDY1__GPIO_0_21 */ + 0x2123 /* MX28_PAD_SSP2_MISO__GPIO_2_18 */ + 0x2131 /* MX28_PAD_SSP2_SS0__GPIO_2_19 */ + 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ + 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ + 0x4143 /* MX28_PAD_JTAG_RTCK__GPIO_4_20 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + lcdif_pins_apx4: lcdif-apx4@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2041 /* MX28_PAD_SSP0_DATA4__SSP2_D0 */ + 0x2051 /* MX28_PAD_SSP0_DATA5__SSP2_D3 */ + 0x2061 /* MX28_PAD_SSP0_DATA6__SSP2_CMD */ + 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */ + 0x2141 /* MX28_PAD_SSP2_SS1__SSP2_D1 */ + 0x2151 /* MX28_PAD_SSP2_SS2__SSP2_D2 */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 { + fsl,pinmux-ids = < + 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */ + >; + fsl,drive-strength = <2>; + fsl,pull-up = <0>; + }; + }; + + lcdif@80030000 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_apx4>; + status = "okay"; + }; + }; + + apbx@80040000 { + saif0: saif@80042000 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + status = "okay"; + }; + + saif1: saif@80046000 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + status = "okay"; + }; + + i2c0: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + + }; + + pcf8563: rtc@51 { + compatible = "phg,pcf8563"; + reg = <0x51>; + }; + }; + + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + auart0: serial@8006a000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; + }; + + auart1: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_2pins_a>; + status = "okay"; + }; + + auart2: serial@8006e000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart2_2pins_a>; + status = "okay"; + }; + }; + }; + + ahb@80080000 { + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + sound { + compatible = "bluegiga,apx4devkit-sgtl5000", + "fsl,mxs-audio-sgtl5000"; + model = "apx4devkit-sgtl5000"; + saif-controllers = <&saif0 &saif1>; + audio-codec = <&sgtl5000>; + }; + + leds { + compatible = "gpio-leds"; + + user { + label = "Heartbeat"; + gpios = <&gpio3 28 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts new file mode 100644 index 0000000..c03a577 --- /dev/null +++ b/arch/arm/boot/dts/imx28-cfa10036.dts @@ -0,0 +1,52 @@ +/* + * Copyright 2012 Free Electrons + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx28.dtsi" + +/ { + model = "Crystalfontz CFA-10036 Board"; + compatible = "crystalfontz,cfa10036", "fsl,imx28"; + + memory { + reg = <0x40000000 0x08000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg &mmc0_sck_cfg>; + bus-width = <4>; + status = "okay"; + }; + }; + + apbx@80040000 { + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_b>; + status = "okay"; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + power { + gpios = <&gpio3 4 1>; + default-state = "on"; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts new file mode 100644 index 0000000..183a3fd --- /dev/null +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2012 Marek Vasut + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx28.dtsi" + +/ { + model = "DENX M28EVK"; + compatible = "denx,m28evk", "fsl,imx28"; + + memory { + reg = <0x40000000 0x08000000>; + }; + + apb@80000000 { + apbh@80000000 { + gpmi-nand@8000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; + + partition@0 { + label = "bootloader"; + reg = <0x00000000 0x00300000>; + read-only; + }; + + partition@1 { + label = "environment"; + reg = <0x00300000 0x00080000>; + }; + + partition@2 { + label = "redundant-environment"; + reg = <0x00380000 0x00080000>; + }; + + partition@3 { + label = "kernel"; + reg = <0x00400000 0x00400000>; + }; + + partition@4 { + label = "filesystem"; + reg = <0x00800000 0x0f800000>; + }; + }; + + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_8bit_pins_a + &mmc0_cd_cfg + &mmc0_sck_cfg>; + bus-width = <8>; + wp-gpios = <&gpio3 10 1>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */ + 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + lcdif_pins_m28: lcdif-m28@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x11e0 /* MX28_PAD_LCD_DOTCLK__LCD_DOTCLK */ + 0x11f0 /* MX28_PAD_LCD_ENABLE__LCD_ENABLE */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + + lcdif@80030000 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_m28>; + status = "okay"; + }; + + can0: can@80032000 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + status = "okay"; + }; + + can1: can@80034000 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + status = "okay"; + }; + }; + + apbx@80040000 { + saif0: saif@80042000 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + status = "okay"; + }; + + saif1: saif@80046000 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + status = "okay"; + }; + + i2c0: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + + }; + + eeprom: eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc: rtc@68 { + compatible = "stm,mt41t62"; + reg = <0x68>; + }; + }; + + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + auart0: serial@8006a000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; + }; + + auart3: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_pins_a>; + status = "okay"; + }; + }; + }; + + ahb@80080000 { + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio3 11 0>; + status = "okay"; + }; + + mac1: ethernet@800f4000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + sound { + compatible = "denx,m28evk-sgtl5000", + "fsl,mxs-audio-sgtl5000"; + model = "m28evk-sgtl5000"; + saif-controllers = <&saif0 &saif1>; + audio-codec = <&sgtl5000>; + }; +}; diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts new file mode 100644 index 0000000..62bf767 --- /dev/null +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -0,0 +1,97 @@ +/dts-v1/; +/include/ "imx28.dtsi" + +/ { + model = "Ka-Ro electronics TX28 module"; + compatible = "karo,tx28", "fsl,imx28"; + + memory { + reg = <0x40000000 0x08000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg + &mmc0_sck_cfg>; + bus-width = <4>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + }; + + apbx@80040000 { + i2c0: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + ds1339: rtc@68 { + compatible = "mxim,ds1339"; + reg = <0x68>; + }; + }; + + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>; + status = "okay"; + }; + + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_4pins_a>; + status = "okay"; + }; + + auart1: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_pins_a>; + status = "okay"; + }; + }; + }; + + ahb@80080000 { + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + + user { + label = "Heartbeat"; + gpios = <&gpio4 10 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; +}; diff --git a/arch/arm/boot/dts/m28evk.dts b/arch/arm/boot/dts/m28evk.dts deleted file mode 100644 index 183a3fd..0000000 --- a/arch/arm/boot/dts/m28evk.dts +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Copyright (C) 2012 Marek Vasut - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "imx28.dtsi" - -/ { - model = "DENX M28EVK"; - compatible = "denx,m28evk", "fsl,imx28"; - - memory { - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - gpmi-nand@8000c000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; - - partition@0 { - label = "bootloader"; - reg = <0x00000000 0x00300000>; - read-only; - }; - - partition@1 { - label = "environment"; - reg = <0x00300000 0x00080000>; - }; - - partition@2 { - label = "redundant-environment"; - reg = <0x00380000 0x00080000>; - }; - - partition@3 { - label = "kernel"; - reg = <0x00400000 0x00400000>; - }; - - partition@4 { - label = "filesystem"; - reg = <0x00800000 0x0f800000>; - }; - }; - - ssp0: ssp@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg - &mmc0_sck_cfg>; - bus-width = <8>; - wp-gpios = <&gpio3 10 1>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog-gpios@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */ - 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */ - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - - lcdif_pins_m28: lcdif-m28@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x11e0 /* MX28_PAD_LCD_DOTCLK__LCD_DOTCLK */ - 0x11f0 /* MX28_PAD_LCD_ENABLE__LCD_ENABLE */ - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_m28>; - status = "okay"; - }; - - can0: can@80032000 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - status = "okay"; - }; - - can1: can@80034000 { - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins_a>; - status = "okay"; - }; - }; - - apbx@80040000 { - saif0: saif@80042000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; - }; - - saif1: saif@80046000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - - }; - - eeprom: eeprom@51 { - compatible = "atmel,24c128"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc: rtc@68 { - compatible = "stm,mt41t62"; - reg = <0x68>; - }; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; - }; - - auart3: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart3_pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio3 11 0>; - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - sound { - compatible = "denx,m28evk-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "m28evk-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; -}; diff --git a/arch/arm/boot/dts/stmp378x_devb.dts b/arch/arm/boot/dts/stmp378x_devb.dts deleted file mode 100644 index 757a327..0000000 --- a/arch/arm/boot/dts/stmp378x_devb.dts +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "imx23.dtsi" - -/ { - model = "Freescale STMP378x Development Board"; - compatible = "fsl,stmp378x-devb", "fsl,imx23"; - - memory { - reg = <0x40000000 0x04000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: ssp@80010000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; - bus-width = <4>; - wp-gpios = <&gpio1 30 0>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog-gpios@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ - 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - }; - }; - - apbx@80040000 { - auart0: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; - }; - - duart: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - - reg_vddio_sd0: vddio-sd0 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 29 0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tx28.dts b/arch/arm/boot/dts/tx28.dts deleted file mode 100644 index 62bf767..0000000 --- a/arch/arm/boot/dts/tx28.dts +++ /dev/null @@ -1,97 +0,0 @@ -/dts-v1/; -/include/ "imx28.dtsi" - -/ { - model = "Ka-Ro electronics TX28 module"; - compatible = "karo,tx28", "fsl,imx28"; - - memory { - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: ssp@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg - &mmc0_sck_cfg>; - bus-width = <4>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog-gpios@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */ - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - }; - }; - - apbx@80040000 { - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - ds1339: rtc@68 { - compatible = "mxim,ds1339"; - reg = <0x68>; - }; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; - status = "okay"; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_4pins_a>; - status = "okay"; - }; - - auart1: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - - user { - label = "Heartbeat"; - gpios = <&gpio4 10 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; -}; diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot index 58733cc..4582999 100644 --- a/arch/arm/mach-mxs/Makefile.boot +++ b/arch/arm/mach-mxs/Makefile.boot @@ -1,10 +1,10 @@ zreladdr-y += 0x40008000 -dtb-y += apx4devkit.dtb \ - cfa10036.dtb \ - imx23-evk.dtb \ +dtb-y += imx23-evk.dtb \ imx23-olinuxino.dtb \ + imx23-stmp378x_devb.dtb \ + imx28-apx4devkit.dtb \ + imx28-cfa10036.dtb \ imx28-evk.dtb \ - m28evk.dtb \ - stmp378x_devb.dtb \ - tx28.dtb \ + imx28-m28evk.dtb \ + imx28-tx28.dtb \ -- cgit v0.10.2 From 5da0127093efb47c61e48d0af3d6ef0762aac00b Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 12 Jul 2012 10:25:27 +0800 Subject: ARM: dts: imx28-evk: add usb devices - add usb phy devices - add usb controller devices - add usb vbus regulators Signed-off-by: Richard Zhao Tested-by: Subodh Nijsure Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 0fcc7ea..773c0e8 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -60,6 +60,8 @@ 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ + 0x3083 /* MX28_PAD_AUART2_RX__GPIO_3_8 */ + 0x3093 /* MX28_PAD_AUART2_TX__GPIO_3_9 */ >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -163,10 +165,28 @@ pinctrl-0 = <&auart3_pins_a>; status = "okay"; }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + + usbphy1: usbphy@8007e000 { + status = "okay"; + }; }; }; ahb@80080000 { + usb0: usb@80080000 { + vbus-supply = <®_usb0_vbus>; + status = "okay"; + }; + + usb1: usb@80090000 { + vbus-supply = <®_usb1_vbus>; + status = "okay"; + }; + mac0: ethernet@800f0000 { phy-mode = "rmii"; pinctrl-names = "default"; @@ -211,6 +231,24 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio2 15 0>; }; + + reg_usb0_vbus: usb0_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 9 0>; + enable-active-high; + }; + + reg_usb1_vbus: usb1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 8 0>; + enable-active-high; + }; }; sound { diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index e906ec1..915db89 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -728,11 +728,13 @@ }; usbphy0: usbphy@8007c000 { + compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; reg = <0x8007c000 0x2000>; status = "disabled"; }; usbphy1: usbphy@8007e000 { + compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; reg = <0x8007e000 0x2000>; status = "disabled"; }; @@ -746,13 +748,19 @@ reg = <0x80080000 0x80000>; ranges; - usbctrl0: usbctrl@80080000 { + usb0: usb@80080000 { + compatible = "fsl,imx28-usb", "fsl,imx27-usb"; reg = <0x80080000 0x10000>; + interrupts = <93>; + fsl,usbphy = <&usbphy0>; status = "disabled"; }; - usbctrl1: usbctrl@80090000 { + usb1: usb@80090000 { + compatible = "fsl,imx28-usb", "fsl,imx27-usb"; reg = <0x80090000 0x10000>; + interrupts = <92>; + fsl,usbphy = <&usbphy1>; status = "disabled"; }; -- cgit v0.10.2 From 71f5aba866570b0e8407b321d449ebd8baefcdd5 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 12 Jul 2012 10:25:22 +0800 Subject: ARM: imx6q: add usb controller clock lookups Signed-off-by: Richard Zhao Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 0bb8555..d924ea7 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -401,6 +401,10 @@ int __init mx6q_clocks_init(void) clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand"); clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand"); clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand"); + clk_register_clkdev(clk[usboh3], NULL, "2184000.usb"); + clk_register_clkdev(clk[usboh3], NULL, "2184200.usb"); + clk_register_clkdev(clk[usboh3], NULL, "2184400.usb"); + clk_register_clkdev(clk[usboh3], NULL, "2184600.usb"); clk_register_clkdev(clk[uart_serial], "per", "2020000.serial"); clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial"); clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial"); -- cgit v0.10.2 From 7571d283c8cb11af7f3b28260e074217ded6c093 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 12 Jul 2012 10:25:23 +0800 Subject: ARM: imx6q: add usbphy clocks Signed-off-by: Richard Zhao Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index d924ea7..d5e88c0 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -152,7 +152,7 @@ enum mx6q_clks { ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg, - ssi2_ipg, ssi3_ipg, rom, + ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, clk_max }; @@ -198,6 +198,9 @@ int __init mx6q_clocks_init(void) clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x2000, 0x3); clk[pll8_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll8_enet", "osc", base + 0xe0, 0x182000, 0x3); + clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6); + clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6); + /* name parent_name reg idx */ clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); @@ -405,6 +408,8 @@ int __init mx6q_clocks_init(void) clk_register_clkdev(clk[usboh3], NULL, "2184200.usb"); clk_register_clkdev(clk[usboh3], NULL, "2184400.usb"); clk_register_clkdev(clk[usboh3], NULL, "2184600.usb"); + clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy"); + clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy"); clk_register_clkdev(clk[uart_serial], "per", "2020000.serial"); clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial"); clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial"); -- cgit v0.10.2 From 396bf1c24e13f45686118acd550dd63b23035b23 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 12 Jul 2012 10:25:24 +0800 Subject: ARM: imx6q: disable usb charger detector The external charger detector needs to be disabled, or the signal at DP will be poor Signed-off-by: Richard Zhao Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index b47e98b..140f550 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -113,6 +114,45 @@ static void __init imx6q_sabrelite_init(void) imx6q_sabrelite_cko1_setup(); } +static void __init imx6q_usb_init(void) +{ + struct device_node *np; + struct platform_device *pdev = NULL; + struct anatop *adata = NULL; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); + if (np) + pdev = of_find_device_by_node(np); + if (pdev) + adata = platform_get_drvdata(pdev); + if (!adata) { + if (np) + of_node_put(np); + return; + } + +#define HW_ANADIG_USB1_CHRG_DETECT 0x000001b0 +#define HW_ANADIG_USB2_CHRG_DETECT 0x00000210 + +#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x00100000 +#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x00080000 + + /* + * The external charger detector needs to be disabled, + * or the signal at DP will be poor + */ + anatop_write_reg(adata, HW_ANADIG_USB1_CHRG_DETECT, + BM_ANADIG_USB_CHRG_DETECT_EN_B + | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B, + ~0); + anatop_write_reg(adata, HW_ANADIG_USB2_CHRG_DETECT, + BM_ANADIG_USB_CHRG_DETECT_EN_B | + BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B, + ~0); + + of_node_put(np); +} + static void __init imx6q_init_machine(void) { /* @@ -127,6 +167,7 @@ static void __init imx6q_init_machine(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); imx6q_pm_init(); + imx6q_usb_init(); } static void __init imx6q_map_io(void) -- cgit v0.10.2 From 74bd88f78f5ac7f30e0ff75e41b0daeec8d4d3bc Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 12 Jul 2012 14:21:41 +0800 Subject: ARM: dts: imx6q-sabrelite: add usb devices - add usbphy devices - add usb host controller and otg devices - add usb h1 vbus regulator Signed-off-by: Richard Zhao Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index e0ec929..46fdfd1 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -42,9 +42,30 @@ }; }; + iomuxc@020e0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_hog>; + + gpios { + pinctrl_gpio_hog: gpiohog { + fsl,pins = < + 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ + >; + }; + }; + }; }; aips-bus@02100000 { /* AIPS2 */ + usb@02184000 { /* USB OTG */ + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; + }; + + usb@02184200 { /* USB1 */ + status = "okay"; + }; + ethernet@02188000 { phy-mode = "rgmii"; phy-reset-gpios = <&gpio3 23 0>; @@ -111,6 +132,15 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + reg_usb_otg_vbus: usb_otg_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; }; sound { diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index bf88fb7..693f31f 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -461,12 +461,14 @@ }; }; - usbphy@020c9000 { /* USBPHY1 */ + usbphy1: usbphy@020c9000 { + compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <0 44 0x04>; }; - usbphy@020ca000 { /* USBPHY2 */ + usbphy2: usbphy@020ca000 { + compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = <0 45 0x04>; }; @@ -614,6 +616,36 @@ reg = <0x0217c000 0x4000>; }; + usb@02184000 { /* USB OTG */ + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = <0 43 0x04>; + fsl,usbphy = <&usbphy1>; + status = "disabled"; + }; + + usb@02184200 { /* USB1 */ + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = <0 40 0x04>; + fsl,usbphy = <&usbphy2>; + status = "disabled"; + }; + + usb@02184400 { /* USB2 */ + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184400 0x200>; + interrupts = <0 41 0x04>; + status = "disabled"; + }; + + usb@02184600 { /* USB3 */ + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184600 0x200>; + interrupts = <0 42 0x04>; + status = "disabled"; + }; + ethernet@02188000 { compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; -- cgit v0.10.2 From 8ad7a3058791d92de98cfb57eb799d37e9d30413 Mon Sep 17 00:00:00 2001 From: Hui Wang Date: Wed, 20 Jun 2012 14:41:50 +0800 Subject: ARM: dts: imx6q-sabrelite: add ecspi1 pinctrl support Imx6q sabrelite board uses ecspi1 to connect a spi flash sst25vf016b, we need to add pinctrl information for it in the dts, otherwise the ecspi1 driver can't work and the connected flash is wrongly detected as a mr25h256 flash like this: m25p80 spi32766.0: found mr25h256, expected sst25vf016b m25p80 spi32766.0: mr25h256 (32 Kbytes) Cc: Richard Zhao Signed-off-by: Hui Wang Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 46fdfd1..d42e851 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -27,6 +27,8 @@ ecspi@02008000 { /* eCSPI1 */ fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; status = "okay"; flash: m25p80@0 { @@ -50,6 +52,7 @@ pinctrl_gpio_hog: gpiohog { fsl,pins = < 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ + 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ >; }; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 693f31f..c25d495 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -581,6 +581,14 @@ 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ }; }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ + 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ + 94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ + }; + }; }; dcic@020e4000 { /* DCIC1 */ -- cgit v0.10.2 From 9d5f6b51bdaff83b85069a2eee7a89c562a5daba Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Wed, 11 Jul 2012 12:52:35 -0300 Subject: ARM: imx6q: ensure ANATOP controller is available During imx6q initialization the usb charger detector is disabled but for it, ANATOP controller symbols need to be available. Signed-off-by: Otavio Salvador Cc: Richard Zhao Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index c296851..ebc4f30 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -834,6 +834,7 @@ config SOC_IMX6Q select HAVE_IMX_MMDC select HAVE_IMX_SRC select HAVE_SMP + select MFD_ANATOP select PINCTRL select PINCTRL_IMX6Q select USE_OF -- cgit v0.10.2 From e9f9c8262a85bfe5ab657b38b8c0132c86c3722e Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Fri, 13 Jul 2012 15:22:43 +0900 Subject: ARM: S3C64XX: Add a new dma request id for device tree based dma channel lookup Commit 4972a80e16a2 (ARM: SAMSUNG: Add device tree support for pl330 dma engine wrappers) introduced a new member 'dt_dmach_prop' in the struct samsung_dma_info which is used to specify the dma channel number property as obtained from the device tree. It also introduced a new dma request id 'DMACH_DT_PROP' to indicate that a device tree node property represting the dma channel is available in 'struct samsung_dma_info'. Add dma request id 'DMACH_DT_PROP' in s3c64xx dma channel id list in order to maintain compatibility to the changes in the Samsung dma wrappper operations. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h index fe1a98c..57b1ff4 100644 --- a/arch/arm/mach-s3c64xx/include/mach/dma.h +++ b/arch/arm/mach-s3c64xx/include/mach/dma.h @@ -21,6 +21,7 @@ */ enum dma_ch { /* DMA0/SDMA0 */ + DMACH_DT_PROP = -1, /* not yet supported, do not use */ DMACH_UART0 = 0, DMACH_UART0_SRC2, DMACH_UART1, -- cgit v0.10.2 From 2b54be661191532ddf1628c3b151b81ae8743caa Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Fri, 13 Jul 2012 07:15:14 +0900 Subject: spi: s3c64xx: remove unused S3C64XX_SPI_ST_TRLCNTZ macro The macro S3C64XX_SPI_ST_TRLCNTZ is not used and hence it is removed. Signed-off-by: Thomas Abraham Acked-by: Jaswinder Singh Acked-by: Grant Likely Signed-off-by: Kukjin Kim diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 3c36cfa..6e60eec 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -113,10 +113,6 @@ #define S3C64XX_SPI_FBCLK_MSK (3<<0) -#define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \ - (((i)->fifo_lvl_mask + 1))) \ - ? 1 : 0) - #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0) #define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask) #define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask) -- cgit v0.10.2 From a5238e360b715e9a1bb39d7d3537f78cc9e9e286 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Fri, 13 Jul 2012 07:15:14 +0900 Subject: spi: s3c64xx: move controller information into driver data Platform data is used to specify controller hardware specific information such as the tx/rx fifo level mask and bit offset of rx fifo level. Such information is not suitable to be supplied from device tree. Instead, it can be moved into the driver data and removed from platform data. Signed-off-by: Thomas Abraham Acked-by: Jaswinder Singh Acked-by: Grant Likely Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index bcb7db4..10a46a9 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -586,17 +586,17 @@ static struct clk exynos4_init_clocks_off[] = { .ctrlbit = (1 << 13), }, { .name = "spi", - .devname = "s3c64xx-spi.0", + .devname = "exynos4210-spi.0", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 16), }, { .name = "spi", - .devname = "s3c64xx-spi.1", + .devname = "exynos4210-spi.1", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 17), }, { .name = "spi", - .devname = "s3c64xx-spi.2", + .devname = "exynos4210-spi.2", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 18), }, { @@ -1245,7 +1245,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = { static struct clksrc_clk exynos4_clk_sclk_spi0 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.0", + .devname = "exynos4210-spi.0", .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 16), }, @@ -1257,7 +1257,7 @@ static struct clksrc_clk exynos4_clk_sclk_spi0 = { static struct clksrc_clk exynos4_clk_sclk_spi1 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.1", + .devname = "exynos4210-spi.1", .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 20), }, @@ -1269,7 +1269,7 @@ static struct clksrc_clk exynos4_clk_sclk_spi1 = { static struct clksrc_clk exynos4_clk_sclk_spi2 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.2", + .devname = "exynos4210-spi.2", .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 24), }, @@ -1347,9 +1347,9 @@ static struct clk_lookup exynos4_clk_lookup[] = { CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), - CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), + CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), + CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), + CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), }; static int xtal_rate; diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c index 833ff40..a71ec4d 100644 --- a/arch/arm/mach-exynos/setup-spi.c +++ b/arch/arm/mach-exynos/setup-spi.c @@ -12,17 +12,8 @@ #include #include -#include #ifdef CONFIG_S3C64XX_DEV_SPI0 -struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { - .fifo_lvl_mask = 0x1ff, - .rx_lvl_offset = 15, - .high_speed = 1, - .clk_from_cmu = true, - .tx_st_done = 25, -}; - int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2)); @@ -34,14 +25,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 15, - .high_speed = 1, - .clk_from_cmu = true, - .tx_st_done = 25, -}; - int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2)); @@ -53,14 +36,6 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI2 -struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 15, - .high_speed = 1, - .clk_from_cmu = true, - .tx_st_done = 25, -}; - int s3c64xx_spi2_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5)); diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c index 8702ecf..14a81c2 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2416.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c @@ -144,7 +144,8 @@ static struct clk_lookup s3c2416_clk_lookup[] = { CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk), CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk), + /* s3c2443-spi.0 is used on s3c2416 and s3c2450 as well */ + CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk), }; void __init s3c2416_init_clocks(int xtal) diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c index a4c5a52..7f689ce 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2443.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c @@ -181,7 +181,7 @@ static struct clk *clks[] __initdata = { static struct clk_lookup s3c2443_clk_lookup[] = { CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk), + CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk), }; void __init s3c2443_init_clocks(int xtal) diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c index aeeb2be..aeb4a24 100644 --- a/arch/arm/mach-s3c24xx/common-s3c2443.c +++ b/arch/arm/mach-s3c24xx/common-s3c2443.c @@ -559,7 +559,7 @@ static struct clk hsmmc1_clk = { static struct clk hsspi_clk = { .name = "spi", - .devname = "s3c64xx-spi.0", + .devname = "s3c2443-spi.0", .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit = S3C2443_PCLKCON_HSSPI, @@ -633,7 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk), + CLKDEV_INIT("s3c2443-spi.0", "spi_busclk0", &hsspi_clk), }; void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c index 5712c85..42abe15 100644 --- a/arch/arm/mach-s3c24xx/setup-spi.c +++ b/arch/arm/mach-s3c24xx/setup-spi.c @@ -13,19 +13,11 @@ #include #include -#include #include #include #ifdef CONFIG_S3C64XX_DEV_SPI0 -struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .tx_st_done = 21, - .high_speed = 1, -}; - int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev) { /* enable hsspi bit in misccr */ diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 52f079a..28041e8 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -178,13 +178,13 @@ static struct clk init_clocks_off[] = { .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, }, { .name = "spi", - .devname = "s3c64xx-spi.0", + .devname = "s3c6410-spi.0", .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_SPI0, }, { .name = "spi", - .devname = "s3c64xx-spi.1", + .devname = "s3c6410-spi.1", .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_SPI1, @@ -331,7 +331,7 @@ static struct clk init_clocks_off[] = { static struct clk clk_48m_spi0 = { .name = "spi_48m", - .devname = "s3c64xx-spi.0", + .devname = "s3c6410-spi.0", .parent = &clk_48m, .enable = s3c64xx_sclk_ctrl, .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, @@ -339,7 +339,7 @@ static struct clk clk_48m_spi0 = { static struct clk clk_48m_spi1 = { .name = "spi_48m", - .devname = "s3c64xx-spi.1", + .devname = "s3c6410-spi.1", .parent = &clk_48m, .enable = s3c64xx_sclk_ctrl, .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, @@ -802,7 +802,7 @@ static struct clksrc_clk clk_sclk_mmc2 = { static struct clksrc_clk clk_sclk_spi0 = { .clk = { .name = "spi-bus", - .devname = "s3c64xx-spi.0", + .devname = "s3c6410-spi.0", .ctrlbit = S3C_CLKCON_SCLK_SPI0, .enable = s3c64xx_sclk_ctrl, }, @@ -814,7 +814,7 @@ static struct clksrc_clk clk_sclk_spi0 = { static struct clksrc_clk clk_sclk_spi1 = { .clk = { .name = "spi-bus", - .devname = "s3c64xx-spi.1", + .devname = "s3c6410-spi.1", .ctrlbit = S3C_CLKCON_SCLK_SPI1, .enable = s3c64xx_sclk_ctrl, }, @@ -858,10 +858,10 @@ static struct clk_lookup s3c64xx_clk_lookup[] = { CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1), + CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), + CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0), + CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), + CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1), }; #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c index d9592ad..ff999d9 100644 --- a/arch/arm/mach-s3c64xx/setup-spi.c +++ b/arch/arm/mach-s3c64xx/setup-spi.c @@ -12,15 +12,8 @@ #include #include -#include #ifdef CONFIG_S3C64XX_DEV_SPI0 -struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .tx_st_done = 21, -}; - int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3, @@ -30,12 +23,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .tx_st_done = 21, -}; - int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3, diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c index ee1e8e7..0004455 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c @@ -227,13 +227,13 @@ static struct clk init_clocks_off[] = { .ctrlbit = (1 << 17), }, { .name = "spi", - .devname = "s3c64xx-spi.0", + .devname = "s5p64x0-spi.0", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 21), }, { .name = "spi", - .devname = "s3c64xx-spi.1", + .devname = "s5p64x0-spi.1", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 22), @@ -467,7 +467,7 @@ static struct clksrc_clk clk_sclk_uclk = { static struct clksrc_clk clk_sclk_spi0 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.0", + .devname = "s5p64x0-spi.0", .ctrlbit = (1 << 20), .enable = s5p64x0_sclk_ctrl, }, @@ -479,7 +479,7 @@ static struct clksrc_clk clk_sclk_spi0 = { static struct clksrc_clk clk_sclk_spi1 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.1", + .devname = "s5p64x0-spi.1", .ctrlbit = (1 << 21), .enable = s5p64x0_sclk_ctrl, }, @@ -519,8 +519,8 @@ static struct clk_lookup s5p6440_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), + CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), + CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c index dae6a13..f3e0ef3 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c @@ -236,13 +236,13 @@ static struct clk init_clocks_off[] = { .ctrlbit = (1 << 17), }, { .name = "spi", - .devname = "s3c64xx-spi.0", + .devname = "s5p64x0-spi.0", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 21), }, { .name = "spi", - .devname = "s3c64xx-spi.1", + .devname = "s5p64x0-spi.1", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 22), @@ -528,7 +528,7 @@ static struct clksrc_clk clk_sclk_uclk = { static struct clksrc_clk clk_sclk_spi0 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.0", + .devname = "s5p64x0-spi.0", .ctrlbit = (1 << 20), .enable = s5p64x0_sclk_ctrl, }, @@ -540,7 +540,7 @@ static struct clksrc_clk clk_sclk_spi0 = { static struct clksrc_clk clk_sclk_spi1 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.1", + .devname = "s5p64x0-spi.1", .ctrlbit = (1 << 21), .enable = s5p64x0_sclk_ctrl, }, @@ -562,8 +562,8 @@ static struct clk_lookup s5p6450_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), + CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), + CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c index e9b8412..1cf84b5 100644 --- a/arch/arm/mach-s5p64x0/setup-spi.c +++ b/arch/arm/mach-s5p64x0/setup-spi.c @@ -10,19 +10,9 @@ #include #include -#include - #include -#include -#include #ifdef CONFIG_S3C64XX_DEV_SPI0 -struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { - .fifo_lvl_mask = 0x1ff, - .rx_lvl_offset = 15, - .tx_st_done = 25, -}; - int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) { if (soc_is_s5p6450()) @@ -36,12 +26,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 15, - .tx_st_done = 25, -}; - int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) { if (soc_is_s5p6450()) diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c index 16eca4e..9262197 100644 --- a/arch/arm/mach-s5pc100/clock.c +++ b/arch/arm/mach-s5pc100/clock.c @@ -564,19 +564,19 @@ static struct clk init_clocks_off[] = { .ctrlbit = (1 << 5), }, { .name = "spi", - .devname = "s3c64xx-spi.0", + .devname = "s5pc100-spi.0", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 6), }, { .name = "spi", - .devname = "s3c64xx-spi.1", + .devname = "s5pc100-spi.1", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 7), }, { .name = "spi", - .devname = "s3c64xx-spi.2", + .devname = "s5pc100-spi.2", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 8), @@ -702,7 +702,7 @@ static struct clk clk_hsmmc0 = { static struct clk clk_48m_spi0 = { .name = "spi_48m", - .devname = "s3c64xx-spi.0", + .devname = "s5pc100-spi.0", .parent = &clk_mout_48m.clk, .enable = s5pc100_sclk0_ctrl, .ctrlbit = (1 << 7), @@ -710,7 +710,7 @@ static struct clk clk_48m_spi0 = { static struct clk clk_48m_spi1 = { .name = "spi_48m", - .devname = "s3c64xx-spi.1", + .devname = "s5pc100-spi.1", .parent = &clk_mout_48m.clk, .enable = s5pc100_sclk0_ctrl, .ctrlbit = (1 << 8), @@ -718,7 +718,7 @@ static struct clk clk_48m_spi1 = { static struct clk clk_48m_spi2 = { .name = "spi_48m", - .devname = "s3c64xx-spi.2", + .devname = "s5pc100-spi.2", .parent = &clk_mout_48m.clk, .enable = s5pc100_sclk0_ctrl, .ctrlbit = (1 << 9), @@ -1085,7 +1085,7 @@ static struct clksrc_clk clk_sclk_mmc2 = { static struct clksrc_clk clk_sclk_spi0 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.0", + .devname = "s5pc100-spi.0", .ctrlbit = (1 << 4), .enable = s5pc100_sclk0_ctrl, }, @@ -1097,7 +1097,7 @@ static struct clksrc_clk clk_sclk_spi0 = { static struct clksrc_clk clk_sclk_spi1 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.1", + .devname = "s5pc100-spi.1", .ctrlbit = (1 << 5), .enable = s5pc100_sclk0_ctrl, }, @@ -1109,7 +1109,7 @@ static struct clksrc_clk clk_sclk_spi1 = { static struct clksrc_clk clk_sclk_spi2 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.2", + .devname = "s5pc100-spi.2", .ctrlbit = (1 << 6), .enable = s5pc100_sclk0_ctrl, }, @@ -1315,12 +1315,12 @@ static struct clk_lookup s5pc100_clk_lookup[] = { CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk), - CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2), - CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk), + CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0), + CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk), + CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1), + CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk), + CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2), + CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk), }; void __init s5pc100_register_clocks(void) diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c index 431a6f7..4b42718 100644 --- a/arch/arm/mach-s5pc100/setup-spi.c +++ b/arch/arm/mach-s5pc100/setup-spi.c @@ -12,16 +12,8 @@ #include #include -#include #ifdef CONFIG_S3C64XX_DEV_SPI0 -struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .high_speed = 1, - .tx_st_done = 21, -}; - int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgall_range(S5PC100_GPB(0), 3, @@ -31,13 +23,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .high_speed = 1, - .tx_st_done = 21, -}; - int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgall_range(S5PC100_GPB(4), 3, @@ -47,13 +32,6 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI2 -struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .high_speed = 1, - .tx_st_done = 21, -}; - int s3c64xx_spi2_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index 09609d5..fcdf52d 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -445,19 +445,19 @@ static struct clk init_clocks_off[] = { .ctrlbit = (1 << 11), }, { .name = "spi", - .devname = "s3c64xx-spi.0", + .devname = "s5pv210-spi.0", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<12), }, { .name = "spi", - .devname = "s3c64xx-spi.1", + .devname = "s5pv210-spi.1", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<13), }, { .name = "spi", - .devname = "s3c64xx-spi.2", + .devname = "s5pv210-spi.2", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<14), @@ -1035,7 +1035,7 @@ static struct clksrc_clk clk_sclk_mmc3 = { static struct clksrc_clk clk_sclk_spi0 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.0", + .devname = "s5pv210-spi.0", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 16), }, @@ -1047,7 +1047,7 @@ static struct clksrc_clk clk_sclk_spi0 = { static struct clksrc_clk clk_sclk_spi1 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.1", + .devname = "s5pv210-spi.1", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 17), }, @@ -1331,8 +1331,8 @@ static struct clk_lookup s5pv210_clk_lookup[] = { CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), + CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), + CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), }; void __init s5pv210_register_clocks(void) diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c index f43c504..2cd66a6 100644 --- a/arch/arm/mach-s5pv210/setup-spi.c +++ b/arch/arm/mach-s5pv210/setup-spi.c @@ -12,16 +12,8 @@ #include #include -#include #ifdef CONFIG_S3C64XX_DEV_SPI0 -struct s3c64xx_spi_info s3c64xx_spi0_pdata = { - .fifo_lvl_mask = 0x1ff, - .rx_lvl_offset = 15, - .high_speed = 1, - .tx_st_done = 25, -}; - int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2)); @@ -33,13 +25,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -struct s3c64xx_spi_info s3c64xx_spi1_pdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 15, - .high_speed = 1, - .tx_st_done = 25, -}; - int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2)); diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index fa95e9a..4e9b9c3 100644 --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h @@ -33,28 +33,13 @@ struct s3c64xx_spi_csinfo { /** * struct s3c64xx_spi_info - SPI Controller defining structure * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. - * @clk_from_cmu: If the SPI clock/prescalar control block is present - * by the platform's clock-management-unit and not in SPI controller. * @num_cs: Number of CS this controller emulates. * @cfg_gpio: Configure pins for this SPI controller. - * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6 - * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number - * @high_speed: If the controller supports HIGH_SPEED_EN bit - * @tx_st_done: Depends on tx fifo_lvl field */ struct s3c64xx_spi_info { int src_clk_nr; - bool clk_from_cmu; - int num_cs; - int (*cfg_gpio)(struct platform_device *pdev); - - /* Following two fields are for future compatibility */ - int fifo_lvl_mask; - int rx_lvl_offset; - int high_speed; - int tx_st_done; }; /** diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 6e60eec..8698618 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -31,6 +31,8 @@ #include #include +#define MAX_SPI_PORTS 3 + /* Registers and bit-fields */ #define S3C64XX_SPI_CH_CFG 0x00 @@ -113,9 +115,12 @@ #define S3C64XX_SPI_FBCLK_MSK (3<<0) -#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0) -#define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask) -#define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask) +#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) +#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ + (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) +#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) +#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ + FIFO_LVL_MASK(i)) #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff #define S3C64XX_SPI_TRAILCNT_OFF 19 @@ -134,6 +139,28 @@ struct s3c64xx_spi_dma_data { }; /** + * struct s3c64xx_spi_info - SPI Controller hardware info + * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. + * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. + * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. + * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. + * @clk_from_cmu: True, if the controller does not include a clock mux and + * prescaler unit. + * + * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but + * differ in some aspects such as the size of the fifo and spi bus clock + * setup. Such differences are specified to the driver using this structure + * which is provided as driver data to the driver. + */ +struct s3c64xx_spi_port_config { + int fifo_lvl_mask[MAX_SPI_PORTS]; + int rx_lvl_offset; + int tx_st_done; + bool high_speed; + bool clk_from_cmu; +}; + +/** * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. * @clk: Pointer to the spi clock. * @src_clk: Pointer to the clock used to generate SPI signals. @@ -171,6 +198,8 @@ struct s3c64xx_spi_driver_data { struct s3c64xx_spi_dma_data rx_dma; struct s3c64xx_spi_dma_data tx_dma; struct samsung_dma_ops *ops; + struct s3c64xx_spi_port_config *port_conf; + unsigned int port_id; }; static struct s3c2410_dma_client s3c64xx_spi_dma_client = { @@ -179,7 +208,6 @@ static struct s3c2410_dma_client s3c64xx_spi_dma_client = { static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) { - struct s3c64xx_spi_info *sci = sdd->cntrlr_info; void __iomem *regs = sdd->regs; unsigned long loops; u32 val; @@ -195,7 +223,7 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) loops = msecs_to_loops(1); do { val = readl(regs + S3C64XX_SPI_STATUS); - } while (TX_FIFO_LVL(val, sci) && loops--); + } while (TX_FIFO_LVL(val, sdd) && loops--); if (loops == 0) dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); @@ -204,7 +232,7 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) loops = msecs_to_loops(1); do { val = readl(regs + S3C64XX_SPI_STATUS); - if (RX_FIFO_LVL(val, sci)) + if (RX_FIFO_LVL(val, sdd)) readl(regs + S3C64XX_SPI_RX_DATA); else break; @@ -307,7 +335,6 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, struct spi_device *spi, struct spi_transfer *xfer, int dma_mode) { - struct s3c64xx_spi_info *sci = sdd->cntrlr_info; void __iomem *regs = sdd->regs; u32 modecfg, chcfg; @@ -357,7 +384,7 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, if (xfer->rx_buf != NULL) { sdd->state |= RXBUSY; - if (sci->high_speed && sdd->cur_speed >= 30000000UL + if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL && !(sdd->cur_mode & SPI_CPHA)) chcfg |= S3C64XX_SPI_CH_HS_EN; @@ -397,7 +424,6 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd, static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, struct spi_transfer *xfer, int dma_mode) { - struct s3c64xx_spi_info *sci = sdd->cntrlr_info; void __iomem *regs = sdd->regs; unsigned long val; int ms; @@ -414,7 +440,7 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, val = msecs_to_loops(ms); do { status = readl(regs + S3C64XX_SPI_STATUS); - } while (RX_FIFO_LVL(status, sci) < xfer->len && --val); + } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); } if (!val) @@ -433,8 +459,8 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, if (xfer->rx_buf == NULL) { val = msecs_to_loops(10); status = readl(regs + S3C64XX_SPI_STATUS); - while ((TX_FIFO_LVL(status, sci) - || !S3C64XX_SPI_ST_TX_DONE(status, sci)) + while ((TX_FIFO_LVL(status, sdd) + || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) && --val) { cpu_relax(); status = readl(regs + S3C64XX_SPI_STATUS); @@ -483,12 +509,11 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd, static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) { - struct s3c64xx_spi_info *sci = sdd->cntrlr_info; void __iomem *regs = sdd->regs; u32 val; /* Disable Clock */ - if (sci->clk_from_cmu) { + if (sdd->port_conf->clk_from_cmu) { clk_disable(sdd->src_clk); } else { val = readl(regs + S3C64XX_SPI_CLK_CFG); @@ -532,7 +557,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) writel(val, regs + S3C64XX_SPI_MODE_CFG); - if (sci->clk_from_cmu) { + if (sdd->port_conf->clk_from_cmu) { /* Configure Clock */ /* There is half-multiplier before the SPI */ clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); @@ -558,7 +583,6 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd, struct spi_message *msg) { - struct s3c64xx_spi_info *sci = sdd->cntrlr_info; struct device *dev = &sdd->pdev->dev; struct spi_transfer *xfer; @@ -574,7 +598,7 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd, /* Map until end or first fail */ list_for_each_entry(xfer, &msg->transfers, transfer_list) { - if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) + if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1)) continue; if (xfer->tx_buf != NULL) { @@ -608,7 +632,6 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd, static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd, struct spi_message *msg) { - struct s3c64xx_spi_info *sci = sdd->cntrlr_info; struct device *dev = &sdd->pdev->dev; struct spi_transfer *xfer; @@ -617,7 +640,7 @@ static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd, list_for_each_entry(xfer, &msg->transfers, transfer_list) { - if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) + if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1)) continue; if (xfer->rx_buf != NULL @@ -636,7 +659,6 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master, struct spi_message *msg) { struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); - struct s3c64xx_spi_info *sci = sdd->cntrlr_info; struct spi_device *spi = msg->spi; struct s3c64xx_spi_csinfo *cs = spi->controller_data; struct spi_transfer *xfer; @@ -691,7 +713,7 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master, } /* Polling method for xfers not bigger than FIFO capacity */ - if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) + if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1)) use_dma = 0; else use_dma = 1; @@ -845,7 +867,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi) pm_runtime_get_sync(&sdd->pdev->dev); /* Check if we can provide the requested rate */ - if (!sci->clk_from_cmu) { + if (!sdd->port_conf->clk_from_cmu) { u32 psr, speed; /* Max possible */ @@ -926,7 +948,7 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) /* Disable Interrupts - we use Polling if not DMA mode */ writel(0, regs + S3C64XX_SPI_INT_EN); - if (!sci->clk_from_cmu) + if (!sdd->port_conf->clk_from_cmu) writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, regs + S3C64XX_SPI_CLK_CFG); writel(0, regs + S3C64XX_SPI_MODE_CFG); @@ -947,6 +969,13 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) flush_fifo(sdd); } +static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( + struct platform_device *pdev) +{ + return (struct s3c64xx_spi_port_config *) + platform_get_device_id(pdev)->driver_data; +} + static int __init s3c64xx_spi_probe(struct platform_device *pdev) { struct resource *mem_res, *dmatx_res, *dmarx_res; @@ -1005,6 +1034,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) platform_set_drvdata(pdev, master); sdd = spi_master_get_devdata(master); + sdd->port_conf = s3c64xx_spi_get_port_config(pdev); sdd->master = master; sdd->cntrlr_info = sci; sdd->pdev = pdev; @@ -1013,10 +1043,11 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) sdd->tx_dma.direction = DMA_MEM_TO_DEV; sdd->rx_dma.dmach = dmarx_res->start; sdd->rx_dma.direction = DMA_DEV_TO_MEM; + sdd->port_id = pdev->id; sdd->cur_bpw = 8; - master->bus_num = pdev->id; + master->bus_num = sdd->port_id; master->setup = s3c64xx_spi_setup; master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; master->transfer_one_message = s3c64xx_spi_transfer_one_message; @@ -1076,7 +1107,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) } /* Setup Deufult Mode */ - s3c64xx_spi_hwinit(sdd, pdev->id); + s3c64xx_spi_hwinit(sdd, sdd->port_id); spin_lock_init(&sdd->lock); init_completion(&sdd->xfer_completion); @@ -1101,7 +1132,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d " "with %d Slaves attached\n", - pdev->id, master->num_chipselect); + sdd->port_id, master->num_chipselect); dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n", mem_res->end, mem_res->start, sdd->rx_dma.dmach, sdd->tx_dma.dmach); @@ -1194,7 +1225,7 @@ static int s3c64xx_spi_resume(struct device *dev) clk_enable(sdd->src_clk); clk_enable(sdd->clk); - s3c64xx_spi_hwinit(sdd, pdev->id); + s3c64xx_spi_hwinit(sdd, sdd->port_id); spi_master_resume(master); @@ -1232,6 +1263,70 @@ static const struct dev_pm_ops s3c64xx_spi_pm = { s3c64xx_spi_runtime_resume, NULL) }; +struct s3c64xx_spi_port_config s3c2443_spi_port_config = { + .fifo_lvl_mask = { 0x7f }, + .rx_lvl_offset = 13, + .tx_st_done = 21, + .high_speed = true, +}; + +struct s3c64xx_spi_port_config s3c6410_spi_port_config = { + .fifo_lvl_mask = { 0x7f, 0x7F }, + .rx_lvl_offset = 13, + .tx_st_done = 21, +}; + +struct s3c64xx_spi_port_config s5p64x0_spi_port_config = { + .fifo_lvl_mask = { 0x1ff, 0x7F }, + .rx_lvl_offset = 15, + .tx_st_done = 25, +}; + +struct s3c64xx_spi_port_config s5pc100_spi_port_config = { + .fifo_lvl_mask = { 0x7f, 0x7F }, + .rx_lvl_offset = 13, + .tx_st_done = 21, + .high_speed = true, +}; + +struct s3c64xx_spi_port_config s5pv210_spi_port_config = { + .fifo_lvl_mask = { 0x1ff, 0x7F }, + .rx_lvl_offset = 15, + .tx_st_done = 25, + .high_speed = true, +}; + +struct s3c64xx_spi_port_config exynos4_spi_port_config = { + .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, + .rx_lvl_offset = 15, + .tx_st_done = 25, + .high_speed = true, + .clk_from_cmu = true, +}; + +static struct platform_device_id s3c64xx_spi_driver_ids[] = { + { + .name = "s3c2443-spi", + .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, + }, { + .name = "s3c6410-spi", + .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, + }, { + .name = "s5p64x0-spi", + .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config, + }, { + .name = "s5pc100-spi", + .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config, + }, { + .name = "s5pv210-spi", + .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config, + }, { + .name = "exynos4210-spi", + .driver_data = (kernel_ulong_t)&exynos4_spi_port_config, + }, + { }, +}; + static struct platform_driver s3c64xx_spi_driver = { .driver = { .name = "s3c64xx-spi", @@ -1239,6 +1334,7 @@ static struct platform_driver s3c64xx_spi_driver = { .pm = &s3c64xx_spi_pm, }, .remove = s3c64xx_spi_remove, + .id_table = s3c64xx_spi_driver_ids, }; MODULE_ALIAS("platform:s3c64xx-spi"); -- cgit v0.10.2 From 868dee91a5f96dfbc97b2cd582614cdc339ec305 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Fri, 13 Jul 2012 07:15:14 +0900 Subject: ARM: SAMSUNG: Remove pdev pointer parameter from spi gpio setup functions The platform data pointer that is passed to the spi gpio setup functions is not used. Hence, this parameter is removed from all the spi gpio setup functions. Signed-off-by: Thomas Abraham Acked-by: Jaswinder Singh Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c index a71ec4d..4999829 100644 --- a/arch/arm/mach-exynos/setup-spi.c +++ b/arch/arm/mach-exynos/setup-spi.c @@ -9,12 +9,10 @@ */ #include -#include - #include #ifdef CONFIG_S3C64XX_DEV_SPI0 -int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi0_cfg_gpio(void) { s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2)); s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP); @@ -25,7 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi1_cfg_gpio(void) { s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2)); s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP); @@ -36,7 +34,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI2 -int s3c64xx_spi2_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi2_cfg_gpio(void) { s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5)); s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP); diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c index 42abe15..3d47e02 100644 --- a/arch/arm/mach-s3c24xx/setup-spi.c +++ b/arch/arm/mach-s3c24xx/setup-spi.c @@ -18,7 +18,7 @@ #include #ifdef CONFIG_S3C64XX_DEV_SPI0 -int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev) +int s3c64xx_spi0_cfg_gpio(void) { /* enable hsspi bit in misccr */ s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1); diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c index ff999d9..4dc5345 100644 --- a/arch/arm/mach-s3c64xx/setup-spi.c +++ b/arch/arm/mach-s3c64xx/setup-spi.c @@ -9,12 +9,10 @@ */ #include -#include - #include #ifdef CONFIG_S3C64XX_DEV_SPI0 -int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi0_cfg_gpio(void) { s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3, S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); @@ -23,7 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi1_cfg_gpio(void) { s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3, S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c index 1cf84b5..7664356 100644 --- a/arch/arm/mach-s5p64x0/setup-spi.c +++ b/arch/arm/mach-s5p64x0/setup-spi.c @@ -9,11 +9,10 @@ */ #include -#include #include #ifdef CONFIG_S3C64XX_DEV_SPI0 -int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi0_cfg_gpio(void) { if (soc_is_s5p6450()) s3c_gpio_cfgall_range(S5P6450_GPC(0), 3, @@ -26,7 +25,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi1_cfg_gpio(void) { if (soc_is_s5p6450()) s3c_gpio_cfgall_range(S5P6450_GPC(4), 3, diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c index 4b42718..1835679 100644 --- a/arch/arm/mach-s5pc100/setup-spi.c +++ b/arch/arm/mach-s5pc100/setup-spi.c @@ -9,12 +9,10 @@ */ #include -#include - #include #ifdef CONFIG_S3C64XX_DEV_SPI0 -int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi0_cfg_gpio(void) { s3c_gpio_cfgall_range(S5PC100_GPB(0), 3, S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); @@ -23,7 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi1_cfg_gpio(void) { s3c_gpio_cfgall_range(S5PC100_GPB(4), 3, S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); @@ -32,7 +30,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI2 -int s3c64xx_spi2_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi2_cfg_gpio(void) { s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP); diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c index 2cd66a6..81aecc1 100644 --- a/arch/arm/mach-s5pv210/setup-spi.c +++ b/arch/arm/mach-s5pv210/setup-spi.c @@ -9,12 +9,10 @@ */ #include -#include - #include #ifdef CONFIG_S3C64XX_DEV_SPI0 -int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi0_cfg_gpio(void) { s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2)); s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP); @@ -25,7 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi1_cfg_gpio(void) { s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2)); s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP); diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index 4e9b9c3..89dbaee 100644 --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h @@ -39,7 +39,7 @@ struct s3c64xx_spi_csinfo { struct s3c64xx_spi_info { int src_clk_nr; int num_cs; - int (*cfg_gpio)(struct platform_device *pdev); + int (*cfg_gpio)(void); }; /** @@ -60,9 +60,9 @@ extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd, int src_clk_nr, int num_cs); /* defined by architecture to configure gpio */ -extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev); -extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev); -extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev); +extern int s3c64xx_spi0_cfg_gpio(void); +extern int s3c64xx_spi1_cfg_gpio(void); +extern int s3c64xx_spi2_cfg_gpio(void); extern struct s3c64xx_spi_info s3c64xx_spi0_pdata; extern struct s3c64xx_spi_info s3c64xx_spi1_pdata; diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 8698618..0a9e43e 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1071,7 +1071,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) goto err1; } - if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) { + if (sci->cfg_gpio == NULL || sci->cfg_gpio()) { dev_err(&pdev->dev, "Unable to config gpio\n"); ret = -EBUSY; goto err2; @@ -1214,12 +1214,11 @@ static int s3c64xx_spi_suspend(struct device *dev) static int s3c64xx_spi_resume(struct device *dev) { - struct platform_device *pdev = to_platform_device(dev); struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); struct s3c64xx_spi_info *sci = sdd->cntrlr_info; - sci->cfg_gpio(pdev); + sci->cfg_gpio(); /* Enable the clock */ clk_enable(sdd->src_clk); -- cgit v0.10.2 From 4d0efdd5889b1c81a62aa07a47d3d55be4b65b61 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Fri, 13 Jul 2012 07:15:14 +0900 Subject: ARM: SAMSUNG: Modify s3c64xx_spi{0|1|2}_set_platdata function With the spi controller hardware configuration moved into the driver data, there are no more default hardware configuration data that is passed through platform data. Accordingly, the s3c64xx_spi{0|1|2}_set_platdata functions are adapted to these changes. Signed-off-by: Thomas Abraham Acked-by: Jaswinder Singh Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c index d0c352d..6dd4fae3 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c @@ -799,7 +799,7 @@ static void __init crag6410_machine_init(void) i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); samsung_keypad_set_platdata(&crag6410_keypad_data); - s3c64xx_spi0_set_platdata(&s3c64xx_spi0_pdata, 0, 1); + s3c64xx_spi0_set_platdata(NULL, 0, 1); platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices)); diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 1d214cb..86d0758 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -1512,7 +1512,7 @@ static struct resource s3c64xx_spi0_resource[] = { }; struct platform_device s3c64xx_device_spi0 = { - .name = "s3c64xx-spi", + .name = "s3c6410-spi", .id = 0, .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource), .resource = s3c64xx_spi0_resource, @@ -1522,13 +1522,10 @@ struct platform_device s3c64xx_device_spi0 = { }, }; -void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd, - int src_clk_nr, int num_cs) +void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, + int num_cs) { - if (!pd) { - pr_err("%s:Need to pass platform data\n", __func__); - return; - } + struct s3c64xx_spi_info pd; /* Reject invalid configuration */ if (!num_cs || src_clk_nr < 0) { @@ -1536,12 +1533,11 @@ void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd, return; } - pd->num_cs = num_cs; - pd->src_clk_nr = src_clk_nr; - if (!pd->cfg_gpio) - pd->cfg_gpio = s3c64xx_spi0_cfg_gpio; + pd.num_cs = num_cs; + pd.src_clk_nr = src_clk_nr; + pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio; - s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0); + s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0); } #endif /* CONFIG_S3C64XX_DEV_SPI0 */ @@ -1554,7 +1550,7 @@ static struct resource s3c64xx_spi1_resource[] = { }; struct platform_device s3c64xx_device_spi1 = { - .name = "s3c64xx-spi", + .name = "s3c6410-spi", .id = 1, .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource), .resource = s3c64xx_spi1_resource, @@ -1564,26 +1560,20 @@ struct platform_device s3c64xx_device_spi1 = { }, }; -void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd, - int src_clk_nr, int num_cs) +void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, + int num_cs) { - if (!pd) { - pr_err("%s:Need to pass platform data\n", __func__); - return; - } - /* Reject invalid configuration */ if (!num_cs || src_clk_nr < 0) { pr_err("%s: Invalid SPI configuration\n", __func__); return; } - pd->num_cs = num_cs; - pd->src_clk_nr = src_clk_nr; - if (!pd->cfg_gpio) - pd->cfg_gpio = s3c64xx_spi1_cfg_gpio; + pd.num_cs = num_cs; + pd.src_clk_nr = src_clk_nr; + pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio; - s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1); + s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1); } #endif /* CONFIG_S3C64XX_DEV_SPI1 */ @@ -1596,7 +1586,7 @@ static struct resource s3c64xx_spi2_resource[] = { }; struct platform_device s3c64xx_device_spi2 = { - .name = "s3c64xx-spi", + .name = "s3c6410-spi", .id = 2, .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource), .resource = s3c64xx_spi2_resource, @@ -1606,13 +1596,10 @@ struct platform_device s3c64xx_device_spi2 = { }, }; -void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd, - int src_clk_nr, int num_cs) +void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, + int num_cs) { - if (!pd) { - pr_err("%s:Need to pass platform data\n", __func__); - return; - } + struct s3c64xx_spi_info pd; /* Reject invalid configuration */ if (!num_cs || src_clk_nr < 0) { @@ -1620,11 +1607,10 @@ void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd, return; } - pd->num_cs = num_cs; - pd->src_clk_nr = src_clk_nr; - if (!pd->cfg_gpio) - pd->cfg_gpio = s3c64xx_spi2_cfg_gpio; + pd.num_cs = num_cs; + pd.src_clk_nr = src_clk_nr; + pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio; - s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2); + s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2); } #endif /* CONFIG_S3C64XX_DEV_SPI2 */ diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index 89dbaee..c818a7c 100644 --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h @@ -45,19 +45,19 @@ struct s3c64xx_spi_info { /** * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board * initialization code. - * @pd: SPI platform data to set. + * @cfg_gpio: Pointer to gpio setup function. * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks. * @num_cs: Number of elements in the 'cs' array. * * Call this from machine init code for each SPI Controller that * has some chips attached to it. */ -extern void s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd, - int src_clk_nr, int num_cs); -extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd, - int src_clk_nr, int num_cs); -extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd, - int src_clk_nr, int num_cs); +extern void s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, + int num_cs); +extern void s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, + int num_cs); +extern void s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, + int num_cs); /* defined by architecture to configure gpio */ extern int s3c64xx_spi0_cfg_gpio(void); -- cgit v0.10.2 From 1c20c200ef96c50b3075f71220c8c8bc018a93c8 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Fri, 13 Jul 2012 07:15:14 +0900 Subject: spi: s3c64xx: Remove the 'set_level' callback from controller data The set_level callback in the controller data, which is used to configure the slave select line, cannot be supported when migrating the driver to device tree based discovery. Since all the platforms currently use gpio as the slave select line, this callback can be removed from the controller data and replaced with call to gpio_set_value in the driver. Signed-off-by: Thomas Abraham Acked-by: Jaswinder Singh Acked-by: Grant Likely Signed-off-by: Kukjin Kim diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index c818a7c..ceba18d 100644 --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h @@ -18,7 +18,6 @@ struct platform_device; * @fb_delay: Slave specific feedback delay. * Refer to FB_CLK_SEL register definition in SPI chapter. * @line: Custom 'identity' of the CS line. - * @set_level: CS line control. * * This is per SPI-Slave Chipselect information. * Allocate and initialize one in machine init code and make the @@ -27,7 +26,6 @@ struct platform_device; struct s3c64xx_spi_csinfo { u8 fb_delay; unsigned line; - void (*set_level)(unsigned line_id, int lvl); }; /** diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 0a9e43e..e4182ea 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -411,14 +412,14 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd, if (sdd->tgl_spi != spi) { /* if last mssg on diff device */ /* Deselect the last toggled device */ cs = sdd->tgl_spi->controller_data; - cs->set_level(cs->line, - spi->mode & SPI_CS_HIGH ? 0 : 1); + gpio_set_value(cs->line, + spi->mode & SPI_CS_HIGH ? 0 : 1); } sdd->tgl_spi = NULL; } cs = spi->controller_data; - cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); } static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, @@ -504,7 +505,7 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd, if (sdd->tgl_spi == spi) sdd->tgl_spi = NULL; - cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); } static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) @@ -833,11 +834,21 @@ static int s3c64xx_spi_setup(struct spi_device *spi) unsigned long flags; int err = 0; - if (cs == NULL || cs->set_level == NULL) { + if (cs == NULL) { dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); return -ENODEV; } + if (!spi_get_ctldata(spi)) { + err = gpio_request(cs->line, dev_name(&spi->dev)); + if (err) { + dev_err(&spi->dev, "request for slave select gpio " + "line [%d] failed\n", cs->line); + return -EBUSY; + } + spi_set_ctldata(spi, cs); + } + sdd = spi_master_get_devdata(spi->master); sci = sdd->cntrlr_info; @@ -908,6 +919,15 @@ setup_exit: return err; } +static void s3c64xx_spi_cleanup(struct spi_device *spi) +{ + struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); + + if (cs) + gpio_free(cs->line); + spi_set_ctldata(spi, NULL); +} + static irqreturn_t s3c64xx_spi_irq(int irq, void *data) { struct s3c64xx_spi_driver_data *sdd = data; @@ -1049,6 +1069,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) master->bus_num = sdd->port_id; master->setup = s3c64xx_spi_setup; + master->cleanup = s3c64xx_spi_cleanup; master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; master->transfer_one_message = s3c64xx_spi_transfer_one_message; master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; -- cgit v0.10.2 From 2b90807549e5d1f700e523ddd098651ecfc18e65 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Fri, 13 Jul 2012 07:15:15 +0900 Subject: spi: s3c64xx: add device tree support Add support for device based discovery. Signed-off-by: Thomas Abraham Acked-by: Jaswinder Singh Acked-by: Grant Likely Signed-off-by: Kukjin Kim diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt new file mode 100644 index 0000000..59bfc4f --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt @@ -0,0 +1,113 @@ +* Samsung SPI Controller + +The Samsung SPI controller is used to interface with various devices such as flash +and display controllers using the SPI communication interface. + +Required SoC Specific Properties: + +- compatible: should be one of the following. + - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms + - samsung,s3c6410-spi: for s3c6410 platforms + - samsung,s5p6440-spi: for s5p6440 and s5p6450 platforms + - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms + - samsung,exynos4210-spi: for exynos4 and exynos5 platforms + +- reg: physical base address of the controller and length of memory mapped + region. + +- interrupts: The interrupt number to the cpu. The interrupt specifier format + depends on the interrupt controller. + +- tx-dma-channel: The dma channel specifier for tx operations. The format of + the dma specifier depends on the dma controller. + +- rx-dma-channel: The dma channel specifier for rx operations. The format of + the dma specifier depends on the dma controller. + +Required Board Specific Properties: + +- #address-cells: should be 1. +- #size-cells: should be 0. +- gpios: The gpio specifier for clock, mosi and miso interface lines (in the + order specified). The format of the gpio specifier depends on the gpio + controller. + +Optional Board Specific Properties: + +- samsung,spi-src-clk: If the spi controller includes a internal clock mux to + select the clock source for the spi bus clock, this property can be used to + indicate the clock to be used for driving the spi bus clock. If not specified, + the clock number 0 is used as default. + +- num-cs: Specifies the number of chip select lines supported. If + not specified, the default number of chip select lines is set to 1. + +SPI Controller specific data in SPI slave nodes: + +- The spi slave nodes should provide the following information which is required + by the spi controller. + + - cs-gpio: A gpio specifier that specifies the gpio line used as + the slave select line by the spi controller. The format of the gpio + specifier depends on the gpio controller. + + - samsung,spi-feedback-delay: The sampling phase shift to be applied on the + miso line (to account for any lag in the miso line). The following are the + valid values. + + - 0: No phase shift. + - 1: 90 degree phase shift sampling. + - 2: 180 degree phase shift sampling. + - 3: 270 degree phase shift sampling. + +Aliases: + +- All the SPI controller nodes should be represented in the aliases node using + the following format 'spi{n}' where n is a unique number for the alias. + + +Example: + +- SoC Specific Portion: + + spi_0: spi@12d20000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d20000 0x100>; + interrupts = <0 66 0>; + tx-dma-channel = <&pdma0 5>; + rx-dma-channel = <&pdma0 4>; + }; + +- Board Specific Portion: + + spi_0: spi@12d20000 { + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpa2 4 2 3 0>, + <&gpa2 6 2 3 0>, + <&gpa2 7 2 3 0>; + + w25q80bw@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25x80"; + reg = <0>; + spi-max-frequency = <10000>; + + controller-data { + cs-gpio = <&gpa2 5 1 0 3>; + samsung,spi-feedback-delay = <0>; + }; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "Kernel"; + reg = <0x40000 0xc0000>; + }; + }; + }; diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index e4182ea..0dedbbd 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -28,6 +28,8 @@ #include #include #include +#include +#include #include #include @@ -137,6 +139,7 @@ struct s3c64xx_spi_dma_data { unsigned ch; enum dma_data_direction direction; enum dma_ch dmach; + struct property *dma_prop; }; /** @@ -201,6 +204,7 @@ struct s3c64xx_spi_driver_data { struct samsung_dma_ops *ops; struct s3c64xx_spi_port_config *port_conf; unsigned int port_id; + unsigned long gpios[4]; }; static struct s3c2410_dma_client s3c64xx_spi_dma_client = { @@ -326,7 +330,9 @@ static int acquire_dma(struct s3c64xx_spi_driver_data *sdd) req.cap = DMA_SLAVE; req.client = &s3c64xx_spi_dma_client; + req.dt_dmach_prop = sdd->rx_dma.dma_prop; sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &req); + req.dt_dmach_prop = sdd->tx_dma.dma_prop; sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &req); return 1; @@ -819,6 +825,48 @@ static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) return 0; } +static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( + struct s3c64xx_spi_driver_data *sdd, + struct spi_device *spi) +{ + struct s3c64xx_spi_csinfo *cs; + struct device_node *slave_np, *data_np; + u32 fb_delay = 0; + + slave_np = spi->dev.of_node; + if (!slave_np) { + dev_err(&spi->dev, "device node not found\n"); + return ERR_PTR(-EINVAL); + } + + for_each_child_of_node(slave_np, data_np) + if (!strcmp(data_np->name, "controller-data")) + break; + if (!data_np) { + dev_err(&spi->dev, "child node 'controller-data' not found\n"); + return ERR_PTR(-EINVAL); + } + + cs = kzalloc(sizeof(*cs), GFP_KERNEL); + if (!cs) { + dev_err(&spi->dev, "could not allocate memory for controller" + " data\n"); + return ERR_PTR(-ENOMEM); + } + + cs->line = of_get_named_gpio(data_np, "cs-gpio", 0); + if (!gpio_is_valid(cs->line)) { + dev_err(&spi->dev, "chip select gpio is not specified or " + "invalid\n"); + kfree(cs); + return ERR_PTR(-EINVAL); + } + + of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); + cs->fb_delay = fb_delay; + return cs; +} + /* * Here we only check the validity of requested configuration * and save the configuration in a local data-structure. @@ -832,9 +880,15 @@ static int s3c64xx_spi_setup(struct spi_device *spi) struct s3c64xx_spi_info *sci; struct spi_message *msg; unsigned long flags; - int err = 0; + int err; - if (cs == NULL) { + sdd = spi_master_get_devdata(spi->master); + if (!cs && spi->dev.of_node) { + cs = s3c64xx_get_slave_ctrldata(sdd, spi); + spi->controller_data = cs; + } + + if (IS_ERR_OR_NULL(cs)) { dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); return -ENODEV; } @@ -844,12 +898,12 @@ static int s3c64xx_spi_setup(struct spi_device *spi) if (err) { dev_err(&spi->dev, "request for slave select gpio " "line [%d] failed\n", cs->line); - return -EBUSY; + err = -EBUSY; + goto err_gpio_req; } spi_set_ctldata(spi, cs); } - sdd = spi_master_get_devdata(spi->master); sci = sdd->cntrlr_info; spin_lock_irqsave(&sdd->lock, flags); @@ -860,7 +914,8 @@ static int s3c64xx_spi_setup(struct spi_device *spi) dev_err(&spi->dev, "setup: attempt while mssg in queue!\n"); spin_unlock_irqrestore(&sdd->lock, flags); - return -EBUSY; + err = -EBUSY; + goto err_msgq; } } @@ -903,19 +958,29 @@ static int s3c64xx_spi_setup(struct spi_device *spi) } speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); - if (spi->max_speed_hz >= speed) + if (spi->max_speed_hz >= speed) { spi->max_speed_hz = speed; - else + } else { err = -EINVAL; + goto setup_exit; + } } pm_runtime_put(&sdd->pdev->dev); + disable_cs(sdd, spi); + return 0; setup_exit: - /* setup() returns with device de-selected */ disable_cs(sdd, spi); +err_msgq: + gpio_free(cs->line); + spi_set_ctldata(spi, NULL); + +err_gpio_req: + kfree(cs); + return err; } @@ -923,8 +988,11 @@ static void s3c64xx_spi_cleanup(struct spi_device *spi) { struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); - if (cs) + if (cs) { gpio_free(cs->line); + if (spi->dev.of_node) + kfree(cs); + } spi_set_ctldata(spi, NULL); } @@ -989,49 +1057,166 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) flush_fifo(sdd); } +static int __devinit s3c64xx_spi_get_dmares( + struct s3c64xx_spi_driver_data *sdd, bool tx) +{ + struct platform_device *pdev = sdd->pdev; + struct s3c64xx_spi_dma_data *dma_data; + struct property *prop; + struct resource *res; + char prop_name[15], *chan_str; + + if (tx) { + dma_data = &sdd->tx_dma; + dma_data->direction = DMA_TO_DEVICE; + chan_str = "tx"; + } else { + dma_data = &sdd->rx_dma; + dma_data->direction = DMA_FROM_DEVICE; + chan_str = "rx"; + } + + if (!sdd->pdev->dev.of_node) { + res = platform_get_resource(pdev, IORESOURCE_DMA, tx ? 0 : 1); + if (!res) { + dev_err(&pdev->dev, "Unable to get SPI-%s dma " + "resource\n", chan_str); + return -ENXIO; + } + dma_data->dmach = res->start; + return 0; + } + + sprintf(prop_name, "%s-dma-channel", chan_str); + prop = of_find_property(pdev->dev.of_node, prop_name, NULL); + if (!prop) { + dev_err(&pdev->dev, "%s dma channel property not specified\n", + chan_str); + return -ENXIO; + } + + dma_data->dmach = DMACH_DT_PROP; + dma_data->dma_prop = prop; + return 0; +} + +#ifdef CONFIG_OF +static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd) +{ + struct device *dev = &sdd->pdev->dev; + int idx, gpio, ret; + + /* find gpios for mosi, miso and clock lines */ + for (idx = 0; idx < 3; idx++) { + gpio = of_get_gpio(dev->of_node, idx); + if (!gpio_is_valid(gpio)) { + dev_err(dev, "invalid gpio[%d]: %d\n", idx, gpio); + goto free_gpio; + } + + ret = gpio_request(gpio, "spi-bus"); + if (ret) { + dev_err(dev, "gpio [%d] request failed\n", gpio); + goto free_gpio; + } + } + return 0; + +free_gpio: + while (--idx >= 0) + gpio_free(sdd->gpios[idx]); + return -EINVAL; +} + +static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd) +{ + unsigned int idx; + for (idx = 0; idx < 3; idx++) + gpio_free(sdd->gpios[idx]); +} + +static struct __devinit s3c64xx_spi_info * s3c64xx_spi_parse_dt( + struct device *dev) +{ + struct s3c64xx_spi_info *sci; + u32 temp; + + sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); + if (!sci) { + dev_err(dev, "memory allocation for spi_info failed\n"); + return ERR_PTR(-ENOMEM); + } + + if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { + dev_warn(dev, "spi bus clock parent not specified, using " + "clock at index 0 as parent\n"); + sci->src_clk_nr = 0; + } else { + sci->src_clk_nr = temp; + } + + if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { + dev_warn(dev, "number of chip select lines not specified, " + "assuming 1 chip select line\n"); + sci->num_cs = 1; + } else { + sci->num_cs = temp; + } + + return sci; +} +#else +static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) +{ + return dev->platform_data; +} + +static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd) +{ + return -EINVAL; +} + +static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd) +{ +} +#endif + +static const struct of_device_id s3c64xx_spi_dt_match[]; + static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( struct platform_device *pdev) { +#ifdef CONFIG_OF + if (pdev->dev.of_node) { + const struct of_device_id *match; + match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node); + return (struct s3c64xx_spi_port_config *)match->data; + } +#endif return (struct s3c64xx_spi_port_config *) platform_get_device_id(pdev)->driver_data; } static int __init s3c64xx_spi_probe(struct platform_device *pdev) { - struct resource *mem_res, *dmatx_res, *dmarx_res; + struct resource *mem_res; struct s3c64xx_spi_driver_data *sdd; - struct s3c64xx_spi_info *sci; + struct s3c64xx_spi_info *sci = pdev->dev.platform_data; struct spi_master *master; int ret, irq; char clk_name[16]; - if (pdev->id < 0) { - dev_err(&pdev->dev, - "Invalid platform device id-%d\n", pdev->id); - return -ENODEV; + if (!sci && pdev->dev.of_node) { + sci = s3c64xx_spi_parse_dt(&pdev->dev); + if (IS_ERR(sci)) + return PTR_ERR(sci); } - if (pdev->dev.platform_data == NULL) { + if (!sci) { dev_err(&pdev->dev, "platform_data missing!\n"); return -ENODEV; } - sci = pdev->dev.platform_data; - - /* Check for availability of necessary resource */ - - dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0); - if (dmatx_res == NULL) { - dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n"); - return -ENXIO; - } - - dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1); - if (dmarx_res == NULL) { - dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n"); - return -ENXIO; - } - mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (mem_res == NULL) { dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); @@ -1059,14 +1244,29 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) sdd->cntrlr_info = sci; sdd->pdev = pdev; sdd->sfr_start = mem_res->start; - sdd->tx_dma.dmach = dmatx_res->start; - sdd->tx_dma.direction = DMA_MEM_TO_DEV; - sdd->rx_dma.dmach = dmarx_res->start; - sdd->rx_dma.direction = DMA_DEV_TO_MEM; - sdd->port_id = pdev->id; + if (pdev->dev.of_node) { + ret = of_alias_get_id(pdev->dev.of_node, "spi"); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get alias id, " + "errno %d\n", ret); + goto err0; + } + sdd->port_id = ret; + } else { + sdd->port_id = pdev->id; + } sdd->cur_bpw = 8; + ret = s3c64xx_spi_get_dmares(sdd, true); + if (ret) + goto err0; + + ret = s3c64xx_spi_get_dmares(sdd, false); + if (ret) + goto err0; + + master->dev.of_node = pdev->dev.of_node; master->bus_num = sdd->port_id; master->setup = s3c64xx_spi_setup; master->cleanup = s3c64xx_spi_cleanup; @@ -1092,7 +1292,10 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) goto err1; } - if (sci->cfg_gpio == NULL || sci->cfg_gpio()) { + if (!sci->cfg_gpio && pdev->dev.of_node) { + if (s3c64xx_spi_parse_dt_gpio(sdd)) + return -EBUSY; + } else if (sci->cfg_gpio == NULL || sci->cfg_gpio()) { dev_err(&pdev->dev, "Unable to config gpio\n"); ret = -EBUSY; goto err2; @@ -1173,6 +1376,8 @@ err5: err4: clk_put(sdd->clk); err3: + if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node) + s3c64xx_spi_dt_gpio_free(sdd); err2: iounmap((void *) sdd->regs); err1: @@ -1204,6 +1409,9 @@ static int s3c64xx_spi_remove(struct platform_device *pdev) clk_disable(sdd->clk); clk_put(sdd->clk); + if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node) + s3c64xx_spi_dt_gpio_free(sdd); + iounmap((void *) sdd->regs); mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -1228,6 +1436,9 @@ static int s3c64xx_spi_suspend(struct device *dev) clk_disable(sdd->src_clk); clk_disable(sdd->clk); + if (!sdd->cntrlr_info->cfg_gpio && dev->of_node) + s3c64xx_spi_dt_gpio_free(sdd); + sdd->cur_speed = 0; /* Output Clock is stopped */ return 0; @@ -1239,7 +1450,10 @@ static int s3c64xx_spi_resume(struct device *dev) struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); struct s3c64xx_spi_info *sci = sdd->cntrlr_info; - sci->cfg_gpio(); + if (!sci->cfg_gpio && dev->of_node) + s3c64xx_spi_parse_dt_gpio(sdd); + else + sci->cfg_gpio(); /* Enable the clock */ clk_enable(sdd->src_clk); @@ -1347,11 +1561,22 @@ static struct platform_device_id s3c64xx_spi_driver_ids[] = { { }, }; +#ifdef CONFIG_OF +static const struct of_device_id s3c64xx_spi_dt_match[] = { + { .compatible = "samsung,exynos4210-spi", + .data = (void *)&exynos4_spi_port_config, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); +#endif /* CONFIG_OF */ + static struct platform_driver s3c64xx_spi_driver = { .driver = { .name = "s3c64xx-spi", .owner = THIS_MODULE, .pm = &s3c64xx_spi_pm, + .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), }, .remove = s3c64xx_spi_remove, .id_table = s3c64xx_spi_driver_ids, -- cgit v0.10.2 From 4922972ecaca1b2eeb0f7643f97006d2f713d42b Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Fri, 13 Jul 2012 15:25:08 +0900 Subject: ARM: EXYNOS: Add device tree node for EXYNOS4 interrupt combiner controller Add node for EXYNOS4 interrupt combiner controller. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index a1dd2ee..2707f0e 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -33,6 +33,17 @@ reg = <0x10490000 0x1000>, <0x10480000 0x100>; }; + combiner:interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x10440000 0x1000>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; + }; + watchdog@10060000 { compatible = "samsung,s3c2410-wdt"; reg = <0x10060000 0x100>; -- cgit v0.10.2 From 5e1ac7db04f963e230ffa0a39c5df376733f8c0b Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 29 May 2012 14:40:04 +0800 Subject: ARM: ux500: Enable Device Tree support mmci for Snowball Allow proper initialisation for MMC via the mmci driver for the Snowball low-cost development board using DT. At the moment we continue to use DMA setup from platform code. Once the DMA generic DT bindings have been completed we can then port the remainder over to DT. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index ec3c339..68f66f3 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts @@ -101,15 +101,30 @@ }; }; + // External Micro SD slot sdi@80126000 { - status = "enabled"; + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <8>; + mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux3_reg>; + + #gpio-cells = <1>; cd-gpios = <&gpio6 26 0x4>; // 218 + cd-inverted; + + status = "okay"; }; + // On-board eMMC sdi@80114000 { - status = "enabled"; + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <8>; + mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux2_reg>; + + status = "okay"; }; uart@80120000 { diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 920251c..18ff781 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -80,7 +80,7 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = { }; #endif -static struct mmci_platform_data mop500_sdi0_data = { +struct mmci_platform_data mop500_sdi0_data = { .ios_handler = mop500_sdi0_ios_handler, .ocr_mask = MMC_VDD_29_30, .f_max = 50000000, @@ -227,7 +227,7 @@ static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = { }; #endif -static struct mmci_platform_data mop500_sdi4_data = { +struct mmci_platform_data mop500_sdi4_data = { .ocr_mask = MMC_VDD_29_30, .f_max = 50000000, .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 4fd93f5..1bf179e 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -776,6 +776,8 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat), /* Requires DMA bindings. */ OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), + OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), + OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data), /* Requires clock name bindings. */ OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL), OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL), @@ -851,7 +853,6 @@ static void __init u8500_init_machine(void) platform_add_devices(snowball_of_platform_devs, ARRAY_SIZE(snowball_of_platform_devs)); - snowball_sdi_init(parent); } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) { /* * The HREFv60 board removed a GPIO expander and routed diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index 2f87b25..b5bfc1a 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -9,6 +9,7 @@ /* For NOMADIK_NR_GPIO */ #include +#include /* Snowball specific GPIO assignments, this board has no GPIO expander */ #define SNOWBALL_ACCEL_INT1_GPIO 163 @@ -78,6 +79,8 @@ struct device; struct i2c_board_info; +extern struct mmci_platform_data mop500_sdi0_data; +extern struct mmci_platform_data mop500_sdi4_data; extern void mop500_sdi_init(struct device *parent); extern void snowball_sdi_init(struct device *parent); -- cgit v0.10.2 From 98582d9562b4bea6b0eb6e2bfafcd3fab3b60ccb Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 17 Apr 2012 15:52:26 +0100 Subject: ARM: ux500: Remove unused i2c platform_data initialisation code Now that u5500 is obsolete, u8500 is the only user of the Nomadik i2c driver. As such there is no requirement to differentiate between initialisation values. By the time a new SoC is released, almost all of the ux500 platform will be DT:ed, so we can make decisions based on the compatible property instead. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 1bf179e..f4bbe5d 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -331,43 +331,12 @@ static struct i2c_board_info __initdata mop500_i2c2_devices[] = { }, }; -#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, t_out, _sm) \ -static struct nmk_i2c_controller u8500_i2c##id##_data = { \ - /* \ - * slave data setup time, which is \ - * 250 ns,100ns,10ns which is 14,6,2 \ - * respectively for a 48 Mhz \ - * i2c clock \ - */ \ - .slsu = _slsu, \ - /* Tx FIFO threshold */ \ - .tft = _tft, \ - /* Rx FIFO threshold */ \ - .rft = _rft, \ - /* std. mode operation */ \ - .clk_freq = clk, \ - /* Slave response timeout(ms) */\ - .timeout = t_out, \ - .sm = _sm, \ -} - -/* - * The board uses 4 i2c controllers, initialize all of - * them with slave data setup time of 250 ns, - * Tx & Rx FIFO threshold values as 8 and standard - * mode of operation - */ -U8500_I2C_CONTROLLER(0, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); -U8500_I2C_CONTROLLER(1, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); -U8500_I2C_CONTROLLER(2, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); -U8500_I2C_CONTROLLER(3, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); - static void __init mop500_i2c_init(struct device *parent) { - db8500_add_i2c0(parent, &u8500_i2c0_data); - db8500_add_i2c1(parent, &u8500_i2c1_data); - db8500_add_i2c2(parent, &u8500_i2c2_data); - db8500_add_i2c3(parent, &u8500_i2c3_data); + db8500_add_i2c0(parent, NULL); + db8500_add_i2c1(parent, NULL); + db8500_add_i2c2(parent, NULL); + db8500_add_i2c3(parent, NULL); } static struct gpio_keys_button mop500_gpio_keys[] = { diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c index 5267ab9..a92440d 100644 --- a/drivers/i2c/busses/i2c-nomadik.c +++ b/drivers/i2c/busses/i2c-nomadik.c @@ -965,8 +965,7 @@ static int __devinit nmk_i2c_probe(struct platform_device *pdev) adap->owner = THIS_MODULE; adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; adap->algo = &nmk_i2c_algo; - adap->timeout = pdata->timeout ? msecs_to_jiffies(pdata->timeout) : - msecs_to_jiffies(20000); + adap->timeout = msecs_to_jiffies(pdata->timeout); snprintf(adap->name, sizeof(adap->name), "Nomadik I2C%d at %lx", pdev->id, (unsigned long)res->start); -- cgit v0.10.2 From 079c61e120bf88ee04b65a2150b060e9f986cfb9 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 17 Apr 2012 16:11:02 +0100 Subject: ARM: ux500: Provide auxdata to be used as name base clock search for nmk-i2c This patch provides a way for find_clk() to complete its name-based searches and still find the nmk-i2c clocks. As Device Tree has a different naming structure to that of more traditional initialisation methods, find_clk() not succeed without these bindings. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index f4bbe5d..2130fae 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -757,6 +757,11 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL), OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL), OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), /* Requires device name bindings. */ OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL), {}, @@ -843,7 +848,6 @@ static void __init u8500_init_machine(void) mop500_uib_init(); } - mop500_i2c_init(parent); /* This board has full regulator constraints */ regulator_has_full_constraints(); -- cgit v0.10.2 From 8733f53c67544ccf358437cc8bb5a175c351ceba Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 17 May 2012 10:40:39 +0100 Subject: ARM: ux500: Kconfig: Compile in leds-gpio support for Snowball Code exists in the mop500 board file (used for HREF and Snowball) to initialise Snowball's user LED via the leds-gpio driver. However, the driver isn't currently built when using the current configuration. This patch aims to change that behavior. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 53d3d46..c013bbf 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -41,6 +41,7 @@ config MACH_HREFV60 config MACH_SNOWBALL bool "U8500 Snowball platform" select MACH_MOP500 + select LEDS_GPIO help Include support for the snowball development platform. -- cgit v0.10.2 From 7fd975fabe65ee8cc1d53811c9aa607e95def406 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 15 Jun 2012 09:30:30 +0100 Subject: ARM: ux500: Enable the user LED on Snowball via Device Tree This patch enables and illuminates the user_led on the Snowball low-cost development board using DT. It also removes initialisation carried out from platform code. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index 68f66f3..aefcb7f 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts @@ -77,6 +77,7 @@ used-led { label = "user_led"; gpios = <&gpio4 14 0x4>; + default-state = "on"; }; }; diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 2130fae..e4e63c7 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -819,7 +819,7 @@ static void __init u8500_init_machine(void) } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { /* * Devices to be DT:ed: - * snowball_led_dev = todo + * snowball_led_dev = done * snowball_key_dev = todo * snowball_sbnet_dev = done * ab8500_device = done -- cgit v0.10.2 From 4eda912908935946ba64e71cb3f5909843a1a566 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 28 May 2012 16:59:26 +0800 Subject: ARM: ux500: Add a ab8500-gpadc node to the db8500 Device Tree This patch provides support for the ab8500-gpadc driver. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index 4ad5160..84032d1 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi @@ -313,6 +313,14 @@ reg = <5>; /* mailbox 5 is i2c */ interrupts = <0 40 0x4>; + ab8500-gpadc { + compatible = "stericsson,ab8500-gpadc"; + interrupts = <0 32 0x4 + 0 39 0x4>; + interrupt-names = "HW_CONV_END", "SW_CONV_END"; + vddadc-supply = <&ab8500_ldo_tvout_reg>; + }; + ab8500-regulators { compatible = "stericsson,ab8500-regulator"; -- cgit v0.10.2 From 12cb7bd48f4fc89bbe31ee2cbac135131a6fb499 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 2 May 2012 08:45:40 +0100 Subject: ARM: ux500: Add support for input/ponkey into the db8500's Device Tree Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index 84032d1..8c494d3 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi @@ -321,6 +321,13 @@ vddadc-supply = <&ab8500_ldo_tvout_reg>; }; + ab8500-ponkey { + compatible = "stericsson,ab8500-ponkey"; + interrupts = <0 6 0x4 + 0 7 0x4>; + interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; + }; + ab8500-regulators { compatible = "stericsson,ab8500-regulator"; -- cgit v0.10.2 From c525f07110c08b4a0c8ed4182d86101d4d023cc0 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 2 May 2012 09:20:37 +0100 Subject: ARM: ux500: Enable LED heartbeat functionality on Snowball This patch configures the user LED on Snowball to double flash every second or so, whilst it's still alive. This can give key indications as to what the board is doing in the case of no console output. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index e4e63c7..9ba9528 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -58,7 +58,7 @@ static struct gpio_led snowball_led_array[] = { { .name = "user_led", - .default_trigger = "none", + .default_trigger = "heartbeat", .gpio = 142, }, }; -- cgit v0.10.2 From fd53d04280672c17540d958b472c0b5b444a06c3 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 2 May 2012 09:48:38 +0100 Subject: ARM: ux500: Enable LED heartbeat functionality on Snowbal via DT This patch configures the user LED on Snowball to double flash every second or so, whilst it's still alive. This can give key indications as to what the board is doing in the case of no console output. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index aefcb7f..7e334d4 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts @@ -78,6 +78,7 @@ label = "user_led"; gpios = <&gpio4 14 0x4>; default-state = "on"; + linux,default-trigger = "heartbeat"; }; }; -- cgit v0.10.2 From 401cd1b851ace22a8a3a94916abec462f4d0fe28 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 3 May 2012 12:53:55 +0100 Subject: ARM: ux500: Add db8500 Device Tree node for ab8500-sysctrl This adds the DT node for the mfd/ab8500-sysctrl driver. It will allow probing of the driver during a Device Tree enabled boot. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index 8c494d3..7a9ad15 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi @@ -328,6 +328,10 @@ interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; }; + ab8500-sysctrl { + compatible = "stericsson,ab8500-sysctrl"; + }; + ab8500-regulators { compatible = "stericsson,ab8500-regulator"; -- cgit v0.10.2 From 78451de7475be601cff4f283f95122a1ca61de16 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 3 May 2012 13:03:59 +0100 Subject: ARM: ux500: Add db8500 Device Tree node for misc/ab8500-pwm This adds the DT node for the misc/ab8500-pwm driver. It will allow probing of the driver during a Device Tree enabled boot. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index 7a9ad15..185f8d4 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi @@ -332,6 +332,10 @@ compatible = "stericsson,ab8500-sysctrl"; }; + ab8500-pwm { + compatible = "stericsson,ab8500-pwm"; + }; + ab8500-regulators { compatible = "stericsson,ab8500-regulator"; -- cgit v0.10.2 From ee189cefa8aaa3db3d65fc330aaf324820c0a623 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 3 May 2012 14:40:24 +0100 Subject: ARM: ux500: Add a ab8500-usb Device Tree node for db8500 based devices Here we specify each of the ab8500 USB driver's seven IRQs, which the driver references by name. We also apply regulator support for the three used by the device. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index 185f8d4..40d8244 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi @@ -321,6 +321,27 @@ vddadc-supply = <&ab8500_ldo_tvout_reg>; }; + ab8500-usb { + compatible = "stericsson,ab8500-usb"; + interrupts = < 0 90 0x4 + 0 96 0x4 + 0 14 0x4 + 0 15 0x4 + 0 79 0x4 + 0 74 0x4 + 0 75 0x4>; + interrupt-names = "ID_WAKEUP_R", + "ID_WAKEUP_F", + "VBUS_DET_F", + "VBUS_DET_R", + "USB_LINK_STATUS", + "USB_ADP_PROBE_PLUG", + "USB_ADP_PROBE_UNPLUG"; + vddulpivio18-supply = <&ab8500_ldo_initcore_reg>; + v-ape-supply = <&db8500_vape_reg>; + musb_1v8-supply = <&db8500_vsmps2_reg>; + }; + ab8500-ponkey { compatible = "stericsson,ab8500-ponkey"; interrupts = <0 6 0x4 -- cgit v0.10.2 From 215891eca1c17aceb4cd8d598659fa86f0f33f8d Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 1 May 2012 16:11:19 +0100 Subject: ARM: ux500: Apply ab8500-debug node do the db8500 DT structure This node has no properties. It merely allows probing of the ab8500-debugfs driver during Device Tree initialisation. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index 40d8244..9669e72 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi @@ -357,6 +357,10 @@ compatible = "stericsson,ab8500-pwm"; }; + ab8500-debugfs { + compatible = "stericsson,ab8500-debug"; + }; + ab8500-regulators { compatible = "stericsson,ab8500-regulator"; -- cgit v0.10.2 From 732973c87fa48011d7f86230691686d53bf22548 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 29 May 2012 10:49:33 +0800 Subject: ARM: ux500: Correctly reference IRQs supplied by the AB8500 from Device Tree The AB8500 driver has now been provided with IRQ domain support. This means we can request IRQs from any of it's uses via Device Tree. This patch advertises the AB8500 as an Interrupt Controller and provides the correct calls in the format the driver expects. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index 9669e72..d698bd8 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi @@ -312,24 +312,26 @@ compatible = "stericsson,ab8500"; reg = <5>; /* mailbox 5 is i2c */ interrupts = <0 40 0x4>; + interrupt-controller; + #interrupt-cells = <2>; ab8500-gpadc { compatible = "stericsson,ab8500-gpadc"; - interrupts = <0 32 0x4 - 0 39 0x4>; + interrupts = <32 0x4 + 39 0x4>; interrupt-names = "HW_CONV_END", "SW_CONV_END"; vddadc-supply = <&ab8500_ldo_tvout_reg>; }; ab8500-usb { compatible = "stericsson,ab8500-usb"; - interrupts = < 0 90 0x4 - 0 96 0x4 - 0 14 0x4 - 0 15 0x4 - 0 79 0x4 - 0 74 0x4 - 0 75 0x4>; + interrupts = < 90 0x4 + 96 0x4 + 14 0x4 + 15 0x4 + 79 0x4 + 74 0x4 + 75 0x4>; interrupt-names = "ID_WAKEUP_R", "ID_WAKEUP_F", "VBUS_DET_F", @@ -344,8 +346,8 @@ ab8500-ponkey { compatible = "stericsson,ab8500-ponkey"; - interrupts = <0 6 0x4 - 0 7 0x4>; + interrupts = <6 0x4 + 7 0x4>; interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; }; -- cgit v0.10.2 From d4b29ac1893e342f27fe79bd37641918e3364699 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Sat, 26 May 2012 07:03:48 +0100 Subject: ARM: ux500: Enable the AB8500 RTC for all DT:ed DB8500 based devices Here we add a node for the AB8500 Real Time Clock in all devices supporting the DB8500. The AB8500 RTC driver makes use of named interrupts we provide support for this too. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index d698bd8..1b7f795 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi @@ -315,6 +315,13 @@ interrupt-controller; #interrupt-cells = <2>; + ab8500-rtc { + compatible = "stericsson,ab8500-rtc"; + interrupts = <17 0x4 + 18 0x4>; + interrupt-names = "60S", "ALARM"; + }; + ab8500-gpadc { compatible = "stericsson,ab8500-gpadc"; interrupts = <32 0x4 -- cgit v0.10.2 From ddb3b99c532930c9f891e97af5ef4e6691076c16 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Sat, 26 May 2012 07:01:31 +0100 Subject: ARM: ux500: Move rtc-pl031 registration to Device Tree when enabled During a Device Tree boot, all probing will now be completed on parse of the Device Tree binary. In the same patch we remove platform registration of the Real Time Clock. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index 1b7f795..f1dc98d 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi @@ -48,7 +48,7 @@ }; rtc@80154000 { - compatible = "stericsson,db8500-rtc"; + compatible = "arm,rtc-pl031", "arm,primecell"; reg = <0x80154000 0x1000>; interrupts = <0 18 0x4>; }; diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 33275eb..a12bd9e 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -237,7 +237,6 @@ struct device * __init u8500_of_init_devices(void) parent = db8500_soc_device_init(); - db8500_add_rtc(parent); db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); platform_device_register_data(parent, -- cgit v0.10.2 From 612e1d5f1c192996889038598fb82ea03fb01573 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 14 Jun 2012 11:27:56 +0100 Subject: pinctrl: pinctrl-nomadik: Append sleepmode property with vendor specific prefixes Any non-standard property should contain the vendor's identifier which should be perpended onto the property name followed by a comma. This aids in name-space collision prevention. This patch ensures the sleepmode property adheres to the rules. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/Documentation/devicetree/bindings/gpio/gpio-nmk.txt b/Documentation/devicetree/bindings/gpio/gpio-nmk.txt index ee87467..8315ac7 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-nmk.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-nmk.txt @@ -26,6 +26,6 @@ Example: #gpio-cells = <2>; gpio-controller; interrupt-controller; - supports-sleepmode; + st,supports-sleepmode; gpio-bank = <1>; }; diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c index 3e7e47d..dd9e6f2 100644 --- a/drivers/pinctrl/pinctrl-nomadik.c +++ b/drivers/pinctrl/pinctrl-nomadik.c @@ -1198,7 +1198,7 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev) if (!pdata) return -ENOMEM; - if (of_get_property(np, "supports-sleepmode", NULL)) + if (of_get_property(np, "st,supports-sleepmode", NULL)) pdata->supports_sleepmode = true; if (of_property_read_u32(np, "gpio-bank", &dev->id)) { -- cgit v0.10.2 From 61be4981f4c216fb78a133827b04540cdff7afd6 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 14 Jun 2012 11:16:03 +0100 Subject: ARM: ux500: Ensure vendor specific properties have the vendor's identifier Any non-standard property should contain the vendor's identifier which should be perpended onto the property name followed by a comma. This aids in name-space collision prevention. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index f1dc98d..e9c2e92 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi @@ -60,7 +60,7 @@ interrupts = <0 119 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <0>; @@ -73,7 +73,7 @@ interrupts = <0 120 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <1>; @@ -86,7 +86,7 @@ interrupts = <0 121 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <2>; @@ -99,7 +99,7 @@ interrupts = <0 122 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <3>; @@ -112,7 +112,7 @@ interrupts = <0 123 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <4>; @@ -125,7 +125,7 @@ interrupts = <0 124 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <5>; @@ -138,7 +138,7 @@ interrupts = <0 125 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <6>; @@ -151,7 +151,7 @@ interrupts = <0 126 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <7>; @@ -164,7 +164,7 @@ interrupts = <0 127 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <8>; -- cgit v0.10.2 From fc67a597a25684084c539a369c09684bf3c0d88e Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 15 Jun 2012 10:46:49 +0100 Subject: ARM: ux500: Remove temporary snowball_of_platform_devs enablement structure All Device Tree enablement for Snowball's Platform devices; LEDs, Keys, Ethernet and all associated AB8500 Multi-Functional Devices are now complete, so here we remove any trace of adding those devices when Device Tree is enabled. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 9ba9528..84461fa 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -796,8 +796,6 @@ static void __init u8500_init_machine(void) for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) mop500_platform_devs[i]->dev.parent = parent; - for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++) - snowball_platform_devs[i]->dev.parent = parent; /* automatically probe child nodes of db8500 device */ of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent); @@ -816,17 +814,6 @@ static void __init u8500_init_machine(void) mop500_uib_init(); - } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { - /* - * Devices to be DT:ed: - * snowball_led_dev = done - * snowball_key_dev = todo - * snowball_sbnet_dev = done - * ab8500_device = done - */ - platform_add_devices(snowball_of_platform_devs, - ARRAY_SIZE(snowball_of_platform_devs)); - } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) { /* * The HREFv60 board removed a GPIO expander and routed -- cgit v0.10.2 From da38487000de965bb94b8f4bca88eade4bb9a485 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 15 Jun 2012 17:37:44 +0100 Subject: ARM: ux500: Remove PMU platform registration when booting with DT PMU registration is successfully completed by Device Tree now, so there is no longer a requirement to register it from platform code. This patch removes platform registration during a DT boot. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index a12bd9e..c8dd94f 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -139,7 +139,6 @@ static struct platform_device *platform_devs[] __initdata = { static struct platform_device *of_platform_devs[] __initdata = { &u8500_dma40_device, - &db8500_pmu_device, }; static resource_size_t __initdata db8500_gpio_base[] = { @@ -248,7 +247,7 @@ struct device * __init u8500_of_init_devices(void) /* * Devices to be DT:ed: * u8500_dma40_device = todo - * db8500_pmu_device = todo + * db8500_pmu_device = done * db8500_prcmu_device = done */ platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs)); -- cgit v0.10.2 From 46fda15c0c21493a9305db0a05e08f072d6409e4 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Sat, 14 Jul 2012 10:53:08 +0900 Subject: ARM: EXYNOS: Fix the incorrect hierarchy of spi controller bus clock The sclk_spi clock is derived currently from the first level divider (MMCx_RATIO) which is incorrect. The output of the first level clock is divided by a second level divider (MMCx_PRE_RATIO), the output of which is used as the spi bus clock (sclk_spi). Fix the clock hierarchy issues for the sclk_spi clock. Signed-off-by: Thomas Abraham Acked-by: Jaswinder Singh [kgene.kim@samsung.com: changed the name of clk for consensus] Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index 10a46a9..26fe9de 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -1242,40 +1242,67 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = { .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 }, }; +static struct clksrc_clk exynos4_clk_mdout_spi0 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.0", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_mdout_spi1 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.1", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_mdout_spi2 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.2", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, +}; + static struct clksrc_clk exynos4_clk_sclk_spi0 = { .clk = { .name = "sclk_spi", .devname = "exynos4210-spi.0", + .parent = &exynos4_clk_mdout_spi0.clk, .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 16), }, - .sources = &exynos4_clkset_group, - .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, - .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 }, }; static struct clksrc_clk exynos4_clk_sclk_spi1 = { .clk = { .name = "sclk_spi", .devname = "exynos4210-spi.1", + .parent = &exynos4_clk_mdout_spi1.clk, .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 20), }, - .sources = &exynos4_clkset_group, - .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, - .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 }, }; static struct clksrc_clk exynos4_clk_sclk_spi2 = { .clk = { .name = "sclk_spi", .devname = "exynos4210-spi.2", + .parent = &exynos4_clk_mdout_spi2.clk, .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 24), }, - .sources = &exynos4_clkset_group, - .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, - .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 }, }; /* Clock initialization code */ @@ -1331,7 +1358,9 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = { &exynos4_clk_sclk_spi0, &exynos4_clk_sclk_spi1, &exynos4_clk_sclk_spi2, - + &exynos4_clk_mdout_spi0, + &exynos4_clk_mdout_spi1, + &exynos4_clk_mdout_spi2, }; static struct clk_lookup exynos4_clk_lookup[] = { -- cgit v0.10.2 From d40af3652bc91f3c25ce4c13b2ee1751c3e742f3 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Sat, 14 Jul 2012 10:54:26 +0900 Subject: ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOX4 Add the platform bits which are required to support SPI controllers. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index 7a4b478..35bced6 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h @@ -195,6 +195,10 @@ #define IRQ_IIC6 EXYNOS4_IRQ_IIC6 #define IRQ_IIC7 EXYNOS4_IRQ_IIC7 +#define IRQ_SPI0 EXYNOS4_IRQ_SPI0 +#define IRQ_SPI1 EXYNOS4_IRQ_SPI1 +#define IRQ_SPI2 EXYNOS4_IRQ_SPI2 + #define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST #define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c index e7e9743..b2b5d5f 100644 --- a/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -55,6 +55,12 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = { "exynos4-sdhci.3", NULL), OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0), "s3c2440-i2c.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0, + "exynos4210-spi.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1, + "exynos4210-spi.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2, + "exynos4210-spi.2", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL), {}, -- cgit v0.10.2 From 4980c39ba182929b4582f95cfaffc1d584f7154e Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Sat, 14 Jul 2012 10:45:32 +0900 Subject: ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS4 platforms Add device nodes for the three instances of spi controllers in EXYNOS4 platforms. Enable instance SPI 2 for SMDKV310 board and disable all spi instances for Origen board. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index b8c4763..0c49caa 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -134,4 +134,16 @@ i2c@138D0000 { status = "disabled"; }; + + spi_0: spi@13920000 { + status = "disabled"; + }; + + spi_1: spi@13930000 { + status = "disabled"; + }; + + spi_2: spi@13940000 { + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 27afc8e..1beccc8 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -179,4 +179,42 @@ i2c@138D0000 { status = "disabled"; }; + + spi_0: spi@13920000 { + status = "disabled"; + }; + + spi_1: spi@13930000 { + status = "disabled"; + }; + + spi_2: spi@13940000 { + gpios = <&gpc1 1 5 3 0>, + <&gpc1 3 5 3 0>, + <&gpc1 4 5 3 0>; + + w25x80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25x80"; + reg = <0>; + spi-max-frequency = <1000000>; + + controller-data { + cs-gpio = <&gpc1 2 1 0 3>; + samsung,spi-feedback-delay = <0>; + }; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "Kernel"; + reg = <0x40000 0xc0000>; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 2707f0e..6904d9d 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -25,6 +25,12 @@ compatible = "samsung,exynos4210"; interrupt-parent = <&gic>; + aliases { + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + }; + gic:interrupt-controller@10490000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -158,6 +164,36 @@ interrupts = <0 65 0>; }; + spi_0: spi@13920000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13920000 0x100>; + interrupts = <0 66 0>; + tx-dma-channel = <&pdma0 7>; + rx-dma-channel = <&pdma0 6>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi_1: spi@13930000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13930000 0x100>; + interrupts = <0 67 0>; + tx-dma-channel = <&pdma1 7>; + rx-dma-channel = <&pdma1 6>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi_2: spi@13940000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13940000 0x100>; + interrupts = <0 68 0>; + tx-dma-channel = <&pdma0 9>; + rx-dma-channel = <&pdma0 8>; + #address-cells = <1>; + #size-cells = <0>; + }; + amba { #address-cells = <1>; #size-cells = <1>; -- cgit v0.10.2 From ea5a9ce6aec67cc30ca43d6d2a0dd83f9291598c Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Sat, 14 Jul 2012 10:53:13 +0900 Subject: ARM: EXYNOS: Add spi clock support for EXYNOS5 Add support for clock instances for each spi controller. Signed-off-by: Thomas Abraham Acked-by: Jaswinder Singh [kgene.kim@samsung.com: changed the name of clk for consensus] Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index fefa336..774533c 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -131,6 +131,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable) return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable); } +static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable); +} + static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable); @@ -741,6 +746,24 @@ static struct clk exynos5_init_clocks_off[] = { .enable = exynos5_clk_ip_peric_ctrl, .ctrlbit = (1 << 14), }, { + .name = "spi", + .devname = "exynos4210-spi.0", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 16), + }, { + .name = "spi", + .devname = "exynos4210-spi.1", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 17), + }, { + .name = "spi", + .devname = "exynos4210-spi.2", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 18), + }, { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0), .enable = &exynos5_clk_ip_mfc_ctrl, @@ -1034,6 +1057,69 @@ static struct clksrc_clk exynos5_clk_sclk_mmc3 = { .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 }, }; +static struct clksrc_clk exynos5_clk_mdout_spi0 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.0", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_mdout_spi1 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.1", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_mdout_spi2 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.2", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_spi0 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.0", + .parent = &exynos5_clk_mdout_spi0.clk, + .enable = exynos5_clksrc_mask_peric1_ctrl, + .ctrlbit = (1 << 16), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_spi1 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.1", + .parent = &exynos5_clk_mdout_spi1.clk, + .enable = exynos5_clksrc_mask_peric1_ctrl, + .ctrlbit = (1 << 20), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_spi2 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.2", + .parent = &exynos5_clk_mdout_spi2.clk, + .enable = exynos5_clksrc_mask_peric1_ctrl, + .ctrlbit = (1 << 24), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 }, +}; + static struct clksrc_clk exynos5_clksrcs[] = { { .clk = { @@ -1148,6 +1234,12 @@ static struct clksrc_clk *exynos5_sysclks[] = { &exynos5_clk_dout_mmc4, &exynos5_clk_aclk_acp, &exynos5_clk_pclk_acp, + &exynos5_clk_sclk_spi0, + &exynos5_clk_sclk_spi1, + &exynos5_clk_sclk_spi2, + &exynos5_clk_mdout_spi0, + &exynos5_clk_mdout_spi1, + &exynos5_clk_mdout_spi2, }; static struct clk *exynos5_clk_cdev[] = { @@ -1176,6 +1268,9 @@ static struct clk_lookup exynos5_clk_lookup[] = { CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), + CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk), + CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk), + CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), -- cgit v0.10.2 From b0b27815c752714e74cce5fc53c4e14797d12214 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Sat, 14 Jul 2012 10:54:31 +0900 Subject: ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOS5 Add the platform bits which are required to support SPI controllers. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index ca4aa89..c72b675 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -154,6 +154,9 @@ #define EXYNOS4_PA_SPI0 0x13920000 #define EXYNOS4_PA_SPI1 0x13930000 #define EXYNOS4_PA_SPI2 0x13940000 +#define EXYNOS5_PA_SPI0 0x12D20000 +#define EXYNOS5_PA_SPI1 0x12D30000 +#define EXYNOS5_PA_SPI2 0x12D40000 #define EXYNOS4_PA_GPIO1 0x11400000 #define EXYNOS4_PA_GPIO2 0x11000000 diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 7b1e11a..ef770bc 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -47,6 +47,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { "s3c2440-i2c.0", NULL), OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1), "s3c2440-i2c.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0, + "exynos4210-spi.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1, + "exynos4210-spi.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2, + "exynos4210-spi.2", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), -- cgit v0.10.2 From 79989ba3e201f3bf992e600a0745ecaf256f08f5 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Sat, 14 Jul 2012 10:45:36 +0900 Subject: ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS5 platforms Add device nodes for the three instances of spi controllers in EXYNOS5 platforms and enable instance SPI 1 for SMDK5250 board. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 49945cc..8a5e348 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -71,4 +71,42 @@ i2c@12CD0000 { status = "disabled"; }; + + spi_0: spi@12d20000 { + status = "disabled"; + }; + + spi_1: spi@12d30000 { + gpios = <&gpa2 4 2 3 0>, + <&gpa2 6 2 3 0>, + <&gpa2 7 2 3 0>; + + w25q80bw@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25x80"; + reg = <0>; + spi-max-frequency = <1000000>; + + controller-data { + cs-gpio = <&gpa2 5 1 0 3>; + samsung,spi-feedback-delay = <0>; + }; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "Kernel"; + reg = <0x40000 0xc0000>; + }; + }; + }; + + spi_2: spi@12d40000 { + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 4272b29..a3a2eb2 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -23,6 +23,12 @@ compatible = "samsung,exynos5250"; interrupt-parent = <&gic>; + aliases { + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + }; + gic:interrupt-controller@10481000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -146,6 +152,36 @@ #size-cells = <0>; }; + spi_0: spi@12d20000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d20000 0x100>; + interrupts = <0 66 0>; + tx-dma-channel = <&pdma0 5>; + rx-dma-channel = <&pdma0 4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi_1: spi@12d30000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d30000 0x100>; + interrupts = <0 67 0>; + tx-dma-channel = <&pdma1 5>; + rx-dma-channel = <&pdma1 4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi_2: spi@12d40000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d40000 0x100>; + interrupts = <0 68 0>; + tx-dma-channel = <&pdma0 7>; + rx-dma-channel = <&pdma0 6>; + #address-cells = <1>; + #size-cells = <0>; + }; + amba { #address-cells = <1>; #size-cells = <1>; -- cgit v0.10.2 From 5d74c8a065abc8ae283a6fe8a1e7dd6313a22165 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 17 Jul 2012 23:13:06 +0200 Subject: ARM: EXYNOS: mark the DMA channel binding for SPI as preliminary Bindings for DMA channels are still under discussion and will change once this has been resolved. Therefore we mark them the newly added ones as preliminary. Let's hope nobody starts relying on them... Signed-off-by: Arnd Bergmann diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt index 59bfc4f..a15ffed 100644 --- a/Documentation/devicetree/bindings/spi/spi-samsung.txt +++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt @@ -18,6 +18,9 @@ Required SoC Specific Properties: - interrupts: The interrupt number to the cpu. The interrupt specifier format depends on the interrupt controller. +[PRELIMINARY: the dma channel allocation will change once there are +official DMA bindings] + - tx-dma-channel: The dma channel specifier for tx operations. The format of the dma specifier depends on the dma controller. diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 6904d9d..02891fe 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -168,8 +168,8 @@ compatible = "samsung,exynos4210-spi"; reg = <0x13920000 0x100>; interrupts = <0 66 0>; - tx-dma-channel = <&pdma0 7>; - rx-dma-channel = <&pdma0 6>; + tx-dma-channel = <&pdma0 7>; /* preliminary */ + rx-dma-channel = <&pdma0 6>; /* preliminary */ #address-cells = <1>; #size-cells = <0>; }; @@ -178,8 +178,8 @@ compatible = "samsung,exynos4210-spi"; reg = <0x13930000 0x100>; interrupts = <0 67 0>; - tx-dma-channel = <&pdma1 7>; - rx-dma-channel = <&pdma1 6>; + tx-dma-channel = <&pdma1 7>; /* preliminary */ + rx-dma-channel = <&pdma1 6>; /* preliminary */ #address-cells = <1>; #size-cells = <0>; }; @@ -188,8 +188,8 @@ compatible = "samsung,exynos4210-spi"; reg = <0x13940000 0x100>; interrupts = <0 68 0>; - tx-dma-channel = <&pdma0 9>; - rx-dma-channel = <&pdma0 8>; + tx-dma-channel = <&pdma0 9>; /* preliminary */ + rx-dma-channel = <&pdma0 8>; /* preliminary */ #address-cells = <1>; #size-cells = <0>; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index a3a2eb2..004aaa8 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -156,8 +156,8 @@ compatible = "samsung,exynos4210-spi"; reg = <0x12d20000 0x100>; interrupts = <0 66 0>; - tx-dma-channel = <&pdma0 5>; - rx-dma-channel = <&pdma0 4>; + tx-dma-channel = <&pdma0 5>; /* preliminary */ + rx-dma-channel = <&pdma0 4>; /* preliminary */ #address-cells = <1>; #size-cells = <0>; }; @@ -166,8 +166,8 @@ compatible = "samsung,exynos4210-spi"; reg = <0x12d30000 0x100>; interrupts = <0 67 0>; - tx-dma-channel = <&pdma1 5>; - rx-dma-channel = <&pdma1 4>; + tx-dma-channel = <&pdma1 5>; /* preliminary */ + rx-dma-channel = <&pdma1 4>; /* preliminary */ #address-cells = <1>; #size-cells = <0>; }; @@ -176,8 +176,8 @@ compatible = "samsung,exynos4210-spi"; reg = <0x12d40000 0x100>; interrupts = <0 68 0>; - tx-dma-channel = <&pdma0 7>; - rx-dma-channel = <&pdma0 6>; + tx-dma-channel = <&pdma0 7>; /* preliminary */ + rx-dma-channel = <&pdma0 6>; /* preliminary */ #address-cells = <1>; #size-cells = <0>; }; -- cgit v0.10.2 From de639854441af37fc88a72daab5842045d518944 Mon Sep 17 00:00:00 2001 From: Alexandre Pereira da Silva Date: Fri, 20 Jul 2012 13:33:09 +0200 Subject: ARM: LPC32xx: Add PWM to base dts file Signed-off-by: Alexandre Pereira da Silva Signed-off-by: Roland Stigge diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index c5f37fb..e5ffe96 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -278,6 +278,11 @@ status = "disabled"; }; + pwm: pwm@4005C000 { + compatible = "nxp,lpc3220-pwm"; + reg = <0x4005C000 0x8>; + status = "disabled"; + }; }; }; }; -- cgit v0.10.2