From d75de08727018659cd7e060cf0018eaf53e49aaf Mon Sep 17 00:00:00 2001 From: Maxime Bizon Date: Fri, 27 Mar 2009 18:42:19 +0100 Subject: [ARM] Kirkwood: invalidate L2 cache before enabling it I get random oopses on my Kirkwood board at startup when L2 cache is enabled. FYI I'm using Marvell uboot version 3.4.16 Each boot produces the same oops, but anything that changes the kernel size (even only changing initramfs) makes the oops different. I noticed that nothing invalidates the L2 cache before enabling it, doing so fixes my problem. Signed-off-by: Maxime Bizon Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c index d6dd838..1afed50 100644 --- a/arch/arm/mm/cache-feroceon-l2.c +++ b/arch/arm/mm/cache-feroceon-l2.c @@ -115,6 +115,10 @@ static inline void l2_inv_pa_range(unsigned long start, unsigned long end) raw_local_irq_restore(flags); } +static inline void l2_inv_all(void) +{ + __asm__("mcr p15, 1, %0, c15, c11, 0" : : "r" (0)); +} /* * Linux primitives. @@ -321,6 +325,7 @@ static void __init enable_l2(void) d = flush_and_disable_dcache(); i = invalidate_and_disable_icache(); + l2_inv_all(); write_extra_features(u | 0x00400000); if (i) enable_icache(); -- cgit v0.10.2 From f000328ac10f23f4841b83ddc60eceb3ba0ac176 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Fri, 27 Mar 2009 14:22:26 -0400 Subject: [ARM] Kirkwood: small L2 code cleanup Strictly speaking, a MCR instruction does not produce any output. Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c index 1afed50..6e77c04 100644 --- a/arch/arm/mm/cache-feroceon-l2.c +++ b/arch/arm/mm/cache-feroceon-l2.c @@ -258,9 +258,7 @@ static void __init enable_dcache(void) static void __init __invalidate_icache(void) { - int dummy; - - __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : "=r" (dummy)); + __asm__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); } static int __init invalidate_and_disable_icache(void) -- cgit v0.10.2