From c362aecdb51ecb364d427a9b947fd2dfbd4cb86a Mon Sep 17 00:00:00 2001
From: Ben Dooks <ben-linux@fluff.org>
Date: Wed, 6 Jun 2007 09:51:51 +0100
Subject: [ARM] 4442/1: OSIRIS: Fix CPLD register definitions

Fix the CPLD register definitions to correctly mirror the
documentation

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 4d6c7a5..4525bb0 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -65,6 +65,11 @@ static struct map_desc osiris_iodesc[] __initdata = {
   /* CPLD control registers */
 
   {
+	  .virtual	= (u32)OSIRIS_VA_CTRL0,
+	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL0),
+	  .length	= SZ_16K,
+	  .type		= MT_DEVICE,
+  }, {
 	  .virtual	= (u32)OSIRIS_VA_CTRL1,
 	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL1),
 	  .length	= SZ_16K,
@@ -74,6 +79,11 @@ static struct map_desc osiris_iodesc[] __initdata = {
 	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL2),
 	  .length	= SZ_16K,
 	  .type		= MT_DEVICE,
+  }, {
+	  .virtual	= (u32)OSIRIS_VA_IDREG,
+	  .pfn		= __phys_to_pfn(OSIRIS_PA_IDREG),
+	  .length	= SZ_16K,
+	  .type		= MT_DEVICE,
   },
 };
 
@@ -195,13 +205,13 @@ static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
 	pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
 		 slot, set, set->nr_map);
 
-	tmp = __raw_readb(OSIRIS_VA_CTRL1);
-	tmp &= ~OSIRIS_CTRL1_NANDSEL;
+	tmp = __raw_readb(OSIRIS_VA_CTRL0);
+	tmp &= ~OSIRIS_CTRL0_NANDSEL;
 	tmp |= slot;
 
-	pr_debug("osiris_nand: ctrl1 now %02x\n", tmp);
+	pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
 
-	__raw_writeb(tmp, OSIRIS_VA_CTRL1);
+	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
 }
 
 static struct s3c2410_platform_nand osiris_nand_info = {
diff --git a/include/asm-arm/arch-s3c2410/osiris-cpld.h b/include/asm-arm/arch-s3c2410/osiris-cpld.h
index 3b64984..a3253e9 100644
--- a/include/asm-arm/arch-s3c2410/osiris-cpld.h
+++ b/include/asm-arm/arch-s3c2410/osiris-cpld.h
@@ -14,12 +14,14 @@
 #ifndef __ASM_ARCH_OSIRISCPLD_H
 #define __ASM_ARCH_OSIRISCPLD_H
 
-/* CTRL1 - NAND WP control */
+/* CTRL0 - NAND WP control */
 
-#define OSIRIS_CTRL1_NANDSEL		(0x3)
-#define OSIRIS_CTRL1_BOOT_INT		(1<<3)
-#define OSIRIS_CTRL1_PCMCIA		(1<<4)
-#define OSIRIS_CTRL1_PCMCIA_nWAIT	(1<<6)
-#define OSIRIS_CTRL1_PCMCIA_nIOIS16	(1<<7)
+#define OSIRIS_CTRL0_NANDSEL		(0x3)
+#define OSIRIS_CTRL0_BOOT_INT		(1<<3)
+#define OSIRIS_CTRL0_PCMCIA		(1<<4)
+#define OSIRIS_CTRL0_PCMCIA_nWAIT	(1<<6)
+#define OSIRIS_CTRL0_PCMCIA_nIOIS16	(1<<7)
+
+#define OSIRIS_ID_REVMASK		(0x7)
 
 #endif /* __ASM_ARCH_OSIRISCPLD_H */
diff --git a/include/asm-arm/arch-s3c2410/osiris-map.h b/include/asm-arm/arch-s3c2410/osiris-map.h
index a14164d..b5c74d2 100644
--- a/include/asm-arm/arch-s3c2410/osiris-map.h
+++ b/include/asm-arm/arch-s3c2410/osiris-map.h
@@ -24,16 +24,19 @@
 
 /* we put the CPLD registers next, to get them out of the way */
 
-#define OSIRIS_VA_CTRL1	    OSIRIS_IOADDR(0x00000000)
-#define OSIRIS_PA_CTRL1	    (OSIRIS_PA_CPLD)
+#define OSIRIS_VA_CTRL0		OSIRIS_IOADDR(0x00000000)
+#define OSIRIS_PA_CTRL0		(OSIRIS_PA_CPLD)
 
-#define OSIRIS_VA_CTRL2	    OSIRIS_IOADDR(0x00100000)
-#define OSIRIS_PA_CTRL2	    (OSIRIS_PA_CPLD + (1<<23))
+#define OSIRIS_VA_CTRL1		OSIRIS_IOADDR(0x00100000)
+#define OSIRIS_PA_CTRL1		(OSIRIS_PA_CPLD + (1<<23))
 
-#define OSIRIS_VA_CTRL3	    OSIRIS_IOADDR(0x00200000)
-#define OSIRIS_PA_CTRL3	    (OSIRIS_PA_CPLD + (2<<23))
+#define OSIRIS_VA_CTRL2		OSIRIS_IOADDR(0x00200000)
+#define OSIRIS_PA_CTRL2		(OSIRIS_PA_CPLD + (2<<23))
 
-#define OSIRIS_VA_CTRL4	    OSIRIS_IOADDR(0x00300000)
-#define OSIRIS_PA_CTRL4	    (OSIRIS_PA_CPLD + (3<<23))
+#define OSIRIS_VA_CTRL3		OSIRIS_IOADDR(0x00300000)
+#define OSIRIS_PA_CTRL3		(OSIRIS_PA_CPLD + (2<<23))
+
+#define OSIRIS_VA_IDREG		OSIRIS_IOADDR(0x00700000)
+#define OSIRIS_PA_IDREG		(OSIRIS_PA_CPLD + (7<<23))
 
 #endif /* __ASM_ARCH_OSIRISMAP_H */
-- 
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