From bfd08baae4591eca753afe3c9c63c583c4d4c78a Mon Sep 17 00:00:00 2001 From: "Steven J. Hill" Date: Tue, 5 Feb 2013 16:52:03 -0600 Subject: MIPS: microMIPS: Add instruction utility macros. Add two new macros for microMIPS. One checks if an exception was taken in either microMIPS or classic MIPS mode. The other checks if a microMIPS instruction is 16-bit or 32-bit in length. [ralf@linux-mips.org: Removed unnecessary parenthesis as noted by Sergei Shtylyov ] Signed-off-by: Steven J. Hill Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: kevink@paralogos.com Cc: ddaney.cavm@gmail.com Cc: Sergei Shtylyov Patchwork: https://patchwork.linux-mips.org/patch/4924/ Signed-off-by: Ralf Baechle (cherry picked from commit 49df26472338b935fd5781bf94a77a88b148a716) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 0da44d4..f64e17f 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -623,6 +623,24 @@ #ifndef __ASSEMBLY__ /* + * Macros for handling the ISA mode bit for microMIPS. + */ +#define get_isa16_mode(x) ((x) & 0x1) +#define msk_isa16_mode(x) ((x) & ~0x1) +#define set_isa16_mode(x) do { (x) |= 0x1; } while(0) + +/* + * microMIPS instructions can be 16-bit or 32-bit in length. This + * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. + */ +static inline int mm_insn_16bit(u16 insn) +{ + u16 opcode = (insn >> 10) & 0x7; + + return (opcode >= 1 && opcode <= 3) ? 1 : 0; +} + +/* * Functions to access the R10000 performance counters. These are basically * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit * performance counter number encoded into bits 1 ... 5 of the instruction. -- cgit v0.10.2