From 31fc0bd4aab30cac3e3388883b1b62750cc2f648 Mon Sep 17 00:00:00 2001 From: Rupjyoti Sarmah Date: Fri, 4 Jun 2010 00:03:12 +0000 Subject: powerpc/4xx: Device tree update for the 460ex DWC SATA Device tree update for the Applied micro processor 460ex on-chip SATA Signed-off-by: Rupjyoti Sarmah Signed-off-by: Josh Boyer diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts index 5806ef0..a303703 100644 --- a/arch/powerpc/boot/dts/canyonlands.dts +++ b/arch/powerpc/boot/dts/canyonlands.dts @@ -163,6 +163,14 @@ interrupts = <0x1e 4>; }; + SATA0: sata@bffd1000 { + compatible = "amcc,sata-460ex"; + reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>; + interrupt-parent = <&UIC3>; + interrupts = <0x0 0x4 /* SATA */ + 0x5 0x4>; /* AHBDMA */ + }; + POB0: opb { compatible = "ibm,opb-460ex", "ibm,opb"; #address-cells = <1>; -- cgit v0.10.2 From 029b8f662b24a35aab20a81087822f1badf5463c Mon Sep 17 00:00:00 2001 From: Dave Kleikamp Date: Wed, 18 Aug 2010 06:44:23 +0000 Subject: powerpc/47x: Make sure mcsr is cleared before enabling machine check interrupts Clear the machine check syndrom register before enabling machine check interrupts. The initial state of the tlb can lead to parity errors being flagged early after a cold boot. Signed-off-by: Dave Kleikamp Signed-off-by: Josh Boyer diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index 5ab484e..562305b 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -113,6 +113,10 @@ _ENTRY(_start); stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ stw r6, 0(r5) + /* Clear the Machine Check Syndrome Register */ + li r0,0 + mtspr SPRN_MCSR,r0 + /* Let's move on */ lis r4,start_kernel@h ori r4,r4,start_kernel@l -- cgit v0.10.2 From 66477466b8b79c98af17f1c2267596c8b6b4b561 Mon Sep 17 00:00:00 2001 From: Dave Kleikamp Date: Wed, 18 Aug 2010 06:44:24 +0000 Subject: powerpc/47x: Remove redundant line from cputable.c There are two entries for .cpu_user_features in arch/powerpc/kernel/cputable.c. Remove the one that doesn't belong Signed-off-by: Dave Kleikamp Signed-off-by: Josh Boyer diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 65e2b4e..1f9123f 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -1826,7 +1826,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .cpu_features = CPU_FTRS_47X, .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, - .cpu_user_features = COMMON_USER_BOOKE, .mmu_features = MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, .icache_bsize = 32, -- cgit v0.10.2 From 3e7f45ad521ac3e38889d255ec7676037fa84ae2 Mon Sep 17 00:00:00 2001 From: Dave Kleikamp Date: Wed, 18 Aug 2010 06:44:25 +0000 Subject: powerpc/4xx: Index interrupt stacks by physical cpu The interrupt stacks need to be indexed by the physical cpu since the critical, debug and machine check handlers use the contents of SPRN_PIR to index the critirq_ctx, dbgirq_ctx, and mcheckirq_ctx arrays. Signed-off-by: Dave Kleikamp Signed-off-by: Josh Boyer diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index d3ce67c..4a65386 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c @@ -67,6 +67,7 @@ #include #include #include +#include #ifdef CONFIG_PPC64 #include @@ -446,22 +447,23 @@ struct thread_info *mcheckirq_ctx[NR_CPUS] __read_mostly; void exc_lvl_ctx_init(void) { struct thread_info *tp; - int i; + int i, hw_cpu; for_each_possible_cpu(i) { - memset((void *)critirq_ctx[i], 0, THREAD_SIZE); - tp = critirq_ctx[i]; + hw_cpu = get_hard_smp_processor_id(i); + memset((void *)critirq_ctx[hw_cpu], 0, THREAD_SIZE); + tp = critirq_ctx[hw_cpu]; tp->cpu = i; tp->preempt_count = 0; #ifdef CONFIG_BOOKE - memset((void *)dbgirq_ctx[i], 0, THREAD_SIZE); - tp = dbgirq_ctx[i]; + memset((void *)dbgirq_ctx[hw_cpu], 0, THREAD_SIZE); + tp = dbgirq_ctx[hw_cpu]; tp->cpu = i; tp->preempt_count = 0; - memset((void *)mcheckirq_ctx[i], 0, THREAD_SIZE); - tp = mcheckirq_ctx[i]; + memset((void *)mcheckirq_ctx[hw_cpu], 0, THREAD_SIZE); + tp = mcheckirq_ctx[hw_cpu]; tp->cpu = i; tp->preempt_count = HARDIRQ_OFFSET; #endif diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c index a10ffc8..93666f9 100644 --- a/arch/powerpc/kernel/setup_32.c +++ b/arch/powerpc/kernel/setup_32.c @@ -258,17 +258,18 @@ static void __init irqstack_early_init(void) #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) static void __init exc_lvl_early_init(void) { - unsigned int i; + unsigned int i, hw_cpu; /* interrupt stacks must be in lowmem, we get that for free on ppc32 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */ for_each_possible_cpu(i) { - critirq_ctx[i] = (struct thread_info *) + hw_cpu = get_hard_smp_processor_id(i); + critirq_ctx[hw_cpu] = (struct thread_info *) __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); #ifdef CONFIG_BOOKE - dbgirq_ctx[i] = (struct thread_info *) + dbgirq_ctx[hw_cpu] = (struct thread_info *) __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); - mcheckirq_ctx[i] = (struct thread_info *) + mcheckirq_ctx[hw_cpu] = (struct thread_info *) __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); #endif } -- cgit v0.10.2 From 32412aa214e05308833a89e6090406294833f989 Mon Sep 17 00:00:00 2001 From: Dave Kleikamp Date: Wed, 18 Aug 2010 06:44:26 +0000 Subject: powerpc/47x: Add an isync before the tlbivax instruction Signed-off-by: Dave Kleikamp Signed-off-by: Josh Boyer diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index cfa7682..b9d9fed 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S @@ -200,6 +200,7 @@ _GLOBAL(_tlbivax_bcast) rlwimi r5,r4,0,16,31 wrteei 0 mtspr SPRN_MMUCR,r5 + isync /* tlbivax 0,r3 - use .long to avoid binutils deps */ .long 0x7c000624 | (r3 << 11) isync -- cgit v0.10.2