From 7a6dba419338704f39798b30c0ee8203d779db6e Mon Sep 17 00:00:00 2001 From: Chenhui Zhao Date: Wed, 8 Jul 2015 18:10:55 +0800 Subject: arm: ls1021a: change the order of setting PMC interrupt registers In deep sleep process, set interrupt status and polarity registers before enabling PMC interrupts. It is more stable, especially on ls1021a-twr board. Signed-off-by: Chenhui Zhao Change-Id: I8305e25a76f0bcc636b58178495165c915ac3c1a Reviewed-on: http://git.am.freescale.net:8181/39478 Tested-by: Review Code-CDREVIEW Reviewed-by: Zhengxiong Jin diff --git a/arch/arm/mach-imx/pm-ls1.c b/arch/arm/mach-imx/pm-ls1.c index 67260a5..8ad1b85 100644 --- a/arch/arm/mach-imx/pm-ls1.c +++ b/arch/arm/mach-imx/pm-ls1.c @@ -195,11 +195,12 @@ static void ls1_setup_pmc_int(void) /* always set external IRQ pins as wakeup source */ pmcintecr |= CCSR_SCFG_PMCINTECR_IRQ0 | CCSR_SCFG_PMCINTECR_IRQ1; - /* enable wakeup interrupt during deep sleep */ - iowrite32be(pmcintecr, ls1_pm_base.scfg + CCSR_SCFG_PMCINTECR); iowrite32be(0, ls1_pm_base.scfg + CCSR_SCFG_PMCINTLECR); /* clear PMC interrupt status */ iowrite32be(0xffffffff, ls1_pm_base.scfg + CCSR_SCFG_PMCINTSR); + /* enable wakeup interrupt during deep sleep */ + iowrite32be(pmcintecr, ls1_pm_base.scfg + CCSR_SCFG_PMCINTECR); + } static void ls1_clear_pmc_int(void) -- cgit v0.10.2