From c6415963006392cd67cb2d322c56ccc1711ac732 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Mon, 26 Aug 2013 19:09:03 +0200 Subject: clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls This array defines PLLs specific to Exynos 4x12 SoCs and not for all Exynos 4 SoCs, so the name should represent that. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Reviewed-by: Sylwester Nawrocki Signed-off-by: Mike Turquette diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index cafb695..41cbe6e 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -984,7 +984,7 @@ static struct of_device_id ext_clk_match[] __initdata = { {}, }; -static struct samsung_pll_clock exynos4_plls[nr_plls] __initdata = { +static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { [apll] = PLL(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, NULL), [mpll] = PLL(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", @@ -1036,8 +1036,8 @@ static void __init exynos4_clk_init(struct device_node *np, samsung_clk_add_lookup(epll, fout_epll); samsung_clk_add_lookup(vpll, fout_vpll); } else { - samsung_clk_register_pll(exynos4_plls, - ARRAY_SIZE(exynos4_plls), reg_base); + samsung_clk_register_pll(exynos4x12_plls, + ARRAY_SIZE(exynos4x12_plls), reg_base); } samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks, -- cgit v0.10.2