From f8adeb82a931c780900f8133aeeea6f0b5154573 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 4 Jul 2013 13:49:47 +1000 Subject: drm/nvc0-/gr: remove hardcoding of UNK count/mask in GPCCS ucode Signed-off-by: Ben Skeggs diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc index 3283272..b9dba10 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc @@ -42,8 +42,8 @@ tpc_count: .b32 0 tpc_mask: .b32 0 #if NV_PGRAPH_GPCX_UNK__SIZE > 0 -unk_count: .b32 1 -unk_mask: .b32 1 +unk_count: .b32 0 +unk_mask: .b32 0 #endif cmd_queue: queue_init @@ -115,6 +115,31 @@ init: iord $r2 I[$r1 + 0x000] // MYINDEX st b32 D[$r0 + #gpc_id] $r2 +#if NV_PGRAPH_GPCX_UNK__SIZE > 0 + // figure out which, and how many, UNKs are actually present + mov $r14 0x0c30 + sethi $r14 0x500000 + clear b32 $r2 + clear b32 $r3 + clear b32 $r4 + init_unk_loop: + call #nv_rd32 + cmp b32 $r15 0 + bra z #init_unk_next + mov $r15 1 + shl b32 $r15 $r2 + or $r4 $r15 + add b32 $r3 1 + init_unk_next: + add b32 $r2 1 + add b32 $r14 4 + cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE + bra ne #init_unk_loop + init_unk_done: + st b32 D[$r0 + #unk_count] $r3 + st b32 D[$r0 + #unk_mask] $r4 +#endif + // initialise context base, and size tracking mov $r2 0x800 shl b32 $r2 6 diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h index 95d13a1..66d034f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h @@ -16,9 +16,9 @@ uint32_t nvd7_grgpc_data[] = { /* 0x0018: tpc_mask */ 0x00000000, /* 0x001c: unk_count */ - 0x00000001, + 0x00000000, /* 0x0020: unk_mask */ - 0x00000001, + 0x00000000, /* 0x0024: cmd_queue */ 0x00000000, 0x00000000, @@ -271,7 +271,7 @@ uint32_t nvd7_grgpc_code[] = { 0xf10004fe, 0xf0120017, 0x12d00227, - 0x2317f100, + 0x5717f100, 0x0010fe04, 0x040017f1, 0xf0c010d0, @@ -286,7 +286,23 @@ uint32_t nvd7_grgpc_code[] = { 0x06038005, 0x040010b7, 0x800012cf, - 0x27f10402, + 0xe7f10402, + 0xe3f00c30, + 0xbd24bd50, +/* 0x035f: init_unk_loop */ + 0xf444bd34, + 0xf6b06821, + 0x0f0bf400, + 0xbb01f7f0, + 0x4ffd04f2, + 0x0130b605, +/* 0x0374: init_unk_next */ + 0xb60120b6, + 0x26b004e0, + 0xe21bf401, +/* 0x0380: init_unk_done */ + 0x80070380, + 0x27f10804, 0x24b60800, 0x4022cf06, 0x47f134bd, @@ -323,7 +339,7 @@ uint32_t nvd7_grgpc_code[] = { 0x10b74013, 0x24bd0800, 0xd01f29f0, -/* 0x03e6: main */ +/* 0x041a: main */ 0x31f40012, 0x0028f400, 0xf424d7f0, @@ -335,12 +351,12 @@ uint32_t nvd7_grgpc_code[] = { 0xe4b60412, 0x051efd01, 0xf50018fe, - 0xf404a821, -/* 0x0416: main_not_ctx_xfer */ + 0xf404dc21, +/* 0x044a: main_not_ctx_xfer */ 0xef94d30e, 0x01f5f010, 0x02ec21f5, -/* 0x0423: ih */ +/* 0x0457: ih */ 0xf9c60ef4, 0x0188fe80, 0x90f980f9, @@ -355,7 +371,7 @@ uint32_t nvd7_grgpc_code[] = { 0xb70421f4, 0xf00400b0, 0xbed001e7, -/* 0x0459: ih_no_fifo */ +/* 0x048d: ih_no_fifo */ 0x400ad000, 0xe0fcf0fc, 0xb0fcd0fc, @@ -363,28 +379,28 @@ uint32_t nvd7_grgpc_code[] = { 0x88fe80fc, 0xf480fc00, 0x01f80032, -/* 0x0474: hub_barrier_done */ +/* 0x04a8: hub_barrier_done */ 0x9801f7f0, 0xfebb040e, 0x18e7f104, 0x40e3f094, 0xf88d21f4, -/* 0x0489: ctx_redswitch */ +/* 0x04bd: ctx_redswitch */ 0x14e7f100, 0x06e4b606, 0xd020f7f0, 0xf7f000ef, -/* 0x0499: ctx_redswitch_delay */ +/* 0x04cd: ctx_redswitch_delay */ 0x01f2b608, 0xf1fd1bf4, 0xd00a20f7, 0x00f800ef, -/* 0x04a8: ctx_xfer */ +/* 0x04dc: ctx_xfer */ 0x0a0417f1, 0xd00614b6, 0x11f4001f, - 0x8921f507, -/* 0x04b9: ctx_xfer_not_load */ + 0xbd21f507, +/* 0x04ed: ctx_xfer_not_load */ 0xfc17f104, 0x0213f04a, 0xd00c27f0, @@ -424,13 +440,13 @@ uint32_t nvd7_grgpc_code[] = { 0x21f5015c, 0x01f40207, 0x1412f406, -/* 0x0554: ctx_xfer_post */ +/* 0x0588: ctx_xfer_post */ 0x4afc17f1, 0xf00213f0, 0x12d00d27, 0x0721f500, -/* 0x0565: ctx_xfer_done */ - 0x7421f502, +/* 0x0599: ctx_xfer_done */ + 0xa821f502, 0x0000f804, 0x00000000, 0x00000000, @@ -456,17 +472,4 @@ uint32_t nvd7_grgpc_code[] = { 0x00000000, 0x00000000, 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h index dc26c28..dc9c778 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h @@ -16,9 +16,9 @@ uint32_t nve0_grgpc_data[] = { /* 0x0018: tpc_mask */ 0x00000000, /* 0x001c: unk_count */ - 0x00000001, + 0x00000000, /* 0x0020: unk_mask */ - 0x00000001, + 0x00000000, /* 0x0024: cmd_queue */ 0x00000000, 0x00000000, @@ -271,7 +271,7 @@ uint32_t nve0_grgpc_code[] = { 0xf10004fe, 0xf0120017, 0x12d00227, - 0x2317f100, + 0x5717f100, 0x0010fe04, 0x040017f1, 0xf0c010d0, @@ -286,7 +286,23 @@ uint32_t nve0_grgpc_code[] = { 0x06038005, 0x040010b7, 0x800012cf, - 0x27f10402, + 0xe7f10402, + 0xe3f00c30, + 0xbd24bd50, +/* 0x035f: init_unk_loop */ + 0xf444bd34, + 0xf6b06821, + 0x0f0bf400, + 0xbb01f7f0, + 0x4ffd04f2, + 0x0130b605, +/* 0x0374: init_unk_next */ + 0xb60120b6, + 0x26b004e0, + 0xe21bf401, +/* 0x0380: init_unk_done */ + 0x80070380, + 0x27f10804, 0x24b60800, 0x4022cf06, 0x47f134bd, @@ -323,7 +339,7 @@ uint32_t nve0_grgpc_code[] = { 0x10b74013, 0x24bd0800, 0xd01f29f0, -/* 0x03e6: main */ +/* 0x041a: main */ 0x31f40012, 0x0028f400, 0xf424d7f0, @@ -335,12 +351,12 @@ uint32_t nve0_grgpc_code[] = { 0xe4b60412, 0x051efd01, 0xf50018fe, - 0xf404a821, -/* 0x0416: main_not_ctx_xfer */ + 0xf404dc21, +/* 0x044a: main_not_ctx_xfer */ 0xef94d30e, 0x01f5f010, 0x02ec21f5, -/* 0x0423: ih */ +/* 0x0457: ih */ 0xf9c60ef4, 0x0188fe80, 0x90f980f9, @@ -355,7 +371,7 @@ uint32_t nve0_grgpc_code[] = { 0xb70421f4, 0xf00400b0, 0xbed001e7, -/* 0x0459: ih_no_fifo */ +/* 0x048d: ih_no_fifo */ 0x400ad000, 0xe0fcf0fc, 0xb0fcd0fc, @@ -363,28 +379,28 @@ uint32_t nve0_grgpc_code[] = { 0x88fe80fc, 0xf480fc00, 0x01f80032, -/* 0x0474: hub_barrier_done */ +/* 0x04a8: hub_barrier_done */ 0x9801f7f0, 0xfebb040e, 0x18e7f104, 0x40e3f094, 0xf88d21f4, -/* 0x0489: ctx_redswitch */ +/* 0x04bd: ctx_redswitch */ 0x14e7f100, 0x06e4b606, 0xd020f7f0, 0xf7f000ef, -/* 0x0499: ctx_redswitch_delay */ +/* 0x04cd: ctx_redswitch_delay */ 0x01f2b608, 0xf1fd1bf4, 0xd00a20f7, 0x00f800ef, -/* 0x04a8: ctx_xfer */ +/* 0x04dc: ctx_xfer */ 0x0a0417f1, 0xd00614b6, 0x11f4001f, - 0x8921f507, -/* 0x04b9: ctx_xfer_not_load */ + 0xbd21f507, +/* 0x04ed: ctx_xfer_not_load */ 0xfc17f104, 0x0213f04a, 0xd00c27f0, @@ -424,13 +440,13 @@ uint32_t nve0_grgpc_code[] = { 0x21f5015c, 0x01f40207, 0x1412f406, -/* 0x0554: ctx_xfer_post */ +/* 0x0588: ctx_xfer_post */ 0x4afc17f1, 0xf00213f0, 0x12d00d27, 0x0721f500, -/* 0x0565: ctx_xfer_done */ - 0x7421f502, +/* 0x0599: ctx_xfer_done */ + 0xa821f502, 0x0000f804, 0x00000000, 0x00000000, @@ -456,17 +472,4 @@ uint32_t nve0_grgpc_code[] = { 0x00000000, 0x00000000, 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h index ecf9a5f..cbbed6a 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h @@ -16,9 +16,9 @@ uint32_t nvf0_grgpc_data[] = { /* 0x0018: tpc_mask */ 0x00000000, /* 0x001c: unk_count */ - 0x00000001, + 0x00000000, /* 0x0020: unk_mask */ - 0x00000001, + 0x00000000, /* 0x0024: cmd_queue */ 0x00000000, 0x00000000, @@ -271,7 +271,7 @@ uint32_t nvf0_grgpc_code[] = { 0xf10004fe, 0xf0120017, 0x12d00227, - 0x2317f100, + 0x5717f100, 0x0010fe04, 0x040017f1, 0xf0c010d0, @@ -286,7 +286,23 @@ uint32_t nvf0_grgpc_code[] = { 0x06038005, 0x040010b7, 0x800012cf, - 0x27f10402, + 0xe7f10402, + 0xe3f00c30, + 0xbd24bd50, +/* 0x035f: init_unk_loop */ + 0xf444bd34, + 0xf6b06821, + 0x0f0bf400, + 0xbb01f7f0, + 0x4ffd04f2, + 0x0130b605, +/* 0x0374: init_unk_next */ + 0xb60120b6, + 0x26b004e0, + 0xe21bf402, +/* 0x0380: init_unk_done */ + 0x80070380, + 0x27f10804, 0x24b60800, 0x4022cf06, 0x47f134bd, @@ -323,7 +339,7 @@ uint32_t nvf0_grgpc_code[] = { 0x10b74013, 0x24bd0800, 0xd01f29f0, -/* 0x03e6: main */ +/* 0x041a: main */ 0x31f40012, 0x0028f400, 0xf424d7f0, @@ -335,12 +351,12 @@ uint32_t nvf0_grgpc_code[] = { 0xe4b60412, 0x051efd01, 0xf50018fe, - 0xf404a821, -/* 0x0416: main_not_ctx_xfer */ + 0xf404dc21, +/* 0x044a: main_not_ctx_xfer */ 0xef94d30e, 0x01f5f010, 0x02ec21f5, -/* 0x0423: ih */ +/* 0x0457: ih */ 0xf9c60ef4, 0x0188fe80, 0x90f980f9, @@ -355,7 +371,7 @@ uint32_t nvf0_grgpc_code[] = { 0xb70421f4, 0xf00400b0, 0xbed001e7, -/* 0x0459: ih_no_fifo */ +/* 0x048d: ih_no_fifo */ 0x400ad000, 0xe0fcf0fc, 0xb0fcd0fc, @@ -363,28 +379,28 @@ uint32_t nvf0_grgpc_code[] = { 0x88fe80fc, 0xf480fc00, 0x01f80032, -/* 0x0474: hub_barrier_done */ +/* 0x04a8: hub_barrier_done */ 0x9801f7f0, 0xfebb040e, 0x18e7f104, 0x40e3f094, 0xf88d21f4, -/* 0x0489: ctx_redswitch */ +/* 0x04bd: ctx_redswitch */ 0x14e7f100, 0x06e4b606, 0xd020f7f0, 0xf7f000ef, -/* 0x0499: ctx_redswitch_delay */ +/* 0x04cd: ctx_redswitch_delay */ 0x01f2b608, 0xf1fd1bf4, 0xd00a20f7, 0x00f800ef, -/* 0x04a8: ctx_xfer */ +/* 0x04dc: ctx_xfer */ 0x0a0417f1, 0xd00614b6, 0x11f4001f, - 0x8921f507, -/* 0x04b9: ctx_xfer_not_load */ + 0xbd21f507, +/* 0x04ed: ctx_xfer_not_load */ 0xfc17f104, 0x0213f04a, 0xd00c27f0, @@ -424,13 +440,13 @@ uint32_t nvf0_grgpc_code[] = { 0x21f5015c, 0x01f40207, 0x1412f406, -/* 0x0554: ctx_xfer_post */ +/* 0x0588: ctx_xfer_post */ 0x4afc17f1, 0xf00213f0, 0x12d00d27, 0x0721f500, -/* 0x0565: ctx_xfer_done */ - 0x7421f502, +/* 0x0599: ctx_xfer_done */ + 0xa821f502, 0x0000f804, 0x00000000, 0x00000000, @@ -456,17 +472,4 @@ uint32_t nvf0_grgpc_code[] = { 0x00000000, 0x00000000, 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, }; 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