From f9f08d70b0081c0f5ff4eabefc47f0832fdb7697 Mon Sep 17 00:00:00 2001 From: Larry Finger Date: Wed, 21 Aug 2013 22:34:06 -0500 Subject: staging: r8188eu: Add files for new driver - part 24 This commit adds files include/odm.h, include/odm_HWConfig.h, include/odm_RTL8188E.h, include/odm_RegConfig8188E.h, include/odm_RegDefine11AC.h, include/odm_RegDefine11N.h, include/odm_debug.h, include/odm_interface.h, include/odm_precomp.h, include/odm_reg.h, include/odm_types.h, include/osdep_intf.h, and include/osdep_service.h. Signed-off-by: Larry Finger Signed-off-by: Greg Kroah-Hartman diff --git a/drivers/staging/rtl8188eu/include/odm.h b/drivers/staging/rtl8188eu/include/odm.h new file mode 100644 index 0000000..2bfe728 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm.h @@ -0,0 +1,1198 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __HALDMOUTSRC_H__ +#define __HALDMOUTSRC_H__ + +/* Definition */ +/* Define all team support ability. */ + +/* Define for all teams. Please Define the constant in your precomp header. */ + +/* define DM_ODM_SUPPORT_AP 0 */ +/* define DM_ODM_SUPPORT_ADSL 0 */ +/* define DM_ODM_SUPPORT_CE 0 */ +/* define DM_ODM_SUPPORT_MP 1 */ + +/* Define ODM SW team support flag. */ + +/* Antenna Switch Relative Definition. */ + +/* Add new function SwAntDivCheck8192C(). */ +/* This is the main function of Antenna diversity function before link. */ +/* Mainly, it just retains last scan result and scan again. */ +/* After that, it compares the scan result to see which one gets better + * RSSI. It selects antenna with better receiving power and returns better + * scan result. */ + +#define TP_MODE 0 +#define RSSI_MODE 1 +#define TRAFFIC_LOW 0 +#define TRAFFIC_HIGH 1 + +/* 3 Tx Power Tracking */ +/* 3============================================================ */ +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 + + +/* */ +/* 3 PSD Handler */ +/* 3============================================================ */ + +#define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ +#define MODE_40M 0 /* 0:20M, 1:40M */ +#define PSD_TH2 3 +#define PSD_CHM 20 /* Minimum channel number for BT AFH */ +#define SIR_STEP_SIZE 3 +#define Smooth_Size_1 5 +#define Smooth_TH_1 3 +#define Smooth_Size_2 10 +#define Smooth_TH_2 4 +#define Smooth_Size_3 20 +#define Smooth_TH_3 4 +#define Smooth_Step_Size 5 +#define Adaptive_SIR 1 +#define PSD_RESCAN 4 +#define PSD_SCAN_INTERVAL 700 /* ms */ + +/* 8723A High Power IGI Setting */ +#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 +#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 +#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a + +/* LPS define */ +#define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */ +#define DM_DIG_FA_TH1_LPS 15 /* 15 lps */ +#define DM_DIG_FA_TH2_LPS 30 /* 30 lps */ +#define RSSI_OFFSET_DIG 0x05; + +/* ANT Test */ +#define ANTTESTALL 0x00 /* Ant A or B will be Testing */ +#define ANTTESTA 0x01 /* Ant A will be Testing */ +#define ANTTESTB 0x02 /* Ant B will be testing */ + +/* structure and define */ + +/* Add for AP/ADSLpseudo DM structuer requirement. */ +/* We need to remove to other position??? */ +struct rtl8192cd_priv { + u8 temp; +}; + +struct rtw_dig { + u8 Dig_Enable_Flag; + u8 Dig_Ext_Port_Stage; + + int RssiLowThresh; + int RssiHighThresh; + + u32 FALowThresh; + u32 FAHighThresh; + + u8 CurSTAConnectState; + u8 PreSTAConnectState; + u8 CurMultiSTAConnectState; + + u8 PreIGValue; + u8 CurIGValue; + u8 BackupIGValue; + + s8 BackoffVal; + s8 BackoffVal_range_max; + s8 BackoffVal_range_min; + u8 rx_gain_range_max; + u8 rx_gain_range_min; + u8 Rssi_val_min; + + u8 PreCCK_CCAThres; + u8 CurCCK_CCAThres; + u8 PreCCKPDState; + u8 CurCCKPDState; + + u8 LargeFAHit; + u8 ForbiddenIGI; + u32 Recover_cnt; + + u8 DIG_Dynamic_MIN_0; + u8 DIG_Dynamic_MIN_1; + bool bMediaConnect_0; + bool bMediaConnect_1; + + u32 AntDiv_RSSI_max; + u32 RSSI_max; +}; + +struct rtl_ps { + u8 PreCCAState; + u8 CurCCAState; + + u8 PreRFState; + u8 CurRFState; + + int Rssi_val_min; + + u8 initialize; + u32 Reg874,RegC70,Reg85C,RegA74; + +}; + +struct false_alarm_stats { + u32 Cnt_Parity_Fail; + u32 Cnt_Rate_Illegal; + u32 Cnt_Crc8_fail; + u32 Cnt_Mcs_fail; + u32 Cnt_Ofdm_fail; + u32 Cnt_Cck_fail; + u32 Cnt_all; + u32 Cnt_Fast_Fsync; + u32 Cnt_SB_Search_fail; + u32 Cnt_OFDM_CCA; + u32 Cnt_CCK_CCA; + u32 Cnt_CCA_all; + u32 Cnt_BW_USC; /* Gary */ + u32 Cnt_BW_LSC; /* Gary */ +}; + +struct dyn_primary_cca { + u8 PriCCA_flag; + u8 intf_flag; + u8 intf_type; + u8 DupRTS_flag; + u8 Monitor_flag; +}; + +struct rx_hpc { + u8 RXHP_flag; + u8 PSD_func_trigger; + u8 PSD_bitmap_RXHP[80]; + u8 Pre_IGI; + u8 Cur_IGI; + u8 Pre_pw_th; + u8 Cur_pw_th; + bool First_time_enter; + bool RXHP_enable; + u8 TP_Mode; + struct timer_list PSDTimer; +}; + +#define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ +#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM + +/* This indicates two different steps. */ +/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to + * the signal on the air. */ +/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in + * SWAW_STEP_PEAK with original RSSI to determine if it is necessary to + * switch antenna. */ + +#define SWAW_STEP_PEAK 0 +#define SWAW_STEP_DETERMINE 1 + +#define TP_MODE 0 +#define RSSI_MODE 1 +#define TRAFFIC_LOW 0 +#define TRAFFIC_HIGH 1 + +struct sw_ant_switch { + u8 try_flag; + s32 PreRSSI; + u8 CurAntenna; + u8 PreAntenna; + u8 RSSI_Trying; + u8 TestMode; + u8 bTriggerAntennaSwitch; + u8 SelectAntennaMap; + u8 RSSI_target; + + /* Before link Antenna Switch check */ + u8 SWAS_NoLink_State; + u32 SWAS_NoLink_BK_Reg860; + bool ANTA_ON; /* To indicate Ant A is or not */ + bool ANTB_ON; /* To indicate Ant B is on or not */ + + s32 RSSI_sum_A; + s32 RSSI_sum_B; + s32 RSSI_cnt_A; + s32 RSSI_cnt_B; + u64 lastTxOkCnt; + u64 lastRxOkCnt; + u64 TXByteCnt_A; + u64 TXByteCnt_B; + u64 RXByteCnt_A; + u64 RXByteCnt_B; + u8 TrafficLoad; + struct timer_list SwAntennaSwitchTimer; + /* Hybrid Antenna Diversity */ + u32 CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; + u32 CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM]; + u32 OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; + u32 OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM]; + u32 RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM]; + u32 RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM]; + u8 TxAnt[ASSOCIATE_ENTRY_NUM]; + u8 TargetSTA; + u8 antsel; + u8 RxIdleAnt; +}; + +struct edca_turbo { + bool bCurrentTurboEDCA; + bool bIsCurRDLState; + u32 prv_traffic_idx; /* edca turbo */ +}; + +struct odm_rate_adapt { + u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ + u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ + u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ + u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ + u32 LastRATR; /* RATR Register Content */ +}; + +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 +#define IQK_BB_REG_NUM 9 +#define HP_THERMAL_NUM 8 + +#define AVG_THERMAL_NUM 8 +#define IQK_Matrix_REG_NUM 8 +#define IQK_Matrix_Settings_NUM 1+24+21 + +#define DM_Type_ByFWi 0 +#define DM_Type_ByDriver 1 + +/* Declare for common info */ + +#define MAX_PATH_NUM_92CS 2 + +struct odm_phy_status_info { + u8 RxPWDBAll; + u8 SignalQuality; /* in 0-100 index. */ + u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */ + u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/* in 0~100 index */ + s8 RxPower; /* in dBm Translate from PWdB */ + s8 RecvSignalPower;/* Real power in dBm for this packet, no + * beautification and aggregation. Keep this raw + * info to be used for the other procedures. */ + u8 BTRxRSSIPercentage; + u8 SignalStrength; /* in 0-100 index. */ + u8 RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */ + u8 RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */ +}; + +struct odm_phy_dbg_info { + /* ODM Write,debug info */ + s8 RxSNRdB[MAX_PATH_NUM_92CS]; + u64 NumQryPhyStatus; + u64 NumQryPhyStatusCCK; + u64 NumQryPhyStatusOFDM; + /* Others */ + s32 RxEVM[MAX_PATH_NUM_92CS]; +}; + +struct odm_per_pkt_info { + s8 Rate; + u8 StationID; + bool bPacketMatchBSSID; + bool bPacketToSelf; + bool bPacketBeacon; +}; + +struct odm_mac_status_info { + u8 test; +}; + +enum odm_ability { + /* BB Team */ + ODM_DIG = 0x00000001, + ODM_HIGH_POWER = 0x00000002, + ODM_CCK_CCA_TH = 0x00000004, + ODM_FA_STATISTICS = 0x00000008, + ODM_RAMASK = 0x00000010, + ODM_RSSI_MONITOR = 0x00000020, + ODM_SW_ANTDIV = 0x00000040, + ODM_HW_ANTDIV = 0x00000080, + ODM_BB_PWRSV = 0x00000100, + ODM_2TPATHDIV = 0x00000200, + ODM_1TPATHDIV = 0x00000400, + ODM_PSD2AFH = 0x00000800 +}; + +/* 2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info */ +/* Please declare below ODM relative info in your STA info structure. */ + +struct odm_sta_info { + /* Driver Write */ + bool bUsed; /* record the sta status link or not? */ + u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */ + + /* ODM Write */ + /* 1 PHY_STATUS_INFO */ + u8 RSSI_Path[4]; /* */ + u8 RSSI_Ave; + u8 RXEVM[4]; + u8 RXSNR[4]; +}; + +/* 2011/10/20 MH Define Common info enum for all team. */ + +enum odm_common_info_def { + /* Fixed value: */ + + /* HOOK BEFORE REG INIT----------- */ + ODM_CMNINFO_PLATFORM = 0, + ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */ + ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */ + ODM_CMNINFO_MP_TEST_CHIP, + ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */ + ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */ + ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */ + ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */ + ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */ + ODM_CMNINFO_EXT_LNA, /* true */ + ODM_CMNINFO_EXT_PA, + ODM_CMNINFO_EXT_TRSW, + ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ + ODM_CMNINFO_BINHCT_TEST, + ODM_CMNINFO_BWIFI_TEST, + ODM_CMNINFO_SMART_CONCURRENT, + /* HOOK BEFORE REG INIT----------- */ + + /* Dynamic value: */ +/* POINTER REFERENCE----------- */ + ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */ + ODM_CMNINFO_TX_UNI, + ODM_CMNINFO_RX_UNI, + ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */ + ODM_CMNINFO_BAND, /* ODM_BAND_TYPE_E */ + ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */ + ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */ + ODM_CMNINFO_BW, /* ODM_BW_E */ + ODM_CMNINFO_CHNL, + + ODM_CMNINFO_DMSP_GET_VALUE, + ODM_CMNINFO_BUDDY_ADAPTOR, + ODM_CMNINFO_DMSP_IS_MASTER, + ODM_CMNINFO_SCAN, + ODM_CMNINFO_POWER_SAVING, + ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */ + ODM_CMNINFO_DRV_STOP, + ODM_CMNINFO_PNP_IN, + ODM_CMNINFO_INIT_ON, + ODM_CMNINFO_ANT_TEST, + ODM_CMNINFO_NET_CLOSED, + ODM_CMNINFO_MP_MODE, +/* POINTER REFERENCE----------- */ + +/* CALL BY VALUE------------- */ + ODM_CMNINFO_WIFI_DIRECT, + ODM_CMNINFO_WIFI_DISPLAY, + ODM_CMNINFO_LINK, + ODM_CMNINFO_RSSI_MIN, + ODM_CMNINFO_DBG_COMP, /* u64 */ + ODM_CMNINFO_DBG_LEVEL, /* u32 */ + ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ + ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ + ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ + ODM_CMNINFO_BT_DISABLED, + ODM_CMNINFO_BT_OPERATION, + ODM_CMNINFO_BT_DIG, + ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */ + ODM_CMNINFO_BT_DISABLE_EDCA, +/* CALL BY VALUE-------------*/ + + /* Dynamic ptr array hook itms. */ + ODM_CMNINFO_STA_STATUS, + ODM_CMNINFO_PHY_STATUS, + ODM_CMNINFO_MAC_STATUS, + ODM_CMNINFO_MAX, +}; + +/* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */ + +enum odm_ability_def { + /* BB ODM section BIT 0-15 */ + ODM_BB_DIG = BIT0, + ODM_BB_RA_MASK = BIT1, + ODM_BB_DYNAMIC_TXPWR = BIT2, + ODM_BB_FA_CNT = BIT3, + ODM_BB_RSSI_MONITOR = BIT4, + ODM_BB_CCK_PD = BIT5, + ODM_BB_ANT_DIV = BIT6, + ODM_BB_PWR_SAVE = BIT7, + ODM_BB_PWR_TRA = BIT8, + ODM_BB_RATE_ADAPTIVE = BIT9, + ODM_BB_PATH_DIV = BIT10, + ODM_BB_PSD = BIT11, + ODM_BB_RXHP = BIT12, + + /* MAC DM section BIT 16-23 */ + ODM_MAC_EDCA_TURBO = BIT16, + ODM_MAC_EARLY_MODE = BIT17, + + /* RF ODM section BIT 24-31 */ + ODM_RF_TX_PWR_TRACK = BIT24, + ODM_RF_RX_GAIN_TRACK = BIT25, + ODM_RF_CALIBRATION = BIT26, +}; + +/* ODM_CMNINFO_INTERFACE */ +enum odm_interface_def { + ODM_ITRF_PCIE = 0x1, + ODM_ITRF_USB = 0x2, + ODM_ITRF_SDIO = 0x4, + ODM_ITRF_ALL = 0x7, +}; + +/* ODM_CMNINFO_IC_TYPE */ +enum odm_ic_type { + ODM_RTL8192S = BIT0, + ODM_RTL8192C = BIT1, + ODM_RTL8192D = BIT2, + ODM_RTL8723A = BIT3, + ODM_RTL8188E = BIT4, + ODM_RTL8812 = BIT5, + ODM_RTL8821 = BIT6, +}; + +#define ODM_IC_11N_SERIES \ + (ODM_RTL8192S | ODM_RTL8192C | ODM_RTL8192D | \ + ODM_RTL8723A | ODM_RTL8188E) +#define ODM_IC_11AC_SERIES (ODM_RTL8812) + +/* ODM_CMNINFO_CUT_VER */ +enum odm_cut_version { + ODM_CUT_A = 1, + ODM_CUT_B = 2, + ODM_CUT_C = 3, + ODM_CUT_D = 4, + ODM_CUT_E = 5, + ODM_CUT_F = 6, + ODM_CUT_TEST = 7, +}; + +/* ODM_CMNINFO_FAB_VER */ +enum odm_fab_Version { + ODM_TSMC = 0, + ODM_UMC = 1, +}; + +/* ODM_CMNINFO_RF_TYPE */ +/* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ +enum odm_rf_path { + ODM_RF_TX_A = BIT0, + ODM_RF_TX_B = BIT1, + ODM_RF_TX_C = BIT2, + ODM_RF_TX_D = BIT3, + ODM_RF_RX_A = BIT4, + ODM_RF_RX_B = BIT5, + ODM_RF_RX_C = BIT6, + ODM_RF_RX_D = BIT7, +}; + +enum odm_rf_type { + ODM_1T1R = 0, + ODM_1T2R = 1, + ODM_2T2R = 2, + ODM_2T3R = 3, + ODM_2T4R = 4, + ODM_3T3R = 5, + ODM_3T4R = 6, + ODM_4T4R = 7, +}; + +/* ODM Dynamic common info value definition */ + +enum odm_mac_phy_mode { + ODM_SMSP = 0, + ODM_DMSP = 1, + ODM_DMDP = 2, +}; + +enum odm_bt_coexist { + ODM_BT_BUSY = 1, + ODM_BT_ON = 2, + ODM_BT_OFF = 3, + ODM_BT_NONE = 4, +}; + +/* ODM_CMNINFO_OP_MODE */ +enum odm_operation_mode { + ODM_NO_LINK = BIT0, + ODM_LINK = BIT1, + ODM_SCAN = BIT2, + ODM_POWERSAVE = BIT3, + ODM_AP_MODE = BIT4, + ODM_CLIENT_MODE = BIT5, + ODM_AD_HOC = BIT6, + ODM_WIFI_DIRECT = BIT7, + ODM_WIFI_DISPLAY = BIT8, +}; + +/* ODM_CMNINFO_WM_MODE */ +enum odm_wireless_mode { + ODM_WM_UNKNOW = 0x0, + ODM_WM_B = BIT0, + ODM_WM_G = BIT1, + ODM_WM_A = BIT2, + ODM_WM_N24G = BIT3, + ODM_WM_N5G = BIT4, + ODM_WM_AUTO = BIT5, + ODM_WM_AC = BIT6, +}; + +/* ODM_CMNINFO_BAND */ +enum odm_band_type { + ODM_BAND_2_4G = BIT0, + ODM_BAND_5G = BIT1, +}; + +/* ODM_CMNINFO_SEC_CHNL_OFFSET */ +enum odm_sec_chnl_offset { + ODM_DONT_CARE = 0, + ODM_BELOW = 1, + ODM_ABOVE = 2 +}; + +/* ODM_CMNINFO_SEC_MODE */ +enum odm_security { + ODM_SEC_OPEN = 0, + ODM_SEC_WEP40 = 1, + ODM_SEC_TKIP = 2, + ODM_SEC_RESERVE = 3, + ODM_SEC_AESCCMP = 4, + ODM_SEC_WEP104 = 5, + ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ + ODM_SEC_SMS4 = 7, +}; + +/* ODM_CMNINFO_BW */ +enum odm_bw { + ODM_BW20M = 0, + ODM_BW40M = 1, + ODM_BW80M = 2, + ODM_BW160M = 3, + ODM_BW10M = 4, +}; + +/* ODM_CMNINFO_BOARD_TYPE */ +enum odm_board_type { + ODM_BOARD_NORMAL = 0, + ODM_BOARD_HIGHPWR = 1, + ODM_BOARD_MINICARD = 2, + ODM_BOARD_SLIM = 3, + ODM_BOARD_COMBO = 4, +}; + +/* ODM_CMNINFO_ONE_PATH_CCA */ +enum odm_cca_path { + ODM_CCA_2R = 0, + ODM_CCA_1R_A = 1, + ODM_CCA_1R_B = 2, +}; + +struct odm_ra_info { + u8 RateID; + u32 RateMask; + u32 RAUseRate; + u8 RateSGI; + u8 RssiStaRA; + u8 PreRssiStaRA; + u8 SGIEnable; + u8 DecisionRate; + u8 PreRate; + u8 HighestRate; + u8 LowestRate; + u32 NscUp; + u32 NscDown; + u16 RTY[5]; + u32 TOTAL; + u16 DROP; + u8 Active; + u16 RptTime; + u8 RAWaitingCounter; + u8 RAPendingCounter; + u8 PTActive; /* on or off */ + u8 PTTryState; /* 0 trying state, 1 for decision state */ + u8 PTStage; /* 0~6 */ + u8 PTStopCount; /* Stop PT counter */ + u8 PTPreRate; /* if rate change do PT */ + u8 PTPreRssi; /* if RSSI change 5% do PT */ + u8 PTModeSS; /* decide whitch rate should do PT */ + u8 RAstage; /* StageRA, decide how many times RA will be done + * between PT */ + u8 PTSmoothFactor; +}; + +struct ijk_matrix_regs_set { + bool bIQKDone; + s32 Value[1][IQK_Matrix_REG_NUM]; +}; + +struct odm_rf_cal { + /* for tx power tracking */ + u32 RegA24; /* for TempCCK */ + s32 RegE94; + s32 RegE9C; + s32 RegEB4; + s32 RegEBC; + + u8 TXPowercount; + bool bTXPowerTrackingInit; + bool bTXPowerTracking; + u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking + * as default */ + u8 TM_Trigger; + u8 InternalPA5G[2]; /* pathA / pathB */ + + u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, + * and 1 for RFIC1 */ + u8 ThermalValue; + u8 ThermalValue_LCK; + u8 ThermalValue_IQK; + u8 ThermalValue_DPK; + u8 ThermalValue_AVG[AVG_THERMAL_NUM]; + u8 ThermalValue_AVG_index; + u8 ThermalValue_RxGain; + u8 ThermalValue_Crystal; + u8 ThermalValue_DPKstore; + u8 ThermalValue_DPKtrack; + bool TxPowerTrackingInProgress; + bool bDPKenable; + + bool bReloadtxpowerindex; + u8 bRfPiEnable; + u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ + + u8 bCCKinCH14; + u8 CCK_index; + u8 OFDM_index[2]; + bool bDoneTxpower; + + u8 ThermalValue_HP[HP_THERMAL_NUM]; + u8 ThermalValue_HP_index; + struct ijk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; + + u8 Delta_IQK; + u8 Delta_LCK; + + /* for IQK */ + u32 RegC04; + u32 Reg874; + u32 RegC08; + u32 RegB68; + u32 RegB6C; + u32 Reg870; + u32 Reg860; + u32 Reg864; + + bool bIQKInitialized; + bool bLCKInProgress; + bool bAntennaDetected; + u32 ADDA_backup[IQK_ADDA_REG_NUM]; + u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; + u32 IQK_BB_backup_recover[9]; + u32 IQK_BB_backup[IQK_BB_REG_NUM]; + + /* for APK */ + u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ + u8 bAPKdone; + u8 bAPKThermalMeterIgnore; + u8 bDPdone; + u8 bDPPathAOK; + u8 bDPPathBOK; +}; + +/* ODM Dynamic common info value definition */ + +struct fast_ant_train { + u8 Bssid[6]; + u8 antsel_rx_keep_0; + u8 antsel_rx_keep_1; + u8 antsel_rx_keep_2; + u32 antSumRSSI[7]; + u32 antRSSIcnt[7]; + u32 antAveRSSI[7]; + u8 FAT_State; + u32 TrainIdx; + u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; + u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; + u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; + u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u8 RxIdleAnt; + bool bBecomeLinked; +}; + +enum fat_state { + FAT_NORMAL_STATE = 0, + FAT_TRAINING_STATE = 1, +}; + +enum ant_div_type { + NO_ANTDIV = 0xFF, + CG_TRX_HW_ANTDIV = 0x01, + CGCS_RX_HW_ANTDIV = 0x02, + FIXED_HW_ANTDIV = 0x03, + CG_TRX_SMART_ANTDIV = 0x04, + CGCS_RX_SW_ANTDIV = 0x05, +}; + +/* Copy from SD4 defined structure. We use to support PHY DM integration. */ +struct odm_dm_struct { + /* Add for different team use temporarily */ + struct adapter *Adapter; /* For CE/NIC team */ + struct rtl8192cd_priv *priv; /* For AP/ADSL team */ + /* WHen you use above pointers, they must be initialized. */ + bool odm_ready; + + struct rtl8192cd_priv *fake_priv; + u64 DebugComponents; + u32 DebugLevel; + +/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ + bool bCckHighPower; + u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ + u8 ControlChannel; +/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ + +/* 1 COMMON INFORMATION */ + /* Init Value */ +/* HOOK BEFORE REG INIT----------- */ + /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */ + u8 SupportPlatform; + /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K */ + u32 SupportAbility; + /* ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */ + u8 SupportInterface; + /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any + * other type = 1/2/3/... */ + u32 SupportICType; + /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ + u8 CutVersion; + /* Fab Version TSMC/UMC = 0/1 */ + u8 FabVersion; + /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ + u8 RFType; + /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/. = 0/1/2/3/4/. */ + u8 BoardType; + /* with external LNA NO/Yes = 0/1 */ + u8 ExtLNA; + /* with external PA NO/Yes = 0/1 */ + u8 ExtPA; + /* with external TRSW NO/Yes = 0/1 */ + u8 ExtTRSW; + u8 PatchID; /* Customer ID */ + bool bInHctTest; + bool bWIFITest; + + bool bDualMacSmartConcurrent; + u32 BK_SupportAbility; + u8 AntDivType; +/* HOOK BEFORE REG INIT----------- */ + + /* Dynamic Value */ +/* POINTER REFERENCE----------- */ + + u8 u8_temp; + bool bool_temp; + struct adapter *adapter_temp; + + /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ + u8 *pMacPhyMode; + /* TX Unicast byte count */ + u64 *pNumTxBytesUnicast; + /* RX Unicast byte count */ + u64 *pNumRxBytesUnicast; + /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ + u8 *pWirelessMode; /* ODM_WIRELESS_MODE_E */ + /* Frequence band 2.4G/5G = 0/1 */ + u8 *pBandType; + /* Secondary channel offset don't_care/below/above = 0/1/2 */ + u8 *pSecChOffset; + /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ + u8 *pSecurity; + /* BW info 20M/40M/80M = 0/1/2 */ + u8 *pBandWidth; + /* Central channel location Ch1/Ch2/.... */ + u8 *pChannel; /* central channel number */ + /* Common info for 92D DMSP */ + + bool *pbGetValueFromOtherMac; + struct adapter **pBuddyAdapter; + bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ + /* Common info for Status */ + bool *pbScanInProcess; + bool *pbPowerSaving; + /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */ + u8 *pOnePathCCA; + /* pMgntInfo->AntennaTest */ + u8 *pAntennaTest; + bool *pbNet_closed; +/* POINTER REFERENCE----------- */ + /* */ +/* CALL BY VALUE------------- */ + bool bWIFI_Direct; + bool bWIFI_Display; + bool bLinked; + u8 RSSI_Min; + u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ + bool bIsMPChip; + bool bOneEntryOnly; + /* Common info for BTDM */ + bool bBtDisabled; /* BT is disabled */ + bool bBtHsOperation; /* BT HS mode is under progress */ + u8 btHsDigVal; /* use BT rssi to decide the DIG value */ + bool bBtDisableEdcaTurbo;/* Under some condition, don't enable the + * EDCA Turbo */ + bool bBtBusy; /* BT is busy. */ +/* CALL BY VALUE------------- */ + + /* 2 Define STA info. */ + /* _ODM_STA_INFO */ + /* For MP, we need to reduce one array pointer for default port.?? */ + struct sta_info *pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; + + u16 CurrminRptTime; + struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as + * array index. STA MacID=0, + * VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} */ + /* */ + /* 2012/02/14 MH Add to share 88E ra with other SW team. */ + /* We need to colelct all support abilit to a proper area. */ + /* */ + bool RaSupport88E; + + /* Define ........... */ + + /* Latest packet phy info (ODM write) */ + struct odm_phy_dbg_info PhyDbgInfo; + + /* Latest packet phy info (ODM write) */ + struct odm_mac_status_info *pMacInfo; + + /* Different Team independt structure?? */ + + /* ODM Structure */ + struct fast_ant_train DM_FatTable; + struct rtw_dig DM_DigTable; + struct rtl_ps DM_PSTable; + struct dyn_primary_cca DM_PriCCA; + struct rx_hpc DM_RXHP_Table; + struct false_alarm_stats FalseAlmCnt; + struct false_alarm_stats FlaseAlmCntBuddyAdapter; + struct sw_ant_switch DM_SWAT_Table; + bool RSSI_test; + + struct edca_turbo DM_EDCA_Table; + u32 WMMEDCA_BE; + /* Copy from SD4 structure */ + /* */ + /* ================================================== */ + /* */ + + bool *pbDriverStopped; + bool *pbDriverIsGoingToPnpSetPowerSleep; + bool *pinit_adpt_in_progress; + + /* PSD */ + bool bUserAssignLevel; + struct timer_list PSDTimer; + u8 RSSI_BT; /* come from BT */ + bool bPSDinProcess; + bool bDMInitialGainEnable; + + /* for rate adaptive, in fact, 88c/92c fw will handle this */ + u8 bUseRAMask; + + struct odm_rate_adapt RateAdaptive; + + struct odm_rf_cal RFCalibrateInfo; + + /* TX power tracking */ + u8 BbSwingIdxOfdm; + u8 BbSwingIdxOfdmCurrent; + u8 BbSwingIdxOfdmBase; + bool BbSwingFlagOfdm; + u8 BbSwingIdxCck; + u8 BbSwingIdxCckCurrent; + u8 BbSwingIdxCckBase; + bool BbSwingFlagCck; + u8 *mp_mode; + /* ODM system resource. */ + + /* ODM relative time. */ + struct timer_list PathDivSwitchTimer; + /* 2011.09.27 add for Path Diversity */ + struct timer_list CCKPathDiversityTimer; + struct timer_list FastAntTrainingTimer; +}; /* DM_Dynamic_Mechanism_Structure */ + +#define ODM_RF_PATH_MAX 2 + +enum ODM_RF_RADIO_PATH { + ODM_RF_PATH_A = 0, /* Radio Path A */ + ODM_RF_PATH_B = 1, /* Radio Path B */ + ODM_RF_PATH_C = 2, /* Radio Path C */ + ODM_RF_PATH_D = 3, /* Radio Path D */ +}; + +enum ODM_RF_CONTENT { + odm_radioa_txt = 0x1000, + odm_radiob_txt = 0x1001, + odm_radioc_txt = 0x1002, + odm_radiod_txt = 0x1003 +}; + +enum odm_bb_config_type { + CONFIG_BB_PHY_REG, + CONFIG_BB_AGC_TAB, + CONFIG_BB_AGC_TAB_2G, + CONFIG_BB_AGC_TAB_5G, + CONFIG_BB_PHY_REG_PG, +}; + +/* Status code */ +enum rt_status { + RT_STATUS_SUCCESS, + RT_STATUS_FAILURE, + RT_STATUS_PENDING, + RT_STATUS_RESOURCE, + RT_STATUS_INVALID_CONTEXT, + RT_STATUS_INVALID_PARAMETER, + RT_STATUS_NOT_SUPPORT, + RT_STATUS_OS_API_FAILED, +}; + +/* 3=========================================================== */ +/* 3 DIG */ +/* 3=========================================================== */ + +enum dm_dig_op { + RT_TYPE_THRESH_HIGH = 0, + RT_TYPE_THRESH_LOW = 1, + RT_TYPE_BACKOFF = 2, + RT_TYPE_RX_GAIN_MIN = 3, + RT_TYPE_RX_GAIN_MAX = 4, + RT_TYPE_ENABLE = 5, + RT_TYPE_DISABLE = 6, + DIG_OP_TYPE_MAX +}; + +#define DM_DIG_THRESH_HIGH 40 +#define DM_DIG_THRESH_LOW 35 + +#define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */ + + +#define DM_false_ALARM_THRESH_LOW 400 +#define DM_false_ALARM_THRESH_HIGH 1000 + +#define DM_DIG_MAX_NIC 0x3e +#define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */ + +#define DM_DIG_MAX_AP 0x32 +#define DM_DIG_MIN_AP 0x20 + +#define DM_DIG_MAX_NIC_HP 0x46 +#define DM_DIG_MIN_NIC_HP 0x2e + +#define DM_DIG_MAX_AP_HP 0x42 +#define DM_DIG_MIN_AP_HP 0x30 + +/* vivi 92c&92d has different definition, 20110504 */ +/* this is for 92c */ +#define DM_DIG_FA_TH0 0x200/* 0x20 */ +#define DM_DIG_FA_TH1 0x300/* 0x100 */ +#define DM_DIG_FA_TH2 0x400/* 0x200 */ +/* this is for 92d */ +#define DM_DIG_FA_TH0_92D 0x100 +#define DM_DIG_FA_TH1_92D 0x400 +#define DM_DIG_FA_TH2_92D 0x600 + +#define DM_DIG_BACKOFF_MAX 12 +#define DM_DIG_BACKOFF_MIN -4 +#define DM_DIG_BACKOFF_DEFAULT 10 + +/* 3=========================================================== */ +/* 3 AGC RX High Power Mode */ +/* 3=========================================================== */ +#define LNA_Low_Gain_1 0x64 +#define LNA_Low_Gain_2 0x5A +#define LNA_Low_Gain_3 0x58 + +#define FA_RXHP_TH1 5000 +#define FA_RXHP_TH2 1500 +#define FA_RXHP_TH3 800 +#define FA_RXHP_TH4 600 +#define FA_RXHP_TH5 500 + +/* 3=========================================================== */ +/* 3 EDCA */ +/* 3=========================================================== */ + +/* 3=========================================================== */ +/* 3 Dynamic Tx Power */ +/* 3=========================================================== */ +/* Dynamic Tx Power Control Threshold */ +#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 +#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 +#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F + +#define TxHighPwrLevel_Normal 0 +#define TxHighPwrLevel_Level1 1 +#define TxHighPwrLevel_Level2 2 +#define TxHighPwrLevel_BT1 3 +#define TxHighPwrLevel_BT2 4 +#define TxHighPwrLevel_15 5 +#define TxHighPwrLevel_35 6 +#define TxHighPwrLevel_50 7 +#define TxHighPwrLevel_70 8 +#define TxHighPwrLevel_100 9 + +/* 3=========================================================== */ +/* 3 Rate Adaptive */ +/* 3=========================================================== */ +#define DM_RATR_STA_INIT 0 +#define DM_RATR_STA_HIGH 1 +#define DM_RATR_STA_MIDDLE 2 +#define DM_RATR_STA_LOW 3 + +/* 3=========================================================== */ +/* 3 BB Power Save */ +/* 3=========================================================== */ + + +enum dm_1r_cca { + CCA_1R = 0, + CCA_2R = 1, + CCA_MAX = 2, +}; + +enum dm_rf { + RF_Save = 0, + RF_Normal = 1, + RF_MAX = 2, +}; + +/* 3=========================================================== */ +/* 3 Antenna Diversity */ +/* 3=========================================================== */ +enum dm_swas { + Antenna_A = 1, + Antenna_B = 2, + Antenna_MAX = 3, +}; + +/* Maximal number of antenna detection mechanism needs to perform. */ +#define MAX_ANTENNA_DETECTION_CNT 10 + +/* Extern Global Variables. */ +#define OFDM_TABLE_SIZE_92C 37 +#define OFDM_TABLE_SIZE_92D 43 +#define CCK_TABLE_SIZE 33 + +extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D]; +extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; +extern u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; + +/* check Sta pointer valid or not */ +#define IS_STA_VALID(pSta) (pSta) +/* 20100514 Joseph: Add definition for antenna switching test after link. */ +/* This indicates two different the steps. */ +/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the + * signal on the air. */ +/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in + * SWAW_STEP_PEAK */ +/* with original RSSI to determine if it is necessary to switch antenna. */ +#define SWAW_STEP_PEAK 0 +#define SWAW_STEP_DETERMINE 1 + +void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI); +void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres); + +void ODM_SetAntenna(struct odm_dm_struct *pDM_Odm, u8 Antenna); + + +#define dm_RF_Saving ODM_RF_Saving +void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal); + +#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink +void ODM_SwAntDivRestAfterLink(struct odm_dm_struct *pDM_Odm); + +#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck +void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm); + +bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, + bool bForceUpdate, u8 *pRATRState); + +#define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi +void ODM_SwAntDivChkPerPktRssi(struct odm_dm_struct *pDM_Odm, u8 StationID, + struct odm_phy_status_info *pPhyInfo); + +u32 ConvertTo_dB(u32 Value); + +u32 GetPSDData(struct odm_dm_struct *pDM_Odm, unsigned int point, + u8 initial_gain_psd); + +void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm); + +u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, + u32 ra_mask, u8 rssi_level); + +void ODM_DMInit(struct odm_dm_struct *pDM_Odm); + +void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm); + +void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, + enum odm_common_info_def CmnInfo, u32 Value); + +void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm, + enum odm_common_info_def CmnInfo, void *pValue); + +void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, + enum odm_common_info_def CmnInfo, + u16 Index, void *pValue); + +void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value); + +void ODM_InitAllTimers(struct odm_dm_struct *pDM_Odm); + +void ODM_CancelAllTimers(struct odm_dm_struct *pDM_Odm); + +void ODM_ReleaseAllTimers(struct odm_dm_struct *pDM_Odm); + +void ODM_ResetIQKResult(struct odm_dm_struct *pDM_Odm); + +void ODM_AntselStatistics_88C(struct odm_dm_struct *pDM_Odm, u8 MacId, + u32 PWDBAll, bool isCCKrate); + +void ODM_SingleDualAntennaDefaultSetting(struct odm_dm_struct *pDM_Odm); + +bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode); + +void odm_dtc(struct odm_dm_struct *pDM_Odm); + +#endif diff --git a/drivers/staging/rtl8188eu/include/odm_HWConfig.h b/drivers/staging/rtl8188eu/include/odm_HWConfig.h new file mode 100644 index 0000000..63779f5 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm_HWConfig.h @@ -0,0 +1,132 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HALHWOUTSRC_H__ +#define __HALHWOUTSRC_H__ + +/* Definition */ +/* CCK Rates, TxHT = 0 */ +#define DESC92C_RATE1M 0x00 +#define DESC92C_RATE2M 0x01 +#define DESC92C_RATE5_5M 0x02 +#define DESC92C_RATE11M 0x03 + +/* OFDM Rates, TxHT = 0 */ +#define DESC92C_RATE6M 0x04 +#define DESC92C_RATE9M 0x05 +#define DESC92C_RATE12M 0x06 +#define DESC92C_RATE18M 0x07 +#define DESC92C_RATE24M 0x08 +#define DESC92C_RATE36M 0x09 +#define DESC92C_RATE48M 0x0a +#define DESC92C_RATE54M 0x0b + +/* MCS Rates, TxHT = 1 */ +#define DESC92C_RATEMCS0 0x0c +#define DESC92C_RATEMCS1 0x0d +#define DESC92C_RATEMCS2 0x0e +#define DESC92C_RATEMCS3 0x0f +#define DESC92C_RATEMCS4 0x10 +#define DESC92C_RATEMCS5 0x11 +#define DESC92C_RATEMCS6 0x12 +#define DESC92C_RATEMCS7 0x13 +#define DESC92C_RATEMCS8 0x14 +#define DESC92C_RATEMCS9 0x15 +#define DESC92C_RATEMCS10 0x16 +#define DESC92C_RATEMCS11 0x17 +#define DESC92C_RATEMCS12 0x18 +#define DESC92C_RATEMCS13 0x19 +#define DESC92C_RATEMCS14 0x1a +#define DESC92C_RATEMCS15 0x1b +#define DESC92C_RATEMCS15_SG 0x1c +#define DESC92C_RATEMCS32 0x20 + +/* structure and define */ + +struct phy_rx_agc_info { + #ifdef __LITTLE_ENDIAN + u8 gain:7, trsw:1; + #else + u8 trsw:1, gain:7; + #endif +}; + +struct phy_status_rpt { + struct phy_rx_agc_info path_agc[2]; + u8 ch_corr[2]; + u8 cck_sig_qual_ofdm_pwdb_all; + u8 cck_agc_rpt_ofdm_cfosho_a; + u8 cck_rpt_b_ofdm_cfosho_b; + u8 rsvd_1;/* ch_corr_msb; */ + u8 noise_power_db_msb; + u8 path_cfotail[2]; + u8 pcts_mask[2]; + s8 stream_rxevm[2]; + u8 path_rxsnr[2]; + u8 noise_power_db_lsb; + u8 rsvd_2[3]; + u8 stream_csi[2]; + u8 stream_target_csi[2]; + s8 sig_evm; + u8 rsvd_3; + +#ifdef __LITTLE_ENDIAN + u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ + u8 sgi_en:1; + u8 rxsc:2; + u8 idle_long:1; + u8 r_ant_train_en:1; + u8 ant_sel_b:1; + u8 ant_sel:1; +#else /* _BIG_ENDIAN_ */ + u8 ant_sel:1; + u8 ant_sel_b:1; + u8 r_ant_train_en:1; + u8 idle_long:1; + u8 rxsc:2; + u8 sgi_en:1; + u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ +#endif +}; + +void odm_Init_RSSIForDM(struct odm_dm_struct *pDM_Odm); + +void ODM_PhyStatusQuery(struct odm_dm_struct *pDM_Odm, + struct odm_phy_status_info *pPhyInfo, + u8 *pPhyStatus, + struct odm_per_pkt_info *pPktinfo); + +void ODM_MacStatusQuery(struct odm_dm_struct *pDM_Odm, + u8 *pMacStatus, + u8 MacID, + bool bPacketMatchBSSID, + bool bPacketToSelf, + bool bPacketBeacon); + +enum HAL_STATUS ODM_ConfigRFWithHeaderFile(struct odm_dm_struct *pDM_Odm, + enum ODM_RF_RADIO_PATH Content, + enum ODM_RF_RADIO_PATH eRFPath); + +enum HAL_STATUS ODM_ConfigBBWithHeaderFile(struct odm_dm_struct *pDM_Odm, + enum odm_bb_config_type ConfigType); + +enum HAL_STATUS ODM_ConfigMACWithHeaderFile(struct odm_dm_struct *pDM_Odm); + +#endif diff --git a/drivers/staging/rtl8188eu/include/odm_RTL8188E.h b/drivers/staging/rtl8188eu/include/odm_RTL8188E.h new file mode 100644 index 0000000..f96ad5a --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm_RTL8188E.h @@ -0,0 +1,56 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ODM_RTL8188E_H__ +#define __ODM_RTL8188E_H__ + +#define MAIN_ANT 0 +#define AUX_ANT 1 +#define MAIN_ANT_CG_TRX 1 +#define AUX_ANT_CG_TRX 0 +#define MAIN_ANT_CGCS_RX 0 +#define AUX_ANT_CGCS_RX 1 + +void ODM_DIG_LowerBound_88E(struct odm_dm_struct *pDM_Odm); + +void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *pDM_Odm); + +void ODM_AntennaDiversity_88E(struct odm_dm_struct *pDM_Odm); + +void ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct *pDM_Odm, u8 *pDesc, + u8 macId); + +void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *pDM_Odm, u8 Ant); + +void ODM_AntselStatistics_88E(struct odm_dm_struct *pDM_Odm, u8 antsel_tr_mux, + u32 MacId, u8 RxPWDBAll); + +void odm_FastAntTraining(struct odm_dm_struct *pDM_Odm); + +void odm_FastAntTrainingCallback(struct odm_dm_struct *pDM_Odm); + +void odm_FastAntTrainingWorkItemCallback(struct odm_dm_struct *pDM_Odm); + +void odm_PrimaryCCA_Init(struct odm_dm_struct *pDM_Odm); + +bool ODM_DynamicPrimaryCCA_DupRTS(struct odm_dm_struct *pDM_Odm); + +void odm_DynamicPrimaryCCA(struct odm_dm_struct *pDM_Odm); + +#endif diff --git a/drivers/staging/rtl8188eu/include/odm_RegConfig8188E.h b/drivers/staging/rtl8188eu/include/odm_RegConfig8188E.h new file mode 100644 index 0000000..727e6b2 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm_RegConfig8188E.h @@ -0,0 +1,43 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8188E +#define __INC_ODM_REGCONFIG_H_8188E + +void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data, + enum ODM_RF_RADIO_PATH RF_PATH, u32 RegAddr); + +void odm_ConfigRF_RadioA_8188E(struct odm_dm_struct *pDM_Odm, + u32 Addr, u32 Data); + +void odm_ConfigRF_RadioB_8188E(struct odm_dm_struct *pDM_Odm, + u32 Addr, u32 Data); + +void odm_ConfigMAC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u8 Data); + +void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, + u32 Bitmask, u32 Data); + +void odm_ConfigBB_PHY_REG_PG_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, + u32 Bitmask, u32 Data); + +void odm_ConfigBB_PHY_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, + u32 Bitmask, u32 Data); + +#endif diff --git a/drivers/staging/rtl8188eu/include/odm_RegDefine11AC.h b/drivers/staging/rtl8188eu/include/odm_RegDefine11AC.h new file mode 100644 index 0000000..f08775c --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm_RegDefine11AC.h @@ -0,0 +1,54 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_REGDEFINE11AC_H__ +#define __ODM_REGDEFINE11AC_H__ + +/* 2 RF REG LIST */ + + + +/* 2 BB REG LIST */ +/* PAGE 8 */ +/* PAGE 9 */ +#define ODM_REG_OFDM_FA_RST_11AC 0x9A4 +/* PAGE A */ +#define ODM_REG_CCK_CCA_11AC 0xA0A +#define ODM_REG_CCK_FA_RST_11AC 0xA2C +#define ODM_REG_CCK_FA_11AC 0xA5C +/* PAGE C */ +#define ODM_REG_IGI_A_11AC 0xC50 +/* PAGE E */ +#define ODM_REG_IGI_B_11AC 0xE50 +/* PAGE F */ +#define ODM_REG_OFDM_FA_11AC 0xF48 + + +/* 2 MAC REG LIST */ + + + + +/* DIG Related */ +#define ODM_BIT_IGI_11AC 0xFFFFFFFF + + + +#endif diff --git a/drivers/staging/rtl8188eu/include/odm_RegDefine11N.h b/drivers/staging/rtl8188eu/include/odm_RegDefine11N.h new file mode 100644 index 0000000..5a61f90 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm_RegDefine11N.h @@ -0,0 +1,171 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_REGDEFINE11N_H__ +#define __ODM_REGDEFINE11N_H__ + + +/* 2 RF REG LIST */ +#define ODM_REG_RF_MODE_11N 0x00 +#define ODM_REG_RF_0B_11N 0x0B +#define ODM_REG_CHNBW_11N 0x18 +#define ODM_REG_T_METER_11N 0x24 +#define ODM_REG_RF_25_11N 0x25 +#define ODM_REG_RF_26_11N 0x26 +#define ODM_REG_RF_27_11N 0x27 +#define ODM_REG_RF_2B_11N 0x2B +#define ODM_REG_RF_2C_11N 0x2C +#define ODM_REG_RXRF_A3_11N 0x3C +#define ODM_REG_T_METER_92D_11N 0x42 +#define ODM_REG_T_METER_88E_11N 0x42 + + + +/* 2 BB REG LIST */ +/* PAGE 8 */ +#define ODM_REG_BB_CTRL_11N 0x800 +#define ODM_REG_RF_PIN_11N 0x804 +#define ODM_REG_PSD_CTRL_11N 0x808 +#define ODM_REG_TX_ANT_CTRL_11N 0x80C +#define ODM_REG_BB_PWR_SAV5_11N 0x818 +#define ODM_REG_CCK_RPT_FORMAT_11N 0x824 +#define ODM_REG_RX_DEFUALT_A_11N 0x858 +#define ODM_REG_RX_DEFUALT_B_11N 0x85A +#define ODM_REG_BB_PWR_SAV3_11N 0x85C +#define ODM_REG_ANTSEL_CTRL_11N 0x860 +#define ODM_REG_RX_ANT_CTRL_11N 0x864 +#define ODM_REG_PIN_CTRL_11N 0x870 +#define ODM_REG_BB_PWR_SAV1_11N 0x874 +#define ODM_REG_ANTSEL_PATH_11N 0x878 +#define ODM_REG_BB_3WIRE_11N 0x88C +#define ODM_REG_SC_CNT_11N 0x8C4 +#define ODM_REG_PSD_DATA_11N 0x8B4 +/* PAGE 9 */ +#define ODM_REG_ANT_MAPPING1_11N 0x914 +#define ODM_REG_ANT_MAPPING2_11N 0x918 +/* PAGE A */ +#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 +#define ODM_REG_CCK_CCA_11N 0xA0A +#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C +#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10 +#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14 +#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22 +#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23 +#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24 +#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25 +#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26 +#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27 +#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28 +#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29 +#define ODM_REG_CCK_FA_RST_11N 0xA2C +#define ODM_REG_CCK_FA_MSB_11N 0xA58 +#define ODM_REG_CCK_FA_LSB_11N 0xA5C +#define ODM_REG_CCK_CCA_CNT_11N 0xA60 +#define ODM_REG_BB_PWR_SAV4_11N 0xA74 +/* PAGE B */ +#define ODM_REG_LNA_SWITCH_11N 0xB2C +#define ODM_REG_PATH_SWITCH_11N 0xB30 +#define ODM_REG_RSSI_CTRL_11N 0xB38 +#define ODM_REG_CONFIG_ANTA_11N 0xB68 +#define ODM_REG_RSSI_BT_11N 0xB9C +/* PAGE C */ +#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00 +#define ODM_REG_RX_PATH_11N 0xC04 +#define ODM_REG_TRMUX_11N 0xC08 +#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C +#define ODM_REG_RXIQI_MATRIX_11N 0xC14 +#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C +#define ODM_REG_IGI_A_11N 0xC50 +#define ODM_REG_ANTDIV_PARA2_11N 0xC54 +#define ODM_REG_IGI_B_11N 0xC58 +#define ODM_REG_ANTDIV_PARA3_11N 0xC5C +#define ODM_REG_BB_PWR_SAV2_11N 0xC70 +#define ODM_REG_RX_OFF_11N 0xC7C +#define ODM_REG_TXIQK_MATRIXA_11N 0xC80 +#define ODM_REG_TXIQK_MATRIXB_11N 0xC88 +#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 +#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C +#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 +#define ODM_REG_ANTDIV_PARA1_11N 0xCA4 +#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0 +/* PAGE D */ +#define ODM_REG_OFDM_FA_RSTD_11N 0xD00 +#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0 +#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4 +#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8 +/* PAGE E */ +#define ODM_REG_TXAGC_A_6_18_11N 0xE00 +#define ODM_REG_TXAGC_A_24_54_11N 0xE04 +#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08 +#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10 +#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14 +#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18 +#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C +#define ODM_REG_FPGA0_IQK_11N 0xE28 +#define ODM_REG_TXIQK_TONE_A_11N 0xE30 +#define ODM_REG_RXIQK_TONE_A_11N 0xE34 +#define ODM_REG_TXIQK_PI_A_11N 0xE38 +#define ODM_REG_RXIQK_PI_A_11N 0xE3C +#define ODM_REG_TXIQK_11N 0xE40 +#define ODM_REG_RXIQK_11N 0xE44 +#define ODM_REG_IQK_AGC_PTS_11N 0xE48 +#define ODM_REG_IQK_AGC_RSP_11N 0xE4C +#define ODM_REG_BLUETOOTH_11N 0xE6C +#define ODM_REG_RX_WAIT_CCA_11N 0xE70 +#define ODM_REG_TX_CCK_RFON_11N 0xE74 +#define ODM_REG_TX_CCK_BBON_11N 0xE78 +#define ODM_REG_OFDM_RFON_11N 0xE7C +#define ODM_REG_OFDM_BBON_11N 0xE80 +#define ODM_REG_TX2RX_11N 0xE84 +#define ODM_REG_TX2TX_11N 0xE88 +#define ODM_REG_RX_CCK_11N 0xE8C +#define ODM_REG_RX_OFDM_11N 0xED0 +#define ODM_REG_RX_WAIT_RIFS_11N 0xED4 +#define ODM_REG_RX2RX_11N 0xED8 +#define ODM_REG_STANDBY_11N 0xEDC +#define ODM_REG_SLEEP_11N 0xEE0 +#define ODM_REG_PMPD_ANAEN_11N 0xEEC + + + + + + + +/* 2 MAC REG LIST */ +#define ODM_REG_BB_RST_11N 0x02 +#define ODM_REG_ANTSEL_PIN_11N 0x4C +#define ODM_REG_EARLY_MODE_11N 0x4D0 +#define ODM_REG_RSSI_MONITOR_11N 0x4FE +#define ODM_REG_EDCA_VO_11N 0x500 +#define ODM_REG_EDCA_VI_11N 0x504 +#define ODM_REG_EDCA_BE_11N 0x508 +#define ODM_REG_EDCA_BK_11N 0x50C +#define ODM_REG_TXPAUSE_11N 0x522 +#define ODM_REG_RESP_TX_11N 0x6D8 +#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0 +#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4 + + +/* DIG Related */ +#define ODM_BIT_IGI_11N 0x0000007F + + +#endif diff --git a/drivers/staging/rtl8188eu/include/odm_debug.h b/drivers/staging/rtl8188eu/include/odm_debug.h new file mode 100644 index 0000000..a9ba6df --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm_debug.h @@ -0,0 +1,145 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __ODM_DBG_H__ +#define __ODM_DBG_H__ + + +/* */ +/* Define the debug levels */ +/* */ +/* 1. DBG_TRACE and DBG_LOUD are used for normal cases. */ +/* They can help SW engineer to develope or trace states changed */ +/* and also help HW enginner to trace every operation to and from HW, */ +/* e.g IO, Tx, Rx. */ +/* */ +/* 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, */ +/* which help us to debug SW or HW. */ + +/* Never used in a call to ODM_RT_TRACE()! */ +#define ODM_DBG_OFF 1 + +/* Fatal bug. */ +/* For example, Tx/Rx/IO locked up, OS hangs, memory access violation, */ +/* resource allocation failed, unexpected HW behavior, HW BUG and so on. */ +#define ODM_DBG_SERIOUS 2 + +/* Abnormal, rare, or unexpeted cases. */ +/* For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. */ +#define ODM_DBG_WARNING 3 + +/* Normal case with useful information about current SW or HW state. */ +/* For example, Tx/Rx descriptor to fill, Tx/Rx descr. completed status, */ +/* SW protocol state change, dynamic mechanism state change and so on. */ +/* */ +#define ODM_DBG_LOUD 4 + +/* Normal case with detail execution flow or information. */ +#define ODM_DBG_TRACE 5 + +/* Define the tracing components */ +/* BB Functions */ +#define ODM_COMP_DIG BIT0 +#define ODM_COMP_RA_MASK BIT1 +#define ODM_COMP_DYNAMIC_TXPWR BIT2 +#define ODM_COMP_FA_CNT BIT3 +#define ODM_COMP_RSSI_MONITOR BIT4 +#define ODM_COMP_CCK_PD BIT5 +#define ODM_COMP_ANT_DIV BIT6 +#define ODM_COMP_PWR_SAVE BIT7 +#define ODM_COMP_PWR_TRA BIT8 +#define ODM_COMP_RATE_ADAPTIVE BIT9 +#define ODM_COMP_PATH_DIV BIT10 +#define ODM_COMP_PSD BIT11 +#define ODM_COMP_DYNAMIC_PRICCA BIT12 +#define ODM_COMP_RXHP BIT13 +/* MAC Functions */ +#define ODM_COMP_EDCA_TURBO BIT16 +#define ODM_COMP_EARLY_MODE BIT17 +/* RF Functions */ +#define ODM_COMP_TX_PWR_TRACK BIT24 +#define ODM_COMP_RX_GAIN_TRACK BIT25 +#define ODM_COMP_CALIBRATION BIT26 +/* Common Functions */ +#define ODM_COMP_COMMON BIT30 +#define ODM_COMP_INIT BIT31 + +/*------------------------Export Marco Definition---------------------------*/ +#define DbgPrint pr_info +#define RT_PRINTK(fmt, args...) \ + DbgPrint( "%s(): " fmt, __func__, ## args); + +#ifndef ASSERT + #define ASSERT(expr) +#endif + +#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \ + if (((comp) & pDM_Odm->DebugComponents) && \ + (level <= pDM_Odm->DebugLevel)) { \ + if (pDM_Odm->SupportICType == ODM_RTL8192C) \ + DbgPrint("[ODM-92C] "); \ + else if (pDM_Odm->SupportICType == ODM_RTL8192D) \ + DbgPrint("[ODM-92D] "); \ + else if (pDM_Odm->SupportICType == ODM_RTL8723A) \ + DbgPrint("[ODM-8723A] "); \ + else if (pDM_Odm->SupportICType == ODM_RTL8188E) \ + DbgPrint("[ODM-8188E] "); \ + else if (pDM_Odm->SupportICType == ODM_RTL8812) \ + DbgPrint("[ODM-8812] "); \ + else if (pDM_Odm->SupportICType == ODM_RTL8821) \ + DbgPrint("[ODM-8821] "); \ + RT_PRINTK fmt; \ + } + +#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \ + if (((comp) & pDM_Odm->DebugComponents) && \ + (level <= pDM_Odm->DebugLevel)) { \ + RT_PRINTK fmt; \ + } + +#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \ + if (!(expr)) { \ + DbgPrint( "Assertion failed! %s at ......\n", #expr); \ + DbgPrint( " ......%s,%s,line=%d\n", __FILE__, \ + __func__, __LINE__); \ + RT_PRINTK fmt; \ + ASSERT(false); \ + } +#define ODM_dbg_enter() { DbgPrint("==> %s\n", __func__); } +#define ODM_dbg_exit() { DbgPrint("<== %s\n", __func__); } +#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __func__, str); } + +#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \ + if (((comp) & pDM_Odm->DebugComponents) && \ + (level <= pDM_Odm->DebugLevel)) { \ + int __i; \ + u8 *__ptr = (u8 *)ptr; \ + DbgPrint("[ODM] "); \ + DbgPrint(title_str); \ + DbgPrint(" "); \ + for (__i = 0; __i < 6; __i++) \ + DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-");\ + DbgPrint("\n"); \ + } + +void ODM_InitDebugSetting(struct odm_dm_struct *pDM_Odm); + +#endif /* __ODM_DBG_H__ */ diff --git a/drivers/staging/rtl8188eu/include/odm_interface.h b/drivers/staging/rtl8188eu/include/odm_interface.h new file mode 100644 index 0000000..e5c8704 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm_interface.h @@ -0,0 +1,164 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_INTERFACE_H__ +#define __ODM_INTERFACE_H__ + +/* */ +/* =========== Constant/Structure/Enum/... Define */ +/* */ + +/* */ +/* =========== Macro Define */ +/* */ + +#define _reg_all(_name) ODM_##_name +#define _reg_ic(_name, _ic) ODM_##_name##_ic +#define _bit_all(_name) BIT_##_name +#define _bit_ic(_name, _ic) BIT_##_name##_ic + +/* _cat: implemented by Token-Pasting Operator. */ + +/*=================================== + +#define ODM_REG_DIG_11N 0xC50 +#define ODM_REG_DIG_11AC 0xDDD + +ODM_REG(DIG,_pDM_Odm) +=====================================*/ + +#define _reg_11N(_name) ODM_REG_##_name##_11N +#define _reg_11AC(_name) ODM_REG_##_name##_11AC +#define _bit_11N(_name) ODM_BIT_##_name##_11N +#define _bit_11AC(_name) ODM_BIT_##_name##_11AC + +#define _cat(_name, _ic_type, _func) \ + ( \ + ((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \ + _func##_11AC(_name) \ + ) + +/* _name: name of register or bit. */ +/* Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" */ +/* gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", + * depends on SupportICType. */ +#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) +#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) + +enum odm_h2c_cmd { + ODM_H2C_RSSI_REPORT = 0, + ODM_H2C_PSD_RESULT= 1, + ODM_H2C_PathDiv = 2, + ODM_MAX_H2CCMD +}; + +/* 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem. */ +/* Suggest HW team to use thread instead of workitem. Windows also support the feature. */ +typedef void (*RT_WORKITEM_CALL_BACK)(void *pContext); + +/* =========== Extern Variable ??? It should be forbidden. */ + +/* =========== EXtern Function Prototype */ + +u8 ODM_Read1Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr); + +u16 ODM_Read2Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr); + +u32 ODM_Read4Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr); + +void ODM_Write1Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u8 Data); + +void ODM_Write2Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u16 Data); + +void ODM_Write4Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 Data); + +void ODM_SetMACReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, + u32 BitMask, u32 Data); + +u32 ODM_GetMACReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask); + +void ODM_SetBBReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, + u32 BitMask, u32 Data); + +u32 ODM_GetBBReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask); + +void ODM_SetRFReg(struct odm_dm_struct *pDM_Odm, enum ODM_RF_RADIO_PATH eRFPath, + u32 RegAddr, u32 BitMask, u32 Data); + +u32 ODM_GetRFReg(struct odm_dm_struct *pDM_Odm, enum ODM_RF_RADIO_PATH eRFPath, + u32 RegAddr, u32 BitMask); + +/* Memory Relative Function. */ +void ODM_AllocateMemory(struct odm_dm_struct *pDM_Odm, void **pPtr, u32 length); +void ODM_FreeMemory(struct odm_dm_struct *pDM_Odm, void *pPtr, u32 length); + +s32 ODM_CompareMemory(struct odm_dm_struct *pDM_Odm, void *pBuf1, void *pBuf2, + u32 length); + +/* ODM MISC-spin lock relative API. */ +void ODM_AcquireSpinLock(struct odm_dm_struct *pDM_Odm, + enum RT_SPINLOCK_TYPE type); + +void ODM_ReleaseSpinLock(struct odm_dm_struct *pDM_Odm, + enum RT_SPINLOCK_TYPE type); + +/* ODM MISC-workitem relative API. */ +void ODM_InitializeWorkItem(struct odm_dm_struct *pDM_Odm, void *pRtWorkItem, + RT_WORKITEM_CALL_BACK RtWorkItemCallback, + void *pContext, const char *szID); + +void ODM_StartWorkItem(void *pRtWorkItem); + +void ODM_StopWorkItem(void *pRtWorkItem); + +void ODM_FreeWorkItem(void *pRtWorkItem); + +void ODM_ScheduleWorkItem(void *pRtWorkItem); + +void ODM_IsWorkItemScheduled(void *pRtWorkItem); + +/* ODM Timer relative API. */ +void ODM_StallExecution(u32 usDelay); + +void ODM_delay_ms(u32 ms); + +void ODM_delay_us(u32 us); + +void ODM_sleep_ms(u32 ms); + +void ODM_sleep_us(u32 us); + +void ODM_SetTimer(struct odm_dm_struct *pDM_Odm, struct timer_list *pTimer, + u32 msDelay); + +void ODM_InitializeTimer(struct odm_dm_struct *pDM_Odm, + struct timer_list *pTimer, void *CallBackFunc, + void *pContext, const char *szID); + +void ODM_CancelTimer(struct odm_dm_struct *pDM_Odm, struct timer_list *pTimer); + +void ODM_ReleaseTimer(struct odm_dm_struct *pDM_Odm, struct timer_list *pTimer); + +/* ODM FW relative API. */ +u32 ODM_FillH2CCmd(u8 *pH2CBuffer, u32 H2CBufferLen, u32 CmdNum, + u32 *pElementID, u32 *pCmdLen, u8 **pCmbBuffer, + u8 *CmdStartSeq); + +#endif /* __ODM_INTERFACE_H__ */ diff --git a/drivers/staging/rtl8188eu/include/odm_precomp.h b/drivers/staging/rtl8188eu/include/odm_precomp.h new file mode 100644 index 0000000..520cbba --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm_precomp.h @@ -0,0 +1,104 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_PRECOMP_H__ +#define __ODM_PRECOMP_H__ + +#include "odm_types.h" + +#define TEST_FALG___ 1 + +/* 2 Config Flags and Structs - defined by each ODM Type */ + +#include +#include +#include + +/* 2 Hardware Parameter Files */ + +#include "Hal8188EFWImg_CE.h" + + +/* 2 OutSrc Header Files */ + +#include "odm.h" +#include "odm_HWConfig.h" +#include "odm_debug.h" +#include "odm_RegDefine11AC.h" +#include "odm_RegDefine11N.h" + +#include "HalPhyRf.h" +#include "HalPhyRf_8188e.h"/* for IQK,LCK,Power-tracking */ +#include "Hal8188ERateAdaptive.h"/* for RA,Power training */ +#include "rtl8188e_hal.h" + +#include "odm_interface.h" +#include "odm_reg.h" + +#include "HalHWImg8188E_MAC.h" +#include "HalHWImg8188E_RF.h" +#include "HalHWImg8188E_BB.h" +#include "Hal8188EReg.h" + +#include "odm_RegConfig8188E.h" +#include "odm_RTL8188E.h" + +void odm_CmnInfoHook_Debug(struct odm_dm_struct *pDM_Odm); +void odm_CmnInfoInit_Debug(struct odm_dm_struct *pDM_Odm); +void odm_DIGInit(struct odm_dm_struct *pDM_Odm); +void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm); +void odm_DynamicBBPowerSavingInit(struct odm_dm_struct *pDM_Odm); +void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm); +void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm); +void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm); +void odm_SwAntDivInit_NIC(struct odm_dm_struct *pDM_Odm); +void odm_GlobalAdapterCheck(void); +void odm_CmnInfoUpdate_Debug(struct odm_dm_struct *pDM_Odm); +void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm); +void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm); +void odm_DIG(struct odm_dm_struct *pDM_Odm); +void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm); +void odm_RefreshRateAdaptiveMaskMP(struct odm_dm_struct *pDM_Odm); +void odm_DynamicBBPowerSaving(struct odm_dm_struct *pDM_Odm); +void odm_SwAntDivChkAntSwitch(struct odm_dm_struct *pDM_Odm, u8 Step); +void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm); +void odm_DynamicTxPower(struct odm_dm_struct *pDM_Odm); +void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm); +void odm_SwAntDivInit(struct odm_dm_struct *pDM_Odm); +void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm); +void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm); +void odm_1R_CCA(struct odm_dm_struct *pDM_Odm); +void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm); +void odm_RefreshRateAdaptiveMaskAPADSL(struct odm_dm_struct *pDM_Odm); +void odm_DynamicTxPowerNIC(struct odm_dm_struct *pDM_Odm); +void odm_DynamicTxPowerAP(struct odm_dm_struct *pDM_Odm); +void odm_RSSIMonitorCheckMP(struct odm_dm_struct *pDM_Odm); +void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm); +void odm_RSSIMonitorCheckAP(struct odm_dm_struct *pDM_Odm); +void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm); +void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm); +void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm); +void odm_TXPowerTrackingCheckMP(struct odm_dm_struct *pDM_Odm); +void odm_TXPowerTrackingCheckAP(struct odm_dm_struct *pDM_Odm); +void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext); +void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm); +void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm); + +#endif /* __ODM_PRECOMP_H__ */ diff --git a/drivers/staging/rtl8188eu/include/odm_reg.h b/drivers/staging/rtl8188eu/include/odm_reg.h new file mode 100644 index 0000000..89bc46b --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm_reg.h @@ -0,0 +1,119 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/* */ +/* File Name: odm_reg.h */ +/* */ +/* Description: */ +/* */ +/* This file is for general register definition. */ +/* */ +/* */ +/* */ +#ifndef __HAL_ODM_REG_H__ +#define __HAL_ODM_REG_H__ + +/* */ +/* Register Definition */ +/* */ + +/* MAC REG */ +#define ODM_BB_RESET 0x002 +#define ODM_DUMMY 0x4fe +#define ODM_EDCA_VO_PARAM 0x500 +#define ODM_EDCA_VI_PARAM 0x504 +#define ODM_EDCA_BE_PARAM 0x508 +#define ODM_EDCA_BK_PARAM 0x50C +#define ODM_TXPAUSE 0x522 + +/* BB REG */ +#define ODM_FPGA_PHY0_PAGE8 0x800 +#define ODM_PSD_SETTING 0x808 +#define ODM_AFE_SETTING 0x818 +#define ODM_TXAGC_B_6_18 0x830 +#define ODM_TXAGC_B_24_54 0x834 +#define ODM_TXAGC_B_MCS32_5 0x838 +#define ODM_TXAGC_B_MCS0_MCS3 0x83c +#define ODM_TXAGC_B_MCS4_MCS7 0x848 +#define ODM_TXAGC_B_MCS8_MCS11 0x84c +#define ODM_ANALOG_REGISTER 0x85c +#define ODM_RF_INTERFACE_OUTPUT 0x860 +#define ODM_TXAGC_B_MCS12_MCS15 0x868 +#define ODM_TXAGC_B_11_A_2_11 0x86c +#define ODM_AD_DA_LSB_MASK 0x874 +#define ODM_ENABLE_3_WIRE 0x88c +#define ODM_PSD_REPORT 0x8b4 +#define ODM_R_ANT_SELECT 0x90c +#define ODM_CCK_ANT_SELECT 0xa07 +#define ODM_CCK_PD_THRESH 0xa0a +#define ODM_CCK_RF_REG1 0xa11 +#define ODM_CCK_MATCH_FILTER 0xa20 +#define ODM_CCK_RAKE_MAC 0xa2e +#define ODM_CCK_CNT_RESET 0xa2d +#define ODM_CCK_TX_DIVERSITY 0xa2f +#define ODM_CCK_FA_CNT_MSB 0xa5b +#define ODM_CCK_FA_CNT_LSB 0xa5c +#define ODM_CCK_NEW_FUNCTION 0xa75 +#define ODM_OFDM_PHY0_PAGE_C 0xc00 +#define ODM_OFDM_RX_ANT 0xc04 +#define ODM_R_A_RXIQI 0xc14 +#define ODM_R_A_AGC_CORE1 0xc50 +#define ODM_R_A_AGC_CORE2 0xc54 +#define ODM_R_B_AGC_CORE1 0xc58 +#define ODM_R_AGC_PAR 0xc70 +#define ODM_R_HTSTF_AGC_PAR 0xc7c +#define ODM_TX_PWR_TRAINING_A 0xc90 +#define ODM_TX_PWR_TRAINING_B 0xc98 +#define ODM_OFDM_FA_CNT1 0xcf0 +#define ODM_OFDM_PHY0_PAGE_D 0xd00 +#define ODM_OFDM_FA_CNT2 0xda0 +#define ODM_OFDM_FA_CNT3 0xda4 +#define ODM_OFDM_FA_CNT4 0xda8 +#define ODM_TXAGC_A_6_18 0xe00 +#define ODM_TXAGC_A_24_54 0xe04 +#define ODM_TXAGC_A_1_MCS32 0xe08 +#define ODM_TXAGC_A_MCS0_MCS3 0xe10 +#define ODM_TXAGC_A_MCS4_MCS7 0xe14 +#define ODM_TXAGC_A_MCS8_MCS11 0xe18 +#define ODM_TXAGC_A_MCS12_MCS15 0xe1c + +/* RF REG */ +#define ODM_GAIN_SETTING 0x00 +#define ODM_CHANNEL 0x18 + +/* Ant Detect Reg */ +#define ODM_DPDT 0x300 + +/* PSD Init */ +#define ODM_PSDREG 0x808 + +/* 92D Path Div */ +#define PATHDIV_REG 0xB30 +#define PATHDIV_TRI 0xBA0 + + +/* */ +/* Bitmap Definition */ +/* */ + +#define BIT_FA_RESET BIT0 + + + +#endif diff --git a/drivers/staging/rtl8188eu/include/odm_types.h b/drivers/staging/rtl8188eu/include/odm_types.h new file mode 100644 index 0000000..78ee2ba --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm_types.h @@ -0,0 +1,62 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ODM_TYPES_H__ +#define __ODM_TYPES_H__ + +/* */ +/* Define Different SW team support */ +/* */ +#define ODM_AP 0x01 /* BIT0 */ +#define ODM_ADSL 0x02 /* BIT1 */ +#define ODM_CE 0x04 /* BIT2 */ +#define ODM_MP 0x08 /* BIT3 */ + +#define RT_PCI_INTERFACE 1 +#define RT_USB_INTERFACE 2 +#define RT_SDIO_INTERFACE 3 + +enum HAL_STATUS { + HAL_STATUS_SUCCESS, + HAL_STATUS_FAILURE, +}; + +enum RT_SPINLOCK_TYPE { + RT_TEMP = 1, +}; + +#include + +#define DEV_BUS_TYPE RT_USB_INTERFACE + +#define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value) +#define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value) +#define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value) + +/* define useless flag to avoid compile warning */ +#define USE_WORKITEM 0 +#define FOR_BRAZIL_PRETEST 0 +#define BT_30_SUPPORT 0 +#define FPGA_TWO_MAC_VERIFICATION 0 + + +#endif /* __ODM_TYPES_H__ */ diff --git a/drivers/staging/rtl8188eu/include/osdep_intf.h b/drivers/staging/rtl8188eu/include/osdep_intf.h new file mode 100644 index 0000000..c4599c5 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/osdep_intf.h @@ -0,0 +1,83 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __OSDEP_INTF_H_ +#define __OSDEP_INTF_H_ + +#include +#include + +struct intf_priv { + u8 *intf_dev; + u32 max_iosz; /* USB2.0: 128, USB1.1: 64, SDIO:64 */ + u32 max_xmitsz; /* USB2.0: unlimited, SDIO:512 */ + u32 max_recvsz; /* USB2.0: unlimited, SDIO:512 */ + + u8 *io_rwmem; + u8 *allocated_io_rwmem; + u32 io_wsz; /* unit: 4bytes */ + u32 io_rsz;/* unit: 4bytes */ + u8 intf_status; + + void (*_bus_io)(u8 *priv); + +/* +Under Sync. IRP (SDIO/USB) +A protection mechanism is necessary for the io_rwmem(read/write protocol) + +Under Async. IRP (SDIO/USB) +The protection mechanism is through the pending queue. +*/ + struct mutex ioctl_mutex; + /* when in USB, IO is through interrupt in/out endpoints */ + struct usb_device *udev; + struct urb *piorw_urb; + u8 io_irp_cnt; + u8 bio_irp_pending; + struct semaphore io_retevt; + struct timer_list io_timer; + u8 bio_irp_timeout; + u8 bio_timer_cancel; +}; + +u8 rtw_init_drv_sw(struct adapter *padapter); +u8 rtw_free_drv_sw(struct adapter *padapter); +u8 rtw_reset_drv_sw(struct adapter *padapter); + +u32 rtw_start_drv_threads(struct adapter *padapter); +void rtw_stop_drv_threads (struct adapter *padapter); +void rtw_cancel_all_timer(struct adapter *padapter); + +int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); + +int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname); +struct net_device *rtw_init_netdev(struct adapter *padapter); +u16 rtw_recv_select_queue(struct sk_buff *skb); +void rtw_proc_init_one(struct net_device *dev); +void rtw_proc_remove_one(struct net_device *dev); + +void rtw_ips_dev_unload(struct adapter *padapter); + +int rtw_ips_pwr_up(struct adapter *padapter); +void rtw_ips_pwr_down(struct adapter *padapter); +int rtw_hw_suspend(struct adapter *padapter); +int rtw_hw_resume(struct adapter *padapter); + +#endif /* _OSDEP_INTF_H_ */ diff --git a/drivers/staging/rtl8188eu/include/osdep_service.h b/drivers/staging/rtl8188eu/include/osdep_service.h new file mode 100644 index 0000000..1be33b7 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/osdep_service.h @@ -0,0 +1,548 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __OSDEP_SERVICE_H_ +#define __OSDEP_SERVICE_H_ + +#include + +#define _FAIL 0 +#define _SUCCESS 1 +#define RTW_RX_HANDLED 2 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* Necessary because we use the proc fs */ +#include /* for struct tasklet_struct */ +#include +#include + +#include +#include + +struct __queue { + struct list_head queue; + spinlock_t lock; +}; + +#define thread_exit() complete_and_exit(NULL, 0) + +static inline struct list_head *get_next(struct list_head *list) +{ + return list->next; +} + +static inline struct list_head *get_list_head(struct __queue *queue) +{ + return (&(queue->queue)); +} + + +#define LIST_CONTAINOR(ptr, type, member) \ + ((type *)((char *)(ptr)-(size_t)(&((type *)0)->member))) + + +static inline void _enter_critical(spinlock_t *plock, unsigned long *pirqL) +{ + spin_lock_irqsave(plock, *pirqL); +} + +static inline void _exit_critical(spinlock_t *plock, unsigned long *pirqL) +{ + spin_unlock_irqrestore(plock, *pirqL); +} + +static inline void _enter_critical_ex(spinlock_t *plock, unsigned long *pirqL) +{ + spin_lock_irqsave(plock, *pirqL); +} + +static inline void _exit_critical_ex(spinlock_t *plock, unsigned long *pirqL) +{ + spin_unlock_irqrestore(plock, *pirqL); +} + +static inline void _enter_critical_bh(spinlock_t *plock, unsigned long *pirqL) +{ + spin_lock_bh(plock); +} + +static inline void _exit_critical_bh(spinlock_t *plock, unsigned long *pirqL) +{ + spin_unlock_bh(plock); +} + +static inline int _enter_critical_mutex(struct mutex *pmutex, unsigned long *pirqL) +{ + int ret; + + ret = mutex_lock_interruptible(pmutex); + return ret; +} + + +static inline void _exit_critical_mutex(struct mutex *pmutex, unsigned long *pirqL) +{ + mutex_unlock(pmutex); +} + +static inline void rtw_list_delete(struct list_head *plist) +{ + list_del_init(plist); +} + +static inline void _init_timer(struct timer_list *ptimer,struct net_device *nic_hdl,void *pfunc,void* cntx) +{ + ptimer->function = pfunc; + ptimer->data = (unsigned long)cntx; + init_timer(ptimer); +} + +static inline void _set_timer(struct timer_list *ptimer,u32 delay_time) +{ + mod_timer(ptimer , (jiffies+(delay_time*HZ/1000))); +} + +static inline void _cancel_timer(struct timer_list *ptimer,u8 *bcancelled) +{ + del_timer_sync(ptimer); + *bcancelled= true;/* true ==1; false==0 */ +} + +#define RTW_TIMER_HDL_ARGS void *FunctionContext +#define RTW_TIMER_HDL_NAME(name) rtw_##name##_timer_hdl +#define RTW_DECLARE_TIMER_HDL(name) void RTW_TIMER_HDL_NAME(name)(RTW_TIMER_HDL_ARGS) + +static inline void _init_workitem(struct work_struct *pwork, void *pfunc, void * cntx) +{ + INIT_WORK(pwork, pfunc); +} + +static inline void _set_workitem(struct work_struct *pwork) +{ + schedule_work(pwork); +} + +static inline void _cancel_workitem_sync(struct work_struct *pwork) +{ + cancel_work_sync(pwork); +} +/* */ +/* Global Mutex: can only be used at PASSIVE level. */ +/* */ + +#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + while (atomic_inc_return((atomic_t *)&(_MutexCounter)) != 1)\ + { \ + atomic_dec((atomic_t *)&(_MutexCounter)); \ + msleep(10); \ + } \ +} + +#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + atomic_dec((atomic_t *)&(_MutexCounter)); \ +} + +static inline int rtw_netif_queue_stopped(struct net_device *pnetdev) +{ + return netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) && + netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 1)) && + netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 2)) && + netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3)); +} + +static inline void rtw_netif_wake_queue(struct net_device *pnetdev) +{ + netif_tx_wake_all_queues(pnetdev); +} + +static inline void rtw_netif_start_queue(struct net_device *pnetdev) +{ + netif_tx_start_all_queues(pnetdev); +} + +static inline void rtw_netif_stop_queue(struct net_device *pnetdev) +{ + netif_tx_stop_all_queues(pnetdev); +} + +#ifndef BIT + #define BIT(x) ( 1 << (x)) +#endif + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 +#define BIT32 0x0100000000 +#define BIT33 0x0200000000 +#define BIT34 0x0400000000 +#define BIT35 0x0800000000 +#define BIT36 0x1000000000 + +extern int RTW_STATUS_CODE(int error_code); + +/* flags used for rtw_update_mem_stat() */ +enum { + MEM_STAT_VIR_ALLOC_SUCCESS, + MEM_STAT_VIR_ALLOC_FAIL, + MEM_STAT_VIR_FREE, + MEM_STAT_PHY_ALLOC_SUCCESS, + MEM_STAT_PHY_ALLOC_FAIL, + MEM_STAT_PHY_FREE, + MEM_STAT_TX, /* used to distinguish TX/RX, asigned from caller */ + MEM_STAT_TX_ALLOC_SUCCESS, + MEM_STAT_TX_ALLOC_FAIL, + MEM_STAT_TX_FREE, + MEM_STAT_RX, /* used to distinguish TX/RX, asigned from caller */ + MEM_STAT_RX_ALLOC_SUCCESS, + MEM_STAT_RX_ALLOC_FAIL, + MEM_STAT_RX_FREE +}; + +extern unsigned char MCS_rate_2R[16]; +extern unsigned char MCS_rate_1R[16]; +extern unsigned char RTW_WPA_OUI[]; +extern unsigned char WPA_TKIP_CIPHER[4]; +extern unsigned char RSN_TKIP_CIPHER[4]; + +#define rtw_update_mem_stat(flag, sz) do {} while (0) +u8 *_rtw_vmalloc(u32 sz); +u8 *_rtw_zvmalloc(u32 sz); +void _rtw_vmfree(u8 *pbuf, u32 sz); +u8 *_rtw_zmalloc(u32 sz); +u8 *_rtw_malloc(u32 sz); +void _rtw_mfree(u8 *pbuf, u32 sz); +#define rtw_vmalloc(sz) _rtw_vmalloc((sz)) +#define rtw_zvmalloc(sz) _rtw_zvmalloc((sz)) +#define rtw_vmfree(pbuf, sz) _rtw_vmfree((pbuf), (sz)) +#define rtw_malloc(sz) _rtw_malloc((sz)) +#define rtw_zmalloc(sz) _rtw_zmalloc((sz)) +#define rtw_mfree(pbuf, sz) _rtw_mfree((pbuf), (sz)) + +void *rtw_malloc2d(int h, int w, int size); +void rtw_mfree2d(void *pbuf, int h, int w, int size); + +void _rtw_memcpy(void *dec, void *sour, u32 sz); +int _rtw_memcmp(void *dst, void *src, u32 sz); +void _rtw_memset(void *pbuf, int c, u32 sz); + +void _rtw_init_listhead(struct list_head *list); +u32 rtw_is_list_empty(struct list_head *phead); +void rtw_list_insert_head(struct list_head *plist, struct list_head *phead); +void rtw_list_insert_tail(struct list_head *plist, struct list_head *phead); +void rtw_list_delete(struct list_head *plist); + +void _rtw_init_sema(struct semaphore *sema, int init_val); +void _rtw_free_sema(struct semaphore *sema); +void _rtw_up_sema(struct semaphore *sema); +u32 _rtw_down_sema(struct semaphore *sema); +void _rtw_mutex_init(struct mutex *pmutex); +void _rtw_mutex_free(struct mutex *pmutex); +void _rtw_spinlock_init(spinlock_t *plock); +void _rtw_spinlock_free(spinlock_t *plock); + +void _rtw_init_queue(struct __queue *pqueue); +u32 _rtw_queue_empty(struct __queue *pqueue); +u32 rtw_end_of_queue_search(struct list_head *queue, struct list_head *pelement); + +u32 rtw_get_current_time(void); +u32 rtw_systime_to_ms(u32 systime); +u32 rtw_ms_to_systime(u32 ms); +s32 rtw_get_passing_time_ms(u32 start); +s32 rtw_get_time_interval_ms(u32 start, u32 end); + +void rtw_sleep_schedulable(int ms); + +void rtw_msleep_os(int ms); +void rtw_usleep_os(int us); + +u32 rtw_atoi(u8 *s); + +void rtw_mdelay_os(int ms); +void rtw_udelay_os(int us); + +void rtw_yield_os(void); + +static inline unsigned char _cancel_timer_ex(struct timer_list *ptimer) +{ + return del_timer_sync(ptimer); +} + +static __inline void thread_enter(char *name) +{ +#ifdef daemonize + daemonize("%s", name); +#endif + allow_signal(SIGTERM); +} + +static inline void flush_signals_thread(void) +{ + if (signal_pending (current)) + flush_signals(current); +} + +static inline int res_to_status(int res) +{ + return res; +} + +#define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r)) +#define RND4(x) (((x >> 2) + (((x & 3) == 0) ? 0: 1)) << 2) + +static inline u32 _RND4(u32 sz) +{ + u32 val; + + val = ((sz >> 2) + ((sz & 3) ? 1: 0)) << 2; + return val; +} + +static inline u32 _RND8(u32 sz) +{ + u32 val; + + val = ((sz >> 3) + ((sz & 7) ? 1: 0)) << 3; + return val; +} + +static inline u32 _RND128(u32 sz) +{ + u32 val; + + val = ((sz >> 7) + ((sz & 127) ? 1: 0)) << 7; + return val; +} + +static inline u32 _RND256(u32 sz) +{ + u32 val; + + val = ((sz >> 8) + ((sz & 255) ? 1: 0)) << 8; + return val; +} + +static inline u32 _RND512(u32 sz) +{ + u32 val; + + val = ((sz >> 9) + ((sz & 511) ? 1: 0)) << 9; + return val; +} + +static inline u32 bitshift(u32 bitmask) +{ + u32 i; + + for (i = 0; i <= 31; i++) + if (((bitmask>>i) & 0x1) == 1) break; + return i; +} + +/* limitation of path length */ +#define PATH_LENGTH_MAX PATH_MAX + +void rtw_suspend_lock_init(void); +void rtw_suspend_lock_uninit(void); +void rtw_lock_suspend(void); +void rtw_unlock_suspend(void); + +/* Atomic integer operations */ +#define ATOMIC_T atomic_t + +void ATOMIC_SET(ATOMIC_T *v, int i); +int ATOMIC_READ(ATOMIC_T *v); +void ATOMIC_ADD(ATOMIC_T *v, int i); +void ATOMIC_SUB(ATOMIC_T *v, int i); +void ATOMIC_INC(ATOMIC_T *v); +void ATOMIC_DEC(ATOMIC_T *v); +int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i); +int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i); +int ATOMIC_INC_RETURN(ATOMIC_T *v); +int ATOMIC_DEC_RETURN(ATOMIC_T *v); + +/* File operation APIs, just for linux now */ +int rtw_is_file_readable(char *path); +int rtw_retrive_from_file(char *path, u8 __user *buf, u32 sz); +int rtw_store_to_file(char *path, u8 __user *buf, u32 sz); + +struct rtw_netdev_priv_indicator { + void *priv; + u32 sizeof_priv; +}; +struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, + void *old_priv); +struct net_device *rtw_alloc_etherdev(int sizeof_priv); + +#define rtw_netdev_priv(netdev) \ + (((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv) +void rtw_free_netdev(struct net_device *netdev); + +#define NDEV_FMT "%s" +#define NDEV_ARG(ndev) ndev->name +#define ADPT_FMT "%s" +#define ADPT_ARG(adapter) adapter->pnetdev->name +#define FUNC_NDEV_FMT "%s(%s)" +#define FUNC_NDEV_ARG(ndev) __func__, ndev->name +#define FUNC_ADPT_FMT "%s(%s)" +#define FUNC_ADPT_ARG(adapter) __func__, adapter->pnetdev->name + +#define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)),(sig), 1) + +u64 rtw_modular64(u64 x, u64 y); +u64 rtw_division64(u64 x, u64 y); + +/* Macros for handling unaligned memory accesses */ + +#define RTW_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1])) +#define RTW_PUT_BE16(a, val) \ + do { \ + (a)[0] = ((u16) (val)) >> 8; \ + (a)[1] = ((u16) (val)) & 0xff; \ + } while (0) + +#define RTW_GET_LE16(a) ((u16) (((a)[1] << 8) | (a)[0])) +#define RTW_PUT_LE16(a, val) \ + do { \ + (a)[1] = ((u16) (val)) >> 8; \ + (a)[0] = ((u16) (val)) & 0xff; \ + } while (0) + +#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \ + ((u32) (a)[2])) +#define RTW_PUT_BE24(a, val) \ + do { \ + (a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff); \ + (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ + (a)[2] = (u8) (((u32) (val)) & 0xff); \ + } while (0) + +#define RTW_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \ + (((u32) (a)[2]) << 8) | ((u32) (a)[3])) +#define RTW_PUT_BE32(a, val) \ + do { \ + (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ + (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ + (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ + (a)[3] = (u8) (((u32) (val)) & 0xff); \ + } while (0) + +#define RTW_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \ + (((u32) (a)[1]) << 8) | ((u32) (a)[0])) +#define RTW_PUT_LE32(a, val) \ + do { \ + (a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \ + (a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \ + (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ + (a)[0] = (u8) (((u32) (val)) & 0xff); \ + } while (0) + +#define RTW_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \ + (((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \ + (((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \ + (((u64) (a)[6]) << 8) | ((u64) (a)[7])) +#define RTW_PUT_BE64(a, val) \ + do { \ + (a)[0] = (u8) (((u64) (val)) >> 56); \ + (a)[1] = (u8) (((u64) (val)) >> 48); \ + (a)[2] = (u8) (((u64) (val)) >> 40); \ + (a)[3] = (u8) (((u64) (val)) >> 32); \ + (a)[4] = (u8) (((u64) (val)) >> 24); \ + (a)[5] = (u8) (((u64) (val)) >> 16); \ + (a)[6] = (u8) (((u64) (val)) >> 8); \ + (a)[7] = (u8) (((u64) (val)) & 0xff); \ + } while (0) + +#define RTW_GET_LE64(a) ((((u64) (a)[7]) << 56) | (((u64) (a)[6]) << 48) | \ + (((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \ + (((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \ + (((u64) (a)[1]) << 8) | ((u64) (a)[0])) + +void rtw_buf_free(u8 **buf, u32 *buf_len); +void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len); + +struct rtw_cbuf { + u32 write; + u32 read; + u32 size; + void *bufs[0]; +}; + +bool rtw_cbuf_full(struct rtw_cbuf *cbuf); +bool rtw_cbuf_empty(struct rtw_cbuf *cbuf); +bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf); +void *rtw_cbuf_pop(struct rtw_cbuf *cbuf); +struct rtw_cbuf *rtw_cbuf_alloc(u32 size); +int wifirate2_ratetbl_inx(unsigned char rate); + +#endif -- cgit v0.10.2