From a929dcf70ed74b8ff52b6fca54f6ebb463e829f4 Mon Sep 17 00:00:00 2001 From: Jason Liu Date: Tue, 11 Jan 2011 05:44:29 +0800 Subject: ARM i.MX50: Rename devices-mx50.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are devices-imx51.h and devices-imx53.h under arch/arm/mach-mx5 directory. So, had better rename devices-mx50.h to devices-imx50.h to follow the same naming convention with imx51 and imx53 part. Signed-off-by: Jason Liu Acked-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c index fd32e4c..e5bb600 100644 --- a/arch/arm/mach-mx5/board-mx50_rdp.c +++ b/arch/arm/mach-mx5/board-mx50_rdp.c @@ -35,7 +35,7 @@ #include #include -#include "devices-mx50.h" +#include "devices-imx50.h" static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = { /* SD1 */ diff --git a/arch/arm/mach-mx5/devices-imx50.h b/arch/arm/mach-mx5/devices-imx50.h new file mode 100644 index 0000000..98ab074 --- /dev/null +++ b/arch/arm/mach-mx5/devices-imx50.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include + +extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst; +#define imx50_add_imx_uart(id, pdata) \ + imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata) diff --git a/arch/arm/mach-mx5/devices-mx50.h b/arch/arm/mach-mx5/devices-mx50.h deleted file mode 100644 index 98ab074..0000000 --- a/arch/arm/mach-mx5/devices-mx50.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include -#include - -extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst; -#define imx50_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata) -- cgit v0.10.2 From 82c520dccf7fd5afcd95b941f48c25f38c162c77 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Fri, 14 Jan 2011 17:48:03 +0800 Subject: arm: mx50_rdp: add fec support Signed-off-by: Richard Zhao Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index de4fa992f..af8749b 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -157,6 +157,7 @@ config MACH_MX50_RDP select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select IMX_HAVE_PLATFORM_SPI_IMX + select IMX_HAVE_PLATFORM_FEC help Include support for MX50 reference design platform (RDP) board. This includes specific configurations for the board and its peripherals. diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c index e5bb600..3180d43 100644 --- a/arch/arm/mach-mx5/board-mx50_rdp.c +++ b/arch/arm/mach-mx5/board-mx50_rdp.c @@ -37,6 +37,9 @@ #include "devices-imx50.h" +#define FEC_EN IMX_GPIO_NR(6, 23) +#define FEC_RESET_B IMX_GPIO_NR(4, 12) + static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = { /* SD1 */ MX50_PAD_ECSPI2_SS0__GPIO_4_19, @@ -102,7 +105,7 @@ static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = { MX50_PAD_I2C3_SCL__USBOTG_OC, MX50_PAD_SSI_RXC__FEC_MDIO, - MX50_PAD_SSI_RXC__FEC_MDIO, + MX50_PAD_SSI_RXFS__FEC_MDC, MX50_PAD_DISP_D0__FEC_TXCLK, MX50_PAD_DISP_D1__FEC_RX_ER, MX50_PAD_DISP_D2__FEC_RX_DV, @@ -111,7 +114,6 @@ static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = { MX50_PAD_DISP_D5__FEC_TX_EN, MX50_PAD_DISP_D6__FEC_TXD1, MX50_PAD_DISP_D7__FEC_TXD0, - MX50_PAD_SSI_RXFS__FEC_MDC, MX50_PAD_I2C3_SDA__GPIO_6_23, MX50_PAD_ECSPI1_SCLK__GPIO_4_12, @@ -168,6 +170,20 @@ static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; +static const struct fec_platform_data fec_data __initconst = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + +static inline void mx50_rdp_fec_reset(void) +{ + gpio_request(FEC_EN, "fec-en"); + gpio_direction_output(FEC_EN, 0); + gpio_request(FEC_RESET_B, "fec-reset_b"); + gpio_direction_output(FEC_RESET_B, 0); + msleep(1); + gpio_set_value(FEC_RESET_B, 1); +} + /* * Board specific initialization. */ @@ -178,6 +194,8 @@ static void __init mx50_rdp_board_init(void) imx50_add_imx_uart(0, &uart_pdata); imx50_add_imx_uart(1, &uart_pdata); + mx50_rdp_fec_reset(); + imx50_add_fec(&fec_data); } static void __init mx50_rdp_timer_init(void) diff --git a/arch/arm/mach-mx5/devices-imx50.h b/arch/arm/mach-mx5/devices-imx50.h index 98ab074..e1093db 100644 --- a/arch/arm/mach-mx5/devices-imx50.h +++ b/arch/arm/mach-mx5/devices-imx50.h @@ -24,3 +24,8 @@ extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst; #define imx50_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata) + +extern const struct imx_fec_data imx50_fec_data __initconst; +#define imx50_add_fec(pdata) \ + imx_add_fec(&imx50_fec_data, pdata) + diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c index b50c351..4f52996 100644 --- a/arch/arm/plat-mxc/devices/platform-fec.c +++ b/arch/arm/plat-mxc/devices/platform-fec.c @@ -31,6 +31,11 @@ const struct imx_fec_data imx35_fec_data __initconst = imx_fec_data_entry_single(MX35); #endif +#ifdef CONFIG_SOC_IMX50 +const struct imx_fec_data imx50_fec_data __initconst = + imx_fec_data_entry_single(MX50); +#endif + #ifdef CONFIG_SOC_IMX51 const struct imx_fec_data imx51_fec_data __initconst = imx_fec_data_entry_single(MX51); -- cgit v0.10.2 From 98b7d550f292ae96f1058f19b83aadd6985a6fa0 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Fri, 14 Jan 2011 17:48:04 +0800 Subject: arm: mx50_rdp: add i2c bus support Signed-off-by: Richard Zhao Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c index 3180d43..75beef7 100644 --- a/arch/arm/mach-mx5/board-mx50_rdp.c +++ b/arch/arm/mach-mx5/board-mx50_rdp.c @@ -184,6 +184,10 @@ static inline void mx50_rdp_fec_reset(void) gpio_set_value(FEC_RESET_B, 1); } +static const struct imxi2c_platform_data i2c_data __initconst = { + .bitrate = 100000, +}; + /* * Board specific initialization. */ @@ -196,6 +200,9 @@ static void __init mx50_rdp_board_init(void) imx50_add_imx_uart(1, &uart_pdata); mx50_rdp_fec_reset(); imx50_add_fec(&fec_data); + imx50_add_imx_i2c(0, &i2c_data); + imx50_add_imx_i2c(1, &i2c_data); + imx50_add_imx_i2c(2, &i2c_data); } static void __init mx50_rdp_timer_init(void) diff --git a/arch/arm/mach-mx5/devices-imx50.h b/arch/arm/mach-mx5/devices-imx50.h index e1093db..c9e4282 100644 --- a/arch/arm/mach-mx5/devices-imx50.h +++ b/arch/arm/mach-mx5/devices-imx50.h @@ -29,3 +29,6 @@ extern const struct imx_fec_data imx50_fec_data __initconst; #define imx50_add_fec(pdata) \ imx_add_fec(&imx50_fec_data, pdata) +extern const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst; +#define imx50_add_imx_i2c(id, pdata) \ + imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata) diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c index 7ba94e1..2ab74f0 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c @@ -69,6 +69,16 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX35 */ +#ifdef CONFIG_SOC_IMX50 +const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst = { +#define imx50_imx_i2c_data_entry(_id, _hwid) \ + imx_imx_i2c_data_entry(MX50, _id, _hwid, SZ_4K) + imx50_imx_i2c_data_entry(0, 1), + imx50_imx_i2c_data_entry(1, 2), + imx50_imx_i2c_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX51 */ + #ifdef CONFIG_SOC_IMX51 const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { #define imx51_imx_i2c_data_entry(_id, _hwid) \ -- cgit v0.10.2 From 00c89c1d1831225bb89b0627e02d0d3f875ec0a4 Mon Sep 17 00:00:00 2001 From: Marc Reilly Date: Sat, 15 Jan 2011 11:36:57 +1100 Subject: Introduce VPR200 board. Signed-off-by: Marc Reilly Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 0717f88..de80d98 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -229,4 +229,18 @@ config MACH_EUKREA_MBIMXSD35_BASEBOARD endchoice +config MACH_VPR200 + bool "Support VPR200 platform" + select SOC_IMX35 + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + help + Include support for VPR200 platform. This includes specific + configurations for the board and its peripherals. + endif diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 8db1329..bc7294f 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -22,3 +22,4 @@ obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd-baseboard.o +obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o diff --git a/arch/arm/mach-mx3/mach-vpr200.c b/arch/arm/mach-mx3/mach-vpr200.c new file mode 100644 index 0000000..22ec78a --- /dev/null +++ b/arch/arm/mach-mx3/mach-vpr200.c @@ -0,0 +1,327 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix + * Copyright 2010 Creative Product Design + * + * Derived from mx35 3stack. + * Original author: Fabio Estevam + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "devices-imx35.h" +#include "devices.h" + +#define GPIO_LCDPWR IMX_GPIO_NR(1, 2) +#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0) + +#define GPIO_BUTTON1 IMX_GPIO_NR(1, 4) +#define GPIO_BUTTON2 IMX_GPIO_NR(1, 5) +#define GPIO_BUTTON3 IMX_GPIO_NR(1, 7) +#define GPIO_BUTTON4 IMX_GPIO_NR(1, 8) +#define GPIO_BUTTON5 IMX_GPIO_NR(1, 9) +#define GPIO_BUTTON6 IMX_GPIO_NR(1, 10) +#define GPIO_BUTTON7 IMX_GPIO_NR(1, 11) +#define GPIO_BUTTON8 IMX_GPIO_NR(1, 12) + +static const struct fb_videomode fb_modedb[] = { + { + /* 800x480 @ 60 Hz */ + .name = "PT0708048", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 50, + .right_margin = 156, + .upper_margin = 10, + .lower_margin = 10, + .hsync_len = 1, /* note: DE only display */ + .vsync_len = 1, /* note: DE only display */ + .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, { + /* 800x480 @ 60 Hz */ + .name = "CTP-CLAA070LC0ACW", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(27000), + .left_margin = 50, + .right_margin = 50, /* whole line should have 900 clocks */ + .upper_margin = 10, + .lower_margin = 10, /* whole frame should have 500 lines */ + .hsync_len = 1, /* note: DE only display */ + .vsync_len = 1, /* note: DE only display */ + .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + } +}; + +static struct ipu_platform_data mx3_ipu_data = { + .irq_base = MXC_IPU_IRQ_START, +}; + +static struct mx3fb_platform_data mx3fb_pdata = { + .dma_dev = &mx3_ipu.dev, + .name = "PT0708048", + .mode = fb_modedb, + .num_modes = ARRAY_SIZE(fb_modedb), +}; + +static struct physmap_flash_data vpr200_flash_data = { + .width = 2, +}; + +static struct resource vpr200_flash_resource = { + .start = MX35_CS0_BASE_ADDR, + .end = MX35_CS0_BASE_ADDR + SZ_64M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device vpr200_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &vpr200_flash_data, + }, + .resource = &vpr200_flash_resource, + .num_resources = 1, +}; + +static const struct mxc_nand_platform_data + vpr200_nand_board_info __initconst = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +#define VPR_KEY_DEBOUNCE 500 +static struct gpio_keys_button vpr200_gpio_keys_table[] = { + {KEY_F2, GPIO_BUTTON1, 1, "vpr-keys: F2", 0, VPR_KEY_DEBOUNCE}, + {KEY_F3, GPIO_BUTTON2, 1, "vpr-keys: F3", 0, VPR_KEY_DEBOUNCE}, + {KEY_F4, GPIO_BUTTON3, 1, "vpr-keys: F4", 0, VPR_KEY_DEBOUNCE}, + {KEY_F5, GPIO_BUTTON4, 1, "vpr-keys: F5", 0, VPR_KEY_DEBOUNCE}, + {KEY_F6, GPIO_BUTTON5, 1, "vpr-keys: F6", 0, VPR_KEY_DEBOUNCE}, + {KEY_F7, GPIO_BUTTON6, 1, "vpr-keys: F7", 0, VPR_KEY_DEBOUNCE}, + {KEY_F8, GPIO_BUTTON7, 1, "vpr-keys: F8", 1, VPR_KEY_DEBOUNCE}, + {KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE}, +}; + +static struct gpio_keys_platform_data vpr200_gpio_keys_data = { + .buttons = vpr200_gpio_keys_table, + .nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table), +}; + +static struct platform_device vpr200_device_gpiokeys = { + .name = "gpio-keys", + .dev = { + .platform_data = &vpr200_gpio_keys_data, + } +}; + +static struct mc13xxx_platform_data vpr200_pmic = { + .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN, +}; + +static const struct imxi2c_platform_data vpr200_i2c0_data __initconst = { + .bitrate = 50000, +}; + +static struct at24_platform_data vpr200_eeprom = { + .byte_len = 2048 / 8, + .page_size = 1, +}; + +static struct i2c_board_info vpr200_i2c_devices[] = { + { + I2C_BOARD_INFO("at24", 0x50), /* E0=0, E1=0, E2=0 */ + .platform_data = &vpr200_eeprom, + }, { + I2C_BOARD_INFO("mc13892", 0x08), + .platform_data = &vpr200_pmic, + .irq = gpio_to_irq(GPIO_PMIC_INT), + } +}; + +static iomux_v3_cfg_t vpr200_pads[] = { + /* UART1 */ + MX35_PAD_TXD1__UART1_TXD_MUX, + MX35_PAD_RXD1__UART1_RXD_MUX, + /* UART3 */ + MX35_PAD_ATA_DATA10__UART3_RXD_MUX, + MX35_PAD_ATA_DATA11__UART3_TXD_MUX, + /* FEC */ + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, + MX35_PAD_FEC_RX_DV__FEC_RX_DV, + MX35_PAD_FEC_COL__FEC_COL, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_TX_EN__FEC_TX_EN, + MX35_PAD_FEC_MDC__FEC_MDC, + MX35_PAD_FEC_MDIO__FEC_MDIO, + MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, + MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, + MX35_PAD_FEC_CRS__FEC_CRS, + MX35_PAD_FEC_RDATA1__FEC_RDATA_1, + MX35_PAD_FEC_TDATA1__FEC_TDATA_1, + MX35_PAD_FEC_RDATA2__FEC_RDATA_2, + MX35_PAD_FEC_TDATA2__FEC_TDATA_2, + MX35_PAD_FEC_RDATA3__FEC_RDATA_3, + MX35_PAD_FEC_TDATA3__FEC_TDATA_3, + /* Display */ + MX35_PAD_LD0__IPU_DISPB_DAT_0, + MX35_PAD_LD1__IPU_DISPB_DAT_1, + MX35_PAD_LD2__IPU_DISPB_DAT_2, + MX35_PAD_LD3__IPU_DISPB_DAT_3, + MX35_PAD_LD4__IPU_DISPB_DAT_4, + MX35_PAD_LD5__IPU_DISPB_DAT_5, + MX35_PAD_LD6__IPU_DISPB_DAT_6, + MX35_PAD_LD7__IPU_DISPB_DAT_7, + MX35_PAD_LD8__IPU_DISPB_DAT_8, + MX35_PAD_LD9__IPU_DISPB_DAT_9, + MX35_PAD_LD10__IPU_DISPB_DAT_10, + MX35_PAD_LD11__IPU_DISPB_DAT_11, + MX35_PAD_LD12__IPU_DISPB_DAT_12, + MX35_PAD_LD13__IPU_DISPB_DAT_13, + MX35_PAD_LD14__IPU_DISPB_DAT_14, + MX35_PAD_LD15__IPU_DISPB_DAT_15, + MX35_PAD_LD16__IPU_DISPB_DAT_16, + MX35_PAD_LD17__IPU_DISPB_DAT_17, + MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, + MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, + MX35_PAD_CONTRAST__IPU_DISPB_CONTR, + /* LCD Enable */ + MX35_PAD_D3_VSYNC__GPIO1_2, + /* USBOTG */ + MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, + MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, + /* SDCARD */ + MX35_PAD_SD1_CMD__ESDHC1_CMD, + MX35_PAD_SD1_CLK__ESDHC1_CLK, + MX35_PAD_SD1_DATA0__ESDHC1_DAT0, + MX35_PAD_SD1_DATA1__ESDHC1_DAT1, + MX35_PAD_SD1_DATA2__ESDHC1_DAT2, + MX35_PAD_SD1_DATA3__ESDHC1_DAT3, + /* PMIC */ + MX35_PAD_GPIO2_0__GPIO2_0, + /* GPIO keys */ + MX35_PAD_SCKR__GPIO1_4, + MX35_PAD_COMPARE__GPIO1_5, + MX35_PAD_SCKT__GPIO1_7, + MX35_PAD_FST__GPIO1_8, + MX35_PAD_HCKT__GPIO1_9, + MX35_PAD_TX5_RX0__GPIO1_10, + MX35_PAD_TX4_RX1__GPIO1_11, + MX35_PAD_TX3_RX2__GPIO1_12, +}; + +/* USB Device config */ +static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_UTMI, + .workaround = FLS_USB2_WORKAROUND_ENGCM09152, +}; + +/* USB HOST config */ +static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { + .portsc = MXC_EHCI_MODE_SERIAL, + .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | + MXC_EHCI_INTERNAL_PHY, +}; + +static struct platform_device *devices[] __initdata = { + &vpr200_flash, + &vpr200_device_gpiokeys, +}; + +/* + * Board specific initialization. + */ +static void __init vpr200_board_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads)); + + imx35_add_fec(NULL); + imx35_add_imx2_wdt(NULL); + + platform_add_devices(devices, ARRAY_SIZE(devices)); + + if (0 != gpio_request(GPIO_LCDPWR, "LCDPWR")) + printk(KERN_WARNING "vpr200: Couldn't get LCDPWR gpio\n"); + else + gpio_direction_output(GPIO_LCDPWR, 0); + + if (0 != gpio_request(GPIO_PMIC_INT, "PMIC_INT")) + printk(KERN_WARNING "vpr200: Couldn't get PMIC_INT gpio\n"); + else + gpio_direction_input(GPIO_PMIC_INT); + + imx35_add_imx_uart0(NULL); + imx35_add_imx_uart2(NULL); + + mxc_register_device(&mx3_ipu, &mx3_ipu_data); + mxc_register_device(&mx3_fb, &mx3fb_pdata); + + imx35_add_fsl_usb2_udc(&otg_device_pdata); + imx35_add_mxc_ehci_hs(&usb_host_pdata); + + imx35_add_mxc_nand(&vpr200_nand_board_info); + imx35_add_sdhci_esdhc_imx(0, NULL); + + i2c_register_board_info(0, vpr200_i2c_devices, + ARRAY_SIZE(vpr200_i2c_devices)); + + imx35_add_imx_i2c0(&vpr200_i2c0_data); +} + +static void __init vpr200_timer_init(void) +{ + mx35_clocks_init(); +} + +struct sys_timer vpr200_timer = { + .init = vpr200_timer_init, +}; + +MACHINE_START(VPR200, "VPR200") + /* Maintainer: Creative Product Design */ + .map_io = mx35_map_io, + .init_irq = mx35_init_irq, + .init_machine = vpr200_board_init, + .timer = &vpr200_timer, +MACHINE_END -- cgit v0.10.2 From 816ad741b6a168e1d0c182d10999c298fc281d17 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Sat, 15 Jan 2011 13:40:12 -0600 Subject: ARM: i.MX53: Add full iomux support for mx53 This iomux file contains all the available pins that are iomux capable. Signed-off-by: Dinh Nguyen Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c index caee04c..eba9df0 100644 --- a/arch/arm/mach-mx5/board-mx53_evk.c +++ b/arch/arm/mach-mx5/board-mx53_evk.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright (C) 2010 Yong Shen. */ @@ -42,28 +42,28 @@ #include "devices-imx53.h" static iomux_v3_cfg_t mx53_evk_pads[] = { - MX53_PAD_CSI0_D10__UART1_TXD, - MX53_PAD_CSI0_D11__UART1_RXD, - MX53_PAD_ATA_DIOW__UART1_TXD, - MX53_PAD_ATA_DMACK__UART1_RXD, + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, + MX53_PAD_PATA_DIOW__UART1_TXD_MUX, + MX53_PAD_PATA_DMACK__UART1_RXD_MUX, - MX53_PAD_ATA_BUFFER_EN__UART2_RXD, - MX53_PAD_ATA_DMARQ__UART2_TXD, - MX53_PAD_ATA_DIOR__UART2_RTS, - MX53_PAD_ATA_INTRQ__UART2_CTS, + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, + MX53_PAD_PATA_DIOR__UART2_RTS, + MX53_PAD_PATA_INTRQ__UART2_CTS, - MX53_PAD_ATA_CS_0__UART3_TXD, - MX53_PAD_ATA_CS_1__UART3_RXD, - MX53_PAD_ATA_DA_1__UART3_CTS, - MX53_PAD_ATA_DA_2__UART3_RTS, + MX53_PAD_PATA_CS_0__UART3_TXD_MUX, + MX53_PAD_PATA_CS_1__UART3_RXD_MUX, + MX53_PAD_PATA_DA_1__UART3_CTS, + MX53_PAD_PATA_DA_2__UART3_RTS, - MX53_PAD_EIM_D16__CSPI1_SCLK, - MX53_PAD_EIM_D17__CSPI1_MISO, - MX53_PAD_EIM_D18__CSPI1_MOSI, + MX53_PAD_EIM_D16__ECSPI1_SCLK, + MX53_PAD_EIM_D17__ECSPI1_MISO, + MX53_PAD_EIM_D18__ECSPI1_MOSI, /* ecspi chip select lines */ - MX53_PAD_EIM_EB2__GPIO_2_30, - MX53_PAD_EIM_D19__GPIO_3_19, + MX53_PAD_EIM_EB2__GPIO2_30, + MX53_PAD_EIM_D19__GPIO3_19, }; static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = { diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h index 68e11d7..bae7fd0 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,305 +21,2355 @@ #include -/* - * various IOMUX alternate output functions (1-7) - */ -typedef enum iomux_config { - IOMUX_CONFIG_ALT0, - IOMUX_CONFIG_ALT1, - IOMUX_CONFIG_ALT2, - IOMUX_CONFIG_ALT3, - IOMUX_CONFIG_ALT4, - IOMUX_CONFIG_ALT5, - IOMUX_CONFIG_ALT6, - IOMUX_CONFIG_ALT7, - IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ -} iomux_pin_cfg_t; - /* These 2 defines are for pins that may not have a mux register, but could * have a pad setting register, and vice-versa. */ -#define NON_MUX_I 0x00 #define NON_PAD_I 0x00 #define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS) -/* UART1 */ -#define MX53_PAD_CSI0_D10__UART1_TXD IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_D11__UART1_RXD IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, MX53_UART_PAD_CTRL) -#define MX53_PAD_ATA_DIOW__UART1_TXD IOMUX_PAD(0x5F0, 0x270, 3, 0x0, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_ATA_DMACK__UART1_RXD IOMUX_PAD(0x5F4, 0x274, 3, 0x880, 3, MX53_UART_PAD_CTRL) - -/* UART2 */ -#define MX53_PAD_ATA_BUFFER_EN__UART2_RXD IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_ATA_DMARQ__UART2_TXD IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_ATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_ATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, MX53_UART_PAD_CTRL) -/* UART3 */ -#define MX53_PAD_ATA_CS_0__UART3_TXD IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_ATA_CS_1__UART3_RXD IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_ATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, 0x0, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_ATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL) +#define _MX53_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x348, 0x20, 0, 0x840, 0, 0) +#define _MX53_PAD_GPIO_19__GPIO4_5 IOMUX_PAD(0x348, 0x20, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_19__CCM_CLKO IOMUX_PAD(0x348, 0x20, 2, 0x0, 0, 0) +#define _MX53_PAD_GPIO_19__SPDIF_OUT1 IOMUX_PAD(0x348, 0x20, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x20, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x20, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x20, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x20,7, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x24, o, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x24, 2, 0x758, 0, 0) +#define _MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x24, 4, 0x890, 0, 0) +#define _MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x24, 5, 0x79C, 0, 0) +#define _MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x24, 6, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x34C, 0x24, 7, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x350, 0x28, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW0__GPIO4_7 IOMUX_PAD(0x350, 0x28, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD IOMUX_PAD(0x350, 0x28, 2, 0x74C, 0, 0) +#define _MX53_PAD_KEY_ROW0__UART4_RXD_MUX IOMUX_PAD(0x350, 0x28, 4, 0x890, 1, 0) +#define _MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x28, 5, 0x7A4, 0, 0) +#define _MX53_PAD_KEY_ROW0__FEC_TX_ER IOMUX_PAD(0x350, 0x28, 6, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x354, 0x2C, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL1__GPIO4_8 IOMUX_PAD(0x354, 0x2C, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x354, 0x2C, 2, 0x75C, 0, 0) +#define _MX53_PAD_KEY_COL1__UART5_TXD_MUX IOMUX_PAD(0x354, 0x2C, 4, 0x898, 0, 0) +#define _MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x2C, 5, 0x7A0, 0, 0) +#define _MX53_PAD_KEY_COL1__FEC_RX_CLK IOMUX_PAD(0x354, 0x2C, 6, 0x808, 0, 0) +#define _MX53_PAD_KEY_COL1__USBPHY1_TXREADY IOMUX_PAD(0x354, 0x2C, 7, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x358, 0x30, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW1__GPIO4_9 IOMUX_PAD(0x358, 0x30, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD IOMUX_PAD(0x358, 0x30, 2, 0x748, 0, 0) +#define _MX53_PAD_KEY_ROW1__UART5_RXD_MUX IOMUX_PAD(0x358, 0x30, 4, 0x898, 1, 0) +#define _MX53_PAD_KEY_ROW1__ECSPI1_SS0 IOMUX_PAD(0x358, 0x30, 5, 0x7A8, 0, 0) +#define _MX53_PAD_KEY_ROW1__FEC_COL IOMUX_PAD(0x358, 0x30, 6, 0x800, 0, 0) +#define _MX53_PAD_KEY_ROW1__USBPHY1_RXVALID IOMUX_PAD(0x358, 0x30, 7, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x35C, 0x34, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL2__GPIO4_10 IOMUX_PAD(0x35C, 0x34, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL2__CAN1_TXCAN IOMUX_PAD(0x35C, 0x34, 2, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL2__FEC_MDIO IOMUX_PAD(0x35C, 0x34, 4, 0x804, 0, 0) +#define _MX53_PAD_KEY_COL2__ECSPI1_SS1 IOMUX_PAD(0x35C, 0x34, 5, 0x7AC, 0, 0) +#define _MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x34, 6, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE IOMUX_PAD(0x35C, 0x34, 7, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x360, 0x38, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW2__GPIO4_11 IOMUX_PAD(0x360, 0x38, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW2__CAN1_RXCAN IOMUX_PAD(0x360, 0x38, 2, 0x760, 0, 0) +#define _MX53_PAD_KEY_ROW2__FEC_MDC IOMUX_PAD(0x360, 0x38, 4, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW2__ECSPI1_SS2 IOMUX_PAD(0x360, 0x38, 5, 0x7B0, 0, 0) +#define _MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x38, 6, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW2__USBPHY1_RXERROR IOMUX_PAD(0x360, 0x38, 7, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x364, 0x3C, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL3__GPIO4_12 IOMUX_PAD(0x364, 0x3C, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL3__USBOH3_H2_DP IOMUX_PAD(0x364, 0x3C, 2, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x364, 0x3C, 3, 0x870, 0, 0) +#define _MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x3C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, 0) +#define _MX53_PAD_KEY_COL3__ECSPI1_SS3 IOMUX_PAD(0x364, 0x3C, 5, 0x7B4, 0, 0) +#define _MX53_PAD_KEY_COL3__FEC_CRS IOMUX_PAD(0x364, 0x3C, 6, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK IOMUX_PAD(0x364, 0x3C, 7, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x368, 0x40, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW3__GPIO4_13 IOMUX_PAD(0x368, 0x40, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW3__USBOH3_H2_DM IOMUX_PAD(0x368, 0x40, 2, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK IOMUX_PAD(0x368, 0x40, 3, 0x768, 0, 0) +#define _MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x40, 4 | IOMUX_CONFIG_SION, 0x820, 0, 0) +#define _MX53_PAD_KEY_ROW3__OSC32K_32K_OUT IOMUX_PAD(0x368, 0x40, 5, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW3__CCM_PLL4_BYP IOMUX_PAD(0x368, 0x40, 6, 0x77C, 0, 0) +#define _MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x40, 7, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x36C, 0x44, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL4__GPIO4_14 IOMUX_PAD(0x36C, 0x44, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL4__CAN2_TXCAN IOMUX_PAD(0x36C, 0x44, 2, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL4__IPU_SISG_4 IOMUX_PAD(0x36C, 0x44, 3, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL4__UART5_RTS IOMUX_PAD(0x36C, 0x44, 4, 0x894, 0, 0) +#define _MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC IOMUX_PAD(0x36C, 0x44, 5, 0x89C, 0, 0) +#define _MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x44, 7, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x370, 0x48, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW4__GPIO4_15 IOMUX_PAD(0x370, 0x48, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x370, 0x48, 2, 0x764, 0, 0) +#define _MX53_PAD_KEY_ROW4__IPU_SISG_5 IOMUX_PAD(0x370, 0x48, 3, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x370, 0x48, 4, 0x894, 1, 0) +#define _MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x370, 0x48, 5, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID IOMUX_PAD(0x370, 0x48, 7, 0x0, 0, 0) +#define _MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK IOMUX_PAD(0x378, 0x4C, 0, 0x0, 0, 0) +#define _MX53_PAD_DI0_DISP_CLK__GPIO4_16 IOMUX_PAD(0x378, 0x4C, 1, 0x0, 0, 0) +#define _MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR IOMUX_PAD(0x378, 0x4C, 2, 0x0, 0, 0) +#define _MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x4C, 5, 0x0, 0, 0) +#define _MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x4C, 6, 0x0, 0, 0) +#define _MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID IOMUX_PAD(0x378, 0x4C, 7, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 IOMUX_PAD(0x37C, 0x50, 0, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN15__GPIO4_17 IOMUX_PAD(0x37C, 0x50, 1, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC IOMUX_PAD(0x37C, 0x50, 2, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x37C, 0x50, 5, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 IOMUX_PAD(0x37C, 0x50, 6, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN15__USBPHY1_BVALID IOMUX_PAD(0x37C, 0x50, 7, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 IOMUX_PAD(0x380, 0x54, 0, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN2__GPIO4_18 IOMUX_PAD(0x380, 0x54, 1, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD IOMUX_PAD(0x380, 0x54, 2, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x380, 0x54, 5, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 IOMUX_PAD(0x380, 0x54, 6, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION IOMUX_PAD(0x380, 0x54, 7, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 IOMUX_PAD(0x384, 0x58, 0, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN3__GPIO4_19 IOMUX_PAD(0x384, 0x58, 1, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x384, 0x58, 2, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x384, 0x58, 5, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 IOMUX_PAD(0x384, 0x58, 6, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN3__USBPHY1_IDDIG IOMUX_PAD(0x384, 0x58, 7, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 IOMUX_PAD(0x388, 0x5C, 0, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN4__GPIO4_20 IOMUX_PAD(0x388, 0x5C, 1, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD IOMUX_PAD(0x388, 0x5C, 2, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN4__ESDHC1_WP IOMUX_PAD(0x388, 0x5C, 3, 0x7FC, 0, 0) +#define _MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD IOMUX_PAD(0x388, 0x5C, 5, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 IOMUX_PAD(0x388, 0x5C, 6, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT IOMUX_PAD(0x388, 0x5C, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 IOMUX_PAD(0x38C, 0x60, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT0__GPIO4_21 IOMUX_PAD(0x38C, 0x60, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT0__CSPI_SCLK IOMUX_PAD(0x38C, 0x60, 2, 0x780, 0, 0) +#define _MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 IOMUX_PAD(0x38C, 0x60, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x38C, 0x60, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 IOMUX_PAD(0x38C, 0x60, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY IOMUX_PAD(0x38C, 0x60, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 IOMUX_PAD(0x390, 0x64, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT1__GPIO4_22 IOMUX_PAD(0x390, 0x64, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT1__CSPI_MOSI IOMUX_PAD(0x390, 0x64, 2, 0x788, 0, 0) +#define _MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 IOMUX_PAD(0x390, 0x64, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x390, 0x64, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 IOMUX_PAD(0x390, 0x64, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID IOMUX_PAD(0x390, 0x64, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 IOMUX_PAD(0x394, 0x68, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT2__GPIO4_23 IOMUX_PAD(0x394, 0x68, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT2__CSPI_MISO IOMUX_PAD(0x394, 0x68, 2, 0x784, 0, 0) +#define _MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 IOMUX_PAD(0x394, 0x68, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE IOMUX_PAD(0x394, 0x68, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 IOMUX_PAD(0x394, 0x68, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE IOMUX_PAD(0x394, 0x68, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 IOMUX_PAD(0x398, 0x6C, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT3__GPIO4_24 IOMUX_PAD(0x398, 0x6C, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT3__CSPI_SS0 IOMUX_PAD(0x398, 0x6C, 2, 0x78C, 0, 0) +#define _MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 IOMUX_PAD(0x398, 0x6C, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x398, 0x6C, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 IOMUX_PAD(0x398, 0x6C, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR IOMUX_PAD(0x398, 0x6C, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 IOMUX_PAD(0x39C, 0x70, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT4__GPIO4_25 IOMUX_PAD(0x39C, 0x70, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT4__CSPI_SS1 IOMUX_PAD(0x39C, 0x70, 2, 0x790, 0, 0) +#define _MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 IOMUX_PAD(0x39C, 0x70, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x39C, 0x70, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 IOMUX_PAD(0x39C, 0x70, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK IOMUX_PAD(0x39C, 0x70, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 IOMUX_PAD(0x3A0, 0x74, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT5__GPIO4_26 IOMUX_PAD(0x3A0, 0x74, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT5__CSPI_SS2 IOMUX_PAD(0x3A0, 0x74, 2, 0x794, 0, 0) +#define _MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 IOMUX_PAD(0x3A0, 0x74, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x3A0, 0x74, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 IOMUX_PAD(0x3A0, 0x74, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 IOMUX_PAD(0x3A0, 0x74, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 IOMUX_PAD(0x3A4, 0x78, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT6__GPIO4_27 IOMUX_PAD(0x3A4, 0x78, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT6__CSPI_SS3 IOMUX_PAD(0x3A4, 0x78, 2, 0x798, 0, 0) +#define _MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 IOMUX_PAD(0x3A4, 0x78, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x78, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 IOMUX_PAD(0x3A4, 0x78, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 IOMUX_PAD(0x3A4, 0x78, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 IOMUX_PAD(0x3A8, 0x7C, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT7__GPIO4_28 IOMUX_PAD(0x3A8, 0x7C, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT7__CSPI_RDY IOMUX_PAD(0x3A8, 0x7C, 2, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 IOMUX_PAD(0x3A8, 0x7C, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x7C, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 IOMUX_PAD(0x3A8, 0x7C, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x7C, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 IOMUX_PAD(0x3AC, 0x80, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT8__GPIO4_29 IOMUX_PAD(0x3AC, 0x80, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT8__PWM1_PWMO IOMUX_PAD(0x3AC, 0x80, 2, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B IOMUX_PAD(0x3AC, 0x80, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x80, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 IOMUX_PAD(0x3AC, 0x80, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT8__USBPHY2_AVALID IOMUX_PAD(0x3AC, 0x80, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 IOMUX_PAD(0x3B0, 0x84, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT9__GPIO4_30 IOMUX_PAD(0x3B0, 0x84, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT9__PWM2_PWMO IOMUX_PAD(0x3B0, 0x84, 2, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B IOMUX_PAD(0x3B0, 0x84, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x84, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 IOMUX_PAD(0x3B0, 0x84, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x84, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x88, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT10__GPIO4_31 IOMUX_PAD(0x3B4, 0x88, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x88, 2, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x3B4, 0x88, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x88, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 IOMUX_PAD(0x3B4, 0x88, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x8C, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT11__GPIO5_5 IOMUX_PAD(0x3B8, 0x8C, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x8C, 2, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x3B8, 0x8C, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x8C, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 IOMUX_PAD(0x3B8, 0x8C, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x90, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT12__GPIO5_6 IOMUX_PAD(0x3BC, 0x90, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x90, 2, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x3BC, 0x90, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x90, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 IOMUX_PAD(0x3BC, 0x90, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x94, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT13__GPIO5_7 IOMUX_PAD(0x3C0, 0x94, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x94, 3, 0x754, 0, 0) +#define _MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 IOMUX_PAD(0x3C0, 0x94, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x94, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 IOMUX_PAD(0x3C0, 0x94, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x98, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT14__GPIO5_8 IOMUX_PAD(0x3C4, 0x98, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC IOMUX_PAD(0x3C4, 0x98, 3, 0x750, 0, 0) +#define _MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 IOMUX_PAD(0x3C4, 0x98, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x98, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 IOMUX_PAD(0x3C4, 0x98, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x9C, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT15__GPIO5_9 IOMUX_PAD(0x3C8, 0x9C, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT15__ECSPI1_SS1 IOMUX_PAD(0x3C8, 0x9C, 2, 0x7AC, 1, 0) +#define _MX53_PAD_DISP0_DAT15__ECSPI2_SS1 IOMUX_PAD(0x3C8, 0x9C, 3, 0x7C8, 0, 0) +#define _MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 IOMUX_PAD(0x3C8, 0x9C, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x9C, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 IOMUX_PAD(0x3C8, 0x9C, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0xA0, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT16__GPIO5_10 IOMUX_PAD(0x3CC, 0xA0, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x3CC, 0xA0, 2, 0x7C0, 0, 0) +#define _MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC IOMUX_PAD(0x3CC, 0xA0, 3, 0x758, 1, 0) +#define _MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0xA0, 4, 0x868, 0, 0) +#define _MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 IOMUX_PAD(0x3CC, 0xA0, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0xA0, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 IOMUX_PAD(0x3CC, 0xA0, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0xA4, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT17__GPIO5_11 IOMUX_PAD(0x3D0, 0xA4, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x3D0, 0xA4, 2, 0x7BC, 0, 0) +#define _MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD IOMUX_PAD(0x3D0, 0xA4, 3, 0x74C, 1, 0) +#define _MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0xA4, 4, 0x86C, 0, 0) +#define _MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 IOMUX_PAD(0x3D0, 0xA4, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0xA4, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0xA8, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT18__GPIO5_12 IOMUX_PAD(0x3D4, 0xA8, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x3D4, 0xA8, 2, 0x7C4, 0, 0) +#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0xA8, 3, 0x75C, 1, 0) +#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0xA8, 4, 0x73C, 0, 0) +#define _MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 IOMUX_PAD(0x3D4, 0xA8, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0xA8, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 IOMUX_PAD(0x3D4, 0xA8, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0xAC, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT19__GPIO5_13 IOMUX_PAD(0x3D8, 0xAC, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x3D8, 0xAC, 2, 0x7B8, 0, 0) +#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD IOMUX_PAD(0x3D8, 0xAC, 3, 0x748, 1, 0) +#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC IOMUX_PAD(0x3D8, 0xAC, 4, 0x738, 0, 0) +#define _MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 IOMUX_PAD(0x3D8, 0xAC, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0xAC, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 IOMUX_PAD(0x3D8, 0xAC, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0xB0, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT20__GPIO5_14 IOMUX_PAD(0x3DC, 0xB0, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT20__ECSPI1_SCLK IOMUX_PAD(0x3DC, 0xB0, 2, 0x79C, 1, 0) +#define _MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC IOMUX_PAD(0x3DC, 0xB0, 3, 0x740, 0, 0) +#define _MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 IOMUX_PAD(0x3DC, 0xB0, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0xB0, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT20__SATA_PHY_TDI IOMUX_PAD(0x3DC, 0xB0, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0xB4, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT21__GPIO5_15 IOMUX_PAD(0x3E0, 0xB4, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT21__ECSPI1_MOSI IOMUX_PAD(0x3E0, 0xB4, 2, 0x7A4, 1, 0) +#define _MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD IOMUX_PAD(0x3E0, 0xB4, 3, 0x734, 0, 0) +#define _MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x3E0, 0xB4, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0xB4, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT21__SATA_PHY_TDO IOMUX_PAD(0x3E0, 0xB4, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0xB8, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT22__GPIO5_16 IOMUX_PAD(0x3E4, 0xB8, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT22__ECSPI1_MISO IOMUX_PAD(0x3E4, 0xB8, 2, 0x7A0, 1, 0) +#define _MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0xB8, 3, 0x744, 0, 0) +#define _MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x3E4, 0xB8, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0xB8, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT22__SATA_PHY_TCK IOMUX_PAD(0x3E4, 0xB8, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0xBC, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT23__GPIO5_17 IOMUX_PAD(0x3E8, 0xBC, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT23__ECSPI1_SS0 IOMUX_PAD(0x3E8, 0xBC, 2, 0x7A8, 1, 0) +#define _MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD IOMUX_PAD(0x3E8, 0xBC, 3, 0x730, 0, 0) +#define _MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x3E8, 0xBC, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0xBC, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT23__SATA_PHY_TMS IOMUX_PAD(0x3E8, 0xBC, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK IOMUX_PAD(0x3EC, 0xC0, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_PIXCLK__GPIO5_18 IOMUX_PAD(0x3EC, 0xC0, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 IOMUX_PAD(0x3EC, 0xC0, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0xC0, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC IOMUX_PAD(0x3F0, 0xC4, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_MCLK__GPIO5_19 IOMUX_PAD(0x3F0, 0xC4, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK IOMUX_PAD(0x3F0, 0xC4, 2, 0x0, 0, 0) +#define _MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 IOMUX_PAD(0x3F0, 0xC4, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 IOMUX_PAD(0x3F0, 0xC4, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_MCLK__TPIU_TRCTL IOMUX_PAD(0x3F0, 0xC4, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN IOMUX_PAD(0x3F4, 0xC8, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DATA_EN__GPIO5_20 IOMUX_PAD(0x3F4, 0xC8, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0xC8, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 IOMUX_PAD(0x3F4, 0xC8, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK IOMUX_PAD(0x3F4, 0xC8, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC IOMUX_PAD(0x3F8, 0xCC, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_VSYNC__GPIO5_21 IOMUX_PAD(0x3F8, 0xCC, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 IOMUX_PAD(0x3F8, 0xCC, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 IOMUX_PAD(0x3F8, 0xCC, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 IOMUX_PAD(0x3F8, 0xCC, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 IOMUX_PAD(0x3FC, 0xD0, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT4__GPIO5_22 IOMUX_PAD(0x3FC, 0xD0, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT4__KPP_COL_5 IOMUX_PAD(0x3FC, 0xD0, 2, 0x840, 1, 0) +#define _MX53_PAD_CSI0_DAT4__ECSPI1_SCLK IOMUX_PAD(0x3FC, 0xD0, 3, 0x79C, 2, 0) +#define _MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP IOMUX_PAD(0x3FC, 0xD0, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC IOMUX_PAD(0x3FC, 0xD0, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 IOMUX_PAD(0x3FC, 0xD0, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 IOMUX_PAD(0x3FC, 0xD0, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 IOMUX_PAD(0x400, 0xD4, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT5__GPIO5_23 IOMUX_PAD(0x400, 0xD4, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT5__KPP_ROW_5 IOMUX_PAD(0x400, 0xD4, 2, 0x84C, 0, 0) +#define _MX53_PAD_CSI0_DAT5__ECSPI1_MOSI IOMUX_PAD(0x400, 0xD4, 3, 0x7A4, 2, 0) +#define _MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT IOMUX_PAD(0x400, 0xD4, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD IOMUX_PAD(0x400, 0xD4, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 IOMUX_PAD(0x400, 0xD4, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 IOMUX_PAD(0x400, 0xD4, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 IOMUX_PAD(0x404, 0xD8, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT6__GPIO5_24 IOMUX_PAD(0x404, 0xD8, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT6__KPP_COL_6 IOMUX_PAD(0x404, 0xD8, 2, 0x844, 0, 0) +#define _MX53_PAD_CSI0_DAT6__ECSPI1_MISO IOMUX_PAD(0x404, 0xD8, 3, 0x7A0, 2, 0) +#define _MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK IOMUX_PAD(0x404, 0xD8, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS IOMUX_PAD(0x404, 0xD8, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 IOMUX_PAD(0x404, 0xD8, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 IOMUX_PAD(0x404, 0xD8, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 IOMUX_PAD(0x408, 0xDC, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT7__GPIO5_25 IOMUX_PAD(0x408, 0xDC, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT7__KPP_ROW_6 IOMUX_PAD(0x408, 0xDC, 2, 0x850, 0, 0) +#define _MX53_PAD_CSI0_DAT7__ECSPI1_SS0 IOMUX_PAD(0x408, 0xDC, 3, 0x7A8, 2, 0) +#define _MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR IOMUX_PAD(0x408, 0xDC, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD IOMUX_PAD(0x408, 0xDC, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 IOMUX_PAD(0x408, 0xDC, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 IOMUX_PAD(0x408, 0xDC, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 IOMUX_PAD(0x40C, 0xE0, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT8__GPIO5_26 IOMUX_PAD(0x40C, 0xE0, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT8__KPP_COL_7 IOMUX_PAD(0x40C, 0xE0, 2, 0x848, 0, 0) +#define _MX53_PAD_CSI0_DAT8__ECSPI2_SCLK IOMUX_PAD(0x40C, 0xE0, 3, 0x7B8, 1, 0) +#define _MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC IOMUX_PAD(0x40C, 0xE0, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x40C, 0xE0, 5 | IOMUX_CONFIG_SION, 0x818, 0, 0) +#define _MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 IOMUX_PAD(0x40C, 0xE0, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 IOMUX_PAD(0x40C, 0xE0, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 IOMUX_PAD(0x410, 0xE4, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT9__GPIO5_27 IOMUX_PAD(0x410, 0xE4, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT9__KPP_ROW_7 IOMUX_PAD(0x410, 0xE4, 2, 0x854, 0, 0) +#define _MX53_PAD_CSI0_DAT9__ECSPI2_MOSI IOMUX_PAD(0x410, 0xE4, 3, 0x7C0, 1, 0) +#define _MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR IOMUX_PAD(0x410, 0xE4, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x410, 0xE4, 5 | IOMUX_CONFIG_SION, 0x814, 0, 0) +#define _MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 IOMUX_PAD(0x410, 0xE4, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 IOMUX_PAD(0x410, 0xE4, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 IOMUX_PAD(0x414, 0xE8, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT10__GPIO5_28 IOMUX_PAD(0x414, 0xE8, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT10__UART1_TXD_MUX IOMUX_PAD(0x414, 0xE8, 2, 0x878, 0, 0) +#define _MX53_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x414, 0xE8, 3, 0x7BC, 1, 0) +#define _MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x414, 0xE8, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x414, 0xE8, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 IOMUX_PAD(0x414, 0xE8, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 IOMUX_PAD(0x414, 0xE8, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 IOMUX_PAD(0x418, 0xEC, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT11__GPIO5_29 IOMUX_PAD(0x418, 0xEC, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT11__UART1_RXD_MUX IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, 0) +#define _MX53_PAD_CSI0_DAT11__ECSPI2_SS0 IOMUX_PAD(0x418, 0xEC, 3, 0x7C4, 1, 0) +#define _MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS IOMUX_PAD(0x418, 0xEC, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 IOMUX_PAD(0x418, 0xEC, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 IOMUX_PAD(0x418, 0xEC, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 IOMUX_PAD(0x418, 0xEC, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 IOMUX_PAD(0x41C, 0xF0, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT12__GPIO5_30 IOMUX_PAD(0x41C, 0xF0, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT12__UART4_TXD_MUX IOMUX_PAD(0x41C, 0xF0, 2, 0x890, 2, 0) +#define _MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 IOMUX_PAD(0x41C, 0xF0, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x41C, 0xF0, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 IOMUX_PAD(0x41C, 0xF0, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 IOMUX_PAD(0x41C, 0xF0, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 IOMUX_PAD(0x420, 0xF4, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT13__GPIO5_31 IOMUX_PAD(0x420, 0xF4, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT13__UART4_RXD_MUX IOMUX_PAD(0x420, 0xF4, 2, 0x890, 3, 0) +#define _MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 IOMUX_PAD(0x420, 0xF4, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 IOMUX_PAD(0x420, 0xF4, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 IOMUX_PAD(0x420, 0xF4, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 IOMUX_PAD(0x420, 0xF4, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 IOMUX_PAD(0x424, 0xF8, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT14__GPIO6_0 IOMUX_PAD(0x424, 0xF8, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT14__UART5_TXD_MUX IOMUX_PAD(0x424, 0xF8, 2, 0x898, 2, 0) +#define _MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 IOMUX_PAD(0x424, 0xF8, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x424, 0xF8, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 IOMUX_PAD(0x424, 0xF8, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 IOMUX_PAD(0x424, 0xF8, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 IOMUX_PAD(0x428, 0xFC, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT15__GPIO6_1 IOMUX_PAD(0x428, 0xFC, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT15__UART5_RXD_MUX IOMUX_PAD(0x428, 0xFC, 2, 0x898, 3, 0) +#define _MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 IOMUX_PAD(0x428, 0xFC, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 IOMUX_PAD(0x428, 0xFC, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 IOMUX_PAD(0x428, 0xFC, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 IOMUX_PAD(0x428, 0xFC, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 IOMUX_PAD(0x42C, 0x100, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT16__GPIO6_2 IOMUX_PAD(0x42C, 0x100, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT16__UART4_RTS IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, 0) +#define _MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 IOMUX_PAD(0x42C, 0x100, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 IOMUX_PAD(0x42C, 0x100, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 IOMUX_PAD(0x42C, 0x100, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 IOMUX_PAD(0x42C, 0x100, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 IOMUX_PAD(0x430, 0x104, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT17__GPIO6_3 IOMUX_PAD(0x430, 0x104, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x430, 0x104, 2, 0x88C, 1, 0) +#define _MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 IOMUX_PAD(0x430, 0x104, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x430, 0x104, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 IOMUX_PAD(0x430, 0x104, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 IOMUX_PAD(0x430, 0x104, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 IOMUX_PAD(0x434, 0x108, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT18__GPIO6_4 IOMUX_PAD(0x434, 0x108, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT18__UART5_RTS IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, 0) +#define _MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 IOMUX_PAD(0x434, 0x108, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 IOMUX_PAD(0x434, 0x108, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 IOMUX_PAD(0x434, 0x108, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 IOMUX_PAD(0x434, 0x108, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 IOMUX_PAD(0x438, 0x10C, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT19__GPIO6_5 IOMUX_PAD(0x438, 0x10C, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x438, 0x10C, 2, 0x894, 3, 0) +#define _MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 IOMUX_PAD(0x438, 0x10C, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x438, 0x10C, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 IOMUX_PAD(0x438, 0x10C, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK IOMUX_PAD(0x438, 0x10C, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A25__EMI_WEIM_A_25 IOMUX_PAD(0x458, 0x110, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A25__GPIO5_2 IOMUX_PAD(0x458, 0x110, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A25__ECSPI2_RDY IOMUX_PAD(0x458, 0x110, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A25__IPU_DI1_PIN12 IOMUX_PAD(0x458, 0x110, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A25__CSPI_SS1 IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, 0) +#define _MX53_PAD_EIM_A25__IPU_DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_A25__USBPHY1_BISTOK IOMUX_PAD(0x458, 0x110, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 IOMUX_PAD(0x45C, 0x114, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB2__GPIO2_30 IOMUX_PAD(0x45C, 0x114, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, 0) +#define _MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS IOMUX_PAD(0x45C, 0x114, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB2__ECSPI1_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, 0) +#define _MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, 0) +#define _MX53_PAD_EIM_D16__EMI_WEIM_D_16 IOMUX_PAD(0x460, 0x118, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D16__GPIO3_16 IOMUX_PAD(0x460, 0x118, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D16__IPU_DI0_PIN5 IOMUX_PAD(0x460, 0x118, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK IOMUX_PAD(0x460, 0x118, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, 0) +#define _MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5, 0x820, 1, 0) +#define _MX53_PAD_EIM_D17__EMI_WEIM_D_17 IOMUX_PAD(0x464, 0x11C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D17__GPIO3_17 IOMUX_PAD(0x464, 0x11C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D17__IPU_DI0_PIN6 IOMUX_PAD(0x464, 0x11C, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, 0) +#define _MX53_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, 0) +#define _MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5, 0x824, 0, 0) +#define _MX53_PAD_EIM_D18__EMI_WEIM_D_18 IOMUX_PAD(0x468, 0x120, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D18__GPIO3_18 IOMUX_PAD(0x468, 0x120, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D18__IPU_DI0_PIN7 IOMUX_PAD(0x468, 0x120, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, 0) +#define _MX53_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, 0) +#define _MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5, 0x828, 0, 0) +#define _MX53_PAD_EIM_D18__IPU_DI1_D0_CS IOMUX_PAD(0x468, 0x120, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_D19__EMI_WEIM_D_19 IOMUX_PAD(0x46C, 0x124, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D19__GPIO3_19 IOMUX_PAD(0x46C, 0x124, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D19__IPU_DI0_PIN8 IOMUX_PAD(0x46C, 0x124, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS IOMUX_PAD(0x46C, 0x124, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, 0) +#define _MX53_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x46C, 0x124, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x46C, 0x124, 6, 0x874, 0, 0) +#define _MX53_PAD_EIM_D19__USBOH3_USBH2_OC IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, 0) +#define _MX53_PAD_EIM_D20__EMI_WEIM_D_20 IOMUX_PAD(0x470, 0x128, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D20__GPIO3_20 IOMUX_PAD(0x470, 0x128, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D20__IPU_DI0_PIN16 IOMUX_PAD(0x470, 0x128, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_D20__IPU_SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D20__CSPI_SS0 IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, 0) +#define _MX53_PAD_EIM_D20__EPIT2_EPITO IOMUX_PAD(0x470, 0x128, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_D20__UART1_RTS IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, 0) +#define _MX53_PAD_EIM_D20__USBOH3_USBH2_PWR IOMUX_PAD(0x470, 0x128, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_D21__EMI_WEIM_D_21 IOMUX_PAD(0x474, 0x12C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D21__GPIO3_21 IOMUX_PAD(0x474, 0x12C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D21__IPU_DI0_PIN17 IOMUX_PAD(0x474, 0x12C, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D21__CSPI_SCLK IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, 0) +#define _MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5, 0x814, 1, 0) +#define _MX53_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, 0) +#define _MX53_PAD_EIM_D22__EMI_WEIM_D_22 IOMUX_PAD(0x478, 0x130, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D22__GPIO3_22 IOMUX_PAD(0x478, 0x130, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D22__IPU_DI0_PIN1 IOMUX_PAD(0x478, 0x130, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, 0) +#define _MX53_PAD_EIM_D22__CSPI_MISO IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, 0) +#define _MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x478, 0x130, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_D23__EMI_WEIM_D_23 IOMUX_PAD(0x47C, 0x134, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D23__GPIO3_23 IOMUX_PAD(0x47C, 0x134, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, 0x884, 0, 0) +#define _MX53_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x47C, 0x134, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D23__IPU_DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_D23__IPU_DI1_PIN2 IOMUX_PAD(0x47C, 0x134, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, 0) +#define _MX53_PAD_EIM_D23__IPU_DI1_PIN14 IOMUX_PAD(0x47C, 0x134, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 IOMUX_PAD(0x480, 0x138, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB3__GPIO2_31 IOMUX_PAD(0x480, 0x138, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, 0) +#define _MX53_PAD_EIM_EB3__UART1_RI IOMUX_PAD(0x480, 0x138, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN3 IOMUX_PAD(0x480, 0x138, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, 0) +#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN16 IOMUX_PAD(0x480, 0x138, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_D24__EMI_WEIM_D_24 IOMUX_PAD(0x484, 0x13C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D24__GPIO3_24 IOMUX_PAD(0x484, 0x13C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D24__UART3_TXD_MUX IOMUX_PAD(0x484, 0x13C, 2, 0x888, 0, 0) +#define _MX53_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, 0) +#define _MX53_PAD_EIM_D24__CSPI_SS2 IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, 0) +#define _MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, 0) +#define _MX53_PAD_EIM_D24__ECSPI2_SS2 IOMUX_PAD(0x484, 0x13C, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_D24__UART1_DTR IOMUX_PAD(0x484, 0x13C, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_D25__EMI_WEIM_D_25 IOMUX_PAD(0x488, 0x140, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D25__GPIO3_25 IOMUX_PAD(0x488, 0x140, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D25__UART3_RXD_MUX IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, 0) +#define _MX53_PAD_EIM_D25__ECSPI1_SS3 IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, 0) +#define _MX53_PAD_EIM_D25__CSPI_SS3 IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, 0) +#define _MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, 0) +#define _MX53_PAD_EIM_D25__ECSPI2_SS3 IOMUX_PAD(0x488, 0x140, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x488, 0x140, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_D26__EMI_WEIM_D_26 IOMUX_PAD(0x48C, 0x144, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D26__GPIO3_26 IOMUX_PAD(0x48C, 0x144, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D26__UART2_TXD_MUX IOMUX_PAD(0x48C, 0x144, 2, 0x880, 0, 0) +#define _MX53_PAD_EIM_D26__FIRI_RXD IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, 0) +#define _MX53_PAD_EIM_D26__IPU_CSI0_D_1 IOMUX_PAD(0x48C, 0x144, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_D26__IPU_DI1_PIN11 IOMUX_PAD(0x48C, 0x144, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_D26__IPU_SISG_2 IOMUX_PAD(0x48C, 0x144, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 IOMUX_PAD(0x48C, 0x144, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_D27__EMI_WEIM_D_27 IOMUX_PAD(0x490, 0x148, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D27__GPIO3_27 IOMUX_PAD(0x490, 0x148, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D27__UART2_RXD_MUX IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, 0) +#define _MX53_PAD_EIM_D27__FIRI_TXD IOMUX_PAD(0x490, 0x148, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D27__IPU_CSI0_D_0 IOMUX_PAD(0x490, 0x148, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_D27__IPU_DI1_PIN13 IOMUX_PAD(0x490, 0x148, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_D27__IPU_SISG_3 IOMUX_PAD(0x490, 0x148, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 IOMUX_PAD(0x490, 0x148, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_D28__EMI_WEIM_D_28 IOMUX_PAD(0x494, 0x14C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D28__GPIO3_28 IOMUX_PAD(0x494, 0x14C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, 0x87C, 0, 0) +#define _MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, 0) +#define _MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, 0) +#define _MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5, 0x818, 1, 0) +#define _MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D29__GPIO3_29 IOMUX_PAD(0x498, 0x150, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D29__UART2_RTS IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, 0) +#define _MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D29__CSPI_SS0 IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, 0) +#define _MX53_PAD_EIM_D29__IPU_DI1_PIN15 IOMUX_PAD(0x498, 0x150, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_D29__IPU_CSI1_VSYNC IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, 0) +#define _MX53_PAD_EIM_D29__IPU_DI0_PIN14 IOMUX_PAD(0x498, 0x150, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_D30__EMI_WEIM_D_30 IOMUX_PAD(0x49C, 0x154, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D30__GPIO3_30 IOMUX_PAD(0x49C, 0x154, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x49C, 0x154, 2, 0x884, 2, 0) +#define _MX53_PAD_EIM_D30__IPU_CSI0_D_3 IOMUX_PAD(0x49C, 0x154, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D30__IPU_DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 IOMUX_PAD(0x49C, 0x154, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_D30__USBOH3_USBH1_OC IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, 0) +#define _MX53_PAD_EIM_D30__USBOH3_USBH2_OC IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, 0) +#define _MX53_PAD_EIM_D31__EMI_WEIM_D_31 IOMUX_PAD(0x4A0, 0x158, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D31__GPIO3_31 IOMUX_PAD(0x4A0, 0x158, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D31__UART3_RTS IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, 0) +#define _MX53_PAD_EIM_D31__IPU_CSI0_D_2 IOMUX_PAD(0x4A0, 0x158, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D31__IPU_DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 IOMUX_PAD(0x4A0, 0x158, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_D31__USBOH3_USBH1_PWR IOMUX_PAD(0x4A0, 0x158, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_D31__USBOH3_USBH2_PWR IOMUX_PAD(0x4A0, 0x158, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A24__EMI_WEIM_A_24 IOMUX_PAD(0x4A8, 0x15C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A24__GPIO5_4 IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 IOMUX_PAD(0x4A8, 0x15C, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A24__IPU_CSI1_D_19 IOMUX_PAD(0x4A8, 0x15C, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A24__IPU_SISG_2 IOMUX_PAD(0x4A8, 0x15C, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_A24__USBPHY2_BVALID IOMUX_PAD(0x4A8, 0x15C, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A23__EMI_WEIM_A_23 IOMUX_PAD(0x4AC, 0x160, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A23__GPIO6_6 IOMUX_PAD(0x4AC, 0x160, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 IOMUX_PAD(0x4AC, 0x160, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A23__IPU_CSI1_D_18 IOMUX_PAD(0x4AC, 0x160, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A23__IPU_SISG_3 IOMUX_PAD(0x4AC, 0x160, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_A23__USBPHY2_ENDSESSION IOMUX_PAD(0x4AC, 0x160, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A22__EMI_WEIM_A_22 IOMUX_PAD(0x4B0, 0x164, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x4B0, 0x164, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 IOMUX_PAD(0x4B0, 0x164, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A22__IPU_CSI1_D_17 IOMUX_PAD(0x4B0, 0x164, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A22__SRC_BT_CFG1_7 IOMUX_PAD(0x4B0, 0x164, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A21__EMI_WEIM_A_21 IOMUX_PAD(0x4B4, 0x168, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A21__GPIO2_17 IOMUX_PAD(0x4B4, 0x168, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 IOMUX_PAD(0x4B4, 0x168, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A21__IPU_CSI1_D_16 IOMUX_PAD(0x4B4, 0x168, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A21__SRC_BT_CFG1_6 IOMUX_PAD(0x4B4, 0x168, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A20__EMI_WEIM_A_20 IOMUX_PAD(0x4B8, 0x16C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A20__GPIO2_18 IOMUX_PAD(0x4B8, 0x16C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 IOMUX_PAD(0x4B8, 0x16C, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A20__IPU_CSI1_D_15 IOMUX_PAD(0x4B8, 0x16C, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A20__SRC_BT_CFG1_5 IOMUX_PAD(0x4B8, 0x16C, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A19__EMI_WEIM_A_19 IOMUX_PAD(0x4BC, 0x170, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A19__GPIO2_19 IOMUX_PAD(0x4BC, 0x170, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 IOMUX_PAD(0x4BC, 0x170, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A19__IPU_CSI1_D_14 IOMUX_PAD(0x4BC, 0x170, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A19__SRC_BT_CFG1_4 IOMUX_PAD(0x4BC, 0x170, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A18__EMI_WEIM_A_18 IOMUX_PAD(0x4C0, 0x174, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A18__GPIO2_20 IOMUX_PAD(0x4C0, 0x174, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 IOMUX_PAD(0x4C0, 0x174, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A18__IPU_CSI1_D_13 IOMUX_PAD(0x4C0, 0x174, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A18__SRC_BT_CFG1_3 IOMUX_PAD(0x4C0, 0x174, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A17__EMI_WEIM_A_17 IOMUX_PAD(0x4C4, 0x178, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A17__GPIO2_21 IOMUX_PAD(0x4C4, 0x178, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 IOMUX_PAD(0x4C4, 0x178, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A17__IPU_CSI1_D_12 IOMUX_PAD(0x4C4, 0x178, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A17__SRC_BT_CFG1_2 IOMUX_PAD(0x4C4, 0x178, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A16__EMI_WEIM_A_16 IOMUX_PAD(0x4C8, 0x17C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A16__GPIO2_22 IOMUX_PAD(0x4C8, 0x17C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK IOMUX_PAD(0x4C8, 0x17C, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK IOMUX_PAD(0x4C8, 0x17C, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A16__SRC_BT_CFG1_1 IOMUX_PAD(0x4C8, 0x17C, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 IOMUX_PAD(0x4CC, 0x180, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_CS0__GPIO2_23 IOMUX_PAD(0x4CC, 0x180, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_CS0__ECSPI2_SCLK IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, 0) +#define _MX53_PAD_EIM_CS0__IPU_DI1_PIN5 IOMUX_PAD(0x4CC, 0x180, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 IOMUX_PAD(0x4D0, 0x184, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_CS1__GPIO2_24 IOMUX_PAD(0x4D0, 0x184, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_CS1__ECSPI2_MOSI IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, 0) +#define _MX53_PAD_EIM_CS1__IPU_DI1_PIN6 IOMUX_PAD(0x4D0, 0x184, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_OE__EMI_WEIM_OE IOMUX_PAD(0x4D4, 0x188, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_OE__GPIO2_25 IOMUX_PAD(0x4D4, 0x188, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_OE__ECSPI2_MISO IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, 0) +#define _MX53_PAD_EIM_OE__IPU_DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_OE__USBPHY2_IDDIG IOMUX_PAD(0x4D4, 0x188, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_RW__EMI_WEIM_RW IOMUX_PAD(0x4D8, 0x18C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_RW__GPIO2_26 IOMUX_PAD(0x4D8, 0x18C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_RW__ECSPI2_SS0 IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, 0) +#define _MX53_PAD_EIM_RW__IPU_DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x4D8, 0x18C, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_LBA__EMI_WEIM_LBA IOMUX_PAD(0x4DC, 0x190, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_LBA__GPIO2_27 IOMUX_PAD(0x4DC, 0x190, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_LBA__ECSPI2_SS1 IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, 0) +#define _MX53_PAD_EIM_LBA__IPU_DI1_PIN17 IOMUX_PAD(0x4DC, 0x190, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 IOMUX_PAD(0x4DC, 0x190, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 IOMUX_PAD(0x4E4, 0x194, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB0__GPIO2_28 IOMUX_PAD(0x4E4, 0x194, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 IOMUX_PAD(0x4E4, 0x194, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB0__IPU_CSI1_D_11 IOMUX_PAD(0x4E4, 0x194, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB0__GPC_PMIC_RDY IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, 0) +#define _MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 IOMUX_PAD(0x4E4, 0x194, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 IOMUX_PAD(0x4E8, 0x198, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB1__GPIO2_29 IOMUX_PAD(0x4E8, 0x198, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 IOMUX_PAD(0x4E8, 0x198, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB1__IPU_CSI1_D_10 IOMUX_PAD(0x4E8, 0x198, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 IOMUX_PAD(0x4E8, 0x198, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 IOMUX_PAD(0x4EC, 0x19C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA0__GPIO3_0 IOMUX_PAD(0x4EC, 0x19C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 IOMUX_PAD(0x4EC, 0x19C, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA0__IPU_CSI1_D_9 IOMUX_PAD(0x4EC, 0x19C, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 IOMUX_PAD(0x4EC, 0x19C, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 IOMUX_PAD(0x4F0, 0x1A0, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA1__GPIO3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 IOMUX_PAD(0x4F0, 0x1A0, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA1__IPU_CSI1_D_8 IOMUX_PAD(0x4F0, 0x1A0, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 IOMUX_PAD(0x4F0, 0x1A0, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 IOMUX_PAD(0x4F4, 0x1A4, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA2__GPIO3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 IOMUX_PAD(0x4F4, 0x1A4, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA2__IPU_CSI1_D_7 IOMUX_PAD(0x4F4, 0x1A4, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 IOMUX_PAD(0x4F4, 0x1A4, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 IOMUX_PAD(0x4F8, 0x1A8, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA3__GPIO3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 IOMUX_PAD(0x4F8, 0x1A8, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA3__IPU_CSI1_D_6 IOMUX_PAD(0x4F8, 0x1A8, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 IOMUX_PAD(0x4F8, 0x1A8, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 IOMUX_PAD(0x4FC, 0x1AC, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA4__GPIO3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 IOMUX_PAD(0x4FC, 0x1AC, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA4__IPU_CSI1_D_5 IOMUX_PAD(0x4FC, 0x1AC, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 IOMUX_PAD(0x4FC, 0x1AC, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 IOMUX_PAD(0x500, 0x1B0, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 17, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA6__IPU_CSI1_D_3 IOMUX_PAD(0x504, 0x1B4, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 IOMUX_PAD(0x504, 0x1B4, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 IOMUX_PAD(0x508, 0x1B8, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA7__GPIO3_7 IOMUX_PAD(0x508, 0x1B8, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 IOMUX_PAD(0x508, 0x1B8, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA7__IPU_CSI1_D_2 IOMUX_PAD(0x508, 0x1B8, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 IOMUX_PAD(0x508, 0x1B8, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 IOMUX_PAD(0x50C, 0x1BC, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA8__GPIO3_8 IOMUX_PAD(0x50C, 0x1BC, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 IOMUX_PAD(0x50C, 0x1BC, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA8__IPU_CSI1_D_1 IOMUX_PAD(0x50C, 0x1BC, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 IOMUX_PAD(0x50C, 0x1BC, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 IOMUX_PAD(0x510, 0x1C0, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA9__GPIO3_9 IOMUX_PAD(0x510, 0x1C0, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 IOMUX_PAD(0x510, 0x1C0, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA9__IPU_CSI1_D_0 IOMUX_PAD(0x510, 0x1C0, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 IOMUX_PAD(0x510, 0x1C0, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA10__GPIO3_10 IOMUX_PAD(0x514, 0x1C4, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA10__IPU_DI1_PIN15 IOMUX_PAD(0x514, 0x1C4, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, 0) +#define _MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 IOMUX_PAD(0x514, 0x1C4, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA11__GPIO3_11 IOMUX_PAD(0x518, 0x1C8, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA11__IPU_DI1_PIN2 IOMUX_PAD(0x518, 0x1C8, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, 0) +#define _MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA12__GPIO3_12 IOMUX_PAD(0x51C, 0x1CC, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA12__IPU_DI1_PIN3 IOMUX_PAD(0x51C, 0x1CC, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, 0) +#define _MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA13__GPIO3_13 IOMUX_PAD(0x520, 0x1D0, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA13__IPU_DI1_D0_CS IOMUX_PAD(0x520, 0x1D0, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, 0) +#define _MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA14__GPIO3_14 IOMUX_PAD(0x524, 0x1D4, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA14__IPU_DI1_D1_CS IOMUX_PAD(0x524, 0x1D4, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK IOMUX_PAD(0x524, 0x1D4, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA15__GPIO3_15 IOMUX_PAD(0x528, 0x1D8, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN1 IOMUX_PAD(0x528, 0x1D8, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN4 IOMUX_PAD(0x528, 0x1D8, 4, 0x0, 0, 0) +#define _MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_WE_B__GPIO6_12 IOMUX_PAD(0x52C, 0x1DC, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_RE_B__GPIO6_13 IOMUX_PAD(0x530, 0x1E0, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT IOMUX_PAD(0x534, 0x1E4, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_WAIT__GPIO5_0 IOMUX_PAD(0x534, 0x1E4, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B IOMUX_PAD(0x534, 0x1E4, 2, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_TX3_P__GPIO6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 IOMUX_PAD(NON_PAD_I, 0x1EC, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_TX2_P__GPIO6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 IOMUX_PAD(NON_PAD_I, 0x1F0, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_CLK_P__GPIO6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK IOMUX_PAD(NON_PAD_I, 0x1F4, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_TX1_P__GPIO6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 IOMUX_PAD(NON_PAD_I, 0x1F8, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_TX0_P__GPIO6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 IOMUX_PAD(NON_PAD_I, 0x1FC, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_TX3_P__GPIO7_22 IOMUX_PAD(NON_PAD_I, 0x200, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 IOMUX_PAD(NON_PAD_I, 0x200, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_CLK_P__GPIO7_24 IOMUX_PAD(NON_PAD_I, 0x204, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK IOMUX_PAD(NON_PAD_I, 0x204, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_TX2_P__GPIO7_26 IOMUX_PAD(NON_PAD_I, 0x208, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 IOMUX_PAD(NON_PAD_I, 0x208, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_TX1_P__GPIO7_28 IOMUX_PAD(NON_PAD_I, 0x20C, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 IOMUX_PAD(NON_PAD_I, 0x20C, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_TX0_P__GPIO7_30 IOMUX_PAD(NON_PAD_I, 0x210, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 IOMUX_PAD(NON_PAD_I, 0x210, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_10__GPIO4_0 IOMUX_PAD(0x540, 0x214, 0, 0x0, 0, 0) +#define _MX53_PAD_GPIO_10__OSC32k_32K_OUT IOMUX_PAD(0x540, 0x214, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_11__GPIO4_1 IOMUX_PAD(0x544, 0x218, 0, 0x0, 0, 0) +#define _MX53_PAD_GPIO_12__GPIO4_2 IOMUX_PAD(0x548, 0x21C, 0, 0x0, 0, 0) +#define _MX53_PAD_GPIO_13__GPIO4_3 IOMUX_PAD(0x54C, 0x220, 0, 0x0, 0, 0) +#define _MX53_PAD_GPIO_14__GPIO4_4 IOMUX_PAD(0x550, 0x224, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CLE__EMI_NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CLE__GPIO6_7 IOMUX_PAD(0x5A0, 0x228, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 IOMUX_PAD(0x5A0, 0x228, 7, 0x0, 0, 0) +#define _MX53_PAD_NANDF_ALE__EMI_NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_ALE__GPIO6_8 IOMUX_PAD(0x5A4, 0x22C, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 IOMUX_PAD(0x5A4, 0x22C, 7, 0x0, 0, 0) +#define _MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_WP_B__GPIO6_9 IOMUX_PAD(0x5A8, 0x230, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, 0x0, 0, 0) +#define _MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 IOMUX_PAD(0x5AC, 0x234, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_RB0__GPIO6_10 IOMUX_PAD(0x5AC, 0x234, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 IOMUX_PAD(0x5AC, 0x234, 7, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 IOMUX_PAD(0x5B0, 0x238, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS0__GPIO6_11 IOMUX_PAD(0x5B0, 0x238, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 IOMUX_PAD(0x5B0, 0x238, 7, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 IOMUX_PAD(0x5B4, 0x23C, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS1__GPIO6_14 IOMUX_PAD(0x5B4, 0x23C, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS1__MLB_MLBCLK IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, 0) +#define _MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 IOMUX_PAD(0x5B4, 0x23C, 7, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 IOMUX_PAD(0x5B8, 0x240, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS2__GPIO6_15 IOMUX_PAD(0x5B8, 0x240, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS2__IPU_SISG_0 IOMUX_PAD(0x5B8, 0x240, 2, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS2__ESAI1_TX0 IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, 0) +#define _MX53_PAD_NANDF_CS2__EMI_WEIM_CRE IOMUX_PAD(0x5B8, 0x240, 4, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK IOMUX_PAD(0x5B8, 0x240, 5, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS2__MLB_MLBSIG IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, 0) +#define _MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 IOMUX_PAD(0x5B8, 0x240, 7, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 IOMUX_PAD(0x5BC, 0x244, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS3__GPIO6_16 IOMUX_PAD(0x5BC, 0x244, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS3__IPU_SISG_1 IOMUX_PAD(0x5BC, 0x244, 2, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS3__ESAI1_TX1 IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, 0) +#define _MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 IOMUX_PAD(0x5BC, 0x244, 4, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS3__MLB_MLBDAT IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, 0) +#define _MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 IOMUX_PAD(0x5BC, 0x244, 7, 0x0, 0, 0) +#define _MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, 0) +#define _MX53_PAD_FEC_MDIO__GPIO1_22 IOMUX_PAD(0x5C4, 0x248, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_MDIO__ESAI1_SCKR IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, 0) +#define _MX53_PAD_FEC_MDIO__FEC_COL IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, 0) +#define _MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 IOMUX_PAD(0x5C4, 0x248, 4, 0x0, 0, 0) +#define _MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x5C4, 0x248, 5, 0x0, 0, 0) +#define _MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 IOMUX_PAD(0x5C4, 0x248, 6, 0x0, 0, 0) +#define _MX53_PAD_FEC_REF_CLK__FEC_TX_CLK IOMUX_PAD(0x5C8, 0x24C, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_REF_CLK__GPIO1_23 IOMUX_PAD(0x5C8, 0x24C, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_REF_CLK__ESAI1_FSR IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, 0) +#define _MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x5C8, 0x24C, 5, 0x0, 0, 0) +#define _MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, 0x0, 0, 0) +#define _MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_RX_ER__GPIO1_24 IOMUX_PAD(0x5CC, 0x250, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_RX_ER__ESAI1_HCKR IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, 0) +#define _MX53_PAD_FEC_RX_ER__FEC_RX_CLK IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, 0) +#define _MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 IOMUX_PAD(0x5CC, 0x250, 4, 0x0, 0, 0) +#define _MX53_PAD_FEC_CRS_DV__FEC_RX_DV IOMUX_PAD(0x5D0, 0x254, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_CRS_DV__GPIO1_25 IOMUX_PAD(0x5D0, 0x254, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_CRS_DV__ESAI1_SCKT IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, 0) +#define _MX53_PAD_FEC_RXD1__FEC_RDATA_1 IOMUX_PAD(0x5D4, 0x258, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_RXD1__GPIO1_26 IOMUX_PAD(0x5D4, 0x258, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_RXD1__ESAI1_FST IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, 0) +#define _MX53_PAD_FEC_RXD1__MLB_MLBSIG IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, 0) +#define _MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 IOMUX_PAD(0x5D4, 0x258, 4, 0x0, 0, 0) +#define _MX53_PAD_FEC_RXD0__FEC_RDATA_0 IOMUX_PAD(0x5D8, 0x25C, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_RXD0__GPIO1_27 IOMUX_PAD(0x5D8, 0x25C, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_RXD0__ESAI1_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, 0) +#define _MX53_PAD_FEC_RXD0__OSC32k_32K_OUT IOMUX_PAD(0x5D8, 0x25C, 3, 0x0, 0, 0) +#define _MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_TX_EN__GPIO1_28 IOMUX_PAD(0x5DC, 0x260, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, 0) +#define _MX53_PAD_FEC_TXD1__FEC_TDATA_1 IOMUX_PAD(0x5E0, 0x264, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_TXD1__GPIO1_29 IOMUX_PAD(0x5E0, 0x264, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, 0) +#define _MX53_PAD_FEC_TXD1__MLB_MLBCLK IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, 0) +#define _MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, 0x0, 0, 0) +#define _MX53_PAD_FEC_TXD0__FEC_TDATA_0 IOMUX_PAD(0x5E4, 0x268, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_TXD0__GPIO1_30 IOMUX_PAD(0x5E4, 0x268, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, 0) +#define _MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 IOMUX_PAD(0x5E4, 0x268, 7, 0x0, 0, 0) +#define _MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_MDC__GPIO1_31 IOMUX_PAD(0x5E8, 0x26C, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, 0) +#define _MX53_PAD_FEC_MDC__MLB_MLBDAT IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, 0) +#define _MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG IOMUX_PAD(0x5E8, 0x26C, 4, 0x0, 0, 0) +#define _MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 IOMUX_PAD(0x5E8, 0x26C, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DIOW__PATA_DIOW IOMUX_PAD(0x5F0, 0x270, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DIOW__GPIO6_17 IOMUX_PAD(0x5F0, 0x270, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DIOW__UART1_TXD_MUX IOMUX_PAD(0x5F0, 0x270, 3, 0x878, 2, 0) +#define _MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 IOMUX_PAD(0x5F0, 0x270, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DMACK__PATA_DMACK IOMUX_PAD(0x5F4, 0x274, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DMACK__GPIO6_18 IOMUX_PAD(0x5F4, 0x274, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DMACK__UART1_RXD_MUX IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, 0) +#define _MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, 0x880, 2, 0) +#define _MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_BUFFER_EN__GPIO7_1 IOMUX_PAD(0x5FC, 0x27C, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, 0) +#define _MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 IOMUX_PAD(0x5FC, 0x27C, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_INTRQ__PATA_INTRQ IOMUX_PAD(0x600, 0x280, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_INTRQ__GPIO7_2 IOMUX_PAD(0x600, 0x280, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, 0x87C, 2, 0) +#define _MX53_PAD_PATA_INTRQ__CAN1_TXCAN IOMUX_PAD(0x600, 0x280, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 IOMUX_PAD(0x600, 0x280, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DIOR__PATA_DIOR IOMUX_PAD(0x604, 0x284, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DIOR__GPIO7_3 IOMUX_PAD(0x604, 0x284, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, 0) +#define _MX53_PAD_PATA_DIOR__CAN1_RXCAN IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, 0) +#define _MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 IOMUX_PAD(0x604, 0x284, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B IOMUX_PAD(0x608, 0x288, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_RESET_B__GPIO7_4 IOMUX_PAD(0x608, 0x288, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_RESET_B__ESDHC3_CMD IOMUX_PAD(0x608, 0x288, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_RESET_B__UART1_CTS IOMUX_PAD(0x608, 0x288, 3, 0x874, 2, 0) +#define _MX53_PAD_PATA_RESET_B__CAN2_TXCAN IOMUX_PAD(0x608, 0x288, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 IOMUX_PAD(0x608, 0x288, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_IORDY__PATA_IORDY IOMUX_PAD(0x60C, 0x28C, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_IORDY__GPIO7_5 IOMUX_PAD(0x60C, 0x28C, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_IORDY__ESDHC3_CLK IOMUX_PAD(0x60C, 0x28C, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_IORDY__UART1_RTS IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, 0) +#define _MX53_PAD_PATA_IORDY__CAN2_RXCAN IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, 0) +#define _MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_0__PATA_DA_0 IOMUX_PAD(0x610, 0x290, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_0__GPIO7_6 IOMUX_PAD(0x610, 0x290, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_0__ESDHC3_RST IOMUX_PAD(0x610, 0x290, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_0__OWIRE_LINE IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, 0) +#define _MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 IOMUX_PAD(0x610, 0x290, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_1__PATA_DA_1 IOMUX_PAD(0x614, 0x294, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_1__GPIO7_7 IOMUX_PAD(0x614, 0x294, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_1__ESDHC4_CMD IOMUX_PAD(0x614, 0x294, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, 0x884, 4, 0) +#define _MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 IOMUX_PAD(0x614, 0x294, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_2__PATA_DA_2 IOMUX_PAD(0x618, 0x298, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_2__GPIO7_8 IOMUX_PAD(0x618, 0x298, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_2__ESDHC4_CLK IOMUX_PAD(0x618, 0x298, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, 0) +#define _MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 IOMUX_PAD(0x618, 0x298, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_CS_0__PATA_CS_0 IOMUX_PAD(0x61C, 0x29C, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_CS_0__GPIO7_9 IOMUX_PAD(0x61C, 0x29C, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_CS_0__UART3_TXD_MUX IOMUX_PAD(0x61C, 0x29C, 4, 0x888, 2, 0) +#define _MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 IOMUX_PAD(0x61C, 0x29C, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_CS_1__PATA_CS_1 IOMUX_PAD(0x620, 0x2A0, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_CS_1__GPIO7_10 IOMUX_PAD(0x620, 0x2A0, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_CS_1__UART3_RXD_MUX IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, 0) +#define _MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 IOMUX_PAD(0x620, 0x2A0, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA0__PATA_DATA_0 IOMUX_PAD(0x628, 0x2A4, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA0__GPIO2_0 IOMUX_PAD(0x628, 0x2A4, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 IOMUX_PAD(0x628, 0x2A4, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA0__ESDHC3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 IOMUX_PAD(0x628, 0x2A4, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 IOMUX_PAD(0x628, 0x2A4, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA1__PATA_DATA_1 IOMUX_PAD(0x62C, 0x2A8, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA1__GPIO2_1 IOMUX_PAD(0x62C, 0x2A8, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 IOMUX_PAD(0x62C, 0x2A8, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA1__ESDHC3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 IOMUX_PAD(0x62C, 0x2A8, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 IOMUX_PAD(0x62C, 0x2A8, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA2__PATA_DATA_2 IOMUX_PAD(0x630, 0x2AC, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA2__GPIO2_2 IOMUX_PAD(0x630, 0x2AC, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 IOMUX_PAD(0x630, 0x2AC, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA2__ESDHC3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 IOMUX_PAD(0x630, 0x2AC, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 IOMUX_PAD(0x630, 0x2AC, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA3__PATA_DATA_3 IOMUX_PAD(0x634, 0x2B0, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA3__GPIO2_3 IOMUX_PAD(0x634, 0x2B0, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 IOMUX_PAD(0x634, 0x2B0, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA3__ESDHC3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 IOMUX_PAD(0x634, 0x2B0, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 IOMUX_PAD(0x634, 0x2B0, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA4__PATA_DATA_4 IOMUX_PAD(0x638, 0x2B4, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA4__GPIO2_4 IOMUX_PAD(0x638, 0x2B4, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 IOMUX_PAD(0x638, 0x2B4, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA4__ESDHC4_DAT4 IOMUX_PAD(0x638, 0x2B4, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 IOMUX_PAD(0x638, 0x2B4, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 IOMUX_PAD(0x638, 0x2B4, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA5__PATA_DATA_5 IOMUX_PAD(0x63C, 0x2B8, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA5__GPIO2_5 IOMUX_PAD(0x63C, 0x2B8, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 IOMUX_PAD(0x63C, 0x2B8, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA7__ESDHC4_DAT7 IOMUX_PAD(0x644, 0x2C0, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 IOMUX_PAD(0x644, 0x2C0, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 IOMUX_PAD(0x644, 0x2C0, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA8__PATA_DATA_8 IOMUX_PAD(0x648, 0x2C4, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA8__GPIO2_8 IOMUX_PAD(0x648, 0x2C4, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA8__ESDHC1_DAT4 IOMUX_PAD(0x648, 0x2C4, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 IOMUX_PAD(0x648, 0x2C4, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA8__ESDHC3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 IOMUX_PAD(0x648, 0x2C4, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 IOMUX_PAD(0x648, 0x2C4, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA9__PATA_DATA_9 IOMUX_PAD(0x64C, 0x2C8, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA9__GPIO2_9 IOMUX_PAD(0x64C, 0x2C8, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA9__ESDHC1_DAT5 IOMUX_PAD(0x64C, 0x2C8, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 IOMUX_PAD(0x64C, 0x2C8, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA9__ESDHC3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 IOMUX_PAD(0x64C, 0x2C8, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 IOMUX_PAD(0x64C, 0x2C8, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA10__PATA_DATA_10 IOMUX_PAD(0x650, 0x2CC, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA10__GPIO2_10 IOMUX_PAD(0x650, 0x2CC, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA10__ESDHC1_DAT6 IOMUX_PAD(0x650, 0x2CC, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 IOMUX_PAD(0x650, 0x2CC, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA10__ESDHC3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 IOMUX_PAD(0x650, 0x2CC, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 IOMUX_PAD(0x650, 0x2CC, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA11__PATA_DATA_11 IOMUX_PAD(0x654, 0x2D0, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA11__GPIO2_11 IOMUX_PAD(0x654, 0x2D0, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA11__ESDHC1_DAT7 IOMUX_PAD(0x654, 0x2D0, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 IOMUX_PAD(0x654, 0x2D0, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA11__ESDHC3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 IOMUX_PAD(0x654, 0x2D0, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 IOMUX_PAD(0x654, 0x2D0, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA12__PATA_DATA_12 IOMUX_PAD(0x658, 0x2D4, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA12__GPIO2_12 IOMUX_PAD(0x658, 0x2D4, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA12__ESDHC2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 IOMUX_PAD(0x658, 0x2D4, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA12__ESDHC4_DAT0 IOMUX_PAD(0x658, 0x2D4, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 IOMUX_PAD(0x658, 0x2D4, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 IOMUX_PAD(0x658, 0x2D4, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA13__PATA_DATA_13 IOMUX_PAD(0x65C, 0x2D8, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA13__GPIO2_13 IOMUX_PAD(0x65C, 0x2D8, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA13__ESDHC2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 IOMUX_PAD(0x65C, 0x2D8, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA13__ESDHC4_DAT1 IOMUX_PAD(0x65C, 0x2D8, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 IOMUX_PAD(0x65C, 0x2D8, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 IOMUX_PAD(0x65C, 0x2D8, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA14__PATA_DATA_14 IOMUX_PAD(0x660, 0x2DC, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA14__GPIO2_14 IOMUX_PAD(0x660, 0x2DC, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA14__ESDHC2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 IOMUX_PAD(0x660, 0x2DC, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA14__ESDHC4_DAT2 IOMUX_PAD(0x660, 0x2DC, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 IOMUX_PAD(0x660, 0x2DC, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 IOMUX_PAD(0x660, 0x2DC, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA15__PATA_DATA_15 IOMUX_PAD(0x664, 0x2E0, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA15__GPIO2_15 IOMUX_PAD(0x664, 0x2E0, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA15__ESDHC2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 IOMUX_PAD(0x664, 0x2E0, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA15__ESDHC4_DAT3 IOMUX_PAD(0x664, 0x2E0, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 IOMUX_PAD(0x664, 0x2E0, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 IOMUX_PAD(0x664, 0x2E0, 6, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x66C, 0x2E4, 0, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA0__GPIO1_16 IOMUX_PAD(0x66C, 0x2E4, 1, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, 0) +#define _MX53_PAD_SD1_DATA0__CCM_PLL3_BYP IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, 0) +#define _MX53_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x670, 0x2E8, 0, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA1__GPIO1_17 IOMUX_PAD(0x670, 0x2E8, 1, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA1__CSPI_SS0 IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, 0) +#define _MX53_PAD_SD1_DATA1__CCM_PLL4_BYP IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, 0) +#define _MX53_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x674, 0x2EC, IOMUX_CONFIG_SION, 0x0, 0, 0) +#define _MX53_PAD_SD1_CMD__GPIO1_18 IOMUX_PAD(0x674, 0x2EC, 1, 0x0, 0, 0) +#define _MX53_PAD_SD1_CMD__GPT_CMPOUT1 IOMUX_PAD(0x674, 0x2EC, 3, 0x0, 0, 0) +#define _MX53_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, 0) +#define _MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, 0) +#define _MX53_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x678, 0x2F0, 0, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA2__GPIO1_19 IOMUX_PAD(0x678, 0x2F0, 1, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA2__GPT_CMPOUT2 IOMUX_PAD(0x678, 0x2F0, 2, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA2__PWM2_PWMO IOMUX_PAD(0x678, 0x2F0, 3, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_B IOMUX_PAD(0x678, 0x2F0, 4, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA2__CSPI_SS1 IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, 0) +#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x678, 0x2F0, 6, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA2__CCM_PLL2_BYP IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, 0) +#define _MX53_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x67C, 0x2F4, 0, 0x0, 0, 0) +#define _MX53_PAD_SD1_CLK__GPIO1_20 IOMUX_PAD(0x67C, 0x2F4, 1, 0x0, 0, 0) +#define _MX53_PAD_SD1_CLK__OSC32k_32K_OUT IOMUX_PAD(0x67C, 0x2F4, 2, 0x0, 0, 0) +#define _MX53_PAD_SD1_CLK__GPT_CLKIN IOMUX_PAD(0x67C, 0x2F4, 3, 0x0, 0, 0) +#define _MX53_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, 0) +#define _MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 IOMUX_PAD(0x67C, 0x2F4, 7, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x680, 0x2F8, 0, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA3__GPIO1_21 IOMUX_PAD(0x680, 0x2F8, 1, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA3__GPT_CMPOUT3 IOMUX_PAD(0x680, 0x2F8, 2, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA3__PWM1_PWMO IOMUX_PAD(0x680, 0x2F8, 3, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_B IOMUX_PAD(0x680, 0x2F8, 4, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA3__CSPI_SS2 IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, 0) +#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x680, 0x2F8, 6, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 IOMUX_PAD(0x680, 0x2F8, 7, 0x0, 0, 0) +#define _MX53_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x688, 0x2FC, 0, 0x0, 0, 0) +#define _MX53_PAD_SD2_CLK__GPIO1_10 IOMUX_PAD(0x688, 0x2FC, 1, 0x0, 0, 0) +#define _MX53_PAD_SD2_CLK__KPP_COL_5 IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, 0) +#define _MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, 0) +#define _MX53_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, 0) +#define _MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, 0x0, 0, 0) +#define _MX53_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x68C, 0x300, 0, 0x0, 0, 0) +#define _MX53_PAD_SD2_CMD__GPIO1_11 IOMUX_PAD(0x68C, 0x300, 1, 0x0, 0, 0) +#define _MX53_PAD_SD2_CMD__KPP_ROW_5 IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, 0) +#define _MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, 0) +#define _MX53_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, 0) +#define _MX53_PAD_SD2_CMD__SCC_RANDOM IOMUX_PAD(0x68C, 0x300, 7, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x690, 0x304, 0, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA3__GPIO1_12 IOMUX_PAD(0x690, 0x304, 1, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA3__KPP_COL_6 IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, 0) +#define _MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, 0) +#define _MX53_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, 0) +#define _MX53_PAD_SD2_DATA3__SJC_DONE IOMUX_PAD(0x690, 0x304, 7, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x694, 0x308, 0, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA2__GPIO1_13 IOMUX_PAD(0x694, 0x308, 1, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA2__KPP_ROW_6 IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, 0) +#define _MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, 0) +#define _MX53_PAD_SD2_DATA2__CSPI_SS1 IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, 0) +#define _MX53_PAD_SD2_DATA2__SJC_FAIL IOMUX_PAD(0x694, 0x308, 7, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA1__GPIO1_14 IOMUX_PAD(0x698, 0x30C, 1, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA1__KPP_COL_7 IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, 0) +#define _MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, 0) +#define _MX53_PAD_SD2_DATA1__CSPI_SS0 IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, 0) +#define _MX53_PAD_SD2_DATA1__RTIC_SEC_VIO IOMUX_PAD(0x698, 0x30C, 7, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA0__GPIO1_15 IOMUX_PAD(0x69C, 0x310, 1, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA0__KPP_ROW_7 IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, 0) +#define _MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, 0) +#define _MX53_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, 0) +#define _MX53_PAD_SD2_DATA0__RTIC_DONE_INT IOMUX_PAD(0x69C, 0x310, 7, 0x0, 0, 0) +#define _MX53_PAD_GPIO_0__CCM_CLKO IOMUX_PAD(0x6A4, 0x314, 0, 0x0, 0, 0) +#define _MX53_PAD_GPIO_0__GPIO1_0 IOMUX_PAD(0x6A4, 0x314, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_0__KPP_COL_5 IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, 0) +#define _MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_0__EPIT1_EPITO IOMUX_PAD(0x6A4, 0x314, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_0__SRTC_ALARM_DEB IOMUX_PAD(0x6A4, 0x314, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_0__USBOH3_USBH1_PWR IOMUX_PAD(0x6A4, 0x314, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_0__CSU_TD IOMUX_PAD(0x6A4, 0x314, 7, 0x0, 0, 0) +#define _MX53_PAD_GPIO_1__ESAI1_SCKR IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, 0) +#define _MX53_PAD_GPIO_1__GPIO1_1 IOMUX_PAD(0x6A8, 0x318, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_1__KPP_ROW_5 IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, 0) +#define _MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK IOMUX_PAD(0x6A8, 0x318, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_1__PWM2_PWMO IOMUX_PAD(0x6A8, 0x318, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_1__WDOG2_WDOG_B IOMUX_PAD(0x6A8, 0x318, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_1__ESDHC1_CD IOMUX_PAD(0x6A8, 0x318, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_1__SRC_TESTER_ACK IOMUX_PAD(0x6A8, 0x318, 7, 0x0, 0, 0) +#define _MX53_PAD_GPIO_9__ESAI1_FSR IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, 0) +#define _MX53_PAD_GPIO_9__GPIO1_9 IOMUX_PAD(0x6AC, 0x31C, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_9__KPP_COL_6 IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, 0) +#define _MX53_PAD_GPIO_9__CCM_REF_EN_B IOMUX_PAD(0x6AC, 0x31C, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_9__PWM1_PWMO IOMUX_PAD(0x6AC, 0x31C, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_9__WDOG1_WDOG_B IOMUX_PAD(0x6AC, 0x31C, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_9__ESDHC1_WP IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, 0) +#define _MX53_PAD_GPIO_9__SCC_FAIL_STATE IOMUX_PAD(0x6AC, 0x31C, 7, 0x0, 0, 0) +#define _MX53_PAD_GPIO_3__ESAI1_HCKR IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, 0) +#define _MX53_PAD_GPIO_3__GPIO1_3 IOMUX_PAD(0x6B0, 0x320, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, 0) +#define _MX53_PAD_GPIO_3__DPLLIP1_TOG_EN IOMUX_PAD(0x6B0, 0x320, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_3__CCM_CLKO2 IOMUX_PAD(0x6B0, 0x320, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x6B0, 0x320, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_3__USBOH3_USBH1_OC IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, 0) +#define _MX53_PAD_GPIO_3__MLB_MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, 0) +#define _MX53_PAD_GPIO_6__ESAI1_SCKT IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, 0) +#define _MX53_PAD_GPIO_6__GPIO1_6 IOMUX_PAD(0x6B4, 0x324, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, 0) +#define _MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_6__CSU_CSU_INT_DEB IOMUX_PAD(0x6B4, 0x324, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x6B4, 0x324, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_6__ESDHC2_LCTL IOMUX_PAD(0x6B4, 0x324, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_6__MLB_MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, 0) +#define _MX53_PAD_GPIO_2__ESAI1_FST IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, 0) +#define _MX53_PAD_GPIO_2__GPIO1_2 IOMUX_PAD(0x6B8, 0x328, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_2__KPP_ROW_6 IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, 0) +#define _MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 IOMUX_PAD(0x6B8, 0x328, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x6B8, 0x328, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_2__ESDHC2_WP IOMUX_PAD(0x6B8, 0x328, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_2__MLB_MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, 0) +#define _MX53_PAD_GPIO_4__ESAI1_HCKT IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, 0) +#define _MX53_PAD_GPIO_4__GPIO1_4 IOMUX_PAD(0x6BC, 0x32C, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_4__KPP_COL_7 IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, 0) +#define _MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 IOMUX_PAD(0x6BC, 0x32C, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x6BC, 0x32C, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_4__ESDHC2_CD IOMUX_PAD(0x6BC, 0x32C, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, 0x0, 0, 0) +#define _MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, 0) +#define _MX53_PAD_GPIO_5__GPIO1_5 IOMUX_PAD(0x6C0, 0x330, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_5__KPP_ROW_7 IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, 0) +#define _MX53_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x6C0, 0x330, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x6C0, 0x330, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x6C0, 0x330, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6, 0x824, 2, 0) +#define _MX53_PAD_GPIO_5__CCM_PLL1_BYP IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, 0) +#define _MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, 0) +#define _MX53_PAD_GPIO_7__GPIO1_7 IOMUX_PAD(0x6C4, 0x334, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x6C4, 0x334, 2, 0x0, 0, 0) +#define _MX53_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x6C4, 0x334, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, 0x880, 4, 0) +#define _MX53_PAD_GPIO_7__FIRI_RXD IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, 0) +#define _MX53_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x6C4, 0x334, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_7__CCM_PLL2_BYP IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, 0) +#define _MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, 0) +#define _MX53_PAD_GPIO_8__GPIO1_8 IOMUX_PAD(0x6C8, 0x338, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x6C8, 0x338, 2, 0x0, 0, 0) +#define _MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, 0) +#define _MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, 0) +#define _MX53_PAD_GPIO_8__FIRI_TXD IOMUX_PAD(0x6C8, 0x338, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x6C8, 0x338, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_8__CCM_PLL3_BYP IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, 0) +#define _MX53_PAD_GPIO_16__ESAI1_TX3_RX2 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, 0) +#define _MX53_PAD_GPIO_16__GPIO7_11 IOMUX_PAD(0x6CC, 0x33C, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT IOMUX_PAD(0x6CC, 0x33C, 2, 0x0, 0, 0) +#define _MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_16__SPDIF_IN1 IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, 0) +#define _MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, 0) +#define _MX53_PAD_GPIO_16__SJC_DE_B IOMUX_PAD(0x6CC, 0x33C, 7, 0x0, 0, 0) +#define _MX53_PAD_GPIO_17__ESAI1_TX0 IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, 0) +#define _MX53_PAD_GPIO_17__GPIO7_12 IOMUX_PAD(0x6D0, 0x340, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, 0) +#define _MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, 0) +#define _MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG IOMUX_PAD(0x6D0, 0x340, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x6D0, 0x340, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_17__IPU_SNOOP2 IOMUX_PAD(0x6D0, 0x340, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, 0x0, 0, 0) +#define _MX53_PAD_GPIO_18__ESAI1_TX1 IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, 0) +#define _MX53_PAD_GPIO_18__GPIO7_13 IOMUX_PAD(0x6D4, 0x344, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, 0) +#define _MX53_PAD_GPIO_18__OWIRE_LINE IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, 0) +#define _MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG IOMUX_PAD(0x6D4, 0x344, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, 0) +#define _MX53_PAD_GPIO_18__ESDHC1_LCTL IOMUX_PAD(0x6D4, 0x344, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_18__SRC_SYSTEM_RST IOMUX_PAD(0x6D4, 0x344, 7, 0x0, 0, 0) -#define MX53_PAD_GPIO_19__GPIO_4_5 IOMUX_PAD(0x348, 0x20,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL0__GPIO_4_6 IOMUX_PAD(0x34C, 0x24,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW0__GPIO_4_7 IOMUX_PAD(0x350, 0x28,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL1__GPIO_4_8 IOMUX_PAD(0x354, 0x2C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW1__GPIO_4_9 IOMUX_PAD(0x358, 0x30,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL2__GPIO_4_10 IOMUX_PAD(0x35C, 0x34,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW2__GPIO_4_11 IOMUX_PAD(0x360, 0x38,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL3__GPIO_4_12 IOMUX_PAD(0x364, 0x3C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW3__GPIO_4_13 IOMUX_PAD(0x368, 0x40,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL4__GPIO_4_14 IOMUX_PAD(0x36C, 0x44,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW4__GPIO_4_15 IOMUX_PAD(0x370, 0x48,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NVCC_KEYPAD__NVCC_KEYPAD IOMUX_PAD(0x374, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_DISP_CLK__GPIO_4_16 IOMUX_PAD(0x378, 0x4C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN15__GPIO_4_17 IOMUX_PAD(0x37C, 0x50,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN2__GPIO_4_18 IOMUX_PAD(0x380, 0x54,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN3__GPIO_4_19 IOMUX_PAD(0x384, 0x58,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN4__GPIO_4_20 IOMUX_PAD(0x388, 0x5C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT0__GPIO_4_21 IOMUX_PAD(0x38C, 0x60,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT1__GPIO_4_22 IOMUX_PAD(0x390, 0x64,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT2__GPIO_4_23 IOMUX_PAD(0x394, 0x68,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT3__GPIO_4_24 IOMUX_PAD(0x398, 0x6C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT4__GPIO_4_25 IOMUX_PAD(0x39C, 0x70,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT5__GPIO_4_26 IOMUX_PAD(0x3A0, 0x74,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT6__GPIO_4_27 IOMUX_PAD(0x3A4, 0x78,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT7__GPIO_4_28 IOMUX_PAD(0x3A8, 0x7C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT8__GPIO_4_29 IOMUX_PAD(0x3AC, 0x80,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT9__GPIO_4_30 IOMUX_PAD(0x3B0, 0x84,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT10__GPIO_4_31 IOMUX_PAD(0x3B4, 0x88,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT11__GPIO_5_5 IOMUX_PAD(0x3B8, 0x8C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT12__GPIO_5_6 IOMUX_PAD(0x3BC, 0x90,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT13__GPIO_5_7 IOMUX_PAD(0x3C0, 0x94,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT14__GPIO_5_8 IOMUX_PAD(0x3C4, 0x98,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT15__GPIO_5_9 IOMUX_PAD(0x3C8, 0x9C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT16__GPIO_5_10 IOMUX_PAD(0x3CC, 0xA0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT17__GPIO_5_11 IOMUX_PAD(0x3D0, 0xA4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT18__GPIO_5_12 IOMUX_PAD(0x3D4, 0xA8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT19__GPIO_5_13 IOMUX_PAD(0x3D8, 0xAC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT20__GPIO_5_14 IOMUX_PAD(0x3DC, 0xB0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT21__GPIO_5_15 IOMUX_PAD(0x3E0, 0xB4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT22__GPIO_5_16 IOMUX_PAD(0x3E4, 0xB8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT23__GPIO_5_17 IOMUX_PAD(0x3E8, 0xBC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_PIXCLK__GPIO_5_18 IOMUX_PAD(0x3EC, 0xC0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_MCLK__GPIO_5_19 IOMUX_PAD(0x3F0, 0xC4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DATA_EN__GPIO_5_20 IOMUX_PAD(0x3F4, 0xC8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_VSYNC__GPIO_5_21 IOMUX_PAD(0x3F8, 0xCC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_D4__GPIO_5_22 IOMUX_PAD(0x3FC, 0xD0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_D5__GPIO_5_23 IOMUX_PAD(0x400, 0xD4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_D6__GPIO_5_24 IOMUX_PAD(0x404, 0xD8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_D7__GPIO_5_25 IOMUX_PAD(0x408, 0xDC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_D8__GPIO_5_26 IOMUX_PAD(0x40C, 0xE0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_D9__GPIO_5_27 IOMUX_PAD(0x410, 0xE4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_D10__GPIO_5_28 IOMUX_PAD(0x414, 0xE8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_D11__GPIO_5_29 IOMUX_PAD(0x418, 0xEC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_D12__GPIO_5_30 IOMUX_PAD(0x41C, 0xF0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_D13__GPIO_5_31 IOMUX_PAD(0x420, 0xF4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_D14__GPIO_6_0 IOMUX_PAD(0x424, 0xF8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_D15__GPIO_6_1 IOMUX_PAD(0x428, 0xFC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_D16__GPIO_6_2 IOMUX_PAD(0x42C, 0x100,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_D17__GPIO_6_3 IOMUX_PAD(0x430, 0x104,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_D18__GPIO_6_4 IOMUX_PAD(0x434, 0x108,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_D19__GPIO_6_5 IOMUX_PAD(0x438, 0x10C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NVCC_CSI0__NVCC_CSI0 IOMUX_PAD(0x43C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_JTAG_TMS__JTAG_TMS IOMUX_PAD(0x440, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_JTAG_MOD__JTAG_MOD IOMUX_PAD(0x444, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_JTAG_TRSTB__JTAG_TRSTB IOMUX_PAD(0x448, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_JTAG_TDI__JTAG_TDI IOMUX_PAD(0x44C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_JTAG_TCK__JTAG_TCK IOMUX_PAD(0x450, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_JTAG_TDO__JTAG_TDO IOMUX_PAD(0x454, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A25__GPIO_5_2 IOMUX_PAD(0x458, 0x110,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB2__GPIO_2_30 IOMUX_PAD(0x45C, 0x114,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D16__GPIO_3_16 IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D17__GPIO_3_17 IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D18__GPIO_3_18 IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D16__CSPI1_SCLK IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT4, 0x79c, 3, NO_PAD_CTRL) -#define MX53_PAD_EIM_D17__CSPI1_MISO IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT4, 0x7a0, 3, NO_PAD_CTRL) -#define MX53_PAD_EIM_D18__CSPI1_MOSI IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT4, 0x7a4, 3, NO_PAD_CTRL) -#define MX53_PAD_EIM_D19__GPIO_3_19 IOMUX_PAD(0x46C, 0x124,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D20__GPIO_3_20 IOMUX_PAD(0x470, 0x128,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D21__GPIO_3_21 IOMUX_PAD(0x474, 0x12C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D22__GPIO_3_22 IOMUX_PAD(0x478, 0x130,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D23__GPIO_3_23 IOMUX_PAD(0x47C, 0x134,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB3__GPIO_2_31 IOMUX_PAD(0x480, 0x138,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D24__GPIO_3_24 IOMUX_PAD(0x484, 0x13C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D25__GPIO_3_25 IOMUX_PAD(0x488, 0x140,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D26__GPIO_3_26 IOMUX_PAD(0x48C, 0x144,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D27__GPIO_3_27 IOMUX_PAD(0x490, 0x148,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D28__GPIO_3_28 IOMUX_PAD(0x494, 0x14C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D29__GPIO_3_29 IOMUX_PAD(0x498, 0x150,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D30__GPIO_3_30 IOMUX_PAD(0x49C, 0x154,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D31__GPIO_3_31 IOMUX_PAD(0x4A0, 0x158,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NVCC_EIM1__NVCC_EIM1 IOMUX_PAD(0x4A4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A24__GPIO_5_4 IOMUX_PAD(0x4A8, 0x15C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A23__GPIO_6_6 IOMUX_PAD(0x4AC, 0x160,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x4B0, 0x164,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A21__GPIO_2_17 IOMUX_PAD(0x4B4, 0x168,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A20__GPIO_2_18 IOMUX_PAD(0x4B8, 0x16C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A19__GPIO_2_19 IOMUX_PAD(0x4BC, 0x170,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A18__GPIO_2_20 IOMUX_PAD(0x4C0, 0x174,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A17__GPIO_2_21 IOMUX_PAD(0x4C4, 0x178,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A16__GPIO_2_22 IOMUX_PAD(0x4C8, 0x17C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS0__GPIO_2_23 IOMUX_PAD(0x4CC, 0x180,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS1__GPIO_2_24 IOMUX_PAD(0x4D0, 0x184,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_OE__GPIO_2_25 IOMUX_PAD(0x4D4, 0x188,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_RW__GPIO_2_26 IOMUX_PAD(0x4D8, 0x18C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_LBA__GPIO_2_27 IOMUX_PAD(0x4DC, 0x190,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NVCC_EIM4__NVCC_EIM4 IOMUX_PAD(0x4E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB0__GPIO_2_28 IOMUX_PAD(0x4E4, 0x194,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB1__GPIO_2_29 IOMUX_PAD(0x4E8, 0x198,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA0__GPIO_3_0 IOMUX_PAD(0x4EC, 0x19C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA1__GPIO_3_1 IOMUX_PAD(0x4F0, 0x1A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA2__GPIO_3_2 IOMUX_PAD(0x4F4, 0x1A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA3__GPIO_3_3 IOMUX_PAD(0x4F8, 0x1A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA4__GPIO_3_4 IOMUX_PAD(0x4FC, 0x1AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA5__GPIO_3_5 IOMUX_PAD(0x500, 0x1B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA6__GPIO_3_6 IOMUX_PAD(0x504, 0x1B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA7__GPIO_3_7 IOMUX_PAD(0x508, 0x1B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA8__GPIO_3_8 IOMUX_PAD(0x50C, 0x1BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA9__GPIO_3_9 IOMUX_PAD(0x510, 0x1C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA10__GPIO_3_10 IOMUX_PAD(0x514, 0x1C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA11__GPIO_3_11 IOMUX_PAD(0x518, 0x1C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA12__GPIO_3_12 IOMUX_PAD(0x51C, 0x1CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA13__GPIO_3_13 IOMUX_PAD(0x520, 0x1D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA14__GPIO_3_14 IOMUX_PAD(0x524, 0x1D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA15__GPIO_3_15 IOMUX_PAD(0x528, 0x1D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_WE_B__GPIO_6_12 IOMUX_PAD(0x52C, 0x1DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_RE_B__GPIO_6_13 IOMUX_PAD(0x530, 0x1E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_WAIT__GPIO_5_0 IOMUX_PAD(0x534, 0x1E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_BCLK__EIM_BCLK IOMUX_PAD(0x538, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NVCC_EIM7__NVCC_EIM7 IOMUX_PAD(0x53C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX3_P__GPIO_6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX2_P__GPIO_6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_CLK_P__GPIO_6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX1_P__GPIO_6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX0_P__GPIO_6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX3_P__GPIO_7_22 IOMUX_PAD(NON_PAD_I, 0x200, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_CLK_P__GPIO_7_24 IOMUX_PAD(NON_PAD_I, 0x204, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX2_P__GPIO_7_26 IOMUX_PAD(NON_PAD_I, 0x208, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX1_P__GPIO_7_28 IOMUX_PAD(NON_PAD_I, 0x20C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX0_P__GPIO_7_30 IOMUX_PAD(NON_PAD_I, 0x210, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_10__GPIO_4_0 IOMUX_PAD(0x540, 0x214, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_11__GPIO_4_1 IOMUX_PAD(0x544, 0x218, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_12__GPIO_4_2 IOMUX_PAD(0x548, 0x21C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_13__GPIO_4_3 IOMUX_PAD(0x54C, 0x220, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_14__GPIO_4_4 IOMUX_PAD(0x550, 0x224, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DRAM_DQM3__DRAM_DQM3 IOMUX_PAD(0x554, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DRAM_SDQS3__DRAM_SDQS3 IOMUX_PAD(0x558, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DRAM_SDCKE1__DRAM_SDCKE1 IOMUX_PAD(0x55C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DRAM_DQM2__DRAM_DQM2 IOMUX_PAD(0x560, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DRAM_SDODT1__DRAM_SDODT1 IOMUX_PAD(0x564, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DRAM_SDQS2__DRAM_SDQS2 IOMUX_PAD(0x568, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DRAM_RESET__DRAM_RESET IOMUX_PAD(0x56C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DRAM_SDCLK1__DRAM_SDCLK1 IOMUX_PAD(0x570, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DRAM_CAS__DRAM_CAS IOMUX_PAD(0x574, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DRAM_SDCLK0__DRAM_SDCLK0 IOMUX_PAD(0x578, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DRAM_SDQS0__DRAM_SDQS0 IOMUX_PAD(0x57C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DRAM_SDODT0__DRAM_SDODT0 IOMUX_PAD(0x580, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DRAM_DQM0__DRAM_DQM0 IOMUX_PAD(0x584, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DRAM_RAS__DRAM_RAS IOMUX_PAD(0x588, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DRAM_SDCKE0__DRAM_SDCKE0 IOMUX_PAD(0x58C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DRAM_SDQS1__DRAM_SDQS1 IOMUX_PAD(0x590, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_DRAM_DQM1__DRAM_DQM1 IOMUX_PAD(0x594, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x598, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x59C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CLE__GPIO_6_7 IOMUX_PAD(0x5A0, 0x228,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_ALE__GPIO_6_8 IOMUX_PAD(0x5A4, 0x22C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_WP_B__GPIO_6_9 IOMUX_PAD(0x5A8, 0x230,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_RB0__GPIO_6_10 IOMUX_PAD(0x5AC, 0x234,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS0__GPIO_6_11 IOMUX_PAD(0x5B0, 0x238,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS1__GPIO_6_14 IOMUX_PAD(0x5B4, 0x23C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS2__GPIO_6_15 IOMUX_PAD(0x5B8, 0x240,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS3__GPIO_6_16 IOMUX_PAD(0x5BC, 0x244,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NVCC_NANDF__NVCC_NANDF IOMUX_PAD(0x5C0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDIO__GPIO_1_22 IOMUX_PAD(0x5C4, 0x248,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_REF_CLK__GPIO_1_23 IOMUX_PAD(0x5C8, 0x24C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RX_ER__GPIO_1_24 IOMUX_PAD(0x5CC, 0x250,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_CRS_DV__GPIO_1_25 IOMUX_PAD(0x5D0, 0x254,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD1__GPIO_1_26 IOMUX_PAD(0x5D4, 0x258,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD0__GPIO_1_27 IOMUX_PAD(0x5D8, 0x25C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TX_EN__GPIO_1_28 IOMUX_PAD(0x5DC, 0x260,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD1__GPIO_1_29 IOMUX_PAD(0x5E0, 0x264,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD0__GPIO_1_30 IOMUX_PAD(0x5E4, 0x268,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDC__GPIO_1_31 IOMUX_PAD(0x5E8, 0x26C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NVCC_FEC__NVCC_FEC IOMUX_PAD(0x5EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DIOW__GPIO_6_17 IOMUX_PAD(0x5F0, 0x270,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DMACK__GPIO_6_18 IOMUX_PAD(0x5F4, 0x274,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DMARQ__GPIO_7_0 IOMUX_PAD(0x5F8, 0x278,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_BUFFER_EN__GPIO_7_1 IOMUX_PAD(0x5FC, 0x27C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_INTRQ__GPIO_7_2 IOMUX_PAD(0x600, 0x280,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DIOR__GPIO_7_3 IOMUX_PAD(0x604, 0x284,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_RESET_B__GPIO_7_4 IOMUX_PAD(0x608, 0x288,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_IORDY__GPIO_7_5 IOMUX_PAD(0x60C, 0x28C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DA_0__GPIO_7_6 IOMUX_PAD(0x610, 0x290,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DA_1__GPIO_7_7 IOMUX_PAD(0x614, 0x294,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DA_2__GPIO_7_8 IOMUX_PAD(0x618, 0x298,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_CS_0__GPIO_7_9 IOMUX_PAD(0x61C, 0x29C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_CS_1__GPIO_7_10 IOMUX_PAD(0x620, 0x2A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NVCC_ATA2__NVCC_ATA2 IOMUX_PAD(0x624, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DATA0__GPIO_2_0 IOMUX_PAD(0x628, 0x2A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DATA1__GPIO_2_1 IOMUX_PAD(0x62C, 0x2A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DATA2__GPIO_2_2 IOMUX_PAD(0x630, 0x2AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DATA3__GPIO_2_3 IOMUX_PAD(0x634, 0x2B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DATA4__GPIO_2_4 IOMUX_PAD(0x638, 0x2B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DATA5__GPIO_2_5 IOMUX_PAD(0x63C, 0x2B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DATA6__GPIO_2_6 IOMUX_PAD(0x640, 0x2BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DATA7__GPIO_2_7 IOMUX_PAD(0x644, 0x2C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DATA8__GPIO_2_8 IOMUX_PAD(0x648, 0x2C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DATA9__GPIO_2_9 IOMUX_PAD(0x64C, 0x2C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DATA10__GPIO_2_10 IOMUX_PAD(0x650, 0x2CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DATA11__GPIO_2_11 IOMUX_PAD(0x654, 0x2D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DATA12__GPIO_2_12 IOMUX_PAD(0x658, 0x2D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DATA13__GPIO_2_13 IOMUX_PAD(0x65C, 0x2D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DATA14__GPIO_2_14 IOMUX_PAD(0x660, 0x2DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_ATA_DATA15__GPIO_2_15 IOMUX_PAD(0x664, 0x2E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NVCC_ATA0__NVCC_ATA0 IOMUX_PAD(0x668, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA0__GPIO_1_16 IOMUX_PAD(0x66C, 0x2E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA1__GPIO_1_17 IOMUX_PAD(0x670, 0x2E8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_CMD__GPIO_1_18 IOMUX_PAD(0x674, 0x2EC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA2__GPIO_1_19 IOMUX_PAD(0x678, 0x2F0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_CLK__GPIO_1_20 IOMUX_PAD(0x67C, 0x2F4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA3__GPIO_1_21 IOMUX_PAD(0x680, 0x2F8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NVCC_SD1__NVCC_SD1 IOMUX_PAD(0x684, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_CLK__GPIO_1_10 IOMUX_PAD(0x688, 0x2FC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_CMD__GPIO_1_11 IOMUX_PAD(0x68C, 0x300,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA3__GPIO_1_12 IOMUX_PAD(0x690, 0x304,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA2__GPIO_1_13 IOMUX_PAD(0x694, 0x308,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA1__GPIO_1_14 IOMUX_PAD(0x698, 0x30C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA0__GPIO_1_15 IOMUX_PAD(0x69C, 0x310,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NVCC_SD2__NVCC_SD2 IOMUX_PAD(0x6A0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_0__GPIO_1_0 IOMUX_PAD(0x6A4, 0x314,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_1__GPIO_1_1 IOMUX_PAD(0x6A8, 0x318,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_9__GPIO_1_9 IOMUX_PAD(0x6AC, 0x31C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_3__GPIO_1_3 IOMUX_PAD(0x6B0, 0x320,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_6__GPIO_1_6 IOMUX_PAD(0x6B4, 0x324,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_2__GPIO_1_2 IOMUX_PAD(0x6B8, 0x328,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_4__GPIO_1_4 IOMUX_PAD(0x6BC, 0x32C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_5__GPIO_1_5 IOMUX_PAD(0x6C0, 0x330,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_7__GPIO_1_7 IOMUX_PAD(0x6C4, 0x334,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_8__GPIO_1_8 IOMUX_PAD(0x6C8, 0x338,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_16__GPIO_7_11 IOMUX_PAD(0x6CC, 0x33C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_17__GPIO_7_12 IOMUX_PAD(0x6D0, 0x340,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_18__GPIO_7_13 IOMUX_PAD(0x6D4, 0x344,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_NVCC_GPIO__NVCC_GPIO IOMUX_PAD(0x6D8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_POR_B__POR_B IOMUX_PAD(0x6DC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x6E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_RESET_IN_B__RESET_IN_B IOMUX_PAD(0x6E4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x6E8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_TEST_MODE__TEST_MODE IOMUX_PAD(0x6EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GRP_ADDDS__GRP_ADDDS IOMUX_PAD(0x6F0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GRP_DDRMODE_CTL__GRP_DDRMODE_CTL IOMUX_PAD(0x6F4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GRP_DDRPKE__GRP_DDRPKE IOMUX_PAD(0x6FC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GRP_DDRPK__GRP_DDRPK IOMUX_PAD(0x708, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GRP_TERM_CTL3__GRP_TERM_CTL3 IOMUX_PAD(0x70C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GRP_DDRHYS__GRP_DDRHYS IOMUX_PAD(0x710, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GRP_DDRMODE__GRP_DDRMODE IOMUX_PAD(0x714, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GRP_B0DS__GRP_B0DS IOMUX_PAD(0x718, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GRP_B1DS__GRP_B1DS IOMUX_PAD(0x71C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GRP_CTLDS__GRP_CTLDS IOMUX_PAD(0x720, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GRP_DDR_TYPE__GRP_DDR_TYPE IOMUX_PAD(0x724, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GRP_B2DS__GRP_B2DS IOMUX_PAD(0x728, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) -#define MX53_PAD_GRP_B3DS__GRP_B3DS IOMUX_PAD(0x72C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_19__KPP_COL_5 (_MX53_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_19__GPIO4_5 (_MX53_PAD_GPIO_19__GPIO4_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_19__CCM_CLKO (_MX53_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_19__SPDIF_OUT1 (_MX53_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 (_MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_19__ECSPI1_RDY (_MX53_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_19__FEC_TDATA_3 (_MX53_PAD_GPIO_19__FEC_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_19__SRC_INT_BOOT (_MX53_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL0__KPP_COL_0 (_MX53_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL0__GPIO4_6 (_MX53_PAD_KEY_COL0__GPIO4_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC (_MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL0__UART4_TXD_MUX (_MX53_PAD_KEY_COL0__UART4_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL0__ECSPI1_SCLK (_MX53_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL0__FEC_RDATA_3 (_MX53_PAD_KEY_COL0__FEC_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST (_MX53_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW0__KPP_ROW_0 (_MX53_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW0__GPIO4_7 (_MX53_PAD_KEY_ROW0__GPIO4_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD (_MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX (_MX53_PAD_KEY_ROW0__UART4_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI (_MX53_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW0__FEC_TX_ER (_MX53_PAD_KEY_ROW0__FEC_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL1__KPP_COL_1 (_MX53_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL1__GPIO4_8 (_MX53_PAD_KEY_COL1__GPIO4_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS (_MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL1__UART5_TXD_MUX (_MX53_PAD_KEY_COL1__UART5_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL1__ECSPI1_MISO (_MX53_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL1__FEC_RX_CLK (_MX53_PAD_KEY_COL1__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY (_MX53_PAD_KEY_COL1__USBPHY1_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW1__KPP_ROW_1 (_MX53_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW1__GPIO4_9 (_MX53_PAD_KEY_ROW1__GPIO4_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD (_MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX (_MX53_PAD_KEY_ROW1__UART5_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 (_MX53_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW1__FEC_COL (_MX53_PAD_KEY_ROW1__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID (_MX53_PAD_KEY_ROW1__USBPHY1_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL2__KPP_COL_2 (_MX53_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL2__GPIO4_10 (_MX53_PAD_KEY_COL2__GPIO4_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL2__CAN1_TXCAN (_MX53_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL2__FEC_MDIO (_MX53_PAD_KEY_COL2__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL2__ECSPI1_SS1 (_MX53_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL2__FEC_RDATA_2 (_MX53_PAD_KEY_COL2__FEC_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE (_MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW2__KPP_ROW_2 (_MX53_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW2__GPIO4_11 (_MX53_PAD_KEY_ROW2__GPIO4_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW2__CAN1_RXCAN (_MX53_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW2__FEC_MDC (_MX53_PAD_KEY_ROW2__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 (_MX53_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 (_MX53_PAD_KEY_ROW2__FEC_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR (_MX53_PAD_KEY_ROW2__USBPHY1_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL3__KPP_COL_3 (_MX53_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL3__GPIO4_12 (_MX53_PAD_KEY_COL3__GPIO4_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL3__USBOH3_H2_DP (_MX53_PAD_KEY_COL3__USBOH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL3__SPDIF_IN1 (_MX53_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL3__I2C2_SCL (_MX53_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL3__ECSPI1_SS3 (_MX53_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL3__FEC_CRS (_MX53_PAD_KEY_COL3__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK (_MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW3__KPP_ROW_3 (_MX53_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW3__GPIO4_13 (_MX53_PAD_KEY_ROW3__GPIO4_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM (_MX53_PAD_KEY_ROW3__USBOH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK (_MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW3__I2C2_SDA (_MX53_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT (_MX53_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP (_MX53_PAD_KEY_ROW3__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 (_MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL4__KPP_COL_4 (_MX53_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL4__GPIO4_14 (_MX53_PAD_KEY_COL4__GPIO4_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL4__CAN2_TXCAN (_MX53_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL4__IPU_SISG_4 (_MX53_PAD_KEY_COL4__IPU_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL4__UART5_RTS (_MX53_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC (_MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 (_MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW4__KPP_ROW_4 (_MX53_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW4__GPIO4_15 (_MX53_PAD_KEY_ROW4__GPIO4_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW4__CAN2_RXCAN (_MX53_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW4__IPU_SISG_5 (_MX53_PAD_KEY_ROW4__IPU_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW4__UART5_CTS (_MX53_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR (_MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID (_MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK (_MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 (_MX53_PAD_DI0_DISP_CLK__GPIO4_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR (_MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 (_MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 (_MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID (_MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 (_MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN15__GPIO4_17 (_MX53_PAD_DI0_PIN15__GPIO4_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC (_MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 (_MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 (_MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID (_MX53_PAD_DI0_PIN15__USBPHY1_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 (_MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN2__GPIO4_18 (_MX53_PAD_DI0_PIN2__GPIO4_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD (_MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 (_MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 (_MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION (_MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 (_MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN3__GPIO4_19 (_MX53_PAD_DI0_PIN3__GPIO4_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS (_MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 (_MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 (_MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG (_MX53_PAD_DI0_PIN3__USBPHY1_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 (_MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN4__GPIO4_20 (_MX53_PAD_DI0_PIN4__GPIO4_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD (_MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN4__ESDHC1_WP (_MX53_PAD_DI0_PIN4__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD (_MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 (_MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT (_MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 (_MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT0__GPIO4_21 (_MX53_PAD_DISP0_DAT0__GPIO4_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT0__CSPI_SCLK (_MX53_PAD_DISP0_DAT0__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 (_MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN (_MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 (_MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY (_MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 (_MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT1__GPIO4_22 (_MX53_PAD_DISP0_DAT1__GPIO4_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT1__CSPI_MOSI (_MX53_PAD_DISP0_DAT1__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 (_MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL (_MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 (_MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID (_MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 (_MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT2__GPIO4_23 (_MX53_PAD_DISP0_DAT2__GPIO4_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT2__CSPI_MISO (_MX53_PAD_DISP0_DAT2__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 (_MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE (_MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 (_MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE (_MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 (_MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT3__GPIO4_24 (_MX53_PAD_DISP0_DAT3__GPIO4_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT3__CSPI_SS0 (_MX53_PAD_DISP0_DAT3__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 (_MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR (_MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 (_MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR (_MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 (_MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT4__GPIO4_25 (_MX53_PAD_DISP0_DAT4__GPIO4_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT4__CSPI_SS1 (_MX53_PAD_DISP0_DAT4__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 (_MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB (_MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 (_MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK (_MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 (_MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT5__GPIO4_26 (_MX53_PAD_DISP0_DAT5__GPIO4_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT5__CSPI_SS2 (_MX53_PAD_DISP0_DAT5__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 (_MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS (_MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 (_MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 (_MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 (_MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT6__GPIO4_27 (_MX53_PAD_DISP0_DAT6__GPIO4_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT6__CSPI_SS3 (_MX53_PAD_DISP0_DAT6__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 (_MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE (_MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 (_MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 (_MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 (_MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT7__GPIO4_28 (_MX53_PAD_DISP0_DAT7__GPIO4_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT7__CSPI_RDY (_MX53_PAD_DISP0_DAT7__CSPI_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 (_MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 (_MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 (_MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID (_MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 (_MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT8__GPIO4_29 (_MX53_PAD_DISP0_DAT8__GPIO4_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT8__PWM1_PWMO (_MX53_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B (_MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 (_MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 (_MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID (_MX53_PAD_DISP0_DAT8__USBPHY2_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 (_MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT9__GPIO4_30 (_MX53_PAD_DISP0_DAT9__GPIO4_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT9__PWM2_PWMO (_MX53_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B (_MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 (_MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 (_MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 (_MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 (_MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT10__GPIO4_31 (_MX53_PAD_DISP0_DAT10__GPIO4_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP (_MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 (_MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 (_MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 (_MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 (_MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT11__GPIO5_5 (_MX53_PAD_DISP0_DAT11__GPIO5_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT (_MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 (_MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 (_MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 (_MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 (_MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT12__GPIO5_6 (_MX53_PAD_DISP0_DAT12__GPIO5_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK (_MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 (_MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 (_MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 (_MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 (_MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT13__GPIO5_7 (_MX53_PAD_DISP0_DAT13__GPIO5_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS (_MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 (_MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 (_MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 (_MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 (_MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT14__GPIO5_8 (_MX53_PAD_DISP0_DAT14__GPIO5_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC (_MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 (_MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 (_MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 (_MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 (_MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT15__GPIO5_9 (_MX53_PAD_DISP0_DAT15__GPIO5_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 (_MX53_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 (_MX53_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 (_MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 (_MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 (_MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 (_MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT16__GPIO5_10 (_MX53_PAD_DISP0_DAT16__GPIO5_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI (_MX53_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC (_MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 (_MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 (_MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 (_MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 (_MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 (_MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT17__GPIO5_11 (_MX53_PAD_DISP0_DAT17__GPIO5_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO (_MX53_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD (_MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 (_MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 (_MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 (_MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 (_MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT18__GPIO5_12 (_MX53_PAD_DISP0_DAT18__GPIO5_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 (_MX53_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 (_MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 (_MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 (_MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 (_MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT19__GPIO5_13 (_MX53_PAD_DISP0_DAT19__GPIO5_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK (_MX53_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 (_MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 (_MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 (_MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 (_MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT20__GPIO5_14 (_MX53_PAD_DISP0_DAT20__GPIO5_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK (_MX53_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC (_MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 (_MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 (_MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI (_MX53_PAD_DISP0_DAT20__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 (_MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT21__GPIO5_15 (_MX53_PAD_DISP0_DAT21__GPIO5_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI (_MX53_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD (_MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 (_MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 (_MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO (_MX53_PAD_DISP0_DAT21__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 (_MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT22__GPIO5_16 (_MX53_PAD_DISP0_DAT22__GPIO5_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO (_MX53_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS (_MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 (_MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 (_MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK (_MX53_PAD_DISP0_DAT22__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 (_MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT23__GPIO5_17 (_MX53_PAD_DISP0_DAT23__GPIO5_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 (_MX53_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD (_MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 (_MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 (_MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS (_MX53_PAD_DISP0_DAT23__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK (_MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 (_MX53_PAD_CSI0_PIXCLK__GPIO5_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 (_MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 (_MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC (_MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_MCLK__GPIO5_19 (_MX53_PAD_CSI0_MCLK__GPIO5_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK (_MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 (_MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 (_MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL (_MX53_PAD_CSI0_MCLK__TPIU_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN (_MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 (_MX53_PAD_CSI0_DATA_EN__GPIO5_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 (_MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 (_MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK (_MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC (_MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_VSYNC__GPIO5_21 (_MX53_PAD_CSI0_VSYNC__GPIO5_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 (_MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 (_MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 (_MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 (_MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT4__GPIO5_22 (_MX53_PAD_CSI0_DAT4__GPIO5_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT4__KPP_COL_5 (_MX53_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK (_MX53_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP (_MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC (_MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 (_MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 (_MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 (_MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT5__GPIO5_23 (_MX53_PAD_CSI0_DAT5__GPIO5_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 (_MX53_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI (_MX53_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT (_MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD (_MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 (_MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 (_MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 (_MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT6__GPIO5_24 (_MX53_PAD_CSI0_DAT6__GPIO5_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT6__KPP_COL_6 (_MX53_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO (_MX53_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK (_MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS (_MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 (_MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 (_MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 (_MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT7__GPIO5_25 (_MX53_PAD_CSI0_DAT7__GPIO5_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 (_MX53_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 (_MX53_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR (_MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD (_MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 (_MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 (_MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 (_MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT8__GPIO5_26 (_MX53_PAD_CSI0_DAT8__GPIO5_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT8__KPP_COL_7 (_MX53_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK (_MX53_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC (_MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT8__I2C1_SDA (_MX53_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 (_MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 (_MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 (_MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT9__GPIO5_27 (_MX53_PAD_CSI0_DAT9__GPIO5_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 (_MX53_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI (_MX53_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR (_MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT9__I2C1_SCL (_MX53_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 (_MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 (_MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 (_MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT10__GPIO5_28 (_MX53_PAD_CSI0_DAT10__GPIO5_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX (_MX53_PAD_CSI0_DAT10__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO (_MX53_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC (_MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 (_MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 (_MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 (_MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 (_MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT11__GPIO5_29 (_MX53_PAD_CSI0_DAT11__GPIO5_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX (_MX53_PAD_CSI0_DAT11__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 (_MX53_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS (_MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 (_MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 (_MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 (_MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 (_MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT12__GPIO5_30 (_MX53_PAD_CSI0_DAT12__GPIO5_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX (_MX53_PAD_CSI0_DAT12__UART4_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 (_MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 (_MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 (_MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 (_MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 (_MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT13__GPIO5_31 (_MX53_PAD_CSI0_DAT13__GPIO5_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX (_MX53_PAD_CSI0_DAT13__UART4_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 (_MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 (_MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 (_MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 (_MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 (_MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT14__GPIO6_0 (_MX53_PAD_CSI0_DAT14__GPIO6_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX (_MX53_PAD_CSI0_DAT14__UART5_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 (_MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 (_MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 (_MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 (_MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 (_MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT15__GPIO6_1 (_MX53_PAD_CSI0_DAT15__GPIO6_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX (_MX53_PAD_CSI0_DAT15__UART5_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 (_MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 (_MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 (_MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 (_MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 (_MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT16__GPIO6_2 (_MX53_PAD_CSI0_DAT16__GPIO6_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT16__UART4_RTS (_MX53_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 (_MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 (_MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 (_MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 (_MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 (_MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT17__GPIO6_3 (_MX53_PAD_CSI0_DAT17__GPIO6_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT17__UART4_CTS (_MX53_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 (_MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 (_MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 (_MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 (_MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 (_MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT18__GPIO6_4 (_MX53_PAD_CSI0_DAT18__GPIO6_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT18__UART5_RTS (_MX53_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 (_MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 (_MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 (_MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 (_MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 (_MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT19__GPIO6_5 (_MX53_PAD_CSI0_DAT19__GPIO6_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT19__UART5_CTS (_MX53_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 (_MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 (_MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 (_MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK (_MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 (_MX53_PAD_EIM_A25__EMI_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A25__GPIO5_2 (_MX53_PAD_EIM_A25__GPIO5_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A25__ECSPI2_RDY (_MX53_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 (_MX53_PAD_EIM_A25__IPU_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A25__CSPI_SS1 (_MX53_PAD_EIM_A25__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS (_MX53_PAD_EIM_A25__IPU_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A25__USBPHY1_BISTOK (_MX53_PAD_EIM_A25__USBPHY1_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 (_MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB2__GPIO2_30 (_MX53_PAD_EIM_EB2__GPIO2_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK (_MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS (_MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB2__ECSPI1_SS0 (_MX53_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB2__I2C2_SCL (_MX53_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 (_MX53_PAD_EIM_D16__EMI_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D16__GPIO3_16 (_MX53_PAD_EIM_D16__GPIO3_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 (_MX53_PAD_EIM_D16__IPU_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK (_MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D16__ECSPI1_SCLK (_MX53_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D16__I2C2_SDA (_MX53_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 (_MX53_PAD_EIM_D17__EMI_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D17__GPIO3_17 (_MX53_PAD_EIM_D17__GPIO3_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 (_MX53_PAD_EIM_D17__IPU_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN (_MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D17__ECSPI1_MISO (_MX53_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D17__I2C3_SCL (_MX53_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 (_MX53_PAD_EIM_D18__EMI_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D18__GPIO3_18 (_MX53_PAD_EIM_D18__GPIO3_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 (_MX53_PAD_EIM_D18__IPU_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO (_MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D18__ECSPI1_MOSI (_MX53_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D18__I2C3_SDA (_MX53_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS (_MX53_PAD_EIM_D18__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 (_MX53_PAD_EIM_D19__EMI_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D19__GPIO3_19 (_MX53_PAD_EIM_D19__GPIO3_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 (_MX53_PAD_EIM_D19__IPU_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS (_MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D19__ECSPI1_SS1 (_MX53_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D19__EPIT1_EPITO (_MX53_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D19__UART1_CTS (_MX53_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC (_MX53_PAD_EIM_D19__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 (_MX53_PAD_EIM_D20__EMI_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D20__GPIO3_20 (_MX53_PAD_EIM_D20__GPIO3_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 (_MX53_PAD_EIM_D20__IPU_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS (_MX53_PAD_EIM_D20__IPU_SER_DISP0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D20__CSPI_SS0 (_MX53_PAD_EIM_D20__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D20__EPIT2_EPITO (_MX53_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D20__UART1_RTS (_MX53_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR (_MX53_PAD_EIM_D20__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 (_MX53_PAD_EIM_D21__EMI_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D21__GPIO3_21 (_MX53_PAD_EIM_D21__GPIO3_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 (_MX53_PAD_EIM_D21__IPU_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK (_MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D21__CSPI_SCLK (_MX53_PAD_EIM_D21__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D21__I2C1_SCL (_MX53_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC (_MX53_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 (_MX53_PAD_EIM_D22__EMI_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D22__GPIO3_22 (_MX53_PAD_EIM_D22__GPIO3_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 (_MX53_PAD_EIM_D22__IPU_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN (_MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D22__CSPI_MISO (_MX53_PAD_EIM_D22__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR (_MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 (_MX53_PAD_EIM_D23__EMI_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D23__GPIO3_23 (_MX53_PAD_EIM_D23__GPIO3_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D23__UART3_CTS (_MX53_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D23__UART1_DCD (_MX53_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS (_MX53_PAD_EIM_D23__IPU_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 (_MX53_PAD_EIM_D23__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN (_MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 (_MX53_PAD_EIM_D23__IPU_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 (_MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB3__GPIO2_31 (_MX53_PAD_EIM_EB3__GPIO2_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB3__UART3_RTS (_MX53_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB3__UART1_RI (_MX53_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 (_MX53_PAD_EIM_EB3__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC (_MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 (_MX53_PAD_EIM_EB3__IPU_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 (_MX53_PAD_EIM_D24__EMI_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D24__GPIO3_24 (_MX53_PAD_EIM_D24__GPIO3_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D24__UART3_TXD_MUX (_MX53_PAD_EIM_D24__UART3_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D24__ECSPI1_SS2 (_MX53_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D24__CSPI_SS2 (_MX53_PAD_EIM_D24__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS (_MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D24__ECSPI2_SS2 (_MX53_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D24__UART1_DTR (_MX53_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 (_MX53_PAD_EIM_D25__EMI_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D25__GPIO3_25 (_MX53_PAD_EIM_D25__GPIO3_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D25__UART3_RXD_MUX (_MX53_PAD_EIM_D25__UART3_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D25__ECSPI1_SS3 (_MX53_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D25__CSPI_SS3 (_MX53_PAD_EIM_D25__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC (_MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D25__ECSPI2_SS3 (_MX53_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D25__UART1_DSR (_MX53_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 (_MX53_PAD_EIM_D26__EMI_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D26__GPIO3_26 (_MX53_PAD_EIM_D26__GPIO3_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D26__UART2_TXD_MUX (_MX53_PAD_EIM_D26__UART2_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D26__FIRI_RXD (_MX53_PAD_EIM_D26__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 (_MX53_PAD_EIM_D26__IPU_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 (_MX53_PAD_EIM_D26__IPU_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D26__IPU_SISG_2 (_MX53_PAD_EIM_D26__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 (_MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 (_MX53_PAD_EIM_D27__EMI_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D27__GPIO3_27 (_MX53_PAD_EIM_D27__GPIO3_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D27__UART2_RXD_MUX (_MX53_PAD_EIM_D27__UART2_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D27__FIRI_TXD (_MX53_PAD_EIM_D27__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 (_MX53_PAD_EIM_D27__IPU_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 (_MX53_PAD_EIM_D27__IPU_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D27__IPU_SISG_3 (_MX53_PAD_EIM_D27__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 (_MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 (_MX53_PAD_EIM_D28__EMI_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D28__GPIO3_28 (_MX53_PAD_EIM_D28__GPIO3_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D28__UART2_CTS (_MX53_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO (_MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D28__CSPI_MOSI (_MX53_PAD_EIM_D28__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D28__I2C1_SDA (_MX53_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D28__IPU_EXT_TRIG (_MX53_PAD_EIM_D28__IPU_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 (_MX53_PAD_EIM_D28__IPU_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 (_MX53_PAD_EIM_D29__EMI_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D29__GPIO3_29 (_MX53_PAD_EIM_D29__GPIO3_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D29__UART2_RTS (_MX53_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS (_MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D29__CSPI_SS0 (_MX53_PAD_EIM_D29__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 (_MX53_PAD_EIM_D29__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC (_MX53_PAD_EIM_D29__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 (_MX53_PAD_EIM_D29__IPU_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 (_MX53_PAD_EIM_D30__EMI_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D30__GPIO3_30 (_MX53_PAD_EIM_D30__GPIO3_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D30__UART3_CTS (_MX53_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 (_MX53_PAD_EIM_D30__IPU_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 (_MX53_PAD_EIM_D30__IPU_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 (_MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC (_MX53_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC (_MX53_PAD_EIM_D30__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 (_MX53_PAD_EIM_D31__EMI_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D31__GPIO3_31 (_MX53_PAD_EIM_D31__GPIO3_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D31__UART3_RTS (_MX53_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 (_MX53_PAD_EIM_D31__IPU_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 (_MX53_PAD_EIM_D31__IPU_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 (_MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR (_MX53_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR (_MX53_PAD_EIM_D31__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 (_MX53_PAD_EIM_A24__EMI_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A24__GPIO5_4 (_MX53_PAD_EIM_A24__GPIO5_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 (_MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 (_MX53_PAD_EIM_A24__IPU_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A24__IPU_SISG_2 (_MX53_PAD_EIM_A24__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A24__USBPHY2_BVALID (_MX53_PAD_EIM_A24__USBPHY2_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 (_MX53_PAD_EIM_A23__EMI_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A23__GPIO6_6 (_MX53_PAD_EIM_A23__GPIO6_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 (_MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 (_MX53_PAD_EIM_A23__IPU_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A23__IPU_SISG_3 (_MX53_PAD_EIM_A23__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION (_MX53_PAD_EIM_A23__USBPHY2_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 (_MX53_PAD_EIM_A22__EMI_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A22__GPIO2_16 (_MX53_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 (_MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 (_MX53_PAD_EIM_A22__IPU_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 (_MX53_PAD_EIM_A22__SRC_BT_CFG1_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 (_MX53_PAD_EIM_A21__EMI_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A21__GPIO2_17 (_MX53_PAD_EIM_A21__GPIO2_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 (_MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 (_MX53_PAD_EIM_A21__IPU_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 (_MX53_PAD_EIM_A21__SRC_BT_CFG1_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 (_MX53_PAD_EIM_A20__EMI_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A20__GPIO2_18 (_MX53_PAD_EIM_A20__GPIO2_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 (_MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 (_MX53_PAD_EIM_A20__IPU_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 (_MX53_PAD_EIM_A20__SRC_BT_CFG1_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 (_MX53_PAD_EIM_A19__EMI_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A19__GPIO2_19 (_MX53_PAD_EIM_A19__GPIO2_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 (_MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 (_MX53_PAD_EIM_A19__IPU_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 (_MX53_PAD_EIM_A19__SRC_BT_CFG1_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 (_MX53_PAD_EIM_A18__EMI_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A18__GPIO2_20 (_MX53_PAD_EIM_A18__GPIO2_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 (_MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 (_MX53_PAD_EIM_A18__IPU_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 (_MX53_PAD_EIM_A18__SRC_BT_CFG1_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 (_MX53_PAD_EIM_A17__EMI_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A17__GPIO2_21 (_MX53_PAD_EIM_A17__GPIO2_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 (_MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 (_MX53_PAD_EIM_A17__IPU_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 (_MX53_PAD_EIM_A17__SRC_BT_CFG1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 (_MX53_PAD_EIM_A16__EMI_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A16__GPIO2_22 (_MX53_PAD_EIM_A16__GPIO2_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK (_MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK (_MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 (_MX53_PAD_EIM_A16__SRC_BT_CFG1_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 (_MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_CS0__GPIO2_23 (_MX53_PAD_EIM_CS0__GPIO2_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_CS0__ECSPI2_SCLK (_MX53_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 (_MX53_PAD_EIM_CS0__IPU_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 (_MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_CS1__GPIO2_24 (_MX53_PAD_EIM_CS1__GPIO2_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_CS1__ECSPI2_MOSI (_MX53_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 (_MX53_PAD_EIM_CS1__IPU_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_OE__EMI_WEIM_OE (_MX53_PAD_EIM_OE__EMI_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_OE__GPIO2_25 (_MX53_PAD_EIM_OE__GPIO2_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_OE__ECSPI2_MISO (_MX53_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 (_MX53_PAD_EIM_OE__IPU_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_OE__USBPHY2_IDDIG (_MX53_PAD_EIM_OE__USBPHY2_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_RW__EMI_WEIM_RW (_MX53_PAD_EIM_RW__EMI_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_RW__GPIO2_26 (_MX53_PAD_EIM_RW__GPIO2_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_RW__ECSPI2_SS0 (_MX53_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 (_MX53_PAD_EIM_RW__IPU_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT (_MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA (_MX53_PAD_EIM_LBA__EMI_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_LBA__GPIO2_27 (_MX53_PAD_EIM_LBA__GPIO2_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_LBA__ECSPI2_SS1 (_MX53_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 (_MX53_PAD_EIM_LBA__IPU_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 (_MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 (_MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB0__GPIO2_28 (_MX53_PAD_EIM_EB0__GPIO2_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 (_MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 (_MX53_PAD_EIM_EB0__IPU_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY (_MX53_PAD_EIM_EB0__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 (_MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 (_MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB1__GPIO2_29 (_MX53_PAD_EIM_EB1__GPIO2_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 (_MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 (_MX53_PAD_EIM_EB1__IPU_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 (_MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 (_MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA0__GPIO3_0 (_MX53_PAD_EIM_DA0__GPIO3_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 (_MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 (_MX53_PAD_EIM_DA0__IPU_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 (_MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 (_MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA1__GPIO3_1 (_MX53_PAD_EIM_DA1__GPIO3_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 (_MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 (_MX53_PAD_EIM_DA1__IPU_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 (_MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 (_MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA2__GPIO3_2 (_MX53_PAD_EIM_DA2__GPIO3_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 (_MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 (_MX53_PAD_EIM_DA2__IPU_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 (_MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 (_MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA3__GPIO3_3 (_MX53_PAD_EIM_DA3__GPIO3_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 (_MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 (_MX53_PAD_EIM_DA3__IPU_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 (_MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 (_MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA4__GPIO3_4 (_MX53_PAD_EIM_DA4__GPIO3_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 (_MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 (_MX53_PAD_EIM_DA4__IPU_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 (_MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 (_MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA5__GPIO3_5 (_MX53_PAD_EIM_DA5__GPIO3_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 (_MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 (_MX53_PAD_EIM_DA5__IPU_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 (_MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 (_MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA6__GPIO3_6 (_MX53_PAD_EIM_DA6__GPIO3_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 (_MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 (_MX53_PAD_EIM_DA6__IPU_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 (_MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 (_MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA7__GPIO3_7 (_MX53_PAD_EIM_DA7__GPIO3_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 (_MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 (_MX53_PAD_EIM_DA7__IPU_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 (_MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 (_MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA8__GPIO3_8 (_MX53_PAD_EIM_DA8__GPIO3_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 (_MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 (_MX53_PAD_EIM_DA8__IPU_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 (_MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 (_MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA9__GPIO3_9 (_MX53_PAD_EIM_DA9__GPIO3_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 (_MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 (_MX53_PAD_EIM_DA9__IPU_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 (_MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 (_MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA10__GPIO3_10 (_MX53_PAD_EIM_DA10__GPIO3_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 (_MX53_PAD_EIM_DA10__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN (_MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 (_MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 (_MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA11__GPIO3_11 (_MX53_PAD_EIM_DA11__GPIO3_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 (_MX53_PAD_EIM_DA11__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC (_MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 (_MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA12__GPIO3_12 (_MX53_PAD_EIM_DA12__GPIO3_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 (_MX53_PAD_EIM_DA12__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC (_MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 (_MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA13__GPIO3_13 (_MX53_PAD_EIM_DA13__GPIO3_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS (_MX53_PAD_EIM_DA13__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK (_MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 (_MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA14__GPIO3_14 (_MX53_PAD_EIM_DA14__GPIO3_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS (_MX53_PAD_EIM_DA14__IPU_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK (_MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 (_MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA15__GPIO3_15 (_MX53_PAD_EIM_DA15__GPIO3_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 (_MX53_PAD_EIM_DA15__IPU_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 (_MX53_PAD_EIM_DA15__IPU_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B (_MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_WE_B__GPIO6_12 (_MX53_PAD_NANDF_WE_B__GPIO6_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B (_MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_RE_B__GPIO6_13 (_MX53_PAD_NANDF_RE_B__GPIO6_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT (_MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_WAIT__GPIO5_0 (_MX53_PAD_EIM_WAIT__GPIO5_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B (_MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 (_MX53_PAD_LVDS1_TX3_P__GPIO6_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 (_MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 (_MX53_PAD_LVDS1_TX2_P__GPIO6_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 (_MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 (_MX53_PAD_LVDS1_CLK_P__GPIO6_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK (_MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 (_MX53_PAD_LVDS1_TX1_P__GPIO6_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 (_MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 (_MX53_PAD_LVDS1_TX0_P__GPIO6_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 (_MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 (_MX53_PAD_LVDS0_TX3_P__GPIO7_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 (_MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 (_MX53_PAD_LVDS0_CLK_P__GPIO7_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK (_MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 (_MX53_PAD_LVDS0_TX2_P__GPIO7_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 (_MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 (_MX53_PAD_LVDS0_TX1_P__GPIO7_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 (_MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 (_MX53_PAD_LVDS0_TX0_P__GPIO7_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 (_MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_10__GPIO4_0 (_MX53_PAD_GPIO_10__GPIO4_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_10__OSC32k_32K_OUT (_MX53_PAD_GPIO_10__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_11__GPIO4_1 (_MX53_PAD_GPIO_11__GPIO4_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_12__GPIO4_2 (_MX53_PAD_GPIO_12__GPIO4_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_13__GPIO4_3 (_MX53_PAD_GPIO_13__GPIO4_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_14__GPIO4_4 (_MX53_PAD_GPIO_14__GPIO4_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE (_MX53_PAD_NANDF_CLE__EMI_NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CLE__GPIO6_7 (_MX53_PAD_NANDF_CLE__GPIO6_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 (_MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE (_MX53_PAD_NANDF_ALE__EMI_NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_ALE__GPIO6_8 (_MX53_PAD_NANDF_ALE__GPIO6_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 (_MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B (_MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_WP_B__GPIO6_9 (_MX53_PAD_NANDF_WP_B__GPIO6_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 (_MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 (_MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_RB0__GPIO6_10 (_MX53_PAD_NANDF_RB0__GPIO6_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 (_MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 (_MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS0__GPIO6_11 (_MX53_PAD_NANDF_CS0__GPIO6_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 (_MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 (_MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS1__GPIO6_14 (_MX53_PAD_NANDF_CS1__GPIO6_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS1__MLB_MLBCLK (_MX53_PAD_NANDF_CS1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 (_MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 (_MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS2__GPIO6_15 (_MX53_PAD_NANDF_CS2__GPIO6_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS2__IPU_SISG_0 (_MX53_PAD_NANDF_CS2__IPU_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS2__ESAI1_TX0 (_MX53_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE (_MX53_PAD_NANDF_CS2__EMI_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK (_MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS2__MLB_MLBSIG (_MX53_PAD_NANDF_CS2__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 (_MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 (_MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS3__GPIO6_16 (_MX53_PAD_NANDF_CS3__GPIO6_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS3__IPU_SISG_1 (_MX53_PAD_NANDF_CS3__IPU_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS3__ESAI1_TX1 (_MX53_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 (_MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS3__MLB_MLBDAT (_MX53_PAD_NANDF_CS3__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 (_MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDIO__FEC_MDIO (_MX53_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDIO__GPIO1_22 (_MX53_PAD_FEC_MDIO__GPIO1_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDIO__ESAI1_SCKR (_MX53_PAD_FEC_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDIO__FEC_COL (_MX53_PAD_FEC_MDIO__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 (_MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 (_MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 (_MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK (_MX53_PAD_FEC_REF_CLK__FEC_TX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_REF_CLK__GPIO1_23 (_MX53_PAD_FEC_REF_CLK__GPIO1_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR (_MX53_PAD_FEC_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 (_MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 (_MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RX_ER__FEC_RX_ER (_MX53_PAD_FEC_RX_ER__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RX_ER__GPIO1_24 (_MX53_PAD_FEC_RX_ER__GPIO1_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR (_MX53_PAD_FEC_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK (_MX53_PAD_FEC_RX_ER__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 (_MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV (_MX53_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_CRS_DV__GPIO1_25 (_MX53_PAD_FEC_CRS_DV__GPIO1_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT (_MX53_PAD_FEC_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 (_MX53_PAD_FEC_RXD1__FEC_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD1__GPIO1_26 (_MX53_PAD_FEC_RXD1__GPIO1_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD1__ESAI1_FST (_MX53_PAD_FEC_RXD1__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD1__MLB_MLBSIG (_MX53_PAD_FEC_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 (_MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 (_MX53_PAD_FEC_RXD0__FEC_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD0__GPIO1_27 (_MX53_PAD_FEC_RXD0__GPIO1_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD0__ESAI1_HCKT (_MX53_PAD_FEC_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT (_MX53_PAD_FEC_RXD0__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TX_EN__FEC_TX_EN (_MX53_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TX_EN__GPIO1_28 (_MX53_PAD_FEC_TX_EN__GPIO1_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 (_MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 (_MX53_PAD_FEC_TXD1__FEC_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD1__GPIO1_29 (_MX53_PAD_FEC_TXD1__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 (_MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD1__MLB_MLBCLK (_MX53_PAD_FEC_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK (_MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 (_MX53_PAD_FEC_TXD0__FEC_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD0__GPIO1_30 (_MX53_PAD_FEC_TXD0__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 (_MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 (_MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDC__FEC_MDC (_MX53_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDC__GPIO1_31 (_MX53_PAD_FEC_MDC__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 (_MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDC__MLB_MLBDAT (_MX53_PAD_FEC_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG (_MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 (_MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DIOW__PATA_DIOW (_MX53_PAD_PATA_DIOW__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DIOW__GPIO6_17 (_MX53_PAD_PATA_DIOW__GPIO6_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX (_MX53_PAD_PATA_DIOW__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 (_MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DMACK__PATA_DMACK (_MX53_PAD_PATA_DMACK__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DMACK__GPIO6_18 (_MX53_PAD_PATA_DMACK__GPIO6_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX (_MX53_PAD_PATA_DMACK__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 (_MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DMARQ__PATA_DMARQ (_MX53_PAD_PATA_DMARQ__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DMARQ__GPIO7_0 (_MX53_PAD_PATA_DMARQ__GPIO7_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX (_MX53_PAD_PATA_DMARQ__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 (_MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 (_MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN (_MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 (_MX53_PAD_PATA_BUFFER_EN__GPIO7_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX (_MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 (_MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 (_MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_INTRQ__PATA_INTRQ (_MX53_PAD_PATA_INTRQ__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_INTRQ__GPIO7_2 (_MX53_PAD_PATA_INTRQ__GPIO7_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_INTRQ__UART2_CTS (_MX53_PAD_PATA_INTRQ__UART2_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN (_MX53_PAD_PATA_INTRQ__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 (_MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 (_MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DIOR__PATA_DIOR (_MX53_PAD_PATA_DIOR__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DIOR__GPIO7_3 (_MX53_PAD_PATA_DIOR__GPIO7_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DIOR__UART2_RTS (_MX53_PAD_PATA_DIOR__UART2_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_DIOR__CAN1_RXCAN (_MX53_PAD_PATA_DIOR__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 (_MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B (_MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_RESET_B__GPIO7_4 (_MX53_PAD_PATA_RESET_B__GPIO7_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD (_MX53_PAD_PATA_RESET_B__ESDHC3_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_RESET_B__UART1_CTS (_MX53_PAD_PATA_RESET_B__UART1_CTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN (_MX53_PAD_PATA_RESET_B__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 (_MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_IORDY__PATA_IORDY (_MX53_PAD_PATA_IORDY__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_IORDY__GPIO7_5 (_MX53_PAD_PATA_IORDY__GPIO7_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_IORDY__ESDHC3_CLK (_MX53_PAD_PATA_IORDY__ESDHC3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_IORDY__UART1_RTS (_MX53_PAD_PATA_IORDY__UART1_RTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_IORDY__CAN2_RXCAN (_MX53_PAD_PATA_IORDY__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 (_MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_0__PATA_DA_0 (_MX53_PAD_PATA_DA_0__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_0__GPIO7_6 (_MX53_PAD_PATA_DA_0__GPIO7_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_0__ESDHC3_RST (_MX53_PAD_PATA_DA_0__ESDHC3_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_0__OWIRE_LINE (_MX53_PAD_PATA_DA_0__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 (_MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_1__PATA_DA_1 (_MX53_PAD_PATA_DA_1__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_1__GPIO7_7 (_MX53_PAD_PATA_DA_1__GPIO7_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_1__ESDHC4_CMD (_MX53_PAD_PATA_DA_1__ESDHC4_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_1__UART3_CTS (_MX53_PAD_PATA_DA_1__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 (_MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_2__PATA_DA_2 (_MX53_PAD_PATA_DA_2__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_2__GPIO7_8 (_MX53_PAD_PATA_DA_2__GPIO7_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_2__ESDHC4_CLK (_MX53_PAD_PATA_DA_2__ESDHC4_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_2__UART3_RTS (_MX53_PAD_PATA_DA_2__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 (_MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_CS_0__PATA_CS_0 (_MX53_PAD_PATA_CS_0__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_CS_0__GPIO7_9 (_MX53_PAD_PATA_CS_0__GPIO7_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX (_MX53_PAD_PATA_CS_0__UART3_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 (_MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_CS_1__PATA_CS_1 (_MX53_PAD_PATA_CS_1__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_CS_1__GPIO7_10 (_MX53_PAD_PATA_CS_1__GPIO7_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX (_MX53_PAD_PATA_CS_1__UART3_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 (_MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA0__PATA_DATA_0 (_MX53_PAD_PATA_DATA0__PATA_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA0__GPIO2_0 (_MX53_PAD_PATA_DATA0__GPIO2_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 (_MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 (_MX53_PAD_PATA_DATA0__ESDHC3_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 (_MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 (_MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 (_MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA1__PATA_DATA_1 (_MX53_PAD_PATA_DATA1__PATA_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA1__GPIO2_1 (_MX53_PAD_PATA_DATA1__GPIO2_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 (_MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 (_MX53_PAD_PATA_DATA1__ESDHC3_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 (_MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 (_MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA2__PATA_DATA_2 (_MX53_PAD_PATA_DATA2__PATA_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA2__GPIO2_2 (_MX53_PAD_PATA_DATA2__GPIO2_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 (_MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 (_MX53_PAD_PATA_DATA2__ESDHC3_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 (_MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 (_MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA3__PATA_DATA_3 (_MX53_PAD_PATA_DATA3__PATA_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA3__GPIO2_3 (_MX53_PAD_PATA_DATA3__GPIO2_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 (_MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 (_MX53_PAD_PATA_DATA3__ESDHC3_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 (_MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 (_MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA4__PATA_DATA_4 (_MX53_PAD_PATA_DATA4__PATA_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA4__GPIO2_4 (_MX53_PAD_PATA_DATA4__GPIO2_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 (_MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 (_MX53_PAD_PATA_DATA4__ESDHC4_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 (_MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 (_MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA5__PATA_DATA_5 (_MX53_PAD_PATA_DATA5__PATA_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA5__GPIO2_5 (_MX53_PAD_PATA_DATA5__GPIO2_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 (_MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 (_MX53_PAD_PATA_DATA5__ESDHC4_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 (_MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 (_MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA6__PATA_DATA_6 (_MX53_PAD_PATA_DATA6__PATA_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA6__GPIO2_6 (_MX53_PAD_PATA_DATA6__GPIO2_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 (_MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 (_MX53_PAD_PATA_DATA6__ESDHC4_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 (_MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 (_MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA7__PATA_DATA_7 (_MX53_PAD_PATA_DATA7__PATA_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA7__GPIO2_7 (_MX53_PAD_PATA_DATA7__GPIO2_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 (_MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 (_MX53_PAD_PATA_DATA7__ESDHC4_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 (_MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 (_MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA8__PATA_DATA_8 (_MX53_PAD_PATA_DATA8__PATA_DATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA8__GPIO2_8 (_MX53_PAD_PATA_DATA8__GPIO2_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 (_MX53_PAD_PATA_DATA8__ESDHC1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 (_MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 (_MX53_PAD_PATA_DATA8__ESDHC3_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 (_MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 (_MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA9__PATA_DATA_9 (_MX53_PAD_PATA_DATA9__PATA_DATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA9__GPIO2_9 (_MX53_PAD_PATA_DATA9__GPIO2_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 (_MX53_PAD_PATA_DATA9__ESDHC1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 (_MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 (_MX53_PAD_PATA_DATA9__ESDHC3_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 (_MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 (_MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA10__PATA_DATA_10 (_MX53_PAD_PATA_DATA10__PATA_DATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA10__GPIO2_10 (_MX53_PAD_PATA_DATA10__GPIO2_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 (_MX53_PAD_PATA_DATA10__ESDHC1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 (_MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 (_MX53_PAD_PATA_DATA10__ESDHC3_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 (_MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 (_MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA11__PATA_DATA_11 (_MX53_PAD_PATA_DATA11__PATA_DATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA11__GPIO2_11 (_MX53_PAD_PATA_DATA11__GPIO2_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 (_MX53_PAD_PATA_DATA11__ESDHC1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 (_MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 (_MX53_PAD_PATA_DATA11__ESDHC3_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 (_MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 (_MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA12__PATA_DATA_12 (_MX53_PAD_PATA_DATA12__PATA_DATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA12__GPIO2_12 (_MX53_PAD_PATA_DATA12__GPIO2_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 (_MX53_PAD_PATA_DATA12__ESDHC2_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 (_MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 (_MX53_PAD_PATA_DATA12__ESDHC4_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 (_MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 (_MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA13__PATA_DATA_13 (_MX53_PAD_PATA_DATA13__PATA_DATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA13__GPIO2_13 (_MX53_PAD_PATA_DATA13__GPIO2_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 (_MX53_PAD_PATA_DATA13__ESDHC2_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 (_MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 (_MX53_PAD_PATA_DATA13__ESDHC4_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 (_MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 (_MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA14__PATA_DATA_14 (_MX53_PAD_PATA_DATA14__PATA_DATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA14__GPIO2_14 (_MX53_PAD_PATA_DATA14__GPIO2_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 (_MX53_PAD_PATA_DATA14__ESDHC2_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 (_MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 (_MX53_PAD_PATA_DATA14__ESDHC4_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 (_MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 (_MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA15__PATA_DATA_15 (_MX53_PAD_PATA_DATA15__PATA_DATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA15__GPIO2_15 (_MX53_PAD_PATA_DATA15__GPIO2_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 (_MX53_PAD_PATA_DATA15__ESDHC2_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 (_MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 (_MX53_PAD_PATA_DATA15__ESDHC4_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 (_MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 (_MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 (_MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA0__GPIO1_16 (_MX53_PAD_SD1_DATA0__GPIO1_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 (_MX53_PAD_SD1_DATA0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA0__CSPI_MISO (_MX53_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP (_MX53_PAD_SD1_DATA0__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 (_MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA1__GPIO1_17 (_MX53_PAD_SD1_DATA1__GPIO1_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 (_MX53_PAD_SD1_DATA1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA1__CSPI_SS0 (_MX53_PAD_SD1_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP (_MX53_PAD_SD1_DATA1__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CMD__ESDHC1_CMD (_MX53_PAD_SD1_CMD__ESDHC1_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CMD__GPIO1_18 (_MX53_PAD_SD1_CMD__GPIO1_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 (_MX53_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CMD__CSPI_MOSI (_MX53_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP (_MX53_PAD_SD1_CMD__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 (_MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA2__GPIO1_19 (_MX53_PAD_SD1_DATA2__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 (_MX53_PAD_SD1_DATA2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA2__PWM2_PWMO (_MX53_PAD_SD1_DATA2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA2__CSPI_SS1 (_MX53_PAD_SD1_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP (_MX53_PAD_SD1_DATA2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CLK__ESDHC1_CLK (_MX53_PAD_SD1_CLK__ESDHC1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CLK__GPIO1_20 (_MX53_PAD_SD1_CLK__GPIO1_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT (_MX53_PAD_SD1_CLK__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CLK__GPT_CLKIN (_MX53_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CLK__CSPI_SCLK (_MX53_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 (_MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 (_MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA3__GPIO1_21 (_MX53_PAD_SD1_DATA3__GPIO1_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 (_MX53_PAD_SD1_DATA3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA3__PWM1_PWMO (_MX53_PAD_SD1_DATA3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA3__CSPI_SS2 (_MX53_PAD_SD1_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 (_MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CLK__ESDHC2_CLK (_MX53_PAD_SD2_CLK__ESDHC2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CLK__GPIO1_10 (_MX53_PAD_SD2_CLK__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CLK__KPP_COL_5 (_MX53_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS (_MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CLK__CSPI_SCLK (_MX53_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CLK__SCC_RANDOM_V (_MX53_PAD_SD2_CLK__SCC_RANDOM_V | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CMD__ESDHC2_CMD (_MX53_PAD_SD2_CMD__ESDHC2_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CMD__GPIO1_11 (_MX53_PAD_SD2_CMD__GPIO1_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CMD__KPP_ROW_5 (_MX53_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC (_MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CMD__CSPI_MOSI (_MX53_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CMD__SCC_RANDOM (_MX53_PAD_SD2_CMD__SCC_RANDOM | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 (_MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA3__GPIO1_12 (_MX53_PAD_SD2_DATA3__GPIO1_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA3__KPP_COL_6 (_MX53_PAD_SD2_DATA3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC (_MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA3__CSPI_SS2 (_MX53_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA3__SJC_DONE (_MX53_PAD_SD2_DATA3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 (_MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA2__GPIO1_13 (_MX53_PAD_SD2_DATA2__GPIO1_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA2__KPP_ROW_6 (_MX53_PAD_SD2_DATA2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD (_MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA2__CSPI_SS1 (_MX53_PAD_SD2_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA2__SJC_FAIL (_MX53_PAD_SD2_DATA2__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 (_MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA1__GPIO1_14 (_MX53_PAD_SD2_DATA1__GPIO1_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA1__KPP_COL_7 (_MX53_PAD_SD2_DATA1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS (_MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA1__CSPI_SS0 (_MX53_PAD_SD2_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO (_MX53_PAD_SD2_DATA1__RTIC_SEC_VIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 (_MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA0__GPIO1_15 (_MX53_PAD_SD2_DATA0__GPIO1_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA0__KPP_ROW_7 (_MX53_PAD_SD2_DATA0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD (_MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA0__CSPI_MISO (_MX53_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT (_MX53_PAD_SD2_DATA0__RTIC_DONE_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_0__CCM_CLKO (_MX53_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_0__GPIO1_0 (_MX53_PAD_GPIO_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_0__KPP_COL_5 (_MX53_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK (_MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_0__EPIT1_EPITO (_MX53_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB (_MX53_PAD_GPIO_0__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR (_MX53_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_0__CSU_TD (_MX53_PAD_GPIO_0__CSU_TD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_1__ESAI1_SCKR (_MX53_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_1__GPIO1_1 (_MX53_PAD_GPIO_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_1__KPP_ROW_5 (_MX53_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK (_MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_1__PWM2_PWMO (_MX53_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_1__WDOG2_WDOG_B (_MX53_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_1__ESDHC1_CD (_MX53_PAD_GPIO_1__ESDHC1_CD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_1__SRC_TESTER_ACK (_MX53_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_9__ESAI1_FSR (_MX53_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_9__GPIO1_9 (_MX53_PAD_GPIO_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_9__KPP_COL_6 (_MX53_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_9__CCM_REF_EN_B (_MX53_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_9__PWM1_PWMO (_MX53_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_9__WDOG1_WDOG_B (_MX53_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_9__ESDHC1_WP (_MX53_PAD_GPIO_9__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_9__SCC_FAIL_STATE (_MX53_PAD_GPIO_9__SCC_FAIL_STATE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_3__ESAI1_HCKR (_MX53_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_3__GPIO1_3 (_MX53_PAD_GPIO_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_3__I2C3_SCL (_MX53_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN (_MX53_PAD_GPIO_3__DPLLIP1_TOG_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_3__CCM_CLKO2 (_MX53_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 (_MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC (_MX53_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_3__MLB_MLBCLK (_MX53_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_6__ESAI1_SCKT (_MX53_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_6__GPIO1_6 (_MX53_PAD_GPIO_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_6__I2C3_SDA (_MX53_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 (_MX53_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB (_MX53_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 (_MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_6__ESDHC2_LCTL (_MX53_PAD_GPIO_6__ESDHC2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_6__MLB_MLBSIG (_MX53_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_2__ESAI1_FST (_MX53_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_2__GPIO1_2 (_MX53_PAD_GPIO_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_2__KPP_ROW_6 (_MX53_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 (_MX53_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 (_MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 (_MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_2__ESDHC2_WP (_MX53_PAD_GPIO_2__ESDHC2_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_2__MLB_MLBDAT (_MX53_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_4__ESAI1_HCKT (_MX53_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_4__GPIO1_4 (_MX53_PAD_GPIO_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_4__KPP_COL_7 (_MX53_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 (_MX53_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 (_MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 (_MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_4__ESDHC2_CD (_MX53_PAD_GPIO_4__ESDHC2_CD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_4__SCC_SEC_STATE (_MX53_PAD_GPIO_4__SCC_SEC_STATE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 (_MX53_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_5__GPIO1_5 (_MX53_PAD_GPIO_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_5__KPP_ROW_7 (_MX53_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_5__CCM_CLKO (_MX53_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 (_MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 (_MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_5__I2C3_SCL (_MX53_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_5__CCM_PLL1_BYP (_MX53_PAD_GPIO_5__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 (_MX53_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_7__GPIO1_7 (_MX53_PAD_GPIO_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_7__EPIT1_EPITO (_MX53_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_7__CAN1_TXCAN (_MX53_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_7__UART2_TXD_MUX (_MX53_PAD_GPIO_7__UART2_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_7__FIRI_RXD (_MX53_PAD_GPIO_7__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_7__SPDIF_PLOCK (_MX53_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_7__CCM_PLL2_BYP (_MX53_PAD_GPIO_7__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 (_MX53_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_8__GPIO1_8 (_MX53_PAD_GPIO_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_8__EPIT2_EPITO (_MX53_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_8__CAN1_RXCAN (_MX53_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_8__UART2_RXD_MUX (_MX53_PAD_GPIO_8__UART2_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_8__FIRI_TXD (_MX53_PAD_GPIO_8__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_8__SPDIF_SRCLK (_MX53_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_8__CCM_PLL3_BYP (_MX53_PAD_GPIO_8__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 (_MX53_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_16__GPIO7_11 (_MX53_PAD_GPIO_16__GPIO7_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT (_MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 (_MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_16__SPDIF_IN1 (_MX53_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_16__I2C3_SDA (_MX53_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_16__SJC_DE_B (_MX53_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_17__ESAI1_TX0 (_MX53_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_17__GPIO7_12 (_MX53_PAD_GPIO_17__GPIO7_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 (_MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_17__GPC_PMIC_RDY (_MX53_PAD_GPIO_17__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG (_MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_17__SPDIF_OUT1 (_MX53_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_17__IPU_SNOOP2 (_MX53_PAD_GPIO_17__IPU_SNOOP2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_17__SJC_JTAG_ACT (_MX53_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_18__ESAI1_TX1 (_MX53_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_18__GPIO7_13 (_MX53_PAD_GPIO_18__GPIO7_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 (_MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_18__OWIRE_LINE (_MX53_PAD_GPIO_18__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG (_MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK (_MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_18__ESDHC1_LCTL (_MX53_PAD_GPIO_18__ESDHC1_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST (_MX53_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) #endif /* __MACH_IOMUX_MX53_H__ */ -- cgit v0.10.2 From bb58b3e8b18c542f30f898fff82f7ce58a4bdf7a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 19 Jan 2011 10:27:33 -0200 Subject: ARM: mx5: Use dummy clock for the keypad Reuse dummy_clk for the imx-keypad device instead of using a dedicated kpp_clk. Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index 0a19e75..c66be0e 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -867,10 +867,6 @@ static struct clk gpt_32k_clk = { .parent = &ckil_clk, }; -static struct clk kpp_clk = { - .id = 0, -}; - static struct clk dummy_clk = { .id = 0, }; @@ -1302,7 +1298,7 @@ static struct clk_lookup mx51_lookups[] = { _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) - _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk) + _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk) _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) -- cgit v0.10.2 From 67f43086a24b77a82724855141a5b7a4d72549bd Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Fri, 14 Jan 2011 23:11:23 +0800 Subject: ARM: mxs: add ocotp read function Signed-off-by: Shawn Guo Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 8bfc8df..cd2fbdf 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -2,6 +2,9 @@ if ARCH_MXS source "arch/arm/mach-mxs/devices/Kconfig" +config MXS_OCOTP + bool + config SOC_IMX23 bool select CPU_ARM926T @@ -26,6 +29,7 @@ config MACH_MX28EVK select SOC_IMX28 select MXS_HAVE_AMBA_DUART select MXS_HAVE_PLATFORM_FEC + select MXS_OCOTP default y help Include support for MX28EVK platform. This includes specific diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile index 39d3f9c..df501a8 100644 --- a/arch/arm/mach-mxs/Makefile +++ b/arch/arm/mach-mxs/Makefile @@ -1,6 +1,8 @@ # Common support obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o +obj-$(CONFIG_MXS_OCOTP) += ocotp.o + obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h index 59133eb..635bb5d 100644 --- a/arch/arm/mach-mxs/include/mach/common.h +++ b/arch/arm/mach-mxs/include/mach/common.h @@ -13,6 +13,7 @@ struct clk; +extern const u32 *mxs_get_ocotp(void); extern int mxs_reset_block(void __iomem *); extern void mxs_timer_init(struct clk *, int); diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c new file mode 100644 index 0000000..65157a3 --- /dev/null +++ b/arch/arm/mach-mxs/ocotp.c @@ -0,0 +1,90 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include + +#define OCOTP_WORD_OFFSET 0x20 +#define OCOTP_WORD_COUNT 0x20 + +#define BM_OCOTP_CTRL_BUSY (1 << 8) +#define BM_OCOTP_CTRL_ERROR (1 << 9) +#define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12) + +static DEFINE_MUTEX(ocotp_mutex); +static u32 ocotp_words[OCOTP_WORD_COUNT]; + +const u32 *mxs_get_ocotp(void) +{ + void __iomem *ocotp_base = MXS_IO_ADDRESS(MXS_OCOTP_BASE_ADDR); + int timeout = 0x400; + size_t i; + static int once = 0; + + if (once) + return ocotp_words; + + mutex_lock(&ocotp_mutex); + + /* + * clk_enable(hbus_clk) for ocotp can be skipped + * as it must be on when system is running. + */ + + /* try to clear ERROR bit */ + __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base); + + /* check both BUSY and ERROR cleared */ + while ((__raw_readl(ocotp_base) & + (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout) + cpu_relax(); + + if (unlikely(!timeout)) + goto error_unlock; + + /* open OCOTP banks for read */ + __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base); + + /* approximately wait 32 hclk cycles */ + udelay(1); + + /* poll BUSY bit becoming cleared */ + timeout = 0x400; + while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout) + cpu_relax(); + + if (unlikely(!timeout)) + goto error_unlock; + + for (i = 0; i < OCOTP_WORD_COUNT; i++) + ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET + + i * 0x10); + + /* close banks for power saving */ + __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base); + + once = 1; + + mutex_unlock(&ocotp_mutex); + + return ocotp_words; + +error_unlock: + mutex_unlock(&ocotp_mutex); + pr_err("%s: timeout in reading OCOTP\n", __func__); + return NULL; +} -- cgit v0.10.2 From a320b2793dae44953dc58e9f681d8f161eb5b3ab Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Fri, 14 Jan 2011 15:25:52 +0800 Subject: ARM: mxs/mx28evk: read fec mac address from ocotp Read fec mac address from ocotp and save it into fec_platform_data mac field for fec driver to use. Signed-off-by: Shawn Guo Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c index 8e2c597..e8db99f 100644 --- a/arch/arm/mach-mxs/mach-mx28evk.c +++ b/arch/arm/mach-mxs/mach-mx28evk.c @@ -119,7 +119,7 @@ static void __init mx28evk_fec_reset(void) gpio_set_value(MX28EVK_FEC_PHY_RESET, 1); } -static struct fec_platform_data mx28_fec_pdata[] = { +static struct fec_platform_data mx28_fec_pdata[] __initdata = { { /* fec0 */ .phy = PHY_INTERFACE_MODE_RMII, @@ -129,12 +129,45 @@ static struct fec_platform_data mx28_fec_pdata[] = { }, }; +static int __init mx28evk_fec_get_mac(void) +{ + int i; + u32 val; + const u32 *ocotp = mxs_get_ocotp(); + + if (!ocotp) + goto error; + + /* + * OCOTP only stores the last 4 octets for each mac address, + * so hard-code Freescale OUI (00:04:9f) here. + */ + for (i = 0; i < 2; i++) { + val = ocotp[i * 4]; + mx28_fec_pdata[i].mac[0] = 0x00; + mx28_fec_pdata[i].mac[1] = 0x04; + mx28_fec_pdata[i].mac[2] = 0x9f; + mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff; + mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff; + mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff; + } + + return 0; + +error: + pr_err("%s: timeout when reading fec mac from OCOTP\n", __func__); + return -ETIMEDOUT; +} + static void __init mx28evk_init(void) { mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads)); mx28_add_duart(); + if (mx28evk_fec_get_mac()) + pr_warn("%s: failed on fec mac setup\n", __func__); + mx28evk_fec_reset(); mx28_add_fec(0, &mx28_fec_pdata[0]); mx28_add_fec(1, &mx28_fec_pdata[1]); -- cgit v0.10.2 From 56f94b1e6eddef55ebc9850ac4e4dfea366401bf Mon Sep 17 00:00:00 2001 From: Daiane Angolini Date: Thu, 9 Dec 2010 15:50:49 -0200 Subject: ARM: mx5/mx51_3ds: Add watchdog support Signed-off-by: Daiane Angolini Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index af8749b..10b6008 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -50,6 +50,7 @@ config MACH_MX51_BABBAGE config MACH_MX51_3DS bool "Support MX51PDK (3DS)" select SOC_IMX51 + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_KEYPAD select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c index 49d6448..8a0619b 100644 --- a/arch/arm/mach-mx5/board-mx51_3ds.c +++ b/arch/arm/mach-mx5/board-mx51_3ds.c @@ -173,6 +173,7 @@ static void __init mxc_board_init(void) imx51_add_sdhci_esdhc_imx(0, NULL); mxc_init_keypad(); + imx51_add_imx2_wdt(0, NULL); } static void __init mx51_3ds_timer_init(void) -- cgit v0.10.2 From 9c2c35848cf77cf8831442492a2f7a6d7723fe0a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 24 Jan 2011 16:55:02 -0200 Subject: ARM: imx: Add initial support for IMX27IPCAM board Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 56684b5..c172418 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -300,4 +300,13 @@ config MACH_MXT_TD60 Include support for i-MXT (aka td60) platform. This includes specific configurations for the module and its peripherals. +config MACH_IMX27IPCAM + bool "IMX27 IPCAM platform" + select SOC_IMX27 + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_UART + help + Include support for IMX27 IPCAM platform. This includes specific + configurations for the board and its peripherals. + endif diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 77100bf..3e49ae0 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -36,3 +36,4 @@ obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o obj-$(CONFIG_MACH_PCA100) += mach-pca100.o obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o +obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c new file mode 100644 index 0000000..d099ea6 --- /dev/null +++ b/arch/arm/mach-imx/mach-imx27ipcam.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Author: Fabio Estevam + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include "devices-imx27.h" + +static const int mx27ipcam_pins[] __initconst = { + /* UART1 */ + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + /* FEC */ + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, +}; + +static void __init mx27ipcam_init(void) +{ + mxc_gpio_setup_multiple_pins(mx27ipcam_pins, ARRAY_SIZE(mx27ipcam_pins), + "mx27ipcam"); + + imx27_add_imx_uart0(NULL); + imx27_add_fec(NULL); + imx27_add_imx2_wdt(NULL); +} + +static void __init mx27ipcam_timer_init(void) +{ + mx27_clocks_init(25000000); +} + +static struct sys_timer mx27ipcam_timer = { + .init = mx27ipcam_timer_init, +}; + +MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM") + /* maintainer: Freescale Semiconductor, Inc. */ + .boot_params = MX27_PHYS_OFFSET + 0x100, + .map_io = mx27_map_io, + .init_irq = mx27_init_irq, + .init_machine = mx27ipcam_init, + .timer = &mx27ipcam_timer, +MACHINE_END diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index 3a70ebf..2315541 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -83,6 +83,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) case MACH_TYPE_MX21ADS: case MACH_TYPE_PCA100: case MACH_TYPE_MXT_TD60: + case MACH_TYPE_IMX27IPCAM: uart_base = MX2X_UART1_BASE_ADDR; break; case MACH_TYPE_MX31LITE: -- cgit v0.10.2 From 47d37d6f94ccf32d302492f969209930b2411f9e Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 11 Jan 2011 15:54:54 +0100 Subject: serial: Add auart driver for i.MX23/28 Signed-off-by: Sascha Hauer diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index c1df767..b7a4d81 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -1595,4 +1595,19 @@ config SERIAL_PCH_UART This driver is for PCH(Platform controller Hub) UART of Intel EG20T which is an IOH(Input/Output Hub) for x86 embedded processor. Enabling PCH_DMA, this PCH UART works as DMA mode. + +config SERIAL_MXS_AUART + depends on ARCH_MXS + tristate "MXS AUART support" + select SERIAL_CORE + help + This driver supports the MXS Application UART (AUART) port. + +config SERIAL_MXS_AUART_CONSOLE + bool "MXS AUART console support" + depends on SERIAL_MXS_AUART=y + select SERIAL_CORE_CONSOLE + help + Enable a MXS AUART port to be the system console. + endmenu diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 8ea92e9..c855071 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -92,3 +92,4 @@ obj-$(CONFIG_SERIAL_MRST_MAX3110) += mrst_max3110.o obj-$(CONFIG_SERIAL_MFD_HSU) += mfd.o obj-$(CONFIG_SERIAL_IFX6X60) += ifx6x60.o obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o +obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o diff --git a/drivers/serial/mxs-auart.c b/drivers/serial/mxs-auart.c new file mode 100644 index 0000000..6d01ac9 --- /dev/null +++ b/drivers/serial/mxs-auart.c @@ -0,0 +1,799 @@ +/* + * Freescale STMP37XX/STMP378X Application UART driver + * + * Author: dmitry pervushin + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define MXS_AUART_PORTS 5 + +#define AUART_CTRL0 0x00000000 +#define AUART_CTRL0_SET 0x00000004 +#define AUART_CTRL0_CLR 0x00000008 +#define AUART_CTRL0_TOG 0x0000000c +#define AUART_CTRL1 0x00000010 +#define AUART_CTRL1_SET 0x00000014 +#define AUART_CTRL1_CLR 0x00000018 +#define AUART_CTRL1_TOG 0x0000001c +#define AUART_CTRL2 0x00000020 +#define AUART_CTRL2_SET 0x00000024 +#define AUART_CTRL2_CLR 0x00000028 +#define AUART_CTRL2_TOG 0x0000002c +#define AUART_LINECTRL 0x00000030 +#define AUART_LINECTRL_SET 0x00000034 +#define AUART_LINECTRL_CLR 0x00000038 +#define AUART_LINECTRL_TOG 0x0000003c +#define AUART_LINECTRL2 0x00000040 +#define AUART_LINECTRL2_SET 0x00000044 +#define AUART_LINECTRL2_CLR 0x00000048 +#define AUART_LINECTRL2_TOG 0x0000004c +#define AUART_INTR 0x00000050 +#define AUART_INTR_SET 0x00000054 +#define AUART_INTR_CLR 0x00000058 +#define AUART_INTR_TOG 0x0000005c +#define AUART_DATA 0x00000060 +#define AUART_STAT 0x00000070 +#define AUART_DEBUG 0x00000080 +#define AUART_VERSION 0x00000090 +#define AUART_AUTOBAUD 0x000000a0 + +#define AUART_CTRL0_SFTRST (1 << 31) +#define AUART_CTRL0_CLKGATE (1 << 30) + +#define AUART_CTRL2_CTSEN (1 << 15) +#define AUART_CTRL2_RTS (1 << 11) +#define AUART_CTRL2_RXE (1 << 9) +#define AUART_CTRL2_TXE (1 << 8) +#define AUART_CTRL2_UARTEN (1 << 0) + +#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16 +#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000 +#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16) +#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8 +#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00 +#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8) +#define AUART_LINECTRL_WLEN_MASK 0x00000060 +#define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5) +#define AUART_LINECTRL_FEN (1 << 4) +#define AUART_LINECTRL_STP2 (1 << 3) +#define AUART_LINECTRL_EPS (1 << 2) +#define AUART_LINECTRL_PEN (1 << 1) +#define AUART_LINECTRL_BRK (1 << 0) + +#define AUART_INTR_RTIEN (1 << 22) +#define AUART_INTR_TXIEN (1 << 21) +#define AUART_INTR_RXIEN (1 << 20) +#define AUART_INTR_CTSMIEN (1 << 17) +#define AUART_INTR_RTIS (1 << 6) +#define AUART_INTR_TXIS (1 << 5) +#define AUART_INTR_RXIS (1 << 4) +#define AUART_INTR_CTSMIS (1 << 1) + +#define AUART_STAT_BUSY (1 << 29) +#define AUART_STAT_CTS (1 << 28) +#define AUART_STAT_TXFE (1 << 27) +#define AUART_STAT_TXFF (1 << 25) +#define AUART_STAT_RXFE (1 << 24) +#define AUART_STAT_OERR (1 << 19) +#define AUART_STAT_BERR (1 << 18) +#define AUART_STAT_PERR (1 << 17) +#define AUART_STAT_FERR (1 << 16) + +static struct uart_driver auart_driver; + +struct mxs_auart_port { + struct uart_port port; + + unsigned int flags; + unsigned int ctrl; + + unsigned int irq; + + struct clk *clk; + struct device *dev; +}; + +static void mxs_auart_stop_tx(struct uart_port *u); + +#define to_auart_port(u) container_of(u, struct mxs_auart_port, port) + +static inline void mxs_auart_tx_chars(struct mxs_auart_port *s) +{ + struct circ_buf *xmit = &s->port.state->xmit; + + while (!(readl(s->port.membase + AUART_STAT) & + AUART_STAT_TXFF)) { + if (s->port.x_char) { + s->port.icount.tx++; + writel(s->port.x_char, + s->port.membase + AUART_DATA); + s->port.x_char = 0; + continue; + } + if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { + s->port.icount.tx++; + writel(xmit->buf[xmit->tail], + s->port.membase + AUART_DATA); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&s->port); + } else + break; + } + if (uart_circ_empty(&(s->port.state->xmit))) + writel(AUART_INTR_TXIEN, + s->port.membase + AUART_INTR_CLR); + else + writel(AUART_INTR_TXIEN, + s->port.membase + AUART_INTR_SET); + + if (uart_tx_stopped(&s->port)) + mxs_auart_stop_tx(&s->port); +} + +static void mxs_auart_rx_char(struct mxs_auart_port *s) +{ + int flag; + u32 stat; + u8 c; + + c = readl(s->port.membase + AUART_DATA); + stat = readl(s->port.membase + AUART_STAT); + + flag = TTY_NORMAL; + s->port.icount.rx++; + + if (stat & AUART_STAT_BERR) { + s->port.icount.brk++; + if (uart_handle_break(&s->port)) + goto out; + } else if (stat & AUART_STAT_PERR) { + s->port.icount.parity++; + } else if (stat & AUART_STAT_FERR) { + s->port.icount.frame++; + } + + /* + * Mask off conditions which should be ingored. + */ + stat &= s->port.read_status_mask; + + if (stat & AUART_STAT_BERR) { + flag = TTY_BREAK; + } else if (stat & AUART_STAT_PERR) + flag = TTY_PARITY; + else if (stat & AUART_STAT_FERR) + flag = TTY_FRAME; + + if (stat & AUART_STAT_OERR) + s->port.icount.overrun++; + + if (uart_handle_sysrq_char(&s->port, c)) + goto out; + + uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag); +out: + writel(stat, s->port.membase + AUART_STAT); +} + +static void mxs_auart_rx_chars(struct mxs_auart_port *s) +{ + struct tty_struct *tty = s->port.state->port.tty; + u32 stat = 0; + + for (;;) { + stat = readl(s->port.membase + AUART_STAT); + if (stat & AUART_STAT_RXFE) + break; + mxs_auart_rx_char(s); + } + + writel(stat, s->port.membase + AUART_STAT); + tty_flip_buffer_push(tty); +} + +static int mxs_auart_request_port(struct uart_port *u) +{ + return 0; +} + +static int mxs_auart_verify_port(struct uart_port *u, + struct serial_struct *ser) +{ + if (u->type != PORT_UNKNOWN && u->type != PORT_IMX) + return -EINVAL; + return 0; +} + +static void mxs_auart_config_port(struct uart_port *u, int flags) +{ +} + +static const char *mxs_auart_type(struct uart_port *u) +{ + struct mxs_auart_port *s = to_auart_port(u); + + return dev_name(s->dev); +} + +static void mxs_auart_release_port(struct uart_port *u) +{ +} + +static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl) +{ + struct mxs_auart_port *s = to_auart_port(u); + + u32 ctrl = readl(u->membase + AUART_CTRL2); + + ctrl &= ~AUART_CTRL2_RTS; + if (mctrl & TIOCM_RTS) + ctrl |= AUART_CTRL2_RTS; + s->ctrl = mctrl; + writel(ctrl, u->membase + AUART_CTRL2); +} + +static u32 mxs_auart_get_mctrl(struct uart_port *u) +{ + struct mxs_auart_port *s = to_auart_port(u); + u32 stat = readl(u->membase + AUART_STAT); + int ctrl2 = readl(u->membase + AUART_CTRL2); + u32 mctrl = s->ctrl; + + mctrl &= ~TIOCM_CTS; + if (stat & AUART_STAT_CTS) + mctrl |= TIOCM_CTS; + + if (ctrl2 & AUART_CTRL2_RTS) + mctrl |= TIOCM_RTS; + + return mctrl; +} + +static void mxs_auart_settermios(struct uart_port *u, + struct ktermios *termios, + struct ktermios *old) +{ + u32 bm, ctrl, ctrl2, div; + unsigned int cflag, baud; + + cflag = termios->c_cflag; + + ctrl = AUART_LINECTRL_FEN; + ctrl2 = readl(u->membase + AUART_CTRL2); + + /* byte size */ + switch (cflag & CSIZE) { + case CS5: + bm = 0; + break; + case CS6: + bm = 1; + break; + case CS7: + bm = 2; + break; + case CS8: + bm = 3; + break; + default: + return; + } + + ctrl |= AUART_LINECTRL_WLEN(bm); + + /* parity */ + if (cflag & PARENB) { + ctrl |= AUART_LINECTRL_PEN; + if ((cflag & PARODD) == 0) + ctrl |= AUART_LINECTRL_EPS; + } + + u->read_status_mask = 0; + + if (termios->c_iflag & INPCK) + u->read_status_mask |= AUART_STAT_PERR; + if (termios->c_iflag & (BRKINT | PARMRK)) + u->read_status_mask |= AUART_STAT_BERR; + + /* + * Characters to ignore + */ + u->ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + u->ignore_status_mask |= AUART_STAT_PERR; + if (termios->c_iflag & IGNBRK) { + u->ignore_status_mask |= AUART_STAT_BERR; + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (termios->c_iflag & IGNPAR) + u->ignore_status_mask |= AUART_STAT_OERR; + } + + /* + * ignore all characters if CREAD is not set + */ + if (cflag & CREAD) + ctrl2 |= AUART_CTRL2_RXE; + else + ctrl2 &= ~AUART_CTRL2_RXE; + + /* figure out the stop bits requested */ + if (cflag & CSTOPB) + ctrl |= AUART_LINECTRL_STP2; + + /* figure out the hardware flow control settings */ + if (cflag & CRTSCTS) + ctrl2 |= AUART_CTRL2_CTSEN; + else + ctrl2 &= ~AUART_CTRL2_CTSEN; + + /* set baud rate */ + baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk); + div = u->uartclk * 32 / baud; + ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F); + ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6); + + writel(ctrl, u->membase + AUART_LINECTRL); + writel(ctrl2, u->membase + AUART_CTRL2); +} + +static irqreturn_t mxs_auart_irq_handle(int irq, void *context) +{ + u32 istatus, istat; + struct mxs_auart_port *s = context; + u32 stat = readl(s->port.membase + AUART_STAT); + + istatus = istat = readl(s->port.membase + AUART_INTR); + + if (istat & AUART_INTR_CTSMIS) { + uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS); + writel(AUART_INTR_CTSMIS, + s->port.membase + AUART_INTR_CLR); + istat &= ~AUART_INTR_CTSMIS; + } + + if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) { + mxs_auart_rx_chars(s); + istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS); + } + + if (istat & AUART_INTR_TXIS) { + mxs_auart_tx_chars(s); + istat &= ~AUART_INTR_TXIS; + } + + writel(istatus & (AUART_INTR_RTIS + | AUART_INTR_TXIS + | AUART_INTR_RXIS + | AUART_INTR_CTSMIS), + s->port.membase + AUART_INTR_CLR); + + return IRQ_HANDLED; +} + +static void mxs_auart_reset(struct uart_port *u) +{ + int i; + unsigned int reg; + + writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR); + + for (i = 0; i < 10000; i++) { + reg = readl(u->membase + AUART_CTRL0); + if (!(reg & AUART_CTRL0_SFTRST)) + break; + udelay(3); + } + writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR); +} + +static int mxs_auart_startup(struct uart_port *u) +{ + struct mxs_auart_port *s = to_auart_port(u); + + clk_enable(s->clk); + + writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR); + + writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET); + + writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN, + u->membase + AUART_INTR); + + /* + * Enable fifo so all four bytes of a DMA word are written to + * output (otherwise, only the LSB is written, ie. 1 in 4 bytes) + */ + writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET); + + return 0; +} + +static void mxs_auart_shutdown(struct uart_port *u) +{ + struct mxs_auart_port *s = to_auart_port(u); + + writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR); + + writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET); + + writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN, + u->membase + AUART_INTR_CLR); + + clk_disable(s->clk); +} + +static unsigned int mxs_auart_tx_empty(struct uart_port *u) +{ + if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE) + return TIOCSER_TEMT; + else + return 0; +} + +static void mxs_auart_start_tx(struct uart_port *u) +{ + struct mxs_auart_port *s = to_auart_port(u); + + /* enable transmitter */ + writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET); + + mxs_auart_tx_chars(s); +} + +static void mxs_auart_stop_tx(struct uart_port *u) +{ + writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR); +} + +static void mxs_auart_stop_rx(struct uart_port *u) +{ + writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR); +} + +static void mxs_auart_break_ctl(struct uart_port *u, int ctl) +{ + if (ctl) + writel(AUART_LINECTRL_BRK, + u->membase + AUART_LINECTRL_SET); + else + writel(AUART_LINECTRL_BRK, + u->membase + AUART_LINECTRL_CLR); +} + +static void mxs_auart_enable_ms(struct uart_port *port) +{ + /* just empty */ +} + +static struct uart_ops mxs_auart_ops = { + .tx_empty = mxs_auart_tx_empty, + .start_tx = mxs_auart_start_tx, + .stop_tx = mxs_auart_stop_tx, + .stop_rx = mxs_auart_stop_rx, + .enable_ms = mxs_auart_enable_ms, + .break_ctl = mxs_auart_break_ctl, + .set_mctrl = mxs_auart_set_mctrl, + .get_mctrl = mxs_auart_get_mctrl, + .startup = mxs_auart_startup, + .shutdown = mxs_auart_shutdown, + .set_termios = mxs_auart_settermios, + .type = mxs_auart_type, + .release_port = mxs_auart_release_port, + .request_port = mxs_auart_request_port, + .config_port = mxs_auart_config_port, + .verify_port = mxs_auart_verify_port, +}; + +static struct mxs_auart_port *auart_port[MXS_AUART_PORTS]; + +#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE +static void mxs_auart_console_putchar(struct uart_port *port, int ch) +{ + unsigned int to = 1000; + + while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) { + if (!to--) + break; + udelay(1); + } + + writel(ch, port->membase + AUART_DATA); +} + +static void +auart_console_write(struct console *co, const char *str, unsigned int count) +{ + struct mxs_auart_port *s; + struct uart_port *port; + unsigned int old_ctrl0, old_ctrl2; + unsigned int to = 1000; + + if (co->index > MXS_AUART_PORTS || co->index < 0) + return; + + s = auart_port[co->index]; + port = &s->port; + + clk_enable(s->clk); + + /* First save the CR then disable the interrupts */ + old_ctrl2 = readl(port->membase + AUART_CTRL2); + old_ctrl0 = readl(port->membase + AUART_CTRL0); + + writel(AUART_CTRL0_CLKGATE, + port->membase + AUART_CTRL0_CLR); + writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, + port->membase + AUART_CTRL2_SET); + + uart_console_write(port, str, count, mxs_auart_console_putchar); + + /* + * Finally, wait for transmitter to become empty + * and restore the TCR + */ + while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) { + if (!to--) + break; + udelay(1); + } + + writel(old_ctrl0, port->membase + AUART_CTRL0); + writel(old_ctrl2, port->membase + AUART_CTRL2); + + clk_disable(s->clk); +} + +static void __init +auart_console_get_options(struct uart_port *port, int *baud, + int *parity, int *bits) +{ + unsigned int lcr_h, quot; + + if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN)) + return; + + lcr_h = readl(port->membase + AUART_LINECTRL); + + *parity = 'n'; + if (lcr_h & AUART_LINECTRL_PEN) { + if (lcr_h & AUART_LINECTRL_EPS) + *parity = 'e'; + else + *parity = 'o'; + } + + if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2)) + *bits = 7; + else + *bits = 8; + + quot = ((readl(port->membase + AUART_LINECTRL) + & AUART_LINECTRL_BAUD_DIVINT_MASK)) + >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6); + quot |= ((readl(port->membase + AUART_LINECTRL) + & AUART_LINECTRL_BAUD_DIVFRAC_MASK)) + >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT; + if (quot == 0) + quot = 1; + + *baud = (port->uartclk << 2) / quot; +} + +static int __init +auart_console_setup(struct console *co, char *options) +{ + struct mxs_auart_port *s; + int baud = 9600; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + int ret; + + /* + * Check whether an invalid uart number has been specified, and + * if so, search for the first available port that does have + * console support. + */ + if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port)) + co->index = 0; + s = auart_port[co->index]; + if (!s) + return -ENODEV; + + clk_enable(s->clk); + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + else + auart_console_get_options(&s->port, &baud, &parity, &bits); + + ret = uart_set_options(&s->port, co, baud, parity, bits, flow); + + clk_disable(s->clk); + + return ret; +} + +static struct console auart_console = { + .name = "ttyAPP", + .write = auart_console_write, + .device = uart_console_device, + .setup = auart_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &auart_driver, +}; +#endif + +static struct uart_driver auart_driver = { + .owner = THIS_MODULE, + .driver_name = "ttyAPP", + .dev_name = "ttyAPP", + .major = 0, + .minor = 0, + .nr = MXS_AUART_PORTS, +#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE + .cons = &auart_console, +#endif +}; + +static int __devinit mxs_auart_probe(struct platform_device *pdev) +{ + struct mxs_auart_port *s; + u32 version; + int ret = 0; + struct resource *r; + + s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL); + if (!s) { + ret = -ENOMEM; + goto out; + } + + s->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(s->clk)) { + ret = PTR_ERR(s->clk); + goto out_free; + } + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + ret = -ENXIO; + goto out_free_clk; + } + + s->port.mapbase = r->start; + s->port.membase = ioremap(r->start, resource_size(r)); + s->port.ops = &mxs_auart_ops; + s->port.iotype = UPIO_MEM; + s->port.line = pdev->id < 0 ? 0 : pdev->id; + s->port.fifosize = 16; + s->port.uartclk = clk_get_rate(s->clk); + s->port.type = PORT_IMX; + s->port.dev = s->dev = get_device(&pdev->dev); + + s->flags = 0; + s->ctrl = 0; + + s->irq = platform_get_irq(pdev, 0); + s->port.irq = s->irq; + ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s); + if (ret) + goto out_free_clk; + + platform_set_drvdata(pdev, s); + + auart_port[pdev->id] = s; + + mxs_auart_reset(&s->port); + + ret = uart_add_one_port(&auart_driver, &s->port); + if (ret) + goto out_free_irq; + + version = readl(s->port.membase + AUART_VERSION); + dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n", + (version >> 24) & 0xff, + (version >> 16) & 0xff, version & 0xffff); + + return 0; + +out_free_irq: + auart_port[pdev->id] = NULL; + free_irq(s->irq, s); +out_free_clk: + clk_put(s->clk); +out_free: + kfree(s); +out: + return ret; +} + +static int __devexit mxs_auart_remove(struct platform_device *pdev) +{ + struct mxs_auart_port *s = platform_get_drvdata(pdev); + + uart_remove_one_port(&auart_driver, &s->port); + + auart_port[pdev->id] = NULL; + + clk_put(s->clk); + free_irq(s->irq, s); + kfree(s); + + return 0; +} + +static struct platform_driver mxs_auart_driver = { + .probe = mxs_auart_probe, + .remove = __devexit_p(mxs_auart_remove), + .driver = { + .name = "mxs-auart", + .owner = THIS_MODULE, + }, +}; + +static int __init mxs_auart_init(void) +{ + int r; + + r = uart_register_driver(&auart_driver); + if (r) + goto out; + + r = platform_driver_register(&mxs_auart_driver); + if (r) + goto out_err; + + return 0; +out_err: + uart_unregister_driver(&auart_driver); +out: + return r; +} + +static void __exit mxs_auart_exit(void) +{ + platform_driver_unregister(&mxs_auart_driver); + uart_unregister_driver(&auart_driver); +} + +module_init(mxs_auart_init); +module_exit(mxs_auart_exit); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Freescale MXS application uart driver"); -- cgit v0.10.2 From cf3567aaad0304410e465a55313c8f0d25ef306d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 11 Jan 2011 15:56:40 +0100 Subject: ARM MXS: Add auart platform support for i.MX28 Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 56312c0..2f1a990 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -609,6 +609,11 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("duart", NULL, uart_clk) _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk) _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk) + _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk) + _REGISTER_CLOCK("mxs-auart.1", NULL, uart_clk) + _REGISTER_CLOCK("mxs-auart.2", NULL, uart_clk) + _REGISTER_CLOCK("mxs-auart.3", NULL, uart_clk) + _REGISTER_CLOCK("mxs-auart.4", NULL, uart_clk) _REGISTER_CLOCK("fec.0", NULL, fec_clk) _REGISTER_CLOCK("rtc", NULL, rtc_clk) _REGISTER_CLOCK("pll2", NULL, pll2_clk) diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h index 33773a6..1ab7bf0 100644 --- a/arch/arm/mach-mxs/devices-mx28.h +++ b/arch/arm/mach-mxs/devices-mx28.h @@ -15,6 +15,14 @@ extern const struct amba_device mx28_duart_device __initconst; #define mx28_add_duart() \ mxs_add_duart(&mx28_duart_device) +extern const struct mxs_auart_data mx28_auart_data[] __initconst; +#define mx28_add_auart(id) mxs_add_auart(&mx28_auart_data[id]) +#define mx28_add_auart0() mx28_add_auart(0) +#define mx28_add_auart1() mx28_add_auart(1) +#define mx28_add_auart2() mx28_add_auart(2) +#define mx28_add_auart3() mx28_add_auart(3) +#define mx28_add_auart4() mx28_add_auart(4) + extern const struct mxs_fec_data mx28_fec_data[] __initconst; #define mx28_add_fec(id, pdata) \ mxs_add_fec(&mx28_fec_data[id], pdata) diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig index cf7dc1a..3001b75 100644 --- a/arch/arm/mach-mxs/devices/Kconfig +++ b/arch/arm/mach-mxs/devices/Kconfig @@ -2,5 +2,8 @@ config MXS_HAVE_AMBA_DUART bool select ARM_AMBA +config MXS_HAVE_PLATFORM_AUART + bool + config MXS_HAVE_PLATFORM_FEC bool diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile index d0a09f6..c814d05 100644 --- a/arch/arm/mach-mxs/devices/Makefile +++ b/arch/arm/mach-mxs/devices/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o +obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o diff --git a/arch/arm/mach-mxs/devices/platform-auart.c b/arch/arm/mach-mxs/devices/platform-auart.c new file mode 100644 index 0000000..f0dbf8a --- /dev/null +++ b/arch/arm/mach-mxs/devices/platform-auart.c @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2010 Pengutronix + * Sascha Hauer + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include +#include + +#define mxs_auart_data_entry_single(soc, _id) \ + { \ + .id = _id, \ + .iobase = soc ## _AUART ## _id ## _BASE_ADDR, \ + .irq = soc ## _INT_AUART ## _id, \ + } + +#define mxs_auart_data_entry(soc, _id) \ + [_id] = mxs_auart_data_entry_single(soc, _id) + +#ifdef CONFIG_SOC_IMX28 +const struct mxs_auart_data mx28_auart_data[] __initconst = { +#define mx28_auart_data_entry(_id) \ + mxs_auart_data_entry(MX28, _id) + mx28_auart_data_entry(0), + mx28_auart_data_entry(1), + mx28_auart_data_entry(2), + mx28_auart_data_entry(3), + mx28_auart_data_entry(4), +}; +#endif + +struct platform_device *__init mxs_add_auart( + const struct mxs_auart_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return mxs_add_platform_device_dmamask("mxs-auart", data->id, + res, ARRAY_SIZE(res), NULL, 0, + DMA_BIT_MASK(32)); +} + diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h index 6c3d1a1..bed4002 100644 --- a/arch/arm/mach-mxs/include/mach/devices-common.h +++ b/arch/arm/mach-mxs/include/mach/devices-common.h @@ -30,6 +30,16 @@ int __init mxs_add_amba_device(const struct amba_device *dev); /* duart */ int __init mxs_add_duart(const struct amba_device *dev); +/* auart */ +struct mxs_auart_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init mxs_add_auart( + const struct mxs_auart_data *data); + /* fec */ #include struct mxs_fec_data { -- cgit v0.10.2 From 376e9c5848abef8c72c09bd89f2f7ee128caa104 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 24 Jan 2011 17:05:25 +0800 Subject: ARM: mxs: add initial pm support This is a very initial pm support and basically does nothing. With this pm support entry, drivers can start testing their own pm functions. Signed-off-by: Shawn Guo Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile index df501a8..6b26f02 100644 --- a/arch/arm/mach-mxs/Makefile +++ b/arch/arm/mach-mxs/Makefile @@ -2,6 +2,7 @@ obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o obj-$(CONFIG_MXS_OCOTP) += ocotp.o +obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c new file mode 100644 index 0000000..fb042da --- /dev/null +++ b/arch/arm/mach-mxs/pm.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static int mxs_suspend_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_MEM: + arch_idle(); + break; + + default: + return -EINVAL; + } + return 0; +} + +static struct platform_suspend_ops mxs_suspend_ops = { + .enter = mxs_suspend_enter, + .valid = suspend_valid_only_mem, +}; + +static int __init mxs_pm_init(void) +{ + suspend_set_ops(&mxs_suspend_ops); + return 0; +} +device_initcall(mxs_pm_init); -- cgit v0.10.2 From 0fbfd987ffd5e0b0d137a5684d4865bb1efac6a3 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Jan 2011 11:18:02 +0100 Subject: ARM i.MX35 pcm043: remove unnecessary CONFIG_I2C ifdefs Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index bcf83fc..a27022d 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -115,7 +115,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = { .bitrate = 50000, }; @@ -134,7 +133,6 @@ static struct i2c_board_info pcm043_i2c_devices[] = { I2C_BOARD_INFO("pcf8563", 0x51), } }; -#endif static struct platform_device *devices[] __initdata = { &pcm043_flash, @@ -369,12 +367,10 @@ static void __init mxc_board_init(void) imx35_add_imx_uart1(&uart_pdata); -#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE i2c_register_board_info(0, pcm043_i2c_devices, ARRAY_SIZE(pcm043_i2c_devices)); imx35_add_imx_i2c0(&pcm043_i2c0_data); -#endif mxc_register_device(&mx3_ipu, &mx3_ipu_data); mxc_register_device(&mx3_fb, &mx3fb_pdata); -- cgit v0.10.2 From 070ed7335961825f6c1a137b929c67627c31c907 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Jan 2011 11:19:35 +0100 Subject: ARM i.MX35 pcm043: put usbh1 outside CONFIG_USB_ULPI The usbh1 port of the pcm043 does not use ulpi, so put it outside the corresponding ifdefs. Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index a27022d..a515290f 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -310,13 +310,13 @@ static struct mxc_usbh_platform_data otg_pdata __initdata = { .portsc = MXC_EHCI_MODE_UTMI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; +#endif static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { .portsc = MXC_EHCI_MODE_SERIAL, .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN, }; -#endif static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, @@ -382,9 +382,9 @@ static void __init mxc_board_init(void) imx35_add_mxc_ehci_otg(&otg_pdata); } - - imx35_add_mxc_ehci_hs(&usbh1_pdata); #endif + imx35_add_mxc_ehci_hs(&usbh1_pdata); + if (!otg_mode_host) imx35_add_fsl_usb2_udc(&otg_device_pdata); -- cgit v0.10.2 From afc11e6ef7547243f1429cce8de616049439a172 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Jan 2011 11:21:26 +0100 Subject: ARM i.MX31 mx31ads: remove unnecessary CONFIG_I2C ifdefs Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index 88b97d6..f9a7109 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -476,7 +476,6 @@ static struct wm8350_platform_data __initdata mx31_wm8350_pdata = { }; #endif -#if defined(CONFIG_I2C_IMX) || defined(CONFIG_I2C_IMX_MODULE) static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = { #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 { @@ -497,11 +496,6 @@ static void mxc_init_i2c(void) imx31_add_imx_i2c1(NULL); } -#else -static void mxc_init_i2c(void) -{ -} -#endif static unsigned int ssi_pins[] = { MX31_PIN_SFS5__SFS5, -- cgit v0.10.2 From 889faeaad0333f692f8acd870faeaa01bf1fc21d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Jan 2011 11:21:59 +0100 Subject: ARM i.MX31 mx31ads: remove unnecessary CONFIG_SERIAL_IMX ifdefs Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index f9a7109..1a83dc5 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -117,7 +117,6 @@ static inline int mxc_init_extuart(void) } #endif -#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -134,11 +133,6 @@ static inline void mxc_init_imx_uart(void) mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); imx31_add_imx_uart0(&uart_pdata); } -#else /* !SERIAL_IMX */ -static inline void mxc_init_imx_uart(void) -{ -} -#endif /* !SERIAL_IMX */ static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc) { -- cgit v0.10.2 From 9f43e44be8787ddc01652dfc4331b34ae1475426 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Jan 2011 11:22:31 +0100 Subject: ARM i.MX31 mx31ads: remove unnecessary CONFIG_SERIAL_8250 ifdefs Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index 1a83dc5..e40eb6e 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -73,8 +73,7 @@ * This file contains the board-specific initialization routines. */ -#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) -/*! +/* * The serial port definition structure. */ static struct plat_serial8250_port serial_platform_data[] = { @@ -110,12 +109,6 @@ static int __init mxc_init_extuart(void) { return platform_device_register(&serial_device); } -#else -static inline int mxc_init_extuart(void) -{ - return 0; -} -#endif static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, -- cgit v0.10.2 From 5ec561afbc44dc8dfe789deafa5bf47da463938a Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Jan 2011 11:23:44 +0100 Subject: ARM i.MX27 pca100: remove unnecessary CONFIG_SPI_IMX ifdefs Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index cccc0a0..faa4e04 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -187,7 +187,6 @@ static struct i2c_board_info pca100_i2c_devices[] = { } }; -#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) static struct spi_eeprom at25320 = { .name = "at25320an", .byte_len = 4096, @@ -211,7 +210,6 @@ static const struct spi_imx_master pca100_spi0_data __initconst = { .chipselect = pca100_spi_cs, .num_chipselect = ARRAY_SIZE(pca100_spi_cs), }; -#endif static void pca100_ac97_warm_reset(struct snd_ac97 *ac97) { @@ -389,13 +387,11 @@ static void __init pca100_init(void) imx27_add_imx_i2c(1, &pca100_i2c1_data); -#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN); mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN); spi_register_board_info(pca100_spi_board_info, ARRAY_SIZE(pca100_spi_board_info)); imx27_add_spi_imx0(&pca100_spi0_data); -#endif gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs"); gpio_direction_output(OTG_PHY_CS_GPIO, 1); -- cgit v0.10.2 From 285faa1b5631968aa27e9816f082448bcd2ba044 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Jan 2011 11:25:40 +0100 Subject: ARM i.MX27 eukrea mbimx27: remove unnecessary CONFIG_SPI_IMX ifdefs Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c index 275c858..b6d68cf 100644 --- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c @@ -357,13 +357,11 @@ void __init eukrea_mbimx27_baseboard_init(void) ads7846_dev_init(); #endif -#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) /* SPI_CS0 init */ mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT); imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data); spi_register_board_info(eukrea_mbimx27_spi_board_info, ARRAY_SIZE(eukrea_mbimx27_spi_board_info)); -#endif /* Leds configuration */ mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT); -- cgit v0.10.2 From b49a2a69e561b7bf22f4c081d7c44aa992e51509 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Jan 2011 11:26:25 +0100 Subject: ARM i.MX31 pcm037 eet: remove unnecessary CONFIG_SPI_IMX ifdefs Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c index fda5654..df6fb07 100644 --- a/arch/arm/mach-mx3/mach-pcm037_eet.c +++ b/arch/arm/mach-mx3/mach-pcm037_eet.c @@ -180,9 +180,7 @@ static int __init eet_init_devices(void) /* SPI */ spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev)); -#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) imx31_add_spi_imx0(&pcm037_spi1_pdata); -#endif platform_device_register(&pcm037_gpio_keys_device); -- cgit v0.10.2 From 0c1c8511a39ac980921e1c06b3f5809c7a42b522 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Jan 2011 11:30:18 +0100 Subject: ARM i.MX51 mx51 3ds: remove unnecessary CONFIG_SERIAL_IMX ifdefs Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c index 8a0619b..2f5acd0 100644 --- a/arch/arm/mach-mx5/board-mx51_3ds.c +++ b/arch/arm/mach-mx5/board-mx51_3ds.c @@ -71,23 +71,10 @@ static iomux_v3_cfg_t mx51_3ds_pads[] = { }; /* Serial ports */ -#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -static inline void mxc_init_imx_uart(void) -{ - imx51_add_imx_uart(0, &uart_pdata); - imx51_add_imx_uart(1, &uart_pdata); - imx51_add_imx_uart(2, &uart_pdata); -} -#else /* !SERIAL_IMX */ -static inline void mxc_init_imx_uart(void) -{ -} -#endif /* SERIAL_IMX */ - #if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE) static int mx51_3ds_board_keymap[] = { KEY(0, 0, KEY_1), @@ -161,7 +148,10 @@ static void __init mxc_board_init(void) { mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads, ARRAY_SIZE(mx51_3ds_pads)); - mxc_init_imx_uart(); + + imx51_add_imx_uart(0, &uart_pdata); + imx51_add_imx_uart(1, &uart_pdata); + imx51_add_imx_uart(2, &uart_pdata); imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata); spi_register_board_info(mx51_3ds_spi_nor_device, -- cgit v0.10.2 From 27d2d62b8b03c9dd2de9a367c19812e089da71c5 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Jan 2011 11:30:33 +0100 Subject: ARM i.MX51 mx51 babbage: remove unnecessary CONFIG_SERIAL_IMX ifdefs Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index 1d231e8..d9d402e 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -161,23 +161,10 @@ static iomux_v3_cfg_t mx51babbage_pads[] = { }; /* Serial ports */ -#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -static inline void mxc_init_imx_uart(void) -{ - imx51_add_imx_uart(0, &uart_pdata); - imx51_add_imx_uart(1, &uart_pdata); - imx51_add_imx_uart(2, &uart_pdata); -} -#else /* !SERIAL_IMX */ -static inline void mxc_init_imx_uart(void) -{ -} -#endif /* SERIAL_IMX */ - static const struct imxi2c_platform_data babbage_i2c_data __initconst = { .bitrate = 100000, }; @@ -360,7 +347,11 @@ static void __init mxc_board_init(void) #endif mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, ARRAY_SIZE(mx51babbage_pads)); - mxc_init_imx_uart(); + + imx51_add_imx_uart(0, &uart_pdata); + imx51_add_imx_uart(1, &uart_pdata); + imx51_add_imx_uart(2, &uart_pdata); + babbage_fec_reset(); imx51_add_fec(NULL); -- cgit v0.10.2 From 818956e0b68f35ef56e9361d0fdea5d935e3827a Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Jan 2011 11:31:35 +0100 Subject: ARM i.MX51 mx51-3ds: remove unnecessary CONFIG_KEYBOARD_IMX ifdefs Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c index 2f5acd0..55d5746 100644 --- a/arch/arm/mach-mx5/board-mx51_3ds.c +++ b/arch/arm/mach-mx5/board-mx51_3ds.c @@ -75,7 +75,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE) static int mx51_3ds_board_keymap[] = { KEY(0, 0, KEY_1), KEY(0, 1, KEY_2), @@ -111,16 +110,6 @@ static const struct matrix_keymap_data mx51_3ds_map_data __initconst = { .keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap), }; -static void mxc_init_keypad(void) -{ - imx51_add_imx_keypad(&mx51_3ds_map_data); -} -#else -static inline void mxc_init_keypad(void) -{ -} -#endif - static int mx51_3ds_spi2_cs[] = { MXC_SPI_CS(0), MX51_3DS_ECSPI2_CS, @@ -162,7 +151,7 @@ static void __init mxc_board_init(void) "devices on the board are unusable.\n"); imx51_add_sdhci_esdhc_imx(0, NULL); - mxc_init_keypad(); + imx51_add_imx_keypad(&mx51_3ds_map_data); imx51_add_imx2_wdt(0, NULL); } -- cgit v0.10.2 From 7f16f817e20b187e3130ce16f510971cf8ff5d07 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Jan 2011 11:34:11 +0100 Subject: ARM i.MX51 cpuimx51: remove unnecessary CONFIG_SERIAL_8250 ifdefs Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c index f8652ef..f576a97 100644 --- a/arch/arm/mach-mx5/board-cpuimx51.c +++ b/arch/arm/mach-mx5/board-cpuimx51.c @@ -60,7 +60,6 @@ #define MX51_USB_PLL_DIV_19_2_MHZ 0x01 #define MX51_USB_PLL_DIV_24_MHZ 0x02 -#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) static struct plat_serial8250_port serial_platform_data[] = { { .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000), @@ -105,12 +104,9 @@ static struct platform_device serial_device = { .platform_data = serial_platform_data, }, }; -#endif static struct platform_device *devices[] __initdata = { -#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) &serial_device, -#endif }; static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = { -- cgit v0.10.2 From 53cdd3068b7b8e3a1a0e540ec42d9037296243b7 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Jan 2011 11:34:33 +0100 Subject: ARM i.MX51 efikamx: remove unnecessary CONFIG_SERIAL_IMX ifdefs Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c index b7946f8..e237040 100644 --- a/arch/arm/mach-mx5/board-mx51_efikamx.c +++ b/arch/arm/mach-mx5/board-mx51_efikamx.c @@ -121,23 +121,10 @@ static iomux_v3_cfg_t mx51efikamx_pads[] = { }; /* Serial ports */ -#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) static const struct imxuart_platform_data uart_pdata = { .flags = IMXUART_HAVE_RTSCTS, }; -static inline void mxc_init_imx_uart(void) -{ - imx51_add_imx_uart(0, &uart_pdata); - imx51_add_imx_uart(1, &uart_pdata); - imx51_add_imx_uart(2, &uart_pdata); -} -#else /* !SERIAL_IMX */ -static inline void mxc_init_imx_uart(void) -{ -} -#endif /* SERIAL_IMX */ - /* This function is board specific as the bit mask for the plldiv will also * be different for other Freescale SoCs, thus a common bitmask is not * possible and cannot get place in /plat-mxc/ehci.c. @@ -320,7 +307,9 @@ static void __init mxc_board_init(void) ARRAY_SIZE(mx51efikamx_pads)); mx51_efikamx_board_id(); mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); - mxc_init_imx_uart(); + imx51_add_imx_uart(0, &uart_pdata); + imx51_add_imx_uart(1, &uart_pdata); + imx51_add_imx_uart(2, &uart_pdata); imx51_add_sdhci_esdhc_imx(0, NULL); /* on < 1.2 boards both SD controllers are used */ -- cgit v0.10.2 From ef19660b0aac537928a13a4087908cc23fa4c002 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 24 Jan 2011 12:57:46 +0100 Subject: ARM i.MX23/28: deobfuscate gpio initialization Signed-off-by: Sascha Hauer Acked-by: Shawn Guo Acked-by: Wolfram Sang diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c index d7ad7a6..36df2d7 100644 --- a/arch/arm/mach-mxs/gpio.c +++ b/arch/arm/mach-mxs/gpio.c @@ -297,20 +297,17 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt) .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32, \ } -#define DEFINE_REGISTER_FUNCTION(prefix) \ -int __init prefix ## _register_gpios(void) \ -{ \ - return mxs_gpio_init(prefix ## _gpio_ports, \ - ARRAY_SIZE(prefix ## _gpio_ports)); \ -} - #ifdef CONFIG_SOC_IMX23 static struct mxs_gpio_port mx23_gpio_ports[] = { DEFINE_MXS_GPIO_PORT(MX23, 0), DEFINE_MXS_GPIO_PORT(MX23, 1), DEFINE_MXS_GPIO_PORT(MX23, 2), }; -DEFINE_REGISTER_FUNCTION(mx23) + +int __init mx23_register_gpios(void) +{ + return mxs_gpio_init(mx23_gpio_ports, ARRAY_SIZE(mx23_gpio_ports)); +} #endif #ifdef CONFIG_SOC_IMX28 @@ -321,5 +318,9 @@ static struct mxs_gpio_port mx28_gpio_ports[] = { DEFINE_MXS_GPIO_PORT(MX28, 3), DEFINE_MXS_GPIO_PORT(MX28, 4), }; -DEFINE_REGISTER_FUNCTION(mx28) + +int __init mx28_register_gpios(void) +{ + return mxs_gpio_init(mx28_gpio_ports, ARRAY_SIZE(mx28_gpio_ports)); +} #endif -- cgit v0.10.2 From 0e8b462de06e0559fc7c5a73d1d913782397987d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 24 Jan 2011 13:09:41 +0100 Subject: ARM i.MX23/28: do not use complicated macros if not necessary Get rid of ## preprocessor construct where it only makes the code harder to read. Signed-off-by: Sascha Hauer Acked-by: Shawn Guo Acked-by: Wolfram Sang diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c index 36df2d7..8bcb340 100644 --- a/arch/arm/mach-mxs/gpio.c +++ b/arch/arm/mach-mxs/gpio.c @@ -287,21 +287,23 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt) return 0; } -#define DEFINE_MXS_GPIO_PORT(soc, _id) \ +#define MX23_GPIO_BASE MX23_IO_ADDRESS(MX23_PINCTRL_BASE_ADDR) +#define MX28_GPIO_BASE MX28_IO_ADDRESS(MX28_PINCTRL_BASE_ADDR) + +#define DEFINE_MXS_GPIO_PORT(_base, _irq, _id) \ { \ .chip.label = "gpio-" #_id, \ .id = _id, \ - .irq = soc ## _INT_GPIO ## _id, \ - .base = soc ## _IO_ADDRESS( \ - soc ## _PINCTRL ## _BASE_ADDR), \ + .irq = _irq, \ + .base = _base, \ .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32, \ } #ifdef CONFIG_SOC_IMX23 static struct mxs_gpio_port mx23_gpio_ports[] = { - DEFINE_MXS_GPIO_PORT(MX23, 0), - DEFINE_MXS_GPIO_PORT(MX23, 1), - DEFINE_MXS_GPIO_PORT(MX23, 2), + DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO0, 0), + DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO1, 1), + DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO2, 2), }; int __init mx23_register_gpios(void) @@ -312,11 +314,11 @@ int __init mx23_register_gpios(void) #ifdef CONFIG_SOC_IMX28 static struct mxs_gpio_port mx28_gpio_ports[] = { - DEFINE_MXS_GPIO_PORT(MX28, 0), - DEFINE_MXS_GPIO_PORT(MX28, 1), - DEFINE_MXS_GPIO_PORT(MX28, 2), - DEFINE_MXS_GPIO_PORT(MX28, 3), - DEFINE_MXS_GPIO_PORT(MX28, 4), + DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO0, 0), + DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO1, 1), + DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO2, 2), + DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO3, 3), + DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO4, 4), }; int __init mx28_register_gpios(void) -- cgit v0.10.2 From d69934bc7bf677a51a13cdbcaa5eae45ea9e2fda Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 24 Jan 2011 09:04:27 +0100 Subject: ARM i.MX23: remove reserved register defines Signed-off-by: Sascha Hauer Acked-by: Shawn Guo Acked-by: Wolfram Sang diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx23.h b/arch/arm/mach-mxs/regs-clkctrl-mx23.h index dbc0474..0ea5c9d 100644 --- a/arch/arm/mach-mxs/regs-clkctrl-mx23.h +++ b/arch/arm/mach-mxs/regs-clkctrl-mx23.h @@ -33,10 +33,6 @@ #define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008) #define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c) -#define BP_CLKCTRL_PLLCTRL0_RSRVD6 30 -#define BM_CLKCTRL_PLLCTRL0_RSRVD6 0xC0000000 -#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \ - (((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6) #define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28 #define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000 #define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \ @@ -45,10 +41,6 @@ #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1 #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2 #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3 -#define BP_CLKCTRL_PLLCTRL0_RSRVD5 26 -#define BM_CLKCTRL_PLLCTRL0_RSRVD5 0x0C000000 -#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v) \ - (((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5) #define BP_CLKCTRL_PLLCTRL0_CP_SEL 24 #define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000 #define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \ @@ -57,10 +49,6 @@ #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1 #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2 #define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3 -#define BP_CLKCTRL_PLLCTRL0_RSRVD4 22 -#define BM_CLKCTRL_PLLCTRL0_RSRVD4 0x00C00000 -#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v) \ - (((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4) #define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20 #define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000 #define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \ @@ -69,23 +57,13 @@ #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1 #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2 #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3 -#define BM_CLKCTRL_PLLCTRL0_RSRVD3 0x00080000 #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 -#define BM_CLKCTRL_PLLCTRL0_RSRVD2 0x00020000 #define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000 -#define BP_CLKCTRL_PLLCTRL0_RSRVD1 0 -#define BM_CLKCTRL_PLLCTRL0_RSRVD1 0x0000FFFF -#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v) \ - (((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1) #define HW_CLKCTRL_PLLCTRL1 (0x00000010) #define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 #define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 -#define BP_CLKCTRL_PLLCTRL1_RSRVD1 16 -#define BM_CLKCTRL_PLLCTRL1_RSRVD1 0x3FFF0000 -#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v) \ - (((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1) #define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 #define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF #define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \ @@ -96,29 +74,15 @@ #define HW_CLKCTRL_CPU_CLR (0x00000028) #define HW_CLKCTRL_CPU_TOG (0x0000002c) -#define BP_CLKCTRL_CPU_RSRVD5 30 -#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000 -#define BF_CLKCTRL_CPU_RSRVD5(v) \ - (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5) #define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 #define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 -#define BM_CLKCTRL_CPU_RSRVD4 0x08000000 #define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 #define BP_CLKCTRL_CPU_DIV_XTAL 16 #define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 #define BF_CLKCTRL_CPU_DIV_XTAL(v) \ (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) -#define BP_CLKCTRL_CPU_RSRVD3 13 -#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000 -#define BF_CLKCTRL_CPU_RSRVD3(v) \ - (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3) #define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 -#define BM_CLKCTRL_CPU_RSRVD2 0x00000800 #define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 -#define BP_CLKCTRL_CPU_RSRVD1 6 -#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0 -#define BF_CLKCTRL_CPU_RSRVD1(v) \ - (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1) #define BP_CLKCTRL_CPU_DIV_CPU 0 #define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F #define BF_CLKCTRL_CPU_DIV_CPU(v) \ @@ -129,10 +93,6 @@ #define HW_CLKCTRL_HBUS_CLR (0x00000038) #define HW_CLKCTRL_HBUS_TOG (0x0000003c) -#define BP_CLKCTRL_HBUS_RSRVD4 30 -#define BM_CLKCTRL_HBUS_RSRVD4 0xC0000000 -#define BF_CLKCTRL_HBUS_RSRVD4(v) \ - (((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4) #define BM_CLKCTRL_HBUS_BUSY 0x20000000 #define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000 #define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000 @@ -143,7 +103,6 @@ #define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 #define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 #define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000 -#define BM_CLKCTRL_HBUS_RSRVD2 0x00080000 #define BP_CLKCTRL_HBUS_SLOW_DIV 16 #define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 #define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ @@ -154,10 +113,6 @@ #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 -#define BP_CLKCTRL_HBUS_RSRVD1 6 -#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0 -#define BF_CLKCTRL_HBUS_RSRVD1(v) \ - (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1) #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 #define BP_CLKCTRL_HBUS_DIV 0 #define BM_CLKCTRL_HBUS_DIV 0x0000001F @@ -167,10 +122,6 @@ #define HW_CLKCTRL_XBUS (0x00000040) #define BM_CLKCTRL_XBUS_BUSY 0x80000000 -#define BP_CLKCTRL_XBUS_RSRVD1 11 -#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF800 -#define BF_CLKCTRL_XBUS_RSRVD1(v) \ - (((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1) #define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 #define BP_CLKCTRL_XBUS_DIV 0 #define BM_CLKCTRL_XBUS_DIV 0x000003FF @@ -192,10 +143,6 @@ #define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000 #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 -#define BP_CLKCTRL_XTAL_RSRVD1 2 -#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC -#define BF_CLKCTRL_XTAL_RSRVD1(v) \ - (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1) #define BP_CLKCTRL_XTAL_DIV_UART 0 #define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 #define BF_CLKCTRL_XTAL_DIV_UART(v) \ @@ -205,12 +152,7 @@ #define BP_CLKCTRL_PIX_CLKGATE 31 #define BM_CLKCTRL_PIX_CLKGATE 0x80000000 -#define BM_CLKCTRL_PIX_RSRVD2 0x40000000 #define BM_CLKCTRL_PIX_BUSY 0x20000000 -#define BP_CLKCTRL_PIX_RSRVD1 13 -#define BM_CLKCTRL_PIX_RSRVD1 0x1FFFE000 -#define BF_CLKCTRL_PIX_RSRVD1(v) \ - (((v) << 13) & BM_CLKCTRL_PIX_RSRVD1) #define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000 #define BP_CLKCTRL_PIX_DIV 0 #define BM_CLKCTRL_PIX_DIV 0x00000FFF @@ -221,12 +163,7 @@ #define BP_CLKCTRL_SSP_CLKGATE 31 #define BM_CLKCTRL_SSP_CLKGATE 0x80000000 -#define BM_CLKCTRL_SSP_RSRVD2 0x40000000 #define BM_CLKCTRL_SSP_BUSY 0x20000000 -#define BP_CLKCTRL_SSP_RSRVD1 10 -#define BM_CLKCTRL_SSP_RSRVD1 0x1FFFFC00 -#define BF_CLKCTRL_SSP_RSRVD1(v) \ - (((v) << 10) & BM_CLKCTRL_SSP_RSRVD1) #define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200 #define BP_CLKCTRL_SSP_DIV 0 #define BM_CLKCTRL_SSP_DIV 0x000001FF @@ -237,12 +174,7 @@ #define BP_CLKCTRL_GPMI_CLKGATE 31 #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 -#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000 #define BM_CLKCTRL_GPMI_BUSY 0x20000000 -#define BP_CLKCTRL_GPMI_RSRVD1 11 -#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800 -#define BF_CLKCTRL_GPMI_RSRVD1(v) \ - (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1) #define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 #define BP_CLKCTRL_GPMI_DIV 0 #define BM_CLKCTRL_GPMI_DIV 0x000003FF @@ -252,10 +184,6 @@ #define HW_CLKCTRL_SPDIF (0x00000090) #define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 -#define BP_CLKCTRL_SPDIF_RSRVD 0 -#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF -#define BF_CLKCTRL_SPDIF_RSRVD(v) \ - (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD) #define HW_CLKCTRL_EMI (0x000000a0) @@ -266,24 +194,12 @@ #define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 #define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 #define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 -#define BP_CLKCTRL_EMI_RSRVD3 18 -#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000 -#define BF_CLKCTRL_EMI_RSRVD3(v) \ - (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3) #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 -#define BP_CLKCTRL_EMI_RSRVD2 12 -#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000 -#define BF_CLKCTRL_EMI_RSRVD2(v) \ - (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2) #define BP_CLKCTRL_EMI_DIV_XTAL 8 #define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 #define BF_CLKCTRL_EMI_DIV_XTAL(v) \ (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) -#define BP_CLKCTRL_EMI_RSRVD1 6 -#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0 -#define BF_CLKCTRL_EMI_RSRVD1(v) \ - (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1) #define BP_CLKCTRL_EMI_DIV_EMI 0 #define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F #define BF_CLKCTRL_EMI_DIV_EMI(v) \ @@ -292,22 +208,13 @@ #define HW_CLKCTRL_IR (0x000000b0) #define BM_CLKCTRL_IR_CLKGATE 0x80000000 -#define BM_CLKCTRL_IR_RSRVD3 0x40000000 #define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 #define BM_CLKCTRL_IR_IR_BUSY 0x10000000 #define BM_CLKCTRL_IR_IROV_BUSY 0x08000000 -#define BP_CLKCTRL_IR_RSRVD2 25 -#define BM_CLKCTRL_IR_RSRVD2 0x06000000 -#define BF_CLKCTRL_IR_RSRVD2(v) \ - (((v) << 25) & BM_CLKCTRL_IR_RSRVD2) #define BP_CLKCTRL_IR_IROV_DIV 16 #define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000 #define BF_CLKCTRL_IR_IROV_DIV(v) \ (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV) -#define BP_CLKCTRL_IR_RSRVD1 10 -#define BM_CLKCTRL_IR_RSRVD1 0x0000FC00 -#define BF_CLKCTRL_IR_RSRVD1(v) \ - (((v) << 10) & BM_CLKCTRL_IR_RSRVD1) #define BP_CLKCTRL_IR_IR_DIV 0 #define BM_CLKCTRL_IR_IR_DIV 0x000003FF #define BF_CLKCTRL_IR_IR_DIV(v) \ @@ -316,12 +223,7 @@ #define HW_CLKCTRL_SAIF (0x000000c0) #define BM_CLKCTRL_SAIF_CLKGATE 0x80000000 -#define BM_CLKCTRL_SAIF_RSRVD2 0x40000000 #define BM_CLKCTRL_SAIF_BUSY 0x20000000 -#define BP_CLKCTRL_SAIF_RSRVD1 17 -#define BM_CLKCTRL_SAIF_RSRVD1 0x1FFE0000 -#define BF_CLKCTRL_SAIF_RSRVD1(v) \ - (((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1) #define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000 #define BP_CLKCTRL_SAIF_DIV 0 #define BM_CLKCTRL_SAIF_DIV 0x0000FFFF @@ -332,20 +234,11 @@ #define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000 #define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000 -#define BP_CLKCTRL_TV_RSRVD 0 -#define BM_CLKCTRL_TV_RSRVD 0x3FFFFFFF -#define BF_CLKCTRL_TV_RSRVD(v) \ - (((v) << 0) & BM_CLKCTRL_TV_RSRVD) #define HW_CLKCTRL_ETM (0x000000e0) #define BM_CLKCTRL_ETM_CLKGATE 0x80000000 -#define BM_CLKCTRL_ETM_RSRVD2 0x40000000 #define BM_CLKCTRL_ETM_BUSY 0x20000000 -#define BP_CLKCTRL_ETM_RSRVD1 7 -#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF80 -#define BF_CLKCTRL_ETM_RSRVD1(v) \ - (((v) << 7) & BM_CLKCTRL_ETM_RSRVD1) #define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040 #define BP_CLKCTRL_ETM_DIV 0 #define BM_CLKCTRL_ETM_DIV 0x0000003F @@ -393,36 +286,23 @@ #define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000 #define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000 -#define BP_CLKCTRL_FRAC1_RSRVD1 0 -#define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF -#define BF_CLKCTRL_FRAC1_RSRVD1(v) \ - (((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1) #define HW_CLKCTRL_CLKSEQ (0x00000110) #define HW_CLKCTRL_CLKSEQ_SET (0x00000114) #define HW_CLKCTRL_CLKSEQ_CLR (0x00000118) #define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c) -#define BP_CLKCTRL_CLKSEQ_RSRVD1 9 -#define BM_CLKCTRL_CLKSEQ_RSRVD1 0xFFFFFE00 -#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \ - (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1) #define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080 #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040 #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020 #define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010 #define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008 -#define BM_CLKCTRL_CLKSEQ_RSRVD0 0x00000004 #define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001 #define HW_CLKCTRL_RESET (0x00000120) -#define BP_CLKCTRL_RESET_RSRVD 2 -#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFFC -#define BF_CLKCTRL_RESET_RSRVD(v) \ - (((v) << 2) & BM_CLKCTRL_RESET_RSRVD) #define BM_CLKCTRL_RESET_CHIP 0x00000002 #define BM_CLKCTRL_RESET_DIG 0x00000001 @@ -432,10 +312,6 @@ #define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 #define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) -#define BP_CLKCTRL_STATUS_RSRVD 0 -#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF -#define BF_CLKCTRL_STATUS_RSRVD(v) \ - (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD) #define HW_CLKCTRL_VERSION (0x00000140) -- cgit v0.10.2 From 44b4ca32fe09ae3844e9e2d12fb7371b3edeee14 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 27 Jan 2011 12:38:01 +0100 Subject: ARM i.MX28: remove reserved register defines Signed-off-by: Sascha Hauer Acked-by: Shawn Guo Acked-by: Wolfram Sang diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h index 661df18..7d1b061 100644 --- a/arch/arm/mach-mxs/regs-clkctrl-mx28.h +++ b/arch/arm/mach-mxs/regs-clkctrl-mx28.h @@ -31,10 +31,6 @@ #define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008) #define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c) -#define BP_CLKCTRL_PLL0CTRL0_RSRVD6 30 -#define BM_CLKCTRL_PLL0CTRL0_RSRVD6 0xC0000000 -#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \ - (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6) #define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28 #define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000 #define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \ @@ -43,10 +39,6 @@ #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3 -#define BP_CLKCTRL_PLL0CTRL0_RSRVD5 26 -#define BM_CLKCTRL_PLL0CTRL0_RSRVD5 0x0C000000 -#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v) \ - (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5) #define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24 #define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000 #define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \ @@ -55,10 +47,6 @@ #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3 -#define BP_CLKCTRL_PLL0CTRL0_RSRVD4 22 -#define BM_CLKCTRL_PLL0CTRL0_RSRVD4 0x00C00000 -#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v) \ - (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4) #define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20 #define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000 #define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \ @@ -67,22 +55,13 @@ #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3 -#define BM_CLKCTRL_PLL0CTRL0_RSRVD3 0x00080000 #define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000 #define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000 -#define BP_CLKCTRL_PLL0CTRL0_RSRVD1 0 -#define BM_CLKCTRL_PLL0CTRL0_RSRVD1 0x0001FFFF -#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v) \ - (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1) #define HW_CLKCTRL_PLL0CTRL1 (0x00000010) #define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000 #define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000 -#define BP_CLKCTRL_PLL0CTRL1_RSRVD1 16 -#define BM_CLKCTRL_PLL0CTRL1_RSRVD1 0x3FFF0000 -#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v) \ - (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1) #define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0 #define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF #define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \ @@ -94,7 +73,6 @@ #define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c) #define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000 -#define BM_CLKCTRL_PLL1CTRL0_RSRVD6 0x40000000 #define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28 #define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000 #define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \ @@ -103,10 +81,6 @@ #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3 -#define BP_CLKCTRL_PLL1CTRL0_RSRVD5 26 -#define BM_CLKCTRL_PLL1CTRL0_RSRVD5 0x0C000000 -#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v) \ - (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5) #define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24 #define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000 #define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \ @@ -115,10 +89,6 @@ #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3 -#define BP_CLKCTRL_PLL1CTRL0_RSRVD4 22 -#define BM_CLKCTRL_PLL1CTRL0_RSRVD4 0x00C00000 -#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v) \ - (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4) #define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20 #define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000 #define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \ @@ -127,22 +97,13 @@ #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3 -#define BM_CLKCTRL_PLL1CTRL0_RSRVD3 0x00080000 #define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000 #define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000 -#define BP_CLKCTRL_PLL1CTRL0_RSRVD1 0 -#define BM_CLKCTRL_PLL1CTRL0_RSRVD1 0x0001FFFF -#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v) \ - (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1) #define HW_CLKCTRL_PLL1CTRL1 (0x00000030) #define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000 #define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000 -#define BP_CLKCTRL_PLL1CTRL1_RSRVD1 16 -#define BM_CLKCTRL_PLL1CTRL1_RSRVD1 0x3FFF0000 -#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v) \ - (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1) #define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0 #define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF #define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \ @@ -154,51 +115,31 @@ #define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c) #define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000 -#define BM_CLKCTRL_PLL2CTRL0_RSRVD3 0x40000000 #define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28 #define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000 #define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \ (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL) -#define BM_CLKCTRL_PLL2CTRL0_RSRVD2 0x08000000 #define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000 #define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24 #define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000 #define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \ (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL) #define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000 -#define BP_CLKCTRL_PLL2CTRL0_RSRVD1 0 -#define BM_CLKCTRL_PLL2CTRL0_RSRVD1 0x007FFFFF -#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v) \ - (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1) #define HW_CLKCTRL_CPU (0x00000050) #define HW_CLKCTRL_CPU_SET (0x00000054) #define HW_CLKCTRL_CPU_CLR (0x00000058) #define HW_CLKCTRL_CPU_TOG (0x0000005c) -#define BP_CLKCTRL_CPU_RSRVD5 30 -#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000 -#define BF_CLKCTRL_CPU_RSRVD5(v) \ - (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5) #define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 #define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 -#define BM_CLKCTRL_CPU_RSRVD4 0x08000000 #define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 #define BP_CLKCTRL_CPU_DIV_XTAL 16 #define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 #define BF_CLKCTRL_CPU_DIV_XTAL(v) \ (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) -#define BP_CLKCTRL_CPU_RSRVD3 13 -#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000 -#define BF_CLKCTRL_CPU_RSRVD3(v) \ - (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3) #define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 -#define BM_CLKCTRL_CPU_RSRVD2 0x00000800 #define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 -#define BP_CLKCTRL_CPU_RSRVD1 6 -#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0 -#define BF_CLKCTRL_CPU_RSRVD1(v) \ - (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1) #define BP_CLKCTRL_CPU_DIV_CPU 0 #define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F #define BF_CLKCTRL_CPU_DIV_CPU(v) \ @@ -212,7 +153,6 @@ #define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000 #define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000 #define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000 -#define BM_CLKCTRL_HBUS_RSRVD2 0x10000000 #define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000 #define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 #define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 @@ -232,10 +172,6 @@ #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 -#define BP_CLKCTRL_HBUS_RSRVD1 6 -#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0 -#define BF_CLKCTRL_HBUS_RSRVD1(v) \ - (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1) #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 #define BP_CLKCTRL_HBUS_DIV 0 #define BM_CLKCTRL_HBUS_DIV 0x0000001F @@ -245,10 +181,6 @@ #define HW_CLKCTRL_XBUS (0x00000070) #define BM_CLKCTRL_XBUS_BUSY 0x80000000 -#define BP_CLKCTRL_XBUS_RSRVD1 12 -#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF000 -#define BF_CLKCTRL_XBUS_RSRVD1(v) \ - (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1) #define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800 #define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 #define BP_CLKCTRL_XBUS_DIV 0 @@ -263,19 +195,10 @@ #define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 #define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 -#define BM_CLKCTRL_XTAL_RSRVD3 0x40000000 #define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 -#define BP_CLKCTRL_XTAL_RSRVD2 27 -#define BM_CLKCTRL_XTAL_RSRVD2 0x18000000 -#define BF_CLKCTRL_XTAL_RSRVD2(v) \ - (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2) #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 -#define BP_CLKCTRL_XTAL_RSRVD1 2 -#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC -#define BF_CLKCTRL_XTAL_RSRVD1(v) \ - (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1) #define BP_CLKCTRL_XTAL_DIV_UART 0 #define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 #define BF_CLKCTRL_XTAL_DIV_UART(v) \ @@ -285,12 +208,7 @@ #define BP_CLKCTRL_SSP0_CLKGATE 31 #define BM_CLKCTRL_SSP0_CLKGATE 0x80000000 -#define BM_CLKCTRL_SSP0_RSRVD2 0x40000000 #define BM_CLKCTRL_SSP0_BUSY 0x20000000 -#define BP_CLKCTRL_SSP0_RSRVD1 10 -#define BM_CLKCTRL_SSP0_RSRVD1 0x1FFFFC00 -#define BF_CLKCTRL_SSP0_RSRVD1(v) \ - (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1) #define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200 #define BP_CLKCTRL_SSP0_DIV 0 #define BM_CLKCTRL_SSP0_DIV 0x000001FF @@ -301,12 +219,7 @@ #define BP_CLKCTRL_SSP1_CLKGATE 31 #define BM_CLKCTRL_SSP1_CLKGATE 0x80000000 -#define BM_CLKCTRL_SSP1_RSRVD2 0x40000000 #define BM_CLKCTRL_SSP1_BUSY 0x20000000 -#define BP_CLKCTRL_SSP1_RSRVD1 10 -#define BM_CLKCTRL_SSP1_RSRVD1 0x1FFFFC00 -#define BF_CLKCTRL_SSP1_RSRVD1(v) \ - (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1) #define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200 #define BP_CLKCTRL_SSP1_DIV 0 #define BM_CLKCTRL_SSP1_DIV 0x000001FF @@ -317,12 +230,7 @@ #define BP_CLKCTRL_SSP2_CLKGATE 31 #define BM_CLKCTRL_SSP2_CLKGATE 0x80000000 -#define BM_CLKCTRL_SSP2_RSRVD2 0x40000000 #define BM_CLKCTRL_SSP2_BUSY 0x20000000 -#define BP_CLKCTRL_SSP2_RSRVD1 10 -#define BM_CLKCTRL_SSP2_RSRVD1 0x1FFFFC00 -#define BF_CLKCTRL_SSP2_RSRVD1(v) \ - (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1) #define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200 #define BP_CLKCTRL_SSP2_DIV 0 #define BM_CLKCTRL_SSP2_DIV 0x000001FF @@ -333,12 +241,7 @@ #define BP_CLKCTRL_SSP3_CLKGATE 31 #define BM_CLKCTRL_SSP3_CLKGATE 0x80000000 -#define BM_CLKCTRL_SSP3_RSRVD2 0x40000000 #define BM_CLKCTRL_SSP3_BUSY 0x20000000 -#define BP_CLKCTRL_SSP3_RSRVD1 10 -#define BM_CLKCTRL_SSP3_RSRVD1 0x1FFFFC00 -#define BF_CLKCTRL_SSP3_RSRVD1(v) \ - (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1) #define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200 #define BP_CLKCTRL_SSP3_DIV 0 #define BM_CLKCTRL_SSP3_DIV 0x000001FF @@ -349,12 +252,7 @@ #define BP_CLKCTRL_GPMI_CLKGATE 31 #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 -#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000 #define BM_CLKCTRL_GPMI_BUSY 0x20000000 -#define BP_CLKCTRL_GPMI_RSRVD1 11 -#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800 -#define BF_CLKCTRL_GPMI_RSRVD1(v) \ - (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1) #define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 #define BP_CLKCTRL_GPMI_DIV 0 #define BM_CLKCTRL_GPMI_DIV 0x000003FF @@ -365,10 +263,6 @@ #define BP_CLKCTRL_SPDIF_CLKGATE 31 #define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 -#define BP_CLKCTRL_SPDIF_RSRVD 0 -#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF -#define BF_CLKCTRL_SPDIF_RSRVD(v) \ - (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD) #define HW_CLKCTRL_EMI (0x000000f0) @@ -379,24 +273,12 @@ #define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 #define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 #define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 -#define BP_CLKCTRL_EMI_RSRVD3 18 -#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000 -#define BF_CLKCTRL_EMI_RSRVD3(v) \ - (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3) #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 -#define BP_CLKCTRL_EMI_RSRVD2 12 -#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000 -#define BF_CLKCTRL_EMI_RSRVD2(v) \ - (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2) #define BP_CLKCTRL_EMI_DIV_XTAL 8 #define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 #define BF_CLKCTRL_EMI_DIV_XTAL(v) \ (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) -#define BP_CLKCTRL_EMI_RSRVD1 6 -#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0 -#define BF_CLKCTRL_EMI_RSRVD1(v) \ - (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1) #define BP_CLKCTRL_EMI_DIV_EMI 0 #define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F #define BF_CLKCTRL_EMI_DIV_EMI(v) \ @@ -406,12 +288,7 @@ #define BP_CLKCTRL_SAIF0_CLKGATE 31 #define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000 -#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000 #define BM_CLKCTRL_SAIF0_BUSY 0x20000000 -#define BP_CLKCTRL_SAIF0_RSRVD1 17 -#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000 -#define BF_CLKCTRL_SAIF0_RSRVD1(v) \ - (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1) #define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000 #define BP_CLKCTRL_SAIF0_DIV 0 #define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF @@ -422,12 +299,7 @@ #define BP_CLKCTRL_SAIF1_CLKGATE 31 #define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000 -#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000 #define BM_CLKCTRL_SAIF1_BUSY 0x20000000 -#define BP_CLKCTRL_SAIF1_RSRVD1 17 -#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000 -#define BF_CLKCTRL_SAIF1_RSRVD1(v) \ - (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1) #define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000 #define BP_CLKCTRL_SAIF1_DIV 0 #define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF @@ -438,12 +310,7 @@ #define BP_CLKCTRL_DIS_LCDIF_CLKGATE 31 #define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000 -#define BM_CLKCTRL_DIS_LCDIF_RSRVD2 0x40000000 #define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000 -#define BP_CLKCTRL_DIS_LCDIF_RSRVD1 14 -#define BM_CLKCTRL_DIS_LCDIF_RSRVD1 0x1FFFC000 -#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v) \ - (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1) #define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000 #define BP_CLKCTRL_DIS_LCDIF_DIV 0 #define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF @@ -453,12 +320,7 @@ #define HW_CLKCTRL_ETM (0x00000130) #define BM_CLKCTRL_ETM_CLKGATE 0x80000000 -#define BM_CLKCTRL_ETM_RSRVD2 0x40000000 #define BM_CLKCTRL_ETM_BUSY 0x20000000 -#define BP_CLKCTRL_ETM_RSRVD1 8 -#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF00 -#define BF_CLKCTRL_ETM_RSRVD1(v) \ - (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1) #define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080 #define BP_CLKCTRL_ETM_DIV 0 #define BM_CLKCTRL_ETM_DIV 0x0000007F @@ -471,7 +333,6 @@ #define BP_CLKCTRL_ENET_DISABLE 30 #define BM_CLKCTRL_ENET_DISABLE 0x40000000 #define BM_CLKCTRL_ENET_STATUS 0x20000000 -#define BM_CLKCTRL_ENET_RSRVD1 0x10000000 #define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000 #define BP_CLKCTRL_ENET_DIV_TIME 21 #define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000 @@ -493,37 +354,23 @@ #define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000 #define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000 #define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000 -#define BP_CLKCTRL_ENET_RSRVD0 0 -#define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF -#define BF_CLKCTRL_ENET_RSRVD0(v) \ - (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0) #define HW_CLKCTRL_HSADC (0x00000150) -#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000 #define BM_CLKCTRL_HSADC_RESETB 0x40000000 #define BP_CLKCTRL_HSADC_FREQDIV 28 #define BM_CLKCTRL_HSADC_FREQDIV 0x30000000 #define BF_CLKCTRL_HSADC_FREQDIV(v) \ (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV) -#define BP_CLKCTRL_HSADC_RSRVD1 0 -#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF -#define BF_CLKCTRL_HSADC_RSRVD1(v) \ - (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1) #define HW_CLKCTRL_FLEXCAN (0x00000160) -#define BM_CLKCTRL_FLEXCAN_RSRVD2 0x80000000 #define BP_CLKCTRL_FLEXCAN_STOP_CAN0 30 #define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000 #define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000 #define BP_CLKCTRL_FLEXCAN_STOP_CAN1 28 #define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000 #define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000 -#define BP_CLKCTRL_FLEXCAN_RSRVD1 0 -#define BM_CLKCTRL_FLEXCAN_RSRVD1 0x07FFFFFF -#define BF_CLKCTRL_FLEXCAN_RSRVD1(v) \ - (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1) #define HW_CLKCTRL_FRAC0 (0x000001b0) #define HW_CLKCTRL_FRAC0_SET (0x000001b4) @@ -564,10 +411,6 @@ #define HW_CLKCTRL_FRAC1_CLR (0x000001c8) #define HW_CLKCTRL_FRAC1_TOG (0x000001cc) -#define BP_CLKCTRL_FRAC1_RSRVD2 24 -#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000 -#define BF_CLKCTRL_FRAC1_RSRVD2(v) \ - (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2) #define BP_CLKCTRL_FRAC1_CLKGATEGPMI 23 #define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000 #define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000 @@ -595,22 +438,10 @@ #define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8) #define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc) -#define BP_CLKCTRL_CLKSEQ_RSRVD0 19 -#define BM_CLKCTRL_CLKSEQ_RSRVD0 0xFFF80000 -#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \ - (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0) #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000 -#define BP_CLKCTRL_CLKSEQ_RSRVD1 15 -#define BM_CLKCTRL_CLKSEQ_RSRVD1 0x00038000 -#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \ - (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1) #define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000 #define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1 #define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0 -#define BP_CLKCTRL_CLKSEQ_RSRVD2 9 -#define BM_CLKCTRL_CLKSEQ_RSRVD2 0x00003E00 -#define BF_CLKCTRL_CLKSEQ_RSRVD2(v) \ - (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2) #define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080 #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040 @@ -623,10 +454,6 @@ #define HW_CLKCTRL_RESET (0x000001e0) -#define BP_CLKCTRL_RESET_RSRVD 6 -#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFC0 -#define BF_CLKCTRL_RESET_RSRVD(v) \ - (((v) << 6) & BM_CLKCTRL_RESET_RSRVD) #define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020 #define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010 #define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008 @@ -640,10 +467,6 @@ #define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 #define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) -#define BP_CLKCTRL_STATUS_RSRVD 0 -#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF -#define BF_CLKCTRL_STATUS_RSRVD(v) \ - (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD) #define HW_CLKCTRL_VERSION (0x00000200) -- cgit v0.10.2 From 4404117d745f2251c5d3c739c50f617e755dbe12 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 27 Jan 2011 15:00:19 -0200 Subject: ARM: mach-mx3/mach-mx31_3ds: Remove unnecessary function for IO mapping Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 0d65db8..2f41430 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -320,14 +320,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -/* - * Set up static virtual mappings. - */ -static void __init mx31_3ds_map_io(void) -{ - mx31_map_io(); -} - /*! * Board specific initialization. */ @@ -382,7 +374,7 @@ static struct sys_timer mx31_3ds_timer = { MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") /* Maintainer: Freescale Semiconductor, Inc. */ .boot_params = MX3x_PHYS_OFFSET + 0x100, - .map_io = mx31_3ds_map_io, + .map_io = mx31_map_io, .init_irq = mx31_init_irq, .init_machine = mxc_board_init, .timer = &mx31_3ds_timer, -- cgit v0.10.2 From 039c4644b49ea707a2159c22f638f4f1c0144c69 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 31 Jan 2011 17:00:24 +0100 Subject: plat-mxc: Provide irq_chip name for GPIO IRQs Signed-off-by: Alexander Stein Signed-off-by: Sascha Hauer diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index d17b3c9..e396df8 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -233,6 +233,7 @@ static int gpio_set_wake_irq(struct irq_data *d, u32 enable) } static struct irq_chip gpio_irq_chip = { + .name = "GPIO", .irq_ack = gpio_ack_irq, .irq_mask = gpio_mask_irq, .irq_unmask = gpio_unmask_irq, -- cgit v0.10.2 From 67f2a87f92716c3126415e114af57164736bbca5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 25 Jan 2011 13:08:33 -0200 Subject: ARM: mach-mx5: Fix build for mx53_loco and mx53_smd Commit 816ad74 (ARM: i.MX53: Add full iomux support for mx53) renamed some of the pad names. Make the changes accordingly so that mx53_loco and mx53_cmd can build without errors. Signed-off-by: Fabio Estevam Acked-by: Richard Zhao Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c index d1348e0..dadc856 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c @@ -39,20 +39,21 @@ #define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) static iomux_v3_cfg_t mx53_loco_pads[] = { - MX53_PAD_CSI0_D10__UART1_TXD, - MX53_PAD_CSI0_D11__UART1_RXD, - MX53_PAD_ATA_DIOW__UART1_TXD, - MX53_PAD_ATA_DMACK__UART1_RXD, - - MX53_PAD_ATA_BUFFER_EN__UART2_RXD, - MX53_PAD_ATA_DMARQ__UART2_TXD, - MX53_PAD_ATA_DIOR__UART2_RTS, - MX53_PAD_ATA_INTRQ__UART2_CTS, - - MX53_PAD_ATA_CS_0__UART3_TXD, - MX53_PAD_ATA_CS_1__UART3_RXD, - MX53_PAD_ATA_DA_1__UART3_CTS, - MX53_PAD_ATA_DA_2__UART3_RTS, + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, + MX53_PAD_PATA_DIOW__UART1_TXD_MUX, + MX53_PAD_PATA_DMACK__UART1_RXD_MUX, + + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, + MX53_PAD_PATA_DIOR__UART2_RTS, + MX53_PAD_PATA_INTRQ__UART2_CTS, + + MX53_PAD_PATA_CS_0__UART3_TXD_MUX, + MX53_PAD_PATA_CS_1__UART3_RXD_MUX, + MX53_PAD_PATA_DA_1__UART3_CTS, + MX53_PAD_PATA_DA_2__UART3_RTS, + }; static const struct imxuart_platform_data mx53_loco_uart_data __initconst = { diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c index 7970f7a..06070c5 100644 --- a/arch/arm/mach-mx5/board-mx53_smd.c +++ b/arch/arm/mach-mx5/board-mx53_smd.c @@ -39,20 +39,20 @@ #define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) static iomux_v3_cfg_t mx53_smd_pads[] = { - MX53_PAD_CSI0_D10__UART1_TXD, - MX53_PAD_CSI0_D11__UART1_RXD, - MX53_PAD_ATA_DIOW__UART1_TXD, - MX53_PAD_ATA_DMACK__UART1_RXD, - - MX53_PAD_ATA_BUFFER_EN__UART2_RXD, - MX53_PAD_ATA_DMARQ__UART2_TXD, - MX53_PAD_ATA_DIOR__UART2_RTS, - MX53_PAD_ATA_INTRQ__UART2_CTS, - - MX53_PAD_ATA_CS_0__UART3_TXD, - MX53_PAD_ATA_CS_1__UART3_RXD, - MX53_PAD_ATA_DA_1__UART3_CTS, - MX53_PAD_ATA_DA_2__UART3_RTS, + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, + MX53_PAD_PATA_DIOW__UART1_TXD_MUX, + MX53_PAD_PATA_DMACK__UART1_RXD_MUX, + + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, + MX53_PAD_PATA_DIOR__UART2_RTS, + MX53_PAD_PATA_INTRQ__UART2_CTS, + + MX53_PAD_PATA_CS_0__UART3_TXD_MUX, + MX53_PAD_PATA_CS_1__UART3_RXD_MUX, + MX53_PAD_PATA_DA_1__UART3_CTS, + MX53_PAD_PATA_DA_2__UART3_RTS, }; static const struct imxuart_platform_data mx53_smd_uart_data __initconst = { -- cgit v0.10.2 From 528f65271f24d1fe9b46065e0fef9571698bd78c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 25 Jan 2011 13:08:34 -0200 Subject: ARM: mach-mx5/board-mx53_loco: Make UART1 functional Fix IOMUX settings for UART1 and make UART1 functional. Signed-off-by: Fabio Estevam Acked-by: Richard Zhao Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c index dadc856..cba4cd5 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c @@ -41,8 +41,6 @@ static iomux_v3_cfg_t mx53_loco_pads[] = { MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, - MX53_PAD_PATA_DIOW__UART1_TXD_MUX, - MX53_PAD_PATA_DMACK__UART1_RXD_MUX, MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, @@ -62,7 +60,7 @@ static const struct imxuart_platform_data mx53_loco_uart_data __initconst = { static inline void mx53_loco_init_uart(void) { - imx53_add_imx_uart(0, &mx53_loco_uart_data); + imx53_add_imx_uart(0, NULL); imx53_add_imx_uart(1, &mx53_loco_uart_data); imx53_add_imx_uart(2, &mx53_loco_uart_data); } -- cgit v0.10.2 From abc1813dc0285353d9ce387b90ffce8acc26227e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 25 Jan 2011 13:08:35 -0200 Subject: ARM: mach-mx5/board-mx53_loco: Remove unused UARTs On mx53_loco only UART1 is used and its signals go to connector J16. Remove UART2 and UART3 as they are not used on this board. Signed-off-by: Fabio Estevam Acked-by: Richard Zhao Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c index cba4cd5..3aefd6d 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c @@ -41,30 +41,8 @@ static iomux_v3_cfg_t mx53_loco_pads[] = { MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, - - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, - MX53_PAD_PATA_DIOR__UART2_RTS, - MX53_PAD_PATA_INTRQ__UART2_CTS, - - MX53_PAD_PATA_CS_0__UART3_TXD_MUX, - MX53_PAD_PATA_CS_1__UART3_RXD_MUX, - MX53_PAD_PATA_DA_1__UART3_CTS, - MX53_PAD_PATA_DA_2__UART3_RTS, - -}; - -static const struct imxuart_platform_data mx53_loco_uart_data __initconst = { - .flags = IMXUART_HAVE_RTSCTS, }; -static inline void mx53_loco_init_uart(void) -{ - imx53_add_imx_uart(0, NULL); - imx53_add_imx_uart(1, &mx53_loco_uart_data); - imx53_add_imx_uart(2, &mx53_loco_uart_data); -} - static inline void mx53_loco_fec_reset(void) { int ret; @@ -88,7 +66,7 @@ static void __init mx53_loco_board_init(void) { mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads, ARRAY_SIZE(mx53_loco_pads)); - mx53_loco_init_uart(); + imx53_add_imx_uart(0, NULL); mx53_loco_fec_reset(); imx53_add_fec(&mx53_loco_fec_data); } -- cgit v0.10.2 From cdb2daa4ffcb331d08e356ed66b57bd14d105746 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 31 Jan 2011 10:32:27 -0200 Subject: ARM: mx5/board-mx53_smd.c: Make UART1 functional Fix UART1 IOMUX settings and configure UART1 to work with only RX/TX pins. Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c index 06070c5..c7b45d4 100644 --- a/arch/arm/mach-mx5/board-mx53_smd.c +++ b/arch/arm/mach-mx5/board-mx53_smd.c @@ -41,8 +41,6 @@ static iomux_v3_cfg_t mx53_smd_pads[] = { MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, - MX53_PAD_PATA_DIOW__UART1_TXD_MUX, - MX53_PAD_PATA_DMACK__UART1_RXD_MUX, MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, @@ -61,7 +59,7 @@ static const struct imxuart_platform_data mx53_smd_uart_data __initconst = { static inline void mx53_smd_init_uart(void) { - imx53_add_imx_uart(0, &mx53_smd_uart_data); + imx53_add_imx_uart(0, NULL); imx53_add_imx_uart(1, &mx53_smd_uart_data); imx53_add_imx_uart(2, &mx53_smd_uart_data); } -- cgit v0.10.2 From df42c8a720ff2e0d52d187bb1120339e79f58604 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 31 Jan 2011 15:12:54 -0200 Subject: ARM: mx5/board-mx53_evk.c: Make UART1 functional Fix UART1 IOMUX settings and configure UART1 to work with only RX/TX pins. Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c index eba9df0..4978007 100644 --- a/arch/arm/mach-mx5/board-mx53_evk.c +++ b/arch/arm/mach-mx5/board-mx53_evk.c @@ -44,8 +44,6 @@ static iomux_v3_cfg_t mx53_evk_pads[] = { MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, - MX53_PAD_PATA_DIOW__UART1_TXD_MUX, - MX53_PAD_PATA_DMACK__UART1_RXD_MUX, MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, @@ -72,7 +70,7 @@ static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = { static inline void mx53_evk_init_uart(void) { - imx53_add_imx_uart(0, &mx53_evk_uart_pdata); + imx53_add_imx_uart(0, NULL); imx53_add_imx_uart(1, &mx53_evk_uart_pdata); imx53_add_imx_uart(2, &mx53_evk_uart_pdata); } -- cgit v0.10.2 From 6ea038a7771be6652784fd06ad01f44028e3a43c Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 2 Feb 2011 13:50:29 +0100 Subject: ARM: mxs: adjust flexcan clock definition Signed-off-by: Marc Kleine-Budde Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 2f1a990..c9d7951 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -619,8 +619,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("pll2", NULL, pll2_clk) _REGISTER_CLOCK(NULL, "hclk", hbus_clk) _REGISTER_CLOCK(NULL, "xclk", xbus_clk) - _REGISTER_CLOCK(NULL, "can0", can0_clk) - _REGISTER_CLOCK(NULL, "can1", can1_clk) + _REGISTER_CLOCK("flexcan.0", NULL, can0_clk) + _REGISTER_CLOCK("flexcan.1", NULL, can1_clk) _REGISTER_CLOCK(NULL, "usb0", usb0_clk) _REGISTER_CLOCK(NULL, "usb1", usb1_clk) _REGISTER_CLOCK(NULL, "pwm", pwm_clk) -- cgit v0.10.2 From 22cbba1b82de458028f4aa270e88492b622c1ea8 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 2 Feb 2011 13:50:30 +0100 Subject: ARM: mxs: dynamically register flexcan devices for mx28 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Marc Kleine-Budde Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h index 1ab7bf0..3b18304 100644 --- a/arch/arm/mach-mxs/devices-mx28.h +++ b/arch/arm/mach-mxs/devices-mx28.h @@ -26,3 +26,9 @@ extern const struct mxs_auart_data mx28_auart_data[] __initconst; extern const struct mxs_fec_data mx28_fec_data[] __initconst; #define mx28_add_fec(id, pdata) \ mxs_add_fec(&mx28_fec_data[id], pdata) + +extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst; +#define mx28_add_flexcan(id, pdata) \ + mxs_add_flexcan(&mx28_flexcan_data[id], pdata) +#define mx28_add_flexcan0(pdata) mx28_add_flexcan(0, pdata) +#define mx28_add_flexcan1(pdata) mx28_add_flexcan(1, pdata) diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig index 3001b75..6c65b67 100644 --- a/arch/arm/mach-mxs/devices/Kconfig +++ b/arch/arm/mach-mxs/devices/Kconfig @@ -7,3 +7,7 @@ config MXS_HAVE_PLATFORM_AUART config MXS_HAVE_PLATFORM_FEC bool + +config MXS_HAVE_PLATFORM_FLEXCAN + select HAVE_CAN_FLEXCAN if CAN + bool diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile index c814d05..a8dc8d5 100644 --- a/arch/arm/mach-mxs/devices/Makefile +++ b/arch/arm/mach-mxs/devices/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o +obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o diff --git a/arch/arm/mach-mxs/devices/platform-flexcan.c b/arch/arm/mach-mxs/devices/platform-flexcan.c new file mode 100644 index 0000000..43a6b4b --- /dev/null +++ b/arch/arm/mach-mxs/devices/platform-flexcan.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2010, 2011 Pengutronix, + * Marc Kleine-Budde + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include +#include + +#define mxs_flexcan_data_entry_single(soc, _id, _hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_CAN ## _hwid, \ + } + +#define mxs_flexcan_data_entry(soc, _id, _hwid, _size) \ + [_id] = mxs_flexcan_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX28 +const struct mxs_flexcan_data mx28_flexcan_data[] __initconst = { +#define mx28_flexcan_data_entry(_id, _hwid) \ + mxs_flexcan_data_entry_single(MX28, _id, _hwid, SZ_8K) + mx28_flexcan_data_entry(0, 0), + mx28_flexcan_data_entry(1, 1), +}; +#endif /* ifdef CONFIG_SOC_IMX28 */ + +struct platform_device *__init mxs_add_flexcan( + const struct mxs_flexcan_data *data, + const struct flexcan_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return mxs_add_platform_device("flexcan", data->id, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h index bed4002..e7aefb4 100644 --- a/arch/arm/mach-mxs/include/mach/devices-common.h +++ b/arch/arm/mach-mxs/include/mach/devices-common.h @@ -51,3 +51,15 @@ struct mxs_fec_data { struct platform_device *__init mxs_add_fec( const struct mxs_fec_data *data, const struct fec_platform_data *pdata); + +/* flexcan */ +#include +struct mxs_flexcan_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init mxs_add_flexcan( + const struct mxs_flexcan_data *data, + const struct flexcan_platform_data *pdata); -- cgit v0.10.2 From 9b1e1ea365b31584fef697a49d03536978d57b50 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 10 Feb 2011 11:07:27 +0100 Subject: ARM: imx/eukrea_mbimx27: fix compile warnings about unused variables MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c index b6d68cf..fa5288018 100644 --- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c @@ -249,7 +249,7 @@ static const struct imxuart_platform_data uart_pdata __initconst = { #define ADS7846_PENDOWN (GPIO_PORTD | 25) -static void ads7846_dev_init(void) +static void __maybe_unused ads7846_dev_init(void) { if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) { printk(KERN_ERR "can't get ads746 pen down GPIO\n"); @@ -268,7 +268,8 @@ static struct ads7846_platform_data ads7846_config __initdata = { .keep_vref_on = 1, }; -static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = { +static struct spi_board_info __maybe_unused + eukrea_mbimx27_spi_board_info[] __initdata = { [0] = { .modalias = "ads7846", .bus_num = 0, -- cgit v0.10.2 From 0be9a196468ad4d03a3f5a1823e02aad5be47968 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 10 Feb 2011 10:56:21 +0100 Subject: ARM: mx3/mx31_3ds: fix compiler warning without CONFIG_USB_ULPI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes: arch/arm/mach-mx3/mach-mx31_3ds.c:249: warning: 'mx31_3ds_host2_init' defined but not used Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 2f41430..dacafcc 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -245,7 +245,7 @@ usbotg_free_reset: return err; } -static int mx31_3ds_host2_init(struct platform_device *pdev) +static int __maybe_unused mx31_3ds_host2_init(struct platform_device *pdev) { int err; -- cgit v0.10.2 From 5836372e8a0ba5cc633f61bc0484ee20c86f4b36 Mon Sep 17 00:00:00 2001 From: David Jander Date: Thu, 10 Feb 2011 10:59:44 +0100 Subject: ARM: imx+mx3: convert to mc13xxx MFD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: David Jander Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index 1643315..49e6a75 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c @@ -216,7 +216,7 @@ static struct regulator_init_data vgen_init = { .consumer_supplies = vgen_consumers, }; -static struct mc13783_regulator_init_data mx27_3ds_regulators[] = { +static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = { { .id = MC13783_REG_VMMC1, .init_data = &vmmc1_init, @@ -227,10 +227,10 @@ static struct mc13783_regulator_init_data mx27_3ds_regulators[] = { }; /* MC13783 */ -static struct mc13783_platform_data mc13783_pdata __initdata = { +static struct mc13xxx_platform_data mc13783_pdata __initdata = { .regulators = mx27_3ds_regulators, .num_regulators = ARRAY_SIZE(mx27_3ds_regulators), - .flags = MC13783_USE_REGULATOR, + .flags = MC13XXX_USE_REGULATOR, }; /* SPI */ diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 5056148..ca20117 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c @@ -252,7 +252,7 @@ static struct regulator_init_data cam_data = { .consumer_supplies = cam_consumers, }; -static struct mc13783_regulator_init_data pcm038_regulators[] = { +static struct mc13xxx_regulator_init_data pcm038_regulators[] = { { .id = MC13783_REG_VCAM, .init_data = &cam_data, @@ -262,11 +262,11 @@ static struct mc13783_regulator_init_data pcm038_regulators[] = { }, }; -static struct mc13783_platform_data pcm038_pmic = { +static struct mc13xxx_platform_data pcm038_pmic = { .regulators = pcm038_regulators, .num_regulators = ARRAY_SIZE(pcm038_regulators), - .flags = MC13783_USE_ADC | MC13783_USE_REGULATOR | - MC13783_USE_TOUCHSCREEN, + .flags = MC13XXX_USE_ADC | MC13XXX_USE_REGULATOR | + MC13XXX_USE_TOUCHSCREEN, }; static struct spi_board_info pcm038_spi_board_info[] __initdata = { diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index dacafcc..6c16c40 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -138,7 +138,7 @@ static struct regulator_init_data gpo_init = { } }; -static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { +static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = { { .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */ .init_data = &pwgtx_init, @@ -156,10 +156,10 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { }; /* MC13783 */ -static struct mc13783_platform_data mc13783_pdata __initdata = { +static struct mc13xxx_platform_data mc13783_pdata __initdata = { .regulators = mx31_3ds_regulators, .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), - .flags = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN, + .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_TOUCHSCREEN }; /* SPI */ diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c index 2c59548..6d0e6c9 100644 --- a/arch/arm/mach-mx3/mach-mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c @@ -274,8 +274,8 @@ static const struct spi_imx_master spi1_pdata __initconst = { .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), }; -static struct mc13783_platform_data mc13783_pdata __initdata = { - .flags = MC13783_USE_RTC | MC13783_USE_TOUCHSCREEN, +static struct mc13xxx_platform_data mc13783_pdata __initdata = { + .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN, }; static struct spi_board_info mc13783_dev __initdata = { diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c index 9e64c66..864aa4f 100644 --- a/arch/arm/mach-mx3/mach-mx31lite.c +++ b/arch/arm/mach-mx3/mach-mx31lite.c @@ -111,9 +111,9 @@ static const struct spi_imx_master spi1_pdata __initconst = { .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), }; -static struct mc13783_platform_data mc13783_pdata __initdata = { - .flags = MC13783_USE_RTC | - MC13783_USE_REGULATOR, +static struct mc13xxx_platform_data mc13783_pdata __initdata = { + .flags = MC13XXX_USE_RTC | + MC13XXX_USE_REGULATOR, }; static struct spi_board_info mc13783_spi_dev __initdata = { diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index 1aa8d65..8fcf991 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -214,7 +214,7 @@ static struct regulator_init_data cam_vreg_data = { .consumer_supplies = cam_consumers, }; -static struct mc13783_regulator_init_data moboard_regulators[] = { +static struct mc13xxx_regulator_init_data moboard_regulators[] = { { .id = MC13783_REG_VMMC1, .init_data = &sdhc_vreg_data, @@ -267,12 +267,12 @@ static struct mc13783_leds_platform_data moboard_leds = { .tc2_period = MC13783_LED_PERIOD_10MS, }; -static struct mc13783_platform_data moboard_pmic = { +static struct mc13xxx_platform_data moboard_pmic = { .regulators = moboard_regulators, .num_regulators = ARRAY_SIZE(moboard_regulators), .leds = &moboard_leds, - .flags = MC13783_USE_REGULATOR | MC13783_USE_RTC | - MC13783_USE_ADC | MC13783_USE_LED, + .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_RTC | + MC13XXX_USE_ADC | MC13XXX_USE_LED, }; static struct spi_board_info moboard_spi_board_info[] __initdata = { -- cgit v0.10.2 From 3dac219615b88010601ee52e7b5fd1c32ef789ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 7 Feb 2011 16:35:19 +0100 Subject: ARM: imx: use .init_early to initialize cpu type and reset address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This used to be done in .map_io which is supposed to only setup the memory mapping. Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index 6cf04da..cabb800 100644 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c @@ -304,9 +304,10 @@ static struct sys_timer eukrea_cpuimx27_timer = { }; MACHINE_START(CPUIMX27, "EUKREA CPUIMX27") - .boot_params = MX27_PHYS_OFFSET + 0x100, - .map_io = mx27_map_io, - .init_irq = mx27_init_irq, - .init_machine = eukrea_cpuimx27_init, - .timer = &eukrea_cpuimx27_timer, + .boot_params = MX27_PHYS_OFFSET + 0x100, + .map_io = mx27_map_io, + .init_early = imx27_init_early, + .init_irq = mx27_init_irq, + .timer = &eukrea_cpuimx27_timer, + .init_machine = eukrea_cpuimx27_init, MACHINE_END diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c index eb395ab..439167d 100644 --- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c +++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c @@ -153,9 +153,10 @@ static struct sys_timer eukrea_cpuimx25_timer = { MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25") /* Maintainer: Eukrea Electromatique */ - .boot_params = MX25_PHYS_OFFSET + 0x100, - .map_io = mx25_map_io, - .init_irq = mx25_init_irq, - .init_machine = eukrea_cpuimx25_init, - .timer = &eukrea_cpuimx25_timer, + .boot_params = MX25_PHYS_OFFSET + 0x100, + .map_io = mx25_map_io, + .init_early = imx25_init_early, + .init_irq = mx25_init_irq, + .timer = &eukrea_cpuimx25_timer, + .init_machine = eukrea_cpuimx25_init, MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c index 40a3666..494723b 100644 --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c @@ -251,9 +251,10 @@ static struct sys_timer visstrim_m10_timer = { }; MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10") - .boot_params = MX27_PHYS_OFFSET + 0x100, - .map_io = mx27_map_io, - .init_irq = mx27_init_irq, - .init_machine = visstrim_m10_board_init, - .timer = &visstrim_m10_timer, + .boot_params = MX27_PHYS_OFFSET + 0x100, + .map_io = mx27_map_io, + .init_early = imx27_init_early, + .init_irq = mx27_init_irq, + .timer = &visstrim_m10_timer, + .init_machine = visstrim_m10_board_init, MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c index d099ea6..9be6cd6 100644 --- a/arch/arm/mach-imx/mach-imx27ipcam.c +++ b/arch/arm/mach-imx/mach-imx27ipcam.c @@ -69,9 +69,10 @@ static struct sys_timer mx27ipcam_timer = { MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM") /* maintainer: Freescale Semiconductor, Inc. */ - .boot_params = MX27_PHYS_OFFSET + 0x100, - .map_io = mx27_map_io, - .init_irq = mx27_init_irq, - .init_machine = mx27ipcam_init, - .timer = &mx27ipcam_timer, + .boot_params = MX27_PHYS_OFFSET + 0x100, + .map_io = mx27_map_io, + .init_early = imx27_init_early, + .init_irq = mx27_init_irq, + .timer = &mx27ipcam_timer, + .init_machine = mx27ipcam_init, MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c index 3a1202e..8411405 100644 --- a/arch/arm/mach-imx/mach-imx27lite.c +++ b/arch/arm/mach-imx/mach-imx27lite.c @@ -75,9 +75,10 @@ static struct sys_timer mx27lite_timer = { }; MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") - .boot_params = MX27_PHYS_OFFSET + 0x100, - .map_io = mx27_map_io, - .init_irq = mx27_init_irq, - .init_machine = mx27lite_init, - .timer = &mx27lite_timer, + .boot_params = MX27_PHYS_OFFSET + 0x100, + .map_io = mx27_map_io, + .init_early = imx27_init_early, + .init_irq = mx27_init_irq, + .timer = &mx27lite_timer, + .init_machine = mx27lite_init, MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c index 1f446e5..47cf56a 100644 --- a/arch/arm/mach-imx/mach-mx1ads.c +++ b/arch/arm/mach-imx/mach-mx1ads.c @@ -144,17 +144,19 @@ struct sys_timer mx1ads_timer = { MACHINE_START(MX1ADS, "Freescale MX1ADS") /* Maintainer: Sascha Hauer, Pengutronix */ - .boot_params = MX1_PHYS_OFFSET + 0x100, - .map_io = mx1_map_io, - .init_irq = mx1_init_irq, - .timer = &mx1ads_timer, - .init_machine = mx1ads_init, + .boot_params = MX1_PHYS_OFFSET + 0x100, + .map_io = mx1_map_io, + .init_early = imx1_init_early, + .init_irq = mx1_init_irq, + .timer = &mx1ads_timer, + .init_machine = mx1ads_init, MACHINE_END MACHINE_START(MXLADS, "Freescale MXLADS") - .boot_params = MX1_PHYS_OFFSET + 0x100, - .map_io = mx1_map_io, - .init_irq = mx1_init_irq, - .timer = &mx1ads_timer, - .init_machine = mx1ads_init, + .boot_params = MX1_PHYS_OFFSET + 0x100, + .map_io = mx1_map_io, + .init_early = imx1_init_early, + .init_irq = mx1_init_irq, + .timer = &mx1ads_timer, + .init_machine = mx1ads_init, MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c index 0a37257..fa52a10 100644 --- a/arch/arm/mach-imx/mach-mx21ads.c +++ b/arch/arm/mach-imx/mach-mx21ads.c @@ -304,9 +304,10 @@ static struct sys_timer mx21ads_timer = { MACHINE_START(MX21ADS, "Freescale i.MX21ADS") /* maintainer: Freescale Semiconductor, Inc. */ - .boot_params = MX21_PHYS_OFFSET + 0x100, - .map_io = mx21ads_map_io, - .init_irq = mx21_init_irq, - .init_machine = mx21ads_board_init, - .timer = &mx21ads_timer, + .boot_params = MX21_PHYS_OFFSET + 0x100, + .map_io = mx21ads_map_io, + .init_early = imx21_init_early, + .init_irq = mx21_init_irq, + .timer = &mx21ads_timer, + .init_machine = mx21ads_board_init, MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c index aa76cfd..0c92a80 100644 --- a/arch/arm/mach-imx/mach-mx25_3ds.c +++ b/arch/arm/mach-imx/mach-mx25_3ds.c @@ -226,10 +226,10 @@ static struct sys_timer mx25pdk_timer = { MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)") /* Maintainer: Freescale Semiconductor, Inc. */ - .boot_params = MX25_PHYS_OFFSET + 0x100, - .map_io = mx25_map_io, - .init_irq = mx25_init_irq, - .init_machine = mx25pdk_init, - .timer = &mx25pdk_timer, + .boot_params = MX25_PHYS_OFFSET + 0x100, + .map_io = mx25_map_io, + .init_early = imx25_init_early, + .init_irq = mx25_init_irq, + .timer = &mx25pdk_timer, + .init_machine = mx25pdk_init, MACHINE_END - diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index 49e6a75..4e0e225 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c @@ -295,9 +295,10 @@ static struct sys_timer mx27pdk_timer = { MACHINE_START(MX27_3DS, "Freescale MX27PDK") /* maintainer: Freescale Semiconductor, Inc. */ - .boot_params = MX27_PHYS_OFFSET + 0x100, - .map_io = mx27_map_io, - .init_irq = mx27_init_irq, - .init_machine = mx27pdk_init, - .timer = &mx27pdk_timer, + .boot_params = MX27_PHYS_OFFSET + 0x100, + .map_io = mx27_map_io, + .init_early = imx27_init_early, + .init_irq = mx27_init_irq, + .timer = &mx27pdk_timer, + .init_machine = mx27pdk_init, MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c index b832f96..367d1e4 100644 --- a/arch/arm/mach-imx/mach-mx27ads.c +++ b/arch/arm/mach-imx/mach-mx27ads.c @@ -344,9 +344,10 @@ static void __init mx27ads_map_io(void) MACHINE_START(MX27ADS, "Freescale i.MX27ADS") /* maintainer: Freescale Semiconductor, Inc. */ - .boot_params = MX27_PHYS_OFFSET + 0x100, - .map_io = mx27ads_map_io, - .init_irq = mx27_init_irq, - .init_machine = mx27ads_board_init, - .timer = &mx27ads_timer, + .boot_params = MX27_PHYS_OFFSET + 0x100, + .map_io = mx27ads_map_io, + .init_early = imx27_init_early, + .init_irq = mx27_init_irq, + .timer = &mx27ads_timer, + .init_machine = mx27ads_board_init, MACHINE_END diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c index 4ce71b0..69787c3 100644 --- a/arch/arm/mach-imx/mach-mxt_td60.c +++ b/arch/arm/mach-imx/mach-mxt_td60.c @@ -266,10 +266,10 @@ static struct sys_timer mxt_td60_timer = { MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") /* maintainer: Maxtrack Industrial */ - .boot_params = MX27_PHYS_OFFSET + 0x100, - .map_io = mx27_map_io, - .init_irq = mx27_init_irq, - .init_machine = mxt_td60_board_init, - .timer = &mxt_td60_timer, + .boot_params = MX27_PHYS_OFFSET + 0x100, + .map_io = mx27_map_io, + .init_early = imx27_init_early, + .init_irq = mx27_init_irq, + .timer = &mxt_td60_timer, + .init_machine = mxt_td60_board_init, MACHINE_END - diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index faa4e04..3514178 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -433,10 +433,10 @@ static struct sys_timer pca100_timer = { }; MACHINE_START(PCA100, "phyCARD-i.MX27") - .boot_params = MX27_PHYS_OFFSET + 0x100, - .map_io = mx27_map_io, - .init_irq = mx27_init_irq, - .init_machine = pca100_init, - .timer = &pca100_timer, + .boot_params = MX27_PHYS_OFFSET + 0x100, + .map_io = mx27_map_io, + .init_early = imx27_init_early, + .init_irq = mx27_init_irq, + .init_machine = pca100_init, + .timer = &pca100_timer, MACHINE_END - diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index ca20117..9656ef3 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c @@ -340,9 +340,10 @@ static struct sys_timer pcm038_timer = { }; MACHINE_START(PCM038, "phyCORE-i.MX27") - .boot_params = MX27_PHYS_OFFSET + 0x100, - .map_io = mx27_map_io, - .init_irq = mx27_init_irq, - .init_machine = pcm038_init, - .timer = &pcm038_timer, + .boot_params = MX27_PHYS_OFFSET + 0x100, + .map_io = mx27_map_io, + .init_early = imx27_init_early, + .init_irq = mx27_init_irq, + .timer = &pcm038_timer, + .init_machine = pcm038_init, MACHINE_END diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c index eae878f..dcaee04 100644 --- a/arch/arm/mach-imx/mach-scb9328.c +++ b/arch/arm/mach-imx/mach-scb9328.c @@ -145,10 +145,11 @@ static struct sys_timer scb9328_timer = { }; MACHINE_START(SCB9328, "Synertronixx scb9328") - /* Sascha Hauer */ - .boot_params = 0x08000100, - .map_io = mx1_map_io, - .init_irq = mx1_init_irq, - .timer = &scb9328_timer, - .init_machine = scb9328_init, + /* Sascha Hauer */ + .boot_params = 0x08000100, + .map_io = mx1_map_io, + .init_early = imx1_init_early, + .init_irq = mx1_init_irq, + .timer = &scb9328_timer, + .init_machine = scb9328_init, MACHINE_END diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c index 729ae09..378c61b 100644 --- a/arch/arm/mach-imx/mm-imx1.c +++ b/arch/arm/mach-imx/mm-imx1.c @@ -30,10 +30,13 @@ static struct map_desc imx_io_desc[] __initdata = { void __init mx1_map_io(void) { + iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); +} + +void __init imx1_init_early(void) +{ mxc_set_cpu_type(MXC_CPU_MX1); mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR)); - - iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); } int imx1_register_gpios(void); diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c index e728af8..b6152c6 100644 --- a/arch/arm/mach-imx/mm-imx21.c +++ b/arch/arm/mach-imx/mm-imx21.c @@ -56,10 +56,13 @@ static struct map_desc imx21_io_desc[] __initdata = { */ void __init mx21_map_io(void) { + iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc)); +} + +void __init imx21_init_early(void) +{ mxc_set_cpu_type(MXC_CPU_MX21); mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR)); - - iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc)); } int imx21_register_gpios(void); diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c index 2edec6c..09dd8d4 100644 --- a/arch/arm/mach-imx/mm-imx25.c +++ b/arch/arm/mach-imx/mm-imx25.c @@ -45,11 +45,14 @@ static struct map_desc mx25_io_desc[] __initdata = { */ void __init mx25_map_io(void) { + iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc)); +} + +void __init imx25_init_early(void) +{ mxc_set_cpu_type(MXC_CPU_MX25); mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR)); mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR)); - - iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc)); } int imx25_register_gpios(void); diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c index 374e48b..bcaa3b6 100644 --- a/arch/arm/mach-imx/mm-imx27.c +++ b/arch/arm/mach-imx/mm-imx27.c @@ -56,10 +56,13 @@ static struct map_desc imx27_io_desc[] __initdata = { */ void __init mx27_map_io(void) { + iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc)); +} + +void __init imx27_init_early(void) +{ mxc_set_cpu_type(MXC_CPU_MX27); mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR)); - - iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc)); } int imx27_register_gpios(void); diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index aea2cd3..e4f1de0 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -24,6 +24,10 @@ extern void mx50_map_io(void); extern void mx51_map_io(void); extern void mx53_map_io(void); extern void mxc91231_map_io(void); +extern void imx1_init_early(void); +extern void imx21_init_early(void); +extern void imx25_init_early(void); +extern void imx27_init_early(void); extern void mxc_init_irq(void __iomem *); extern void tzic_init_irq(void __iomem *); extern void mx1_init_irq(void); -- cgit v0.10.2 From 97976e223be3091a91da103358c3c6cffff7db81 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 7 Feb 2011 16:35:20 +0100 Subject: ARM: mx3: use .init_early to initialize cpu type, reset address and iomuxer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This used to be done in .map_io which is supposed to only setup the memory mapping. Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c index 28b6f41..835e2a0 100644 --- a/arch/arm/mach-mx3/mach-armadillo5x0.c +++ b/arch/arm/mach-mx3/mach-armadillo5x0.c @@ -569,9 +569,10 @@ static struct sys_timer armadillo5x0_timer = { MACHINE_START(ARMADILLO5X0, "Armadillo-500") /* Maintainer: Alberto Panizzo */ - .boot_params = MX3x_PHYS_OFFSET + 0x100, - .map_io = mx31_map_io, - .init_irq = mx31_init_irq, - .timer = &armadillo5x0_timer, - .init_machine = armadillo5x0_init, + .boot_params = MX3x_PHYS_OFFSET + 0x100, + .map_io = mx31_map_io, + .init_early = imx31_init_early, + .init_irq = mx31_init_irq, + .timer = &armadillo5x0_timer, + .init_machine = armadillo5x0_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c index 26ae90f..3eedf0f 100644 --- a/arch/arm/mach-mx3/mach-cpuimx35.c +++ b/arch/arm/mach-mx3/mach-cpuimx35.c @@ -184,9 +184,10 @@ struct sys_timer eukrea_cpuimx35_timer = { MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35") /* Maintainer: Eukrea Electromatique */ - .boot_params = MX3x_PHYS_OFFSET + 0x100, - .map_io = mx35_map_io, - .init_irq = mx35_init_irq, - .init_machine = mxc_board_init, - .timer = &eukrea_cpuimx35_timer, + .boot_params = MX3x_PHYS_OFFSET + 0x100, + .map_io = mx35_map_io, + .init_ext3_fs = imx35_init_early, + .init_irq = mx35_init_irq, + .timer = &eukrea_cpuimx35_timer, + .init_machine = mxc_board_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c index a5f3eb2..52b8dd7 100644 --- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c +++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c @@ -274,9 +274,10 @@ static struct sys_timer kzm_timer = { * initialize __mach_desc_KZM_ARM11_01 data structure. */ MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") - .boot_params = MX3x_PHYS_OFFSET + 0x100, - .map_io = kzm_map_io, - .init_irq = mx31_init_irq, - .init_machine = kzm_board_init, - .timer = &kzm_timer, + .boot_params = MX3x_PHYS_OFFSET + 0x100, + .map_io = kzm_map_io, + .init_early = imx31_init_early, + .init_irq = mx31_init_irq, + .timer = &kzm_timer, + .init_machine = kzm_board_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 6c16c40..3d0ded9 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -373,9 +373,10 @@ static struct sys_timer mx31_3ds_timer = { */ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") /* Maintainer: Freescale Semiconductor, Inc. */ - .boot_params = MX3x_PHYS_OFFSET + 0x100, - .map_io = mx31_map_io, - .init_irq = mx31_init_irq, - .init_machine = mxc_board_init, - .timer = &mx31_3ds_timer, + .boot_params = MX3x_PHYS_OFFSET + 0x100, + .map_io = mx31_map_io, + .init_early = imx31_init_early, + .init_irq = mx31_init_irq, + .timer = &mx31_3ds_timer, + .init_machine = mxc_board_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index e40eb6e..787bdc4 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -550,9 +550,10 @@ static struct sys_timer mx31ads_timer = { */ MACHINE_START(MX31ADS, "Freescale MX31ADS") /* Maintainer: Freescale Semiconductor, Inc. */ - .boot_params = MX3x_PHYS_OFFSET + 0x100, - .map_io = mx31ads_map_io, - .init_irq = mx31ads_init_irq, - .init_machine = mxc_board_init, - .timer = &mx31ads_timer, + .boot_params = MX3x_PHYS_OFFSET + 0x100, + .map_io = mx31ads_map_io, + .init_early = imx31_init_early, + .init_irq = mx31ads_init_irq, + .timer = &mx31ads_timer, + .init_machine = mxc_board_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c index 6d0e6c9..1c3f491 100644 --- a/arch/arm/mach-mx3/mach-mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c @@ -347,10 +347,10 @@ static struct sys_timer mx31lilly_timer = { }; MACHINE_START(LILLY1131, "INCO startec LILLY-1131") - .boot_params = MX3x_PHYS_OFFSET + 0x100, - .map_io = mx31_map_io, - .init_irq = mx31_init_irq, - .init_machine = mx31lilly_board_init, - .timer = &mx31lilly_timer, + .boot_params = MX3x_PHYS_OFFSET + 0x100, + .map_io = mx31_map_io, + .init_early = imx31_init_early, + .init_irq = mx31_init_irq, + .timer = &mx31lilly_timer, + .init_machine = mx31lilly_board_init, MACHINE_END - diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c index 864aa4f..01e24b5 100644 --- a/arch/arm/mach-mx3/mach-mx31lite.c +++ b/arch/arm/mach-mx3/mach-mx31lite.c @@ -281,9 +281,10 @@ struct sys_timer mx31lite_timer = { MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") /* Maintainer: Freescale Semiconductor, Inc. */ - .boot_params = MX3x_PHYS_OFFSET + 0x100, - .map_io = mx31lite_map_io, - .init_irq = mx31_init_irq, - .init_machine = mxc_board_init, - .timer = &mx31lite_timer, + .boot_params = MX3x_PHYS_OFFSET + 0x100, + .map_io = mx31lite_map_io, + .init_early = imx31_init_early, + .init_irq = mx31_init_irq, + .timer = &mx31lite_timer, + .init_machine = mxc_board_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index 8fcf991..fd988a0 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -564,10 +564,10 @@ struct sys_timer mx31moboard_timer = { MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") /* Maintainer: Valentin Longchamp, EPFL Mobots group */ - .boot_params = MX3x_PHYS_OFFSET + 0x100, - .map_io = mx31_map_io, - .init_irq = mx31_init_irq, - .init_machine = mxc_board_init, - .timer = &mx31moboard_timer, + .boot_params = MX3x_PHYS_OFFSET + 0x100, + .map_io = mx31_map_io, + .init_early = imx31_init_early, + .init_irq = mx31_init_irq, + .timer = &mx31moboard_timer, + .init_machine = mxc_board_init, MACHINE_END - diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c index b1963f2..c5115dc 100644 --- a/arch/arm/mach-mx3/mach-mx35_3ds.c +++ b/arch/arm/mach-mx3/mach-mx35_3ds.c @@ -193,9 +193,10 @@ struct sys_timer mx35pdk_timer = { MACHINE_START(MX35_3DS, "Freescale MX35PDK") /* Maintainer: Freescale Semiconductor, Inc */ - .boot_params = MX3x_PHYS_OFFSET + 0x100, - .map_io = mx35_map_io, - .init_irq = mx35_init_irq, - .init_machine = mxc_board_init, - .timer = &mx35pdk_timer, + .boot_params = MX3x_PHYS_OFFSET + 0x100, + .map_io = mx35_map_io, + .init_early = imx35_init_early, + .init_irq = mx35_init_irq, + .timer = &mx35pdk_timer, + .init_machine = mxc_board_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c index b752f6b..7d444f7 100644 --- a/arch/arm/mach-mx3/mach-pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c @@ -675,9 +675,10 @@ struct sys_timer pcm037_timer = { MACHINE_START(PCM037, "Phytec Phycore pcm037") /* Maintainer: Pengutronix */ - .boot_params = MX3x_PHYS_OFFSET + 0x100, - .map_io = mx31_map_io, - .init_irq = mx31_init_irq, - .init_machine = mxc_board_init, - .timer = &pcm037_timer, + .boot_params = MX3x_PHYS_OFFSET + 0x100, + .map_io = mx31_map_io, + .init_early = imx31_init_early, + .init_irq = mx31_init_irq, + .timer = &pcm037_timer, + .init_machine = mxc_board_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index a515290f..b03e19d 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -403,10 +403,10 @@ struct sys_timer pcm043_timer = { MACHINE_START(PCM043, "Phytec Phycore pcm043") /* Maintainer: Pengutronix */ - .boot_params = MX3x_PHYS_OFFSET + 0x100, - .map_io = mx35_map_io, - .init_irq = mx35_init_irq, - .init_machine = mxc_board_init, - .timer = &pcm043_timer, + .boot_params = MX3x_PHYS_OFFSET + 0x100, + .map_io = mx35_map_io, + .init_early = imx35_init_early, + .init_irq = mx35_init_irq, + .timer = &pcm043_timer, + .init_machine = mxc_board_init, MACHINE_END - diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c index fd1050c..064f2db 100644 --- a/arch/arm/mach-mx3/mach-qong.c +++ b/arch/arm/mach-mx3/mach-qong.c @@ -270,9 +270,10 @@ static struct sys_timer qong_timer = { MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") /* Maintainer: DENX Software Engineering GmbH */ - .boot_params = MX3x_PHYS_OFFSET + 0x100, - .map_io = mx31_map_io, - .init_irq = mx31_init_irq, - .init_machine = mxc_board_init, - .timer = &qong_timer, + .boot_params = MX3x_PHYS_OFFSET + 0x100, + .map_io = mx31_map_io, + .init_early = imx31_init_early, + .init_irq = mx31_init_irq, + .timer = &qong_timer, + .init_machine = mxc_board_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mach-vpr200.c b/arch/arm/mach-mx3/mach-vpr200.c index 22ec78a..2cf390f 100644 --- a/arch/arm/mach-mx3/mach-vpr200.c +++ b/arch/arm/mach-mx3/mach-vpr200.c @@ -320,8 +320,9 @@ struct sys_timer vpr200_timer = { MACHINE_START(VPR200, "VPR200") /* Maintainer: Creative Product Design */ - .map_io = mx35_map_io, - .init_irq = mx35_init_irq, - .init_machine = vpr200_board_init, - .timer = &vpr200_timer, + .map_io = mx35_map_io, + .init_early = imx35_init_early, + .init_irq = mx35_init_irq, + .timer = &vpr200_timer, + .init_machine = vpr200_board_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c index 47118f7..3387319 100644 --- a/arch/arm/mach-mx3/mm.c +++ b/arch/arm/mach-mx3/mm.c @@ -52,10 +52,13 @@ static struct map_desc mx31_io_desc[] __initdata = { */ void __init mx31_map_io(void) { + iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); +} + +void __init imx31_init_early(void) +{ mxc_set_cpu_type(MXC_CPU_MX31); mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); - - iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); } int imx31_register_gpios(void); @@ -77,11 +80,14 @@ static struct map_desc mx35_io_desc[] __initdata = { void __init mx35_map_io(void) { + iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); +} + +void __init imx35_init_early(void) +{ mxc_set_cpu_type(MXC_CPU_MX35); mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); - - iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); } int imx35_register_gpios(void); diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index e4f1de0..857eebf47 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -28,6 +28,9 @@ extern void imx1_init_early(void); extern void imx21_init_early(void); extern void imx25_init_early(void); extern void imx27_init_early(void); +extern void imx31_init_early(void); +extern void imx35_init_early(void); +extern void imx50_init_early(void); extern void mxc_init_irq(void __iomem *); extern void tzic_init_irq(void __iomem *); extern void mx1_init_irq(void); -- cgit v0.10.2 From ab130421269aec9bf83d8ef5b7ceda80e2619599 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 7 Feb 2011 16:35:21 +0100 Subject: ARM: mx5: use .init_early to initialize cpu type, reset address and iomuxer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This used to be done in .map_io which is supposed to only setup the memory mapping. Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c index f576a97..2d4199d 100644 --- a/arch/arm/mach-mx5/board-cpuimx51.c +++ b/arch/arm/mach-mx5/board-cpuimx51.c @@ -294,7 +294,8 @@ MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module") /* Maintainer: Eric Bénard */ .boot_params = MX51_PHYS_OFFSET + 0x100, .map_io = mx51_map_io, + .init_early = imx51_init_early, .init_irq = mx51_init_irq, - .init_machine = eukrea_cpuimx51_init, .timer = &mxc_timer, + .init_machine = eukrea_cpuimx51_init, MACHINE_END diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c index ad93189..6c3b445 100644 --- a/arch/arm/mach-mx5/board-cpuimx51sd.c +++ b/arch/arm/mach-mx5/board-cpuimx51sd.c @@ -329,7 +329,8 @@ MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD") /* Maintainer: Eric Bénard */ .boot_params = MX51_PHYS_OFFSET + 0x100, .map_io = mx51_map_io, + .init_early = imx51_init_early, .init_irq = mx51_init_irq, - .init_machine = eukrea_cpuimx51sd_init, .timer = &mxc_timer, + .init_machine = eukrea_cpuimx51sd_init, MACHINE_END diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c index 75beef7..dedf7f2 100644 --- a/arch/arm/mach-mx5/board-mx50_rdp.c +++ b/arch/arm/mach-mx5/board-mx50_rdp.c @@ -216,7 +216,8 @@ static struct sys_timer mx50_rdp_timer = { MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform") .map_io = mx50_map_io, + .init_early = imx50_init_early, .init_irq = mx50_init_irq, - .init_machine = mx50_rdp_board_init, .timer = &mx50_rdp_timer, + .init_machine = mx50_rdp_board_init, MACHINE_END diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c index 55d5746..0168470 100644 --- a/arch/arm/mach-mx5/board-mx51_3ds.c +++ b/arch/arm/mach-mx5/board-mx51_3ds.c @@ -168,7 +168,8 @@ MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") /* Maintainer: Freescale Semiconductor, Inc. */ .boot_params = MX51_PHYS_OFFSET + 0x100, .map_io = mx51_map_io, + .init_early = imx51_init_early, .init_irq = mx51_init_irq, - .init_machine = mxc_board_init, .timer = &mxc_timer, + .init_machine = mxc_board_init, MACHINE_END diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index d9d402e..2bd9c9e 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -398,7 +398,8 @@ MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") /* Maintainer: Amit Kucheria */ .boot_params = MX51_PHYS_OFFSET + 0x100, .map_io = mx51_map_io, + .init_early = imx51_init_early, .init_irq = mx51_init_irq, - .init_machine = mxc_board_init, .timer = &mxc_timer, + .init_machine = mxc_board_init, MACHINE_END diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c index e237040..2aac4c5 100644 --- a/arch/arm/mach-mx5/board-mx51_efikamx.c +++ b/arch/arm/mach-mx5/board-mx51_efikamx.c @@ -347,7 +347,8 @@ MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop") /* Maintainer: Amit Kucheria */ .boot_params = MX51_PHYS_OFFSET + 0x100, .map_io = mx51_map_io, + .init_early = imx51_init_early, .init_irq = mx51_init_irq, - .init_machine = mxc_board_init, .timer = &mxc_timer, + .init_machine = mxc_board_init, MACHINE_END diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c index 4978007..8ed316b 100644 --- a/arch/arm/mach-mx5/board-mx53_evk.c +++ b/arch/arm/mach-mx5/board-mx53_evk.c @@ -150,7 +150,8 @@ static struct sys_timer mx53_evk_timer = { MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board") .map_io = mx53_map_io, + .init_early = imx53_init_early, .init_irq = mx53_init_irq, - .init_machine = mx53_evk_board_init, .timer = &mx53_evk_timer, + .init_machine = mx53_evk_board_init, MACHINE_END diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c index 3aefd6d..0fea252 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c @@ -82,7 +82,8 @@ static struct sys_timer mx53_loco_timer = { MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board") .map_io = mx53_map_io, + .init_early = imx53_init_early, .init_irq = mx53_init_irq, - .init_machine = mx53_loco_board_init, .timer = &mx53_loco_timer, + .init_machine = mx53_loco_board_init, MACHINE_END diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c index c7b45d4..fa0fad8 100644 --- a/arch/arm/mach-mx5/board-mx53_smd.c +++ b/arch/arm/mach-mx5/board-mx53_smd.c @@ -103,7 +103,8 @@ static struct sys_timer mx53_smd_timer = { MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board") .map_io = mx53_map_io, + .init_early = imx53_init_early, .init_irq = mx53_init_irq, - .init_machine = mx53_smd_board_init, .timer = &mx53_smd_timer, + .init_machine = mx53_smd_board_init, MACHINE_END diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c index 8c6540e..69b3426 100644 --- a/arch/arm/mach-mx5/mm-mx50.c +++ b/arch/arm/mach-mx5/mm-mx50.c @@ -44,10 +44,14 @@ static struct map_desc mx50_io_desc[] __initdata = { */ void __init mx50_map_io(void) { + iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc)); +} + +void __init imx50_init_early(void) +{ mxc_set_cpu_type(MXC_CPU_MX50); mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR)); mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); - iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc)); } int imx50_register_gpios(void); diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index 457f9f9..8730cd1 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c @@ -47,18 +47,26 @@ static struct map_desc mx53_io_desc[] __initdata = { */ void __init mx51_map_io(void) { + iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); +} + +void __init imx51_init_early(void) +{ mxc_set_cpu_type(MXC_CPU_MX51); mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); - iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); } void __init mx53_map_io(void) { + iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); +} + +void __init imx53_init_early(void) +{ mxc_set_cpu_type(MXC_CPU_MX53); mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG_BASE_ADDR)); - iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); } int imx51_register_gpios(void); diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 857eebf47..4746b9a 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -31,6 +31,8 @@ extern void imx27_init_early(void); extern void imx31_init_early(void); extern void imx35_init_early(void); extern void imx50_init_early(void); +extern void imx51_init_early(void); +extern void imx53_init_early(void); extern void mxc_init_irq(void __iomem *); extern void tzic_init_irq(void __iomem *); extern void mx1_init_irq(void); -- cgit v0.10.2 From 23b120cdfae4f5c29da69de750d545bad719ead4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 7 Feb 2011 16:35:22 +0100 Subject: ARM: mxc91231: use .init_early to initialize cpu type MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This used to be done in .map_io which is supposed to only setup the memory mapping. Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c index 395d83b..f31a45e 100644 --- a/arch/arm/mach-mxc91231/magx-zn5.c +++ b/arch/arm/mach-mxc91231/magx-zn5.c @@ -53,9 +53,10 @@ struct sys_timer zn5_timer = { }; MACHINE_START(MAGX_ZN5, "Motorola Zn5") - .boot_params = MXC91231_PHYS_OFFSET + 0x100, - .map_io = mxc91231_map_io, - .init_irq = mxc91231_init_irq, - .timer = &zn5_timer, - .init_machine = zn5_init, + .boot_params = MXC91231_PHYS_OFFSET + 0x100, + .map_io = mxc91231_map_io, + .init_early = mxc91231_init_early, + .init_irq = mxc91231_init_irq, + .timer = &zn5_timer, + .init_machine = zn5_init, MACHINE_END diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c index 7652c30..a77f6da 100644 --- a/arch/arm/mach-mxc91231/mm.c +++ b/arch/arm/mach-mxc91231/mm.c @@ -45,11 +45,14 @@ static struct map_desc mxc91231_io_desc[] __initdata = { */ void __init mxc91231_map_io(void) { - mxc_set_cpu_type(MXC_CPU_MXC91231); - iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc)); } +void __init mxc91231_init_early(void) +{ + mxc_set_cpu_type(MXC_CPU_MXC91231); +} + int mxc91231_register_gpios(void); void __init mxc91231_init_irq(void) diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 4746b9a..a22ebe1 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -33,6 +33,7 @@ extern void imx35_init_early(void); extern void imx50_init_early(void); extern void imx51_init_early(void); extern void imx53_init_early(void); +extern void mxc91231_init_early(void); extern void mxc_init_irq(void __iomem *); extern void tzic_init_irq(void __iomem *); extern void mx1_init_irq(void); -- cgit v0.10.2 From cb07625d1f84fb48e6849cb530762ffcc6f8e458 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 3 Jan 2011 10:33:01 +0100 Subject: ARM i.MX ehci: factor out soc specific functions Currently we have a mxc_initialize_usb_hw which is called on every i.MX SoC. This function dispatches the different SoC types, which is quite ugly. This patch moves the SoC specific USB initialization to their correspondive mach directories. Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 3e49ae0..b85794d 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -9,10 +9,10 @@ obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o -obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o +obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o -obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o +obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o # Support for CMOS sensor interface obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c new file mode 100644 index 0000000..865daf0 --- /dev/null +++ b/arch/arm/mach-imx/ehci-imx25.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2009 Daniel Mack + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include +#include + +#include +#include + +#define USBCTRL_OTGBASE_OFFSET 0x600 + +#define MX25_OTG_SIC_SHIFT 29 +#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) +#define MX25_OTG_PM_BIT (1 << 24) + +#define MX25_H1_SIC_SHIFT 21 +#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) +#define MX25_H1_PM_BIT (1 << 8) +#define MX25_H1_IPPUE_UP_BIT (1 << 7) +#define MX25_H1_IPPUE_DOWN_BIT (1 << 6) +#define MX25_H1_TLL_BIT (1 << 5) +#define MX25_H1_USBTE_BIT (1 << 4) + +int mx25_initialize_usb_hw(int port, unsigned int flags) +{ + unsigned int v; + + v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); + + switch (port) { + case 0: /* OTG port */ + v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; + + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX25_OTG_PM_BIT; + + break; + case 1: /* H1 port */ + v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_TLL_BIT | + MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; + + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX25_H1_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX25_H1_TLL_BIT; + + if (flags & MXC_EHCI_INTERNAL_PHY) + v |= MX25_H1_USBTE_BIT; + + if (flags & MXC_EHCI_IPPUE_DOWN) + v |= MX25_H1_IPPUE_DOWN_BIT; + + if (flags & MXC_EHCI_IPPUE_UP) + v |= MX25_H1_IPPUE_UP_BIT; + + break; + default: + return -EINVAL; + } + + writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); + + return 0; +} + diff --git a/arch/arm/mach-imx/ehci-imx27.c b/arch/arm/mach-imx/ehci-imx27.c new file mode 100644 index 0000000..fa69419 --- /dev/null +++ b/arch/arm/mach-imx/ehci-imx27.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2009 Daniel Mack + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include +#include + +#include +#include + +#define USBCTRL_OTGBASE_OFFSET 0x600 + +#define MX27_OTG_SIC_SHIFT 29 +#define MX27_OTG_SIC_MASK (0x3 << MX27_OTG_SIC_SHIFT) +#define MX27_OTG_PM_BIT (1 << 24) + +#define MX27_H2_SIC_SHIFT 21 +#define MX27_H2_SIC_MASK (0x3 << MX27_H2_SIC_SHIFT) +#define MX27_H2_PM_BIT (1 << 16) +#define MX27_H2_DT_BIT (1 << 5) + +#define MX27_H1_SIC_SHIFT 13 +#define MX27_H1_SIC_MASK (0x3 << MX27_H1_SIC_SHIFT) +#define MX27_H1_PM_BIT (1 << 8) +#define MX27_H1_DT_BIT (1 << 4) + +int mx27_initialize_usb_hw(int port, unsigned int flags) +{ + unsigned int v; + + v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); + + switch (port) { + case 0: /* OTG port */ + v &= ~(MX27_OTG_SIC_MASK | MX27_OTG_PM_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_OTG_SIC_SHIFT; + + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX27_OTG_PM_BIT; + break; + case 1: /* H1 port */ + v &= ~(MX27_H1_SIC_MASK | MX27_H1_PM_BIT | MX27_H1_DT_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H1_SIC_SHIFT; + + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX27_H1_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX27_H1_DT_BIT; + + break; + case 2: /* H2 port */ + v &= ~(MX27_H2_SIC_MASK | MX27_H2_PM_BIT | MX27_H2_DT_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H2_SIC_SHIFT; + + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX27_H2_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX27_H2_DT_BIT; + + break; + default: + return -EINVAL; + } + + writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); + + return 0; +} + diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index bc7294f..224d07a 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -5,8 +5,8 @@ # Object file lists. obj-y := mm.o devices.o cpu.o -obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o -obj-$(CONFIG_SOC_IMX35) += clock-imx35.o +obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o ehci-imx31.o +obj-$(CONFIG_SOC_IMX35) += clock-imx35.o ehci-imx35.o obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o diff --git a/arch/arm/mach-mx3/ehci-imx31.c b/arch/arm/mach-mx3/ehci-imx31.c new file mode 100644 index 0000000..314a983 --- /dev/null +++ b/arch/arm/mach-mx3/ehci-imx31.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2009 Daniel Mack + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include +#include + +#include +#include + +#define USBCTRL_OTGBASE_OFFSET 0x600 + +#define MX31_OTG_SIC_SHIFT 29 +#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) +#define MX31_OTG_PM_BIT (1 << 24) + +#define MX31_H2_SIC_SHIFT 21 +#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) +#define MX31_H2_PM_BIT (1 << 16) +#define MX31_H2_DT_BIT (1 << 5) + +#define MX31_H1_SIC_SHIFT 13 +#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) +#define MX31_H1_PM_BIT (1 << 8) +#define MX31_H1_DT_BIT (1 << 4) + +int mx31_initialize_usb_hw(int port, unsigned int flags) +{ + unsigned int v; + + v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); + + switch (port) { + case 0: /* OTG port */ + v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT; + + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX31_OTG_PM_BIT; + + break; + case 1: /* H1 port */ + v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT; + + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX31_H1_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX31_H1_DT_BIT; + + break; + case 2: /* H2 port */ + v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT; + + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX31_H2_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX31_H2_DT_BIT; + + break; + default: + return -EINVAL; + } + + writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); + + return 0; +} + diff --git a/arch/arm/mach-mx3/ehci-imx35.c b/arch/arm/mach-mx3/ehci-imx35.c new file mode 100644 index 0000000..33983a4 --- /dev/null +++ b/arch/arm/mach-mx3/ehci-imx35.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2009 Daniel Mack + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include +#include + +#include +#include + +#define USBCTRL_OTGBASE_OFFSET 0x600 + +#define MX35_OTG_SIC_SHIFT 29 +#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) +#define MX35_OTG_PM_BIT (1 << 24) + +#define MX35_H1_SIC_SHIFT 21 +#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) +#define MX35_H1_PM_BIT (1 << 8) +#define MX35_H1_IPPUE_UP_BIT (1 << 7) +#define MX35_H1_IPPUE_DOWN_BIT (1 << 6) +#define MX35_H1_TLL_BIT (1 << 5) +#define MX35_H1_USBTE_BIT (1 << 4) + +int mx35_initialize_usb_hw(int port, unsigned int flags) +{ + unsigned int v; + + v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); + + switch (port) { + case 0: /* OTG port */ + v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; + + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX35_OTG_PM_BIT; + + break; + case 1: /* H1 port */ + v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | + MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; + + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX35_H1_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX35_H1_TLL_BIT; + + if (flags & MXC_EHCI_INTERNAL_PHY) + v |= MX35_H1_USBTE_BIT; + + if (flags & MXC_EHCI_IPPUE_DOWN) + v |= MX35_H1_IPPUE_DOWN_BIT; + + if (flags & MXC_EHCI_IPPUE_UP) + v |= MX35_H1_IPPUE_UP_BIT; + + break; + default: + return -EINVAL; + } + + writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); + + return 0; +} + diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 0d43be9..dc27288 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -3,7 +3,7 @@ # # Object file lists. -obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o +obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o obj-$(CONFIG_SOC_IMX50) += mm-mx50.o obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o diff --git a/arch/arm/mach-mx5/ehci.c b/arch/arm/mach-mx5/ehci.c new file mode 100644 index 0000000..7ce12c8 --- /dev/null +++ b/arch/arm/mach-mx5/ehci.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2009 Daniel Mack + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include +#include + +#include +#include + +#define MXC_OTG_OFFSET 0 +#define MXC_H1_OFFSET 0x200 +#define MXC_H2_OFFSET 0x400 + +/* USB_CTRL */ +#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ +#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ +#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ +#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ +#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ + +/* USB_PHY_CTRL_FUNC */ +#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ +#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ + +/* USBH2CTRL */ +#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) +#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) +#define MXC_H2_UCTRL_H2PM_BIT (1 << 4) + +#define MXC_USBCMD_OFFSET 0x140 + +/* USBCMD */ +#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */ + +int mx51_initialize_usb_hw(int port, unsigned int flags) +{ + unsigned int v; + void __iomem *usb_base; + void __iomem *usbotg_base; + void __iomem *usbother_base; + int ret = 0; + + usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + if (!usb_base) { + printk(KERN_ERR "%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + switch (port) { + case 0: /* OTG port */ + usbotg_base = usb_base + MXC_OTG_OFFSET; + break; + case 1: /* Host 1 port */ + usbotg_base = usb_base + MXC_H1_OFFSET; + break; + case 2: /* Host 2 port */ + usbotg_base = usb_base + MXC_H2_OFFSET; + break; + default: + printk(KERN_ERR"%s no such port %d\n", __func__, port); + ret = -ENOENT; + goto error; + } + usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; + + switch (port) { + case 0: /*OTG port */ + if (flags & MXC_EHCI_INTERNAL_PHY) { + v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); + + if (flags & MXC_EHCI_POWER_PINS_ENABLED) { + /* OC/USBPWR is not used */ + v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; + } else { + /* OC/USBPWR is used */ + v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; + } + __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); + + v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); + if (flags & MXC_EHCI_WAKEUP_ENABLED) + v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */ + else + v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v |= MXC_OTG_UCTRL_OPM_BIT; + else + v &= ~MXC_OTG_UCTRL_OPM_BIT; + __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); + } + break; + case 1: /* Host 1 */ + /*Host ULPI */ + v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); + if (flags & MXC_EHCI_WAKEUP_ENABLED) { + /* HOST1 wakeup/ULPI intr enable */ + v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); + } else { + /* HOST1 wakeup/ULPI intr disable */ + v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); + } + + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ + else + v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ + __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); + + v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ + else + v |= MXC_H1_OC_DIS_BIT; /* OC is not used */ + __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); + + v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET); + if (flags & MXC_EHCI_ITC_NO_THRESHOLD) + /* Interrupt Threshold Control:Immediate (no threshold) */ + v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK; + __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET); + break; + case 2: /* Host 2 ULPI */ + v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); + if (flags & MXC_EHCI_WAKEUP_ENABLED) { + /* HOST1 wakeup/ULPI intr enable */ + v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); + } else { + /* HOST1 wakeup/ULPI intr disable */ + v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); + } + + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ + else + v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ + __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); + break; + } + +error: + iounmap(usb_base); + return ret; +} + diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 8772ce3..06fb3a4 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -14,352 +14,29 @@ */ #include -#include #include #include -#define USBCTRL_OTGBASE_OFFSET 0x600 - -#define MX31_OTG_SIC_SHIFT 29 -#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) -#define MX31_OTG_PM_BIT (1 << 24) - -#define MX31_H2_SIC_SHIFT 21 -#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) -#define MX31_H2_PM_BIT (1 << 16) -#define MX31_H2_DT_BIT (1 << 5) - -#define MX31_H1_SIC_SHIFT 13 -#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) -#define MX31_H1_PM_BIT (1 << 8) -#define MX31_H1_DT_BIT (1 << 4) - -#define MX35_OTG_SIC_SHIFT 29 -#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) -#define MX35_OTG_PM_BIT (1 << 24) - -#define MX35_H1_SIC_SHIFT 21 -#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) -#define MX35_H1_PM_BIT (1 << 8) -#define MX35_H1_IPPUE_UP_BIT (1 << 7) -#define MX35_H1_IPPUE_DOWN_BIT (1 << 6) -#define MX35_H1_TLL_BIT (1 << 5) -#define MX35_H1_USBTE_BIT (1 << 4) - -#define MXC_OTG_OFFSET 0 -#define MXC_H1_OFFSET 0x200 -#define MXC_H2_OFFSET 0x400 - -/* USB_CTRL */ -#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ -#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ -#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ -#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ -#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ - -/* USB_PHY_CTRL_FUNC */ -#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ -#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ - -/* USBH2CTRL */ -#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) -#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) -#define MXC_H2_UCTRL_H2PM_BIT (1 << 4) - -#define MXC_USBCMD_OFFSET 0x140 - -/* USBCMD */ -#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */ - int mxc_initialize_usb_hw(int port, unsigned int flags) { - unsigned int v; #if defined(CONFIG_SOC_IMX25) - if (cpu_is_mx25()) { - v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + - USBCTRL_OTGBASE_OFFSET)); - - switch (port) { - case 0: /* OTG port */ - v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) - << MX35_OTG_SIC_SHIFT; - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX35_OTG_PM_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | - MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) - << MX35_H1_SIC_SHIFT; - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX35_H1_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX35_H1_TLL_BIT; - - if (flags & MXC_EHCI_INTERNAL_PHY) - v |= MX35_H1_USBTE_BIT; - - if (flags & MXC_EHCI_IPPUE_DOWN) - v |= MX35_H1_IPPUE_DOWN_BIT; - - if (flags & MXC_EHCI_IPPUE_UP) - v |= MX35_H1_IPPUE_UP_BIT; - - break; - default: - return -EINVAL; - } - - writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + - USBCTRL_OTGBASE_OFFSET)); - return 0; - } + if (cpu_is_mx25()) + return mx25_initialize_usb_hw(port, flags); #endif /* if defined(CONFIG_SOC_IMX25) */ #if defined(CONFIG_ARCH_MX3) - if (cpu_is_mx31()) { - v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + - USBCTRL_OTGBASE_OFFSET)); - - switch (port) { - case 0: /* OTG port */ - v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) - << MX31_OTG_SIC_SHIFT; - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_OTG_PM_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) - << MX31_H1_SIC_SHIFT; - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H1_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H1_DT_BIT; - - break; - case 2: /* H2 port */ - v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) - << MX31_H2_SIC_SHIFT; - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H2_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H2_DT_BIT; - - break; - default: - return -EINVAL; - } - - writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + - USBCTRL_OTGBASE_OFFSET)); - return 0; - } - - if (cpu_is_mx35()) { - v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + - USBCTRL_OTGBASE_OFFSET)); - - switch (port) { - case 0: /* OTG port */ - v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) - << MX35_OTG_SIC_SHIFT; - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX35_OTG_PM_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | - MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) - << MX35_H1_SIC_SHIFT; - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX35_H1_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX35_H1_TLL_BIT; - - if (flags & MXC_EHCI_INTERNAL_PHY) - v |= MX35_H1_USBTE_BIT; - - if (flags & MXC_EHCI_IPPUE_DOWN) - v |= MX35_H1_IPPUE_DOWN_BIT; - - if (flags & MXC_EHCI_IPPUE_UP) - v |= MX35_H1_IPPUE_UP_BIT; - - break; - default: - return -EINVAL; - } - - writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + - USBCTRL_OTGBASE_OFFSET)); - return 0; - } + if (cpu_is_mx31()) + return mx31_initialize_usb_hw(port, flags); + if (cpu_is_mx35()) + return mx35_initialize_usb_hw(port, flags); #endif /* CONFIG_ARCH_MX3 */ #ifdef CONFIG_MACH_MX27 - if (cpu_is_mx27()) { - /* On i.MX27 we can use the i.MX31 USBCTRL bits, they - * are identical - */ - v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + - USBCTRL_OTGBASE_OFFSET)); - switch (port) { - case 0: /* OTG port */ - v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) - << MX31_OTG_SIC_SHIFT; - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_OTG_PM_BIT; - break; - case 1: /* H1 port */ - v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) - << MX31_H1_SIC_SHIFT; - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H1_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H1_DT_BIT; - - break; - case 2: /* H2 port */ - v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) - << MX31_H2_SIC_SHIFT; - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H2_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H2_DT_BIT; - - break; - default: - return -EINVAL; - } - writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + - USBCTRL_OTGBASE_OFFSET)); - return 0; - } + if (cpu_is_mx27()) + return mx27_initialize_usb_hw(port, flags); #endif /* CONFIG_MACH_MX27 */ #ifdef CONFIG_SOC_IMX51 - if (cpu_is_mx51()) { - void __iomem *usb_base; - void __iomem *usbotg_base; - void __iomem *usbother_base; - int ret = 0; - - usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) { - printk(KERN_ERR "%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - switch (port) { - case 0: /* OTG port */ - usbotg_base = usb_base + MXC_OTG_OFFSET; - break; - case 1: /* Host 1 port */ - usbotg_base = usb_base + MXC_H1_OFFSET; - break; - case 2: /* Host 2 port */ - usbotg_base = usb_base + MXC_H2_OFFSET; - break; - default: - printk(KERN_ERR"%s no such port %d\n", __func__, port); - ret = -ENOENT; - goto error; - } - usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; - - switch (port) { - case 0: /*OTG port */ - if (flags & MXC_EHCI_INTERNAL_PHY) { - v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); - - if (flags & MXC_EHCI_POWER_PINS_ENABLED) { - /* OC/USBPWR is not used */ - v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; - } else { - /* OC/USBPWR is used */ - v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; - } - __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); - - v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); - if (flags & MXC_EHCI_WAKEUP_ENABLED) - v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */ - else - v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ - if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v |= MXC_OTG_UCTRL_OPM_BIT; - else - v &= ~MXC_OTG_UCTRL_OPM_BIT; - __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); - } - break; - case 1: /* Host 1 */ - /*Host ULPI */ - v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); - if (flags & MXC_EHCI_WAKEUP_ENABLED) { - /* HOST1 wakeup/ULPI intr enable */ - v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); - } else { - /* HOST1 wakeup/ULPI intr disable */ - v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); - } - - if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ - else - v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ - __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); - - v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); - if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ - else - v |= MXC_H1_OC_DIS_BIT; /* OC is not used */ - __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); - - v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET); - if (flags & MXC_EHCI_ITC_NO_THRESHOLD) - /* Interrupt Threshold Control:Immediate (no threshold) */ - v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK; - __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET); - break; - case 2: /* Host 2 ULPI */ - v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); - if (flags & MXC_EHCI_WAKEUP_ENABLED) { - /* HOST1 wakeup/ULPI intr enable */ - v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); - } else { - /* HOST1 wakeup/ULPI intr disable */ - v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); - } - - if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ - else - v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ - __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); - break; - } - -error: - iounmap(usb_base); - return ret; - } + if (cpu_is_mx51()) + return mx51_initialize_usb_hw(port, flags); #endif printk(KERN_WARNING "%s() unable to setup USBCONTROL for this CPU\n", __func__); diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h index a523a40..7e555a1 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h +++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h @@ -50,5 +50,11 @@ struct mxc_usbh_platform_data { int mxc_initialize_usb_hw(int port, unsigned int flags); +int mx51_initialize_usb_hw(int port, unsigned int flags); +int mx25_initialize_usb_hw(int port, unsigned int flags); +int mx31_initialize_usb_hw(int port, unsigned int flags); +int mx35_initialize_usb_hw(int port, unsigned int flags); +int mx27_initialize_usb_hw(int port, unsigned int flags); + #endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */ -- cgit v0.10.2 From 4bd597b633ae630e09d58957bd99870eac35fcb4 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 3 Jan 2011 11:30:28 +0100 Subject: ARM i.MX ehci: do ehci init in board specific functions The mxc-ehci driver calls SoC specific phy initialization right after calling board specific initialization. To offer greater flexibility for boards to setup the phy and to get rid of some unnecessary flags in platform data this patch lets the boards call the SoC specific phy initialization and remove it from the driver. Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index cabb800..6b724c2 100644 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c @@ -210,14 +210,24 @@ static struct platform_device serial_device = { #endif #if defined(CONFIG_USB_ULPI) +static int eukrea_cpuimx27_otg_init(struct platform_device *pdev) +{ + return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); +} + static struct mxc_usbh_platform_data otg_pdata __initdata = { + .init = eukrea_cpuimx27_otg_init, .portsc = MXC_EHCI_MODE_ULPI, - .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; +static int eukrea_cpuimx27_usbh2_init(struct platform_device *pdev) +{ + return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); +} + static struct mxc_usbh_platform_data usbh2_pdata __initdata = { + .init = eukrea_cpuimx27_usbh2_init, .portsc = MXC_EHCI_MODE_ULPI, - .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; #endif diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c index 439167d..9da8d18 100644 --- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c +++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c @@ -84,15 +84,25 @@ static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = { }, }; +static int eukrea_cpuimx25_otg_init(struct platform_device *pdev) +{ + return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); +} + static const struct mxc_usbh_platform_data otg_pdata __initconst = { + .init = eukrea_cpuimx25_otg_init, .portsc = MXC_EHCI_MODE_UTMI, - .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; +static int eukrea_cpuimx25_usbh2_init(struct platform_device *pdev) +{ + return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI | + MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN); +} + static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { + .init = eukrea_cpuimx25_usbh2_init, .portsc = MXC_EHCI_MODE_SERIAL, - .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | - MXC_EHCI_IPPUE_DOWN, }; static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c index 494723b..ffff2d0 100644 --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -210,14 +211,16 @@ static struct i2c_board_info visstrim_m10_i2c_devices[] = { static int otg_phy_init(struct platform_device *pdev) { gpio_set_value(OTG_PHY_CS_GPIO, 0); - return 0; + + mdelay(10); + + return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); } static const struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata __initconst = { .init = otg_phy_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, - .flags = MXC_EHCI_POWER_PINS_ENABLED, }; static void __init visstrim_m10_board_init(void) diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c index cd18a0c..aafc6f7 100644 --- a/arch/arm/mach-imx/mach-mx25_3ds.c +++ b/arch/arm/mach-imx/mach-mx25_3ds.c @@ -185,9 +185,14 @@ static const struct matrix_keymap_data mx25pdk_keymap_data __initconst = { .keymap_size = ARRAY_SIZE(mx25pdk_keymap), }; +static int mx25pdk_usbh2_init(struct platform_device *pdev) +{ + return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); +} + static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { + .init = mx25pdk_usbh2_init, .portsc = MXC_EHCI_MODE_SERIAL, - .flags = MXC_EHCI_INTERNAL_PHY, }; static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index 4e0e225..ba88417 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c @@ -160,10 +160,14 @@ static int otg_phy_init(void) } #if defined(CONFIG_USB_ULPI) +static int mx27_3ds_otg_init(struct platform_device *pdev) +{ + return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); +} static struct mxc_usbh_platform_data otg_pdata __initdata = { + .init = mx27_3ds_otg_init, .portsc = MXC_EHCI_MODE_ULPI, - .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; #endif diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index 3514178..f754bab 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -271,25 +271,29 @@ static const struct imxmmc_platform_data sdhc_pdata __initconst = { static int otg_phy_init(struct platform_device *pdev) { gpio_set_value(OTG_PHY_CS_GPIO, 0); - return 0; + + mdelay(10); + + return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); } static struct mxc_usbh_platform_data otg_pdata __initdata = { .init = otg_phy_init, .portsc = MXC_EHCI_MODE_ULPI, - .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; static int usbh2_phy_init(struct platform_device *pdev) { gpio_set_value(USBH2_PHY_CS_GPIO, 0); - return 0; + + mdelay(10); + + return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); } static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = usbh2_phy_init, .portsc = MXC_EHCI_MODE_ULPI, - .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; #endif diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 9656ef3..38c7708 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c @@ -281,9 +281,15 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = { } }; +static int pcm038_usbh2_init(struct platform_device *pdev) +{ + return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | + MXC_EHCI_INTERFACE_DIFF_UNI); +} + static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { + .init = pcm038_usbh2_init, .portsc = MXC_EHCI_MODE_ULPI, - .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, }; static void __init pcm038_init(void) diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c index 835e2a0..34e619e 100644 --- a/arch/arm/mach-mx3/mach-armadillo5x0.c +++ b/arch/arm/mach-mx3/mach-armadillo5x0.c @@ -176,8 +176,10 @@ static int usbotg_init(struct platform_device *pdev) gpio_set_value(OTG_RESET, 0/*LOW*/); mdelay(5); gpio_set_value(OTG_RESET, 1/*HIGH*/); + mdelay(10); - return 0; + return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | + MXC_EHCI_INTERFACE_DIFF_UNI); otg_free_reset: gpio_free(OTG_RESET); @@ -233,8 +235,10 @@ static int usbh2_init(struct platform_device *pdev) gpio_set_value(USBH2_RESET, 0/*LOW*/); mdelay(5); gpio_set_value(USBH2_RESET, 1/*HIGH*/); + mdelay(10); - return 0; + return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | + MXC_EHCI_INTERFACE_DIFF_UNI); h2_free_reset: gpio_free(USBH2_RESET); @@ -246,13 +250,11 @@ h2_free_cs: static struct mxc_usbh_platform_data usbotg_pdata __initdata = { .init = usbotg_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, - .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, }; static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = usbh2_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, - .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, }; #endif /* CONFIG_USB_ULPI */ diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c index 3eedf0f..0f23056 100644 --- a/arch/arm/mach-mx3/mach-cpuimx35.c +++ b/arch/arm/mach-mx3/mach-cpuimx35.c @@ -111,15 +111,25 @@ static const struct mxc_nand_platform_data .flash_bbt = 1, }; +static int eukrea_cpuimx35_otg_init(struct platform_device *pdev) +{ + return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); +} + static const struct mxc_usbh_platform_data otg_pdata __initconst = { + .init = eukrea_cpuimx35_otg_init, .portsc = MXC_EHCI_MODE_UTMI, - .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; +static int eukrea_cpuimx35_usbh1_init(struct platform_device *pdev) +{ + return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI | + MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN); +} + static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { + .init = eukrea_cpuimx35_usbh1_init, .portsc = MXC_EHCI_MODE_SERIAL, - .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | - MXC_EHCI_IPPUE_DOWN, }; static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 3d0ded9..2d744b2 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -245,7 +245,13 @@ usbotg_free_reset: return err; } -static int __maybe_unused mx31_3ds_host2_init(struct platform_device *pdev) +#if defined(CONFIG_USB_ULPI) +static int mx31_3ds_otg_init(struct platform_device *pdev) +{ + return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); +} + +static int mx31_3ds_host2_init(struct platform_device *pdev) { int err; @@ -276,23 +282,24 @@ static int __maybe_unused mx31_3ds_host2_init(struct platform_device *pdev) mdelay(1); gpio_set_value(USBH2_RST_B, 1); - return 0; + + mdelay(10); + + return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); usbotg_free_reset: gpio_free(USBH2_RST_B); return err; } -#if defined(CONFIG_USB_ULPI) static struct mxc_usbh_platform_data otg_pdata __initdata = { + .init = mx31_3ds_otg_init, .portsc = MXC_EHCI_MODE_ULPI, - .flags = MXC_EHCI_POWER_PINS_ENABLED, }; static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = mx31_3ds_host2_init, .portsc = MXC_EHCI_MODE_ULPI, - .flags = MXC_EHCI_POWER_PINS_ENABLED, }; #endif diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c index 1c3f491..be79a0d 100644 --- a/arch/arm/mach-mx3/mach-mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -156,7 +157,9 @@ static int usbotg_init(struct platform_device *pdev) gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), "USBH1 CS"); gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), 0); - return 0; + mdelay(10); + + return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); } static int usbh1_init(struct platform_device *pdev) @@ -183,7 +186,10 @@ static int usbh1_init(struct platform_device *pdev) mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); - return 0; + mdelay(10); + + return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | + MXC_EHCI_INTERFACE_SINGLE_UNI); } static int usbh2_init(struct platform_device *pdev) @@ -220,25 +226,24 @@ static int usbh2_init(struct platform_device *pdev) gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); - return 0; + mdelay(10); + + return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); } static struct mxc_usbh_platform_data usbotg_pdata = { .init = usbotg_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, - .flags = MXC_EHCI_POWER_PINS_ENABLED, }; static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { .init = usbh1_init, .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, - .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, }; static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = usbh2_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, - .flags = MXC_EHCI_POWER_PINS_ENABLED, }; static void lilly1131_usb_init(void) diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c index 01e24b5..e146f1a 100644 --- a/arch/arm/mach-mx3/mach-mx31lite.c +++ b/arch/arm/mach-mx3/mach-mx31lite.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -167,13 +168,14 @@ static int usbh2_init(struct platform_device *pdev) gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); - return 0; + mdelay(10); + + return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); } static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = usbh2_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, - .flags = MXC_EHCI_POWER_PINS_ENABLED, }; #endif diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index fd988a0..ea88033 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -401,10 +401,14 @@ static void usb_xcvr_reset(void) } #if defined(CONFIG_USB_ULPI) +static int moboard_usbh2_init_hw(struct platform_device *pdev) +{ + return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); +} static struct mxc_usbh_platform_data usbh2_pdata __initdata = { + .init = moboard_usbh2_init_hw, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, - .flags = MXC_EHCI_POWER_PINS_ENABLED, }; static int __init moboard_usbh2_init(void) diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c index c5115dc..dac1896 100644 --- a/arch/arm/mach-mx3/mach-mx35_3ds.c +++ b/arch/arm/mach-mx3/mach-mx35_3ds.c @@ -120,6 +120,11 @@ static iomux_v3_cfg_t mx35pdk_pads[] = { MX35_PAD_SD1_DATA3__ESDHC1_DAT3, }; +static int mx35_3ds_otg_init(struct platform_device *pdev) +{ + return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); +} + /* OTG config */ static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, @@ -127,15 +132,20 @@ static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = { }; static struct mxc_usbh_platform_data otg_pdata __initdata = { + .init = mx35_3ds_otg_init, .portsc = MXC_EHCI_MODE_UTMI, - .flags = MXC_EHCI_INTERNAL_PHY, }; +static int mx35_3ds_usbh_init(struct platform_device *pdev) +{ + return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI | + MXC_EHCI_INTERNAL_PHY); +} + /* USB HOST config */ static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { + .init = mx35_3ds_usbh_init, .portsc = MXC_EHCI_MODE_SERIAL, - .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | - MXC_EHCI_INTERNAL_PHY, }; static int otg_mode_host; diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c index 7d444f7..55f95d4 100644 --- a/arch/arm/mach-mx3/mach-pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c @@ -534,14 +534,24 @@ static struct platform_device pcm970_sja1000 = { }; #if defined(CONFIG_USB_ULPI) +static int pcm037_otg_init(struct platform_device *pdev) +{ + return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); +} + static struct mxc_usbh_platform_data otg_pdata __initdata = { + .init = pcm037_otg_init, .portsc = MXC_EHCI_MODE_ULPI, - .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; +static int pcm037_usbh2_init(struct platform_device *pdev) +{ + return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); +} + static struct mxc_usbh_platform_data usbh2_pdata __initdata = { + .init = pcm037_usbh2_init, .portsc = MXC_EHCI_MODE_ULPI, - .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; #endif diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index b03e19d..4fa0714 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -306,16 +306,26 @@ pcm037_nand_board_info __initconst = { }; #if defined(CONFIG_USB_ULPI) +static int pcm043_otg_init(struct platform_device *pdev) +{ + return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); +} + static struct mxc_usbh_platform_data otg_pdata __initdata = { + .init = pcm043_otg_init, .portsc = MXC_EHCI_MODE_UTMI, - .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; #endif +static int pcm043_usbh1_init(struct platform_device *pdev) +{ + return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI | + MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN); +} + static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { + .init = pcm043_usbh1_init, .portsc = MXC_EHCI_MODE_SERIAL, - .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | - MXC_EHCI_IPPUE_DOWN, }; static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c index 94a0b9e..6410b9c 100644 --- a/arch/arm/mach-mx3/mx31moboard-devboard.c +++ b/arch/arm/mach-mx3/mx31moboard-devboard.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -149,7 +150,10 @@ static int devboard_usbh1_hw_init(struct platform_device *pdev) mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); - return 0; + mdelay(10); + + return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | + MXC_EHCI_INTERFACE_SINGLE_UNI); } #define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) @@ -187,7 +191,6 @@ static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on) static struct mxc_usbh_platform_data usbh1_pdata __initdata = { .init = devboard_usbh1_hw_init, .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, - .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, }; static int __init devboard_usbh1_init(void) diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c index f449a97..57f7b00 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c @@ -265,7 +265,10 @@ static int marxbot_usbh1_hw_init(struct platform_device *pdev) mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); - return 0; + mdelay(10); + + return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | + MXC_EHCI_INTERFACE_SINGLE_UNI); } #define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) @@ -303,7 +306,6 @@ static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on) static struct mxc_usbh_platform_data usbh1_pdata __initdata = { .init = marxbot_usbh1_hw_init, .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, - .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, }; static int __init marxbot_usbh1_init(void) diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c index bbec3c8..87d556f 100644 --- a/arch/arm/mach-mx3/mx31moboard-smartbot.c +++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c @@ -123,9 +123,14 @@ static const struct fsl_usb2_platform_data usb_pdata __initconst = { #if defined(CONFIG_USB_ULPI) +static int smartbot_otg_init(struct platform_device *pdev) +{ + return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); +} + static struct mxc_usbh_platform_data otg_host_pdata __initdata = { + .init = smartbot_otg_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, - .flags = MXC_EHCI_POWER_PINS_ENABLED, }; static int __init smartbot_otg_host_init(void) diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c index 2d4199d..d0296a9 100644 --- a/arch/arm/mach-mx5/board-cpuimx51.c +++ b/arch/arm/mach-mx5/board-cpuimx51.c @@ -184,7 +184,10 @@ static int initialize_otg_port(struct platform_device *pdev) v |= MX51_USB_PLL_DIV_19_2_MHZ; __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); iounmap(usb_base); - return 0; + + mdelay(10); + + return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY); } static int initialize_usbh1_port(struct platform_device *pdev) @@ -202,13 +205,16 @@ static int initialize_usbh1_port(struct platform_device *pdev) v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); iounmap(usb_base); - return 0; + + mdelay(10); + + return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED | + MXC_EHCI_ITC_NO_THRESHOLD); } static struct mxc_usbh_platform_data dr_utmi_config = { .init = initialize_otg_port, .portsc = MXC_EHCI_UTMI_16BIT, - .flags = MXC_EHCI_INTERNAL_PHY, }; static struct fsl_usb2_platform_data usb_pdata = { @@ -219,7 +225,6 @@ static struct fsl_usb2_platform_data usb_pdata = { static struct mxc_usbh_platform_data usbh1_config = { .init = initialize_usbh1_port, .portsc = MXC_EHCI_MODE_ULPI, - .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD), }; static int otg_mode_host; diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c index 6c3b445..f38b341 100644 --- a/arch/arm/mach-mx5/board-cpuimx51sd.c +++ b/arch/arm/mach-mx5/board-cpuimx51sd.c @@ -167,7 +167,10 @@ static int initialize_otg_port(struct platform_device *pdev) v |= MX51_USB_PLL_DIV_19_2_MHZ; __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); iounmap(usb_base); - return 0; + + mdelay(10); + + return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY); } static int initialize_usbh1_port(struct platform_device *pdev) @@ -186,13 +189,16 @@ static int initialize_usbh1_port(struct platform_device *pdev) __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); iounmap(usb_base); - return 0; + + mdelay(10); + + return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED | + MXC_EHCI_ITC_NO_THRESHOLD); } static struct mxc_usbh_platform_data dr_utmi_config = { .init = initialize_otg_port, .portsc = MXC_EHCI_UTMI_16BIT, - .flags = MXC_EHCI_INTERNAL_PHY, }; static struct fsl_usb2_platform_data usb_pdata = { @@ -203,7 +209,6 @@ static struct fsl_usb2_platform_data usb_pdata = { static struct mxc_usbh_platform_data usbh1_config = { .init = initialize_usbh1_port, .portsc = MXC_EHCI_MODE_ULPI, - .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD), }; static int otg_mode_host; diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index 2bd9c9e..7874bcd 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -259,7 +259,10 @@ static int initialize_otg_port(struct platform_device *pdev) v |= MX51_USB_PLL_DIV_19_2_MHZ; __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); iounmap(usb_base); - return 0; + + mdelay(10); + + return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY); } static int initialize_usbh1_port(struct platform_device *pdev) @@ -277,13 +280,16 @@ static int initialize_usbh1_port(struct platform_device *pdev) v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); iounmap(usb_base); - return 0; + + mdelay(10); + + return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED | + MXC_EHCI_ITC_NO_THRESHOLD); } static struct mxc_usbh_platform_data dr_utmi_config = { .init = initialize_otg_port, .portsc = MXC_EHCI_UTMI_16BIT, - .flags = MXC_EHCI_INTERNAL_PHY, }; static struct fsl_usb2_platform_data usb_pdata = { @@ -294,7 +300,6 @@ static struct fsl_usb2_platform_data usb_pdata = { static struct mxc_usbh_platform_data usbh1_config = { .init = initialize_usbh1_port, .portsc = MXC_EHCI_MODE_ULPI, - .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD), }; static int otg_mode_host; diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c index 2aac4c5..b0fa553 100644 --- a/arch/arm/mach-mx5/board-mx51_efikamx.c +++ b/arch/arm/mach-mx5/board-mx51_efikamx.c @@ -145,13 +145,15 @@ static int initialize_otg_port(struct platform_device *pdev) v |= MX51_USB_PLL_DIV_24_MHZ; __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); iounmap(usb_base); - return 0; + + mdelay(10); + + return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY); } static struct mxc_usbh_platform_data dr_utmi_config = { .init = initialize_otg_port, .portsc = MXC_EHCI_UTMI_16BIT, - .flags = MXC_EHCI_INTERNAL_PHY, }; /* PCBID2 PCBID1 PCBID0 STATE diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 5fd20e9..a138787 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -13,7 +13,6 @@ obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o obj-$(CONFIG_MXC_PWM) += pwm.o -obj-$(CONFIG_USB_EHCI_MXC) += ehci.o obj-$(CONFIG_MXC_ULPI) += ulpi.o obj-$(CONFIG_MXC_USE_EPIT) += epit.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c deleted file mode 100644 index 06fb3a4..0000000 --- a/arch/arm/plat-mxc/ehci.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2009 Daniel Mack - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - */ - -#include - -#include -#include - -int mxc_initialize_usb_hw(int port, unsigned int flags) -{ -#if defined(CONFIG_SOC_IMX25) - if (cpu_is_mx25()) - return mx25_initialize_usb_hw(port, flags); -#endif /* if defined(CONFIG_SOC_IMX25) */ -#if defined(CONFIG_ARCH_MX3) - if (cpu_is_mx31()) - return mx31_initialize_usb_hw(port, flags); - if (cpu_is_mx35()) - return mx35_initialize_usb_hw(port, flags); -#endif /* CONFIG_ARCH_MX3 */ -#ifdef CONFIG_MACH_MX27 - if (cpu_is_mx27()) - return mx27_initialize_usb_hw(port, flags); -#endif /* CONFIG_MACH_MX27 */ -#ifdef CONFIG_SOC_IMX51 - if (cpu_is_mx51()) - return mx51_initialize_usb_hw(port, flags); -#endif - printk(KERN_WARNING - "%s() unable to setup USBCONTROL for this CPU\n", __func__); - return -EINVAL; -} -EXPORT_SYMBOL(mxc_initialize_usb_hw); - diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h index 7e555a1..2c159dc 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h +++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h @@ -44,12 +44,9 @@ struct mxc_usbh_platform_data { int (*exit)(struct platform_device *pdev); unsigned int portsc; - unsigned int flags; struct otg_transceiver *otg; }; -int mxc_initialize_usb_hw(int port, unsigned int flags); - int mx51_initialize_usb_hw(int port, unsigned int flags); int mx25_initialize_usb_hw(int port, unsigned int flags); int mx31_initialize_usb_hw(int port, unsigned int flags); diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index c8e360d..25c8c10 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -203,11 +203,6 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev) mdelay(10); } - /* setup specific usb hw */ - ret = mxc_initialize_usb_hw(pdev->id, pdata->flags); - if (ret < 0) - goto err_init; - ehci = hcd_to_ehci(hcd); /* EHCI registers start at offset 0x100 */ -- cgit v0.10.2 From e134fb2b40ca7e2d96ba460b0c844c6a9fa489c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 11 Feb 2011 10:23:19 +0100 Subject: ARM: mx3+mx5: rename mxc_board_init to ${machine}_init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mxc_board_init is too generic to be useful. Additionally change some mxc_timer to ${machine}_timer, too. Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c index 0f23056..6db0520 100644 --- a/arch/arm/mach-mx3/mach-cpuimx35.c +++ b/arch/arm/mach-mx3/mach-cpuimx35.c @@ -156,7 +156,7 @@ __setup("otg_mode=", eukrea_cpuimx35_otg_mode); /* * Board specific initialization. */ -static void __init mxc_board_init(void) +static void __init eukrea_cpuimx35_init(void) { mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads, ARRAY_SIZE(eukrea_cpuimx35_pads)); @@ -199,5 +199,5 @@ MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35") .init_ext3_fs = imx35_init_early, .init_irq = mx35_init_irq, .timer = &eukrea_cpuimx35_timer, - .init_machine = mxc_board_init, + .init_machine = eukrea_cpuimx35_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c index 52b8dd7..d3cc739 100644 --- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c +++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c @@ -266,13 +266,9 @@ static void __init kzm_timer_init(void) } static struct sys_timer kzm_timer = { - .init = kzm_timer_init, + .init = kzm_timer_init, }; -/* - * The following uses standard kernel macros define in arch.h in order to - * initialize __mach_desc_KZM_ARM11_01 data structure. - */ MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = kzm_map_io, diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 2d744b2..0d24b3c 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -327,10 +327,7 @@ static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -/*! - * Board specific initialization. - */ -static void __init mxc_board_init(void) +static void __init mx31_3ds_init(void) { mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), "mx31_3ds"); @@ -385,5 +382,5 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") .init_early = imx31_init_early, .init_irq = mx31_init_irq, .timer = &mx31_3ds_timer, - .init_machine = mxc_board_init, + .init_machine = mx31_3ds_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index 787bdc4..cb80b96 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -524,10 +524,7 @@ static void __init mx31ads_init_irq(void) mx31ads_init_expio(); } -/*! - * Board specific initialization. - */ -static void __init mxc_board_init(void) +static void __init mx31ads_init(void) { mxc_init_extuart(); mxc_init_imx_uart(); @@ -555,5 +552,5 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS") .init_early = imx31_init_early, .init_irq = mx31ads_init_irq, .timer = &mx31ads_timer, - .init_machine = mxc_board_init, + .init_machine = mx31ads_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c index e146f1a..81021bf 100644 --- a/arch/arm/mach-mx3/mach-mx31lite.c +++ b/arch/arm/mach-mx3/mach-mx31lite.c @@ -229,7 +229,7 @@ void __init mx31lite_map_io(void) static int mx31lite_baseboard; core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444); -static void __init mxc_board_init(void) +static void __init mx31lite_init(void) { int ret; @@ -288,5 +288,5 @@ MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") .init_early = imx31_init_early, .init_irq = mx31_init_irq, .timer = &mx31lite_timer, - .init_machine = mxc_board_init, + .init_machine = mx31lite_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index ea88033..845d0b6 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -507,7 +507,7 @@ core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444); /* * Board specific initialization. */ -static void __init mxc_board_init(void) +static void __init mx31moboard_init(void) { mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins), "moboard"); @@ -573,5 +573,5 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") .init_early = imx31_init_early, .init_irq = mx31_init_irq, .timer = &mx31moboard_timer, - .init_machine = mxc_board_init, + .init_machine = mx31moboard_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c index dac1896..be12ac1 100644 --- a/arch/arm/mach-mx3/mach-mx35_3ds.c +++ b/arch/arm/mach-mx3/mach-mx35_3ds.c @@ -166,7 +166,7 @@ __setup("otg_mode=", mx35_3ds_otg_mode); /* * Board specific initialization. */ -static void __init mxc_board_init(void) +static void __init mx35_3ds_init(void) { mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); @@ -208,5 +208,5 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK") .init_early = imx35_init_early, .init_irq = mx35_init_irq, .timer = &mx35pdk_timer, - .init_machine = mxc_board_init, + .init_machine = mx35_3ds_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c index 55f95d4..783d31b 100644 --- a/arch/arm/mach-mx3/mach-pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c @@ -578,7 +578,7 @@ __setup("otg_mode=", pcm037_otg_mode); /* * Board specific initialization. */ -static void __init mxc_board_init(void) +static void __init pcm037_init(void) { int ret; @@ -690,5 +690,5 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037") .init_early = imx31_init_early, .init_irq = mx31_init_irq, .timer = &pcm037_timer, - .init_machine = mxc_board_init, + .init_machine = pcm037_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index 4fa0714..6c662c7 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -351,7 +351,7 @@ __setup("otg_mode=", pcm043_otg_mode); /* * Board specific initialization. */ -static void __init mxc_board_init(void) +static void __init pcm043_init(void) { mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); @@ -418,5 +418,5 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043") .init_early = imx35_init_early, .init_irq = mx35_init_irq, .timer = &pcm043_timer, - .init_machine = mxc_board_init, + .init_machine = pcm043_init, MACHINE_END diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c index 064f2db..0028163 100644 --- a/arch/arm/mach-mx3/mach-qong.c +++ b/arch/arm/mach-mx3/mach-qong.c @@ -247,7 +247,7 @@ static void __init qong_init_fpga(void) /* * Board specific initialization. */ -static void __init mxc_board_init(void) +static void __init qong_init(void) { mxc_init_imx_uart(); qong_init_nor_mtd(); @@ -275,5 +275,5 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") .init_early = imx31_init_early, .init_irq = mx31_init_irq, .timer = &qong_timer, - .init_machine = mxc_board_init, + .init_machine = qong_init, MACHINE_END diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c index 0168470..63dfbea 100644 --- a/arch/arm/mach-mx5/board-mx51_3ds.c +++ b/arch/arm/mach-mx5/board-mx51_3ds.c @@ -133,7 +133,7 @@ static struct spi_board_info mx51_3ds_spi_nor_device[] = { /* * Board specific initialization. */ -static void __init mxc_board_init(void) +static void __init mx51_3ds_init(void) { mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads, ARRAY_SIZE(mx51_3ds_pads)); @@ -160,8 +160,8 @@ static void __init mx51_3ds_timer_init(void) mx51_clocks_init(32768, 24000000, 22579200, 0); } -static struct sys_timer mxc_timer = { - .init = mx51_3ds_timer_init, +static struct sys_timer mx51_3ds_timer = { + .init = mx51_3ds_timer_init, }; MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") @@ -170,6 +170,6 @@ MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") .map_io = mx51_map_io, .init_early = imx51_init_early, .init_irq = mx51_init_irq, - .timer = &mxc_timer, - .init_machine = mxc_board_init, + .timer = &mx51_3ds_timer, + .init_machine = mx51_3ds_init, MACHINE_END diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index 7874bcd..b2ecd19 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -341,7 +341,7 @@ static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = { /* * Board specific initialization. */ -static void __init mxc_board_init(void) +static void __init mx51_babbage_init(void) { iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 | @@ -395,8 +395,8 @@ static void __init mx51_babbage_timer_init(void) mx51_clocks_init(32768, 24000000, 22579200, 0); } -static struct sys_timer mxc_timer = { - .init = mx51_babbage_timer_init, +static struct sys_timer mx51_babbage_timer = { + .init = mx51_babbage_timer_init, }; MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") @@ -405,6 +405,6 @@ MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") .map_io = mx51_map_io, .init_early = imx51_init_early, .init_irq = mx51_init_irq, - .timer = &mxc_timer, - .init_machine = mxc_board_init, + .timer = &mx51_babbage_timer, + .init_machine = mx51_babbage_init, MACHINE_END diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c index b0fa553..c4094fa 100644 --- a/arch/arm/mach-mx5/board-mx51_efikamx.c +++ b/arch/arm/mach-mx5/board-mx51_efikamx.c @@ -303,7 +303,7 @@ void mx51_efikamx_reset(void) gpio_direction_output(EFIKAMX_RESET, 0); } -static void __init mxc_board_init(void) +static void __init mx51_efikamx_init(void) { mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads, ARRAY_SIZE(mx51efikamx_pads)); @@ -341,8 +341,8 @@ static void __init mx51_efikamx_timer_init(void) mx51_clocks_init(32768, 24000000, 22579200, 24576000); } -static struct sys_timer mxc_timer = { - .init = mx51_efikamx_timer_init, +static struct sys_timer mx51_efikamx_timer = { + .init = mx51_efikamx_timer_init, }; MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop") @@ -351,6 +351,6 @@ MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop") .map_io = mx51_map_io, .init_early = imx51_init_early, .init_irq = mx51_init_irq, - .timer = &mxc_timer, - .init_machine = mxc_board_init, + .timer = &mx51_efikamx_timer, + .init_machine = mx51_efikamx_init, MACHINE_END -- cgit v0.10.2 From a0c859c593827c0ff488e05909e9901ecd10159f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 11 Feb 2011 10:21:08 +0100 Subject: ARM: mx3: remove some useless comments MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 0d24b3c..b7d0953 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -42,10 +42,6 @@ /* CPLD IRQ line for external uart, external ethernet etc */ #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1) -/* - * This file contains the board-specific initialization routines. - */ - static int mx31_3ds_pins[] = { /* UART1 */ MX31_PIN_CTS1__CTS1, @@ -371,10 +367,6 @@ static struct sys_timer mx31_3ds_timer = { .init = mx31_3ds_timer_init, }; -/* - * The following uses standard kernel macros defined in arch.h in order to - * initialize __mach_desc_MX31_3DS data structure. - */ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") /* Maintainer: Freescale Semiconductor, Inc. */ .boot_params = MX3x_PHYS_OFFSET + 0x100, diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index cb80b96..14e7671 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -69,9 +69,6 @@ #define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11) #define MXC_MAX_EXP_IO_LINES 16 -/* - * This file contains the board-specific initialization routines. - */ /* * The serial port definition structure. @@ -497,9 +494,7 @@ static void mxc_init_audio(void) mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi"); } -/*! - * This structure defines static mappings for the i.MX31ADS board. - */ +/* static mappings */ static struct map_desc mx31ads_io_desc[] __initdata = { { .virtual = MX31_CS4_BASE_ADDR_VIRT, @@ -509,9 +504,6 @@ static struct map_desc mx31ads_io_desc[] __initdata = { }, }; -/*! - * Set up static virtual mappings. - */ static void __init mx31ads_map_io(void) { mx31_map_io(); @@ -541,10 +533,6 @@ static struct sys_timer mx31ads_timer = { .init = mx31ads_timer_init, }; -/* - * The following uses standard kernel macros defined in arch.h in order to - * initialize __mach_desc_MX31ADS data structure. - */ MACHINE_START(MX31ADS, "Freescale MX31ADS") /* Maintainer: Freescale Semiconductor, Inc. */ .boot_params = MX3x_PHYS_OFFSET + 0x100, diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c index 0028163..17f758b 100644 --- a/arch/arm/mach-mx3/mach-qong.c +++ b/arch/arm/mach-mx3/mach-qong.c @@ -54,10 +54,6 @@ #define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1) -/* - * This file contains the board-specific initialization routines. - */ - static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -263,11 +259,6 @@ static struct sys_timer qong_timer = { .init = qong_timer_init, }; -/* - * The following uses standard kernel macros defined in arch.h in order to - * initialize __mach_desc_QONG data structure. - */ - MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") /* Maintainer: DENX Software Engineering GmbH */ .boot_params = MX3x_PHYS_OFFSET + 0x100, diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c index 3387319..eefd4cf 100644 --- a/arch/arm/mach-mx3/mm.c +++ b/arch/arm/mach-mx3/mm.c @@ -28,14 +28,6 @@ #include #include -/*! - * @file mm.c - * - * @brief This file creates static virtual to physical mappings, common to all MX3 boards. - * - * @ingroup Memory - */ - #ifdef CONFIG_SOC_IMX31 static struct map_desc mx31_io_desc[] __initdata = { imx_map_entry(MX31, X_MEMC, MT_DEVICE), @@ -135,4 +127,3 @@ static int mxc_init_l2x0(void) arch_initcall(mxc_init_l2x0); #endif - -- cgit v0.10.2 From 4e43d9fad1c0984e167ab14bd8148289acd61b9c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 11 Feb 2011 10:21:09 +0100 Subject: ARM: mx3/mx31ads: fix comments of irq callbacks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The arguments to these callbacks were changed in e981a30 (ARM: mx3: irq_data conversion.) but the comments were not adapted. Cc: Lennert Buytenhek Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index 14e7671..4e4b780 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -144,7 +144,7 @@ static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc) /* * Disable an expio pin's interrupt by setting the bit in the imr. - * @param irq an expio virtual irq number + * @param d an expio virtual irq description */ static void expio_mask_irq(struct irq_data *d) { @@ -156,7 +156,7 @@ static void expio_mask_irq(struct irq_data *d) /* * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. - * @param irq an expanded io virtual irq number + * @param d an expio virtual irq description */ static void expio_ack_irq(struct irq_data *d) { @@ -167,7 +167,7 @@ static void expio_ack_irq(struct irq_data *d) /* * Enable a expio pin's interrupt by clearing the bit in the imr. - * @param irq a expio virtual irq number + * @param d an expio virtual irq description */ static void expio_unmask_irq(struct irq_data *d) { -- cgit v0.10.2 From 124c13b9a34267bfae9c1bb0bdf4a8a6c1cc1df1 Mon Sep 17 00:00:00 2001 From: Julien Boibessot Date: Fri, 11 Feb 2011 15:15:30 +0100 Subject: i.MX51 iomux: Fixes MX51_PAD_UART2_TXD__UART2_TXD & MX51_PAD_USBH1_DATA2__UART2_TXD declarations Fixes 2 small regressions of recent iomux changes: - current MX51_PAD_UART2_TXD__UART2_TXD declaration overwrites IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT register (0x09ec) and prevent UART2 Rx from working properly. (Tested on my custom i.MX51 board where UART2 is used as console) - current MX51_PAD_USBH1_DATA2__UART2_TXD declaration also has the same problem. (Not tested) Signed-off-by: Julien Boibessot Signed-off-by: Sascha Hauer diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index b6767f9..6056cf2 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -473,7 +473,7 @@ #define _MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0) #define _MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0) #define _MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0) -#define _MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, 0x09ec, 3, 0) +#define _MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, 0x0000, 0, 0) #define _MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0) #define _MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0) #define _MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0) @@ -528,7 +528,7 @@ #define _MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0) #define _MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0) #define _MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, 0x09ec, 5, 0) +#define _MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, 0x0000, 0, 0) #define _MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0) #define _MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0) #define _MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0) -- cgit v0.10.2 From 18fd7315cc475ff53c60e5e7b3bad126c0163527 Mon Sep 17 00:00:00 2001 From: Jesper Juhl Date: Mon, 14 Feb 2011 23:54:00 +0100 Subject: Freescale STMP37XX/STMP378X Application UART driver: remove duplicate linux/device.h include Do not include linux/device.h twice in drivers/tty/serial/mxs-auart.c . Once is enough. Signed-off-by: Jesper Juhl Signed-off-by: Sascha Hauer diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c index 6d01ac9..7e02c9c 100644 --- a/drivers/tty/serial/mxs-auart.c +++ b/drivers/tty/serial/mxs-auart.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include -- cgit v0.10.2 From 08ec1130d4652ba1cab5ce0a423bcb2229c7a60b Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 17 Feb 2011 14:28:49 +0800 Subject: ARM: mx23: rename mx23 auart irq definition to align with mx28 i.MX23 Reference Manual names auart irq differently from i.MX28. This patch is to align the naming with mx28, so that some device registration codes can be shared. Signed-off-by: Shawn Guo Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h index 9edd02e..4768402 100644 --- a/arch/arm/mach-mxs/include/mach/mx23.h +++ b/arch/arm/mach-mxs/include/mach/mx23.h @@ -101,9 +101,9 @@ #define MX23_INT_SSP2_DMA 20 #define MX23_INT_ECC8_IRQ 21 #define MX23_INT_RTC_ALARM 22 -#define MX23_INT_UARTAPP_TX_DMA 23 -#define MX23_INT_UARTAPP_INTERNAL 24 -#define MX23_INT_UARTAPP_RX_DMA 25 +#define MX23_INT_AUART1_TX_DMA 23 +#define MX23_INT_AUART1 24 +#define MX23_INT_AUART1_RX_DMA 25 #define MX23_INT_I2C_DMA 26 #define MX23_INT_I2C_ERROR 27 #define MX23_INT_TIMER0 28 @@ -135,9 +135,9 @@ #define MX23_INT_DCP 54 #define MX23_INT_BCH 56 #define MX23_INT_PXP 57 -#define MX23_INT_UARTAPP2_TX_DMA 58 -#define MX23_INT_UARTAPP2_INTERNAL 59 -#define MX23_INT_UARTAPP2_RX_DMA 60 +#define MX23_INT_AUART2_TX_DMA 58 +#define MX23_INT_AUART2 59 +#define MX23_INT_AUART2_RX_DMA 60 #define MX23_INT_VDAC_DETECT 61 #define MX23_INT_VDD5V_DROOP 64 #define MX23_INT_DCDC4P2_BO 65 -- cgit v0.10.2 From edca314f27c984f353a5129253d8d5241b82c517 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 17 Feb 2011 14:28:50 +0800 Subject: ARM: mx23: dynamically allocate mx23 auart device i.MX23 Reference Manaul starts auart index from 1 than 0. Changing the index to start from 0 requires corresponding changes on base address, irq, and iomux definitions, and will probably confuse people who reads codes and hardware documents together. This patch introduced the field 'hwid' to distinguish the driver id and controller id. These two ids are different on mx23 while identical on mx28. Signed-off-by: Shawn Guo Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c index ca72a05..7c5dace 100644 --- a/arch/arm/mach-mxs/clock-mx23.c +++ b/arch/arm/mach-mxs/clock-mx23.c @@ -442,6 +442,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk) /* for amba-pl011 driver */ _REGISTER_CLOCK("duart", NULL, uart_clk) + _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk) _REGISTER_CLOCK("rtc", NULL, rtc_clk) _REGISTER_CLOCK(NULL, "hclk", hbus_clk) _REGISTER_CLOCK(NULL, "usb", usb_clk) diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h index 1256788..c4d4773 100644 --- a/arch/arm/mach-mxs/devices-mx23.h +++ b/arch/arm/mach-mxs/devices-mx23.h @@ -14,3 +14,8 @@ extern const struct amba_device mx23_duart_device __initconst; #define mx23_add_duart() \ mxs_add_duart(&mx23_duart_device) + +extern const struct mxs_auart_data mx23_auart_data[] __initconst; +#define mx23_add_auart(id) mxs_add_auart(&mx23_auart_data[id]) +#define mx23_add_auart0() mx23_add_auart(0) +#define mx23_add_auart1() mx23_add_auart(1) diff --git a/arch/arm/mach-mxs/devices/platform-auart.c b/arch/arm/mach-mxs/devices/platform-auart.c index f0dbf8a..796606c 100644 --- a/arch/arm/mach-mxs/devices/platform-auart.c +++ b/arch/arm/mach-mxs/devices/platform-auart.c @@ -7,23 +7,33 @@ * Free Software Foundation. */ #include +#include #include #include -#define mxs_auart_data_entry_single(soc, _id) \ +#define mxs_auart_data_entry_single(soc, _id, hwid) \ { \ .id = _id, \ - .iobase = soc ## _AUART ## _id ## _BASE_ADDR, \ - .irq = soc ## _INT_AUART ## _id, \ + .iobase = soc ## _AUART ## hwid ## _BASE_ADDR, \ + .irq = soc ## _INT_AUART ## hwid, \ } -#define mxs_auart_data_entry(soc, _id) \ - [_id] = mxs_auart_data_entry_single(soc, _id) +#define mxs_auart_data_entry(soc, _id, hwid) \ + [_id] = mxs_auart_data_entry_single(soc, _id, hwid) + +#ifdef CONFIG_SOC_IMX23 +const struct mxs_auart_data mx23_auart_data[] __initconst = { +#define mx23_auart_data_entry(_id, hwid) \ + mxs_auart_data_entry(MX23, _id, hwid) + mx23_auart_data_entry(0, 1), + mx23_auart_data_entry(1, 2), +}; +#endif #ifdef CONFIG_SOC_IMX28 const struct mxs_auart_data mx28_auart_data[] __initconst = { #define mx28_auart_data_entry(_id) \ - mxs_auart_data_entry(MX28, _id) + mxs_auart_data_entry(MX28, _id, _id) mx28_auart_data_entry(0), mx28_auart_data_entry(1), mx28_auart_data_entry(2), -- cgit v0.10.2 From 2e8acbc28314ce1a0f9cc65a7e76bd24595a6bad Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 17 Feb 2011 14:28:51 +0800 Subject: ARM: mxs/mx23evk: add auart device Signed-off-by: Shawn Guo Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index cd2fbdf..3c5ce09 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -19,6 +19,7 @@ config MACH_MX23EVK bool "Support MX23EVK Platform" select SOC_IMX23 select MXS_HAVE_AMBA_DUART + select MXS_HAVE_PLATFORM_AUART default y help Include support for MX23EVK platform. This includes specific diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c index aa06400..0737ce2 100644 --- a/arch/arm/mach-mxs/mach-mx23evk.c +++ b/arch/arm/mach-mxs/mach-mx23evk.c @@ -30,6 +30,16 @@ static const iomux_cfg_t mx23evk_pads[] __initconst = { /* duart */ MX23_PAD_PWM0__DUART_RX | MXS_PAD_4MA, MX23_PAD_PWM1__DUART_TX | MXS_PAD_4MA, + + /* auart */ + MX23_PAD_AUART1_RX__AUART1_RX | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX23_PAD_AUART1_TX__AUART1_TX | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX23_PAD_AUART1_CTS__AUART1_CTS | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX23_PAD_AUART1_RTS__AUART1_RTS | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), }; static void __init mx23evk_init(void) @@ -37,6 +47,7 @@ static void __init mx23evk_init(void) mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads)); mx23_add_duart(); + mx23_add_auart0(); } static void __init mx23evk_timer_init(void) -- cgit v0.10.2 From 15808182ae8044a064286445bcecaee6105cd718 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 17 Feb 2011 14:28:52 +0800 Subject: ARM: mxs/mx28evk: add auart devices Signed-off-by: Shawn Guo Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 3c5ce09..55bf075 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -29,6 +29,7 @@ config MACH_MX28EVK bool "Support MX28EVK Platform" select SOC_IMX28 select MXS_HAVE_AMBA_DUART + select MXS_HAVE_PLATFORM_AUART select MXS_HAVE_PLATFORM_FEC select MXS_OCOTP default y diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c index e8db99f..1f0b708 100644 --- a/arch/arm/mach-mxs/mach-mx28evk.c +++ b/arch/arm/mach-mxs/mach-mx28evk.c @@ -38,6 +38,25 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = { MX28_PAD_PWM1__DUART_TX | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* auart0 */ + MX28_PAD_AUART0_RX__AUART0_RX | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_AUART0_TX__AUART0_TX | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_AUART0_CTS__AUART0_CTS | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_AUART0_RTS__AUART0_RTS | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* auart3 */ + MX28_PAD_AUART3_RX__AUART3_RX | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_AUART3_TX__AUART3_TX | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_AUART3_CTS__AUART3_CTS | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_AUART3_RTS__AUART3_RTS | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* fec0 */ MX28_PAD_ENET0_MDC__ENET0_MDC | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), @@ -164,6 +183,8 @@ static void __init mx28evk_init(void) mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads)); mx28_add_duart(); + mx28_add_auart0(); + mx28_add_auart3(); if (mx28evk_fec_get_mac()) pr_warn("%s: failed on fec mac setup\n", __func__); -- cgit v0.10.2 From 7ac18a3845145f4f48e611640e33918ae450f955 Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Thu, 17 Feb 2011 15:31:28 +0100 Subject: Introduce EFIKA_COMMON The Genesi EFIKA MX and EFIKA Smartbook are sharing a lot of things so it makes sense to create a common file for both devices and a specific file for each. No functionnal change except dropping uart 1 & 2. Signed-off-by: Arnaud Patard Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 10b6008..aa20a38 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -113,12 +113,16 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD endchoice -config MACH_MX51_EFIKAMX - bool "Support MX51 Genesi Efika MX nettop" +config MX51_EFIKA_COMMON + bool select SOC_IMX51 select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select IMX_HAVE_PLATFORM_SPI_IMX + +config MACH_MX51_EFIKAMX + bool "Support MX51 Genesi Efika MX nettop" + select MX51_EFIKA_COMMON help Include support for Genesi Efika MX nettop. This includes specific configurations for the board and its peripherals. diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index dc27288..64f6b0d 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -16,5 +16,6 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o +obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c index c4094fa..272de6e 100644 --- a/arch/arm/mach-mx5/board-mx51_efikamx.c +++ b/arch/arm/mach-mx5/board-mx51_efikamx.c @@ -40,8 +40,7 @@ #include "devices-imx51.h" #include "devices.h" - -#define MX51_USB_PLL_DIV_24_MHZ 0x01 +#include "efika.h" #define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16) #define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17) @@ -53,9 +52,6 @@ #define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31) -#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24) -#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25) - /* board 1.1 doesn't have same reset gpio */ #define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2) #define EFIKAMX_RESET IMX_GPIO_NR(1, 4) @@ -67,38 +63,11 @@ #define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) static iomux_v3_cfg_t mx51efikamx_pads[] = { - /* UART1 */ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_RTS__UART1_RTS, - MX51_PAD_UART1_CTS__UART1_CTS, /* board id */ MX51_PAD_PCBID0, MX51_PAD_PCBID1, MX51_PAD_PCBID2, - /* SD 1 */ - MX51_PAD_SD1_CMD__SD1_CMD, - MX51_PAD_SD1_CLK__SD1_CLK, - MX51_PAD_SD1_DATA0__SD1_DATA0, - MX51_PAD_SD1_DATA1__SD1_DATA1, - MX51_PAD_SD1_DATA2__SD1_DATA2, - MX51_PAD_SD1_DATA3__SD1_DATA3, - - /* SD 2 */ - MX51_PAD_SD2_CMD__SD2_CMD, - MX51_PAD_SD2_CLK__SD2_CLK, - MX51_PAD_SD2_DATA0__SD2_DATA0, - MX51_PAD_SD2_DATA1__SD2_DATA1, - MX51_PAD_SD2_DATA2__SD2_DATA2, - MX51_PAD_SD2_DATA3__SD2_DATA3, - - /* SD/MMC WP/CD */ - MX51_PAD_GPIO1_0__SD1_CD, - MX51_PAD_GPIO1_1__SD1_WP, - MX51_PAD_GPIO1_7__SD2_WP, - MX51_PAD_GPIO1_8__SD2_CD, - /* leds */ MX51_PAD_CSI1_D9__GPIO3_13, MX51_PAD_CSI1_VSYNC__GPIO3_14, @@ -107,55 +76,11 @@ static iomux_v3_cfg_t mx51efikamx_pads[] = { /* power key */ MX51_PAD_PWRKEY, - /* spi */ - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, - MX51_PAD_CSPI1_MISO__ECSPI1_MISO, - MX51_PAD_CSPI1_SS0__GPIO4_24, - MX51_PAD_CSPI1_SS1__GPIO4_25, - MX51_PAD_CSPI1_RDY__ECSPI1_RDY, - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, - /* reset */ MX51_PAD_DI1_PIN13__GPIO3_2, MX51_PAD_GPIO1_4__GPIO1_4, }; -/* Serial ports */ -static const struct imxuart_platform_data uart_pdata = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* This function is board specific as the bit mask for the plldiv will also - * be different for other Freescale SoCs, thus a common bitmask is not - * possible and cannot get place in /plat-mxc/ehci.c. - */ -static int initialize_otg_port(struct platform_device *pdev) -{ - u32 v; - void __iomem *usb_base; - void __iomem *usbother_base; - usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) - return -ENOMEM; - usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); - - /* Set the PHY clock to 19.2MHz */ - v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; - v |= MX51_USB_PLL_DIV_24_MHZ; - __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - iounmap(usb_base); - - mdelay(10); - - return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY); -} - -static struct mxc_usbh_platform_data dr_utmi_config = { - .init = initialize_otg_port, - .portsc = MXC_EHCI_UTMI_16BIT, -}; - /* PCBID2 PCBID1 PCBID0 STATE 1 1 1 ER1:rev1.1 1 1 0 ER2:rev1.2 @@ -254,47 +179,6 @@ static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initcon .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey), }; -static struct mtd_partition mx51_efikamx_spi_nor_partitions[] = { - { - .name = "u-boot", - .offset = 0, - .size = SZ_256K, - }, - { - .name = "config", - .offset = MTDPART_OFS_APPEND, - .size = SZ_64K, - }, -}; - -static struct flash_platform_data mx51_efikamx_spi_flash_data = { - .name = "spi_flash", - .parts = mx51_efikamx_spi_nor_partitions, - .nr_parts = ARRAY_SIZE(mx51_efikamx_spi_nor_partitions), - .type = "sst25vf032b", -}; - -static struct spi_board_info mx51_efikamx_spi_board_info[] __initdata = { - { - .modalias = "m25p80", - .max_speed_hz = 25000000, - .bus_num = 0, - .chip_select = 1, - .platform_data = &mx51_efikamx_spi_flash_data, - .irq = -1, - }, -}; - -static int mx51_efikamx_spi_cs[] = { - EFIKAMX_SPI_CS0, - EFIKAMX_SPI_CS1, -}; - -static const struct spi_imx_master mx51_efikamx_spi_pdata __initconst = { - .chipselect = mx51_efikamx_spi_cs, - .num_chipselect = ARRAY_SIZE(mx51_efikamx_spi_cs), -}; - void mx51_efikamx_reset(void) { if (system_rev == 0x11) @@ -307,12 +191,9 @@ static void __init mx51_efikamx_init(void) { mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads, ARRAY_SIZE(mx51efikamx_pads)); + efika_board_common_init(); + mx51_efikamx_board_id(); - mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); - imx51_add_imx_uart(0, &uart_pdata); - imx51_add_imx_uart(1, &uart_pdata); - imx51_add_imx_uart(2, &uart_pdata); - imx51_add_sdhci_esdhc_imx(0, NULL); /* on < 1.2 boards both SD controllers are used */ if (system_rev < 0x12) { @@ -323,10 +204,6 @@ static void __init mx51_efikamx_init(void) platform_device_register(&mx51_efikamx_leds_device); imx51_add_gpio_keys(&mx51_efikamx_powerkey_data); - spi_register_board_info(mx51_efikamx_spi_board_info, - ARRAY_SIZE(mx51_efikamx_spi_board_info)); - imx51_add_ecspi(0, &mx51_efikamx_spi_pdata); - if (system_rev == 0x11) { gpio_request(EFIKAMX_RESET1_1, "reset"); gpio_direction_output(EFIKAMX_RESET1_1, 1); diff --git a/arch/arm/mach-mx5/efika.h b/arch/arm/mach-mx5/efika.h new file mode 100644 index 0000000..c828043 --- /dev/null +++ b/arch/arm/mach-mx5/efika.h @@ -0,0 +1,6 @@ +#ifndef _EFIKA_H +#define _EFIKA_H + +void __init efika_board_common_init(void); + +#endif diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c new file mode 100644 index 0000000..a249ca3 --- /dev/null +++ b/arch/arm/mach-mx5/mx51_efika.c @@ -0,0 +1,175 @@ +/* + * based on code from the following + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. + * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "devices-imx51.h" +#include "devices.h" +#include "efika.h" + +#define MX51_USB_PLL_DIV_24_MHZ 0x01 + +#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24) +#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25) + +static iomux_v3_cfg_t mx51efika_pads[] = { + /* UART1 */ + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, + + /* SD 1 */ + MX51_PAD_SD1_CMD__SD1_CMD, + MX51_PAD_SD1_CLK__SD1_CLK, + MX51_PAD_SD1_DATA0__SD1_DATA0, + MX51_PAD_SD1_DATA1__SD1_DATA1, + MX51_PAD_SD1_DATA2__SD1_DATA2, + MX51_PAD_SD1_DATA3__SD1_DATA3, + + /* SD 2 */ + MX51_PAD_SD2_CMD__SD2_CMD, + MX51_PAD_SD2_CLK__SD2_CLK, + MX51_PAD_SD2_DATA0__SD2_DATA0, + MX51_PAD_SD2_DATA1__SD2_DATA1, + MX51_PAD_SD2_DATA2__SD2_DATA2, + MX51_PAD_SD2_DATA3__SD2_DATA3, + + /* SD/MMC WP/CD */ + MX51_PAD_GPIO1_0__SD1_CD, + MX51_PAD_GPIO1_1__SD1_WP, + MX51_PAD_GPIO1_7__SD2_WP, + MX51_PAD_GPIO1_8__SD2_CD, + + /* spi */ + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, + MX51_PAD_CSPI1_MISO__ECSPI1_MISO, + MX51_PAD_CSPI1_SS0__GPIO4_24, + MX51_PAD_CSPI1_SS1__GPIO4_25, + MX51_PAD_CSPI1_RDY__ECSPI1_RDY, + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, +}; + +/* Serial ports */ +static const struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +/* This function is board specific as the bit mask for the plldiv will also + * be different for other Freescale SoCs, thus a common bitmask is not + * possible and cannot get place in /plat-mxc/ehci.c. + */ +static int initialize_otg_port(struct platform_device *pdev) +{ + u32 v; + void __iomem *usb_base; + void __iomem *usbother_base; + usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + if (!usb_base) + return -ENOMEM; + usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); + + /* Set the PHY clock to 19.2MHz */ + v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); + v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; + v |= MX51_USB_PLL_DIV_24_MHZ; + __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); + iounmap(usb_base); + + mdelay(10); + + return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY); +} + +static struct mxc_usbh_platform_data dr_utmi_config = { + .init = initialize_otg_port, + .portsc = MXC_EHCI_UTMI_16BIT, +}; + +static struct mtd_partition mx51_efika_spi_nor_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = SZ_256K, + }, + { + .name = "config", + .offset = MTDPART_OFS_APPEND, + .size = SZ_64K, + }, +}; + +static struct flash_platform_data mx51_efika_spi_flash_data = { + .name = "spi_flash", + .parts = mx51_efika_spi_nor_partitions, + .nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions), + .type = "sst25vf032b", +}; + +static struct spi_board_info mx51_efika_spi_board_info[] __initdata = { + { + .modalias = "m25p80", + .max_speed_hz = 25000000, + .bus_num = 0, + .chip_select = 1, + .platform_data = &mx51_efika_spi_flash_data, + .irq = -1, + }, +}; + +static int mx51_efika_spi_cs[] = { + EFIKAMX_SPI_CS0, + EFIKAMX_SPI_CS1, +}; + +static const struct spi_imx_master mx51_efika_spi_pdata __initconst = { + .chipselect = mx51_efika_spi_cs, + .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs), +}; + +void __init efika_board_common_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx51efika_pads, + ARRAY_SIZE(mx51efika_pads)); + mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); + imx51_add_imx_uart(0, &uart_pdata); + imx51_add_sdhci_esdhc_imx(0, NULL); + + spi_register_board_info(mx51_efika_spi_board_info, + ARRAY_SIZE(mx51_efika_spi_board_info)); + imx51_add_ecspi(0, &mx51_efika_spi_pdata); +} + -- cgit v0.10.2 From 9d72af6e3582977196e3474903950206dc3c590e Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Thu, 17 Feb 2011 15:31:29 +0100 Subject: efikamx: add usb h1 support Now that usb has been fixed, we can enable usb h1 on efikamx Signed-off-by: Arnaud Patard Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index aa20a38..1405464 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -119,6 +119,7 @@ config MX51_EFIKA_COMMON select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select IMX_HAVE_PLATFORM_SPI_IMX + select MXC_ULPI if USB_ULPI config MACH_MX51_EFIKAMX bool "Support MX51 Genesi Efika MX nettop" diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c index 272de6e..8f17336 100644 --- a/arch/arm/mach-mx5/board-mx51_efikamx.c +++ b/arch/arm/mach-mx5/board-mx51_efikamx.c @@ -211,6 +211,20 @@ static void __init mx51_efikamx_init(void) gpio_request(EFIKAMX_RESET, "reset"); gpio_direction_output(EFIKAMX_RESET, 1); } + + /* + * enable wifi by default only on mx + * sb and mx have same wlan pin but the value to enable it are + * different :/ + */ + gpio_request(EFIKA_WLAN_EN, "wlan_en"); + gpio_direction_output(EFIKA_WLAN_EN, 0); + msleep(10); + + gpio_request(EFIKA_WLAN_RESET, "wlan_rst"); + gpio_direction_output(EFIKA_WLAN_RESET, 0); + msleep(10); + gpio_set_value(EFIKA_WLAN_RESET, 1); } static void __init mx51_efikamx_timer_init(void) diff --git a/arch/arm/mach-mx5/efika.h b/arch/arm/mach-mx5/efika.h index c828043..014aa98 100644 --- a/arch/arm/mach-mx5/efika.h +++ b/arch/arm/mach-mx5/efika.h @@ -1,6 +1,10 @@ #ifndef _EFIKA_H #define _EFIKA_H +#define EFIKA_WLAN_EN IMX_GPIO_NR(2, 16) +#define EFIKA_WLAN_RESET IMX_GPIO_NR(2, 10) +#define EFIKA_USB_PHY_RESET IMX_GPIO_NR(2, 9) + void __init efika_board_common_init(void); #endif diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c index a249ca3..c08ec63 100644 --- a/arch/arm/mach-mx5/mx51_efika.c +++ b/arch/arm/mach-mx5/mx51_efika.c @@ -30,6 +30,10 @@ #include #include +#include +#include +#include + #include #include #include @@ -40,7 +44,12 @@ #include "devices.h" #include "efika.h" -#define MX51_USB_PLL_DIV_24_MHZ 0x01 +#define MX51_USB_CTRL_1_OFFSET 0x10 +#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) +#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 + +#define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5) +#define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27) #define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24) #define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25) @@ -81,6 +90,29 @@ static iomux_v3_cfg_t mx51efika_pads[] = { MX51_PAD_CSPI1_SS1__GPIO4_25, MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, + + /* USB HOST1 */ + MX51_PAD_USBH1_CLK__USBH1_CLK, + MX51_PAD_USBH1_DIR__USBH1_DIR, + MX51_PAD_USBH1_NXT__USBH1_NXT, + MX51_PAD_USBH1_DATA0__USBH1_DATA0, + MX51_PAD_USBH1_DATA1__USBH1_DATA1, + MX51_PAD_USBH1_DATA2__USBH1_DATA2, + MX51_PAD_USBH1_DATA3__USBH1_DATA3, + MX51_PAD_USBH1_DATA4__USBH1_DATA4, + MX51_PAD_USBH1_DATA5__USBH1_DATA5, + MX51_PAD_USBH1_DATA6__USBH1_DATA6, + MX51_PAD_USBH1_DATA7__USBH1_DATA7, + + /* USB HUB RESET */ + MX51_PAD_GPIO1_5__GPIO1_5, + + /* WLAN */ + MX51_PAD_EIM_A22__GPIO2_16, + MX51_PAD_EIM_A16__GPIO2_10, + + /* USB PHY RESET */ + MX51_PAD_EIM_D27__GPIO2_9, }; /* Serial ports */ @@ -105,13 +137,13 @@ static int initialize_otg_port(struct platform_device *pdev) /* Set the PHY clock to 19.2MHz */ v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; - v |= MX51_USB_PLL_DIV_24_MHZ; + v |= MX51_USB_PLL_DIV_19_2_MHZ; __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); iounmap(usb_base); mdelay(10); - return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY); + return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); } static struct mxc_usbh_platform_data dr_utmi_config = { @@ -119,6 +151,73 @@ static struct mxc_usbh_platform_data dr_utmi_config = { .portsc = MXC_EHCI_UTMI_16BIT, }; +static int initialize_usbh1_port(struct platform_device *pdev) +{ + iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; + iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27; + u32 v; + void __iomem *usb_base; + void __iomem *socregs_base; + + mxc_iomux_v3_setup_pad(usbh1gpio); + gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp"); + gpio_direction_output(EFIKAMX_USBH1_STP, 0); + msleep(1); + gpio_set_value(EFIKAMX_USBH1_STP, 1); + msleep(1); + + usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); + + /* The clock for the USBH1 ULPI port will come externally */ + /* from the PHY. */ + v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET); + __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, + socregs_base + MX51_USB_CTRL_1_OFFSET); + + iounmap(usb_base); + + gpio_free(EFIKAMX_USBH1_STP); + mxc_iomux_v3_setup_pad(usbh1stp); + + mdelay(10); + + return mx51_initialize_usb_hw(0, MXC_EHCI_ITC_NO_THRESHOLD); +} + +static struct mxc_usbh_platform_data usbh1_config = { + .init = initialize_usbh1_port, + .portsc = MXC_EHCI_MODE_ULPI, +}; + +static void mx51_efika_hubreset(void) +{ + gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst"); + gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1); + msleep(1); + gpio_set_value(EFIKAMX_USB_HUB_RESET, 0); + msleep(1); + gpio_set_value(EFIKAMX_USB_HUB_RESET, 1); +} + +static void __init mx51_efika_usb(void) +{ + mx51_efika_hubreset(); + + /* pulling it low, means no USB at all... */ + gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset"); + gpio_direction_output(EFIKA_USB_PHY_RESET, 0); + msleep(1); + gpio_set_value(EFIKA_USB_PHY_RESET, 1); + + usbh1_config.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT | + ULPI_OTG_EXTVBUSIND); + + mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); + mxc_register_device(&mxc_usbh1_device, &usbh1_config); +} + static struct mtd_partition mx51_efika_spi_nor_partitions[] = { { .name = "u-boot", @@ -164,8 +263,8 @@ void __init efika_board_common_init(void) { mxc_iomux_v3_setup_multiple_pads(mx51efika_pads, ARRAY_SIZE(mx51efika_pads)); - mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); imx51_add_imx_uart(0, &uart_pdata); + mx51_efika_usb(); imx51_add_sdhci_esdhc_imx(0, NULL); spi_register_board_info(mx51_efika_spi_board_info, -- cgit v0.10.2 From 2432cff0fc1c9d1a41476994b18fda04bf9f2686 Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Thu, 17 Feb 2011 15:31:30 +0100 Subject: efikamx: add mc13892 support / implement power off This patch declares regulators for the efikamx. Use it also to power off the efikamx. Unfortunately, on the efikamx to2 boards, this doesn't work but they allow to power off by setting GPIO 4 13 to high level instead of powering off through the mc13892. Signed-off-by: Arnaud Patard Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c index 8f17336..acab191 100644 --- a/arch/arm/mach-mx5/board-mx51_efikamx.c +++ b/arch/arm/mach-mx5/board-mx51_efikamx.c @@ -25,6 +25,9 @@ #include #include #include +#include +#include +#include #include #include @@ -56,6 +59,10 @@ #define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2) #define EFIKAMX_RESET IMX_GPIO_NR(1, 4) +#define EFIKAMX_POWEROFF IMX_GPIO_NR(4, 13) + +#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6) + /* the pci ids pin have pull up. they're driven low according to board id */ #define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) #define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) @@ -79,6 +86,9 @@ static iomux_v3_cfg_t mx51efikamx_pads[] = { /* reset */ MX51_PAD_DI1_PIN13__GPIO3_2, MX51_PAD_GPIO1_4__GPIO1_4, + + /* power off */ + MX51_PAD_CSI2_VSYNC__GPIO4_13, }; /* PCBID2 PCBID1 PCBID0 STATE @@ -187,6 +197,46 @@ void mx51_efikamx_reset(void) gpio_direction_output(EFIKAMX_RESET, 0); } +static struct regulator *pwgt1, *pwgt2, *coincell; + +static void mx51_efikamx_power_off(void) +{ + if (!IS_ERR(coincell)) + regulator_disable(coincell); + + if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { + regulator_disable(pwgt2); + regulator_disable(pwgt1); + } + gpio_direction_output(EFIKAMX_POWEROFF, 1); +} + +static int __init mx51_efikamx_power_init(void) +{ + if (machine_is_mx51_efikamx()) { + pwgt1 = regulator_get(NULL, "pwgt1"); + pwgt2 = regulator_get(NULL, "pwgt2"); + if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { + regulator_enable(pwgt1); + regulator_enable(pwgt2); + } + gpio_request(EFIKAMX_POWEROFF, "poweroff"); + pm_power_off = mx51_efikamx_power_off; + + /* enable coincell charger. maybe need a small power driver ? */ + coincell = regulator_get(NULL, "coincell"); + if (!IS_ERR(coincell)) { + regulator_set_voltage(coincell, 3000000, 3000000); + regulator_enable(coincell); + } + + regulator_has_full_constraints(); + } + + return 0; +} +late_initcall(mx51_efikamx_power_init); + static void __init mx51_efikamx_init(void) { mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads, diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c index c08ec63..b4d5ae9 100644 --- a/arch/arm/mach-mx5/mx51_efika.c +++ b/arch/arm/mach-mx5/mx51_efika.c @@ -23,6 +23,9 @@ #include #include #include +#include +#include +#include #include #include @@ -39,6 +42,7 @@ #include #include #include +#include #include "devices-imx51.h" #include "devices.h" @@ -54,6 +58,8 @@ #define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24) #define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25) +#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6) + static iomux_v3_cfg_t mx51efika_pads[] = { /* UART1 */ MX51_PAD_UART1_RXD__UART1_RXD, @@ -90,6 +96,7 @@ static iomux_v3_cfg_t mx51efika_pads[] = { MX51_PAD_CSPI1_SS1__GPIO4_25, MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, + MX51_PAD_GPIO1_6__GPIO1_6, /* USB HOST1 */ MX51_PAD_USBH1_CLK__USBH1_CLK, @@ -238,6 +245,336 @@ static struct flash_platform_data mx51_efika_spi_flash_data = { .type = "sst25vf032b", }; +static struct regulator_consumer_supply sw1_consumers[] = { + { + .supply = "cpu_vcc", + } +}; + +static struct regulator_consumer_supply vdig_consumers[] = { + /* sgtl5000 */ + REGULATOR_SUPPLY("VDDA", "1-000a"), + REGULATOR_SUPPLY("VDDD", "1-000a"), +}; + +static struct regulator_consumer_supply vvideo_consumers[] = { + /* sgtl5000 */ + REGULATOR_SUPPLY("VDDIO", "1-000a"), +}; + +static struct regulator_consumer_supply vsd_consumers[] = { + REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.0"), + REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"), +}; + +static struct regulator_consumer_supply pwgt1_consumer[] = { + { + .supply = "pwgt1", + } +}; + +static struct regulator_consumer_supply pwgt2_consumer[] = { + { + .supply = "pwgt2", + } +}; + +static struct regulator_consumer_supply coincell_consumer[] = { + { + .supply = "coincell", + } +}; + +static struct regulator_init_data sw1_init = { + .constraints = { + .name = "SW1", + .min_uV = 600000, + .max_uV = 1375000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + .state_mem = { + .uV = 850000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), + .consumer_supplies = sw1_consumers, +}; + +static struct regulator_init_data sw2_init = { + .constraints = { + .name = "SW2", + .min_uV = 900000, + .max_uV = 1850000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + .state_mem = { + .uV = 950000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + } +}; + +static struct regulator_init_data sw3_init = { + .constraints = { + .name = "SW3", + .min_uV = 1100000, + .max_uV = 1850000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data sw4_init = { + .constraints = { + .name = "SW4", + .min_uV = 1100000, + .max_uV = 1850000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data viohi_init = { + .constraints = { + .name = "VIOHI", + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data vusb_init = { + .constraints = { + .name = "VUSB", + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data swbst_init = { + .constraints = { + .name = "SWBST", + } +}; + +static struct regulator_init_data vdig_init = { + .constraints = { + .name = "VDIG", + .min_uV = 1050000, + .max_uV = 1800000, + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(vdig_consumers), + .consumer_supplies = vdig_consumers, +}; + +static struct regulator_init_data vpll_init = { + .constraints = { + .name = "VPLL", + .min_uV = 1050000, + .max_uV = 1800000, + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data vusb2_init = { + .constraints = { + .name = "VUSB2", + .min_uV = 2400000, + .max_uV = 2775000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data vvideo_init = { + .constraints = { + .name = "VVIDEO", + .min_uV = 2775000, + .max_uV = 2775000, + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .apply_uV = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers), + .consumer_supplies = vvideo_consumers, +}; + +static struct regulator_init_data vaudio_init = { + .constraints = { + .name = "VAUDIO", + .min_uV = 2300000, + .max_uV = 3000000, + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, + .boot_on = 1, + } +}; + +static struct regulator_init_data vsd_init = { + .constraints = { + .name = "VSD", + .min_uV = 1800000, + .max_uV = 3150000, + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(vsd_consumers), + .consumer_supplies = vsd_consumers, +}; + +static struct regulator_init_data vcam_init = { + .constraints = { + .name = "VCAM", + .min_uV = 2500000, + .max_uV = 3000000, + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, + .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, + .boot_on = 1, + } +}; + +static struct regulator_init_data vgen1_init = { + .constraints = { + .name = "VGEN1", + .min_uV = 1200000, + .max_uV = 3150000, + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data vgen2_init = { + .constraints = { + .name = "VGEN2", + .min_uV = 1200000, + .max_uV = 3150000, + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data vgen3_init = { + .constraints = { + .name = "VGEN3", + .min_uV = 1800000, + .max_uV = 2900000, + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data gpo1_init = { + .constraints = { + .name = "GPO1", + } +}; + +static struct regulator_init_data gpo2_init = { + .constraints = { + .name = "GPO2", + } +}; + +static struct regulator_init_data gpo3_init = { + .constraints = { + .name = "GPO3", + } +}; + +static struct regulator_init_data gpo4_init = { + .constraints = { + .name = "GPO4", + } +}; + +static struct regulator_init_data pwgt1_init = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer), + .consumer_supplies = pwgt1_consumer, +}; + +static struct regulator_init_data pwgt2_init = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer), + .consumer_supplies = pwgt2_consumer, +}; + +static struct regulator_init_data vcoincell_init = { + .constraints = { + .name = "COINCELL", + .min_uV = 3000000, + .max_uV = 3000000, + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(coincell_consumer), + .consumer_supplies = coincell_consumer, +}; + +static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = { + { .id = MC13892_SW1, .init_data = &sw1_init }, + { .id = MC13892_SW2, .init_data = &sw2_init }, + { .id = MC13892_SW3, .init_data = &sw3_init }, + { .id = MC13892_SW4, .init_data = &sw4_init }, + { .id = MC13892_SWBST, .init_data = &swbst_init }, + { .id = MC13892_VIOHI, .init_data = &viohi_init }, + { .id = MC13892_VPLL, .init_data = &vpll_init }, + { .id = MC13892_VDIG, .init_data = &vdig_init }, + { .id = MC13892_VSD, .init_data = &vsd_init }, + { .id = MC13892_VUSB2, .init_data = &vusb2_init }, + { .id = MC13892_VVIDEO, .init_data = &vvideo_init }, + { .id = MC13892_VAUDIO, .init_data = &vaudio_init }, + { .id = MC13892_VCAM, .init_data = &vcam_init }, + { .id = MC13892_VGEN1, .init_data = &vgen1_init }, + { .id = MC13892_VGEN2, .init_data = &vgen2_init }, + { .id = MC13892_VGEN3, .init_data = &vgen3_init }, + { .id = MC13892_VUSB, .init_data = &vusb_init }, + { .id = MC13892_GPO1, .init_data = &gpo1_init }, + { .id = MC13892_GPO2, .init_data = &gpo2_init }, + { .id = MC13892_GPO3, .init_data = &gpo3_init }, + { .id = MC13892_GPO4, .init_data = &gpo4_init }, + { .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init }, + { .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init }, + { .id = MC13892_VCOINCELL, .init_data = &vcoincell_init }, +}; + +static struct mc13xxx_platform_data mx51_efika_mc13892_data = { + .flags = MC13XXX_USE_RTC | MC13XXX_USE_REGULATOR, + .num_regulators = ARRAY_SIZE(mx51_efika_regulators), + .regulators = mx51_efika_regulators, +}; + static struct spi_board_info mx51_efika_spi_board_info[] __initdata = { { .modalias = "m25p80", @@ -247,6 +584,14 @@ static struct spi_board_info mx51_efika_spi_board_info[] __initdata = { .platform_data = &mx51_efika_spi_flash_data, .irq = -1, }, + { + .modalias = "mc13892", + .max_speed_hz = 1000000, + .bus_num = 0, + .chip_select = 0, + .platform_data = &mx51_efika_mc13892_data, + .irq = gpio_to_irq(EFIKAMX_PMIC), + }, }; static int mx51_efika_spi_cs[] = { @@ -267,6 +612,18 @@ void __init efika_board_common_init(void) mx51_efika_usb(); imx51_add_sdhci_esdhc_imx(0, NULL); + /* FIXME: comes from original code. check this. */ + if (mx51_revision() < IMX_CHIP_REVISION_2_0) + sw2_init.constraints.state_mem.uV = 1100000; + else if (mx51_revision() == IMX_CHIP_REVISION_2_0) { + sw2_init.constraints.state_mem.uV = 1250000; + sw1_init.constraints.state_mem.uV = 1000000; + } + if (machine_is_mx51_efikasb()) + vgen1_init.constraints.max_uV = 1200000; + + gpio_request(EFIKAMX_PMIC, "pmic irq"); + gpio_direction_input(EFIKAMX_PMIC); spi_register_board_info(mx51_efika_spi_board_info, ARRAY_SIZE(mx51_efika_spi_board_info)); imx51_add_ecspi(0, &mx51_efika_spi_pdata); -- cgit v0.10.2 From 856e656c4a328907c2b1fdbb6523f16fe1c71b46 Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Thu, 17 Feb 2011 15:31:31 +0100 Subject: efika: enable cpufreq Enable cpufreq on Genesi efika platforms Signed-off-by: Arnaud Patard Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c index b4d5ae9..74991c9 100644 --- a/arch/arm/mach-mx5/mx51_efika.c +++ b/arch/arm/mach-mx5/mx51_efika.c @@ -47,6 +47,7 @@ #include "devices-imx51.h" #include "devices.h" #include "efika.h" +#include "cpu_op-mx51.h" #define MX51_USB_CTRL_1_OFFSET 0x10 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) @@ -627,5 +628,9 @@ void __init efika_board_common_init(void) spi_register_board_info(mx51_efika_spi_board_info, ARRAY_SIZE(mx51_efika_spi_board_info)); imx51_add_ecspi(0, &mx51_efika_spi_pdata); + +#if defined(CONFIG_CPU_FREQ_IMX) + get_cpu_op = mx51_get_cpu_op; +#endif } -- cgit v0.10.2 From 102c91d8c60bc40e100ead62ac1e9ba05601510c Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Thu, 17 Feb 2011 15:31:32 +0100 Subject: mx51: add support for efika smartbook Signed-off-by: Arnaud Patard Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 1405464..026b681 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -128,6 +128,13 @@ config MACH_MX51_EFIKAMX Include support for Genesi Efika MX nettop. This includes specific configurations for the board and its peripherals. +config MACH_MX51_EFIKASB + bool "Support MX51 Genesi Efika Smartbook" + select MX51_EFIKA_COMMON + help + Include support for Genesi Efika Smartbook. This includes specific + configurations for the board and its peripherals. + config MACH_MX53_EVK bool "Support MX53 EVK platforms" select SOC_IMX53 diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 64f6b0d..4f63048 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -18,4 +18,5 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o +obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c new file mode 100644 index 0000000..18e29b9 --- /dev/null +++ b/arch/arm/mach-mx5/board-mx51_efikasb.c @@ -0,0 +1,283 @@ +/* + * Copyright (C) Arnaud Patard + * + * based on code from the following + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. + * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "devices-imx51.h" +#include "devices.h" +#include "efika.h" + +#define EFIKASB_USBH2_STP IMX_GPIO_NR(2, 20) +#define EFIKASB_GREEN_LED IMX_GPIO_NR(1, 3) +#define EFIKASB_WHITE_LED IMX_GPIO_NR(2, 25) +#define EFIKASB_PCBID0 IMX_GPIO_NR(2, 28) +#define EFIKASB_PCBID1 IMX_GPIO_NR(2, 29) +#define EFIKASB_PWRKEY IMX_GPIO_NR(2, 31) +#define EFIKASB_LID IMX_GPIO_NR(3, 14) +#define EFIKASB_POWEROFF IMX_GPIO_NR(4, 13) +#define EFIKASB_RFKILL IMX_GPIO_NR(3, 1) + +#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) + +static iomux_v3_cfg_t mx51efikasb_pads[] = { + /* USB HOST2 */ + MX51_PAD_EIM_D16__USBH2_DATA0, + MX51_PAD_EIM_D17__USBH2_DATA1, + MX51_PAD_EIM_D18__USBH2_DATA2, + MX51_PAD_EIM_D19__USBH2_DATA3, + MX51_PAD_EIM_D20__USBH2_DATA4, + MX51_PAD_EIM_D21__USBH2_DATA5, + MX51_PAD_EIM_D22__USBH2_DATA6, + MX51_PAD_EIM_D23__USBH2_DATA7, + MX51_PAD_EIM_A24__USBH2_CLK, + MX51_PAD_EIM_A25__USBH2_DIR, + MX51_PAD_EIM_A26__USBH2_STP, + MX51_PAD_EIM_A27__USBH2_NXT, + + /* leds */ + MX51_PAD_EIM_CS0__GPIO2_25, + MX51_PAD_GPIO1_3__GPIO1_3, + + /* pcb id */ + MX51_PAD_EIM_CS3__GPIO2_28, + MX51_PAD_EIM_CS4__GPIO2_29, + + /* lid */ + MX51_PAD_CSI1_VSYNC__GPIO3_14, + + /* power key*/ + MX51_PAD_PWRKEY, + + /* wifi/bt button */ + MX51_PAD_DI1_PIN12__GPIO3_1, + + /* power off */ + MX51_PAD_CSI2_VSYNC__GPIO4_13, + + /* wdog reset */ + MX51_PAD_GPIO1_4__WDOG1_WDOG_B, + + /* BT */ + MX51_PAD_EIM_A17__GPIO2_11, +}; + +static int initialize_usbh2_port(struct platform_device *pdev) +{ + iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP; + iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20; + + mxc_iomux_v3_setup_pad(usbh2gpio); + gpio_request(EFIKASB_USBH2_STP, "usbh2_stp"); + gpio_direction_output(EFIKASB_USBH2_STP, 0); + msleep(1); + gpio_set_value(EFIKASB_USBH2_STP, 1); + msleep(1); + + gpio_free(EFIKASB_USBH2_STP); + mxc_iomux_v3_setup_pad(usbh2stp); + + mdelay(10); + + return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); +} + +static struct mxc_usbh_platform_data usbh2_config = { + .init = initialize_usbh2_port, + .portsc = MXC_EHCI_MODE_ULPI, +}; + +static void __init mx51_efikasb_usb(void) +{ + usbh2_config.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT | + ULPI_OTG_EXTVBUSIND); + mxc_register_device(&mxc_usbh2_device, &usbh2_config); +} + +static struct gpio_led mx51_efikasb_leds[] = { + { + .name = "efikasb:green", + .default_trigger = "default-on", + .gpio = EFIKASB_GREEN_LED, + .active_low = 1, + }, + { + .name = "efikasb:white", + .default_trigger = "caps", + .gpio = EFIKASB_WHITE_LED, + }, +}; + +static struct gpio_led_platform_data mx51_efikasb_leds_data = { + .leds = mx51_efikasb_leds, + .num_leds = ARRAY_SIZE(mx51_efikasb_leds), +}; + +static struct platform_device mx51_efikasb_leds_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &mx51_efikasb_leds_data, + }, +}; + +static struct gpio_keys_button mx51_efikasb_keys[] = { + { + .code = KEY_POWER, + .gpio = EFIKASB_PWRKEY, + .type = EV_PWR, + .desc = "Power Button", + .wakeup = 1, + .debounce_interval = 10, /* ms */ + }, + { + .code = SW_LID, + .gpio = EFIKASB_LID, + .type = EV_SW, + .desc = "Lid Switch", + }, + { + /* SW_RFKILLALL vs KEY_RFKILL ? */ + .code = SW_RFKILL_ALL, + .gpio = EFIKASB_RFKILL, + .type = EV_SW, + .desc = "rfkill", + }, +}; + +static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = { + .buttons = mx51_efikasb_keys, + .nbuttons = ARRAY_SIZE(mx51_efikasb_keys), +}; + +static struct regulator *pwgt1, *pwgt2; + +static void mx51_efikasb_power_off(void) +{ + gpio_set_value(EFIKA_USB_PHY_RESET, 0); + + if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { + regulator_disable(pwgt2); + regulator_disable(pwgt1); + } + gpio_direction_output(EFIKASB_POWEROFF, 1); +} + +static int __init mx51_efikasb_power_init(void) +{ + if (machine_is_mx51_efikasb()) { + pwgt1 = regulator_get(NULL, "pwgt1"); + pwgt2 = regulator_get(NULL, "pwgt2"); + if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { + regulator_enable(pwgt1); + regulator_enable(pwgt2); + } + gpio_request(EFIKASB_POWEROFF, "poweroff"); + pm_power_off = mx51_efikasb_power_off; + + regulator_has_full_constraints(); + } + + return 0; +} +late_initcall(mx51_efikasb_power_init); + +/* 01 R1.3 board + 10 R2.0 board */ +static void __init mx51_efikasb_board_id(void) +{ + int id; + + gpio_request(EFIKASB_PCBID0, "pcb id0"); + gpio_direction_input(EFIKASB_PCBID0); + gpio_request(EFIKASB_PCBID1, "pcb id1"); + gpio_direction_input(EFIKASB_PCBID1); + + id = gpio_get_value(EFIKASB_PCBID0); + id |= gpio_get_value(EFIKASB_PCBID1) << 1; + + switch (id) { + default: + break; + case 1: + system_rev = 0x13; + break; + case 2: + system_rev = 0x20; + break; + } +} + +static void __init efikasb_board_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads, + ARRAY_SIZE(mx51efikasb_pads)); + efika_board_common_init(); + + mx51_efikasb_board_id(); + mx51_efikasb_usb(); + imx51_add_sdhci_esdhc_imx(1, NULL); + + platform_device_register(&mx51_efikasb_leds_device); + imx51_add_gpio_keys(&mx51_efikasb_keys_data); + +} + +static void __init mx51_efikasb_timer_init(void) +{ + mx51_clocks_init(32768, 24000000, 22579200, 24576000); +} + +static struct sys_timer mx51_efikasb_timer = { + .init = mx51_efikasb_timer_init, +}; + +MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook") + .boot_params = MX51_PHYS_OFFSET + 0x100, + .map_io = mx51_map_io, + .init_early = imx51_init_early, + .init_irq = mx51_init_irq, + .init_machine = efikasb_board_init, + .timer = &mx51_efikasb_timer, +MACHINE_END -- cgit v0.10.2 From 78c73591a91c120c4be02dafc018fcd7ecc8688a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 17 Feb 2011 18:09:52 -0200 Subject: ARM: mx5: Add watchdog support for MX53 Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index c66be0e..8164b1d 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -1336,6 +1336,8 @@ static struct clk_lookup mx53_lookups[] = { _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk) _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk) _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk) + _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk) + _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk) }; static void clk_tree_init(void) diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h index 8639735..9251008 100644 --- a/arch/arm/mach-mx5/devices-imx53.h +++ b/arch/arm/mach-mx5/devices-imx53.h @@ -29,3 +29,7 @@ imx53_sdhci_esdhc_imx_data[] __initconst; extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst; #define imx53_add_ecspi(id, pdata) \ imx_add_spi_imx(&imx53_ecspi_data[id], pdata) + +extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst; +#define imx53_add_imx2_wdt(id, pdata) \ + imx_add_imx2_wdt(&imx53_imx2_wdt_data[id]) diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index 8730cd1..ff55730 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c @@ -66,7 +66,7 @@ void __init imx53_init_early(void) { mxc_set_cpu_type(MXC_CPU_MX53); mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG_BASE_ADDR)); + mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR)); } int imx51_register_gpios(void); diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c index e0aec61..5e07ef2 100644 --- a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c +++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c @@ -53,6 +53,15 @@ const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX51 */ +#ifdef CONFIG_SOC_IMX53 +const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst = { +#define imx53_imx2_wdt_data_entry(_id, _hwid) \ + imx_imx2_wdt_data_entry(MX53, _id, _hwid, SZ_16K) + imx53_imx2_wdt_data_entry(0, 1), + imx53_imx2_wdt_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX53 */ + struct platform_device *__init imx_add_imx2_wdt( const struct imx_imx2_wdt_data *data) { diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index d7a8e52..ace1786 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -79,7 +79,7 @@ #define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000) #define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000) #define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000) -#define MX53_WDOG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000) +#define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000) #define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000) #define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000) #define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000) -- cgit v0.10.2 From daa7954ccd8a0e99376d52c46978f16067f8c2de Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 17 Feb 2011 18:09:53 -0200 Subject: ARM: mach-mx5: Add watchdog support for MX53 based boards Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 026b681..6466d73 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -138,6 +138,7 @@ config MACH_MX51_EFIKASB config MACH_MX53_EVK bool "Support MX53 EVK platforms" select SOC_IMX53 + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX @@ -149,6 +150,7 @@ config MACH_MX53_EVK config MACH_MX53_SMD bool "Support MX53 SMD platforms" select SOC_IMX53 + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_UART help Include support for MX53 SMD platform. This includes specific @@ -157,6 +159,7 @@ config MACH_MX53_SMD config MACH_MX53_LOCO bool "Support MX53 LOCO platforms" select SOC_IMX53 + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_UART help Include support for MX53 LOCO platform. This includes specific diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c index 8ed316b..652e1e0 100644 --- a/arch/arm/mach-mx5/board-mx53_evk.c +++ b/arch/arm/mach-mx5/board-mx53_evk.c @@ -137,6 +137,7 @@ static void __init mx53_evk_board_init(void) spi_register_board_info(mx53_evk_spi_board_info, ARRAY_SIZE(mx53_evk_spi_board_info)); imx53_add_ecspi(0, &mx53_evk_spi_data); + imx53_add_imx2_wdt(0, NULL); } static void __init mx53_evk_timer_init(void) diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c index 0fea252..6005f49 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c @@ -69,6 +69,7 @@ static void __init mx53_loco_board_init(void) imx53_add_imx_uart(0, NULL); mx53_loco_fec_reset(); imx53_add_fec(&mx53_loco_fec_data); + imx53_add_imx2_wdt(0, NULL); } static void __init mx53_loco_timer_init(void) diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c index fa0fad8..8a8694c 100644 --- a/arch/arm/mach-mx5/board-mx53_smd.c +++ b/arch/arm/mach-mx5/board-mx53_smd.c @@ -90,6 +90,7 @@ static void __init mx53_smd_board_init(void) mx53_smd_init_uart(); mx53_smd_fec_reset(); imx53_add_fec(&mx53_smd_fec_data); + imx53_add_imx2_wdt(0, NULL); } static void __init mx53_smd_timer_init(void) -- cgit v0.10.2 From 6388b96e84712a2cc045e8371eabd7312ee12fc4 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Fri, 18 Feb 2011 12:36:14 +0800 Subject: ARM: imx53_loco: add all pad configure. Signed-off-by: Richard Zhao Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c index 6005f49..3d749ad 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c @@ -39,8 +39,145 @@ #define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) static iomux_v3_cfg_t mx53_loco_pads[] = { + /* FEC */ + MX53_PAD_FEC_MDC__FEC_MDC, + MX53_PAD_FEC_MDIO__FEC_MDIO, + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, + MX53_PAD_FEC_RX_ER__FEC_RX_ER, + MX53_PAD_FEC_CRS_DV__FEC_RX_DV, + MX53_PAD_FEC_RXD1__FEC_RDATA_1, + MX53_PAD_FEC_RXD0__FEC_RDATA_0, + MX53_PAD_FEC_TX_EN__FEC_TX_EN, + MX53_PAD_FEC_TXD1__FEC_TDATA_1, + MX53_PAD_FEC_TXD0__FEC_TDATA_0, + /* FEC_nRST */ + MX53_PAD_PATA_DA_0__GPIO7_6, + /* FEC_nINT */ + MX53_PAD_PATA_DATA4__GPIO2_4, + /* AUDMUX5 */ + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC, + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD, + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS, + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD, + /* I2C2 */ + MX53_PAD_KEY_COL3__I2C2_SCL, + MX53_PAD_KEY_ROW3__I2C2_SDA, + /* SD1 */ + MX53_PAD_SD1_CMD__ESDHC1_CMD, + MX53_PAD_SD1_CLK__ESDHC1_CLK, + MX53_PAD_SD1_DATA0__ESDHC1_DAT0, + MX53_PAD_SD1_DATA1__ESDHC1_DAT1, + MX53_PAD_SD1_DATA2__ESDHC1_DAT2, + MX53_PAD_SD1_DATA3__ESDHC1_DAT3, + /* SD3 */ + MX53_PAD_PATA_DATA8__ESDHC3_DAT0, + MX53_PAD_PATA_DATA9__ESDHC3_DAT1, + MX53_PAD_PATA_DATA10__ESDHC3_DAT2, + MX53_PAD_PATA_DATA11__ESDHC3_DAT3, + MX53_PAD_PATA_DATA0__ESDHC3_DAT4, + MX53_PAD_PATA_DATA1__ESDHC3_DAT5, + MX53_PAD_PATA_DATA2__ESDHC3_DAT6, + MX53_PAD_PATA_DATA3__ESDHC3_DAT7, + MX53_PAD_PATA_IORDY__ESDHC3_CLK, + MX53_PAD_PATA_RESET_B__ESDHC3_CMD, + /* SD3_CD */ + MX53_PAD_EIM_DA11__GPIO3_11, + /* SD3_WP */ + MX53_PAD_EIM_DA12__GPIO3_12, + /* VGA */ + MX53_PAD_EIM_OE__IPU_DI1_PIN7, + MX53_PAD_EIM_RW__IPU_DI1_PIN8, + /* DISPLB */ + MX53_PAD_EIM_D20__IPU_SER_DISP0_CS, + MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK, + MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN, + MX53_PAD_EIM_D23__IPU_DI0_D0_CS, + /* DISP0_POWER_EN */ + MX53_PAD_EIM_D24__GPIO3_24, + /* DISP0 DET INT */ + MX53_PAD_EIM_D31__GPIO3_31, + /* LVDS */ + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3, + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK, + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2, + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1, + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0, + MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3, + MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2, + MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK, + MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1, + MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0, + /* I2C1 */ + MX53_PAD_CSI0_DAT8__I2C1_SDA, + MX53_PAD_CSI0_DAT9__I2C1_SCL, + /* UART1 */ MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, + /* CSI0 */ + MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12, + MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13, + MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14, + MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15, + MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16, + MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17, + MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18, + MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19, + MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC, + MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC, + MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK, + /* DISPLAY */ + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK, + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15, + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2, + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3, + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0, + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1, + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2, + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3, + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4, + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5, + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6, + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7, + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8, + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9, + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10, + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11, + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12, + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13, + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14, + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15, + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16, + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17, + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18, + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19, + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20, + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21, + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22, + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23, + /* Audio CLK*/ + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK, + /* PWM */ + MX53_PAD_GPIO_1__PWM2_PWMO, + /* SPDIF */ + MX53_PAD_GPIO_7__SPDIF_PLOCK, + MX53_PAD_GPIO_17__SPDIF_OUT1, + /* GPIO */ + MX53_PAD_PATA_DA_1__GPIO7_7, + MX53_PAD_PATA_DA_2__GPIO7_8, + MX53_PAD_PATA_DATA5__GPIO2_5, + MX53_PAD_PATA_DATA6__GPIO2_6, + MX53_PAD_PATA_DATA14__GPIO2_14, + MX53_PAD_PATA_DATA15__GPIO2_15, + MX53_PAD_PATA_INTRQ__GPIO7_2, + MX53_PAD_EIM_WAIT__GPIO5_0, + MX53_PAD_NANDF_WP_B__GPIO6_9, + MX53_PAD_NANDF_RB0__GPIO6_10, + MX53_PAD_NANDF_CS1__GPIO6_14, + MX53_PAD_NANDF_CS2__GPIO6_15, + MX53_PAD_NANDF_CS3__GPIO6_16, + MX53_PAD_GPIO_5__GPIO1_5, + MX53_PAD_GPIO_16__GPIO7_11, + MX53_PAD_GPIO_8__GPIO1_8, }; static inline void mx53_loco_fec_reset(void) -- cgit v0.10.2 From c4e942b76414367d034640835a0fcbab5d0cc434 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Fri, 18 Feb 2011 12:36:15 +0800 Subject: ARM: imx53_loco add uncompress print Signed-off-by: Richard Zhao Signed-off-by: Sascha Hauer diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index e634d6c..b702884 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -111,6 +111,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) uart_base = MX50_UART1_BASE_ADDR; break; case MACH_TYPE_MX53_EVK: + case MACH_TYPE_MX53_LOCO: uart_base = MX53_UART1_BASE_ADDR; break; default: -- cgit v0.10.2 From 942b99f3a0497a9a53df82ad685082b2980fe75d Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Fri, 18 Feb 2011 12:36:16 +0800 Subject: ARM: imx53_loco: add i2c device support Signed-off-by: Richard Zhao Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 6466d73..f065a0d 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -160,6 +160,7 @@ config MACH_MX53_LOCO bool "Support MX53 LOCO platforms" select SOC_IMX53 select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART help Include support for MX53 LOCO platform. This includes specific diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c index 3d749ad..160899e 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c @@ -199,6 +199,10 @@ static struct fec_platform_data mx53_loco_fec_data = { .phy = PHY_INTERFACE_MODE_RMII, }; +static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = { + .bitrate = 100000, +}; + static void __init mx53_loco_board_init(void) { mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads, @@ -207,6 +211,8 @@ static void __init mx53_loco_board_init(void) mx53_loco_fec_reset(); imx53_add_fec(&mx53_loco_fec_data); imx53_add_imx2_wdt(0, NULL); + imx53_add_imx_i2c(0, &mx53_loco_i2c_data); + imx53_add_imx_i2c(1, &mx53_loco_i2c_data); } static void __init mx53_loco_timer_init(void) -- cgit v0.10.2 From b807afe41ceefef11a0d965cd9970142afc53d25 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Fri, 18 Feb 2011 12:36:17 +0800 Subject: ARM: imx50: correct iomux-mx50.h wrong daisy chain settings Most fix is for uart txd/cts. They don't need to select input. And fix some other pads with wrong select input. Signed-off-by: Richard Zhao Signed-off-by: Sascha Hauer diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx50.h b/arch/arm/plat-mxc/include/mach/iomux-mx50.h index 058a922..98e7fd0 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx50.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx50.h @@ -86,7 +86,7 @@ #define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \ MX50_I2C_PAD_CTRL) #define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C1_SCL__UART2_TXD IOMUX_PAD(0x2EC, 0x40, 2, 0x7cc, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_I2C1_SCL__UART2_TXD IOMUX_PAD(0x2EC, 0x40, 2, 0x0, 0, MX50_UART_PAD_CTRL) #define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \ MX50_I2C_PAD_CTRL) @@ -96,7 +96,7 @@ #define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \ MX50_I2C_PAD_CTRL) #define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x48, 2, 0x7c8, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x48, 2, 0x0, 0, MX50_UART_PAD_CTRL) #define MX50_PAD_I2C2_SCL__DCDC_OK IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \ @@ -172,7 +172,7 @@ #define MX50_PAD_SSI_RXFS__AUD3_RXFS IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXFS__UART5_TXD IOMUX_PAD(0x328, 0x7C, 2, 0x7e4, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__UART5_TXD IOMUX_PAD(0x328, 0x7C, 2, 0x0, 0, MX50_UART_PAD_CTRL) #define MX50_PAD_SSI_RXFS__WEIM_D6 IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL) #define MX50_PAD_SSI_RXFS__CSPI_SS2 IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD) #define MX50_PAD_SSI_RXFS__FEC_COL IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH) @@ -186,25 +186,25 @@ #define MX50_PAD_SSI_RXC__FEC_RX_CLK IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL) #define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL) -#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x7c4, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x0, 0, MX50_UART_PAD_CTRL) #define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL) #define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x7c0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x0, 0, MX50_UART_PAD_CTRL) #define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART1_CTS__UART5_TXD IOMUX_PAD(0x338, 0x8C, 2, 0x7e4, 2, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_CTS__UART5_TXD IOMUX_PAD(0x338, 0x8C, 2, 0x0, 0, MX50_UART_PAD_CTRL) #define MX50_PAD_UART1_CTS__SD4_D4 IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL) #define MX50_PAD_UART1_CTS__SD4_CMD IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL) #define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL) #define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_UART1_RTS__UART5_RXD IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_RTS__SD4_D5 IOMUX_PAD(0x33C, 0x90, 4, 0x0, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART1_RTS__SD4_CLK IOMUX_PAD(0x33C, 0x90, 5, 0x0, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART1_RTS__SD4_D5 IOMUX_PAD(0x33C, 0x90, 4, 0x764, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART1_RTS__SD4_CLK IOMUX_PAD(0x33C, 0x90, 5, 0x748, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x7cc, 2, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x0, 0, MX50_UART_PAD_CTRL) #define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_UART2_TXD__SD4_D6 IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL) #define MX50_PAD_UART2_TXD__SD4_D4 IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL) @@ -214,7 +214,7 @@ #define MX50_PAD_UART2_RXD__SD4_D7 IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL) #define MX50_PAD_UART2_RXD__SD4_D5 IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x7c8, 2, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x0, 0, MX50_UART_PAD_CTRL) #define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_UART2_CTS__SD4_CMD IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL) #define MX50_PAD_UART2_CTS__SD4_D6 IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL) @@ -224,7 +224,7 @@ #define MX50_PAD_UART2_RTS__SD4_CLK IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL) #define MX50_PAD_UART2_RTS__SD4_D7 IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x350, 0xA4, 0, 0x7d4, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x350, 0xA4, 0, 0x0, 0, MX50_UART_PAD_CTRL) #define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_UART3_TXD__SD1_D4 IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL) #define MX50_PAD_UART3_TXD__SD4_D0 IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL) @@ -238,9 +238,9 @@ #define MX50_PAD_UART3_RXD__SD2_CD IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL) #define MX50_PAD_UART3_RXD__WEIM_D13 IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL) -#define MX50_PAD_UART4_TXD__UART4_TXD IOMUX_PAD(0x358, 0xAC, 0, 0x7dc, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART4_TXD__UART4_TXD IOMUX_PAD(0x358, 0xAC, 0, 0x0, 0, MX50_UART_PAD_CTRL) #define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0xAC, 2, 0x7d0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0xAC, 2, 0x0, 0, MX50_UART_PAD_CTRL) #define MX50_PAD_UART4_TXD__SD1_D6 IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL) #define MX50_PAD_UART4_TXD__SD4_D2 IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL) #define MX50_PAD_UART4_TXD__SD2_LCTL IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL) @@ -278,7 +278,7 @@ #define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD) #define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0xC8, 4, 0x7d0, 3, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0xC8, 4, 0x0, 0, MX50_UART_PAD_CTRL) #define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7 IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_ECSPI1_MOSI__WEIM_D9 IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL) @@ -294,7 +294,7 @@ #define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) #define MX50_PAD_ECSPI1_SS0__CSPI_SS3 IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD) #define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0xD0, 4, 0x7d8, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0xD0, 4, 0x0, 0, MX50_UART_PAD_CTRL) #define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9 IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_ECSPI1_SS0__WEIM_D11 IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL) @@ -311,17 +311,17 @@ #define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0xD8, 4, 0x7e0, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0xD8, 4, 0x0, 0, MX50_UART_PAD_CTRL) #define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5 IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_ECSPI2_MOSI__WEIM_D9 IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0xDC, 0, 0x73c, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0xDC, 0, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) #define MX50_PAD_ECSPI2_MISO__ELCDIF_RS IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI2_MISO__UART5_TXD IOMUX_PAD(0x388, 0xDC, 4, 0x7e4, 4, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0xDC, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__UART5_TXD IOMUX_PAD(0x388, 0xDC, 4, 0x0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0xDC, 5, 0x73c, 0, NO_PAD_CTRL) #define MX50_PAD_ECSPI2_MISO__NANDF_CEN6 IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_ECSPI2_MISO__WEIM_D10 IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL) @@ -503,7 +503,7 @@ #define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL) #define MX50_PAD_DISP_RD__WEIM_A25 IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, 0x73c, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) #define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL) #define MX50_PAD_DISP_RS__WEIM_A26 IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL) @@ -691,8 +691,8 @@ #define MX50_PAD_EPDC_D9__EPDC_D9 IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D9__WEIM_D9 IOMUX_PAD(0x570, 0x1D4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D9__ELCDIF_D25 IOMUX_PAD(0x570, 0x1D4, 3, 0x810, 2, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D9__WEIM_D9 IOMUX_PAD(0x570, 0x1D4, 2, 0x810, 2, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__ELCDIF_D25 IOMUX_PAD(0x570, 0x1D4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) #define MX50_PAD_EPDC_D10__EPDC_D10 IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL) #define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL) -- cgit v0.10.2 From 646e610d403e1ad977530c1b0a87dabc8293b5ef Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 21 Feb 2011 14:28:10 +0800 Subject: ARM: imx53_smd add uncompress print Signed-off-by: Frank Li Signed-off-by: Sascha Hauer diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index b702884..7412558 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -112,6 +112,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) break; case MACH_TYPE_MX53_EVK: case MACH_TYPE_MX53_LOCO: + case MACH_TYPE_MX53_SMD: uart_base = MX53_UART1_BASE_ADDR; break; default: -- cgit v0.10.2 From 503e1639654b5a7ef80557985fef8a36a785b9e1 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Fri, 18 Feb 2011 20:26:30 +0800 Subject: ARM: imx53: correct Silicon Revision definition following fuse map Signed-off-by: Richard Zhao Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index d40671d..df46b5e 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -78,11 +78,16 @@ static int get_mx53_srev(void) void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR); u32 rev = readl(iim_base + IIM_SREV) & 0xff; - if (rev == 0x0) + switch (rev) { + case 0x0: return IMX_CHIP_REVISION_1_0; - else if (rev == 0x10) + case 0x2: return IMX_CHIP_REVISION_2_0; - return 0; + case 0x3: + return IMX_CHIP_REVISION_2_1; + default: + return IMX_CHIP_REVISION_UNKNOWN; + } } /* -- cgit v0.10.2 From 510dc2ec6849f1ca8ab829b8149d08b955db381b Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Tue, 22 Feb 2011 18:13:22 +0800 Subject: ARM: imx53: add sdhc pad settings Signed-off-by: Richard Zhao Signed-off-by: Sascha Hauer diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h index bae7fd0..e95d9cb 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h @@ -27,6 +27,9 @@ #define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) #define _MX53_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x348, 0x20, 0, 0x840, 0, 0) #define _MX53_PAD_GPIO_19__GPIO4_5 IOMUX_PAD(0x348, 0x20, 1, 0x0, 0, 0) @@ -2057,13 +2060,13 @@ #define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 (_MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B (_MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_RESET_B__GPIO7_4 (_MX53_PAD_PATA_RESET_B__GPIO7_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD (_MX53_PAD_PATA_RESET_B__ESDHC3_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD (_MX53_PAD_PATA_RESET_B__ESDHC3_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_RESET_B__UART1_CTS (_MX53_PAD_PATA_RESET_B__UART1_CTS | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_RESET_B__CAN2_TXCAN (_MX53_PAD_PATA_RESET_B__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 (_MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_IORDY__PATA_IORDY (_MX53_PAD_PATA_IORDY__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_IORDY__GPIO7_5 (_MX53_PAD_PATA_IORDY__GPIO7_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_IORDY__ESDHC3_CLK (_MX53_PAD_PATA_IORDY__ESDHC3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_IORDY__ESDHC3_CLK (_MX53_PAD_PATA_IORDY__ESDHC3_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_IORDY__UART1_RTS (_MX53_PAD_PATA_IORDY__UART1_RTS | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_IORDY__CAN2_RXCAN (_MX53_PAD_PATA_IORDY__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 (_MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -2074,12 +2077,12 @@ #define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 (_MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DA_1__PATA_DA_1 (_MX53_PAD_PATA_DA_1__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DA_1__GPIO7_7 (_MX53_PAD_PATA_DA_1__GPIO7_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DA_1__ESDHC4_CMD (_MX53_PAD_PATA_DA_1__ESDHC4_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_1__ESDHC4_CMD (_MX53_PAD_PATA_DA_1__ESDHC4_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DA_1__UART3_CTS (_MX53_PAD_PATA_DA_1__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) #define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 (_MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DA_2__PATA_DA_2 (_MX53_PAD_PATA_DA_2__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DA_2__GPIO7_8 (_MX53_PAD_PATA_DA_2__GPIO7_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DA_2__ESDHC4_CLK (_MX53_PAD_PATA_DA_2__ESDHC4_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_2__ESDHC4_CLK (_MX53_PAD_PATA_DA_2__ESDHC4_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DA_2__UART3_RTS (_MX53_PAD_PATA_DA_2__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) #define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 (_MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_CS_0__PATA_CS_0 (_MX53_PAD_PATA_CS_0__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -2093,124 +2096,124 @@ #define MX53_PAD_PATA_DATA0__PATA_DATA_0 (_MX53_PAD_PATA_DATA0__PATA_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA0__GPIO2_0 (_MX53_PAD_PATA_DATA0__GPIO2_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 (_MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 (_MX53_PAD_PATA_DATA0__ESDHC3_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 (_MX53_PAD_PATA_DATA0__ESDHC3_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 (_MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 (_MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 (_MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA1__PATA_DATA_1 (_MX53_PAD_PATA_DATA1__PATA_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA1__GPIO2_1 (_MX53_PAD_PATA_DATA1__GPIO2_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 (_MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 (_MX53_PAD_PATA_DATA1__ESDHC3_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 (_MX53_PAD_PATA_DATA1__ESDHC3_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 (_MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 (_MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA2__PATA_DATA_2 (_MX53_PAD_PATA_DATA2__PATA_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA2__GPIO2_2 (_MX53_PAD_PATA_DATA2__GPIO2_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 (_MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 (_MX53_PAD_PATA_DATA2__ESDHC3_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 (_MX53_PAD_PATA_DATA2__ESDHC3_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 (_MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 (_MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA3__PATA_DATA_3 (_MX53_PAD_PATA_DATA3__PATA_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA3__GPIO2_3 (_MX53_PAD_PATA_DATA3__GPIO2_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 (_MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 (_MX53_PAD_PATA_DATA3__ESDHC3_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 (_MX53_PAD_PATA_DATA3__ESDHC3_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 (_MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 (_MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA4__PATA_DATA_4 (_MX53_PAD_PATA_DATA4__PATA_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA4__GPIO2_4 (_MX53_PAD_PATA_DATA4__GPIO2_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 (_MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 (_MX53_PAD_PATA_DATA4__ESDHC4_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 (_MX53_PAD_PATA_DATA4__ESDHC4_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 (_MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 (_MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA5__PATA_DATA_5 (_MX53_PAD_PATA_DATA5__PATA_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA5__GPIO2_5 (_MX53_PAD_PATA_DATA5__GPIO2_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 (_MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 (_MX53_PAD_PATA_DATA5__ESDHC4_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 (_MX53_PAD_PATA_DATA5__ESDHC4_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 (_MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 (_MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA6__PATA_DATA_6 (_MX53_PAD_PATA_DATA6__PATA_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA6__GPIO2_6 (_MX53_PAD_PATA_DATA6__GPIO2_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 (_MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 (_MX53_PAD_PATA_DATA6__ESDHC4_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 (_MX53_PAD_PATA_DATA6__ESDHC4_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 (_MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 (_MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA7__PATA_DATA_7 (_MX53_PAD_PATA_DATA7__PATA_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA7__GPIO2_7 (_MX53_PAD_PATA_DATA7__GPIO2_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 (_MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 (_MX53_PAD_PATA_DATA7__ESDHC4_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 (_MX53_PAD_PATA_DATA7__ESDHC4_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 (_MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 (_MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA8__PATA_DATA_8 (_MX53_PAD_PATA_DATA8__PATA_DATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA8__GPIO2_8 (_MX53_PAD_PATA_DATA8__GPIO2_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 (_MX53_PAD_PATA_DATA8__ESDHC1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 (_MX53_PAD_PATA_DATA8__ESDHC1_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 (_MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 (_MX53_PAD_PATA_DATA8__ESDHC3_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 (_MX53_PAD_PATA_DATA8__ESDHC3_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 (_MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 (_MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA9__PATA_DATA_9 (_MX53_PAD_PATA_DATA9__PATA_DATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA9__GPIO2_9 (_MX53_PAD_PATA_DATA9__GPIO2_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 (_MX53_PAD_PATA_DATA9__ESDHC1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 (_MX53_PAD_PATA_DATA9__ESDHC1_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 (_MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 (_MX53_PAD_PATA_DATA9__ESDHC3_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 (_MX53_PAD_PATA_DATA9__ESDHC3_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 (_MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 (_MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA10__PATA_DATA_10 (_MX53_PAD_PATA_DATA10__PATA_DATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA10__GPIO2_10 (_MX53_PAD_PATA_DATA10__GPIO2_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 (_MX53_PAD_PATA_DATA10__ESDHC1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 (_MX53_PAD_PATA_DATA10__ESDHC1_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 (_MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 (_MX53_PAD_PATA_DATA10__ESDHC3_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 (_MX53_PAD_PATA_DATA10__ESDHC3_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 (_MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 (_MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA11__PATA_DATA_11 (_MX53_PAD_PATA_DATA11__PATA_DATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA11__GPIO2_11 (_MX53_PAD_PATA_DATA11__GPIO2_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 (_MX53_PAD_PATA_DATA11__ESDHC1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 (_MX53_PAD_PATA_DATA11__ESDHC1_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 (_MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 (_MX53_PAD_PATA_DATA11__ESDHC3_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 (_MX53_PAD_PATA_DATA11__ESDHC3_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 (_MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 (_MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA12__PATA_DATA_12 (_MX53_PAD_PATA_DATA12__PATA_DATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA12__GPIO2_12 (_MX53_PAD_PATA_DATA12__GPIO2_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 (_MX53_PAD_PATA_DATA12__ESDHC2_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 (_MX53_PAD_PATA_DATA12__ESDHC2_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 (_MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 (_MX53_PAD_PATA_DATA12__ESDHC4_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 (_MX53_PAD_PATA_DATA12__ESDHC4_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 (_MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 (_MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA13__PATA_DATA_13 (_MX53_PAD_PATA_DATA13__PATA_DATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA13__GPIO2_13 (_MX53_PAD_PATA_DATA13__GPIO2_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 (_MX53_PAD_PATA_DATA13__ESDHC2_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 (_MX53_PAD_PATA_DATA13__ESDHC2_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 (_MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 (_MX53_PAD_PATA_DATA13__ESDHC4_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 (_MX53_PAD_PATA_DATA13__ESDHC4_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 (_MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 (_MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA14__PATA_DATA_14 (_MX53_PAD_PATA_DATA14__PATA_DATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA14__GPIO2_14 (_MX53_PAD_PATA_DATA14__GPIO2_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 (_MX53_PAD_PATA_DATA14__ESDHC2_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 (_MX53_PAD_PATA_DATA14__ESDHC2_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 (_MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 (_MX53_PAD_PATA_DATA14__ESDHC4_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 (_MX53_PAD_PATA_DATA14__ESDHC4_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 (_MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 (_MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA15__PATA_DATA_15 (_MX53_PAD_PATA_DATA15__PATA_DATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA15__GPIO2_15 (_MX53_PAD_PATA_DATA15__GPIO2_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 (_MX53_PAD_PATA_DATA15__ESDHC2_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 (_MX53_PAD_PATA_DATA15__ESDHC2_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 (_MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 (_MX53_PAD_PATA_DATA15__ESDHC4_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 (_MX53_PAD_PATA_DATA15__ESDHC4_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 (_MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 (_MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 (_MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 (_MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_SD1_DATA0__GPIO1_16 (_MX53_PAD_SD1_DATA0__GPIO1_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_DATA0__GPT_CAPIN1 (_MX53_PAD_SD1_DATA0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_DATA0__CSPI_MISO (_MX53_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP (_MX53_PAD_SD1_DATA0__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 (_MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 (_MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_SD1_DATA1__GPIO1_17 (_MX53_PAD_SD1_DATA1__GPIO1_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_DATA1__GPT_CAPIN2 (_MX53_PAD_SD1_DATA1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_DATA1__CSPI_SS0 (_MX53_PAD_SD1_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP (_MX53_PAD_SD1_DATA1__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_CMD__ESDHC1_CMD (_MX53_PAD_SD1_CMD__ESDHC1_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CMD__ESDHC1_CMD (_MX53_PAD_SD1_CMD__ESDHC1_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_SD1_CMD__GPIO1_18 (_MX53_PAD_SD1_CMD__GPIO1_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_CMD__GPT_CMPOUT1 (_MX53_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_CMD__CSPI_MOSI (_MX53_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_CMD__CCM_PLL1_BYP (_MX53_PAD_SD1_CMD__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 (_MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 (_MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_SD1_DATA2__GPIO1_19 (_MX53_PAD_SD1_DATA2__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 (_MX53_PAD_SD1_DATA2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_DATA2__PWM2_PWMO (_MX53_PAD_SD1_DATA2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -2218,13 +2221,13 @@ #define MX53_PAD_SD1_DATA2__CSPI_SS1 (_MX53_PAD_SD1_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP (_MX53_PAD_SD1_DATA2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_CLK__ESDHC1_CLK (_MX53_PAD_SD1_CLK__ESDHC1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CLK__ESDHC1_CLK (_MX53_PAD_SD1_CLK__ESDHC1_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_SD1_CLK__GPIO1_20 (_MX53_PAD_SD1_CLK__GPIO1_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_CLK__OSC32k_32K_OUT (_MX53_PAD_SD1_CLK__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_CLK__GPT_CLKIN (_MX53_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_CLK__CSPI_SCLK (_MX53_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 (_MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 (_MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 (_MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_SD1_DATA3__GPIO1_21 (_MX53_PAD_SD1_DATA3__GPIO1_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 (_MX53_PAD_SD1_DATA3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_DATA3__PWM1_PWMO (_MX53_PAD_SD1_DATA3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -2232,37 +2235,37 @@ #define MX53_PAD_SD1_DATA3__CSPI_SS2 (_MX53_PAD_SD1_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 (_MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_CLK__ESDHC2_CLK (_MX53_PAD_SD2_CLK__ESDHC2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CLK__ESDHC2_CLK (_MX53_PAD_SD2_CLK__ESDHC2_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_SD2_CLK__GPIO1_10 (_MX53_PAD_SD2_CLK__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_CLK__KPP_COL_5 (_MX53_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS (_MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_CLK__CSPI_SCLK (_MX53_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_CLK__SCC_RANDOM_V (_MX53_PAD_SD2_CLK__SCC_RANDOM_V | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_CMD__ESDHC2_CMD (_MX53_PAD_SD2_CMD__ESDHC2_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CMD__ESDHC2_CMD (_MX53_PAD_SD2_CMD__ESDHC2_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_SD2_CMD__GPIO1_11 (_MX53_PAD_SD2_CMD__GPIO1_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_CMD__KPP_ROW_5 (_MX53_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC (_MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_CMD__CSPI_MOSI (_MX53_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_CMD__SCC_RANDOM (_MX53_PAD_SD2_CMD__SCC_RANDOM | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 (_MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 (_MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_SD2_DATA3__GPIO1_12 (_MX53_PAD_SD2_DATA3__GPIO1_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_DATA3__KPP_COL_6 (_MX53_PAD_SD2_DATA3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC (_MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_DATA3__CSPI_SS2 (_MX53_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_DATA3__SJC_DONE (_MX53_PAD_SD2_DATA3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 (_MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 (_MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_SD2_DATA2__GPIO1_13 (_MX53_PAD_SD2_DATA2__GPIO1_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_DATA2__KPP_ROW_6 (_MX53_PAD_SD2_DATA2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD (_MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_DATA2__CSPI_SS1 (_MX53_PAD_SD2_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_DATA2__SJC_FAIL (_MX53_PAD_SD2_DATA2__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 (_MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 (_MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_SD2_DATA1__GPIO1_14 (_MX53_PAD_SD2_DATA1__GPIO1_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_DATA1__KPP_COL_7 (_MX53_PAD_SD2_DATA1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS (_MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_DATA1__CSPI_SS0 (_MX53_PAD_SD2_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO (_MX53_PAD_SD2_DATA1__RTIC_SEC_VIO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 (_MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 (_MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) #define MX53_PAD_SD2_DATA0__GPIO1_15 (_MX53_PAD_SD2_DATA0__GPIO1_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_DATA0__KPP_ROW_7 (_MX53_PAD_SD2_DATA0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD (_MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -- cgit v0.10.2 From ddb95fdd25d38a53eb3d227cc1a21f997d3bef7d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 22 Feb 2011 20:24:13 -0300 Subject: ARM: imx/mach-mx25_3ds: Use IMX_GPIO_NR instead of hard-coded values Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c index aafc6f7..66b6cdd 100644 --- a/arch/arm/mach-imx/mach-mx25_3ds.c +++ b/arch/arm/mach-imx/mach-mx25_3ds.c @@ -109,8 +109,8 @@ static const struct fec_platform_data mx25_fec_pdata __initconst = { .phy = PHY_INTERFACE_MODE_RMII, }; -#define FEC_ENABLE_GPIO 35 -#define FEC_RESET_B_GPIO 104 +#define FEC_ENABLE_GPIO IMX_GPIO_NR(2, 3) +#define FEC_RESET_B_GPIO IMX_GPIO_NR(4, 8) static void __init mx25pdk_fec_reset(void) { -- cgit v0.10.2 From b03b2a7a2007e4122ec105b54580327d4126e000 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 23 Feb 2011 16:06:55 +0800 Subject: ARM: mx51_defconfig: change CONFIG_LEDS_CLASS 'm' to 'y' This patch is to fix the warning below. arch/arm/configs/mx51_defconfig:113:warning: symbol value 'm' invalid for LEDS_CLASS Signed-off-by: Shawn Guo Signed-off-by: Sascha Hauer diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig index 9cba68c..e3c9032 100644 --- a/arch/arm/configs/mx51_defconfig +++ b/arch/arm/configs/mx51_defconfig @@ -110,7 +110,7 @@ CONFIG_MMC=y CONFIG_MMC_BLOCK=m CONFIG_MMC_SDHCI=m CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=m +CONFIG_LEDS_CLASS=y CONFIG_RTC_CLASS=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_EXT2_FS=y -- cgit v0.10.2 From ea7ee4cae4db6630b388f39c3abe4f86f67211f9 Mon Sep 17 00:00:00 2001 From: Denis 'GNUtoo' Carikli Date: Fri, 18 Feb 2011 22:22:23 +0100 Subject: mx31: add support for the bugbase 1.3 from buglabs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Note that the hardware schematics and documentations can be obtained here: http://www.bugcommunity.com/wiki/index.php/BUGbase Signed-off-by: Denis 'GNUtoo' Carikli Acked-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index de80d98..4f57f13 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -199,6 +199,15 @@ config MACH_KZM_ARM11_01 Include support for KZM-ARM11-01. This includes specific configurations for the board and its peripherals. +config MACH_BUG + bool "Support Buglabs BUGBase platform" + select SOC_IMX31 + select IMX_HAVE_PLATFORM_IMX_UART + default y + help + Include support for BUGBase 1.3 platform. This includes specific + configurations for the board and its peripherals. + config MACH_EUKREA_CPUIMX35 bool "Support Eukrea CPUIMX35 Platform" select SOC_IMX35 diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 224d07a..a54faf2 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o +obj-$(CONFIG_MACH_BUG) += mach-bug.o obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd-baseboard.o obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o diff --git a/arch/arm/mach-mx3/mach-bug.c b/arch/arm/mach-mx3/mach-bug.c new file mode 100644 index 0000000..d137d70 --- /dev/null +++ b/arch/arm/mach-mx3/mach-bug.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "devices-imx31.h" + +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static const unsigned int bug_pins[] __initconst = { + MX31_PIN_PC_RST__CTS5, + MX31_PIN_PC_VS2__RTS5, + MX31_PIN_PC_BVD2__TXD5, + MX31_PIN_PC_BVD1__RXD5, +}; + +static void __init bug_board_init(void) +{ + mxc_iomux_setup_multiple_pins(bug_pins, + ARRAY_SIZE(bug_pins), "uart-4"); + imx31_add_imx_uart4(&uart_pdata); +} + +static void __init bug_timer_init(void) +{ + mx31_clocks_init(26000000); +} + +static struct sys_timer bug_timer = { + .init = bug_timer_init, +}; + +MACHINE_START(BUG, "BugLabs BUGBase") + .map_io = mx31_map_io, + .init_early = imx31_init_early, + .init_irq = mx31_init_irq, + .timer = &bug_timer, + .init_machine = bug_board_init, +MACHINE_END diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index 7412558..4864b0a 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -62,6 +62,7 @@ static inline void flush(void) #define MX2X_UART1_BASE_ADDR 0x1000a000 #define MX3X_UART1_BASE_ADDR 0x43F90000 #define MX3X_UART2_BASE_ADDR 0x43F94000 +#define MX3X_UART5_BASE_ADDR 0x43FB4000 #define MX51_UART1_BASE_ADDR 0x73fbc000 #define MX50_UART1_BASE_ADDR 0x53fbc000 #define MX53_UART1_BASE_ADDR 0x53fbc000 @@ -102,6 +103,9 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) case MACH_TYPE_MAGX_ZN5: uart_base = MX3X_UART2_BASE_ADDR; break; + case MACH_TYPE_BUG: + uart_base = MX3X_UART5_BASE_ADDR; + break; case MACH_TYPE_MX51_BABBAGE: case MACH_TYPE_EUKREA_CPUIMX51SD: case MACH_TYPE_MX51_3DS: -- cgit v0.10.2 From d4abe93386890061f109f2f2a46761ac5129bed6 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 23 Feb 2011 14:51:58 +0100 Subject: arm: mach-mx3: use IMX_GPIO_NR instead of hard-coded values The latter are error-prone because the bank number is one less than one would read in the documentation. Signed-off-by: Wolfram Sang Acked-by: Eric Benard Cc: Sascha Hauer Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c index 14a5ffc..8076147 100644 --- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c @@ -165,8 +165,8 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { MX35_PAD_SD1_DATA3__ESDHC1_DAT3, }; -#define GPIO_LED1 (2 * 32 + 29) -#define GPIO_SWITCH1 (2 * 32 + 25) +#define GPIO_LED1 IMX_GPIO_NR(3, 29) +#define GPIO_SWITCH1 IMX_GPIO_NR(3, 25) #define GPIO_LCDPWR (4) static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd, diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c index 6db0520..a42f1a9 100644 --- a/arch/arm/mach-mx3/mach-cpuimx35.c +++ b/arch/arm/mach-mx3/mach-cpuimx35.c @@ -60,7 +60,7 @@ static struct tsc2007_platform_data tsc2007_info = { .x_plate_ohms = 180, }; -#define TSC2007_IRQGPIO (2 * 32 + 2) +#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 2) static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = { { I2C_BOARD_INFO("pcf8563", 0x51), diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index 6c662c7..262af17 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -219,9 +219,9 @@ static iomux_v3_cfg_t pcm043_pads[] = { MX35_PAD_SD1_DATA3__ESDHC1_DAT3, }; -#define AC97_GPIO_TXFS (1 * 32 + 31) -#define AC97_GPIO_TXD (1 * 32 + 28) -#define AC97_GPIO_RESET (1 * 32 + 0) +#define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31) +#define AC97_GPIO_TXD IMX_GPIO_NR(2, 28) +#define AC97_GPIO_RESET IMX_GPIO_NR(2, 0) static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) { -- cgit v0.10.2 From 2c4066cca46e2e82b63127a3dba5e5f68a612749 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20B=C3=A9nard?= Date: Fri, 25 Feb 2011 13:48:15 +0100 Subject: eukrea-tlv320: add MBIMXSD51 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig index 642270a..9eeb8f0 100644 --- a/sound/soc/imx/Kconfig +++ b/sound/soc/imx/Kconfig @@ -44,7 +44,8 @@ config SND_SOC_EUKREA_TLV320 tristate "Eukrea TLV320" depends on MACH_EUKREA_MBIMX27_BASEBOARD \ || MACH_EUKREA_MBIMXSD25_BASEBOARD \ - || MACH_EUKREA_MBIMXSD35_BASEBOARD + || MACH_EUKREA_MBIMXSD35_BASEBOARD \ + || MACH_EUKREA_MBIMXSD51_BASEBOARD select SND_SOC_TLV320AIC23 select SND_MXC_SOC_SSI select SND_MXC_SOC_FIQ diff --git a/sound/soc/imx/eukrea-tlv320.c b/sound/soc/imx/eukrea-tlv320.c index e20c9e1..a08e822 100644 --- a/sound/soc/imx/eukrea-tlv320.c +++ b/sound/soc/imx/eukrea-tlv320.c @@ -98,7 +98,8 @@ static int __init eukrea_tlv320_init(void) int ret; if (!machine_is_eukrea_cpuimx27() && !machine_is_eukrea_cpuimx25sd() - && !machine_is_eukrea_cpuimx35sd()) + && !machine_is_eukrea_cpuimx35sd() + && !machine_is_eukrea_cpuimx51sd()) /* return happy. We might run on a totally different machine */ return 0; -- cgit v0.10.2 From b137214692effb1bc2221de8ccb11c09fb9df6f2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20B=C3=A9nard?= Date: Fri, 25 Feb 2011 14:38:27 +0100 Subject: cpuimx51sd: add cpufreq support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c index f38b341..6f5bcc1 100644 --- a/arch/arm/mach-mx5/board-cpuimx51sd.c +++ b/arch/arm/mach-mx5/board-cpuimx51sd.c @@ -42,6 +42,7 @@ #include "devices-imx51.h" #include "devices.h" +#include "cpu_op-mx51.h" #define USBH1_RST IMX_GPIO_NR(2, 28) #define ETH_RST IMX_GPIO_NR(2, 31) @@ -274,6 +275,10 @@ static void __init eukrea_cpuimx51sd_init(void) mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads, ARRAY_SIZE(eukrea_cpuimx51sd_pads)); +#if defined(CONFIG_CPU_FREQ_IMX) + get_cpu_op = mx51_get_cpu_op; +#endif + imx51_add_imx_uart(0, &uart_pdata); imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info); -- cgit v0.10.2 From 33d3487f557ea6787b1a8166b1ed123bb2136619 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20B=C3=A9nard?= Date: Fri, 25 Feb 2011 15:04:14 +0100 Subject: cpuimx51sd: fix tsc2007 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - wrong MUX was set before for IRQ - get_pendown_state is no more needed Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c index 6f5bcc1..820146e 100644 --- a/arch/arm/mach-mx5/board-cpuimx51sd.c +++ b/arch/arm/mach-mx5/board-cpuimx51sd.c @@ -110,7 +110,7 @@ static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = { /* Touchscreen */ /* IRQ */ - _MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | + _MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), }; @@ -119,15 +119,9 @@ static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -static int ts_get_pendown_state(void) -{ - return gpio_get_value(TSC2007_IRQGPIO) ? 0 : 1; -} - static struct tsc2007_platform_data tsc2007_info = { .model = 2007, .x_plate_ohms = 180, - .get_pendown_state = ts_get_pendown_state, }; static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = { -- cgit v0.10.2 From 8c3f2d7a2df5b3ad020571cacb1824f8df4768fd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20B=C3=A9nard?= Date: Fri, 25 Feb 2011 14:38:29 +0100 Subject: cpuimx51sd: mcp2515 supports up to 10MHz SPI clock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c index 820146e..29b1808 100644 --- a/arch/arm/mach-mx5/board-cpuimx51sd.c +++ b/arch/arm/mach-mx5/board-cpuimx51sd.c @@ -242,7 +242,7 @@ static struct mcp251x_platform_data mcp251x_info = { static struct spi_board_info cpuimx51sd_spi_device[] = { { .modalias = "mcp2515", - .max_speed_hz = 6500000, + .max_speed_hz = 10000000, .bus_num = 0, .mode = SPI_MODE_0, .chip_select = 0, -- cgit v0.10.2 From 84082d665dc62e632e21213fda8b22c0b8c25b81 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lothar=20Wa=C3=9Fmann?= Date: Wed, 15 Dec 2010 22:11:31 +0100 Subject: ARM: mxs: free dma_mask in error path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes a small memory leak that was only hit in very unlikely error paths. Signed-off-by: Lothar Waßmann Signed-off-by: Uwe Kleine-König diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c index c20d547..cfdb6b2 100644 --- a/arch/arm/mach-mxs/devices.c +++ b/arch/arm/mach-mxs/devices.c @@ -66,6 +66,8 @@ struct platform_device *__init mxs_add_platform_device_dmamask( ret = platform_device_add(pdev); if (ret) { err: + if (dmamask) + kfree(pdev->dev.dma_mask); platform_device_put(pdev); return ERR_PTR(ret); } -- cgit v0.10.2 From c762b293d4a12fb726cec62cfe3e64f66cf3103f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 18 Feb 2011 21:59:25 +0100 Subject: ARM: mxc: free dma_mask in error path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes a small memory leak that was only hit in very unlikely error paths Signed-off-by: Uwe Kleine-König diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c index e9bcefe..eee1b60 100644 --- a/arch/arm/plat-mxc/devices.c +++ b/arch/arm/plat-mxc/devices.c @@ -81,6 +81,8 @@ struct platform_device *__init imx_add_platform_device_dmamask( ret = platform_device_add(pdev); if (ret) { err: + if (dmamask) + kfree(pdev->dev.dma_mask); platform_device_put(pdev); return ERR_PTR(ret); } -- cgit v0.10.2 From f4b5d2b0d1df863eab004e42b4492fce6ccc52b2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lothar=20Wa=C3=9Fmann?= Date: Wed, 15 Dec 2010 22:20:13 +0100 Subject: ARM: mxs: add a dma mask to fec devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is not strictly necessary but the right thing to do. Signed-off-by: Lothar Waßmann Signed-off-by: Uwe Kleine-König diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c index c42dff7..9859cf2 100644 --- a/arch/arm/mach-mxs/devices/platform-fec.c +++ b/arch/arm/mach-mxs/devices/platform-fec.c @@ -45,6 +45,7 @@ struct platform_device *__init mxs_add_fec( }, }; - return mxs_add_platform_device("imx28-fec", data->id, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); + return mxs_add_platform_device_dmamask("imx28-fec", data->id, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata), + DMA_BIT_MASK(32)); } -- cgit v0.10.2 From 78159566b7ec120a1020cfc9469ac526bdd05387 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 19 Jan 2011 11:37:10 +0100 Subject: ARM: mxc: add a dma mask to fec devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is not strictly necessary but the right thing to do. Signed-off-by: Uwe Kleine-König diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c index 4f52996..6561c9d 100644 --- a/arch/arm/plat-mxc/devices/platform-fec.c +++ b/arch/arm/plat-mxc/devices/platform-fec.c @@ -62,7 +62,7 @@ struct platform_device *__init imx_add_fec( }, }; - return imx_add_platform_device("fec", 0 /* -1? */, + return imx_add_platform_device_dmamask("fec", 0, res, ARRAY_SIZE(res), - pdata, sizeof(*pdata)); + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); } -- cgit v0.10.2 From 2301dfa7be2cb3e6bdd07cc1cb349b5853c4d5ee Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 25 Jan 2011 11:58:15 +0100 Subject: ARM: mxs: Add pwm clocks and device registration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Sascha Hauer Signed-off-by: Uwe Kleine-König diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 55bf075..836cc81 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -8,10 +8,12 @@ config MXS_OCOTP config SOC_IMX23 bool select CPU_ARM926T + select HAVE_PWM config SOC_IMX28 bool select CPU_ARM926T + select HAVE_PWM comment "MXS platforms:" diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c index 7c5dace..38ee1b1 100644 --- a/arch/arm/mach-mxs/clock-mx23.c +++ b/arch/arm/mach-mxs/clock-mx23.c @@ -447,7 +447,11 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "hclk", hbus_clk) _REGISTER_CLOCK(NULL, "usb", usb_clk) _REGISTER_CLOCK(NULL, "audio", audio_clk) - _REGISTER_CLOCK(NULL, "pwm", pwm_clk) + _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk) + _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk) + _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk) + _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk) + _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk) }; static int clk_misc_init(void) diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index febd787..40726c7 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -622,7 +622,14 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("flexcan.1", NULL, can1_clk) _REGISTER_CLOCK(NULL, "usb0", usb0_clk) _REGISTER_CLOCK(NULL, "usb1", usb1_clk) - _REGISTER_CLOCK(NULL, "pwm", pwm_clk) + _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk) + _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk) + _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk) + _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk) + _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk) + _REGISTER_CLOCK("mxs-pwm.5", NULL, pwm_clk) + _REGISTER_CLOCK("mxs-pwm.6", NULL, pwm_clk) + _REGISTER_CLOCK("mxs-pwm.7", NULL, pwm_clk) _REGISTER_CLOCK(NULL, "lradc", lradc_clk) _REGISTER_CLOCK(NULL, "spdif", spdif_clk) }; diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h index c4d4773..7fb27b1 100644 --- a/arch/arm/mach-mxs/devices-mx23.h +++ b/arch/arm/mach-mxs/devices-mx23.h @@ -19,3 +19,5 @@ extern const struct mxs_auart_data mx23_auart_data[] __initconst; #define mx23_add_auart(id) mxs_add_auart(&mx23_auart_data[id]) #define mx23_add_auart0() mx23_add_auart(0) #define mx23_add_auart1() mx23_add_auart(1) + +#define mx23_add_mxs_pwm(id) mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id) diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h index 3b18304..69d19ea 100644 --- a/arch/arm/mach-mxs/devices-mx28.h +++ b/arch/arm/mach-mxs/devices-mx28.h @@ -32,3 +32,5 @@ extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst; mxs_add_flexcan(&mx28_flexcan_data[id], pdata) #define mx28_add_flexcan0(pdata) mx28_add_flexcan(0, pdata) #define mx28_add_flexcan1(pdata) mx28_add_flexcan(1, pdata) + +#define mx28_add_mxs_pwm(id) mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id) diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig index 6c65b67..3aeec24 100644 --- a/arch/arm/mach-mxs/devices/Kconfig +++ b/arch/arm/mach-mxs/devices/Kconfig @@ -11,3 +11,6 @@ config MXS_HAVE_PLATFORM_FEC config MXS_HAVE_PLATFORM_FLEXCAN select HAVE_CAN_FLEXCAN if CAN bool + +config MXS_HAVE_PLATFORM_MXS_PWM + bool diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile index a8dc8d5..978310f 100644 --- a/arch/arm/mach-mxs/devices/Makefile +++ b/arch/arm/mach-mxs/devices/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o +obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o diff --git a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c new file mode 100644 index 0000000..680f5a9 --- /dev/null +++ b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2010 Pengutronix + * Sascha Hauer + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +struct platform_device *__init mxs_add_mxs_pwm(resource_size_t iobase, int id) +{ + struct resource res = { + .flags = IORESOURCE_MEM, + }; + + res.start = iobase + 0x10 + 0x20 * id; + res.end = res.start + 0x1f; + + return mxs_add_platform_device("mxs-pwm", id, &res, 1, NULL, 0); +} diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h index e7aefb4..d460d30 100644 --- a/arch/arm/mach-mxs/include/mach/devices-common.h +++ b/arch/arm/mach-mxs/include/mach/devices-common.h @@ -63,3 +63,7 @@ struct mxs_flexcan_data { struct platform_device *__init mxs_add_flexcan( const struct mxs_flexcan_data *data, const struct flexcan_platform_data *pdata); + +/* pwm */ +struct platform_device *__init mxs_add_mxs_pwm( + resource_size_t iobase, int id); -- cgit v0.10.2 From ccb24d50b7ee242a2bf2dd208193f7335a3a0d7d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 16 Feb 2011 10:46:12 +0100 Subject: ARM: mxs: Add missing EXPORT_SYMBOL for mxs_reset_block MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is used for example in the i2c driver which can be compiled modular. Signed-off-by: Sascha Hauer Signed-off-by: Uwe Kleine-König diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c index 9343d7e..20ec3bd 100644 --- a/arch/arm/mach-mxs/system.c +++ b/arch/arm/mach-mxs/system.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -135,3 +136,4 @@ error: pr_err("%s(%p): module reset timeout\n", __func__, reset_addr); return -ETIMEDOUT; } +EXPORT_SYMBOL(mxs_reset_block); -- cgit v0.10.2 From 1cb59f9f79f4ed89845f6f8bebf0273442e1ccd5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lothar=20Wa=C3=9Fmann?= Date: Fri, 10 Dec 2010 16:22:47 +0100 Subject: ARM: mxs: Initial support for Ka-Ro TX28 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Based on code created by Lothar Waßmann, Sascha Hauer, Wolfram Sang and me. Signed-off-by: Lothar Waßmann Signed-off-by: Sascha Hauer Signed-off-by: Wolfram Sang Signed-off-by: Uwe Kleine-König diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 836cc81..895d066 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -39,4 +39,16 @@ config MACH_MX28EVK Include support for MX28EVK platform. This includes specific configurations for the board and its peripherals. +config MODULE_TX28 + bool + select SOC_IMX28 + select MXS_HAVE_AMBA_DUART + select MXS_HAVE_PLATFORM_AUART + select MXS_HAVE_PLATFORM_FEC + select MXS_HAVE_PLATFORM_MXS_PWM + +config MACH_TX28 + bool "Ka-Ro TX28 module" + select MODULE_TX28 + endif diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile index 6b26f02..2f1f614 100644 --- a/arch/arm/mach-mxs/Makefile +++ b/arch/arm/mach-mxs/Makefile @@ -9,5 +9,7 @@ obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o +obj-$(CONFIG_MODULE_TX28) += module-tx28.o +obj-$(CONFIG_MACH_TX28) += mach-tx28.o obj-y += devices/ diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h index f186c08..35a89dd 100644 --- a/arch/arm/mach-mxs/include/mach/mxs.h +++ b/arch/arm/mach-mxs/include/mach/mxs.h @@ -28,8 +28,13 @@ /* * MXS CPU types */ -#define cpu_is_mx23() (machine_is_mx23evk()) -#define cpu_is_mx28() (machine_is_mx28evk()) +#define cpu_is_mx23() ( \ + machine_is_mx23evk() || \ + 0) +#define cpu_is_mx28() ( \ + machine_is_mx28evk() || \ + machine_is_tx28() || \ + 0) /* * IO addresses common to MXS-based diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h index a005e76f..f12a173 100644 --- a/arch/arm/mach-mxs/include/mach/uncompress.h +++ b/arch/arm/mach-mxs/include/mach/uncompress.h @@ -63,6 +63,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id) mxs_duart_base = MX23_DUART_BASE_ADDR; break; case MACH_TYPE_MX28EVK: + case MACH_TYPE_TX28: mxs_duart_base = MX28_DUART_BASE_ADDR; break; default: diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c new file mode 100644 index 0000000..b609b84 --- /dev/null +++ b/arch/arm/mach-mxs/mach-tx28.c @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2010 + * + * based on: mach-mx28_evk.c + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation + */ +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "devices-mx28.h" +#include "module-tx28.h" + +#define TX28_STK5_GPIO_LED MXS_GPIO_NR(4, 10) + +static const iomux_cfg_t tx28_stk5v3_pads[] __initconst = { + /* LED */ + MX28_PAD_ENET0_RXD3__GPIO_4_10 | + MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL, + + /* framebuffer */ +#define LCD_MODE (MXS_PAD_3V3 | MXS_PAD_4MA) + MX28_PAD_LCD_D00__LCD_D0 | LCD_MODE, + MX28_PAD_LCD_D01__LCD_D1 | LCD_MODE, + MX28_PAD_LCD_D02__LCD_D2 | LCD_MODE, + MX28_PAD_LCD_D03__LCD_D3 | LCD_MODE, + MX28_PAD_LCD_D04__LCD_D4 | LCD_MODE, + MX28_PAD_LCD_D05__LCD_D5 | LCD_MODE, + MX28_PAD_LCD_D06__LCD_D6 | LCD_MODE, + MX28_PAD_LCD_D07__LCD_D7 | LCD_MODE, + MX28_PAD_LCD_D08__LCD_D8 | LCD_MODE, + MX28_PAD_LCD_D09__LCD_D9 | LCD_MODE, + MX28_PAD_LCD_D10__LCD_D10 | LCD_MODE, + MX28_PAD_LCD_D11__LCD_D11 | LCD_MODE, + MX28_PAD_LCD_D12__LCD_D12 | LCD_MODE, + MX28_PAD_LCD_D13__LCD_D13 | LCD_MODE, + MX28_PAD_LCD_D14__LCD_D14 | LCD_MODE, + MX28_PAD_LCD_D15__LCD_D15 | LCD_MODE, + MX28_PAD_LCD_D16__LCD_D16 | LCD_MODE, + MX28_PAD_LCD_D17__LCD_D17 | LCD_MODE, + MX28_PAD_LCD_D18__LCD_D18 | LCD_MODE, + MX28_PAD_LCD_D19__LCD_D19 | LCD_MODE, + MX28_PAD_LCD_D20__LCD_D20 | LCD_MODE, + MX28_PAD_LCD_D21__LCD_D21 | LCD_MODE, + MX28_PAD_LCD_D22__LCD_D22 | LCD_MODE, + MX28_PAD_LCD_D23__LCD_D23 | LCD_MODE, + MX28_PAD_LCD_RD_E__LCD_VSYNC | LCD_MODE, + MX28_PAD_LCD_WR_RWN__LCD_HSYNC | LCD_MODE, + MX28_PAD_LCD_RS__LCD_DOTCLK | LCD_MODE, + MX28_PAD_LCD_CS__LCD_CS | LCD_MODE, + MX28_PAD_LCD_VSYNC__LCD_VSYNC | LCD_MODE, + MX28_PAD_LCD_HSYNC__LCD_HSYNC | LCD_MODE, + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | LCD_MODE, + MX28_PAD_LCD_ENABLE__GPIO_1_31 | LCD_MODE, + MX28_PAD_LCD_RESET__GPIO_3_30 | LCD_MODE, + MX28_PAD_PWM0__PWM_0 | LCD_MODE, + + /* UART1 */ + MX28_PAD_AUART0_CTS__DUART_RX, + MX28_PAD_AUART0_RTS__DUART_TX, + MX28_PAD_AUART0_TX__DUART_RTS, + MX28_PAD_AUART0_RX__DUART_CTS, + + /* UART2 */ + MX28_PAD_AUART1_RX__AUART1_RX, + MX28_PAD_AUART1_TX__AUART1_TX, + MX28_PAD_AUART1_RTS__AUART1_RTS, + MX28_PAD_AUART1_CTS__AUART1_CTS, + + /* CAN */ + MX28_PAD_GPMI_RDY2__CAN0_TX, + MX28_PAD_GPMI_RDY3__CAN0_RX, + + /* I2C */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + + /* TSC2007 */ + MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP, + + /* MMC0 */ + MX28_PAD_SSP0_DATA0__SSP0_D0 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA1__SSP0_D1 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA2__SSP0_D2 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA3__SSP0_D3 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA4__SSP0_D4 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA5__SSP0_D5 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA6__SSP0_D6 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA7__SSP0_D7 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_CMD__SSP0_CMD | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_SSP0_SCK__SSP0_SCK | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), +}; + +static struct gpio_led tx28_stk5v3_leds[] = { + { + .name = "GPIO-LED", + .default_trigger = "heartbeat", + .gpio = TX28_STK5_GPIO_LED, + }, +}; + +static const struct gpio_led_platform_data tx28_stk5v3_led_data __initconst = { + .leds = tx28_stk5v3_leds, + .num_leds = ARRAY_SIZE(tx28_stk5v3_leds), +}; + +static struct spi_board_info tx28_spi_board_info[] = { + { + .modalias = "spidev", + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 1, + .controller_data = (void *)SPI_GPIO_NO_CHIPSELECT, + .mode = SPI_MODE_0, + }, +}; + +static void __init tx28_stk5v3_init(void) +{ + mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads, + ARRAY_SIZE(tx28_stk5v3_pads)); + + mx28_add_duart(); /* UART1 */ + mx28_add_auart(1); /* UART2 */ + + tx28_add_fec0(); + /* spi via ssp will be added when available */ + spi_register_board_info(tx28_spi_board_info, + ARRAY_SIZE(tx28_spi_board_info)); + mxs_add_platform_device("leds-gpio", 0, NULL, 0, + &tx28_stk5v3_led_data, sizeof(tx28_stk5v3_led_data)); +} + +static void __init tx28_timer_init(void) +{ + mx28_clocks_init(); +} + +static struct sys_timer tx28_timer = { + .init = tx28_timer_init, +}; + +MACHINE_START(TX28, "Ka-Ro electronics TX28 module") + .map_io = mx28_map_io, + .init_irq = mx28_init_irq, + .init_machine = tx28_stk5v3_init, + .timer = &tx28_timer, +MACHINE_END diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c new file mode 100644 index 0000000..fa0b154 --- /dev/null +++ b/arch/arm/mach-mxs/module-tx28.c @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2010 + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#include +#include +#include + +#include +#include "../devices-mx28.h" + +#include "module-tx28.h" + +#define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29) +#define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13) + +static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = { + /* PHY POWER */ + MX28_PAD_PWM4__GPIO_3_29 | + MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3, + /* PHY RESET */ + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | + MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3, + /* Mode strap pins 0-2 */ + MX28_PAD_ENET0_RXD0__GPIO_4_3 | + MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3, + MX28_PAD_ENET0_RXD1__GPIO_4_4 | + MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3, + MX28_PAD_ENET0_RX_EN__GPIO_4_2 | + MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3, + /* nINT */ + MX28_PAD_ENET0_TX_CLK__GPIO_4_5 | + MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3, + + MX28_PAD_ENET0_MDC__GPIO_4_0, + MX28_PAD_ENET0_MDIO__GPIO_4_1, + MX28_PAD_ENET0_TX_EN__GPIO_4_6, + MX28_PAD_ENET0_TXD0__GPIO_4_7, + MX28_PAD_ENET0_TXD1__GPIO_4_8, + MX28_PAD_ENET_CLK__GPIO_4_16, +}; + +#define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3) +static const iomux_cfg_t tx28_fec_pads[] __initconst = { + MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE, + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | FEC_MODE, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | FEC_MODE, + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | FEC_MODE, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | FEC_MODE, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | FEC_MODE, + MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE, +}; + +static const struct fec_platform_data tx28_fec_data __initconst = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + +int __init tx28_add_fec0(void) +{ + int i, ret; + + pr_debug("%s: Switching FEC PHY power off\n", __func__); + ret = mxs_iomux_setup_multiple_pads(tx28_fec_gpio_pads, + ARRAY_SIZE(tx28_fec_gpio_pads)); + for (i = 0; i < ARRAY_SIZE(tx28_fec_gpio_pads); i++) { + unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]), + PAD_PIN(tx28_fec_gpio_pads[i])); + + ret = gpio_request(gpio, "FEC"); + if (ret) { + pr_err("Failed to request GPIO_%d_%d: %d\n", + PAD_BANK(tx28_fec_gpio_pads[i]), + PAD_PIN(tx28_fec_gpio_pads[i]), ret); + goto free_gpios; + } + ret = gpio_direction_output(gpio, 0); + if (ret) { + pr_err("Failed to set direction of GPIO_%d_%d to output: %d\n", + gpio / 32 + 1, gpio % 32, ret); + goto free_gpios; + } + } + + /* Power up fec phy */ + pr_debug("%s: Switching FEC PHY power on\n", __func__); + ret = gpio_direction_output(TX28_FEC_PHY_POWER, 1); + if (ret) { + pr_err("Failed to power on PHY: %d\n", ret); + goto free_gpios; + } + mdelay(26); /* 25ms according to data sheet */ + + /* nINT */ + gpio_direction_input(MXS_GPIO_NR(4, 5)); + /* Mode strap pins */ + gpio_direction_output(MXS_GPIO_NR(4, 2), 1); + gpio_direction_output(MXS_GPIO_NR(4, 3), 1); + gpio_direction_output(MXS_GPIO_NR(4, 4), 1); + + udelay(100); /* minimum assertion time for nRST */ + + pr_debug("%s: Deasserting FEC PHY RESET\n", __func__); + gpio_set_value(TX28_FEC_PHY_RESET, 1); + + ret = mxs_iomux_setup_multiple_pads(tx28_fec_pads, + ARRAY_SIZE(tx28_fec_pads)); + if (ret) { + pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n", + __func__, ret); + goto free_gpios; + } + pr_debug("%s: Registering FEC device\n", __func__); + mx28_add_fec(0, &tx28_fec_data); + return 0; + +free_gpios: + while (--i >= 0) { + unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]), + PAD_PIN(tx28_fec_gpio_pads[i])); + + gpio_free(gpio); + } + + return ret; +} diff --git a/arch/arm/mach-mxs/module-tx28.h b/arch/arm/mach-mxs/module-tx28.h new file mode 100644 index 0000000..df9e1b6 --- /dev/null +++ b/arch/arm/mach-mxs/module-tx28.h @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +int __init tx28_add_fec0(void); -- cgit v0.10.2 From 20fcd4aa019af7576f8ee704c6fd2908811981d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20B=C3=A9nard?= Date: Fri, 25 Feb 2011 13:49:15 +0100 Subject: i.MX25: add sdma clock definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/clock-imx25.c b/arch/arm/mach-imx/clock-imx25.c index daa0165..a65838f 100644 --- a/arch/arm/mach-imx/clock-imx25.c +++ b/arch/arm/mach-imx/clock-imx25.c @@ -228,6 +228,7 @@ DEFINE_CLOCK(esdhc1_per_clk, 0, CCM_CGCR0, 3, get_rate_esdhc1, NULL, DEFINE_CLOCK(esdhc2_ahb_clk, 0, CCM_CGCR0, 22, get_rate_esdhc2, NULL, NULL); DEFINE_CLOCK(esdhc2_per_clk, 0, CCM_CGCR0, 4, get_rate_esdhc2, NULL, &esdhc2_ahb_clk); +DEFINE_CLOCK(sdma_ahb_clk, 0, CCM_CGCR0, 26, NULL, NULL, NULL); DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); @@ -253,6 +254,7 @@ DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk); DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk); DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk); +DEFINE_CLOCK(sdma_clk, 0, CCM_CGCR2, 6, get_rate_ipg, NULL, &sdma_ahb_clk); DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGCR1, 13, get_rate_esdhc1, NULL, &esdhc1_per_clk); DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGCR1, 14, get_rate_esdhc2, NULL, @@ -304,6 +306,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "audmux", audmux_clk) _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) + _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk) }; int __init mx25_clocks_init(void) -- cgit v0.10.2 From d058b649336e16d110744888fd4287733a4ea854 Mon Sep 17 00:00:00 2001 From: Ryan Lortie Date: Sat, 26 Feb 2011 19:41:52 -0500 Subject: ARM: imx35: fix ATA_DATA3 pad control address According to the "i.MX35 (MCIMX35) Multimedia Applications Processor Reference Manual" the correct address for the pad control register IOMUXC_SW_PAD_CTL_PAD_ATA_DATA3 is 0x06ec, not 0x6e8. Signed-off-by: Ryan Lortie Acked-by: Marc Reilly Signed-off-by: Sascha Hauer diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h index 2a24bae..3117c18 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx35.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h @@ -989,13 +989,13 @@ #define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL) #define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__ATA_DATA_3 IOMUX_PAD(0x6e8, 0x288, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__ESDHC3_CLK IOMUX_PAD(0x6e8, 0x288, 1, 0x814, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x6e8, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__CSPI2_SCLK IOMUX_PAD(0x6e8, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__GPIO2_16 IOMUX_PAD(0x6e8, 0x288, 5, 0x884, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 IOMUX_PAD(0x6e8, 0x288, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 IOMUX_PAD(0x6e8, 0x288, 7, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__ATA_DATA_3 IOMUX_PAD(0x6ec, 0x288, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__ESDHC3_CLK IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__CSPI2_SCLK IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__GPIO2_16 IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 IOMUX_PAD(0x6ec, 0x288, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 IOMUX_PAD(0x6ec, 0x288, 7, 0x0, 0, NO_PAD_CTRL) #define MX35_PAD_ATA_DATA4__ATA_DATA_4 IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL) #define MX35_PAD_ATA_DATA4__ESDHC3_CMD IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL) -- cgit v0.10.2 From 4dbbaa69e12a2dfd57a156ff3e233dabc9a9e885 Mon Sep 17 00:00:00 2001 From: Ryan Lortie Date: Sat, 26 Feb 2011 19:41:53 -0500 Subject: ARM: imx35: fix trivial copy/paste error MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change imx31_add_imx_keypad() to imx35_add_imx_keypad() in mach-mx3/devices-imx35.h. Signed-off-by: Ryan Lortie Acked-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h index 677b18a..d545d86 100644 --- a/arch/arm/mach-mx3/devices-imx35.h +++ b/arch/arm/mach-mx3/devices-imx35.h @@ -35,7 +35,7 @@ extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst; #define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata) extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst; -#define imx31_add_imx_keypad(pdata) \ +#define imx35_add_imx_keypad(pdata) \ imx_add_imx_keypad(&imx35_imx_keypad_data, pdata) extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst; -- cgit v0.10.2 From 40b2747b5b4f49a5f268c71321677fa98f63f046 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Wed, 23 Feb 2011 16:58:37 +0000 Subject: MX1: Rename SPI interrupt name and base address. Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Sascha Hauer diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 75d9621..7c871b8 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -54,13 +54,13 @@ #define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR) #define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR) #define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR) -#define MX1_SPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR) +#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR) #define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR) #define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR) #define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR) #define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR) #define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR) -#define MX1_SPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR) +#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR) #define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR) #define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) #define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) @@ -112,7 +112,8 @@ #define MX1_PWM_INT 34 #define MX1_SDHC_INT 35 #define MX1_INT_I2C 39 -#define MX1_CSPI_INT 41 +#define MX1_INT_CSPI2 40 +#define MX1_INT_CSPI1 41 #define MX1_SSI_TX_INT 42 #define MX1_SSI_TX_ERR_INT 43 #define MX1_SSI_RX_INT 44 -- cgit v0.10.2 From e893f7cb47f7e472d852922547f1283bd12f7d26 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Wed, 23 Feb 2011 16:58:38 +0000 Subject: MX1: Register clock for SPI2 Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/clock-imx1.c b/arch/arm/mach-imx/clock-imx1.c index 3938a56..dcc4172 100644 --- a/arch/arm/mach-imx/clock-imx1.c +++ b/arch/arm/mach-imx/clock-imx1.c @@ -592,6 +592,7 @@ static struct clk_lookup lookups[] __initdata = { _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk) _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) _REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk) + _REGISTER_CLOCK("imx1-cspi.1", NULL, spi_clk) _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) _REGISTER_CLOCK(NULL, "mshc", mshc_clk) -- cgit v0.10.2 From 13f40686b1dc8cc3c2110d3f902e0b3ec9ddee10 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Wed, 23 Feb 2011 16:58:36 +0000 Subject: MX1: Add data structure for SPI Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Sascha Hauer diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c index 013c85f..f4a60ab 100644 --- a/arch/arm/plat-mxc/devices/platform-spi_imx.c +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -21,6 +21,15 @@ #define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \ [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size) +#ifdef CONFIG_SOC_IMX1 +const struct imx_spi_imx_data imx1_cspi_data[] __initconst = { +#define imx1_cspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX1, CSPI, "imx1-cspi", _id, _hwid, SZ_4K) + imx1_cspi_data_entry(0, 1), + imx1_cspi_data_entry(1, 2), +}; +#endif + #ifdef CONFIG_SOC_IMX21 const struct imx_spi_imx_data imx21_cspi_data[] __initconst = { #define imx21_cspi_data_entry(_id, _hwid) \ -- cgit v0.10.2 From 19373c04b9c260b83e268e40e3210c01281efb6d Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Wed, 23 Feb 2011 16:58:39 +0000 Subject: MX1: Add registration functions for SPI. Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h index 8197948..fd26715 100644 --- a/arch/arm/mach-imx/devices-imx1.h +++ b/arch/arm/mach-imx/devices-imx1.h @@ -18,3 +18,10 @@ extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst; imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata) #define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata) #define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata) + +extern const struct imx_spi_imx_data imx1_cspi_data[] __initconst; +#define imx1_add_cspi(id, pdata) \ + imx_add_spi_imx(&imx1_cspi_data[id], pdata) + +#define imx1_add_spi_imx0(pdata) imx1_add_cspi(0, pdata) +#define imx1_add_spi_imx1(pdata) imx1_add_cspi(1, pdata) -- cgit v0.10.2 From 30feed37f21e00655475d8bf17bcea02221e53d2 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 28 Feb 2011 17:40:04 +0100 Subject: arm: mxs: add i2c-devices for mx28 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Wolfram Sang Acked-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h index 69d19ea..a9eecdc 100644 --- a/arch/arm/mach-mxs/devices-mx28.h +++ b/arch/arm/mach-mxs/devices-mx28.h @@ -33,4 +33,7 @@ extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst; #define mx28_add_flexcan0(pdata) mx28_add_flexcan(0, pdata) #define mx28_add_flexcan1(pdata) mx28_add_flexcan(1, pdata) +extern const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst; +#define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id]) + #define mx28_add_mxs_pwm(id) mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id) diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig index 3aeec24..a878915 100644 --- a/arch/arm/mach-mxs/devices/Kconfig +++ b/arch/arm/mach-mxs/devices/Kconfig @@ -12,5 +12,8 @@ config MXS_HAVE_PLATFORM_FLEXCAN select HAVE_CAN_FLEXCAN if CAN bool +config MXS_HAVE_PLATFORM_MXS_I2C + bool + config MXS_HAVE_PLATFORM_MXS_PWM bool diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile index 978310f..345b839 100644 --- a/arch/arm/mach-mxs/devices/Makefile +++ b/arch/arm/mach-mxs/devices/Makefile @@ -2,4 +2,5 @@ obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o +obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o diff --git a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c new file mode 100644 index 0000000..eab3a06 --- /dev/null +++ b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2011 Pengutronix + * Wolfram Sang + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include +#include + +#define mxs_i2c_data_entry_single(soc, _id) \ + { \ + .id = _id, \ + .iobase = soc ## _I2C ## _id ## _BASE_ADDR, \ + .errirq = soc ## _INT_I2C ## _id ## _ERROR, \ + .dmairq = soc ## _INT_I2C ## _id ## _DMA, \ + } + +#define mxs_i2c_data_entry(soc, _id) \ + [_id] = mxs_i2c_data_entry_single(soc, _id) + +#ifdef CONFIG_SOC_IMX28 +const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst = { + mxs_i2c_data_entry(MX28, 0), + mxs_i2c_data_entry(MX28, 1), +}; +#endif + +struct platform_device *__init mxs_add_mxs_i2c(const struct mxs_i2c_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->errirq, + .end = data->errirq, + .flags = IORESOURCE_IRQ, + }, { + .start = data->dmairq, + .end = data->dmairq, + .flags = IORESOURCE_IRQ, + }, + }; + + return mxs_add_platform_device("mxs-i2c", data->id, res, + ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h index d460d30..71f2448 100644 --- a/arch/arm/mach-mxs/include/mach/devices-common.h +++ b/arch/arm/mach-mxs/include/mach/devices-common.h @@ -64,6 +64,15 @@ struct platform_device *__init mxs_add_flexcan( const struct mxs_flexcan_data *data, const struct flexcan_platform_data *pdata); +/* i2c */ +struct mxs_i2c_data { + int id; + resource_size_t iobase; + resource_size_t errirq; + resource_size_t dmairq; +}; +struct platform_device * __init mxs_add_mxs_i2c(const struct mxs_i2c_data *data); + /* pwm */ struct platform_device *__init mxs_add_mxs_pwm( resource_size_t iobase, int id); -- cgit v0.10.2 From a77dd2aa92388d61f7344a32b06fd1de70e71928 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 28 Feb 2011 17:40:05 +0100 Subject: arm: mxs: tx28: add i2c bus and connected RTC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Wolfram Sang Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 895d066..4f0b673 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -45,6 +45,7 @@ config MODULE_TX28 select MXS_HAVE_AMBA_DUART select MXS_HAVE_PLATFORM_AUART select MXS_HAVE_PLATFORM_FEC + select MXS_HAVE_PLATFORM_MXS_I2C select MXS_HAVE_PLATFORM_MXS_PWM config MACH_TX28 diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c index b609b84..b65e371 100644 --- a/arch/arm/mach-mxs/mach-tx28.c +++ b/arch/arm/mach-mxs/mach-tx28.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -140,6 +141,12 @@ static struct spi_board_info tx28_spi_board_info[] = { }, }; +static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = { + { + I2C_BOARD_INFO("ds1339", 0x68), + }, +}; + static void __init tx28_stk5v3_init(void) { mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads, @@ -154,6 +161,9 @@ static void __init tx28_stk5v3_init(void) ARRAY_SIZE(tx28_spi_board_info)); mxs_add_platform_device("leds-gpio", 0, NULL, 0, &tx28_stk5v3_led_data, sizeof(tx28_stk5v3_led_data)); + mx28_add_mxs_i2c(0); + i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo, + ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo)); } static void __init tx28_timer_init(void) -- cgit v0.10.2 From 359219025e20a3ad61f081a82e0feec0583aca9b Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Mon, 28 Feb 2011 19:32:03 +0800 Subject: ARM: imx51/53: add sdhc3/4 clock Signed-off-by: Richard Zhao Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index 8164b1d..652ace4 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -42,6 +42,9 @@ static struct clk usboh3_clk; static struct clk emi_fast_clk; static struct clk ipu_clk; static struct clk mipi_hsc1_clk; +static struct clk esdhc1_clk; +static struct clk esdhc2_clk; +static struct clk esdhc3_mx53_clk; #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ @@ -1143,10 +1146,80 @@ CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1) CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1) CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1) +/* mx51 specific */ CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2) CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2) CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2) +static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk) + reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL; + else if (parent == &esdhc2_clk) + reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL; + else + return -EINVAL; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk) + reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + else if (parent == &esdhc2_clk) + reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + else + return -EINVAL; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +/* mx53 specific */ +static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk) + reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL; + else if (parent == &esdhc3_mx53_clk) + reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL; + else + return -EINVAL; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53) +CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53) +CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53) + +static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk) + reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + else if (parent == &esdhc3_mx53_clk) + reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + else + return -EINVAL; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + #define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \ static struct clk name = { \ .id = i, \ @@ -1251,9 +1324,62 @@ DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET, clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk); DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET, NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); +DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET, + NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); +DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET, + NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); + +/* mx51 specific */ DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk); +static struct clk esdhc3_clk = { + .id = 2, + .parent = &esdhc1_clk, + .set_parent = clk_esdhc3_set_parent, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .enable = _clk_max_enable, + .disable = _clk_max_disable, + .secondary = &esdhc3_ipg_clk, +}; +static struct clk esdhc4_clk = { + .id = 3, + .parent = &esdhc1_clk, + .set_parent = clk_esdhc4_set_parent, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_max_enable, + .disable = _clk_max_disable, + .secondary = &esdhc4_ipg_clk, +}; + +/* mx53 specific */ +static struct clk esdhc2_mx53_clk = { + .id = 2, + .parent = &esdhc1_clk, + .set_parent = clk_esdhc2_mx53_set_parent, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, + .enable = _clk_max_enable, + .disable = _clk_max_disable, + .secondary = &esdhc3_ipg_clk, +}; + +DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET, + clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk); + +static struct clk esdhc4_mx53_clk = { + .id = 3, + .parent = &esdhc1_clk, + .set_parent = clk_esdhc4_mx53_set_parent, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_max_enable, + .disable = _clk_max_disable, + .secondary = &esdhc4_ipg_clk, +}; + DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk); DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk); DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk); @@ -1312,6 +1438,8 @@ static struct clk_lookup mx51_lookups[] = { _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk) _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) + _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk) + _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_clk) _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk) _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk) @@ -1332,7 +1460,9 @@ static struct clk_lookup mx53_lookups[] = { _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) + _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_mx53_clk) + _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_mx53_clk) + _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_mx53_clk) _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk) _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk) _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk) @@ -1425,6 +1555,14 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, mx53_revision(); clk_disable(&iim_clk); + /* Set SDHC parents to be PLL2 */ + clk_set_parent(&esdhc1_clk, &pll2_sw_clk); + clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk); + + /* set SDHC root clock as 200MHZ*/ + clk_set_rate(&esdhc1_clk, 200000000); + clk_set_rate(&esdhc3_mx53_clk, 200000000); + /* System timer */ mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT); diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index b462c22..87c0c58 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -217,9 +217,12 @@ #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19) #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) @@ -271,6 +274,10 @@ #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22) +#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19) #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) -- cgit v0.10.2 From 772edeaec182fa98a2b4ed0753ca3dfd4f51d6a8 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Mon, 28 Feb 2011 19:32:02 +0800 Subject: ARM: imx53_loco: add esdhc device support Signed-off-by: Richard Zhao Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index f065a0d..a72c833 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -162,6 +162,7 @@ config MACH_MX53_LOCO select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX help Include support for MX53 LOCO platform. This includes specific configurations for the board and its peripherals. diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c index 160899e..0a18f8d 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c @@ -213,6 +213,8 @@ static void __init mx53_loco_board_init(void) imx53_add_imx2_wdt(0, NULL); imx53_add_imx_i2c(0, &mx53_loco_i2c_data); imx53_add_imx_i2c(1, &mx53_loco_i2c_data); + imx53_add_sdhci_esdhc_imx(0, NULL); + imx53_add_sdhci_esdhc_imx(2, NULL); } static void __init mx53_loco_timer_init(void) -- cgit v0.10.2 From 3fc6b60976d01feda083e2a05b3c40217ad32799 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 1 Mar 2011 21:30:58 +0100 Subject: ARM: mx3/cpuimx35: fix build failure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It seems vim's autocompletion played tricks on me without me noticing. This was intruduced in 97976e2 (ARM: mx3: use .init_early to initialize cpu type, reset address and iomuxer) Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c index a42f1a9..ec63d99 100644 --- a/arch/arm/mach-mx3/mach-cpuimx35.c +++ b/arch/arm/mach-mx3/mach-cpuimx35.c @@ -196,7 +196,7 @@ MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35") /* Maintainer: Eukrea Electromatique */ .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx35_map_io, - .init_ext3_fs = imx35_init_early, + .init_early = imx35_init_early, .init_irq = mx35_init_irq, .timer = &eukrea_cpuimx35_timer, .init_machine = eukrea_cpuimx35_init, -- cgit v0.10.2 From a5e2051b720fb5bcb35f0edfc80c108448acb713 Mon Sep 17 00:00:00 2001 From: Javier Martin Date: Tue, 1 Mar 2011 15:02:08 +0100 Subject: ARM: Add SSI and aic3204 code to Visstrim_M10 boards. Visstrim_M10 boards have an TI tlv320aic3204 codec attached to SSI1. Signed-off-by: Javier Martin Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index c172418..17e2c6d 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -265,6 +265,7 @@ config MACH_IMX27LITE bool "LogicPD MX27 LITEKIT platform" select SOC_IMX27 select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_IMX_SSI help Include support for MX27 LITEKIT platform. This includes specific configurations for the board and its peripherals. diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c index ffff2d0..d7e0d21 100644 --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c @@ -67,6 +67,11 @@ static const int visstrim_m10_pins[] __initconst = { PD15_AOUT_FEC_COL, PD16_AIN_FEC_TX_ER, PF23_AIN_FEC_TX_EN, + /* SSI1 */ + PC20_PF_SSI1_FS, + PC21_PF_SSI1_RXD, + PC22_PF_SSI1_TXD, + PC23_PF_SSI1_CLK, /* SDHC1 */ PE18_PF_SD1_D0, PE19_PF_SD1_D1, @@ -205,6 +210,9 @@ static struct i2c_board_info visstrim_m10_i2c_devices[] = { I2C_BOARD_INFO("pca9555", 0x20), .platform_data = &visstrim_m10_pca9555_pdata, }, + { + I2C_BOARD_INFO("tlv320aic32x4", 0x18), + } }; /* USB OTG */ @@ -223,6 +231,11 @@ visstrim_m10_usbotg_pdata __initconst = { .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, }; +/* SSI */ +static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = { + .flags = IMX_SSI_DMA | IMX_SSI_SYN, +}; + static void __init visstrim_m10_board_init(void) { int ret; @@ -232,6 +245,7 @@ static void __init visstrim_m10_board_init(void) if (ret) pr_err("Failed to setup pins (%d)\n", ret); + imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata); imx27_add_imx_uart0(&uart_pdata); i2c_register_board_info(0, visstrim_m10_i2c_devices, -- cgit v0.10.2 From 352cd9a0b849494a44a46c60219b8b6ea99f1d70 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 1 Mar 2011 16:59:44 -0300 Subject: ARM: mx35_3ds: Add I2C support Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 4f57f13..8b4b097 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -183,6 +183,7 @@ config MACH_MX35_3DS select MXC_DEBUG_BOARD select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c index be12ac1..5f35d5c 100644 --- a/arch/arm/mach-mx3/mach-mx35_3ds.c +++ b/arch/arm/mach-mx3/mach-mx35_3ds.c @@ -118,6 +118,9 @@ static iomux_v3_cfg_t mx35pdk_pads[] = { MX35_PAD_SD1_DATA1__ESDHC1_DAT1, MX35_PAD_SD1_DATA2__ESDHC1_DAT2, MX35_PAD_SD1_DATA3__ESDHC1_DAT3, + /* I2C1 */ + MX35_PAD_I2C1_CLK__I2C1_SCL, + MX35_PAD_I2C1_DAT__I2C1_SDA, }; static int mx35_3ds_otg_init(struct platform_device *pdev) @@ -163,6 +166,10 @@ static int __init mx35_3ds_otg_mode(char *options) } __setup("otg_mode=", mx35_3ds_otg_mode); +static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = { + .bitrate = 100000, +}; + /* * Board specific initialization. */ @@ -190,6 +197,7 @@ static void __init mx35_3ds_init(void) if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT)) pr_warn("Init of the debugboard failed, all " "devices on the debugboard are unusable.\n"); + imx35_add_imx_i2c0(&mx35_3ds_i2c0_data); } static void __init mx35pdk_timer_init(void) -- cgit v0.10.2 From 3d94302442cce1124a0adc0402bf609d9d8d808c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 1 Mar 2011 16:59:45 -0300 Subject: ARM: mx31_3ds: Add I2C support Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 8b4b097..340809a 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -94,6 +94,7 @@ config MACH_MX31_3DS select MXC_DEBUG_BOARD select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_KEYPAD select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_EHCI diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index b7d0953..35fdb2a 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -96,6 +96,9 @@ static int mx31_3ds_pins[] = { IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1), /* USB Host2 reset */ IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO), + /* I2C1 */ + MX31_PIN_I2C_CLK__I2C1_SCL, + MX31_PIN_I2C_DAT__I2C1_SDA, }; /* @@ -323,6 +326,10 @@ static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; +static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = { + .bitrate = 100000, +}; + static void __init mx31_3ds_init(void) { mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), @@ -356,6 +363,7 @@ static void __init mx31_3ds_init(void) printk(KERN_WARNING "Init of the debug board failed, all " "devices on the debug board are unusable.\n"); imx31_add_imx2_wdt(NULL); + imx31_add_imx_i2c0(&mx31_3ds_i2c0_data); } static void __init mx31_3ds_timer_init(void) -- cgit v0.10.2 From 5885f0362b3fbe476b7ef0af0beac7a114a0a8dd Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 1 Mar 2011 16:59:46 -0300 Subject: ARM: mx27_3ds: Add I2C support Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 17e2c6d..3f88df6 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -238,6 +238,7 @@ config MACH_MX27_3DS select SOC_IMX27 select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_KEYPAD select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_EHCI diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index ba88417..f4f2725 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c @@ -98,6 +98,9 @@ static const int mx27pdk_pins[] __initconst = { PD22_PF_CSPI2_SCLK, PD23_PF_CSPI2_MISO, PD24_PF_CSPI2_MOSI, + /* I2C1 */ + PD17_PF_I2C_DATA, + PD18_PF_I2C_CLK, }; static const struct imxuart_platform_data uart_pdata __initconst = { @@ -257,6 +260,9 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = { }, }; +static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = { + .bitrate = 100000, +}; static void __init mx27pdk_init(void) { @@ -286,6 +292,7 @@ static void __init mx27pdk_init(void) if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT)) pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n"); + imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data); } static void __init mx27pdk_timer_init(void) -- cgit v0.10.2 From ff864521a93ca3932e281828d41f709e107dad70 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 1 Mar 2011 16:59:47 -0300 Subject: ARM: mx25_3ds: Add I2C support Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 3f88df6..5eec099 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -100,6 +100,7 @@ config MACH_MX25_3DS select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMXDI_RTC + select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_FB select IMX_HAVE_PLATFORM_IMX_KEYPAD select IMX_HAVE_PLATFORM_IMX_UART diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c index 66b6cdd..06da438 100644 --- a/arch/arm/mach-imx/mach-mx25_3ds.c +++ b/arch/arm/mach-imx/mach-mx25_3ds.c @@ -103,6 +103,10 @@ static iomux_v3_cfg_t mx25pdk_pads[] = { MX25_PAD_SD1_DATA1__SD1_DATA1, MX25_PAD_SD1_DATA2__SD1_DATA2, MX25_PAD_SD1_DATA3__SD1_DATA3, + + /* I2C1 */ + MX25_PAD_I2C1_CLK__I2C1_CLK, + MX25_PAD_I2C1_DAT__I2C1_DAT, }; static const struct fec_platform_data mx25_fec_pdata __initconst = { @@ -200,6 +204,10 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .phy_mode = FSL_USB2_PHY_UTMI, }; +static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = { + .bitrate = 100000, +}; + static void __init mx25pdk_init(void) { mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, @@ -218,6 +226,7 @@ static void __init mx25pdk_init(void) imx25_add_imx_keypad(&mx25pdk_keymap_data); imx25_add_sdhci_esdhc_imx(0, NULL); + imx25_add_imx_i2c0(&mx25_3ds_i2c0_data); } static void __init mx25pdk_timer_init(void) -- cgit v0.10.2 From 2093023889b8c15bb90acb435e33e2843ef0153c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 1 Mar 2011 16:59:48 -0300 Subject: ARM: mx53_smd: Add I2C support Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index a72c833..03ec6e9 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -151,6 +151,7 @@ config MACH_MX53_SMD bool "Support MX53 SMD platforms" select SOC_IMX53 select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART help Include support for MX53 SMD platform. This includes specific diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c index 8a8694c..5eb1638 100644 --- a/arch/arm/mach-mx5/board-mx53_smd.c +++ b/arch/arm/mach-mx5/board-mx53_smd.c @@ -51,6 +51,9 @@ static iomux_v3_cfg_t mx53_smd_pads[] = { MX53_PAD_PATA_CS_1__UART3_RXD_MUX, MX53_PAD_PATA_DA_1__UART3_CTS, MX53_PAD_PATA_DA_2__UART3_RTS, + /* I2C1 */ + MX53_PAD_CSI0_DAT8__I2C1_SDA, + MX53_PAD_CSI0_DAT9__I2C1_SCL, }; static const struct imxuart_platform_data mx53_smd_uart_data __initconst = { @@ -83,6 +86,10 @@ static struct fec_platform_data mx53_smd_fec_data = { .phy = PHY_INTERFACE_MODE_RMII, }; +static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = { + .bitrate = 100000, +}; + static void __init mx53_smd_board_init(void) { mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads, @@ -91,6 +98,7 @@ static void __init mx53_smd_board_init(void) mx53_smd_fec_reset(); imx53_add_fec(&mx53_smd_fec_data); imx53_add_imx2_wdt(0, NULL); + imx53_add_imx_i2c(0, &mx53_smd_i2c_data); } static void __init mx53_smd_timer_init(void) -- cgit v0.10.2 From 10a3c45c6821d3ffe974bc5937693f18a16dd96c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 2 Mar 2011 10:59:48 +0100 Subject: ARM: iomux-imx31: allow pin_list to be const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes the following warning in a mx3_defconfig build: arch/arm/mach-mx3/mach-bug.c: In function 'bug_board_init': arch/arm/mach-mx3/mach-bug.c:47: warning: passing argument 1 of 'mxc_iomux_setup_multiple_pins' discards qualifiers from pointer target type While at it remove some useless consts from unsigned int arguments. Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/iomux-imx31.c b/arch/arm/mach-mx3/iomux-imx31.c index a1d7fa5..cf8f809 100644 --- a/arch/arm/mach-mx3/iomux-imx31.c +++ b/arch/arm/mach-mx3/iomux-imx31.c @@ -97,7 +97,7 @@ EXPORT_SYMBOL(mxc_iomux_set_pad); * - reserves the pin so that it is not claimed by another driver * - setups the iomux according to the configuration */ -int mxc_iomux_alloc_pin(const unsigned int pin, const char *label) +int mxc_iomux_alloc_pin(unsigned int pin, const char *label) { unsigned pad = pin & IOMUX_PADNUM_MASK; @@ -118,10 +118,10 @@ int mxc_iomux_alloc_pin(const unsigned int pin, const char *label) } EXPORT_SYMBOL(mxc_iomux_alloc_pin); -int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, +int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, const char *label) { - unsigned int *p = pin_list; + const unsigned int *p = pin_list; int i; int ret = -EINVAL; @@ -139,7 +139,7 @@ setup_error: } EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins); -void mxc_iomux_release_pin(const unsigned int pin) +void mxc_iomux_release_pin(unsigned int pin) { unsigned pad = pin & IOMUX_PADNUM_MASK; @@ -148,9 +148,9 @@ void mxc_iomux_release_pin(const unsigned int pin) } EXPORT_SYMBOL(mxc_iomux_release_pin); -void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count) +void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count) { - unsigned int *p = pin_list; + const unsigned int *p = pin_list; int i; for (i = 0; i < count; i++) { diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index cbaed29..c92f0b1 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -112,12 +112,12 @@ enum iomux_gp_func { * - setups the iomux according to the configuration * - if the pin is configured as a GPIO, we claim it through kernel gpiolib */ -int mxc_iomux_alloc_pin(const unsigned int pin, const char *label); +int mxc_iomux_alloc_pin(unsigned int pin, const char *label); /* * setups mutliple pins * convenient way to call the above function with tables */ -int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, +int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, const char *label); /* @@ -126,12 +126,12 @@ int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, * - frees the GPIO if the pin was configured as GPIO * - DOES NOT reconfigure the IOMUX in its reset state */ -void mxc_iomux_release_pin(const unsigned int pin); +void mxc_iomux_release_pin(unsigned int pin); /* * releases multiple pins * convenvient way to call the above function with tables */ -void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count); +void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count); /* * This function enables/disables the general purpose function for a particular -- cgit v0.10.2 From 8d8eb17765dc8e232e30a9fb55f89c0056fa17ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 2 Mar 2011 10:59:49 +0100 Subject: ARM: mxc91231/iomux: allow pin_list to be const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While at it remove some useless consts from unsigned int arguments. Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxc91231/iomux.c b/arch/arm/mach-mxc91231/iomux.c index 405d9b1..66fc41c 100644 --- a/arch/arm/mach-mxc91231/iomux.c +++ b/arch/arm/mach-mxc91231/iomux.c @@ -50,7 +50,7 @@ unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG]; /* * set the mode for a IOMUX pin. */ -int mxc_iomux_mode(const unsigned int pin_mode) +int mxc_iomux_mode(unsigned int pin_mode) { u32 side, field, l, mode, ret = 0; void __iomem *reg; @@ -114,7 +114,7 @@ EXPORT_SYMBOL(mxc_iomux_set_pad); * - reserves the pin so that it is not claimed by another driver * - setups the iomux according to the configuration */ -int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label) +int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label) { unsigned pad = PIN_GLOBAL_NUM(pin_mode); if (pad >= (PIN_MAX + 1)) { @@ -134,10 +134,10 @@ int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label) } EXPORT_SYMBOL(mxc_iomux_alloc_pin); -int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, +int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, const char *label) { - unsigned int *p = pin_list; + const unsigned int *p = pin_list; int i; int ret = -EINVAL; @@ -155,7 +155,7 @@ setup_error: } EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins); -void mxc_iomux_release_pin(const unsigned int pin_mode) +void mxc_iomux_release_pin(unsigned int pin_mode) { unsigned pad = PIN_GLOBAL_NUM(pin_mode); @@ -164,9 +164,9 @@ void mxc_iomux_release_pin(const unsigned int pin_mode) } EXPORT_SYMBOL(mxc_iomux_release_pin); -void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count) +void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count) { - unsigned int *p = pin_list; + const unsigned int *p = pin_list; int i; for (i = 0; i < count; i++) { diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h index 15d5951..bf28df0 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h @@ -46,12 +46,12 @@ * - setups the iomux according to the configuration * - if the pin is configured as a GPIO, we claim it through kernel gpiolib */ -int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label); +int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label); /* * setups mutliple pins * convenient way to call the above function with tables */ -int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, +int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, const char *label); /* @@ -60,12 +60,12 @@ int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, * - frees the GPIO if the pin was configured as GPIO * - DOES NOT reconfigure the IOMUX in its reset state */ -void mxc_iomux_release_pin(const unsigned int pin_mode); +void mxc_iomux_release_pin(unsigned int pin_mode); /* * releases multiple pins * convenvient way to call the above function with tables */ -void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count); +void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count); #define MUX_SIDE_AP (0) #define MUX_SIDE_SP (1) -- cgit v0.10.2 From f0a523b5e5e2db4e8518ae20f466c0a6be7e145e Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Jan 2011 15:22:31 +0100 Subject: video: Add i.MX23/28 framebuffer driver changes since v2: - use v3 and v4 for specifying the ip version instead of i.MX23/28. This is a better namespace when future versions are added. - rename mach/fb.h to mach/mxsfb.h changes since v1: - Add a LCDC_ prefix to the register names. - use set/clear registers where appropriate - protect call to mxsfb_disable_controller() in mxsfb_remove() with a (host->enabled) as suggested by Lothar Wassmann Signed-off-by: Sascha Hauer Acked-by: Shawn Guo Cc: Paul Mundt Cc: linux-fbdev@vger.kernel.org diff --git a/arch/arm/mach-mxs/include/mach/mxsfb.h b/arch/arm/mach-mxs/include/mach/mxsfb.h new file mode 100644 index 0000000..e4d7979 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/mxsfb.h @@ -0,0 +1,49 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_FB_H +#define __MACH_FB_H + +#include + +#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */ +#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */ +#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */ +#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */ + +#define FB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6) +#define FB_SYNC_DOTCLK_FAILING_ACT (1 << 7) /* failing/negtive edge sampling */ + +struct mxsfb_platform_data { + struct fb_videomode *mode_list; + unsigned mode_count; + + unsigned default_bpp; + + unsigned dotclk_delay; /* refer manual HW_LCDIF_VDCTRL4 register */ + unsigned ld_intf_width; /* refer STMLCDIF_* macros */ + + unsigned fb_size; /* Size of the video memory. If zero a + * default will be used + */ + unsigned long fb_phys; /* physical address for the video memory. If + * zero the framebuffer memory will be dynamically + * allocated. If specified,fb_size must also be specified. + * fb_phys must be unused by Linux. + */ +}; + +#endif /* __MACH_FB_H */ diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 6bafb51b..e0ea23f 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -2365,6 +2365,15 @@ config FB_JZ4740 help Framebuffer support for the JZ4740 SoC. +config FB_MXS + tristate "MXS LCD framebuffer support" + depends on FB && ARCH_MXS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + Framebuffer support for the MXS SoC. + source "drivers/video/omap/Kconfig" source "drivers/video/omap2/Kconfig" diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 8c8fabd..9a096ae 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -153,6 +153,7 @@ obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o obj-$(CONFIG_FB_BFIN_7393) += bfin_adv7393fb.o obj-$(CONFIG_FB_MX3) += mx3fb.o obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o +obj-$(CONFIG_FB_MXS) += mxsfb.o # the test framebuffer is last obj-$(CONFIG_FB_VIRTUAL) += vfb.o diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c new file mode 100644 index 0000000..7d02848 --- /dev/null +++ b/drivers/video/mxsfb.c @@ -0,0 +1,919 @@ +/* + * Copyright (C) 2010 Juergen Beisert, Pengutronix + * + * This code is based on: + * Author: Vitaly Wool + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DRIVER_NAME "mxsfb" + +/** + * @file + * @brief LCDIF driver for i.MX23 and i.MX28 + * + * The LCDIF support four modes of operation + * - MPU interface (to drive smart displays) -> not supported yet + * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet + * - Dotclock interface (to drive LC displays with RGB data and sync signals) + * - DVI (to drive ITU-R BT656) -> not supported yet + * + * This driver depends on a correct setup of the pins used for this purpose + * (platform specific). + * + * For the developer: Don't forget to set the data bus width to the display + * in the imx_fb_videomode structure. You will else end up with ugly colours. + * If you fight against jitter you can vary the clock delay. This is a feature + * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give + * the required value in the imx_fb_videomode structure. + */ + +#include +#include +#include +#include +#include +#include + +#define REG_SET 4 +#define REG_CLR 8 + +#define LCDC_CTRL 0x00 +#define LCDC_CTRL1 0x10 +#define LCDC_V4_CTRL2 0x20 +#define LCDC_V3_TRANSFER_COUNT 0x20 +#define LCDC_V4_TRANSFER_COUNT 0x30 +#define LCDC_V4_CUR_BUF 0x40 +#define LCDC_V4_NEXT_BUF 0x50 +#define LCDC_V3_CUR_BUF 0x30 +#define LCDC_V3_NEXT_BUF 0x40 +#define LCDC_TIMING 0x60 +#define LCDC_VDCTRL0 0x70 +#define LCDC_VDCTRL1 0x80 +#define LCDC_VDCTRL2 0x90 +#define LCDC_VDCTRL3 0xa0 +#define LCDC_VDCTRL4 0xb0 +#define LCDC_DVICTRL0 0xc0 +#define LCDC_DVICTRL1 0xd0 +#define LCDC_DVICTRL2 0xe0 +#define LCDC_DVICTRL3 0xf0 +#define LCDC_DVICTRL4 0x100 +#define LCDC_V4_DATA 0x180 +#define LCDC_V3_DATA 0x1b0 +#define LCDC_V4_DEBUG0 0x1d0 +#define LCDC_V3_DEBUG0 0x1f0 + +#define CTRL_SFTRST (1 << 31) +#define CTRL_CLKGATE (1 << 30) +#define CTRL_BYPASS_COUNT (1 << 19) +#define CTRL_VSYNC_MODE (1 << 18) +#define CTRL_DOTCLK_MODE (1 << 17) +#define CTRL_DATA_SELECT (1 << 16) +#define CTRL_SET_BUS_WIDTH(x) (((x) & 0x3) << 10) +#define CTRL_GET_BUS_WIDTH(x) (((x) >> 10) & 0x3) +#define CTRL_SET_WORD_LENGTH(x) (((x) & 0x3) << 8) +#define CTRL_GET_WORD_LENGTH(x) (((x) >> 8) & 0x3) +#define CTRL_MASTER (1 << 5) +#define CTRL_DF16 (1 << 3) +#define CTRL_DF18 (1 << 2) +#define CTRL_DF24 (1 << 1) +#define CTRL_RUN (1 << 0) + +#define CTRL1_FIFO_CLEAR (1 << 21) +#define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16) +#define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf) + +#define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16) +#define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff) +#define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff) +#define TRANSFER_COUNT_GET_HCOUNT(x) ((x) & 0xffff) + + +#define VDCTRL0_ENABLE_PRESENT (1 << 28) +#define VDCTRL0_VSYNC_ACT_HIGH (1 << 27) +#define VDCTRL0_HSYNC_ACT_HIGH (1 << 26) +#define VDCTRL0_DOTCLK_ACT_FAILING (1 << 25) +#define VDCTRL0_ENABLE_ACT_HIGH (1 << 24) +#define VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) +#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) +#define VDCTRL0_HALF_LINE (1 << 19) +#define VDCTRL0_HALF_LINE_MODE (1 << 18) +#define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) +#define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) + +#define VDCTRL2_SET_HSYNC_PERIOD(x) ((x) & 0x3ffff) +#define VDCTRL2_GET_HSYNC_PERIOD(x) ((x) & 0x3ffff) + +#define VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) +#define VDCTRL3_VSYNC_ONLY (1 << 28) +#define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16) +#define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff) +#define SET_VERT_WAIT_CNT(x) ((x) & 0xffff) +#define GET_VERT_WAIT_CNT(x) ((x) & 0xffff) + +#define VDCTRL4_SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) /* v4 only */ +#define VDCTRL4_GET_DOTCLK_DLY(x) (((x) >> 29) & 0x7) /* v4 only */ +#define VDCTRL4_SYNC_SIGNALS_ON (1 << 18) +#define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff) + +#define DEBUG0_HSYNC (1 < 26) +#define DEBUG0_VSYNC (1 < 25) + +#define MIN_XRES 120 +#define MIN_YRES 120 + +#define RED 0 +#define GREEN 1 +#define BLUE 2 +#define TRANSP 3 + +enum mxsfb_devtype { + MXSFB_V3, + MXSFB_V4, +}; + +/* CPU dependent register offsets */ +struct mxsfb_devdata { + unsigned transfer_count; + unsigned cur_buf; + unsigned next_buf; + unsigned debug0; + unsigned hs_wdth_mask; + unsigned hs_wdth_shift; + unsigned ipversion; +}; + +struct mxsfb_info { + struct fb_info fb_info; + struct platform_device *pdev; + struct clk *clk; + void __iomem *base; /* registers */ + unsigned allocated_size; + int enabled; + unsigned ld_intf_width; + unsigned dotclk_delay; + const struct mxsfb_devdata *devdata; + int mapped; +}; + +#define mxsfb_is_v3(host) (host->devdata->ipversion == 3) +#define mxsfb_is_v4(host) (host->devdata->ipversion == 4) + +static const struct mxsfb_devdata mxsfb_devdata[] = { + [MXSFB_V3] = { + .transfer_count = LCDC_V3_TRANSFER_COUNT, + .cur_buf = LCDC_V3_CUR_BUF, + .next_buf = LCDC_V3_NEXT_BUF, + .debug0 = LCDC_V3_DEBUG0, + .hs_wdth_mask = 0xff, + .hs_wdth_shift = 24, + .ipversion = 3, + }, + [MXSFB_V4] = { + .transfer_count = LCDC_V4_TRANSFER_COUNT, + .cur_buf = LCDC_V4_CUR_BUF, + .next_buf = LCDC_V4_NEXT_BUF, + .debug0 = LCDC_V4_DEBUG0, + .hs_wdth_mask = 0x3fff, + .hs_wdth_shift = 18, + .ipversion = 4, + }, +}; + +#define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info)) + +/* mask and shift depends on architecture */ +static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val) +{ + return (val & host->devdata->hs_wdth_mask) << + host->devdata->hs_wdth_shift; +} + +static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val) +{ + return (val >> host->devdata->hs_wdth_shift) & + host->devdata->hs_wdth_mask; +} + +static const struct fb_bitfield def_rgb565[] = { + [RED] = { + .offset = 11, + .length = 5, + }, + [GREEN] = { + .offset = 5, + .length = 6, + }, + [BLUE] = { + .offset = 0, + .length = 5, + }, + [TRANSP] = { /* no support for transparency */ + .length = 0, + } +}; + +static const struct fb_bitfield def_rgb666[] = { + [RED] = { + .offset = 16, + .length = 6, + }, + [GREEN] = { + .offset = 8, + .length = 6, + }, + [BLUE] = { + .offset = 0, + .length = 6, + }, + [TRANSP] = { /* no support for transparency */ + .length = 0, + } +}; + +static const struct fb_bitfield def_rgb888[] = { + [RED] = { + .offset = 16, + .length = 8, + }, + [GREEN] = { + .offset = 8, + .length = 8, + }, + [BLUE] = { + .offset = 0, + .length = 8, + }, + [TRANSP] = { /* no support for transparency */ + .length = 0, + } +}; + +static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf) +{ + chan &= 0xffff; + chan >>= 16 - bf->length; + return chan << bf->offset; +} + +static int mxsfb_check_var(struct fb_var_screeninfo *var, + struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + const struct fb_bitfield *rgb = NULL; + + if (var->xres < MIN_XRES) + var->xres = MIN_XRES; + if (var->yres < MIN_YRES) + var->yres = MIN_YRES; + + var->xres_virtual = var->xres; + + var->yres_virtual = var->yres; + + switch (var->bits_per_pixel) { + case 16: + /* always expect RGB 565 */ + rgb = def_rgb565; + break; + case 32: + switch (host->ld_intf_width) { + case STMLCDIF_8BIT: + pr_debug("Unsupported LCD bus width mapping\n"); + break; + case STMLCDIF_16BIT: + case STMLCDIF_18BIT: + /* 24 bit to 18 bit mapping */ + rgb = def_rgb666; + break; + case STMLCDIF_24BIT: + /* real 24 bit */ + rgb = def_rgb888; + break; + } + break; + default: + pr_debug("Unsupported colour depth: %u\n", var->bits_per_pixel); + return -EINVAL; + } + + /* + * Copy the RGB parameters for this display + * from the machine specific parameters. + */ + var->red = rgb[RED]; + var->green = rgb[GREEN]; + var->blue = rgb[BLUE]; + var->transp = rgb[TRANSP]; + + return 0; +} + +static void mxsfb_enable_controller(struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + u32 reg; + + dev_dbg(&host->pdev->dev, "%s\n", __func__); + + clk_enable(host->clk); + clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U); + + /* if it was disabled, re-enable the mode again */ + writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET); + + /* enable the SYNC signals first, then the DMA engine */ + reg = readl(host->base + LCDC_VDCTRL4); + reg |= VDCTRL4_SYNC_SIGNALS_ON; + writel(reg, host->base + LCDC_VDCTRL4); + + writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET); + + host->enabled = 1; +} + +static void mxsfb_disable_controller(struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + unsigned loop; + u32 reg; + + dev_dbg(&host->pdev->dev, "%s\n", __func__); + + /* + * Even if we disable the controller here, it will still continue + * until its FIFOs are running out of data + */ + writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR); + + loop = 1000; + while (loop) { + reg = readl(host->base + LCDC_CTRL); + if (!(reg & CTRL_RUN)) + break; + loop--; + } + + writel(VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4 + REG_CLR); + + clk_disable(host->clk); + + host->enabled = 0; +} + +static int mxsfb_set_par(struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + u32 ctrl, vdctrl0, vdctrl4; + int line_size, fb_size; + int reenable = 0; + + line_size = fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3); + fb_size = fb_info->var.yres_virtual * line_size; + + if (fb_size > fb_info->fix.smem_len) + return -ENOMEM; + + fb_info->fix.line_length = line_size; + + /* + * It seems, you can't re-program the controller if it is still running. + * This may lead into shifted pictures (FIFO issue?). + * So, first stop the controller and drain its FIFOs + */ + if (host->enabled) { + reenable = 1; + mxsfb_disable_controller(fb_info); + } + + /* clear the FIFOs */ + writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET); + + ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER | + CTRL_SET_BUS_WIDTH(host->ld_intf_width);; + + switch (fb_info->var.bits_per_pixel) { + case 16: + dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n"); + ctrl |= CTRL_SET_WORD_LENGTH(0); + writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1); + break; + case 32: + dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n"); + ctrl |= CTRL_SET_WORD_LENGTH(3); + switch (host->ld_intf_width) { + case STMLCDIF_8BIT: + dev_dbg(&host->pdev->dev, + "Unsupported LCD bus width mapping\n"); + return -EINVAL; + case STMLCDIF_16BIT: + case STMLCDIF_18BIT: + /* 24 bit to 18 bit mapping */ + ctrl |= CTRL_DF24; /* ignore the upper 2 bits in + * each colour component + */ + break; + case STMLCDIF_24BIT: + /* real 24 bit */ + break; + } + /* do not use packed pixels = one pixel per word instead */ + writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1); + break; + default: + dev_dbg(&host->pdev->dev, "Unhandled color depth of %u\n", + fb_info->var.bits_per_pixel); + return -EINVAL; + } + + writel(ctrl, host->base + LCDC_CTRL); + + writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) | + TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres), + host->base + host->devdata->transfer_count); + + vdctrl0 = VDCTRL0_ENABLE_PRESENT | /* always in DOTCLOCK mode */ + VDCTRL0_VSYNC_PERIOD_UNIT | + VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | + VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len); + if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT) + vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH; + if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT) + vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH; + if (fb_info->var.sync & FB_SYNC_DATA_ENABLE_HIGH_ACT) + vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH; + if (fb_info->var.sync & FB_SYNC_DOTCLK_FAILING_ACT) + vdctrl0 |= VDCTRL0_DOTCLK_ACT_FAILING; + + writel(vdctrl0, host->base + LCDC_VDCTRL0); + + /* frame length in lines */ + writel(fb_info->var.upper_margin + fb_info->var.vsync_len + + fb_info->var.lower_margin + fb_info->var.yres, + host->base + LCDC_VDCTRL1); + + /* line length in units of clocks or pixels */ + writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) | + VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin + + fb_info->var.hsync_len + fb_info->var.right_margin + + fb_info->var.xres), + host->base + LCDC_VDCTRL2); + + writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin + + fb_info->var.hsync_len) | + SET_VERT_WAIT_CNT(fb_info->var.upper_margin + + fb_info->var.vsync_len), + host->base + LCDC_VDCTRL3); + + vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres); + if (mxsfb_is_v4(host)) + vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay); + writel(vdctrl4, host->base + LCDC_VDCTRL4); + + writel(fb_info->fix.smem_start + + fb_info->fix.line_length * fb_info->var.yoffset, + host->base + host->devdata->next_buf); + + if (reenable) + mxsfb_enable_controller(fb_info); + + return 0; +} + +static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, + u_int transp, struct fb_info *fb_info) +{ + unsigned int val; + int ret = -EINVAL; + + /* + * If greyscale is true, then we convert the RGB value + * to greyscale no matter what visual we are using. + */ + if (fb_info->var.grayscale) + red = green = blue = (19595 * red + 38470 * green + + 7471 * blue) >> 16; + + switch (fb_info->fix.visual) { + case FB_VISUAL_TRUECOLOR: + /* + * 12 or 16-bit True Colour. We encode the RGB value + * according to the RGB bitfield information. + */ + if (regno < 16) { + u32 *pal = fb_info->pseudo_palette; + + val = chan_to_field(red, &fb_info->var.red); + val |= chan_to_field(green, &fb_info->var.green); + val |= chan_to_field(blue, &fb_info->var.blue); + + pal[regno] = val; + ret = 0; + } + break; + + case FB_VISUAL_STATIC_PSEUDOCOLOR: + case FB_VISUAL_PSEUDOCOLOR: + break; + } + + return ret; +} + +static int mxsfb_blank(int blank, struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + + switch (blank) { + case FB_BLANK_POWERDOWN: + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + case FB_BLANK_NORMAL: + if (host->enabled) + mxsfb_disable_controller(fb_info); + break; + + case FB_BLANK_UNBLANK: + if (!host->enabled) + mxsfb_enable_controller(fb_info); + break; + } + return 0; +} + +static int mxsfb_pan_display(struct fb_var_screeninfo *var, + struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + unsigned offset; + + if (var->xoffset != 0) + return -EINVAL; + + offset = fb_info->fix.line_length * var->yoffset; + + /* update on next VSYNC */ + writel(fb_info->fix.smem_start + offset, + host->base + host->devdata->next_buf); + + return 0; +} + +static struct fb_ops mxsfb_ops = { + .owner = THIS_MODULE, + .fb_check_var = mxsfb_check_var, + .fb_set_par = mxsfb_set_par, + .fb_setcolreg = mxsfb_setcolreg, + .fb_blank = mxsfb_blank, + .fb_pan_display = mxsfb_pan_display, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, +}; + +static int __devinit mxsfb_restore_mode(struct mxsfb_info *host) +{ + struct fb_info *fb_info = &host->fb_info; + unsigned line_count; + unsigned period; + unsigned long pa, fbsize; + int bits_per_pixel, ofs; + u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl; + struct fb_videomode vmode; + + /* Only restore the mode when the controller is running */ + ctrl = readl(host->base + LCDC_CTRL); + if (!(ctrl & CTRL_RUN)) + return -EINVAL; + + vdctrl0 = readl(host->base + LCDC_VDCTRL0); + vdctrl2 = readl(host->base + LCDC_VDCTRL2); + vdctrl3 = readl(host->base + LCDC_VDCTRL3); + vdctrl4 = readl(host->base + LCDC_VDCTRL4); + + transfer_count = readl(host->base + host->devdata->transfer_count); + + vmode.xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count); + vmode.yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count); + + switch (CTRL_GET_WORD_LENGTH(ctrl)) { + case 0: + bits_per_pixel = 16; + break; + case 3: + bits_per_pixel = 32; + case 1: + default: + return -EINVAL; + } + + fb_info->var.bits_per_pixel = bits_per_pixel; + + vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U); + vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2); + vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len; + vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len - + vmode.left_margin - vmode.xres; + vmode.vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0); + period = readl(host->base + LCDC_VDCTRL1); + vmode.upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode.vsync_len; + vmode.lower_margin = period - vmode.vsync_len - vmode.upper_margin - vmode.yres; + + vmode.vmode = FB_VMODE_NONINTERLACED; + + vmode.sync = 0; + if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH) + vmode.sync |= FB_SYNC_HOR_HIGH_ACT; + if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH) + vmode.sync |= FB_SYNC_VERT_HIGH_ACT; + + pr_debug("Reconstructed video mode:\n"); + pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n", + vmode.xres, vmode.yres, + vmode.hsync_len, vmode.left_margin, vmode.right_margin, + vmode.vsync_len, vmode.upper_margin, vmode.lower_margin); + pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode.pixclock)); + + fb_add_videomode(&vmode, &fb_info->modelist); + + host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl); + host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4); + + fb_info->fix.line_length = vmode.xres * (bits_per_pixel >> 3); + + pa = readl(host->base + host->devdata->cur_buf); + fbsize = fb_info->fix.line_length * vmode.yres; + if (pa < fb_info->fix.smem_start) + return -EINVAL; + if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len) + return -EINVAL; + ofs = pa - fb_info->fix.smem_start; + if (ofs) { + memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize); + writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf); + } + + line_count = fb_info->fix.smem_len / fb_info->fix.line_length; + fb_info->fix.ypanstep = 1; + + clk_enable(host->clk); + host->enabled = 1; + + return 0; +} + +static int __devinit mxsfb_init_fbinfo(struct mxsfb_info *host) +{ + struct fb_info *fb_info = &host->fb_info; + struct fb_var_screeninfo *var = &fb_info->var; + struct mxsfb_platform_data *pdata = host->pdev->dev.platform_data; + dma_addr_t fb_phys; + void *fb_virt; + unsigned fb_size = pdata->fb_size; + + fb_info->fbops = &mxsfb_ops; + fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST; + strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id)); + fb_info->fix.type = FB_TYPE_PACKED_PIXELS; + fb_info->fix.ypanstep = 1; + fb_info->fix.visual = FB_VISUAL_TRUECOLOR, + fb_info->fix.accel = FB_ACCEL_NONE; + + var->bits_per_pixel = pdata->default_bpp ? pdata->default_bpp : 16; + var->nonstd = 0; + var->activate = FB_ACTIVATE_NOW; + var->accel_flags = 0; + var->vmode = FB_VMODE_NONINTERLACED; + + host->dotclk_delay = pdata->dotclk_delay; + host->ld_intf_width = pdata->ld_intf_width; + + /* Memory allocation for framebuffer */ + if (pdata->fb_phys) { + if (!fb_size) + return -EINVAL; + + fb_phys = pdata->fb_phys; + + if (!request_mem_region(fb_phys, fb_size, host->pdev->name)) + return -ENOMEM; + + fb_virt = ioremap(fb_phys, fb_size); + if (!fb_virt) { + release_mem_region(fb_phys, fb_size); + return -ENOMEM; + } + host->mapped = 1; + } else { + if (!fb_size) + fb_size = SZ_2M; /* default */ + fb_virt = alloc_pages_exact(fb_size, GFP_DMA); + if (!fb_virt) + return -ENOMEM; + + fb_phys = virt_to_phys(fb_virt); + } + + fb_info->fix.smem_start = fb_phys; + fb_info->screen_base = fb_virt; + fb_info->screen_size = fb_info->fix.smem_len = fb_size; + + if (mxsfb_restore_mode(host)) + memset(fb_virt, 0, fb_size); + + return 0; +} + +static void __devexit mxsfb_free_videomem(struct mxsfb_info *host) +{ + struct fb_info *fb_info = &host->fb_info; + + if (host->mapped) { + iounmap(fb_info->screen_base); + release_mem_region(fb_info->fix.smem_start, + fb_info->screen_size); + } else { + free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len); + } +} + +static int __devinit mxsfb_probe(struct platform_device *pdev) +{ + struct mxsfb_platform_data *pdata = pdev->dev.platform_data; + struct resource *res; + struct mxsfb_info *host; + struct fb_info *fb_info; + struct fb_modelist *modelist; + int i, ret; + + if (!pdata) { + dev_err(&pdev->dev, "No platformdata. Giving up\n"); + return -ENODEV; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Cannot get memory IO resource\n"); + return -ENODEV; + } + + if (!request_mem_region(res->start, resource_size(res), pdev->name)) + return -EBUSY; + + fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev); + if (!fb_info) { + dev_err(&pdev->dev, "Failed to allocate fbdev\n"); + ret = -ENOMEM; + goto error_alloc_info; + } + + host = to_imxfb_host(fb_info); + + host->base = ioremap(res->start, resource_size(res)); + if (!host->base) { + dev_err(&pdev->dev, "ioremap failed\n"); + ret = -ENOMEM; + goto error_ioremap; + } + + host->pdev = pdev; + platform_set_drvdata(pdev, host); + + host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data]; + + host->clk = clk_get(&host->pdev->dev, NULL); + if (IS_ERR(host->clk)) { + ret = PTR_ERR(host->clk); + goto error_getclock; + } + + fb_info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL); + if (!fb_info->pseudo_palette) { + ret = -ENOMEM; + goto error_pseudo_pallette; + } + + INIT_LIST_HEAD(&fb_info->modelist); + + ret = mxsfb_init_fbinfo(host); + if (ret != 0) + goto error_init_fb; + + for (i = 0; i < pdata->mode_count; i++) + fb_add_videomode(&pdata->mode_list[i], &fb_info->modelist); + + modelist = list_first_entry(&fb_info->modelist, + struct fb_modelist, list); + fb_videomode_to_var(&fb_info->var, &modelist->mode); + + /* init the color fields */ + mxsfb_check_var(&fb_info->var, fb_info); + + platform_set_drvdata(pdev, fb_info); + + ret = register_framebuffer(fb_info); + if (ret != 0) { + dev_err(&pdev->dev,"Failed to register framebuffer\n"); + goto error_register; + } + + if (!host->enabled) { + writel(0, host->base + LCDC_CTRL); + mxsfb_set_par(fb_info); + mxsfb_enable_controller(fb_info); + } + + dev_info(&pdev->dev, "initialized\n"); + + return 0; + +error_register: + if (host->enabled) + clk_disable(host->clk); + fb_destroy_modelist(&fb_info->modelist); +error_init_fb: + kfree(fb_info->pseudo_palette); +error_pseudo_pallette: + clk_put(host->clk); +error_getclock: + iounmap(host->base); +error_ioremap: + framebuffer_release(fb_info); +error_alloc_info: + release_mem_region(res->start, resource_size(res)); + + return ret; +} + +static int __devexit mxsfb_remove(struct platform_device *pdev) +{ + struct fb_info *fb_info = platform_get_drvdata(pdev); + struct mxsfb_info *host = to_imxfb_host(fb_info); + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (host->enabled) + mxsfb_disable_controller(fb_info); + + unregister_framebuffer(fb_info); + kfree(fb_info->pseudo_palette); + mxsfb_free_videomem(host); + iounmap(host->base); + clk_put(host->clk); + + framebuffer_release(fb_info); + release_mem_region(res->start, resource_size(res)); + + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_device_id mxsfb_devtype[] = { + { + .name = "imx23-fb", + .driver_data = MXSFB_V3, + }, { + .name = "imx28-fb", + .driver_data = MXSFB_V4, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(platform, mxsfb_devtype); + +static struct platform_driver mxsfb_driver = { + .probe = mxsfb_probe, + .remove = __devexit_p(mxsfb_remove), + .id_table = mxsfb_devtype, + .driver = { + .name = DRIVER_NAME, + }, +}; + +static int __init mxsfb_init(void) +{ + return platform_driver_register(&mxsfb_driver); +} + +static void __exit mxsfb_exit(void) +{ + platform_driver_unregister(&mxsfb_driver); +} + +module_init(mxsfb_init); +module_exit(mxsfb_exit); + +MODULE_DESCRIPTION("Freescale mxs framebuffer driver"); +MODULE_AUTHOR("Sascha Hauer, Pengutronix"); +MODULE_LICENSE("GPL"); -- cgit v0.10.2 From 2e8fd696145819c6c5d6ac08c603af655e7f2298 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Jan 2011 15:32:49 +0100 Subject: ARM i.MX23/28: Add framebuffer device support Signed-off-by: Sascha Hauer Cc: Shawn Guo diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c index 38ee1b1..2415b33 100644 --- a/arch/arm/mach-mxs/clock-mx23.c +++ b/arch/arm/mach-mxs/clock-mx23.c @@ -452,6 +452,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk) _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk) _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk) + _REGISTER_CLOCK("imx23-fb", NULL, lcdif_clk) }; static int clk_misc_init(void) diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 40726c7..8277056 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -632,6 +632,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxs-pwm.7", NULL, pwm_clk) _REGISTER_CLOCK(NULL, "lradc", lradc_clk) _REGISTER_CLOCK(NULL, "spdif", spdif_clk) + _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk) }; static int clk_misc_init(void) diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h index 7fb27b1..c7e14f4 100644 --- a/arch/arm/mach-mxs/devices-mx23.h +++ b/arch/arm/mach-mxs/devices-mx23.h @@ -10,6 +10,7 @@ */ #include #include +#include extern const struct amba_device mx23_duart_device __initconst; #define mx23_add_duart() \ @@ -21,3 +22,6 @@ extern const struct mxs_auart_data mx23_auart_data[] __initconst; #define mx23_add_auart1() mx23_add_auart(1) #define mx23_add_mxs_pwm(id) mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id) + +struct platform_device *__init mx23_add_mxsfb( + const struct mxsfb_platform_data *pdata); diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h index a9eecdc..9d08555 100644 --- a/arch/arm/mach-mxs/devices-mx28.h +++ b/arch/arm/mach-mxs/devices-mx28.h @@ -10,6 +10,7 @@ */ #include #include +#include extern const struct amba_device mx28_duart_device __initconst; #define mx28_add_duart() \ @@ -37,3 +38,6 @@ extern const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst; #define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id]) #define mx28_add_mxs_pwm(id) mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id) + +struct platform_device *__init mx28_add_mxsfb( + const struct mxsfb_platform_data *pdata); diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig index a878915..1451ad0 100644 --- a/arch/arm/mach-mxs/devices/Kconfig +++ b/arch/arm/mach-mxs/devices/Kconfig @@ -17,3 +17,6 @@ config MXS_HAVE_PLATFORM_MXS_I2C config MXS_HAVE_PLATFORM_MXS_PWM bool + +config MXS_HAVE_PLATFORM_MXSFB + bool diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile index 345b839..39bd773 100644 --- a/arch/arm/mach-mxs/devices/Makefile +++ b/arch/arm/mach-mxs/devices/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o +obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c new file mode 100644 index 0000000..bf72c9b --- /dev/null +++ b/arch/arm/mach-mxs/devices/platform-mxsfb.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2011 Pengutronix, Sascha Hauer + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include +#include +#include +#include + +#ifdef CONFIG_SOC_IMX23 +struct platform_device *__init mx23_add_mxsfb( + const struct mxsfb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = MX23_LCDIF_BASE_ADDR, + .end = MX23_LCDIF_BASE_ADDR + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, + }; + + return mxs_add_platform_device_dmamask("imx23-fb", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} +#endif /* ifdef CONFIG_SOC_IMX23 */ + +#ifdef CONFIG_SOC_IMX28 +struct platform_device *__init mx28_add_mxsfb( + const struct mxsfb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = MX28_LCDIF_BASE_ADDR, + .end = MX28_LCDIF_BASE_ADDR + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, + }; + + return mxs_add_platform_device_dmamask("imx28-fb", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} +#endif /* ifdef CONFIG_SOC_IMX28 */ -- cgit v0.10.2 From 761b6d1a3efd50b3f15f9e78615297802e0f91d2 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 1 Mar 2011 10:21:51 +0100 Subject: arm: mxs: add irq_chip-name for GPIO IRQs Reported-by: Alexander Stein Signed-off-by: Wolfram Sang Acked-by: Shawn Guo Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c index 64848fa..5120ab5 100644 --- a/arch/arm/mach-mxs/gpio.c +++ b/arch/arm/mach-mxs/gpio.c @@ -182,6 +182,7 @@ static int mxs_gpio_set_wake_irq(u32 irq, u32 enable) } static struct irq_chip gpio_irq_chip = { + .name = "mxs gpio", .ack = mxs_gpio_ack_irq, .mask = mxs_gpio_mask_irq, .unmask = mxs_gpio_unmask_irq, -- cgit v0.10.2 From 1a46cce8564b3f4e42c283bd7d18ad9674383ef5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 2 Mar 2011 11:26:49 -0300 Subject: ARM: mx3/mx35_3ds: Use MX35 USB OTG Erratum Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c index 5f35d5c..ff5fe23 100644 --- a/arch/arm/mach-mx3/mach-mx35_3ds.c +++ b/arch/arm/mach-mx3/mach-mx35_3ds.c @@ -132,6 +132,11 @@ static int mx35_3ds_otg_init(struct platform_device *pdev) static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_UTMI_WIDE, + .workaround = FLS_USB2_WORKAROUND_ENGCM09152, +/* + * ENGCM09152 also requires a hardware change. + * Please check the MX35 Chip Errata document for details. + */ }; static struct mxc_usbh_platform_data otg_pdata __initdata = { -- cgit v0.10.2 From d79c01b0a212ae25c7b2c63274fffacf38dbcaaa Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 2 Mar 2011 13:30:52 -0300 Subject: ARM: mx5/mx53_smd: Fix IOMUX for UART2 On mx53_smd board only RX/TX pins are used on UART2. Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c index 5eb1638..31e1732 100644 --- a/arch/arm/mach-mx5/board-mx53_smd.c +++ b/arch/arm/mach-mx5/board-mx53_smd.c @@ -44,8 +44,6 @@ static iomux_v3_cfg_t mx53_smd_pads[] = { MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, - MX53_PAD_PATA_DIOR__UART2_RTS, - MX53_PAD_PATA_INTRQ__UART2_CTS, MX53_PAD_PATA_CS_0__UART3_TXD_MUX, MX53_PAD_PATA_CS_1__UART3_RXD_MUX, @@ -63,7 +61,7 @@ static const struct imxuart_platform_data mx53_smd_uart_data __initconst = { static inline void mx53_smd_init_uart(void) { imx53_add_imx_uart(0, NULL); - imx53_add_imx_uart(1, &mx53_smd_uart_data); + imx53_add_imx_uart(1, NULL); imx53_add_imx_uart(2, &mx53_smd_uart_data); } -- cgit v0.10.2 From 54c4bd658ee7cfdaec57d5fb8677e9bf8a380df5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 2 Mar 2011 13:30:53 -0300 Subject: ARM: mx5/mx53_evk: Fix IOMUX for UART3 On mx53_evk board only RX/TX pins are used on UART3. Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c index 652e1e0..7b5735c 100644 --- a/arch/arm/mach-mx5/board-mx53_evk.c +++ b/arch/arm/mach-mx5/board-mx53_evk.c @@ -52,8 +52,6 @@ static iomux_v3_cfg_t mx53_evk_pads[] = { MX53_PAD_PATA_CS_0__UART3_TXD_MUX, MX53_PAD_PATA_CS_1__UART3_RXD_MUX, - MX53_PAD_PATA_DA_1__UART3_CTS, - MX53_PAD_PATA_DA_2__UART3_RTS, MX53_PAD_EIM_D16__ECSPI1_SCLK, MX53_PAD_EIM_D17__ECSPI1_MISO, @@ -72,7 +70,7 @@ static inline void mx53_evk_init_uart(void) { imx53_add_imx_uart(0, NULL); imx53_add_imx_uart(1, &mx53_evk_uart_pdata); - imx53_add_imx_uart(2, &mx53_evk_uart_pdata); + imx53_add_imx_uart(2, NULL); } static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = { -- cgit v0.10.2 From 9685a3609d7f15297987c511c323b43693317960 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Wed, 2 Mar 2011 08:11:05 +0000 Subject: MX1: Add structure, registration functions for framebuffer and rename LCDC INT Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h index fd26715..da59365 100644 --- a/arch/arm/mach-imx/devices-imx1.h +++ b/arch/arm/mach-imx/devices-imx1.h @@ -9,6 +9,10 @@ #include #include +extern const struct imx_imx_fb_data imx1_imx_fb_data __initconst; +#define imx1_add_imx_fb(pdata) \ + imx_add_imx_fb(&imx1_imx_fb_data, pdata) + extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst; #define imx1_add_imx_i2c(pdata) \ imx_add_imx_i2c(&imx1_imx_i2c_data, pdata) diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c index 6100a7d..79a1cb1 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-fb.c +++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c @@ -16,6 +16,11 @@ .irq = soc ## _INT_LCDC, \ } +#ifdef CONFIG_SOC_IMX1 +const struct imx_imx_fb_data imx1_imx_fb_data __initconst = + imx_imx_fb_data_entry_single(MX1, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX1 */ + #ifdef CONFIG_SOC_IMX21 const struct imx_imx_fb_data imx21_imx_fb_data __initconst = imx_imx_fb_data_entry_single(MX21, SZ_4K); diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 7c871b8..97b19e7 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -89,7 +89,7 @@ #define MX1_GPIO_INT_PORTA 11 #define MX1_GPIO_INT_PORTB 12 #define MX1_GPIO_INT_PORTC 13 -#define MX1_LCDC_INT 14 +#define MX1_INT_LCDC 14 #define MX1_SIM_INT 15 #define MX1_SIM_DATA_INT 16 #define MX1_RTC_INT 17 -- cgit v0.10.2 From 5ae30b477e9fb7319e2976fbf3521c0fac2625f1 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 17 Feb 2011 14:43:48 +0100 Subject: ARM i.MX: Move gpio initialization to SoC specific files This saves us from soc level dispatching in generic files Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c index 378c61b..8613e44 100644 --- a/arch/arm/mach-imx/mm-imx1.c +++ b/arch/arm/mach-imx/mm-imx1.c @@ -23,6 +23,8 @@ #include #include +#include +#include static struct map_desc imx_io_desc[] __initdata = { imx_map_entry(MX1, IO, MT_DEVICE), @@ -39,10 +41,15 @@ void __init imx1_init_early(void) mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR)); } -int imx1_register_gpios(void); +static struct mxc_gpio_port imx1_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD), +}; void __init mx1_init_irq(void) { mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR)); - imx1_register_gpios(); + mxc_gpio_init(imx1_gpio_ports, ARRAY_SIZE(imx1_gpio_ports)); } diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c index b6152c6..6027e35 100644 --- a/arch/arm/mach-imx/mm-imx21.c +++ b/arch/arm/mach-imx/mm-imx21.c @@ -24,6 +24,8 @@ #include #include #include +#include +#include /* MX21 memory map definition */ static struct map_desc imx21_io_desc[] __initdata = { @@ -65,10 +67,17 @@ void __init imx21_init_early(void) mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR)); } -int imx21_register_gpios(void); +static struct mxc_gpio_port imx21_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO), + DEFINE_IMX_GPIO_PORT(MX21, 1, 2), + DEFINE_IMX_GPIO_PORT(MX21, 2, 3), + DEFINE_IMX_GPIO_PORT(MX21, 3, 4), + DEFINE_IMX_GPIO_PORT(MX21, 4, 5), + DEFINE_IMX_GPIO_PORT(MX21, 5, 6), +}; void __init mx21_init_irq(void) { mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR)); - imx21_register_gpios(); + mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports)); } diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c index 09dd8d4..02f7b5c 100644 --- a/arch/arm/mach-imx/mm-imx25.c +++ b/arch/arm/mach-imx/mm-imx25.c @@ -27,6 +27,8 @@ #include #include #include +#include +#include /* * This table defines static virtual address mappings for I/O regions. @@ -55,11 +57,16 @@ void __init imx25_init_early(void) mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR)); } -int imx25_register_gpios(void); +static struct mxc_gpio_port imx25_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1), + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2), + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3), + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4), +}; void __init mx25_init_irq(void) { mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR)); - imx25_register_gpios(); + mxc_gpio_init(imx25_gpio_ports, ARRAY_SIZE(imx25_gpio_ports)); } diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c index bcaa3b6..e172e3e 100644 --- a/arch/arm/mach-imx/mm-imx27.c +++ b/arch/arm/mach-imx/mm-imx27.c @@ -24,6 +24,8 @@ #include #include #include +#include +#include /* MX27 memory map definition */ static struct map_desc imx27_io_desc[] __initdata = { @@ -65,10 +67,17 @@ void __init imx27_init_early(void) mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR)); } -int imx27_register_gpios(void); +static struct mxc_gpio_port imx27_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO), + DEFINE_IMX_GPIO_PORT(MX27, 1, 2), + DEFINE_IMX_GPIO_PORT(MX27, 2, 3), + DEFINE_IMX_GPIO_PORT(MX27, 3, 4), + DEFINE_IMX_GPIO_PORT(MX27, 4, 5), + DEFINE_IMX_GPIO_PORT(MX27, 5, 6), +}; void __init mx27_init_irq(void) { mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR)); - imx27_register_gpios(); + mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); } diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c index eefd4cf..54d7174 100644 --- a/arch/arm/mach-mx3/mm.c +++ b/arch/arm/mach-mx3/mm.c @@ -27,6 +27,8 @@ #include #include #include +#include +#include #ifdef CONFIG_SOC_IMX31 static struct map_desc mx31_io_desc[] __initdata = { @@ -53,11 +55,16 @@ void __init imx31_init_early(void) mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); } -int imx31_register_gpios(void); +static struct mxc_gpio_port imx31_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1), + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2), + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3), +}; + void __init mx31_init_irq(void) { mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); - imx31_register_gpios(); + mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports)); } #endif /* ifdef CONFIG_SOC_IMX31 */ @@ -82,11 +89,16 @@ void __init imx35_init_early(void) mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); } -int imx35_register_gpios(void); +static struct mxc_gpio_port imx35_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1), + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2), + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3), +}; + void __init mx35_init_irq(void) { mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); - imx35_register_gpios(); + mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports)); } #endif /* ifdef CONFIG_SOC_IMX35 */ diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c index 69b3426..b9c363b 100644 --- a/arch/arm/mach-mx5/mm-mx50.c +++ b/arch/arm/mach-mx5/mm-mx50.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include /* * Define the MX50 memory map. @@ -54,10 +56,17 @@ void __init imx50_init_early(void) mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); } -int imx50_register_gpios(void); +static struct mxc_gpio_port imx50_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH), + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH), + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), +}; void __init mx50_init_irq(void) { tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR)); - imx50_register_gpios(); + mxc_gpio_init(imx50_gpio_ports, ARRAY_SIZE(imx50_gpio_ports)); } diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index e396df8..57d5985 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -350,113 +350,3 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) return 0; } - -#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \ - { \ - .chip.label = "gpio-" #_id, \ - .irq = _irq, \ - .irq_high = _irq_high, \ - .base = soc ## _IO_ADDRESS( \ - soc ## _GPIO ## _hwid ## _BASE_ADDR), \ - .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \ - } - -#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \ - DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0) -#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \ - DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0) - -#define DEFINE_REGISTER_FUNCTION(prefix) \ -int __init prefix ## _register_gpios(void) \ -{ \ - return mxc_gpio_init(prefix ## _gpio_ports, \ - ARRAY_SIZE(prefix ## _gpio_ports)); \ -} - -#if defined(CONFIG_SOC_IMX1) -static struct mxc_gpio_port imx1_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA), - DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB), - DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC), - DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD), -}; - -DEFINE_REGISTER_FUNCTION(imx1) - -#endif /* if defined(CONFIG_SOC_IMX1) */ - -#if defined(CONFIG_SOC_IMX21) -static struct mxc_gpio_port imx21_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO), - DEFINE_IMX_GPIO_PORT(MX21, 1, 2), - DEFINE_IMX_GPIO_PORT(MX21, 2, 3), - DEFINE_IMX_GPIO_PORT(MX21, 3, 4), - DEFINE_IMX_GPIO_PORT(MX21, 4, 5), - DEFINE_IMX_GPIO_PORT(MX21, 5, 6), -}; - -DEFINE_REGISTER_FUNCTION(imx21) - -#endif /* if defined(CONFIG_SOC_IMX21) */ - -#if defined(CONFIG_SOC_IMX25) -static struct mxc_gpio_port imx25_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1), - DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2), - DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3), - DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4), -}; - -DEFINE_REGISTER_FUNCTION(imx25) - -#endif /* if defined(CONFIG_SOC_IMX25) */ - -#if defined(CONFIG_SOC_IMX27) -static struct mxc_gpio_port imx27_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO), - DEFINE_IMX_GPIO_PORT(MX27, 1, 2), - DEFINE_IMX_GPIO_PORT(MX27, 2, 3), - DEFINE_IMX_GPIO_PORT(MX27, 3, 4), - DEFINE_IMX_GPIO_PORT(MX27, 4, 5), - DEFINE_IMX_GPIO_PORT(MX27, 5, 6), -}; - -DEFINE_REGISTER_FUNCTION(imx27) - -#endif /* if defined(CONFIG_SOC_IMX27) */ - -#if defined(CONFIG_SOC_IMX31) -static struct mxc_gpio_port imx31_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1), - DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2), - DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3), -}; - -DEFINE_REGISTER_FUNCTION(imx31) - -#endif /* if defined(CONFIG_SOC_IMX31) */ - -#if defined(CONFIG_SOC_IMX35) -static struct mxc_gpio_port imx35_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1), - DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2), - DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3), -}; - -DEFINE_REGISTER_FUNCTION(imx35) - -#endif /* if defined(CONFIG_SOC_IMX35) */ - -#if defined(CONFIG_SOC_IMX50) -static struct mxc_gpio_port imx50_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH), - DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH), - DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), - DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), - DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), - DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), -}; - -DEFINE_REGISTER_FUNCTION(imx50) - -#endif /* if defined(CONFIG_SOC_IMX50) */ diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index 0044e2f..a2747f1 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -46,6 +46,21 @@ struct mxc_gpio_port { spinlock_t lock; }; +#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \ + { \ + .chip.label = "gpio-" #_id, \ + .irq = _irq, \ + .irq_high = _irq_high, \ + .base = soc ## _IO_ADDRESS( \ + soc ## _GPIO ## _hwid ## _BASE_ADDR), \ + .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \ + } + +#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \ + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0) +#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \ + DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0) + int mxc_gpio_init(struct mxc_gpio_port*, int); #endif -- cgit v0.10.2 From ff255feba1c575311378a3d7a3867e46549c8aa6 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 17 Feb 2011 15:08:12 +0100 Subject: ARM i.MX: iomux v1 initialization away from initcall This saves us from soc level dispatching in generic files Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c index 8613e44..2e482ba 100644 --- a/arch/arm/mach-imx/mm-imx1.c +++ b/arch/arm/mach-imx/mm-imx1.c @@ -25,6 +25,7 @@ #include #include #include +#include static struct map_desc imx_io_desc[] __initdata = { imx_map_entry(MX1, IO, MT_DEVICE), @@ -39,6 +40,8 @@ void __init imx1_init_early(void) { mxc_set_cpu_type(MXC_CPU_MX1); mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR)); + imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR), + MX1_NUM_GPIO_PORT); } static struct mxc_gpio_port imx1_gpio_ports[] = { diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c index 6027e35..7a0c500 100644 --- a/arch/arm/mach-imx/mm-imx21.c +++ b/arch/arm/mach-imx/mm-imx21.c @@ -26,6 +26,7 @@ #include #include #include +#include /* MX21 memory map definition */ static struct map_desc imx21_io_desc[] __initdata = { @@ -65,6 +66,8 @@ void __init imx21_init_early(void) { mxc_set_cpu_type(MXC_CPU_MX21); mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR)); + imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR), + MX21_NUM_GPIO_PORT); } static struct mxc_gpio_port imx21_gpio_ports[] = { diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c index e172e3e..a6761a3 100644 --- a/arch/arm/mach-imx/mm-imx27.c +++ b/arch/arm/mach-imx/mm-imx27.c @@ -26,6 +26,7 @@ #include #include #include +#include /* MX27 memory map definition */ static struct map_desc imx27_io_desc[] __initdata = { @@ -65,6 +66,8 @@ void __init imx27_init_early(void) { mxc_set_cpu_type(MXC_CPU_MX27); mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR)); + imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR), + MX27_NUM_GPIO_PORT); } static struct mxc_gpio_port imx27_gpio_ports[] = { diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h index 884f575..c07d302 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v1.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h @@ -100,4 +100,6 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, const char *label); extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); +extern int __init imx_iomuxv1_init(void __iomem *base, int numports); + #endif /* __MACH_IOMUX_V1_H__ */ diff --git a/arch/arm/plat-mxc/iomux-v1.c b/arch/arm/plat-mxc/iomux-v1.c index 960a02c..3238c10 100644 --- a/arch/arm/plat-mxc/iomux-v1.c +++ b/arch/arm/plat-mxc/iomux-v1.c @@ -211,28 +211,10 @@ void mxc_gpio_release_multiple_pins(const int *pin_list, int count) } EXPORT_SYMBOL(mxc_gpio_release_multiple_pins); -static int imx_iomuxv1_init(void) +int __init imx_iomuxv1_init(void __iomem *base, int numports) { -#ifdef CONFIG_ARCH_MX1 - if (cpu_is_mx1()) { - imx_iomuxv1_baseaddr = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR); - imx_iomuxv1_numports = MX1_NUM_GPIO_PORT; - } else -#endif -#ifdef CONFIG_MACH_MX21 - if (cpu_is_mx21()) { - imx_iomuxv1_baseaddr = MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR); - imx_iomuxv1_numports = MX21_NUM_GPIO_PORT; - } else -#endif -#ifdef CONFIG_MACH_MX27 - if (cpu_is_mx27()) { - imx_iomuxv1_baseaddr = MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR); - imx_iomuxv1_numports = MX27_NUM_GPIO_PORT; - } else -#endif - return -ENODEV; + imx_iomuxv1_baseaddr = base; + imx_iomuxv1_numports = numports; return 0; } -pure_initcall(imx_iomuxv1_init); -- cgit v0.10.2 From 94573e6623cf9159f036adc670a3d4b29e6d86fe Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 2 Mar 2011 10:10:14 +0100 Subject: ARM i.MX31 lilly: remove incomplete otg support The platform data for the otg port is present but never used, so remove it. Signed-off-by: Sascha Hauer Cc: Daniel Mack diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c index be79a0d..e2f9de1 100644 --- a/arch/arm/mach-mx3/mach-mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c @@ -116,52 +116,6 @@ static struct platform_device physmap_flash_device = { #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) -static int usbotg_init(struct platform_device *pdev) -{ - unsigned int pins[] = { - MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, - MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, - MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, - MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, - MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, - MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, - MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, - MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, - MX31_PIN_USBOTG_CLK__USBOTG_CLK, - MX31_PIN_USBOTG_DIR__USBOTG_DIR, - MX31_PIN_USBOTG_NXT__USBOTG_NXT, - MX31_PIN_USBOTG_STP__USBOTG_STP, - }; - - mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB OTG"); - - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); - - mxc_iomux_set_gpr(MUX_PGP_USB_4WIRE, true); - mxc_iomux_set_gpr(MUX_PGP_USB_COMMON, true); - - /* chip select */ - mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE2, IOMUX_CONFIG_GPIO), - "USBOTG_CS"); - gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), "USBH1 CS"); - gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), 0); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - static int usbh1_init(struct platform_device *pdev) { int pins[] = { @@ -231,11 +185,6 @@ static int usbh2_init(struct platform_device *pdev) return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); } -static struct mxc_usbh_platform_data usbotg_pdata = { - .init = usbotg_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { .init = usbh1_init, .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, @@ -248,8 +197,6 @@ static struct mxc_usbh_platform_data usbh2_pdata __initdata = { static void lilly1131_usb_init(void) { - usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); -- cgit v0.10.2 From 48f6b0999673cce33e4a54d89c78460cc28e5156 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 2 Mar 2011 09:27:42 +0100 Subject: ARM i.MX: introduce imx_otg_ulpi_create to create ULPI transceivers The boards are currently using otg_ulpi_create and mxc_ulpi_access_ops, both are only present if CONFIG_USB_ULPI is set. To remove the need of ifdefs in the board code introduce a imx_otg_ulpi_create functions which expands to a static inline function if compiled without ulpi. Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index 6b724c2..759299b 100644 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c @@ -209,7 +209,6 @@ static struct platform_device serial_device = { }; #endif -#if defined(CONFIG_USB_ULPI) static int eukrea_cpuimx27_otg_init(struct platform_device *pdev) { return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); @@ -229,7 +228,6 @@ static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = eukrea_cpuimx27_usbh2_init, .portsc = MXC_EHCI_MODE_ULPI, }; -#endif static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, @@ -283,21 +281,19 @@ static void __init eukrea_cpuimx27_init(void) platform_device_register(&serial_device); #endif -#if defined(CONFIG_USB_ULPI) if (otg_mode_host) { - otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - - imx27_add_mxc_ehci_otg(&otg_pdata); + otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | + ULPI_OTG_DRVVBUS_EXT); + if (otg_pdata.otg) + imx27_add_mxc_ehci_otg(&otg_pdata); + } else { + imx27_add_fsl_usb2_udc(&otg_device_pdata); } - usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - - imx27_add_mxc_ehci_hs(2, &usbh2_pdata); -#endif - if (!otg_mode_host) - imx27_add_fsl_usb2_udc(&otg_device_pdata); + usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | + ULPI_OTG_DRVVBUS_EXT); + if (usbh2_pdata.otg) + imx27_add_mxc_ehci_hs(2, &usbh2_pdata); #ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD eukrea_mbimx27_baseboard_init(); diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index f4f2725..614b3c0 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c @@ -162,7 +162,6 @@ static int otg_phy_init(void) return 0; } -#if defined(CONFIG_USB_ULPI) static int mx27_3ds_otg_init(struct platform_device *pdev) { return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); @@ -172,7 +171,6 @@ static struct mxc_usbh_platform_data otg_pdata __initdata = { .init = mx27_3ds_otg_init, .portsc = MXC_EHCI_MODE_ULPI, }; -#endif static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, @@ -275,14 +273,15 @@ static void __init mx27pdk_init(void) imx27_add_mxc_mmc(0, &sdhc1_pdata); imx27_add_imx2_wdt(NULL); otg_phy_init(); -#if defined(CONFIG_USB_ULPI) + if (otg_mode_host) { - otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); + otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | + ULPI_OTG_DRVVBUS_EXT); - imx27_add_mxc_ehci_otg(&otg_pdata); + if (otg_pdata.otg) + imx27_add_mxc_ehci_otg(&otg_pdata); } -#endif + if (!otg_mode_host) imx27_add_fsl_usb2_udc(&otg_device_pdata); diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index f754bab..63e1825 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -267,7 +267,6 @@ static const struct imxmmc_platform_data sdhc_pdata __initconst = { .exit = pca100_sdhc2_exit, }; -#if defined(CONFIG_USB_ULPI) static int otg_phy_init(struct platform_device *pdev) { gpio_set_value(OTG_PHY_CS_GPIO, 0); @@ -295,7 +294,6 @@ static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = usbh2_phy_init, .portsc = MXC_EHCI_MODE_ULPI, }; -#endif static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, @@ -402,23 +400,22 @@ static void __init pca100_init(void) gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs"); gpio_direction_output(USBH2_PHY_CS_GPIO, 1); -#if defined(CONFIG_USB_ULPI) if (otg_mode_host) { - otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); + otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | + ULPI_OTG_DRVVBUS_EXT); - imx27_add_mxc_ehci_otg(&otg_pdata); + if (otg_pdata.otg) + imx27_add_mxc_ehci_otg(&otg_pdata); + } else { + gpio_set_value(OTG_PHY_CS_GPIO, 0); + imx27_add_fsl_usb2_udc(&otg_device_pdata); } usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - imx27_add_mxc_ehci_hs(2, &usbh2_pdata); -#endif - if (!otg_mode_host) { - gpio_set_value(OTG_PHY_CS_GPIO, 0); - imx27_add_fsl_usb2_udc(&otg_device_pdata); - } + if (usbh2_pdata.otg) + imx27_add_mxc_ehci_hs(2, &usbh2_pdata); imx27_add_imx_fb(&pca100_fb_data); diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c index 34e619e..226829b 100644 --- a/arch/arm/mach-mx3/mach-armadillo5x0.c +++ b/arch/arm/mach-mx3/mach-armadillo5x0.c @@ -133,7 +133,6 @@ static int armadillo5x0_pins[] = { }; /* USB */ -#if defined(CONFIG_USB_ULPI) #define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4) #define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6) @@ -256,7 +255,6 @@ static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = usbh2_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, }; -#endif /* CONFIG_USB_ULPI */ /* RTC over I2C*/ #define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4) @@ -549,15 +547,15 @@ static void __init armadillo5x0_init(void) i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1); /* USB */ -#if defined(CONFIG_USB_ULPI) - usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - - imx31_add_mxc_ehci_otg(&usbotg_pdata); - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); -#endif + + usbotg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | + ULPI_OTG_DRVVBUS_EXT); + if (usbotg_pdata.otg) + imx31_add_mxc_ehci_otg(&usbotg_pdata); + usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | + ULPI_OTG_DRVVBUS_EXT); + if (usbh2_pdata.otg) + imx31_add_mxc_ehci_hs(2, &usbh2_pdata); } static void __init armadillo5x0_timer_init(void) diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 35fdb2a..f1dbb9d 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -244,7 +244,6 @@ usbotg_free_reset: return err; } -#if defined(CONFIG_USB_ULPI) static int mx31_3ds_otg_init(struct platform_device *pdev) { return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); @@ -300,7 +299,6 @@ static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = mx31_3ds_host2_init, .portsc = MXC_EHCI_MODE_ULPI, }; -#endif static const struct fsl_usb2_platform_data usbotg_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, @@ -345,17 +343,17 @@ static void __init mx31_3ds_init(void) imx31_add_imx_keypad(&mx31_3ds_keymap_data); mx31_3ds_usbotg_init(); -#if defined(CONFIG_USB_ULPI) if (otg_mode_host) { - otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - - imx31_add_mxc_ehci_otg(&otg_pdata); + otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | + ULPI_OTG_DRVVBUS_EXT); + if (otg_pdata.otg) + imx31_add_mxc_ehci_otg(&otg_pdata); } - usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); -#endif + usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | + ULPI_OTG_DRVVBUS_EXT); + if (usbh2_pdata.otg) + imx31_add_mxc_ehci_hs(2, &usbh2_pdata); + if (!otg_mode_host) imx31_add_fsl_usb2_udc(&usbotg_pdata); diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c index e2f9de1..ed95745 100644 --- a/arch/arm/mach-mx3/mach-mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c @@ -111,8 +111,6 @@ static struct platform_device physmap_flash_device = { /* USB */ -#if defined(CONFIG_USB_ULPI) - #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) @@ -197,16 +195,13 @@ static struct mxc_usbh_platform_data usbh2_pdata __initdata = { static void lilly1131_usb_init(void) { - usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - imx31_add_mxc_ehci_hs(1, &usbh1_pdata); - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); -} -#else -static inline void lilly1131_usb_init(void) {} -#endif /* CONFIG_USB_ULPI */ + usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | + ULPI_OTG_DRVVBUS_EXT); + if (usbh2_pdata.otg) + imx31_add_mxc_ehci_hs(2, &usbh2_pdata); +} /* SPI */ diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c index 81021bf..24a21a3 100644 --- a/arch/arm/mach-mx3/mach-mx31lite.c +++ b/arch/arm/mach-mx3/mach-mx31lite.c @@ -130,7 +130,6 @@ static struct spi_board_info mc13783_spi_dev __initdata = { * USB */ -#if defined(CONFIG_USB_ULPI) #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) @@ -177,7 +176,6 @@ static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = usbh2_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, }; -#endif /* * NOR flash @@ -254,13 +252,11 @@ static void __init mx31lite_init(void) imx31_add_spi_imx1(&spi1_pdata); spi_register_board_info(&mc13783_spi_dev, 1); -#if defined(CONFIG_USB_ULPI) /* USB */ - usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); -#endif + usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | + ULPI_OTG_DRVVBUS_EXT); + if (usbh2_pdata.otg) + imx31_add_mxc_ehci_hs(2, &usbh2_pdata); /* SMSC9117 IRQ pin */ ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq"); diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index 845d0b6..6f3692b 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -400,7 +400,6 @@ static void usb_xcvr_reset(void) mdelay(1); } -#if defined(CONFIG_USB_ULPI) static int moboard_usbh2_init_hw(struct platform_device *pdev) { return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); @@ -415,8 +414,10 @@ static int __init moboard_usbh2_init(void) { struct platform_device *pdev; - usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); + usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | + ULPI_OTG_DRVVBUS_EXT); + if (!usbh2_pdata.otg) + return -ENODEV; pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata); if (IS_ERR(pdev)) @@ -424,10 +425,6 @@ static int __init moboard_usbh2_init(void) return 0; } -#else -static inline int moboard_usbh2_init(void) { return 0; } -#endif - static struct gpio_led mx31moboard_leds[] = { { diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c index 783d31b..f07d3bd 100644 --- a/arch/arm/mach-mx3/mach-pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c @@ -533,7 +533,6 @@ static struct platform_device pcm970_sja1000 = { .num_resources = ARRAY_SIZE(pcm970_sja1000_resources), }; -#if defined(CONFIG_USB_ULPI) static int pcm037_otg_init(struct platform_device *pdev) { return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); @@ -553,7 +552,6 @@ static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = pcm037_usbh2_init, .portsc = MXC_EHCI_MODE_ULPI, }; -#endif static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, @@ -656,19 +654,18 @@ static void __init pcm037_init(void) platform_device_register(&pcm970_sja1000); -#if defined(CONFIG_USB_ULPI) if (otg_mode_host) { - otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - - imx31_add_mxc_ehci_otg(&otg_pdata); + otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | + ULPI_OTG_DRVVBUS_EXT); + if (otg_pdata.otg) + imx31_add_mxc_ehci_otg(&otg_pdata); } - usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); + usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | + ULPI_OTG_DRVVBUS_EXT); + if (usbh2_pdata.otg) + imx31_add_mxc_ehci_hs(2, &usbh2_pdata); - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); -#endif if (!otg_mode_host) imx31_add_fsl_usb2_udc(&otg_device_pdata); diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index 262af17..b3ecfb2 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -305,7 +305,6 @@ pcm037_nand_board_info __initconst = { .hw_ecc = 1, }; -#if defined(CONFIG_USB_ULPI) static int pcm043_otg_init(struct platform_device *pdev) { return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); @@ -315,7 +314,6 @@ static struct mxc_usbh_platform_data otg_pdata __initdata = { .init = pcm043_otg_init, .portsc = MXC_EHCI_MODE_UTMI, }; -#endif static int pcm043_usbh1_init(struct platform_device *pdev) { @@ -385,14 +383,12 @@ static void __init pcm043_init(void) mxc_register_device(&mx3_ipu, &mx3_ipu_data); mxc_register_device(&mx3_fb, &mx3fb_pdata); -#if defined(CONFIG_USB_ULPI) if (otg_mode_host) { - otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - - imx35_add_mxc_ehci_otg(&otg_pdata); + otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | + ULPI_OTG_DRVVBUS_EXT); + if (otg_pdata.otg) + imx35_add_mxc_ehci_otg(&otg_pdata); } -#endif imx35_add_mxc_ehci_hs(&usbh1_pdata); if (!otg_mode_host) diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c index 87d556f..35f806e 100644 --- a/arch/arm/mach-mx3/mx31moboard-smartbot.c +++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c @@ -137,8 +137,10 @@ static int __init smartbot_otg_host_init(void) { struct platform_device *pdev; - otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); + otg_host_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | + ULPI_OTG_DRVVBUS_EXT); + if (!otg_host_pdata.otg) + return -ENODEV; pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata); if (IS_ERR(pdev)) diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c index 18e29b9..db04ce84 100644 --- a/arch/arm/mach-mx5/board-mx51_efikasb.c +++ b/arch/arm/mach-mx5/board-mx51_efikasb.c @@ -129,10 +129,10 @@ static struct mxc_usbh_platform_data usbh2_config = { static void __init mx51_efikasb_usb(void) { - usbh2_config.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT | - ULPI_OTG_EXTVBUSIND); - mxc_register_device(&mxc_usbh2_device, &usbh2_config); + usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | + ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); + if (usbh2_config.otg) + mxc_register_device(&mxc_usbh2_device, &usbh2_config); } static struct gpio_led mx51_efikasb_leds[] = { diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c index 74991c9..51a67fc 100644 --- a/arch/arm/mach-mx5/mx51_efika.c +++ b/arch/arm/mach-mx5/mx51_efika.c @@ -218,12 +218,12 @@ static void __init mx51_efika_usb(void) msleep(1); gpio_set_value(EFIKA_USB_PHY_RESET, 1); - usbh1_config.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT | - ULPI_OTG_EXTVBUSIND); + usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | + ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); - mxc_register_device(&mxc_usbh1_device, &usbh1_config); + if (usbh1_config.otg) + mxc_register_device(&mxc_usbh1_device, &usbh1_config); } static struct mtd_partition mx51_efika_spi_nor_partitions[] = { diff --git a/arch/arm/plat-mxc/include/mach/ulpi.h b/arch/arm/plat-mxc/include/mach/ulpi.h index 96b6ab4..f9161c9 100644 --- a/arch/arm/plat-mxc/include/mach/ulpi.h +++ b/arch/arm/plat-mxc/include/mach/ulpi.h @@ -1,6 +1,15 @@ #ifndef __MACH_ULPI_H #define __MACH_ULPI_H +#ifdef CONFIG_USB_ULPI +struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags); +#else +static inline struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags) +{ + return NULL; +} +#endif + extern struct otg_io_access_ops mxc_ulpi_access_ops; #endif /* __MACH_ULPI_H */ diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c index 582c6df..477e45b 100644 --- a/arch/arm/plat-mxc/ulpi.c +++ b/arch/arm/plat-mxc/ulpi.c @@ -22,6 +22,7 @@ #include #include #include +#include #include @@ -111,3 +112,7 @@ struct otg_io_access_ops mxc_ulpi_access_ops = { }; EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops); +struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags) +{ + return otg_ulpi_create(&mxc_ulpi_access_ops, flags); +} -- cgit v0.10.2 From 76851671287209759f63c090ffaffca56ba00358 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 3 Mar 2011 16:40:02 +0800 Subject: ARM: imx5x: clean up ARCH_MX5X MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move to SOC_SOC_IMX5X. Leave only places which prevent multi-soc using ARCH_MX5X. Signed-off-by: Richard Zhao Acked-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 03ec6e9..83ee088 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -1,5 +1,6 @@ if ARCH_MX5 -# ARCH_MX51 and ARCH_MX50 are left for compatibility +# ARCH_MX50/51/53 are left to mark places where prevent multi-soc in single +# image. So for most time, SOC_IMX50/51/53 should be used. config ARCH_MX50 bool diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c index 33530d2..be7df13 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-dma.c +++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c @@ -194,7 +194,7 @@ static int __init imxXX_add_imx_dma(void) } else #endif -#if defined(CONFIG_ARCH_MX51) +#if defined(CONFIG_SOC_IMX51) if (cpu_is_mx51()) { imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1; ret = imx_add_imx_sdma(&imx51_imx_sdma_data); diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index ba65c92..a3d930d3 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -23,17 +23,17 @@ #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS /* these are ordered by size to support multi-SoC kernels */ -#if defined CONFIG_ARCH_MX53 +#if defined CONFIG_SOC_IMX53 #define MXC_GPIO_IRQS (32 * 7) #elif defined CONFIG_ARCH_MX2 #define MXC_GPIO_IRQS (32 * 6) -#elif defined CONFIG_ARCH_MX50 +#elif defined CONFIG_SOC_IMX50 #define MXC_GPIO_IRQS (32 * 6) #elif defined CONFIG_ARCH_MX1 #define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MX25 #define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_ARCH_MX51 +#elif defined CONFIG_SOC_IMX51 #define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MXC91231 #define MXC_GPIO_IRQS (32 * 4) diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 04c7a26..3781f2f 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -127,7 +127,7 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx35() (0) #endif -#ifdef CONFIG_ARCH_MX50 +#ifdef CONFIG_SOC_IMX50 # ifdef mxc_cpu_type # undef mxc_cpu_type # define mxc_cpu_type __mxc_cpu_type @@ -139,7 +139,7 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx50() (0) #endif -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 # ifdef mxc_cpu_type # undef mxc_cpu_type # define mxc_cpu_type __mxc_cpu_type @@ -151,7 +151,7 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx51() (0) #endif -#ifdef CONFIG_ARCH_MX53 +#ifdef CONFIG_SOC_IMX53 # ifdef mxc_cpu_type # undef mxc_cpu_type # define mxc_cpu_type __mxc_cpu_type diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index c895922..450afc5 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -476,7 +476,7 @@ config MTD_NAND_MPC5121_NFC config MTD_NAND_MXC tristate "MXC NAND support" - depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3 || ARCH_MX51 + depends on IMX_HAVE_PLATFORM_MXC_NAND help This enables the driver for the NAND flash controller on the MXC processors. diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index bb233a9..9f9d3f7 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -164,10 +164,10 @@ config SPI_IMX_VER_0_4 def_bool y if ARCH_MX31 config SPI_IMX_VER_0_7 - def_bool y if ARCH_MX25 || ARCH_MX35 || ARCH_MX51 || ARCH_MX53 + def_bool y if ARCH_MX25 || ARCH_MX35 || SOC_IMX51 || SOC_IMX53 config SPI_IMX_VER_2_3 - def_bool y if ARCH_MX51 || ARCH_MX53 + def_bool y if SOC_IMX51 || SOC_IMX53 config SPI_IMX tristate "Freescale i.MX SPI controllers" -- cgit v0.10.2 From c23eb89ef71cda127cfcfee84292cb2fb5747d4d Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 3 Mar 2011 16:40:03 +0800 Subject: ARM: imx3x: clean up ARCH_MX3X Move to SOC_SOC_IMX3X. Leave ARCH_MX31/35 definitions there, in case some place prevent multi-soc single image. Signed-off-by: Richard Zhao Acked-by: Marc Kleine-Budde Signed-off-by: Sascha Hauer diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 9d30c6f..0a4aa17 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -811,7 +811,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH config CACHE_L2X0 bool "Enable the L2x0 outer cache controller" depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ - REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \ + REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \ ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \ ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE default y diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c index be7df13..3538b85e 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-dma.c +++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c @@ -94,7 +94,7 @@ static struct sdma_script_start_addrs addr_imx25_to1 = { }; #endif -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 static struct sdma_script_start_addrs addr_imx31_to1 = { .per_2_per_addr = 1677, }; @@ -106,7 +106,7 @@ static struct sdma_script_start_addrs addr_imx31_to2 = { }; #endif -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 static struct sdma_script_start_addrs addr_imx35_to1 = { .ap_2_ap_addr = 642, .uart_2_mcu_addr = 817, diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 3781f2f..7e07263 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -103,7 +103,7 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx27() (0) #endif -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 # ifdef mxc_cpu_type # undef mxc_cpu_type # define mxc_cpu_type __mxc_cpu_type @@ -115,7 +115,7 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx31() (0) #endif -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 # ifdef mxc_cpu_type # undef mxc_cpu_type # define mxc_cpu_type __mxc_cpu_type diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 0382332..9928115 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1944,7 +1944,7 @@ config 68360_ENET config FEC bool "FEC ethernet controller (of ColdFire and some i.MX CPUs)" depends on M523x || M527x || M5272 || M528x || M520x || M532x || \ - MACH_MX27 || ARCH_MX35 || ARCH_MX25 || ARCH_MX5 || SOC_IMX28 + IMX_HAVE_PLATFORM_FEC || SOC_IMX28 select PHYLIB help Say Y here if you want to use the built-in 10/100 Fast ethernet diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 9f9d3f7..bd9dad5 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -161,10 +161,10 @@ config SPI_IMX_VER_0_0 def_bool y if SOC_IMX21 || SOC_IMX27 config SPI_IMX_VER_0_4 - def_bool y if ARCH_MX31 + def_bool y if SOC_MX31 config SPI_IMX_VER_0_7 - def_bool y if ARCH_MX25 || ARCH_MX35 || SOC_IMX51 || SOC_IMX53 + def_bool y if ARCH_MX25 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53 config SPI_IMX_VER_2_3 def_bool y if SOC_IMX51 || SOC_IMX53 diff --git a/drivers/usb/gadget/fsl_mxc_udc.c b/drivers/usb/gadget/fsl_mxc_udc.c index 77b1eb5..834fe94 100644 --- a/drivers/usb/gadget/fsl_mxc_udc.c +++ b/drivers/usb/gadget/fsl_mxc_udc.c @@ -88,7 +88,7 @@ eenahb: void fsl_udc_clk_finalize(struct platform_device *pdev) { struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; -#if defined(CONFIG_ARCH_MX35) +#if defined(CONFIG_SOC_IMX35) unsigned int v; /* workaround ENGcm09152 for i.MX35 */ -- cgit v0.10.2 From 65e7a3222fd9f47eafa908ef3e350ce4f953914e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 3 Mar 2011 22:36:57 +0100 Subject: ARM: mxc91231: select MXC_AVIC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes: arch/arm/kernel/built-in.o: In function `__irq_svc': io.c:(.text+0x2e0): undefined reference to `avic_base' arch/arm/kernel/built-in.o: In function `__irq_usr': io.c:(.text+0x4c8): undefined reference to `avic_base' arch/arm/mach-mxc91231/built-in.o: In function `mxc91231_init_irq': magx-zn5.c:(.init.text+0x18): undefined reference to `mxc_init_irq' and was broken by c7259df (ARM i.MX irq: Compile avic irq code only on SoCs that need it) Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 389f217..b0cb425 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -33,6 +33,7 @@ config ARCH_MX3 config ARCH_MXC91231 bool "MXC91231-based" select CPU_V6 + select MXC_AVIC help This enables support for systems based on the Freescale MXC91231 family -- cgit v0.10.2 From db63a493838473e3ae87e0db06bb6ddd817f20a2 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sun, 6 Mar 2011 00:40:19 +0800 Subject: ARM: mxs: add helper macro for pad control This patch is to add pad control helper macro to make the code easy to read. The need is being seen when adding pad definitions for LCDIF which gets ~30 pads to define. Signed-off-by: Shawn Guo Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h index fe558e3..7abdf58 100644 --- a/arch/arm/mach-mxs/include/mach/iomux.h +++ b/arch/arm/mach-mxs/include/mach/iomux.h @@ -91,6 +91,9 @@ typedef u32 iomux_cfg_t; #define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ MXS_PAD_PULL_VALID_MASK) +/* generic pad control used in most cases */ +#define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL) + #define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c index 0737ce2..d724054 100644 --- a/arch/arm/mach-mxs/mach-mx23evk.c +++ b/arch/arm/mach-mxs/mach-mx23evk.c @@ -28,18 +28,14 @@ static const iomux_cfg_t mx23evk_pads[] __initconst = { /* duart */ - MX23_PAD_PWM0__DUART_RX | MXS_PAD_4MA, - MX23_PAD_PWM1__DUART_TX | MXS_PAD_4MA, + MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, + MX23_PAD_PWM1__DUART_TX | MXS_PAD_CTRL, /* auart */ - MX23_PAD_AUART1_RX__AUART1_RX | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX23_PAD_AUART1_TX__AUART1_TX | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX23_PAD_AUART1_CTS__AUART1_CTS | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX23_PAD_AUART1_RTS__AUART1_RTS | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX23_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL, + MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL, + MX23_PAD_AUART1_CTS__AUART1_CTS | MXS_PAD_CTRL, + MX23_PAD_AUART1_RTS__AUART1_RTS | MXS_PAD_CTRL, }; static void __init mx23evk_init(void) diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c index 1f0b708..987e3d5 100644 --- a/arch/arm/mach-mxs/mach-mx28evk.c +++ b/arch/arm/mach-mxs/mach-mx28evk.c @@ -33,68 +33,42 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = { /* duart */ - MX28_PAD_PWM0__DUART_RX | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_PWM1__DUART_TX | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, + MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL, /* auart0 */ - MX28_PAD_AUART0_RX__AUART0_RX | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_AUART0_TX__AUART0_TX | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_AUART0_CTS__AUART0_CTS | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_AUART0_RTS__AUART0_RTS | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL, + MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL, + MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL, + MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL, /* auart3 */ - MX28_PAD_AUART3_RX__AUART3_RX | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_AUART3_TX__AUART3_TX | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_AUART3_CTS__AUART3_CTS | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_AUART3_RTS__AUART3_RTS | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL, + MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL, + MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL, + MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL, +#define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP) /* fec0 */ - MX28_PAD_ENET0_MDC__ENET0_MDC | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_ENET0_MDIO__ENET0_MDIO | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_ENET_CLK__CLKCTRL_ENET | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC, + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC, + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC, + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC, /* fec1 */ - MX28_PAD_ENET0_CRS__ENET1_RX_EN | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_ENET0_RXD2__ENET1_RXD0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_ENET0_RXD3__ENET1_RXD1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_ENET0_COL__ENET1_TX_EN | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_ENET0_TXD2__ENET1_TXD0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_ENET0_TXD3__ENET1_TXD1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC, + MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC, + MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC, + MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC, + MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC, + MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC, /* phy power line */ - MX28_PAD_SSP1_DATA3__GPIO_2_15 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_SSP1_DATA3__GPIO_2_15 | MXS_PAD_CTRL, /* phy reset line */ - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MXS_PAD_CTRL, }; /* fec */ -- cgit v0.10.2 From 122eb103924316c1229f1b8aeea7492893d910c9 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sun, 6 Mar 2011 00:40:21 +0800 Subject: ARM: mxs: fix typo "GPO" in iomux-mx23.h Signed-off-by: Shawn Guo Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h index 94e5dd8..b0190a4 100644 --- a/arch/arm/mach-mxs/include/mach/iomux-mx23.h +++ b/arch/arm/mach-mxs/include/mach/iomux-mx23.h @@ -254,102 +254,102 @@ #define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2) /* MUXSEL_GPIO */ -#define MX23_PAD_GPMI_D00__GPO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D01__GPO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D02__GPO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D03__GPO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D04__GPO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D05__GPO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D06__GPO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D07__GPO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D08__GPO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D09__GPO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D10__GPO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D11__GPO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D12__GPO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D13__GPO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D14__GPO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D15__GPO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CLE__GPO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_ALE__GPO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE2N__GPO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY0__GPO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY1__GPO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY2__GPO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY3__GPO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_WPN__GPO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_WRN__GPO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDN__GPO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_CTS__GPO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_RTS__GPO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_RX__GPO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_TX__GPO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_I2C_SCL__GPO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO) -#define MX23_PAD_I2C_SDA__GPO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D08__GPIO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D09__GPIO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D10__GPIO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D11__GPIO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D12__GPIO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D13__GPIO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D14__GPIO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D15__GPIO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_CLE__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_ALE__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_RDY0__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_RDY1__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_RDY2__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_RDY3__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_WPN__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_WRN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_RDN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) +#define MX23_PAD_AUART1_CTS__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) +#define MX23_PAD_AUART1_RTS__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) +#define MX23_PAD_AUART1_RX__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) +#define MX23_PAD_AUART1_TX__GPIO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO) +#define MX23_PAD_I2C_SCL__GPIO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO) +#define MX23_PAD_I2C_SDA__GPIO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D00__GPO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D01__GPO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D02__GPO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D03__GPO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D04__GPO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D05__GPO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D06__GPO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D07__GPO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D08__GPO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D09__GPO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D10__GPO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D11__GPO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D12__GPO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D13__GPO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D14__GPO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D15__GPO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D16__GPO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D17__GPO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_RESET__GPO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_RS__GPO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_WR__GPO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_CS__GPO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_DOTCK__GPO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_ENABLE__GPO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_HSYNC__GPO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_VSYNC__GPO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM0__GPO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM1__GPO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM2__GPO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM3__GPO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM4__GPO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_RESET__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_RS__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_WR__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_CS__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_DOTCK__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_ENABLE__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_HSYNC__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_VSYNC__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) +#define MX23_PAD_PWM0__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) +#define MX23_PAD_PWM1__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) +#define MX23_PAD_PWM2__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) +#define MX23_PAD_PWM3__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) +#define MX23_PAD_PWM4__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_CMD__GPO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DETECT__GPO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA0__GPO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA1__GPO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA2__GPO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA3__GPO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_SCK__GPO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_ROTARYA__GPO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_ROTARYB__GPO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A00__GPO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A01__GPO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A02__GPO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A03__GPO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A04__GPO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A05__GPO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A06__GPO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A07__GPO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A08__GPO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A09__GPO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A10__GPO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A11__GPO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A12__GPO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_BA0__GPO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_BA1__GPO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CASN__GPO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CE0N__GPO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CE1N__GPO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE1N__GPO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE0N__GPO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CKE__GPO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_RASN__GPO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_WEN__GPO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_CMD__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_DETECT__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_DATA0__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_DATA1__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_DATA2__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_DATA3__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_SCK__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) +#define MX23_PAD_ROTARYA__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) +#define MX23_PAD_ROTARYB__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A00__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A01__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A02__GPIO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A03__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A04__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A05__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A06__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A07__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A08__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A09__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A10__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A11__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A12__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_BA0__GPIO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_BA1__GPIO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_CASN__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_CE0N__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_CE1N__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_CE1N__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_CE0N__GPIO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_CKE__GPIO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_RASN__GPIO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_WEN__GPIO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO) #endif /* __MACH_IOMUX_MX23_H__ */ -- cgit v0.10.2 From b73d77b2b75091b09d31f5c47924c99d4f19930a Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sun, 6 Mar 2011 00:40:22 +0800 Subject: ARM: mxs/mx23evk: add framebuffer device Signed-off-by: Shawn Guo Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 4f0b673..989c08c 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -22,6 +22,7 @@ config MACH_MX23EVK select SOC_IMX23 select MXS_HAVE_AMBA_DUART select MXS_HAVE_PLATFORM_AUART + select MXS_HAVE_PLATFORM_MXSFB default y help Include support for MX23EVK platform. This includes specific diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c index d724054..a66994f 100644 --- a/arch/arm/mach-mxs/mach-mx23evk.c +++ b/arch/arm/mach-mxs/mach-mx23evk.c @@ -26,6 +26,9 @@ #include "devices-mx23.h" +#define MX23EVK_LCD_ENABLE MXS_GPIO_NR(1, 18) +#define MX23EVK_BL_ENABLE MXS_GPIO_NR(1, 28) + static const iomux_cfg_t mx23evk_pads[] __initconst = { /* duart */ MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, @@ -36,14 +39,90 @@ static const iomux_cfg_t mx23evk_pads[] __initconst = { MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL, MX23_PAD_AUART1_CTS__AUART1_CTS | MXS_PAD_CTRL, MX23_PAD_AUART1_RTS__AUART1_RTS | MXS_PAD_CTRL, + + /* mxsfb (lcdif) */ + MX23_PAD_LCD_D00__LCD_D00 | MXS_PAD_CTRL, + MX23_PAD_LCD_D01__LCD_D01 | MXS_PAD_CTRL, + MX23_PAD_LCD_D02__LCD_D02 | MXS_PAD_CTRL, + MX23_PAD_LCD_D03__LCD_D03 | MXS_PAD_CTRL, + MX23_PAD_LCD_D04__LCD_D04 | MXS_PAD_CTRL, + MX23_PAD_LCD_D05__LCD_D05 | MXS_PAD_CTRL, + MX23_PAD_LCD_D06__LCD_D06 | MXS_PAD_CTRL, + MX23_PAD_LCD_D07__LCD_D07 | MXS_PAD_CTRL, + MX23_PAD_LCD_D08__LCD_D08 | MXS_PAD_CTRL, + MX23_PAD_LCD_D09__LCD_D09 | MXS_PAD_CTRL, + MX23_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL, + MX23_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL, + MX23_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL, + MX23_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL, + MX23_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL, + MX23_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL, + MX23_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL, + MX23_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL, + MX23_PAD_GPMI_D08__LCD_D18 | MXS_PAD_CTRL, + MX23_PAD_GPMI_D09__LCD_D19 | MXS_PAD_CTRL, + MX23_PAD_GPMI_D10__LCD_D20 | MXS_PAD_CTRL, + MX23_PAD_GPMI_D11__LCD_D21 | MXS_PAD_CTRL, + MX23_PAD_GPMI_D12__LCD_D22 | MXS_PAD_CTRL, + MX23_PAD_GPMI_D13__LCD_D23 | MXS_PAD_CTRL, + MX23_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL, + MX23_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL, + MX23_PAD_LCD_DOTCK__LCD_DOTCK | MXS_PAD_CTRL, + MX23_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL, + /* LCD panel enable */ + MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL, + /* backlight control */ + MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL, +}; + +/* mxsfb (lcdif) */ +static struct fb_videomode mx23evk_video_modes[] = { + { + .name = "Samsung-LMS430HF02", + .refresh = 60, + .xres = 480, + .yres = 272, + .pixclock = 108096, /* picosecond (9.2 MHz) */ + .left_margin = 15, + .right_margin = 8, + .upper_margin = 12, + .lower_margin = 4, + .hsync_len = 1, + .vsync_len = 1, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | + FB_SYNC_DOTCLK_FAILING_ACT, + }, +}; + +static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = { + .mode_list = mx23evk_video_modes, + .mode_count = ARRAY_SIZE(mx23evk_video_modes), + .default_bpp = 32, + .ld_intf_width = STMLCDIF_24BIT, }; static void __init mx23evk_init(void) { + int ret; + mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads)); mx23_add_duart(); mx23_add_auart0(); + + ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable"); + if (ret) + pr_warn("failed to request gpio lcd-enable: %d\n", ret); + else + gpio_set_value(MX23EVK_LCD_ENABLE, 1); + + ret = gpio_request_one(MX23EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable"); + if (ret) + pr_warn("failed to request gpio bl-enable: %d\n", ret); + else + gpio_set_value(MX23EVK_BL_ENABLE, 1); + + mx23_add_mxsfb(&mx23evk_mxsfb_pdata); } static void __init mx23evk_timer_init(void) -- cgit v0.10.2 From 4ca94366b314c22fda49cbe2c51ceb7bb3e16932 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 21 Feb 2011 18:31:45 +0800 Subject: ARM: mxs: add dma channel definitions Signed-off-by: Shawn Guo Tested-by: Wolfram Sang Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h index 4768402..1745e98 100644 --- a/arch/arm/mach-mxs/include/mach/mx23.h +++ b/arch/arm/mach-mxs/include/mach/mx23.h @@ -142,4 +142,28 @@ #define MX23_INT_VDD5V_DROOP 64 #define MX23_INT_DCDC4P2_BO 65 +/* + * APBH DMA + */ +#define MX23_DMA_SSP1 1 +#define MX23_DMA_SSP2 2 +#define MX23_DMA_GPMI0 4 +#define MX23_DMA_GPMI1 5 +#define MX23_DMA_GPMI2 6 +#define MX23_DMA_GPMI3 7 + +/* + * APBX DMA + */ +#define MX23_DMA_ADC 0 +#define MX23_DMA_DAC 1 +#define MX23_DMA_SPDIF 2 +#define MX23_DMA_I2C 3 +#define MX23_DMA_SAIF0 4 +#define MX23_DMA_UART0_RX 6 +#define MX23_DMA_UART0_TX 7 +#define MX23_DMA_UART1_RX 8 +#define MX23_DMA_UART1_TX 9 +#define MX23_DMA_SAIF1 10 + #endif /* __MACH_MX23_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h index 0716745..3f3485a 100644 --- a/arch/arm/mach-mxs/include/mach/mx28.h +++ b/arch/arm/mach-mxs/include/mach/mx28.h @@ -185,4 +185,41 @@ #define MX28_INT_GPIO1 126 #define MX28_INT_GPIO0 127 +/* + * APBH DMA + */ +#define MX28_DMA_SSP0 0 +#define MX28_DMA_SSP1 1 +#define MX28_DMA_SSP2 2 +#define MX28_DMA_SSP3 3 +#define MX28_DMA_GPMI0 4 +#define MX28_DMA_GPMI1 5 +#define MX28_DMA_GPMI2 6 +#define MX28_DMA_GPMI3 7 +#define MX28_DMA_GPMI4 8 +#define MX28_DMA_GPMI5 9 +#define MX28_DMA_GPMI6 10 +#define MX28_DMA_GPMI7 11 +#define MX28_DMA_HSADC 12 +#define MX28_DMA_LCDIF 13 + +/* + * APBX DMA + */ +#define MX28_DMA_AUART4_RX 0 +#define MX28_DMA_AUART4_TX 1 +#define MX28_DMA_SPDIF_TX 2 +#define MX28_DMA_SAIF0 4 +#define MX28_DMA_SAIF1 5 +#define MX28_DMA_I2C0 6 +#define MX28_DMA_I2C1 7 +#define MX28_DMA_AUART0_RX 8 +#define MX28_DMA_AUART0_TX 9 +#define MX28_DMA_AUART1_RX 10 +#define MX28_DMA_AUART1_TX 11 +#define MX28_DMA_AUART2_RX 12 +#define MX28_DMA_AUART2_TX 13 +#define MX28_DMA_AUART3_RX 14 +#define MX28_DMA_AUART3_TX 15 + #endif /* __MACH_MX28_H__ */ -- cgit v0.10.2 From 3baa4feeadf22ae72dad217f31ea739d881fc149 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 22 Feb 2011 21:36:27 +0800 Subject: ARM: mxs: add dma device Signed-off-by: Shawn Guo Tested-by: Wolfram Sang Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c index 2415b33..d133c7f 100644 --- a/arch/arm/mach-mxs/clock-mx23.c +++ b/arch/arm/mach-mxs/clock-mx23.c @@ -444,7 +444,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("duart", NULL, uart_clk) _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk) _REGISTER_CLOCK("rtc", NULL, rtc_clk) - _REGISTER_CLOCK(NULL, "hclk", hbus_clk) + _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk) + _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk) _REGISTER_CLOCK(NULL, "usb", usb_clk) _REGISTER_CLOCK(NULL, "audio", audio_clk) _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk) diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 8277056..a350f95 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -616,8 +616,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxs-auart.4", NULL, uart_clk) _REGISTER_CLOCK("rtc", NULL, rtc_clk) _REGISTER_CLOCK("pll2", NULL, pll2_clk) - _REGISTER_CLOCK(NULL, "hclk", hbus_clk) - _REGISTER_CLOCK(NULL, "xclk", xbus_clk) + _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk) + _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk) _REGISTER_CLOCK("flexcan.0", NULL, can0_clk) _REGISTER_CLOCK("flexcan.1", NULL, can1_clk) _REGISTER_CLOCK(NULL, "usb0", usb0_clk) diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile index 39bd773..0d9bea3 100644 --- a/arch/arm/mach-mxs/devices/Makefile +++ b/arch/arm/mach-mxs/devices/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o +obj-y += platform-dma.o obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o diff --git a/arch/arm/mach-mxs/devices/platform-dma.c b/arch/arm/mach-mxs/devices/platform-dma.c new file mode 100644 index 0000000..295c442 --- /dev/null +++ b/arch/arm/mach-mxs/devices/platform-dma.c @@ -0,0 +1,49 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include +#include + +#include +#include +#include + +static struct platform_device *__init mxs_add_dma(const char *devid, + resource_size_t base) +{ + struct resource res[] = { + { + .start = base, + .end = base + SZ_8K - 1, + .flags = IORESOURCE_MEM, + } + }; + + return mxs_add_platform_device_dmamask(devid, -1, + res, ARRAY_SIZE(res), NULL, 0, + DMA_BIT_MASK(32)); +} + +static int __init mxs_add_mxs_dma(void) +{ + char *apbh = "mxs-dma-apbh"; + char *apbx = "mxs-dma-apbx"; + + if (cpu_is_mx23()) { + mxs_add_dma(apbh, MX23_APBH_DMA_BASE_ADDR); + mxs_add_dma(apbx, MX23_APBX_DMA_BASE_ADDR); + } + + if (cpu_is_mx28()) { + mxs_add_dma(apbh, MX28_APBH_DMA_BASE_ADDR); + mxs_add_dma(apbx, MX28_APBX_DMA_BASE_ADDR); + } + + return 0; +} +arch_initcall(mxs_add_mxs_dma); -- cgit v0.10.2 From 208277f74e449fca082c1895086bd44c159efba5 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 21 Feb 2011 18:42:55 +0800 Subject: ARM: mxs: make ssp error irq definition consistent MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Shawn Guo Acked-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h index 1745e98..c0a18c2 100644 --- a/arch/arm/mach-mxs/include/mach/mx23.h +++ b/arch/arm/mach-mxs/include/mach/mx23.h @@ -93,7 +93,7 @@ #define MX23_INT_USB_WAKEUP 12 #define MX23_INT_GPMI_DMA 13 #define MX23_INT_SSP1_DMA 14 -#define MX23_INT_SSP_ERROR 15 +#define MX23_INT_SSP1_ERROR 15 #define MX23_INT_GPIO0 16 #define MX23_INT_GPIO1 17 #define MX23_INT_GPIO2 18 diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h index 3f3485a..75d8611 100644 --- a/arch/arm/mach-mxs/include/mach/mx28.h +++ b/arch/arm/mach-mxs/include/mach/mx28.h @@ -163,10 +163,10 @@ #define MX28_INT_USB0 93 #define MX28_INT_USB1_WAKEUP 94 #define MX28_INT_USB0_WAKEUP 95 -#define MX28_INT_SSP0 96 -#define MX28_INT_SSP1 97 -#define MX28_INT_SSP2 98 -#define MX28_INT_SSP3 99 +#define MX28_INT_SSP0_ERROR 96 +#define MX28_INT_SSP1_ERROR 97 +#define MX28_INT_SSP2_ERROR 98 +#define MX28_INT_SSP3_ERROR 99 #define MX28_INT_ENET_SWI 100 #define MX28_INT_ENET_MAC0 101 #define MX28_INT_ENET_MAC1 102 -- cgit v0.10.2 From acc9cdca62e596ca77e41e24a9d2c020a461bd99 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 3 Mar 2011 22:13:38 +0800 Subject: ARM: mxs/mx28evk: add flexcan devices Signed-off-by: Shawn Guo Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 989c08c..5ea676a 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -34,6 +34,7 @@ config MACH_MX28EVK select MXS_HAVE_AMBA_DUART select MXS_HAVE_PLATFORM_AUART select MXS_HAVE_PLATFORM_FEC + select MXS_HAVE_PLATFORM_FLEXCAN select MXS_OCOTP default y help diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c index 987e3d5..8bb2217 100644 --- a/arch/arm/mach-mxs/mach-mx28evk.c +++ b/arch/arm/mach-mxs/mach-mx28evk.c @@ -28,6 +28,7 @@ #include "devices-mx28.h" #include "gpio.h" +#define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13) #define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15) #define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) @@ -69,6 +70,15 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = { MX28_PAD_SSP1_DATA3__GPIO_2_15 | MXS_PAD_CTRL, /* phy reset line */ MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MXS_PAD_CTRL, + + /* flexcan0 */ + MX28_PAD_GPMI_RDY2__CAN0_TX, + MX28_PAD_GPMI_RDY3__CAN0_RX, + /* flexcan1 */ + MX28_PAD_GPMI_CE2N__CAN1_TX, + MX28_PAD_GPMI_CE3N__CAN1_RX, + /* transceiver power control */ + MX28_PAD_SSP1_CMD__GPIO_2_13, }; /* fec */ @@ -152,8 +162,44 @@ error: return -ETIMEDOUT; } +/* + * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers + */ +static int flexcan0_en, flexcan1_en; + +static void mx28evk_flexcan_switch(void) +{ + if (flexcan0_en || flexcan1_en) + gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1); + else + gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0); +} + +static void mx28evk_flexcan0_switch(int enable) +{ + flexcan0_en = enable; + mx28evk_flexcan_switch(); +} + +static void mx28evk_flexcan1_switch(int enable) +{ + flexcan1_en = enable; + mx28evk_flexcan_switch(); +} + +static const struct flexcan_platform_data + mx28evk_flexcan_pdata[] __initconst = { + { + .transceiver_switch = mx28evk_flexcan0_switch, + }, { + .transceiver_switch = mx28evk_flexcan1_switch, + } +}; + static void __init mx28evk_init(void) { + int ret; + mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads)); mx28_add_duart(); @@ -166,6 +212,15 @@ static void __init mx28evk_init(void) mx28evk_fec_reset(); mx28_add_fec(0, &mx28_fec_pdata[0]); mx28_add_fec(1, &mx28_fec_pdata[1]); + + ret = gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT, + "flexcan-switch"); + if (ret) { + pr_err("failed to request gpio flexcan-switch: %d\n", ret); + } else { + mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]); + mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]); + } } static void __init mx28evk_timer_init(void) -- cgit v0.10.2 From beb859645a8a9dfa089bef05206c844d9d34f307 Mon Sep 17 00:00:00 2001 From: Alberto Panizzo Date: Mon, 7 Mar 2011 11:44:13 +0100 Subject: spi_imx: Fix misspelled configuration variable SOC_IMX31 This fix a kernel NULL pointer error while initialising SPI introduced by: 4d2f13be1e370a670c1cae20c194d5ce961e0fa5 Signed-off-by: Alberto Panizzo Signed-off-by: Sascha Hauer diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index bd9dad5..996cf03 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -161,7 +161,7 @@ config SPI_IMX_VER_0_0 def_bool y if SOC_IMX21 || SOC_IMX27 config SPI_IMX_VER_0_4 - def_bool y if SOC_MX31 + def_bool y if SOC_IMX31 config SPI_IMX_VER_0_7 def_bool y if ARCH_MX25 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53 -- cgit v0.10.2 From 0ce88b34ea5a1b48438848739a72da6b4fe7a5fa Mon Sep 17 00:00:00 2001 From: Alberto Panizzo Date: Mon, 7 Mar 2011 11:45:07 +0100 Subject: mach-mx31_3ds: Add support for the MMC slot of the personality board Signed-off-by: Alberto Panizzo Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index f1dbb9d..cff9206 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "devices-imx31.h" #include "devices.h" @@ -99,6 +100,85 @@ static int mx31_3ds_pins[] = { /* I2C1 */ MX31_PIN_I2C_CLK__I2C1_SCL, MX31_PIN_I2C_DAT__I2C1_SDA, + /* SDHC1 */ + MX31_PIN_SD1_DATA3__SD1_DATA3, + MX31_PIN_SD1_DATA2__SD1_DATA2, + MX31_PIN_SD1_DATA1__SD1_DATA1, + MX31_PIN_SD1_DATA0__SD1_DATA0, + MX31_PIN_SD1_CLK__SD1_CLK, + MX31_PIN_SD1_CMD__SD1_CMD, + MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */ + MX31_PIN_GPIO3_0__GPIO3_0, /* OE */ +}; + +/* + * Support for SD card slot in personality board + */ +#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1) +#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0) + +static struct gpio mx31_3ds_sdhc1_gpios[] = { + { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" }, + { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" }, +}; + +static int mx31_3ds_sdhc1_init(struct device *dev, + irq_handler_t detect_irq, + void *data) +{ + int ret; + + ret = gpio_request_array(mx31_3ds_sdhc1_gpios, + ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); + if (ret) { + pr_warning("Unable to request the SD/MMC GPIOs.\n"); + return ret; + } + + ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), + detect_irq, IRQF_DISABLED | + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, + "sdhc1-detect", data); + if (ret) { + pr_warning("Unable to request the SD/MMC card-detect IRQ.\n"); + goto gpio_free; + } + + return 0; + +gpio_free: + gpio_free_array(mx31_3ds_sdhc1_gpios, + ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); + return ret; +} + +static void mx31_3ds_sdhc1_exit(struct device *dev, void *data) +{ + free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data); + gpio_free_array(mx31_3ds_sdhc1_gpios, + ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); +} + +static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd) +{ + /* + * While the voltage stuff is done by the driver, activate the + * Buffer Enable Pin only if there is a card in slot to fix the card + * voltage issue caused by bi-directional chip TXB0108 on 3Stack. + * Done here because at this stage we have for sure a debounced value + * of the presence of the card, showed by the value of vdd. + * 7 == ilog2(MMC_VDD_165_195) + */ + if (vdd > 7) + gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1); + else + gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0); +} + +static struct imxmmc_platform_data sdhc1_pdata = { + .init = mx31_3ds_sdhc1_init, + .exit = mx31_3ds_sdhc1_exit, + .setpower = mx31_3ds_sdhc1_setpower, }; /* @@ -137,6 +217,21 @@ static struct regulator_init_data gpo_init = { } }; +static struct regulator_consumer_supply vmmc2_consumers[] = { + REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"), +}; + +static struct regulator_init_data vmmc2_init = { + .constraints = { + .min_uV = 3000000, + .max_uV = 3000000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers), + .consumer_supplies = vmmc2_consumers, +}; + static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = { { .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */ @@ -151,6 +246,9 @@ static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = { }, { .id = MC13783_REG_GPO3, /* Turn on 3.3V */ .init_data = &gpo_init, + }, { + .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */ + .init_data = &vmmc2_init, }, }; @@ -362,6 +460,7 @@ static void __init mx31_3ds_init(void) "devices on the debug board are unusable.\n"); imx31_add_imx2_wdt(NULL); imx31_add_imx_i2c0(&mx31_3ds_i2c0_data); + imx31_add_mxc_mmc(0, &sdhc1_pdata); } static void __init mx31_3ds_timer_init(void) -- cgit v0.10.2 From e42010e0e129cc31a83ce9d8d1c7e1d50ba155f3 Mon Sep 17 00:00:00 2001 From: Alberto Panizzo Date: Mon, 7 Mar 2011 11:46:38 +0100 Subject: mach-mx31_3ds: Add support for framebuffer and LCD Signed-off-by: Alberto Panizzo Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index cff9206..d760a06 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -36,6 +37,8 @@ #include #include #include +#include +#include #include "devices-imx31.h" #include "devices.h" @@ -50,6 +53,12 @@ static int mx31_3ds_pins[] = { MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1, IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), + /*SPI0*/ + MX31_PIN_CSPI1_SCLK__SCLK, + MX31_PIN_CSPI1_MOSI__MOSI, + MX31_PIN_CSPI1_MISO__MISO, + MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, + MX31_PIN_CSPI1_SS2__SS2, /* CS for LCD */ /* SPI 1 */ MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_MOSI__MOSI, @@ -109,6 +118,70 @@ static int mx31_3ds_pins[] = { MX31_PIN_SD1_CMD__SD1_CMD, MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */ MX31_PIN_GPIO3_0__GPIO3_0, /* OE */ + /* Framebuffer */ + MX31_PIN_LD0__LD0, + MX31_PIN_LD1__LD1, + MX31_PIN_LD2__LD2, + MX31_PIN_LD3__LD3, + MX31_PIN_LD4__LD4, + MX31_PIN_LD5__LD5, + MX31_PIN_LD6__LD6, + MX31_PIN_LD7__LD7, + MX31_PIN_LD8__LD8, + MX31_PIN_LD9__LD9, + MX31_PIN_LD10__LD10, + MX31_PIN_LD11__LD11, + MX31_PIN_LD12__LD12, + MX31_PIN_LD13__LD13, + MX31_PIN_LD14__LD14, + MX31_PIN_LD15__LD15, + MX31_PIN_LD16__LD16, + MX31_PIN_LD17__LD17, + MX31_PIN_VSYNC3__VSYNC3, + MX31_PIN_HSYNC__HSYNC, + MX31_PIN_FPSHIFT__FPSHIFT, + MX31_PIN_CONTRAST__CONTRAST, +}; + +/* + * FB support + */ +static const struct fb_videomode fb_modedb[] = { + { /* 480x640 @ 60 Hz */ + .name = "Epson-VGA", + .refresh = 60, + .xres = 480, + .yres = 640, + .pixclock = 41701, + .left_margin = 20, + .right_margin = 41, + .upper_margin = 10, + .lower_margin = 5, + .hsync_len = 20, + .vsync_len = 10, + .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, +}; + +static struct ipu_platform_data mx3_ipu_data = { + .irq_base = MXC_IPU_IRQ_START, +}; + +static struct mx3fb_platform_data mx3fb_pdata = { + .dma_dev = &mx3_ipu.dev, + .name = "Epson-VGA", + .mode = fb_modedb, + .num_modes = ARRAY_SIZE(fb_modedb), +}; + +/* LCD */ +static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = { + .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1), + .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS), + .core_supply = "lcd_2v8", + .io_supply = "vdd_lcdio", }; /* @@ -232,6 +305,38 @@ static struct regulator_init_data vmmc2_init = { .consumer_supplies = vmmc2_consumers, }; +static struct regulator_consumer_supply vmmc1_consumers[] = { + REGULATOR_SUPPLY("lcd_2v8", NULL), +}; + +static struct regulator_init_data vmmc1_init = { + .constraints = { + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers), + .consumer_supplies = vmmc1_consumers, +}; + +static struct regulator_consumer_supply vgen_consumers[] = { + REGULATOR_SUPPLY("vdd_lcdio", NULL), +}; + +static struct regulator_init_data vgen_init = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(vgen_consumers), + .consumer_supplies = vgen_consumers, +}; + static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = { { .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */ @@ -249,6 +354,12 @@ static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = { }, { .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */ .init_data = &vmmc2_init, + }, { + .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */ + .init_data = &vmmc1_init, + }, { + .id = MC13783_REG_VGEN, /* Power LCD */ + .init_data = &vgen_init, }, }; @@ -260,6 +371,15 @@ static struct mc13xxx_platform_data mc13783_pdata __initdata = { }; /* SPI */ +static int spi0_internal_chipselect[] = { + MXC_SPI_CS(2), +}; + +static const struct spi_imx_master spi0_pdata __initconst = { + .chipselect = spi0_internal_chipselect, + .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect), +}; + static int spi1_internal_chipselect[] = { MXC_SPI_CS(0), MXC_SPI_CS(2), @@ -279,6 +399,12 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = { .platform_data = &mc13783_pdata, .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), .mode = SPI_CS_HIGH, + }, { + .modalias = "l4f00242t03", + .max_speed_hz = 5000000, + .bus_num = 0, + .chip_select = 0, /* SS2 */ + .platform_data = &mx31_3ds_l4f00242t03_pdata, }, }; @@ -461,6 +587,10 @@ static void __init mx31_3ds_init(void) imx31_add_imx2_wdt(NULL); imx31_add_imx_i2c0(&mx31_3ds_i2c0_data); imx31_add_mxc_mmc(0, &sdhc1_pdata); + + imx31_add_spi_imx0(&spi0_pdata); + mxc_register_device(&mx3_ipu, &mx3_ipu_data); + mxc_register_device(&mx3_fb, &mx3fb_pdata); } static void __init mx31_3ds_timer_init(void) -- cgit v0.10.2 From 164f7b5237cca2701dd2943928ec8d078877a28d Mon Sep 17 00:00:00 2001 From: Alberto Panizzo Date: Mon, 7 Mar 2011 11:47:37 +0100 Subject: mach-mx31_3ds: Add support for the camera device on the personality board Signed-off-by: Alberto Panizzo Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index d760a06..544d3e4 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -25,6 +25,9 @@ #include #include #include +#include + +#include #include #include @@ -39,6 +42,7 @@ #include #include #include +#include #include "devices-imx31.h" #include "devices.h" @@ -141,6 +145,106 @@ static int mx31_3ds_pins[] = { MX31_PIN_HSYNC__HSYNC, MX31_PIN_FPSHIFT__FPSHIFT, MX31_PIN_CONTRAST__CONTRAST, + /* CSI */ + MX31_PIN_CSI_D6__CSI_D6, + MX31_PIN_CSI_D7__CSI_D7, + MX31_PIN_CSI_D8__CSI_D8, + MX31_PIN_CSI_D9__CSI_D9, + MX31_PIN_CSI_D10__CSI_D10, + MX31_PIN_CSI_D11__CSI_D11, + MX31_PIN_CSI_D12__CSI_D12, + MX31_PIN_CSI_D13__CSI_D13, + MX31_PIN_CSI_D14__CSI_D14, + MX31_PIN_CSI_D15__CSI_D15, + MX31_PIN_CSI_HSYNC__CSI_HSYNC, + MX31_PIN_CSI_MCLK__CSI_MCLK, + MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, + MX31_PIN_CSI_VSYNC__CSI_VSYNC, + MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */ + IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */ +}; + +/* + * Camera support + */ +static phys_addr_t mx3_camera_base __initdata; +#define MX31_3DS_CAMERA_BUF_SIZE SZ_8M + +#define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5) +#define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1) + +static struct gpio mx31_3ds_camera_gpios[] = { + { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" }, + { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" }, +}; + +static int __init mx31_3ds_camera_alloc_dma(void) +{ + int dma; + + if (!mx3_camera_base) + return -ENOMEM; + + dma = dma_declare_coherent_memory(&mx3_camera.dev, + mx3_camera_base, mx3_camera_base, + MX31_3DS_CAMERA_BUF_SIZE, + DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); + + if (!(dma & DMA_MEMORY_MAP)) + return -ENOMEM; + + return 0; +} + +static int mx31_3ds_camera_power(struct device *dev, int on) +{ + /* enable or disable the camera */ + pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE"); + gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1); + + if (!on) + goto out; + + /* If enabled, give a reset impulse */ + gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0); + msleep(20); + gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1); + msleep(100); + +out: + return 0; +} + +static struct i2c_board_info mx31_3ds_i2c_camera = { + I2C_BOARD_INFO("ov2640", 0x30), +}; + +static struct regulator_bulk_data mx31_3ds_camera_regs[] = { + { .supply = "cmos_vcore" }, + { .supply = "cmos_2v8" }, +}; + +static struct soc_camera_link iclink_ov2640 = { + .bus_id = 0, + .board_info = &mx31_3ds_i2c_camera, + .i2c_adapter_id = 0, + .power = mx31_3ds_camera_power, + .regulators = mx31_3ds_camera_regs, + .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs), +}; + +static struct platform_device mx31_3ds_ov2640 = { + .name = "soc-camera-pdrv", + .id = 0, + .dev = { + .platform_data = &iclink_ov2640, + }, +}; + +struct mx3_camera_pdata mx31_3ds_camera_pdata = { + .dma_dev = &mx3_ipu.dev, + .flags = MX3_CAMERA_DATAWIDTH_10, + .mclk_10khz = 2600, }; /* @@ -307,6 +411,7 @@ static struct regulator_init_data vmmc2_init = { static struct regulator_consumer_supply vmmc1_consumers[] = { REGULATOR_SUPPLY("lcd_2v8", NULL), + REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"), }; static struct regulator_init_data vmmc1_init = { @@ -337,6 +442,22 @@ static struct regulator_init_data vgen_init = { .consumer_supplies = vgen_consumers, }; +static struct regulator_consumer_supply vvib_consumers[] = { + REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"), +}; + +static struct regulator_init_data vvib_init = { + .constraints = { + .min_uV = 1300000, + .max_uV = 1300000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(vvib_consumers), + .consumer_supplies = vvib_consumers, +}; + static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = { { .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */ @@ -360,6 +481,9 @@ static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = { }, { .id = MC13783_REG_VGEN, /* Power LCD */ .init_data = &vgen_init, + }, { + .id = MC13783_REG_VVIB, /* Power CMOS */ + .init_data = &vvib_init, }, }; @@ -552,8 +676,14 @@ static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = { .bitrate = 100000, }; +static struct platform_device *devices[] __initdata = { + &mx31_3ds_ov2640, +}; + static void __init mx31_3ds_init(void) { + int ret; + mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), "mx31_3ds"); @@ -564,6 +694,8 @@ static void __init mx31_3ds_init(void) spi_register_board_info(mx31_3ds_spi_devs, ARRAY_SIZE(mx31_3ds_spi_devs)); + platform_add_devices(devices, ARRAY_SIZE(devices)); + imx31_add_imx_keypad(&mx31_3ds_keymap_data); mx31_3ds_usbotg_init(); @@ -591,6 +723,20 @@ static void __init mx31_3ds_init(void) imx31_add_spi_imx0(&spi0_pdata); mxc_register_device(&mx3_ipu, &mx3_ipu_data); mxc_register_device(&mx3_fb, &mx3fb_pdata); + + /* CSI */ + /* Camera power: default - off */ + ret = gpio_request_array(mx31_3ds_camera_gpios, + ARRAY_SIZE(mx31_3ds_camera_gpios)); + if (ret) { + pr_err("Failed to request camera gpios"); + iclink_ov2640.power = NULL; + } + + if (!mx31_3ds_camera_alloc_dma()) + mxc_register_device(&mx3_camera, &mx31_3ds_camera_pdata); + else + pr_err("Failed to allocate dma memory for camera"); } static void __init mx31_3ds_timer_init(void) @@ -602,6 +748,15 @@ static struct sys_timer mx31_3ds_timer = { .init = mx31_3ds_timer_init, }; +static void __init mx31_3ds_reserve(void) +{ + /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */ + mx3_camera_base = memblock_alloc(MX31_3DS_CAMERA_BUF_SIZE, + MX31_3DS_CAMERA_BUF_SIZE); + memblock_free(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE); + memblock_remove(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE); +} + MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") /* Maintainer: Freescale Semiconductor, Inc. */ .boot_params = MX3x_PHYS_OFFSET + 0x100, @@ -610,4 +765,5 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") .init_irq = mx31_init_irq, .timer = &mx31_3ds_timer, .init_machine = mx31_3ds_init, + .reserve = mx31_3ds_reserve, MACHINE_END -- cgit v0.10.2 From cba57eb7d55923b74ed8c7d1dd97ecf98b7bba77 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 7 Mar 2011 12:18:55 +0200 Subject: ARM: imx/mx25: fix (again) spi device registration typo This typo was fixed in 46e3f30 (mx25: fix spi device registration typo), but a the merge at 0e44e059 (Merge commit 'v2.6.37-rc4' into imx-for-2.6.38) resolved the merge conflict wrongly. Cc: Sascha Hauer Signed-off-by: Baruch Siach Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h index bde33ca..d1ea79a 100644 --- a/arch/arm/mach-imx/devices-imx25.h +++ b/arch/arm/mach-imx/devices-imx25.h @@ -81,7 +81,7 @@ imx25_sdhci_esdhc_imx_data[] __initconst; extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst; #define imx25_add_spi_imx(id, pdata) \ - imx_add_spi_imx(&imx25_spi_imx_data[id], pdata) + imx_add_spi_imx(&imx25_cspi_data[id], pdata) #define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) #define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) #define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) -- cgit v0.10.2 From 47be6b92c37a27837d73f4807684ce423aed796d Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 7 Mar 2011 15:19:11 +0200 Subject: ARM: imx/mx25: dynamically allocate pwm devices Signed-off-by: Baruch Siach Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h index d1ea79a..b591d72 100644 --- a/arch/arm/mach-imx/devices-imx25.h +++ b/arch/arm/mach-imx/devices-imx25.h @@ -85,3 +85,7 @@ extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst; #define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) #define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) #define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) + +extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst; +#define imx25_add_mxc_pwm(id) \ + imx_add_mxc_pwm(&imx25_mxc_pwm_data[id]) -- cgit v0.10.2 From 12b90f8a2ce4d913d9080dcd6b6c329db00cbbeb Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 8 Mar 2011 18:51:09 +0800 Subject: ARM: mx28: set proper parent for lcdif clock Most likely, the LCD panel on mx28 platform will require a pixel clock higher than ref_xtal_clk (24 MHz), so the patch initializes the parent of lcdif clock as ref_pix_clk. Signed-off-by: Shawn Guo Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index a350f95..5e489a2 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -750,6 +750,8 @@ int __init mx28_clocks_init(void) clk_enable(&emi_clk); clk_enable(&uart_clk); + clk_set_parent(&lcdif_clk, &ref_pix_clk); + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0); -- cgit v0.10.2 From 0590a790319e2de59e0f15cf00af7fe473eb9ec8 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 8 Mar 2011 18:51:10 +0800 Subject: ARM: mxs/mx28evk: add framebuffer device Signed-off-by: Shawn Guo Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 5ea676a..4f6f174 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -35,6 +35,7 @@ config MACH_MX28EVK select MXS_HAVE_PLATFORM_AUART select MXS_HAVE_PLATFORM_FEC select MXS_HAVE_PLATFORM_FLEXCAN + select MXS_HAVE_PLATFORM_MXSFB select MXS_OCOTP default y help diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c index 8bb2217..08002d0 100644 --- a/arch/arm/mach-mxs/mach-mx28evk.c +++ b/arch/arm/mach-mxs/mach-mx28evk.c @@ -30,6 +30,8 @@ #define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13) #define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15) +#define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18) +#define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30) #define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) static const iomux_cfg_t mx28evk_pads[] __initconst = { @@ -79,6 +81,40 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = { MX28_PAD_GPMI_CE3N__CAN1_RX, /* transceiver power control */ MX28_PAD_SSP1_CMD__GPIO_2_13, + + /* mxsfb (lcdif) */ + MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL, + MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL, + MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL, + MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL, + MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL, + MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL, + MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL, + MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL, + MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL, + MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL, + MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL, + MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL, + MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL, + MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL, + MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL, + MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL, + MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL, + MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL, + MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL, + MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL, + MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL, + MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL, + MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL, + MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL, + MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL, + MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL, + MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL, + MX28_PAD_LCD_CS__LCD_ENABLE | MXS_PAD_CTRL, + /* LCD panel enable */ + MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL, + /* backlight control */ + MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL, }; /* fec */ @@ -196,6 +232,32 @@ static const struct flexcan_platform_data } }; +/* mxsfb (lcdif) */ +static struct fb_videomode mx28evk_video_modes[] = { + { + .name = "Seiko-43WVF1G", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 29851, /* picosecond (33.5 MHz) */ + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | + FB_SYNC_DOTCLK_FAILING_ACT, + }, +}; + +static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = { + .mode_list = mx28evk_video_modes, + .mode_count = ARRAY_SIZE(mx28evk_video_modes), + .default_bpp = 32, + .ld_intf_width = STMLCDIF_24BIT, +}; + static void __init mx28evk_init(void) { int ret; @@ -221,6 +283,20 @@ static void __init mx28evk_init(void) mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]); mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]); } + + ret = gpio_request_one(MX28EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable"); + if (ret) + pr_warn("failed to request gpio lcd-enable: %d\n", ret); + else + gpio_set_value(MX28EVK_LCD_ENABLE, 1); + + ret = gpio_request_one(MX28EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable"); + if (ret) + pr_warn("failed to request gpio bl-enable: %d\n", ret); + else + gpio_set_value(MX28EVK_BL_ENABLE, 1); + + mx28_add_mxsfb(&mx28evk_mxsfb_pdata); } static void __init mx28evk_timer_init(void) -- cgit v0.10.2 From bb0a80e394b512028ad6cf4c86157d4f9db5aab8 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 10 Mar 2011 14:15:46 +0800 Subject: mx51 enchance the sd/mmc HW timing compatibility on mx51 boards. Some cards have the CRC errors in read on mx51 BBG board. Configure the eSDHC pad configurations to level up the compatibility to fix this issue. Signed-off-by: Richard Zhu Tested-by: Shawn Guo Signed-off-by: Sascha Hauer diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index 6056cf2..df6acc0 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -985,11 +985,11 @@ #define MX51_PAD_NANDF_WE_B__GPIO3_3 (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_WE_B__NANDF_WE_B (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_WE_B__PATA_DIOW (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_WE_B__SD3_DATA0 (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WE_B__SD3_DATA0 (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_NANDF_RE_B__GPIO3_4 (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_RE_B__NANDF_RE_B (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_RE_B__PATA_DIOR (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RE_B__SD3_DATA1 (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RE_B__SD3_DATA1 (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_NANDF_ALE__GPIO3_5 (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_ALE__NANDF_ALE (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -999,18 +999,18 @@ #define MX51_PAD_NANDF_WP_B__GPIO3_7 (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_WP_B__NANDF_WP_B (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_WP_B__PATA_DMACK (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_WP_B__SD3_DATA2 (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WP_B__SD3_DATA2 (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_NANDF_RB0__ECSPI2_SS1 (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) #define MX51_PAD_NANDF_RB0__GPIO3_8 (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_RB0__NANDF_RB0 (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_RB0__PATA_DMARQ (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB0__SD3_DATA3 (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB0__SD3_DATA3 (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_NANDF_RB1__CSPI_MOSI (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) #define MX51_PAD_NANDF_RB1__ECSPI2_RDY (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) #define MX51_PAD_NANDF_RB1__GPIO3_9 (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_RB1__NANDF_RB1 (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_RB1__PATA_IORDY (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB1__SD4_CMD (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__SD4_CMD (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_NANDF_RB2__DISP2_WAIT (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) #define MX51_PAD_NANDF_RB2__FEC_COL (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) @@ -1036,41 +1036,41 @@ #define MX51_PAD_NANDF_CS2__GPIO3_18 (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_CS2__NANDF_CS2 (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_CS2__PATA_CS_0 (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS2__SD4_CLK (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__SD4_CLK (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) #define MX51_PAD_NANDF_CS2__USBH3_H1_DP (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_CS3__FEC_MDC (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) #define MX51_PAD_NANDF_CS3__GPIO3_19 (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_CS3__NANDF_CS3 (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_CS3__PATA_CS_1 (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS3__SD4_DAT0 (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS3__SD4_DAT0 (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_NANDF_CS3__USBH3_H1_DM (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_CS4__FEC_TDATA1 (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) #define MX51_PAD_NANDF_CS4__GPIO3_20 (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_CS4__NANDF_CS4 (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_CS4__PATA_DA_0 (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS4__SD4_DAT1 (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS4__SD4_DAT1 (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_NANDF_CS4__USBH3_STP (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_CS5__FEC_TDATA2 (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) #define MX51_PAD_NANDF_CS5__GPIO3_21 (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_CS5__NANDF_CS5 (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_CS5__PATA_DA_1 (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS5__SD4_DAT2 (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS5__SD4_DAT2 (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_NANDF_CS5__USBH3_DIR (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_CS6__CSPI_SS3 (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) #define MX51_PAD_NANDF_CS6__FEC_TDATA3 (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) #define MX51_PAD_NANDF_CS6__GPIO3_22 (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_CS6__NANDF_CS6 (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_CS6__PATA_DA_2 (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS6__SD4_DAT3 (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS6__SD4_DAT3 (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_NANDF_CS7__FEC_TX_EN (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) #define MX51_PAD_NANDF_CS7__GPIO3_23 (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_CS7__NANDF_CS7 (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS7__SD3_CLK (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS7__SD3_CLK (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) #define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) #define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) #define MX51_PAD_NANDF_RDY_INT__GPIO3_24 (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RDY_INT__SD3_CMD (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RDY_INT__SD3_CMD (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_NANDF_D15__ECSPI2_MOSI (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) #define MX51_PAD_NANDF_D15__GPIO3_25 (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_D15__NANDF_D15 (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -1479,26 +1479,26 @@ #define MX51_PAD_SD1_CLK__SD1_CLK (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) #define MX51_PAD_SD1_DATA0__AUD5_TXD (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_SD1_DATA0__CSPI_MISO (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_SD1_DATA0__SD1_DATA0 (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA0__SD1_DATA0 (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_EIM_DA0__EIM_DA0 (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_DA1__EIM_DA1 (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_DA2__EIM_DA2 (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_DA3__EIM_DA3 (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_SD1_DATA1__AUD5_RXD (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD1_DATA1__SD1_DATA1 (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA1__SD1_DATA1 (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_EIM_DA4__EIM_DA4 (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_DA5__EIM_DA5 (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_DA6__EIM_DA6 (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_DA7__EIM_DA7 (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_SD1_DATA2__AUD5_TXC (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD1_DATA2__SD1_DATA2 (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA2__SD1_DATA2 (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_EIM_DA10__EIM_DA10 (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_DA11__EIM_DA11 (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_DA8__EIM_DA8 (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_DA9__EIM_DA9 (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_SD1_DATA3__AUD5_TXFS (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_SD1_DATA3__CSPI_SS1 (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_SD1_DATA3__SD1_DATA3 (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA3__SD1_DATA3 (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_GPIO1_0__CSPI_SS2 (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) #define MX51_PAD_GPIO1_0__GPIO1_0 (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_GPIO1_0__SD1_CD (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) @@ -1517,16 +1517,16 @@ #define MX51_PAD_SD2_CLK__SD2_CLK (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) #define MX51_PAD_SD2_DATA0__CSPI_MISO (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) #define MX51_PAD_SD2_DATA0__SD1_DAT4 (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD2_DATA0__SD2_DATA0 (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA0__SD2_DATA0 (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_SD2_DATA1__SD1_DAT5 (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD2_DATA1__SD2_DATA1 (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA1__SD2_DATA1 (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_SD2_DATA1__USBH3_H2_DP (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_SD2_DATA2__SD1_DAT6 (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD2_DATA2__SD2_DATA2 (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA2__SD2_DATA2 (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_SD2_DATA2__USBH3_H2_DM (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_SD2_DATA3__CSPI_SS2 (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) #define MX51_PAD_SD2_DATA3__SD1_DAT7 (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD2_DATA3__SD2_DATA3 (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA3__SD2_DATA3 (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) #define MX51_PAD_GPIO1_2__CCM_OUT_2 (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_GPIO1_2__GPIO1_2 (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_GPIO1_2__I2C2_SCL (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) -- cgit v0.10.2 From f7fdaca910e6bc13659ecdffc28c97938b752e01 Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Sun, 20 Feb 2011 17:10:51 -0500 Subject: arm: imx: Zero entire imxdma structure The semantic match that finds the problem: // @@ type T; identifier x; @@ T *x; ... * memset(x, ..., ... * sizeof(x) * ...); // Signed-off-by: Ilia Mirkin Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c index e9f1769..236f149 100644 --- a/arch/arm/mach-imx/dma-v1.c +++ b/arch/arm/mach-imx/dma-v1.c @@ -699,7 +699,7 @@ int imx_dma_request(int channel, const char *name) local_irq_restore(flags); return -EBUSY; } - memset(imxdma, 0, sizeof(imxdma)); + memset(imxdma, 0, sizeof(*imxdma)); imxdma->name = name; local_irq_restore(flags); /* request_irq() can block */ -- cgit v0.10.2