From 30d6e2d5eb3b5614398879a98ccc119fa9ffb83c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 23 Sep 2012 16:18:38 -0300 Subject: ARM: dts: imx28-evk: Use pinctrl for gpio-led Since commit 8fe4554f (leds: leds-gpio: adopt pinctrl support) gpio-led driver has pinctrl support, so setup the gpio led pin via pinctrl and avoid the following warning: leds-gpio leds.12: pins are not configured from the driver Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index a0ad71c..2da316e 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -76,7 +76,6 @@ 0x20c3 /* MX28_PAD_SSP1_SCK__GPIO_2_12 */ 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ - 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ 0x3083 /* MX28_PAD_AUART2_RX__GPIO_3_8 */ 0x3093 /* MX28_PAD_AUART2_TX__GPIO_3_9 */ >; @@ -85,6 +84,16 @@ fsl,pull-up = <0>; }; + led_pin_gpio3_5: led_gpio3_5@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + gpmi_pins_evk: gpmi-nand-evk@0 { reg = <0>; fsl,pinmux-ids = < @@ -288,6 +297,8 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_gpio3_5>; user { label = "Heartbeat"; -- cgit v0.10.2 From b34aa18502446379494529b863eb0743856b1a25 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 24 Sep 2012 23:52:19 -0300 Subject: ARM: dts: imx23-olinuxino: Remove unneeded "default-on" The initial state of the gpio led can be set directly in "gpios" node. Hence, linux,default-trigger can be removed. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts index 384d8b6..35489a1 100644 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/imx23-olinuxino.dts @@ -94,8 +94,7 @@ user { label = "green"; - gpios = <&gpio2 1 0>; - linux,default-trigger = "default-on"; + gpios = <&gpio2 1 1>; }; }; }; -- cgit v0.10.2 From 098e7522896c0d0fe5264124949626df44520f57 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 24 Sep 2012 23:52:20 -0300 Subject: ARM: dts: imx23-olinuxino: Use pinctrl for gpio-led Since commit 8fe4554f (leds: leds-gpio: adopt pinctrl support) gpio-led driver has pinctrl support, so setup the gpio led pin via pinctrl and avoid the following warning: leds-gpio leds.5: pins are not configured from the driver Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts index 35489a1..8bd56fc 100644 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/imx23-olinuxino.dts @@ -40,6 +40,15 @@ reg = <0>; fsl,pinmux-ids = < 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + led_pin_gpio0_17: led_gpio0_17@0 { + reg = <0>; + fsl,pinmux-ids = < 0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */ >; fsl,drive-strength = <0>; @@ -91,6 +100,8 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_gpio0_17>; user { label = "green"; -- cgit v0.10.2 From 8eec4b3117405e5561d2c65c9222cf3334c0ca3a Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sun, 7 Oct 2012 10:36:28 +0800 Subject: ARM: dts: cfa10049: Add FEC to the CFA-10049 expansion board Signed-off-by: Maxime Ripard Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index 05c892e..a34676f 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -96,4 +96,15 @@ gpio = <&gpio0 7 1>; }; }; + + ahb@80080000 { + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio2 21 0>; + phy-reset-duration = <100>; + status = "okay"; + }; + }; }; diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 4748ec5..b8c452a 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -160,6 +160,7 @@ static struct sys_timer imx28_timer = { enum mac_oui { OUI_FSL, OUI_DENX, + OUI_CRYSTALFONTZ, }; static void __init update_fec_mac_prop(enum mac_oui oui) @@ -205,6 +206,11 @@ static void __init update_fec_mac_prop(enum mac_oui oui) macaddr[1] = 0xe5; macaddr[2] = 0x4e; break; + case OUI_CRYSTALFONTZ: + macaddr[0] = 0x58; + macaddr[1] = 0xb9; + macaddr[2] = 0xe1; + break; } val = ocotp[i]; macaddr[3] = (val >> 16) & 0xff; @@ -355,6 +361,12 @@ static void __init tx28_post_init(void) pinctrl_put(pctl); } +static void __init cfa10049_init(void) +{ + enable_clk_enet_out(); + update_fec_mac_prop(OUI_CRYSTALFONTZ); +} + static void __init mxs_machine_init(void) { if (of_machine_is_compatible("fsl,imx28-evk")) @@ -365,6 +377,8 @@ static void __init mxs_machine_init(void) m28evk_init(); else if (of_machine_is_compatible("bluegiga,apx4devkit")) apx4devkit_init(); + else if (of_machine_is_compatible("crystalfontz,cfa10049")) + cfa10049_init(); of_platform_populate(NULL, of_default_bus_match_table, mxs_auxdata_lookup, NULL); -- cgit v0.10.2 From 70191db9308e33b5d0063f3a4a6ad22abf594a9d Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Wed, 17 Oct 2012 18:13:24 +0900 Subject: ARM: dts: Enable serial controllers on Origen and SMDKV310 This patch adds status override of serial nodes to enable used serial ports on Origen and SMDKV310 board. Signed-off-by: Tomasz Figa Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 3e68f52..f16c99f 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -57,6 +57,22 @@ status = "okay"; }; + serial@13800000 { + status = "okay"; + }; + + serial@13810000 { + status = "okay"; + }; + + serial@13820000 { + status = "okay"; + }; + + serial@13830000 { + status = "okay"; + }; + gpio_keys { compatible = "gpio-keys"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 63610c3..9b23a82 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -43,6 +43,22 @@ status = "okay"; }; + serial@13800000 { + status = "okay"; + }; + + serial@13810000 { + status = "okay"; + }; + + serial@13820000 { + status = "okay"; + }; + + serial@13830000 { + status = "okay"; + }; + keypad@100A0000 { samsung,keypad-num-rows = <2>; samsung,keypad-num-columns = <8>; -- cgit v0.10.2 From 2eae613b95a786714bd1b5825ea3abc78d229d3f Mon Sep 17 00:00:00 2001 From: Arun Kumar K Date: Tue, 23 Oct 2012 22:51:33 +0900 Subject: ARM: EXYNOS: Add MFC device tree support This patch adds device tree entry for MFC v6 in the Exynos5 SoC. Makes the required changes in the clock files and adds MFC to the DT device list. Signed-off-by: Naveen Krishna Chatradhi Signed-off-by: Arun Kumar K [kgene.kim@samsung.com: fixed section mismatches Seung-Woo Kim reported] Signed-off-by: Kukjin Kim diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt new file mode 100644 index 0000000..67ec3d4 --- /dev/null +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt @@ -0,0 +1,23 @@ +* Samsung Multi Format Codec (MFC) + +Multi Format Codec (MFC) is the IP present in Samsung SoCs which +supports high resolution decoding and encoding functionalities. +The MFC device driver is a v4l2 driver which can encode/decode +video raw/elementary streams and has support for all popular +video codecs. + +Required properties: + - compatible : value should be either one among the following + (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs + (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs + + - reg : Physical base address of the IP registers and length of memory + mapped region. + + - interrupts : MFC interrupt number to the CPU. + + - samsung,mfc-r : Base address of the first memory bank used by MFC + for DMA contiguous memory allocation and its size. + + - samsung,mfc-l : Base address of the second memory bank used by MFC + for DMA contiguous memory allocation and its size. diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index a352df4..21d4ccd 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -166,4 +166,9 @@ spi_2: spi@12d40000 { status = "disabled"; }; + + codec@11000000 { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; + }; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index dddfd6e..49546bc 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -62,6 +62,12 @@ interrupts = <0 42 0>; }; + codec@11000000 { + compatible = "samsung,mfc-v6"; + reg = <0x11000000 0x10000>; + interrupts = <0 96 0>; + }; + rtc { compatible = "samsung,s3c6410-rtc"; reg = <0x101E0000 0x100>; diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index da55107..bb3b09a 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -63,6 +63,7 @@ config SOC_EXYNOS5250 depends on ARCH_EXYNOS5 select S5P_PM if PM select S5P_SLEEP if PM + select S5P_DEV_MFC select SAMSUNG_DMADEV help Enable EXYNOS5250 SoC support diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index c44ca1e..8c4e325 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -664,7 +664,7 @@ static struct clk exynos5_init_clocks_off[] = { .ctrlbit = (1 << 25), }, { .name = "mfc", - .devname = "s5p-mfc", + .devname = "s5p-mfc-v6", .enable = exynos5_clk_ip_mfc_ctrl, .ctrlbit = (1 << 0), }, { diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index db1cd8e..b7f1154 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -11,6 +11,8 @@ #include #include +#include +#include #include #include @@ -18,6 +20,7 @@ #include #include +#include #include "common.h" @@ -72,6 +75,7 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { "exynos-gsc.2", NULL), OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3, "exynos-gsc.3", NULL), + OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL), {}, }; @@ -92,6 +96,17 @@ static char const *exynos5250_dt_compat[] __initdata = { NULL }; +static void __init exynos5_reserve(void) +{ + struct s5p_mfc_dt_meminfo mfc_mem; + + /* Reserve memory for MFC only if it's available */ + mfc_mem.compatible = "samsung,mfc-v6"; + if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem)) + s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff, + mfc_mem.lsize); +} + DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") /* Maintainer: Kukjin Kim */ .init_irq = exynos5_init_irq, @@ -103,4 +118,5 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") .timer = &exynos4_timer, .dt_compat = exynos5250_dt_compat, .restart = exynos5_restart, + .reserve = exynos5_reserve, MACHINE_END diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 03f654d..52dfa8f 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -933,6 +933,7 @@ struct platform_device s5p_device_mfc_r = { .coherent_dma_mask = DMA_BIT_MASK(32), }, }; + #endif /* CONFIG_S5P_DEV_MFC */ /* MIPI CSIS */ diff --git a/arch/arm/plat-samsung/include/plat/mfc.h b/arch/arm/plat-samsung/include/plat/mfc.h index ac13227..e6d7c42 100644 --- a/arch/arm/plat-samsung/include/plat/mfc.h +++ b/arch/arm/plat-samsung/include/plat/mfc.h @@ -10,6 +10,14 @@ #ifndef __PLAT_SAMSUNG_MFC_H #define __PLAT_SAMSUNG_MFC_H __FILE__ +struct s5p_mfc_dt_meminfo { + unsigned long loff; + unsigned long lsize; + unsigned long roff; + unsigned long rsize; + char *compatible; +}; + /** * s5p_mfc_reserve_mem - function to early reserve memory for MFC driver * @rbase: base address for MFC 'right' memory interface @@ -24,4 +32,7 @@ void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, phys_addr_t lbase, unsigned int lsize); +int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname, + int depth, void *data); + #endif /* __PLAT_SAMSUNG_MFC_H */ diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c index ad60894..5ec104b 100644 --- a/arch/arm/plat-samsung/s5p-dev-mfc.c +++ b/arch/arm/plat-samsung/s5p-dev-mfc.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include #include @@ -69,3 +71,35 @@ static int __init s5p_mfc_memory_init(void) return 0; } device_initcall(s5p_mfc_memory_init); + +#ifdef CONFIG_OF +int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname, + int depth, void *data) +{ + __be32 *prop; + unsigned long len; + struct s5p_mfc_dt_meminfo *mfc_mem = data; + + if (!data) + return 0; + + if (!of_flat_dt_is_compatible(node, mfc_mem->compatible)) + return 0; + + prop = of_get_flat_dt_prop(node, "samsung,mfc-l", &len); + if (!prop || (len != 2 * sizeof(unsigned long))) + return 0; + + mfc_mem->loff = be32_to_cpu(prop[0]); + mfc_mem->lsize = be32_to_cpu(prop[1]); + + prop = of_get_flat_dt_prop(node, "samsung,mfc-r", &len); + if (!prop || (len != 2 * sizeof(unsigned long))) + return 0; + + mfc_mem->roff = be32_to_cpu(prop[0]); + mfc_mem->rsize = be32_to_cpu(prop[1]); + + return 1; +} +#endif -- cgit v0.10.2 From a957fdca4feb7fbc51f9c7c6a152a86f35ca7751 Mon Sep 17 00:00:00 2001 From: Julien Boibessot Date: Thu, 18 Oct 2012 11:50:26 +0200 Subject: ARM: mxs: Add support for the Armadeus Systems APF28 module The APF28 is a small SOM built around an i.MX28 processor with 128MBytes DDR2, 256MBytes NAND Flash and an Ethernet PHY. Signed-off-by: Julien Boibessot Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c1ce813..9bca96f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -54,6 +54,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx23-olinuxino.dtb \ imx23-stmp378x_devb.dtb \ + imx28-apf28.dtb \ imx28-apx4devkit.dtb \ imx28-cfa10036.dtb \ imx28-cfa10049.dtb \ diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts new file mode 100644 index 0000000..7eb0758 --- /dev/null +++ b/arch/arm/boot/dts/imx28-apf28.dts @@ -0,0 +1,85 @@ +/* + * Copyright 2012 Armadeus Systems - + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx28.dtsi" + +/ { + model = "Armadeus Systems APF28 module"; + compatible = "armadeus,imx28-apf28", "fsl,imx28"; + + memory { + reg = <0x40000000 0x08000000>; + }; + + apb@80000000 { + apbh@80000000 { + gpmi-nand@8000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x300000>; + }; + + partition@300000 { + label = "env"; + reg = <0x300000 0x80000>; + }; + + partition@380000 { + label = "env2"; + reg = <0x380000 0x80000>; + }; + + partition@400000 { + label = "dtb"; + reg = <0x400000 0x80000>; + }; + + partition@480000 { + label = "splash"; + reg = <0x480000 0x80000>; + }; + + partition@500000 { + label = "kernel"; + reg = <0x500000 0x800000>; + }; + + partition@d00000 { + label = "rootfs"; + reg = <0xd00000 0xf300000>; + }; + }; + }; + + apbx@80040000 { + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + }; + }; + + ahb@80080000 { + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio4 13 0>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index b8c452a..9cfb25c 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -367,6 +367,11 @@ static void __init cfa10049_init(void) update_fec_mac_prop(OUI_CRYSTALFONTZ); } +static void __init apf28_init(void) +{ + enable_clk_enet_out(); +} + static void __init mxs_machine_init(void) { if (of_machine_is_compatible("fsl,imx28-evk")) @@ -379,6 +384,8 @@ static void __init mxs_machine_init(void) apx4devkit_init(); else if (of_machine_is_compatible("crystalfontz,cfa10049")) cfa10049_init(); + else if (of_machine_is_compatible("armadeus,imx28-apf28")) + apf28_init(); of_platform_populate(NULL, of_default_bus_match_table, mxs_auxdata_lookup, NULL); -- cgit v0.10.2 From 8d4155dbb184f02c08bd36c5120f2b4dc4f14860 Mon Sep 17 00:00:00 2001 From: Amit Daniel Kachhap Date: Mon, 29 Oct 2012 21:18:01 +0900 Subject: ARM: EXYNOS: Add devicetree node for TMU driver for exynos4 This patch adds necessary source definations needed for TMU driver and adds devicetree node for exynos4210. Signed-off-by: Amit Daniel Kachhap Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 214c557..038de97 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -303,4 +303,11 @@ #gpio-cells = <4>; }; }; + + tmu@100C0000 { + compatible = "samsung,exynos4210-tmu"; + interrupt-parent = <&combiner>; + reg = <0x100C0000 0x100>; + interrupts = <2 4>; + }; }; diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index 6a45c9a..1870bee 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -576,6 +576,10 @@ static struct clk exynos4_init_clocks_off[] = { .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 15), }, { + .name = "tmu_apbif", + .enable = exynos4_clk_ip_perir_ctrl, + .ctrlbit = (1 << 17), + }, { .name = "keypad", .enable = exynos4_clk_ip_perir_ctrl, .ctrlbit = (1 << 16), diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index 35bced6..5adacd1 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h @@ -136,6 +136,9 @@ #define EXYNOS4_IRQ_TSI IRQ_SPI(115) #define EXYNOS4_IRQ_SATA IRQ_SPI(116) +#define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4) +#define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4) + #define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) #define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1) #define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2) diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 8480849..772acd3 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -88,6 +88,8 @@ #define EXYNOS4_PA_TWD 0x10500600 #define EXYNOS4_PA_L2CC 0x10502000 +#define EXYNOS4_PA_TMU 0x100C0000 + #define EXYNOS4_PA_MDMA0 0x10810000 #define EXYNOS4_PA_MDMA1 0x12850000 #define EXYNOS4_PA_PDMA0 0x12680000 diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c index e58d786..0276ae4 100644 --- a/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -77,6 +77,8 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = { "exynos4210-spi.2", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU, + "exynos-tmu", NULL), {}, }; -- cgit v0.10.2 From ef405e04abd0d4bc3f7082d241517f6db3f5c06d Mon Sep 17 00:00:00 2001 From: Amit Daniel Kachhap Date: Mon, 29 Oct 2012 21:23:29 +0900 Subject: ARM: EXYNOS: Add devicetree node for TMU driver for exynos5 This patch adds necessary source definations needed for TMU driver and adds devicetree node for exynos5250. Signed-off-by: Amit Daniel Kachhap [kgene.kim@samsung.com: used address value directly in auxdata] Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 49546bc..670dfdb 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -74,6 +74,12 @@ interrupts = <0 43 0>, <0 44 0>; }; + tmu@10060000 { + compatible = "samsung,exynos5250-tmu"; + reg = <0x10060000 0x100>; + interrupts = <0 65 0>; + }; + serial@12C00000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C00000 0x100>; diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index 8c4e325..cdfff4b 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -616,6 +616,11 @@ static struct clk exynos5_init_clocks_off[] = { .enable = exynos5_clk_ip_peric_ctrl, .ctrlbit = (1 << 24), }, { + .name = "tmu_apbif", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peris_ctrl, + .ctrlbit = (1 << 21), + }, { .name = "rtc", .parent = &exynos5_clk_aclk_66.clk, .enable = exynos5_clk_ip_peris_ctrl, diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index b7f1154..4c0f336 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -76,6 +76,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3, "exynos-gsc.3", NULL), OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL), + OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000, + "exynos-tmu", NULL), {}, }; -- cgit v0.10.2 From 566cf8eef26d99415aa8a542bd6bba6a719d2031 Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Mon, 29 Oct 2012 21:48:43 +0900 Subject: ARM: dts: add device tree support for exynos5 hdmi This patch adds support for device tree based discovery for exynos5 hdmi. Hdmi node is also renamed with "exynos5-hdmi". Signed-off-by: Rahul Sharma Signed-off-by: Kukjin Kim diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmi.txt b/Documentation/devicetree/bindings/drm/exynos/hdmi.txt new file mode 100644 index 0000000..589edee --- /dev/null +++ b/Documentation/devicetree/bindings/drm/exynos/hdmi.txt @@ -0,0 +1,22 @@ +Device-Tree bindings for drm hdmi driver + +Required properties: +- compatible: value should be "samsung,exynos5-hdmi". +- reg: physical base address of the hdmi and length of memory mapped + region. +- interrupts: interrupt number to the cpu. +- hpd-gpio: following information about the hotplug gpio pin. + a) phandle of the gpio controller node. + b) pin number within the gpio controller. + c) pin function mode. + d) optional flags and pull up/down. + e) drive strength. + +Example: + + hdmi { + compatible = "samsung,exynos5-hdmi"; + reg = <0x14530000 0x100000>; + interrupts = <0 95 0>; + hpd-gpio = <&gpx3 7 0xf 1 3>; + }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index a352df4..2a478ab 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -166,4 +166,8 @@ spi_2: spi@12d40000 { status = "disabled"; }; + + hdmi { + hpd-gpio = <&gpx3 7 0xf 1 3>; + }; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index dddfd6e..b68be1c 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -520,4 +520,10 @@ reg = <0x13e30000 0x1000>; interrupts = <0 88 0>; }; + + hdmi { + compatible = "samsung,exynos5-hdmi"; + reg = <0x14530000 0x100000>; + interrupts = <0 95 0>; + }; }; diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index db1cd8e..5e38208 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -72,6 +72,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { "exynos-gsc.2", NULL), OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3, "exynos-gsc.3", NULL), + OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000, + "exynos5-hdmi", NULL), {}, }; -- cgit v0.10.2 From 5af0d8a372811c353ab7de5d161463f58aa2173a Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Mon, 29 Oct 2012 21:51:36 +0900 Subject: ARM: dts: add device tree support for exynos5 mixer This patch adds support for device tree based discovery for exynos5 mixer. Mixer node is also renamed with "exynos5-mixer". Signed-off-by: Rahul Sharma Signed-off-by: Kukjin Kim diff --git a/Documentation/devicetree/bindings/drm/exynos/mixer.txt b/Documentation/devicetree/bindings/drm/exynos/mixer.txt new file mode 100644 index 0000000..9b2ea03 --- /dev/null +++ b/Documentation/devicetree/bindings/drm/exynos/mixer.txt @@ -0,0 +1,15 @@ +Device-Tree bindings for mixer driver + +Required properties: +- compatible: value should be "samsung,exynos5-mixer". +- reg: physical base address of the mixer and length of memory mapped + region. +- interrupts: interrupt number to the cpu. + +Example: + + mixer { + compatible = "samsung,exynos5-mixer"; + reg = <0x14450000 0x10000>; + interrupts = <0 94 0>; + }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index b68be1c..2a203e6 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -526,4 +526,10 @@ reg = <0x14530000 0x100000>; interrupts = <0 95 0>; }; + + mixer { + compatible = "samsung,exynos5-mixer"; + reg = <0x14450000 0x10000>; + interrupts = <0 94 0>; + }; }; diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 5e38208..4fc15da 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -74,6 +74,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { "exynos-gsc.3", NULL), OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000, "exynos5-hdmi", NULL), + OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000, + "exynos5-mixer", NULL), {}, }; -- cgit v0.10.2 From 3e3e9ce4474c3c1ec6e3e05268705ed086825159 Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Mon, 29 Oct 2012 21:51:42 +0900 Subject: ARM: dts: add device tree support for exynos5 hdmiphy This patch adds support for device tree based discovery for exynos5 hdmiphy. Signed-off-by: Rahul Sharma Signed-off-by: Kukjin Kim diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt b/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt new file mode 100644 index 0000000..858f4f9 --- /dev/null +++ b/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt @@ -0,0 +1,12 @@ +Device-Tree bindings for hdmiphy driver + +Required properties: +- compatible: value should be "samsung,exynos5-hdmiphy". +- reg: I2C address of the hdmiphy device. + +Example: + + hdmiphy { + compatible = "samsung,exynos5-hdmiphy"; + reg = <0x38>; + }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 2a478ab..7dc196f 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -79,6 +79,16 @@ status = "disabled"; }; + i2c@12CE0000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + + hdmiphy@38 { + compatible = "samsung,exynos5-hdmiphy"; + reg = <0x38>; + }; + }; + dwmmc_0: dwmmc0@12200000 { num-slots = <1>; supports-highspeed; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 2a203e6..190068f 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -156,6 +156,14 @@ #size-cells = <0>; }; + i2c@12CE0000 { + compatible = "samsung,s3c2440-hdmiphy-i2c"; + reg = <0x12CE0000 0x1000>; + interrupts = <0 64 0>; + #address-cells = <1>; + #size-cells = <0>; + }; + spi_0: spi@12d20000 { compatible = "samsung,exynos4210-spi"; reg = <0x12d20000 0x100>; diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 4fc15da..0f20ba8 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -47,6 +47,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { "s3c2440-i2c.0", NULL), OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1), "s3c2440-i2c.1", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8), + "s3c2440-hdmiphy-i2c", NULL), OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0, "dw_mmc.0", NULL), OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1, -- cgit v0.10.2 From 62a1f83f0cbbc9c2e2776b4ad91ccb2f500b6a0b Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Mon, 29 Oct 2012 21:51:47 +0900 Subject: ARM: dts: add device tree support for exynos5 hdmiddc This patch adds support for device tree based discovery for exynos5 hdmi ddc. Signed-off-by: Rahul Sharma Signed-off-by: Kukjin Kim diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt b/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt new file mode 100644 index 0000000..fa166d9 --- /dev/null +++ b/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt @@ -0,0 +1,12 @@ +Device-Tree bindings for hdmiddc driver + +Required properties: +- compatible: value should be "samsung,exynos5-hdmiddc". +- reg: I2C address of the hdmiddc device. + +Example: + + hdmiddc { + compatible = "samsung,exynos5-hdmiddc"; + reg = <0x50>; + }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 7dc196f..7212d53 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -56,7 +56,15 @@ }; i2c@12C80000 { - status = "disabled"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + gpios = <&gpa0 6 3 3 0>, + <&gpa0 7 3 3 0>; + + hdmiddc@50 { + compatible = "samsung,exynos5-hdmiddc"; + reg = <0x50>; + }; }; i2c@12C90000 { diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 0f20ba8..db03537 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -47,6 +47,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { "s3c2440-i2c.0", NULL), OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1), "s3c2440-i2c.1", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2), + "s3c2440-i2c.2", NULL), OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8), "s3c2440-hdmiphy-i2c", NULL), OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0, -- cgit v0.10.2 From cf3a97b4e4c4601d043ca1549c27e5fe18f55dde Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Mon, 29 Oct 2012 21:51:51 +0900 Subject: ARM: EXYNOS: add clocks for exynos5 hdmi This patch adds support for clocks for hdmi, hdmiphy and mixer. Signed-off-by: Rahul Sharma Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index c44ca1e..a86f20f 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -196,6 +196,11 @@ static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable) return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable); } +static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); +} + /* Core list of CMU_CPU side */ static struct clksrc_clk exynos5_clk_mout_apll = { @@ -669,12 +674,17 @@ static struct clk exynos5_init_clocks_off[] = { .ctrlbit = (1 << 0), }, { .name = "hdmi", - .devname = "exynos4-hdmi", + .devname = "exynos5-hdmi", .enable = exynos5_clk_ip_disp1_ctrl, .ctrlbit = (1 << 6), }, { + .name = "hdmiphy", + .devname = "exynos5-hdmi", + .enable = exynos5_clk_hdmiphy_ctrl, + .ctrlbit = (1 << 0), + }, { .name = "mixer", - .devname = "s5p-mixer", + .devname = "exynos5-mixer", .enable = exynos5_clk_ip_disp1_ctrl, .ctrlbit = (1 << 5), }, { -- cgit v0.10.2 From 0a9d5ac307aefbb2c772537d3fe7f75046d563ac Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Mon, 29 Oct 2012 21:51:55 +0900 Subject: ARM: EXYNOS: removing exynos-drm device registration from non-dt platforms As exynos-drm is a software device, its registration is moved to the exynos drm driver. This will provide generic solution for device registration for dt and non-dt platforms. Corresponding patches are posted to dri-devel list. Signed-off-by: Rahul Sharma Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 9b58024..1797dee 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -53,7 +53,6 @@ obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o -obj-$(CONFIG_EXYNOS_DEV_DRM) += dev-drm.o obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o diff --git a/arch/arm/mach-exynos/dev-drm.c b/arch/arm/mach-exynos/dev-drm.c deleted file mode 100644 index 17c9c6e..0000000 --- a/arch/arm/mach-exynos/dev-drm.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * linux/arch/arm/mach-exynos/dev-drm.c - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS - core DRM device - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include - -#include - -static u64 exynos_drm_dma_mask = DMA_BIT_MASK(32); - -struct platform_device exynos_device_drm = { - .name = "exynos-drm", - .dev = { - .dma_mask = &exynos_drm_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - } -}; diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c index c05d7aa..9497060 100644 --- a/arch/arm/mach-exynos/mach-nuri.c +++ b/arch/arm/mach-exynos/mach-nuri.c @@ -1327,9 +1327,6 @@ static struct platform_device *nuri_devices[] __initdata = { &cam_vdda_fixed_rdev, &cam_8m_12v_fixed_rdev, &exynos4_bus_devfreq, -#ifdef CONFIG_DRM_EXYNOS - &exynos_device_drm, -#endif }; static void __init nuri_map_io(void) diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c index 9adf491..d8dc6d7 100644 --- a/arch/arm/mach-exynos/mach-origen.c +++ b/arch/arm/mach-exynos/mach-origen.c @@ -709,9 +709,6 @@ static struct platform_device *origen_devices[] __initdata = { &s5p_device_mfc_l, &s5p_device_mfc_r, &s5p_device_mixer, -#ifdef CONFIG_DRM_EXYNOS - &exynos_device_drm, -#endif &exynos4_device_ohci, &origen_device_gpiokeys, &origen_lcd_hv070wsa, diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c index 730f1ac..17b9ca4 100644 --- a/arch/arm/mach-exynos/mach-smdk4x12.c +++ b/arch/arm/mach-exynos/mach-smdk4x12.c @@ -317,9 +317,6 @@ static struct platform_device *smdk4x12_devices[] __initdata = { &s5p_device_mfc, &s5p_device_mfc_l, &s5p_device_mfc_r, -#ifdef CONFIG_DRM_EXYNOS - &exynos_device_drm, -#endif &samsung_device_keypad, }; diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c index ee4fb1a..4f0ac53 100644 --- a/arch/arm/mach-exynos/mach-smdkv310.c +++ b/arch/arm/mach-exynos/mach-smdkv310.c @@ -300,9 +300,6 @@ static struct platform_device *smdkv310_devices[] __initdata = { &s5p_device_fimc_md, &s5p_device_g2d, &s5p_device_jpeg, -#ifdef CONFIG_DRM_EXYNOS - &exynos_device_drm, -#endif &exynos4_device_ac97, &exynos4_device_i2s0, &exynos4_device_ohci, diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c index ebc9dd3..cfdf876 100644 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ b/arch/arm/mach-exynos/mach-universal_c210.c @@ -1081,9 +1081,6 @@ static struct platform_device *universal_devices[] __initdata = { &s5p_device_onenand, &s5p_device_fimd0, &s5p_device_jpeg, -#ifdef CONFIG_DRM_EXYNOS - &exynos_device_drm, -#endif &s3c_device_usb_hsotg, &s5p_device_mfc, &s5p_device_mfc_l, diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index 5da4b4f..133e3e4 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -133,8 +133,6 @@ extern struct platform_device exynos4_device_pcm1; extern struct platform_device exynos4_device_pcm2; extern struct platform_device exynos4_device_spdif; -extern struct platform_device exynos_device_drm; - extern struct platform_device samsung_asoc_dma; extern struct platform_device samsung_asoc_idma; extern struct platform_device samsung_device_keypad; -- cgit v0.10.2 From 2bde51cb16e3b3f505b465cab263adc3a57d6c0a Mon Sep 17 00:00:00 2001 From: Julien Boibessot Date: Sat, 27 Oct 2012 12:15:46 +0200 Subject: ARM: dts: mxs: Add PWM3 muxing options for i.MX28 Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Julien Boibessot Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index e16d631..2b607aa 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -491,6 +491,16 @@ fsl,pull-up = <0>; }; + pwm3_pins_a: pwm3@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x31c0 /* MX28_PAD_PWM3__PWM_3 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + pwm4_pins_a: pwm4@0 { reg = <0>; fsl,pinmux-ids = < -- cgit v0.10.2 From 16d477018bdddcf87a908310ac9343734e26cde0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 25 Sep 2012 13:32:18 +0200 Subject: ARM: mx28: Skip OCOTP FEC MAC setup if in DT Currently, the kernel unconditionally adds "local-mac-address" and "mac-address" properties under both FEC ethernet DT nodes in case the update_fec_mac_prop() function is called. These properties are loaded with MAC address compiled from vendors OUI and a per-device NIC saved in OCOTP storage. Some more advanced bootloaders do augment the DT passed to the kernel by these properties already. In such case, it is wrong for kernel to override these values. Adjust the FEC MAC address loading so that in case the DT properties are already present in the DT passed from the bootloader, skip the loading from OCOTP altogether. If the DT properties are not present, load them from OCOTP. Note that the later case will lead to zeroed out MAC address if OCOTP is not programmed. This will lead to FEC not working at all. Signed-off-by: Marek Vasut Cc: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 9cfb25c..48c2eba 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -176,8 +176,12 @@ static void __init update_fec_mac_prop(enum mac_oui oui) np = of_find_compatible_node(from, NULL, "fsl,imx28-fec"); if (!np) return; + from = np; + if (of_get_property(np, "local-mac-address", NULL)) + continue; + newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL); if (!newmac) return; -- cgit v0.10.2 From 414b41536c4564db696d5fb18d8baf695491cd02 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Wed, 31 Oct 2012 18:39:26 +0100 Subject: ARM: mxs: Add support for the Armadeus Systems APF28Dev docking board The APF28Dev is a docking board for an APF28 SOM Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Julien Boibessot Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9bca96f..b451a79 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -55,6 +55,7 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx23-olinuxino.dtb \ imx23-stmp378x_devb.dtb \ imx28-apf28.dtb \ + imx28-apf28dev.dtb \ imx28-apx4devkit.dtb \ imx28-cfa10036.dtb \ imx28-cfa10049.dtb \ diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts new file mode 100644 index 0000000..dde09d4 --- /dev/null +++ b/arch/arm/boot/dts/imx28-apf28dev.dts @@ -0,0 +1,92 @@ +/* + * Copyright 2012 Armadeus Systems - + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* APF28Dev is a docking board for the APF28 SOM */ +/include/ "imx28-apf28.dts" + +/ { + model = "Armadeus Systems APF28Dev docking/development board"; + compatible = "armadeus,imx28-apf28dev", "armadeus,imx28-apf28", "fsl,imx28"; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg &mmc0_sck_cfg>; + bus-width = <4>; + status = "okay"; + }; + }; + + apbx@80040000 { + lradc@80050000 { + status = "okay"; + }; + + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_a &pwm4_pins_a>; + status = "okay"; + }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + + usbphy1: usbphy@8007e000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + vbus-supply = <®_usb0_vbus>; + status = "okay"; + }; + + usb1: usb@80090000 { + status = "okay"; + }; + + mac1: ethernet@800f4000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + phy-reset-gpios = <&gpio0 23 0>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_usb0_vbus: usb0_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 23 1>; + }; + }; + + leds { + compatible = "gpio-leds"; + + user { + label = "Heartbeat"; + gpios = <&gpio0 21 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; -- cgit v0.10.2 From 809efa565a83dee14ae44726a7a2766960a11b62 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 25 Sep 2012 12:04:51 +0100 Subject: ARM: ux500: Move regulator-name properties out to board DTS files Regulator supply names should be allocated by board rather than per SoC, as the same SoC could be wired differently on varying hardware. Here we push all regulator-name allocation out to the dbx5x0 subordinate board files; HREF and Snowball. Requested-by: Mark Brown Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index 4b0e0ca..058e682 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -209,123 +209,103 @@ // DB8500_REGULATOR_VAPE db8500_vape_reg: db8500_vape { regulator-compatible = "db8500_vape"; - regulator-name = "db8500-vape"; regulator-always-on; }; // DB8500_REGULATOR_VARM db8500_varm_reg: db8500_varm { regulator-compatible = "db8500_varm"; - regulator-name = "db8500-varm"; }; // DB8500_REGULATOR_VMODEM db8500_vmodem_reg: db8500_vmodem { regulator-compatible = "db8500_vmodem"; - regulator-name = "db8500-vmodem"; }; // DB8500_REGULATOR_VPLL db8500_vpll_reg: db8500_vpll { regulator-compatible = "db8500_vpll"; - regulator-name = "db8500-vpll"; }; // DB8500_REGULATOR_VSMPS1 db8500_vsmps1_reg: db8500_vsmps1 { regulator-compatible = "db8500_vsmps1"; - regulator-name = "db8500-vsmps1"; }; // DB8500_REGULATOR_VSMPS2 db8500_vsmps2_reg: db8500_vsmps2 { regulator-compatible = "db8500_vsmps2"; - regulator-name = "db8500-vsmps2"; }; // DB8500_REGULATOR_VSMPS3 db8500_vsmps3_reg: db8500_vsmps3 { regulator-compatible = "db8500_vsmps3"; - regulator-name = "db8500-vsmps3"; }; // DB8500_REGULATOR_VRF1 db8500_vrf1_reg: db8500_vrf1 { regulator-compatible = "db8500_vrf1"; - regulator-name = "db8500-vrf1"; }; // DB8500_REGULATOR_SWITCH_SVAMMDSP db8500_sva_mmdsp_reg: db8500_sva_mmdsp { regulator-compatible = "db8500_sva_mmdsp"; - regulator-name = "db8500-sva-mmdsp"; }; // DB8500_REGULATOR_SWITCH_SVAMMDSPRET db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { regulator-compatible = "db8500_sva_mmdsp_ret"; - regulator-name = "db8500-sva-mmdsp-ret"; }; // DB8500_REGULATOR_SWITCH_SVAPIPE db8500_sva_pipe_reg: db8500_sva_pipe { regulator-compatible = "db8500_sva_pipe"; - regulator-name = "db8500_sva_pipe"; }; // DB8500_REGULATOR_SWITCH_SIAMMDSP db8500_sia_mmdsp_reg: db8500_sia_mmdsp { regulator-compatible = "db8500_sia_mmdsp"; - regulator-name = "db8500_sia_mmdsp"; }; // DB8500_REGULATOR_SWITCH_SIAMMDSPRET db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { - regulator-name = "db8500-sia-mmdsp-ret"; }; // DB8500_REGULATOR_SWITCH_SIAPIPE db8500_sia_pipe_reg: db8500_sia_pipe { regulator-compatible = "db8500_sia_pipe"; - regulator-name = "db8500-sia-pipe"; }; // DB8500_REGULATOR_SWITCH_SGA db8500_sga_reg: db8500_sga { regulator-compatible = "db8500_sga"; - regulator-name = "db8500-sga"; vin-supply = <&db8500_vape_reg>; }; // DB8500_REGULATOR_SWITCH_B2R2_MCDE db8500_b2r2_mcde_reg: db8500_b2r2_mcde { regulator-compatible = "db8500_b2r2_mcde"; - regulator-name = "db8500-b2r2-mcde"; vin-supply = <&db8500_vape_reg>; }; // DB8500_REGULATOR_SWITCH_ESRAM12 db8500_esram12_reg: db8500_esram12 { regulator-compatible = "db8500_esram12"; - regulator-name = "db8500-esram12"; }; // DB8500_REGULATOR_SWITCH_ESRAM12RET db8500_esram12_ret_reg: db8500_esram12_ret { regulator-compatible = "db8500_esram12_ret"; - regulator-name = "db8500-esram12-ret"; }; // DB8500_REGULATOR_SWITCH_ESRAM34 db8500_esram34_reg: db8500_esram34 { regulator-compatible = "db8500_esram34"; - regulator-name = "db8500-esram34"; }; // DB8500_REGULATOR_SWITCH_ESRAM34RET db8500_esram34_ret_reg: db8500_esram34_ret { regulator-compatible = "db8500_esram34_ret"; - regulator-name = "db8500-esram34-ret"; }; }; @@ -404,7 +384,6 @@ // supplies to the display/camera ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { regulator-compatible = "ab8500_ldo_aux1"; - regulator-name = "V-DISPLAY"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2900000>; regulator-boot-on; @@ -415,7 +394,6 @@ // supplies to the on-board eMMC ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { regulator-compatible = "ab8500_ldo_aux2"; - regulator-name = "V-eMMC1"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <3300000>; }; @@ -423,7 +401,6 @@ // supply for VAUX3; SDcard slots ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { regulator-compatible = "ab8500_ldo_aux3"; - regulator-name = "V-MMC-SD"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <3300000>; }; @@ -431,49 +408,41 @@ // supply for v-intcore12; VINTCORE12 LDO ab8500_ldo_initcore_reg: ab8500_ldo_initcore { regulator-compatible = "ab8500_ldo_initcore"; - regulator-name = "V-INTCORE"; }; // supply for tvout; gpadc; TVOUT LDO ab8500_ldo_tvout_reg: ab8500_ldo_tvout { regulator-compatible = "ab8500_ldo_tvout"; - regulator-name = "V-TVOUT"; }; // supply for ab8500-usb; USB LDO ab8500_ldo_usb_reg: ab8500_ldo_usb { regulator-compatible = "ab8500_ldo_usb"; - regulator-name = "dummy"; }; // supply for ab8500-vaudio; VAUDIO LDO ab8500_ldo_audio_reg: ab8500_ldo_audio { regulator-compatible = "ab8500_ldo_audio"; - regulator-name = "V-AUD"; }; // supply for v-anamic1 VAMic1-LDO ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { regulator-compatible = "ab8500_ldo_anamic1"; - regulator-name = "V-AMIC1"; }; // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { regulator-compatible = "ab8500_ldo_amamic2"; - regulator-name = "V-AMIC2"; }; // supply for v-dmic; VDMIC LDO ab8500_ldo_dmic_reg: ab8500_ldo_dmic { regulator-compatible = "ab8500_ldo_dmic"; - regulator-name = "V-DMIC"; }; // supply for U8500 CSI/DSI; VANA LDO ab8500_ldo_ana_reg: ab8500_ldo_ana { regulator-compatible = "ab8500_ldo_ana"; - regulator-name = "V-CSI/DSI"; }; }; }; diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts index 2131d77..e2213204 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -91,5 +91,137 @@ msp3: msp@80125000 { status = "okay"; }; + + prcmu@80157000 { + db8500-prcmu-regulators { + db8500_vape_reg: db8500_vape { + regulator-name = "db8500-vape"; + }; + + db8500_varm_reg: db8500_varm { + regulator-name = "db8500-varm"; + }; + + db8500_vmodem_reg: db8500_vmodem { + regulator-name = "db8500-vmodem"; + }; + + db8500_vpll_reg: db8500_vpll { + regulator-name = "db8500-vpll"; + }; + + db8500_vsmps1_reg: db8500_vsmps1 { + regulator-name = "db8500-vsmps1"; + }; + + db8500_vsmps2_reg: db8500_vsmps2 { + regulator-name = "db8500-vsmps2"; + }; + + db8500_vsmps3_reg: db8500_vsmps3 { + regulator-name = "db8500-vsmps3"; + }; + + db8500_vrf1_reg: db8500_vrf1 { + regulator-name = "db8500-vrf1"; + }; + + db8500_sva_mmdsp_reg: db8500_sva_mmdsp { + regulator-name = "db8500-sva-mmdsp"; + }; + + db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { + regulator-name = "db8500-sva-mmdsp-ret"; + }; + + db8500_sva_pipe_reg: db8500_sva_pipe { + regulator-name = "db8500_sva_pipe"; + }; + + db8500_sia_mmdsp_reg: db8500_sia_mmdsp { + regulator-name = "db8500_sia_mmdsp"; + }; + + db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { + regulator-name = "db8500-sia-mmdsp-ret"; + }; + + db8500_sia_pipe_reg: db8500_sia_pipe { + regulator-name = "db8500-sia-pipe"; + }; + + db8500_sga_reg: db8500_sga { + regulator-name = "db8500-sga"; + }; + + db8500_b2r2_mcde_reg: db8500_b2r2_mcde { + regulator-name = "db8500-b2r2-mcde"; + }; + + db8500_esram12_reg: db8500_esram12 { + regulator-name = "db8500-esram12"; + }; + + db8500_esram12_ret_reg: db8500_esram12_ret { + regulator-name = "db8500-esram12-ret"; + }; + + db8500_esram34_reg: db8500_esram34 { + regulator-name = "db8500-esram34"; + }; + + db8500_esram34_ret_reg: db8500_esram34_ret { + regulator-name = "db8500-esram34-ret"; + }; + }; + + ab8500@5 { + ab8500-regulators { + ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { + regulator-name = "V-DISPLAY"; + }; + + ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { + regulator-name = "V-eMMC1"; + }; + + ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { + regulator-name = "V-MMC-SD"; + }; + + ab8500_ldo_initcore_reg: ab8500_ldo_initcore { + regulator-name = "V-INTCORE"; + }; + + ab8500_ldo_tvout_reg: ab8500_ldo_tvout { + regulator-name = "V-TVOUT"; + }; + + ab8500_ldo_usb_reg: ab8500_ldo_usb { + regulator-name = "dummy"; + }; + + ab8500_ldo_audio_reg: ab8500_ldo_audio { + regulator-name = "V-AUD"; + }; + + ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { + regulator-name = "V-AMIC1"; + }; + + ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { + regulator-name = "V-AMIC2"; + }; + + ab8500_ldo_dmic_reg: ab8500_ldo_dmic { + regulator-name = "V-DMIC"; + }; + + ab8500_ldo_ana_reg: ab8500_ldo_ana { + regulator-name = "V-CSI/DSI"; + }; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index 702c0ba..639b8e9 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts @@ -183,5 +183,137 @@ reg = <0x33>; }; }; + + prcmu@80157000 { + db8500-prcmu-regulators { + db8500_vape_reg: db8500_vape { + regulator-name = "db8500-vape"; + }; + + db8500_varm_reg: db8500_varm { + regulator-name = "db8500-varm"; + }; + + db8500_vmodem_reg: db8500_vmodem { + regulator-name = "db8500-vmodem"; + }; + + db8500_vpll_reg: db8500_vpll { + regulator-name = "db8500-vpll"; + }; + + db8500_vsmps1_reg: db8500_vsmps1 { + regulator-name = "db8500-vsmps1"; + }; + + db8500_vsmps2_reg: db8500_vsmps2 { + regulator-name = "db8500-vsmps2"; + }; + + db8500_vsmps3_reg: db8500_vsmps3 { + regulator-name = "db8500-vsmps3"; + }; + + db8500_vrf1_reg: db8500_vrf1 { + regulator-name = "db8500-vrf1"; + }; + + db8500_sva_mmdsp_reg: db8500_sva_mmdsp { + regulator-name = "db8500-sva-mmdsp"; + }; + + db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { + regulator-name = "db8500-sva-mmdsp-ret"; + }; + + db8500_sva_pipe_reg: db8500_sva_pipe { + regulator-name = "db8500_sva_pipe"; + }; + + db8500_sia_mmdsp_reg: db8500_sia_mmdsp { + regulator-name = "db8500_sia_mmdsp"; + }; + + db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { + regulator-name = "db8500-sia-mmdsp-ret"; + }; + + db8500_sia_pipe_reg: db8500_sia_pipe { + regulator-name = "db8500-sia-pipe"; + }; + + db8500_sga_reg: db8500_sga { + regulator-name = "db8500-sga"; + }; + + db8500_b2r2_mcde_reg: db8500_b2r2_mcde { + regulator-name = "db8500-b2r2-mcde"; + }; + + db8500_esram12_reg: db8500_esram12 { + regulator-name = "db8500-esram12"; + }; + + db8500_esram12_ret_reg: db8500_esram12_ret { + regulator-name = "db8500-esram12-ret"; + }; + + db8500_esram34_reg: db8500_esram34 { + regulator-name = "db8500-esram34"; + }; + + db8500_esram34_ret_reg: db8500_esram34_ret { + regulator-name = "db8500-esram34-ret"; + }; + }; + + ab8500@5 { + ab8500-regulators { + ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { + regulator-name = "V-DISPLAY"; + }; + + ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { + regulator-name = "V-eMMC1"; + }; + + ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { + regulator-name = "V-MMC-SD"; + }; + + ab8500_ldo_initcore_reg: ab8500_ldo_initcore { + regulator-name = "V-INTCORE"; + }; + + ab8500_ldo_tvout_reg: ab8500_ldo_tvout { + regulator-name = "V-TVOUT"; + }; + + ab8500_ldo_usb_reg: ab8500_ldo_usb { + regulator-name = "dummy"; + }; + + ab8500_ldo_audio_reg: ab8500_ldo_audio { + regulator-name = "V-AUD"; + }; + + ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { + regulator-name = "V-AMIC1"; + }; + + ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { + regulator-name = "V-AMIC2"; + }; + + ab8500_ldo_dmic_reg: ab8500_ldo_dmic { + regulator-name = "V-DMIC"; + }; + + ab8500_ldo_ana_reg: ab8500_ldo_ana { + regulator-name = "V-CSI/DSI"; + }; + }; + }; + }; }; }; -- cgit v0.10.2 From 0ddf855af6162df41345ea6afabd0190d751bfb9 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 25 Sep 2012 16:03:45 +0100 Subject: ARM: ux500: Fix initialisation order for UIBs An earlier change prevented User Interface Boards (UIBs) from being initialised on boards which did not support them. This change had the undesired effect of reordering the UIB initialisation calls with I2C registration. Here we ensure UIBs are only setup after all required infrastructure is already in place. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 416d436..e7dd757 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -618,8 +618,6 @@ static void __init mop500_init_machine(void) /* This board has full regulator constraints */ regulator_has_full_constraints(); - - mop500_uib_init(); } static void __init snowball_init_machine(void) @@ -684,8 +682,6 @@ static void __init hrefv60_init_machine(void) /* This board has full regulator constraints */ regulator_has_full_constraints(); - - mop500_uib_init(); } MACHINE_START(U8500, "ST-Ericsson MOP500 platform") @@ -721,7 +717,7 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform") .timer = &ux500_timer, .handle_irq = gic_handle_irq, .init_machine = snowball_init_machine, - .init_late = ux500_init_late, + .init_late = NULL, MACHINE_END #ifdef CONFIG_MACH_UX500_DT @@ -811,8 +807,6 @@ static void __init u8500_init_machine(void) i2c_register_board_info(2, mop500_i2c2_devices, ARRAY_SIZE(mop500_i2c2_devices)); - mop500_uib_init(); - } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { mop500_of_audio_init(parent); } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) { @@ -824,8 +818,6 @@ static void __init u8500_init_machine(void) mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; platform_add_devices(mop500_platform_devs, ARRAY_SIZE(mop500_platform_devs)); - - mop500_uib_init(); } /* This board has full regulator constraints */ diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 1f3fbc2..721e7b4 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -26,6 +26,8 @@ #include #include +#include "board-mop500.h" + void __iomem *_PRCMU_BASE; /* @@ -82,6 +84,7 @@ void __init ux500_init_irq(void) void __init ux500_init_late(void) { + mop500_uib_init(); } static const char * __init ux500_get_machine(void) -- cgit v0.10.2 From 81bf8c2e0f473c443bb067a55f55e6311adf5993 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 26 Sep 2012 12:55:56 +0100 Subject: ARM: ux500: Elaborate on SDI device node names in Device Tree In the DB8500 Reference Manual SDI devices are described as being part of peripheral blocks. This is more in line with how these devices are actually represented in hardware, so here we detail which peripheral block each of the SDI devices belong in the node name. Requested-by: Linus Walleij Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index 058e682..3b4298b 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -546,42 +546,42 @@ status = "disabled"; }; - sdi@80126000 { + sdi0_per1@80126000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80126000 0x1000>; interrupts = <0 60 0x4>; status = "disabled"; }; - sdi@80118000 { + sdi1_per2@80118000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80118000 0x1000>; interrupts = <0 50 0x4>; status = "disabled"; }; - sdi@80005000 { + sdi2_per3@80005000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80005000 0x1000>; interrupts = <0 41 0x4>; status = "disabled"; }; - sdi@80119000 { + sdi3_per2@80119000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80119000 0x1000>; interrupts = <0 59 0x4>; status = "disabled"; }; - sdi@80114000 { + sdi4_per2@80114000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80114000 0x1000>; interrupts = <0 99 0x4>; status = "disabled"; }; - sdi@80008000 { + sdi5_per3@80008000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80008000 0x1000>; interrupts = <0 100 0x4>; diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index 639b8e9..9a37244 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts @@ -120,7 +120,7 @@ }; // External Micro SD slot - sdi@80126000 { + sdi0_per1@80126000 { arm,primecell-periphid = <0x10480180>; max-frequency = <50000000>; bus-width = <8>; @@ -134,7 +134,7 @@ }; // On-board eMMC - sdi@80114000 { + sdi4_per2@80114000 { arm,primecell-periphid = <0x10480180>; max-frequency = <50000000>; bus-width = <8>; -- cgit v0.10.2 From 706b0a07ec3251063cca9a7912f6228ec892f44a Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 14 Sep 2012 15:27:41 +0100 Subject: ARM: ux500: Add SDI (MMC) support to the HREF Device Tree Here we add the Device Tree nodes which are required to successfully probe the MMCI driver which will enable the four cards available on ST-Ericsson's HREF hardware development platform. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts index e2213204..3fd83c6 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -77,6 +77,50 @@ }; }; + // External Micro SD slot + sdi0_per1@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + mmc-cap-sd-highspeed; + mmc-cap-mmc-highspeed; + vmmc-supply = <&ab8500_ldo_aux3_reg>; + + cd-gpios = <&tc3589x_gpio 3 0x4>; + + status = "okay"; + }; + + // WLAN SDIO channel + sdi1_per2@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + + status = "okay"; + }; + + // PoP:ed eMMC + sdi2_per3@80005000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <8>; + mmc-cap-mmc-highspeed; + + status = "okay"; + }; + + // On-board eMMC + sdi4_per2@80114000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <8>; + mmc-cap-mmc-highspeed; + vmmc-supply = <&ab8500_ldo_aux2_reg>; + + status = "okay"; + }; + sound { compatible = "stericsson,snd-soc-mop500"; diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index e7dd757..d141dd0 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -800,7 +800,6 @@ static void __init u8500_init_machine(void) platform_add_devices(mop500_platform_devs, ARRAY_SIZE(mop500_platform_devs)); - mop500_sdi_init(parent); mop500_audio_init(parent); i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); -- cgit v0.10.2 From 92a0f489efc4e194385179441265b45f6271dbee Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 26 Sep 2012 11:12:48 +0100 Subject: ARM: ux500: Correct Snowball's external SD/MMC slot's bus width Snowball's external SD/MMC slot is only capable of 4 bit data transfer, not 8 bits as previously thought. This is a simple fixup moving to the correct settings. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index 9a37244..6a2b58b 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts @@ -123,7 +123,7 @@ sdi0_per1@80126000 { arm,primecell-periphid = <0x10480180>; max-frequency = <50000000>; - bus-width = <8>; + bus-width = <4>; mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux3_reg>; -- cgit v0.10.2 From d1b8bfa342ca61a39d002e16ffc7f4990e4b0d1a Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 26 Sep 2012 13:29:09 +0100 Subject: ARM: ux500: Create a DTS hierarchy for ST-Ericsson's HREF boards There are two main versions of the ST-Ericsson hardware reference board, each with subtle differences. These versions are described in current platform data as 'mop500' for HREF v1.1 & v2.0 and 'hrefv60+' for latter incarnations. However, the boards have much in common, so this patch creates a .dtsi (Device Tree Source Include) file which describes the similarities between the two boards and individual 'hrefprev60' and 'hrefv60plus' .dts files which depict the differences. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi new file mode 100644 index 0000000..27baa44 --- /dev/null +++ b/arch/arm/boot/dts/href.dtsi @@ -0,0 +1,262 @@ +/* + * Copyright 2012 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "dbx5x0.dtsi" + +/ { + memory { + reg = <0x00000000 0x20000000>; + }; + + soc-u9500 { + uart@80120000 { + status = "okay"; + }; + + uart@80121000 { + status = "okay"; + }; + + uart@80007000 { + status = "okay"; + }; + + i2c@80004000 { + tc3589x@42 { + compatible = "tc3589x"; + reg = <0x42>; + interrupt-parent = <&gpio6>; + interrupts = <25 0x1>; + + interrupt-controller; + #interrupt-cells = <2>; + + tc3589x_gpio: tc3589x_gpio { + compatible = "tc3589x-gpio"; + interrupts = <0 0x1>; + + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; + + i2c@80128000 { + lp5521@0x33 { + compatible = "lp5521"; + reg = <0x33>; + }; + + lp5521@0x34 { + compatible = "lp5521"; + reg = <0x34>; + }; + + bh1780@0x29 { + compatible = "rohm,bh1780gli"; + reg = <0x33>; + }; + }; + + // External Micro SD slot + sdi0_per1@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + mmc-cap-sd-highspeed; + mmc-cap-mmc-highspeed; + vmmc-supply = <&ab8500_ldo_aux3_reg>; + + cd-gpios = <&tc3589x_gpio 3 0x4>; + + status = "okay"; + }; + + // WLAN SDIO channel + sdi1_per2@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + + status = "okay"; + }; + + // PoP:ed eMMC + sdi2_per3@80005000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <8>; + mmc-cap-mmc-highspeed; + + status = "okay"; + }; + + // On-board eMMC + sdi4_per2@80114000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <8>; + mmc-cap-mmc-highspeed; + vmmc-supply = <&ab8500_ldo_aux2_reg>; + + status = "okay"; + }; + + sound { + compatible = "stericsson,snd-soc-mop500"; + + stericsson,cpu-dai = <&msp1 &msp3>; + stericsson,audio-codec = <&codec>; + }; + + msp1: msp@80124000 { + status = "okay"; + }; + + msp3: msp@80125000 { + status = "okay"; + }; + + prcmu@80157000 { + db8500-prcmu-regulators { + db8500_vape_reg: db8500_vape { + regulator-name = "db8500-vape"; + }; + + db8500_varm_reg: db8500_varm { + regulator-name = "db8500-varm"; + }; + + db8500_vmodem_reg: db8500_vmodem { + regulator-name = "db8500-vmodem"; + }; + + db8500_vpll_reg: db8500_vpll { + regulator-name = "db8500-vpll"; + }; + + db8500_vsmps1_reg: db8500_vsmps1 { + regulator-name = "db8500-vsmps1"; + }; + + db8500_vsmps2_reg: db8500_vsmps2 { + regulator-name = "db8500-vsmps2"; + }; + + db8500_vsmps3_reg: db8500_vsmps3 { + regulator-name = "db8500-vsmps3"; + }; + + db8500_vrf1_reg: db8500_vrf1 { + regulator-name = "db8500-vrf1"; + }; + + db8500_sva_mmdsp_reg: db8500_sva_mmdsp { + regulator-name = "db8500-sva-mmdsp"; + }; + + db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { + regulator-name = "db8500-sva-mmdsp-ret"; + }; + + db8500_sva_pipe_reg: db8500_sva_pipe { + regulator-name = "db8500_sva_pipe"; + }; + + db8500_sia_mmdsp_reg: db8500_sia_mmdsp { + regulator-name = "db8500_sia_mmdsp"; + }; + + db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { + regulator-name = "db8500-sia-mmdsp-ret"; + }; + + db8500_sia_pipe_reg: db8500_sia_pipe { + regulator-name = "db8500-sia-pipe"; + }; + + db8500_sga_reg: db8500_sga { + regulator-name = "db8500-sga"; + }; + + db8500_b2r2_mcde_reg: db8500_b2r2_mcde { + regulator-name = "db8500-b2r2-mcde"; + }; + + db8500_esram12_reg: db8500_esram12 { + regulator-name = "db8500-esram12"; + }; + + db8500_esram12_ret_reg: db8500_esram12_ret { + regulator-name = "db8500-esram12-ret"; + }; + + db8500_esram34_reg: db8500_esram34 { + regulator-name = "db8500-esram34"; + }; + + db8500_esram34_ret_reg: db8500_esram34_ret { + regulator-name = "db8500-esram34-ret"; + }; + }; + + ab8500@5 { + ab8500-regulators { + ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { + regulator-name = "V-DISPLAY"; + }; + + ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { + regulator-name = "V-eMMC1"; + }; + + ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { + regulator-name = "V-MMC-SD"; + }; + + ab8500_ldo_initcore_reg: ab8500_ldo_initcore { + regulator-name = "V-INTCORE"; + }; + + ab8500_ldo_tvout_reg: ab8500_ldo_tvout { + regulator-name = "V-TVOUT"; + }; + + ab8500_ldo_usb_reg: ab8500_ldo_usb { + regulator-name = "dummy"; + }; + + ab8500_ldo_audio_reg: ab8500_ldo_audio { + regulator-name = "V-AUD"; + }; + + ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { + regulator-name = "V-AMIC1"; + }; + + ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { + regulator-name = "V-AMIC2"; + }; + + ab8500_ldo_dmic_reg: ab8500_ldo_dmic { + regulator-name = "V-DMIC"; + }; + + ab8500_ldo_ana_reg: ab8500_ldo_ana { + regulator-name = "V-CSI/DSI"; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts index 3fd83c6..2a85893 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -11,261 +11,9 @@ /dts-v1/; /include/ "dbx5x0.dtsi" +/include/ "href.dtsi" / { - model = "ST-Ericsson HREF platform with Device Tree"; + model = "ST-Ericsson HREF (v60+) platform with Device Tree"; compatible = "st-ericsson,hrefv60+"; - - memory { - reg = <0x00000000 0x20000000>; - }; - - soc-u9500 { - uart@80120000 { - status = "okay"; - }; - - uart@80121000 { - status = "okay"; - }; - - uart@80007000 { - status = "okay"; - }; - - i2c@80004000 { - tc3589x@42 { - compatible = "tc3589x"; - reg = <0x42>; - interrupt-parent = <&gpio6>; - interrupts = <25 0x1>; - - interrupt-controller; - #interrupt-cells = <2>; - - tc3589x_gpio: tc3589x_gpio { - compatible = "tc3589x-gpio"; - interrupts = <0 0x1>; - - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - tps61052@33 { - compatible = "tps61052"; - reg = <0x33>; - }; - }; - - i2c@80128000 { - lp5521@0x33 { - compatible = "lp5521"; - reg = <0x33>; - }; - - lp5521@0x34 { - compatible = "lp5521"; - reg = <0x34>; - }; - - bh1780@0x29 { - compatible = "rohm,bh1780gli"; - reg = <0x33>; - }; - }; - - // External Micro SD slot - sdi0_per1@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <4>; - mmc-cap-sd-highspeed; - mmc-cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux3_reg>; - - cd-gpios = <&tc3589x_gpio 3 0x4>; - - status = "okay"; - }; - - // WLAN SDIO channel - sdi1_per2@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <4>; - - status = "okay"; - }; - - // PoP:ed eMMC - sdi2_per3@80005000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <8>; - mmc-cap-mmc-highspeed; - - status = "okay"; - }; - - // On-board eMMC - sdi4_per2@80114000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <8>; - mmc-cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux2_reg>; - - status = "okay"; - }; - - sound { - compatible = "stericsson,snd-soc-mop500"; - - stericsson,cpu-dai = <&msp1 &msp3>; - stericsson,audio-codec = <&codec>; - }; - - msp1: msp@80124000 { - status = "okay"; - }; - - msp3: msp@80125000 { - status = "okay"; - }; - - prcmu@80157000 { - db8500-prcmu-regulators { - db8500_vape_reg: db8500_vape { - regulator-name = "db8500-vape"; - }; - - db8500_varm_reg: db8500_varm { - regulator-name = "db8500-varm"; - }; - - db8500_vmodem_reg: db8500_vmodem { - regulator-name = "db8500-vmodem"; - }; - - db8500_vpll_reg: db8500_vpll { - regulator-name = "db8500-vpll"; - }; - - db8500_vsmps1_reg: db8500_vsmps1 { - regulator-name = "db8500-vsmps1"; - }; - - db8500_vsmps2_reg: db8500_vsmps2 { - regulator-name = "db8500-vsmps2"; - }; - - db8500_vsmps3_reg: db8500_vsmps3 { - regulator-name = "db8500-vsmps3"; - }; - - db8500_vrf1_reg: db8500_vrf1 { - regulator-name = "db8500-vrf1"; - }; - - db8500_sva_mmdsp_reg: db8500_sva_mmdsp { - regulator-name = "db8500-sva-mmdsp"; - }; - - db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { - regulator-name = "db8500-sva-mmdsp-ret"; - }; - - db8500_sva_pipe_reg: db8500_sva_pipe { - regulator-name = "db8500_sva_pipe"; - }; - - db8500_sia_mmdsp_reg: db8500_sia_mmdsp { - regulator-name = "db8500_sia_mmdsp"; - }; - - db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { - regulator-name = "db8500-sia-mmdsp-ret"; - }; - - db8500_sia_pipe_reg: db8500_sia_pipe { - regulator-name = "db8500-sia-pipe"; - }; - - db8500_sga_reg: db8500_sga { - regulator-name = "db8500-sga"; - }; - - db8500_b2r2_mcde_reg: db8500_b2r2_mcde { - regulator-name = "db8500-b2r2-mcde"; - }; - - db8500_esram12_reg: db8500_esram12 { - regulator-name = "db8500-esram12"; - }; - - db8500_esram12_ret_reg: db8500_esram12_ret { - regulator-name = "db8500-esram12-ret"; - }; - - db8500_esram34_reg: db8500_esram34 { - regulator-name = "db8500-esram34"; - }; - - db8500_esram34_ret_reg: db8500_esram34_ret { - regulator-name = "db8500-esram34-ret"; - }; - }; - - ab8500@5 { - ab8500-regulators { - ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - regulator-name = "V-DISPLAY"; - }; - - ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { - regulator-name = "V-eMMC1"; - }; - - ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { - regulator-name = "V-MMC-SD"; - }; - - ab8500_ldo_initcore_reg: ab8500_ldo_initcore { - regulator-name = "V-INTCORE"; - }; - - ab8500_ldo_tvout_reg: ab8500_ldo_tvout { - regulator-name = "V-TVOUT"; - }; - - ab8500_ldo_usb_reg: ab8500_ldo_usb { - regulator-name = "dummy"; - }; - - ab8500_ldo_audio_reg: ab8500_ldo_audio { - regulator-name = "V-AUD"; - }; - - ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { - regulator-name = "V-AMIC1"; - }; - - ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { - regulator-name = "V-AMIC2"; - }; - - ab8500_ldo_dmic_reg: ab8500_ldo_dmic { - regulator-name = "V-DMIC"; - }; - - ab8500_ldo_ana_reg: ab8500_ldo_ana { - regulator-name = "V-CSI/DSI"; - }; - }; - }; - }; - }; }; -- cgit v0.10.2 From dd06fafffbd8c8267e5cf945ddc318045e7682db Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 26 Sep 2012 17:08:35 +0100 Subject: ARM: ux500: Create a Device Tree for early HREFs In ux500 platform code we currently support a number of devices. Two of these devices are fairly similar, but have key differences. Early (pre-v60) HREFs and the more up-to-date versions (v60+), and they both need to be supported by Device Tree. Here we apply a DT source file for the earlier versions. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts new file mode 100644 index 0000000..2dd28b9 --- /dev/null +++ b/arch/arm/boot/dts/hrefprev60.dts @@ -0,0 +1,28 @@ +/* + * Copyright 2012 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "dbx5x0.dtsi" +/include/ "href.dtsi" + +/ { + model = "ST-Ericsson HREF (pre-v60) platform with Device Tree"; + compatible = "st-ericsson,mop500"; + + soc-u9500 { + i2c@80004000 { + tps61052@33 { + compatible = "tps61052"; + reg = <0x33>; + }; + }; + }; +}; -- cgit v0.10.2 From 6b8db1326a67440e23f668f0e2b258e5e4127b82 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 26 Sep 2012 17:09:17 +0100 Subject: ARM: ux500: Add support for gpio-keys and Proximity Sensor for HREF Here we ensure the SFH7741 Proximity Sensor is registered through gpio-keys when booting with Device Tree enabled. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi index 27baa44..592fb9d 100644 --- a/arch/arm/boot/dts/href.dtsi +++ b/arch/arm/boot/dts/href.dtsi @@ -16,6 +16,17 @@ reg = <0x00000000 0x20000000>; }; + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + linux,code = <11>; + label = "SFH7741 Proximity Sensor"; + }; + }; + soc-u9500 { uart@80120000 { status = "okay"; diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts index 2dd28b9..0756f97 100644 --- a/arch/arm/boot/dts/hrefprev60.dts +++ b/arch/arm/boot/dts/hrefprev60.dts @@ -17,6 +17,12 @@ model = "ST-Ericsson HREF (pre-v60) platform with Device Tree"; compatible = "st-ericsson,mop500"; + gpio_keys { + button@1 { + gpios = <&tc3589x_gpio 7 0x4>; + }; + }; + soc-u9500 { i2c@80004000 { tps61052@33 { diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts index 2a85893..4b867b2 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -16,4 +16,10 @@ / { model = "ST-Ericsson HREF (v60+) platform with Device Tree"; compatible = "st-ericsson,hrefv60+"; + + gpio_keys { + button@1 { + gpios = <&gpio6 25 0x4>; + }; + }; }; -- cgit v0.10.2 From d6b22ebbbf1f71f9ebbc622c96bab93d554937e7 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 26 Sep 2012 16:02:45 +0100 Subject: ARM: ux500: Remove platform specific device registration when DT is enabled Most devices have now been successfully DT:ed and each supported platform has its own Device Tree source file. Hence the majority of the platform specific device registration calls can now be successfully removed. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index d141dd0..297bf55 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -775,8 +775,6 @@ static const struct of_device_id u8500_local_bus_nodes[] = { static void __init u8500_init_machine(void) { struct device *parent = NULL; - int i2c0_devs; - int i; /* Pinmaps must be in place before devices register */ if (of_machine_is_compatible("st-ericsson,mop500")) @@ -786,39 +784,12 @@ static void __init u8500_init_machine(void) else if (of_machine_is_compatible("st-ericsson,hrefv60+")) hrefv60_pinmaps_init(); + /* TODO: Export SoC, USB, cpu-freq and DMA40 */ parent = u8500_of_init_devices(); - for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) - mop500_platform_devs[i]->dev.parent = parent; - /* automatically probe child nodes of db8500 device */ of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent); - if (of_machine_is_compatible("st-ericsson,mop500")) { - mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; - - platform_add_devices(mop500_platform_devs, - ARRAY_SIZE(mop500_platform_devs)); - - mop500_audio_init(parent); - i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); - i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); - i2c_register_board_info(2, mop500_i2c2_devices, - ARRAY_SIZE(mop500_i2c2_devices)); - - } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { - mop500_of_audio_init(parent); - } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) { - /* - * The HREFv60 board removed a GPIO expander and routed - * all these GPIO pins to the internal GPIO controller - * instead. - */ - mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; - platform_add_devices(mop500_platform_devs, - ARRAY_SIZE(mop500_platform_devs)); - } - /* This board has full regulator constraints */ regulator_has_full_constraints(); } -- cgit v0.10.2 From fa86a76475f498961847c0511c153620463b76bd Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 27 Sep 2012 10:17:36 +0100 Subject: ARM: ux500: Move all Device Tree booting into cpu-db8500 To aid the kernel in its effort to move to DT only booting, we're transplanting all Device Tree related code to cpu-db8500 which will remain persistent throughout the transition. This change paths the way for complete removal of board-mop500, which will be done once the all DMA settings are moved into the respective DT source files. Acked-by: Arnd Bergmann Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 297bf55..daa4237 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -33,8 +33,6 @@ #include #include #include -#include -#include #include #include @@ -464,7 +462,7 @@ static struct stedma40_chan_cfg ssp0_dma_cfg_tx = { }; #endif -static struct pl022_ssp_controller ssp0_plat = { +struct pl022_ssp_controller ssp0_plat = { .bus_id = 0, #ifdef CONFIG_STE_DMA40 .enable_dma = 1, @@ -541,7 +539,7 @@ static struct stedma40_chan_cfg uart2_dma_cfg_tx = { }; #endif -static struct amba_pl011_data uart0_plat = { +struct amba_pl011_data uart0_plat = { #ifdef CONFIG_STE_DMA40 .dma_filter = stedma40_filter, .dma_rx_param = &uart0_dma_cfg_rx, @@ -549,7 +547,7 @@ static struct amba_pl011_data uart0_plat = { #endif }; -static struct amba_pl011_data uart1_plat = { +struct amba_pl011_data uart1_plat = { #ifdef CONFIG_STE_DMA40 .dma_filter = stedma40_filter, .dma_rx_param = &uart1_dma_cfg_rx, @@ -557,7 +555,7 @@ static struct amba_pl011_data uart1_plat = { #endif }; -static struct amba_pl011_data uart2_plat = { +struct amba_pl011_data uart2_plat = { #ifdef CONFIG_STE_DMA40 .dma_filter = stedma40_filter, .dma_rx_param = &uart2_dma_cfg_rx, @@ -719,99 +717,3 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform") .init_machine = snowball_init_machine, .init_late = NULL, MACHINE_END - -#ifdef CONFIG_MACH_UX500_DT - -struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { - /* Requires call-back bindings. */ - OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata), - /* Requires DMA and call-back bindings. */ - OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), - OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat), - OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat), - /* Requires DMA bindings. */ - OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), - OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), - OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data), - OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data), - OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data), - /* Requires clock name bindings. */ - OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL), - OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL), - OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL), - OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL), - OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL), - OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), - /* Requires device name bindings. */ - OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL), - /* Requires clock name and DMA bindings. */ - OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000, - "ux500-msp-i2s.0", &msp0_platform_data), - OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000, - "ux500-msp-i2s.1", &msp1_platform_data), - OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000, - "ux500-msp-i2s.2", &msp2_platform_data), - OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000, - "ux500-msp-i2s.3", &msp3_platform_data), - {}, -}; - -static const struct of_device_id u8500_local_bus_nodes[] = { - /* only create devices below soc node */ - { .compatible = "stericsson,db8500", }, - { .compatible = "stericsson,db8500-prcmu", }, - { .compatible = "simple-bus"}, - { }, -}; - -static void __init u8500_init_machine(void) -{ - struct device *parent = NULL; - - /* Pinmaps must be in place before devices register */ - if (of_machine_is_compatible("st-ericsson,mop500")) - mop500_pinmaps_init(); - else if (of_machine_is_compatible("calaosystems,snowball-a9500")) - snowball_pinmaps_init(); - else if (of_machine_is_compatible("st-ericsson,hrefv60+")) - hrefv60_pinmaps_init(); - - /* TODO: Export SoC, USB, cpu-freq and DMA40 */ - parent = u8500_of_init_devices(); - - /* automatically probe child nodes of db8500 device */ - of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent); - - /* This board has full regulator constraints */ - regulator_has_full_constraints(); -} - -static const char * u8500_dt_board_compat[] = { - "calaosystems,snowball-a9500", - "st-ericsson,hrefv60+", - "st-ericsson,u8500", - "st-ericsson,mop500", - NULL, -}; - - -DT_MACHINE_START(U8500_DT, "ST-Ericsson U8500 platform (Device Tree Support)") - .smp = smp_ops(ux500_smp_ops), - .map_io = u8500_map_io, - .init_irq = ux500_init_irq, - /* we re-use nomadik timer here */ - .timer = &ux500_timer, - .handle_irq = gic_handle_irq, - .init_machine = u8500_init_machine, - .init_late = ux500_init_late, - .dt_compat = u8500_dt_board_compat, -MACHINE_END -#endif diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index aca39a6..d772082 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -89,6 +89,10 @@ extern struct msp_i2s_platform_data msp1_platform_data; extern struct msp_i2s_platform_data msp2_platform_data; extern struct msp_i2s_platform_data msp3_platform_data; extern struct arm_pmu_platdata db8500_pmu_platdata; +extern struct amba_pl011_data uart0_plat; +extern struct amba_pl011_data uart1_plat; +extern struct amba_pl011_data uart2_plat; +extern struct pl022_ssp_controller ssp0_plat; extern void mop500_sdi_init(struct device *parent); extern void snowball_sdi_init(struct device *parent); @@ -106,8 +110,4 @@ void mop500_of_audio_init(struct device *parent); int __init mop500_uib_init(void); void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, unsigned n); - -/* TODO: Once all pieces are DT:ed, remove completely. */ -struct device * __init u8500_of_init_devices(void); - #endif diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index bcdfe6b..25e1e32 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -17,9 +17,14 @@ #include #include #include +#include +#include +#include #include #include +#include +#include #include #include #include @@ -29,6 +34,7 @@ #include "devices-db8500.h" #include "ste-dma40-db8500.h" +#include "board-mop500.h" /* minimum static i/o mapping required to boot U8500 platforms */ static struct map_desc u8500_uart_io_desc[] __initdata = { @@ -227,12 +233,12 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500) return parent; } +#ifdef CONFIG_MACH_UX500_DT + /* TODO: Once all pieces are DT:ed, remove completely. */ -struct device * __init u8500_of_init_devices(void) +static struct device * __init u8500_of_init_devices(void) { - struct device *parent; - - parent = db8500_soc_device_init(); + struct device *parent = db8500_soc_device_init(); db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); @@ -251,3 +257,96 @@ struct device * __init u8500_of_init_devices(void) return parent; } + +static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { + /* Requires call-back bindings. */ + OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata), + /* Requires DMA and call-back bindings. */ + OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), + OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat), + OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat), + /* Requires DMA bindings. */ + OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), + OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), + OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data), + OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data), + OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data), + /* Requires clock name bindings. */ + OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL), + OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL), + OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL), + OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL), + OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL), + OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL), + OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL), + OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL), + OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), + /* Requires device name bindings. */ + OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL), + /* Requires clock name and DMA bindings. */ + OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000, + "ux500-msp-i2s.0", &msp0_platform_data), + OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000, + "ux500-msp-i2s.1", &msp1_platform_data), + OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000, + "ux500-msp-i2s.2", &msp2_platform_data), + OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000, + "ux500-msp-i2s.3", &msp3_platform_data), + {}, +}; + +static const struct of_device_id u8500_local_bus_nodes[] = { + /* only create devices below soc node */ + { .compatible = "stericsson,db8500", }, + { .compatible = "stericsson,db8500-prcmu", }, + { .compatible = "simple-bus"}, + { }, +}; + +static void __init u8500_init_machine(void) +{ + struct device *parent = NULL; + + /* Pinmaps must be in place before devices register */ + if (of_machine_is_compatible("st-ericsson,mop500")) + mop500_pinmaps_init(); + else if (of_machine_is_compatible("calaosystems,snowball-a9500")) + snowball_pinmaps_init(); + else if (of_machine_is_compatible("st-ericsson,hrefv60+")) + hrefv60_pinmaps_init(); + + /* TODO: Export SoC, USB, cpu-freq and DMA40 */ + parent = u8500_of_init_devices(); + + /* automatically probe child nodes of db8500 device */ + of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent); + + /* This board has full regulator constraints */ + regulator_has_full_constraints(); +} + +static const char * u8500_dt_board_compat[] = { + "calaosystems,snowball-a9500", + "st-ericsson,hrefv60+", + "st-ericsson,u8500", + "st-ericsson,mop500", + NULL, +}; + +DT_MACHINE_START(U8500_DT, "ST-Ericsson U8500 platform (Device Tree Support)") + .map_io = u8500_map_io, + .init_irq = ux500_init_irq, + /* we re-use nomadik timer here */ + .timer = &ux500_timer, + .handle_irq = gic_handle_irq, + .init_machine = u8500_init_machine, + .init_late = ux500_init_late, + .dt_compat = u8500_dt_board_compat, +MACHINE_END + +#endif -- cgit v0.10.2 From ab196b4138fb9b3e6908c85eb4bf412d2a6753cd Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 27 Sep 2012 11:47:43 +0100 Subject: ARM: ux500: Strip out duplicate touch screen platform information We're currently carrying two 'struct bu21013_platform_device's which are identical for no apparent reason. Here we remove the extra burden and apply the same information to the two different instances of the bu21012_tp driver registration. Acked-by: Arnd Bergmann Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/board-mop500-stuib.c b/arch/arm/mach-ux500/board-mop500-stuib.c index 8c97977..564f57d 100644 --- a/arch/arm/mach-ux500/board-mop500-stuib.c +++ b/arch/arm/mach-ux500/board-mop500-stuib.c @@ -162,18 +162,6 @@ static struct bu21013_platform_device tsc_plat_device = { .y_flip = true, }; -static struct bu21013_platform_device tsc_plat2_device = { - .cs_en = bu21013_gpio_board_init, - .cs_dis = bu21013_gpio_board_exit, - .irq_read_val = bu21013_read_pin_val, - .irq = NOMADIK_GPIO_TO_IRQ(TOUCH_GPIO_PIN), - .touch_x_max = TOUCH_XMAX, - .touch_y_max = TOUCH_YMAX, - .ext_clk = false, - .x_flip = false, - .y_flip = true, -}; - static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = { { I2C_BOARD_INFO("bu21013_tp", 0x5C), @@ -181,21 +169,17 @@ static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = { }, { I2C_BOARD_INFO("bu21013_tp", 0x5D), - .platform_data = &tsc_plat2_device, + .platform_data = &tsc_plat_device, }, }; void __init mop500_stuib_init(void) { - if (machine_is_hrefv60()) { + if (machine_is_hrefv60()) tsc_plat_device.cs_pin = HREFV60_TOUCH_RST_GPIO; - tsc_plat2_device.cs_pin = HREFV60_TOUCH_RST_GPIO; - } else { + else tsc_plat_device.cs_pin = GPIO_BU21013_CS; - tsc_plat2_device.cs_pin = GPIO_BU21013_CS; - - } mop500_uib_i2c_add(0, mop500_i2c0_devices_stuib, ARRAY_SIZE(mop500_i2c0_devices_stuib)); -- cgit v0.10.2 From fb647002e4b6393a1f552b2fe48ba88c50d1d6e4 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 28 Sep 2012 15:24:40 +0100 Subject: Documentation: Detail permitted DT properties for the BU21013 Touch Screen Here we apply required documentation for the Rohm BU21013 Touch Screen driver which describe available properties and how to use them. Cc: Dmitry Torokhov Cc: linux-input@vger.kernel.org Cc: devicetree-discuss@lists.ozlabs.org Acked-by: Arnd Bergmann Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt b/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt new file mode 100644 index 0000000..ca5a2c8 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt @@ -0,0 +1,28 @@ +* Rohm BU21013 Touch Screen + +Required properties: + - compatible : "rohm,bu21013_tp" + - reg : I2C device address + +Optional properties: + - touch-gpio : GPIO pin registering a touch event + - -supply : Phandle to a regulator supply + - rohm,touch-max-x : Maximum outward permitted limit in the X axis + - rohm,touch-max-y : Maximum outward permitted limit in the Y axis + - rohm,flip-x : Flip touch coordinates on the X axis + - rohm,flip-y : Flip touch coordinates on the Y axis + +Example: + + i2c@80110000 { + bu21013_tp@0x5c { + compatible = "rohm,bu21013_tp"; + reg = <0x5c>; + touch-gpio = <&gpio2 20 0x4>; + avdd-supply = <&ab8500_ldo_aux1_reg>; + + rohm,touch-max-x = <384>; + rohm,touch-max-y = <704>; + rohm,flip-y; + }; + }; -- cgit v0.10.2 From 6934e00465b3ec1cdfe0078fd3c42d41d6b2b531 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 28 Sep 2012 14:06:29 +0100 Subject: ARM: ux500: Create a new Device Tree include file for boards supporting STUIBs This is a skeleton creation which will be populated with the devices found on one of ST-Ericsson's (UIB) User Interface Board. Acked-by: Arnd Bergmann Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts index 0756f97..e112cce 100644 --- a/arch/arm/boot/dts/hrefprev60.dts +++ b/arch/arm/boot/dts/hrefprev60.dts @@ -12,6 +12,7 @@ /dts-v1/; /include/ "dbx5x0.dtsi" /include/ "href.dtsi" +/include/ "stuib.dtsi" / { model = "ST-Ericsson HREF (pre-v60) platform with Device Tree"; diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts index 4b867b2..b5fc355 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -12,6 +12,7 @@ /dts-v1/; /include/ "dbx5x0.dtsi" /include/ "href.dtsi" +/include/ "stuib.dtsi" / { model = "ST-Ericsson HREF (v60+) platform with Device Tree"; diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi new file mode 100644 index 0000000..64ac327 --- /dev/null +++ b/arch/arm/boot/dts/stuib.dtsi @@ -0,0 +1,15 @@ +/* + * Copyright 2012 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/ { + soc-u9500 { + }; +}; -- cgit v0.10.2 From 74a1c9ab87a98f3e2e5e62cfaf949eab012477af Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 28 Sep 2012 14:20:03 +0100 Subject: ARM: ux500: Stop calling the UIB init function when using Device Tree As there will be a Device Tree created for the UIBs, there is no need to call the UIB initiation functions. Each device will be detailed and registered from the Device Tree instead. Acked-by: Arnd Bergmann Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 25e1e32..ca792d0 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -345,7 +345,7 @@ DT_MACHINE_START(U8500_DT, "ST-Ericsson U8500 platform (Device Tree Support)") .timer = &ux500_timer, .handle_irq = gic_handle_irq, .init_machine = u8500_init_machine, - .init_late = ux500_init_late, + .init_late = NULL, .dt_compat = u8500_dt_board_compat, MACHINE_END -- cgit v0.10.2 From cbebba7d8640105d9caf197c1f31d3360db4e1c7 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 28 Sep 2012 14:41:06 +0100 Subject: ARM: ux500: Add all bu21013 touch screen components to supported Device Trees It is possible to connect a BU21013 Touch Screen to all version of the HREF which support the ST-UIB. This patch applies all the necessary settings to the pre-v60 and v60+ HREF Device Trees. Acked-by: Arnd Bergmann Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts index e112cce..cd9e535 100644 --- a/arch/arm/boot/dts/hrefprev60.dts +++ b/arch/arm/boot/dts/hrefprev60.dts @@ -31,5 +31,11 @@ reg = <0x33>; }; }; + + i2c@80110000 { + bu21013_tp@0x5c { + reset-gpio = <&tc3589x_gpio 13 0x4>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts index b5fc355..82103a2 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -23,4 +23,12 @@ gpios = <&gpio6 25 0x4>; }; }; + + soc-u9500 { + i2c@80110000 { + bu21013_tp@0x5c { + reset-gpio = <&gpio4 15 0x4>; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi index 64ac327..62f3ecd 100644 --- a/arch/arm/boot/dts/stuib.dtsi +++ b/arch/arm/boot/dts/stuib.dtsi @@ -11,5 +11,28 @@ / { soc-u9500 { + i2c@80110000 { + bu21013_tp@0x5c { + compatible = "rhom,bu21013_tp"; + reg = <0x5c>; + touch-gpio = <&gpio2 20 0x4>; + avdd-supply = <&ab8500_ldo_aux1_reg>; + + rhom,touch-max-x = <384>; + rhom,touch-max-y = <704>; + rhom,flip-y; + }; + + bu21013_tp@0x5d { + compatible = "rhom,bu21013_tp"; + reg = <0x5d>; + touch-gpio = <&gpio2 20 0x4>; + avdd-supply = <&ab8500_ldo_aux1_reg>; + + rhom,touch-max-x = <384>; + rhom,touch-max-y = <704>; + rhom,flip-y; + }; + }; }; }; -- cgit v0.10.2 From 65c7733bcf8c7d2660f6f4d0fef06aa636a69efe Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 28 Sep 2012 14:45:12 +0100 Subject: ARM: ux500: Stop informing the regulator subsystem that we have full constraints The regulator_has_full_constraints() call is not required if we are booting with Device Tree as it's assumed in this case. Acked-by: Arnd Bergmann Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index ca792d0..776c50b 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -325,9 +325,6 @@ static void __init u8500_init_machine(void) /* automatically probe child nodes of db8500 device */ of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent); - - /* This board has full regulator constraints */ - regulator_has_full_constraints(); } static const char * u8500_dt_board_compat[] = { -- cgit v0.10.2 From cb5527035d384d7fdead83adf00833d734c282ce Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 4 Oct 2012 12:41:35 +0100 Subject: ARM: ux500: Apply a Device Tree node for the STMPE MFD Here we apply the STMPE Multi-Functional Device's node to the ST User Interface Board Device Tree file. It includes all of the properties required for correct device initialsation. Acked-by: Arnd Bergmann Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi index 62f3ecd..d6e36b5 100644 --- a/arch/arm/boot/dts/stuib.dtsi +++ b/arch/arm/boot/dts/stuib.dtsi @@ -11,6 +11,19 @@ / { soc-u9500 { + i2c@80004000 { + stmpe1601: stmpe1601@40 { + compatible = "st,stmpe1601"; + reg = <0x40>; + interrupts = <26 0x4>; + interrupt-parent = <&gpio6>; + interrupt-controller; + + wakeup-source; + st,autosleep-timeout = <1024>; + }; + }; + i2c@80110000 { bu21013_tp@0x5c { compatible = "rhom,bu21013_tp"; -- cgit v0.10.2 From 092778190d693a10d2d364b5e99f5deca903fe41 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 4 Oct 2012 14:21:35 +0100 Subject: ARM: ux500: Supply the STMPE keypad Device Tree node to the STUIB DT This patch allows the STMPE keypad driver to be successfully probed and initialised during a Device Tree enabled boot sequence. It contains all of the required properties needed to setup and map each key on the 6x3 keypad located on the ST User Interface Board. Acked-by: Arnd Bergmann Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi index d6e36b5..6c7e492 100644 --- a/arch/arm/boot/dts/stuib.dtsi +++ b/arch/arm/boot/dts/stuib.dtsi @@ -21,6 +21,33 @@ wakeup-source; st,autosleep-timeout = <1024>; + + stmpe_keypad { + compatible = "st,stmpe-keypad"; + + debounce-interval = <64>; + st,scan-count = <8>; + st,no-autorepeat; + + linux,keymap = <0x205006b + 0x4010074 + 0x3050072 + 0x1030004 + 0x502006a + 0x500000a + 0x5008b + 0x706001c + 0x405000b + 0x6070003 + 0x3040067 + 0x303006c + 0x60400e7 + 0x602009e + 0x4020073 + 0x5050002 + 0x4030069 + 0x3020008>; + }; }; }; -- cgit v0.10.2 From f91243e0f086c618313dfdece1648ae4ed259a1c Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 8 Oct 2012 14:34:52 +0100 Subject: ARM: ux500: Remove unused board compatible string 'st-ericsson,u8500' is too much of a broad name to be used for any of the supported development boards supported by ST-Ericsson. As such it was never used. It has no place to remain in the board compatible list, hence why it's being removed. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 776c50b..4fd6b7c 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -330,7 +330,6 @@ static void __init u8500_init_machine(void) static const char * u8500_dt_board_compat[] = { "calaosystems,snowball-a9500", "st-ericsson,hrefv60+", - "st-ericsson,u8500", "st-ericsson,mop500", NULL, }; -- cgit v0.10.2 From fd053c7dbdb412628a135c19d2c793c8e0af6c1a Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 8 Oct 2012 09:14:13 +0100 Subject: ARM: ux500: Add skeleton DTS file for the u9540 This patch sees the creation of a sparse Device Tree file for ST-Ericsson's latest development board supporting the latest dual-core Cortex-a9 u9540 SoC. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/u9540.dts b/arch/arm/boot/dts/u9540.dts new file mode 100644 index 0000000..0a66f34 --- /dev/null +++ b/arch/arm/boot/dts/u9540.dts @@ -0,0 +1,26 @@ +/* + * Copyright 2012 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "dbx5x0.dtsi" + +/ { + model = "ST-Ericsson U9540 platform with Device Tree"; + compatible = "st-ericsson,u9540"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + soc-u9500 { + }; + +}; -- cgit v0.10.2 From 661c6af0a5823870c986ab0c387b8ab8543edbd3 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 8 Oct 2012 14:20:10 +0100 Subject: ARM: ux500: Add support for ST-Ericsson's u9540 SoC First level board support for the u9540. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 4fd6b7c..0b15591 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -319,6 +320,8 @@ static void __init u8500_init_machine(void) snowball_pinmaps_init(); else if (of_machine_is_compatible("st-ericsson,hrefv60+")) hrefv60_pinmaps_init(); + else if (of_machine_is_compatible("st-ericsson,u9540")) {} + /* TODO: Add u9540 pinmaps. */ /* TODO: Export SoC, USB, cpu-freq and DMA40 */ parent = u8500_of_init_devices(); @@ -331,6 +334,7 @@ static const char * u8500_dt_board_compat[] = { "calaosystems,snowball-a9500", "st-ericsson,hrefv60+", "st-ericsson,mop500", + "st-ericsson,u9540", NULL, }; @@ -345,4 +349,14 @@ DT_MACHINE_START(U8500_DT, "ST-Ericsson U8500 platform (Device Tree Support)") .dt_compat = u8500_dt_board_compat, MACHINE_END +DT_MACHINE_START(U9540_DT, "ST-Ericsson 9540 platform (Device Tree Support)") + .map_io = u8500_map_io, + .init_irq = ux500_init_irq, + .timer = &ux500_timer, + .handle_irq = gic_handle_irq, + .init_machine = u8500_init_machine, + .init_late = NULL, + .dt_compat = u8500_dt_board_compat, +MACHINE_END + #endif -- cgit v0.10.2 From d6fea1e03e0531fb55d4fc590ee136c17fcd139c Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 8 Oct 2012 09:19:31 +0100 Subject: ARM: ux500: Add UART support to the u9540 Device Tree Add the 3 UART nodes required to enable serial ports on the u9540. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/u9540.dts b/arch/arm/boot/dts/u9540.dts index 0a66f34..28efe20 100644 --- a/arch/arm/boot/dts/u9540.dts +++ b/arch/arm/boot/dts/u9540.dts @@ -21,6 +21,17 @@ }; soc-u9500 { - }; + uart@80120000 { + status = "okay"; + }; + + uart@80121000 { + status = "okay"; + }; + + uart@80007000 { + status = "okay"; + }; + }; }; -- cgit v0.10.2 From 457da8539980344355e7c2b06f4a82b33ce4a26d Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 8 Oct 2012 14:09:05 +0100 Subject: ARM: ux500: Enable SDI4 port on the u9540 when booting with Device Tree Here we add the device node for the SDI4 (MMC) port to the u9540 Device Tree source file. This will allow successful probing of the internal MMC storage device when booting with DT enabled. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/u9540.dts b/arch/arm/boot/dts/u9540.dts index 28efe20..2dade76 100644 --- a/arch/arm/boot/dts/u9540.dts +++ b/arch/arm/boot/dts/u9540.dts @@ -21,7 +21,6 @@ }; soc-u9500 { - uart@80120000 { status = "okay"; }; @@ -33,5 +32,16 @@ uart@80007000 { status = "okay"; }; + + // On-board eMMC + sdi4_per2@80114000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <8>; + mmc-cap-mmc-highspeed; + vmmc-supply = <&ab8500_ldo_aux2_reg>; + + status = "okay"; + }; }; }; -- cgit v0.10.2 From a37e84ca31f4354373fe9a930d80566d6833a877 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 10 Oct 2012 09:38:26 +0100 Subject: ARM: ux500: Enable all MMC devices on the u9540 when booting with DT The u9540 supports 3 MMC devices. This patch enables two of them and updates the configuration of the already enabled SDI4 port. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/u9540.dts b/arch/arm/boot/dts/u9540.dts index 2dade76..95892ec 100644 --- a/arch/arm/boot/dts/u9540.dts +++ b/arch/arm/boot/dts/u9540.dts @@ -33,10 +33,35 @@ status = "okay"; }; + // External Micro SD slot + sdi0_per1@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + mmc-cap-sd-highspeed; + mmc-cap-mmc-highspeed; + vmmc-supply = <&ab8500_ldo_aux3_reg>; + + cd-gpios = <&gpio7 6 0x4>; // 230 + cd-inverted; + + status = "okay"; + }; + + + // WLAN SDIO channel + sdi1_per2@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + + status = "okay"; + }; + // On-board eMMC sdi4_per2@80114000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; + max-frequency = <100000000>; bus-width = <8>; mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux2_reg>; -- cgit v0.10.2 From 58e5b9e3d0b5e1319fd24124e79b4d4e6188bf1b Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 15 Oct 2012 08:49:33 +0100 Subject: ARM: ux500: Rename references to the ccu9540 dev board accordingly When enabling ST-Ericsson's ccu9540 development board the board's full name has not been used. This patch adapts all references of the board's short name to how it should be referenced. Reviewed-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/ccu9540.dts b/arch/arm/boot/dts/ccu9540.dts new file mode 100644 index 0000000..26dfe83 --- /dev/null +++ b/arch/arm/boot/dts/ccu9540.dts @@ -0,0 +1,72 @@ +/* + * Copyright 2012 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "dbx5x0.dtsi" + +/ { + model = "ST-Ericsson CCU9540 platform with Device Tree"; + compatible = "st-ericsson,ccu9540"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + soc-u9500 { + uart@80120000 { + status = "okay"; + }; + + uart@80121000 { + status = "okay"; + }; + + uart@80007000 { + status = "okay"; + }; + + // External Micro SD slot + sdi0_per1@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + mmc-cap-sd-highspeed; + mmc-cap-mmc-highspeed; + vmmc-supply = <&ab8500_ldo_aux3_reg>; + + cd-gpios = <&gpio7 6 0x4>; // 230 + cd-inverted; + + status = "okay"; + }; + + + // WLAN SDIO channel + sdi1_per2@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + + status = "okay"; + }; + + // On-board eMMC + sdi4_per2@80114000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + mmc-cap-mmc-highspeed; + vmmc-supply = <&ab8500_ldo_aux2_reg>; + + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/u9540.dts b/arch/arm/boot/dts/u9540.dts deleted file mode 100644 index 95892ec..0000000 --- a/arch/arm/boot/dts/u9540.dts +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "dbx5x0.dtsi" - -/ { - model = "ST-Ericsson U9540 platform with Device Tree"; - compatible = "st-ericsson,u9540"; - - memory { - reg = <0x00000000 0x20000000>; - }; - - soc-u9500 { - uart@80120000 { - status = "okay"; - }; - - uart@80121000 { - status = "okay"; - }; - - uart@80007000 { - status = "okay"; - }; - - // External Micro SD slot - sdi0_per1@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - mmc-cap-sd-highspeed; - mmc-cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux3_reg>; - - cd-gpios = <&gpio7 6 0x4>; // 230 - cd-inverted; - - status = "okay"; - }; - - - // WLAN SDIO channel - sdi1_per2@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <4>; - - status = "okay"; - }; - - // On-board eMMC - sdi4_per2@80114000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - mmc-cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux2_reg>; - - status = "okay"; - }; - }; -}; diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 0b15591..6e9a06d 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -320,8 +320,8 @@ static void __init u8500_init_machine(void) snowball_pinmaps_init(); else if (of_machine_is_compatible("st-ericsson,hrefv60+")) hrefv60_pinmaps_init(); - else if (of_machine_is_compatible("st-ericsson,u9540")) {} - /* TODO: Add u9540 pinmaps. */ + else if (of_machine_is_compatible("st-ericsson,ccu9540")) {} + /* TODO: Add pinmaps for ccu9540 board. */ /* TODO: Export SoC, USB, cpu-freq and DMA40 */ parent = u8500_of_init_devices(); @@ -334,7 +334,7 @@ static const char * u8500_dt_board_compat[] = { "calaosystems,snowball-a9500", "st-ericsson,hrefv60+", "st-ericsson,mop500", - "st-ericsson,u9540", + "st-ericsson,ccu9540", NULL, }; -- cgit v0.10.2 From 46c1bf813376654f6b75120b9c2cf3de0f67af7d Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 15 Oct 2012 08:55:17 +0100 Subject: ARM: ux500: Remove duplicate DT_MACHINE_START - make u8500 for generic The u8500 and u9540 DT_MACHINE_START calls are almost identical at the moment, referencing exactly the same function pointers. Until this changes we may as well convert the original one to be more generic and use that instead. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 6e9a06d..472b49f 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -338,7 +338,7 @@ static const char * u8500_dt_board_compat[] = { NULL, }; -DT_MACHINE_START(U8500_DT, "ST-Ericsson U8500 platform (Device Tree Support)") +DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)") .map_io = u8500_map_io, .init_irq = ux500_init_irq, /* we re-use nomadik timer here */ @@ -349,14 +349,4 @@ DT_MACHINE_START(U8500_DT, "ST-Ericsson U8500 platform (Device Tree Support)") .dt_compat = u8500_dt_board_compat, MACHINE_END -DT_MACHINE_START(U9540_DT, "ST-Ericsson 9540 platform (Device Tree Support)") - .map_io = u8500_map_io, - .init_irq = ux500_init_irq, - .timer = &ux500_timer, - .handle_irq = gic_handle_irq, - .init_machine = u8500_init_machine, - .init_late = NULL, - .dt_compat = u8500_dt_board_compat, -MACHINE_END - #endif -- cgit v0.10.2 From 79b40753a318adb3254c6d534b834c10f99cba05 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 15 Oct 2012 10:07:55 +0100 Subject: ARM: ux500: List DT compatibility using platform names rather than by board So far, each ST-Ericsson board supported by Device Tree has been similar enough to run though a single DT_MACHINE_INIT call. On the back of that it has been suggested that we should reduce the number of compatible strings in our dt_compat structure. After subsequent discussion with Arnd Bergmann the conclusion was to list entries by platform as opposed to by board. The other suggestion was to use a single string which would cover all supported platforms, but any wildcard entries would include unsupported chipsets, such as the u5500 and potential new chips which no not yet have DT functionality. Hence, the best solution which encompasses all supported platforms, but no unsupported ones was to list the currently enabled four chipsets; u8500, u8540, u9500 and u9540 instead. Acked-by: Arnd Bergmann Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/ccu9540.dts b/arch/arm/boot/dts/ccu9540.dts index 26dfe83..0430546 100644 --- a/arch/arm/boot/dts/ccu9540.dts +++ b/arch/arm/boot/dts/ccu9540.dts @@ -14,7 +14,7 @@ / { model = "ST-Ericsson CCU9540 platform with Device Tree"; - compatible = "st-ericsson,ccu9540"; + compatible = "st-ericsson,ccu9540", "st-ericsson,u9540"; memory { reg = <0x00000000 0x20000000>; diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts index cd9e535..b398946 100644 --- a/arch/arm/boot/dts/hrefprev60.dts +++ b/arch/arm/boot/dts/hrefprev60.dts @@ -16,7 +16,7 @@ / { model = "ST-Ericsson HREF (pre-v60) platform with Device Tree"; - compatible = "st-ericsson,mop500"; + compatible = "st-ericsson,mop500", "st-ericsson,u8500"; gpio_keys { button@1 { diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts index 82103a2..a01ac8f 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -16,7 +16,7 @@ / { model = "ST-Ericsson HREF (v60+) platform with Device Tree"; - compatible = "st-ericsson,hrefv60+"; + compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; gpio_keys { button@1 { diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index 6a2b58b..9e02a91 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts @@ -14,7 +14,7 @@ / { model = "Calao Systems Snowball platform with device tree"; - compatible = "calaosystems,snowball-a9500"; + compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500"; memory { reg = <0x00000000 0x20000000>; diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 472b49f..c65e7e3 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -330,11 +330,11 @@ static void __init u8500_init_machine(void) of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent); } -static const char * u8500_dt_board_compat[] = { - "calaosystems,snowball-a9500", - "st-ericsson,hrefv60+", - "st-ericsson,mop500", - "st-ericsson,ccu9540", +static const char * stericsson_dt_platform_compat[] = { + "st-ericsson,u8500", + "st-ericsson,u8540", + "st-ericsson,u9500", + "st-ericsson,u9540", NULL, }; @@ -346,7 +346,7 @@ DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)") .handle_irq = gic_handle_irq, .init_machine = u8500_init_machine, .init_late = NULL, - .dt_compat = u8500_dt_board_compat, + .dt_compat = stericsson_dt_platform_compat, MACHINE_END #endif -- cgit v0.10.2 From 0563f638f052185ea45441b5e7ec06a90e4e7837 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 24 Oct 2012 11:18:14 +0100 Subject: ARM: ux500: Add node for the MMC GPIO regulator There is a very simple mechanism to change and SDI's voltage which consists of toggling some GPIOs. This scenario can be better handled if we convert it to a GPIO regulator. This patch provides one which can be read from Device Tree. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index 3b4298b..7ce45fc 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -629,5 +629,19 @@ ranges = <0 0x50000000 0x4000000>; status = "disabled"; }; + + vmmci: regulator-gpio { + compatible = "regulator-gpio"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2600000>; + regulator-name = "mmci-reg"; + regulator-type = "voltage"; + + gpios = <&tc3589x_gpio 18 0x4>; + gpio-enable = <&tc3589x_gpio 17 0x4>; + states = <1800000 0x1 + 2900000 0x0>; + }; }; }; -- cgit v0.10.2 From 98c52c7c676b047e67c235616cc3fefad05c04d4 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 24 Oct 2012 11:21:35 +0100 Subject: ARM: ux500: Change the type of interrupt to something compatible On boot the Nomadik GPIO controller complains that an IRQ can't be configured as active high level-sensitive, so this patch converts it to be low-to-high edge triggered instead. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi index 6c7e492..39446a2 100644 --- a/arch/arm/boot/dts/stuib.dtsi +++ b/arch/arm/boot/dts/stuib.dtsi @@ -15,7 +15,7 @@ stmpe1601: stmpe1601@40 { compatible = "st,stmpe1601"; reg = <0x40>; - interrupts = <26 0x4>; + interrupts = <26 0x1>; interrupt-parent = <&gpio6>; interrupt-controller; -- cgit v0.10.2 From 5c6cfcf5542b64dbc4f224a3575e231848f40c5f Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 24 Oct 2012 12:01:41 +0100 Subject: ARM: ux500: CONFIG: Enable GPIO Regulators It is the intention to convert the MMC voltage changing from GPIO flipping to using a proper GPIO regulator interface. A prerequisite of that is to enable the GPIO regulator functionality. As this affects all ux5x0 based boards we'll do it here instead of in the Kconfigs. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index da68454..6fe7ede 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig @@ -76,6 +76,7 @@ CONFIG_AB8500_CORE=y CONFIG_REGULATOR=y CONFIG_REGULATOR_AB8500=y CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y # CONFIG_HID_SUPPORT is not set CONFIG_USB_GADGET=y CONFIG_AB8500_USB=y -- cgit v0.10.2 From f44c5fd12d8152e45585905422d03427754e1907 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 24 Oct 2012 11:24:47 +0100 Subject: ARM: ux500: Convert DT_MACHINE_START to use SMP operations The Device Tree machine description for the ux5x0 was moved recently and as a consequence missed the addition of SMP operations. Without this patch SMP doesn't work and only one CPU is present after booting. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index c65e7e3..4a0c40a 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -339,6 +339,7 @@ static const char * stericsson_dt_platform_compat[] = { }; DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)") + .smp = smp_ops(ux500_smp_ops), .map_io = u8500_map_io, .init_irq = ux500_init_irq, /* we re-use nomadik timer here */ -- cgit v0.10.2 From db7a8946dc40eee55222bf76d9c0b66a72af4ca0 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 31 Oct 2012 11:30:10 +0100 Subject: ARM: dts: cfa10049: Add the DH2228FV DAC to the DTS There is no driver for it yet, so it will use spidev. Signed-off-by: Maxime Ripard Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index a34676f..5549c6c 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -29,6 +29,7 @@ 0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */ 0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */ 0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */ + 0x01b2 /* MX28_PAD_GPMI_CLE__SSP3_D5 */ >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -60,6 +61,11 @@ spi-max-frequency = <100000>; }; + dac0: dh2228@2 { + compatible = "rohm,dh2228fv"; + reg = <2>; + spi-max-frequency = <100000>; + }; }; }; -- cgit v0.10.2 From 4ced2a40baaabc7afea7c504d222401f013f39b1 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Thu, 1 Nov 2012 17:50:59 +0100 Subject: ARM: dts: mxs: Add 16 bits LCD screen muxing options for I.MX28 Signed-off-by: Julien Boibessot Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 2b607aa..8e2c8b2 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -544,6 +544,31 @@ fsl,pull-up = <0>; }; + lcdif_16bit_pins_a: lcdif-16bit@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ + 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ + 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ + 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ + 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ + 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ + 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ + 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ + 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ + 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ + 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ + 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ + 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ + 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ + 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ + 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + can0_pins_a: can0@0 { reg = <0>; fsl,pinmux-ids = < -- cgit v0.10.2 From 24acd6bf1d18636344e7f58a69294c2ce7c10a9e Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Fri, 2 Nov 2012 19:01:47 +0100 Subject: ARM: mxs: apf28dev: Add pinctrl and gpios Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Julien Boibessot Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts index dde09d4..8e765ae 100644 --- a/arch/arm/boot/dts/imx28-apf28dev.dts +++ b/arch/arm/boot/dts/imx28-apf28dev.dts @@ -26,6 +26,27 @@ bus-width = <4>; status = "okay"; }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_apf28dev>; + + hog_pins_apf28dev: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1103 /* MX28_PAD_LCD_D16__GPIO_1_16 */ + 0x1113 /* MX28_PAD_LCD_D17__GPIO_1_17 */ + 0x1123 /* MX28_PAD_LCD_D18__GPIO_1_18 */ + 0x1133 /* MX28_PAD_LCD_D19__GPIO_1_19 */ + 0x1143 /* MX28_PAD_LCD_D20__GPIO_1_20 */ + 0x1153 /* MX28_PAD_LCD_D21__GPIO_1_21 */ + 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; }; apbx@80040000 { -- cgit v0.10.2 From a4dabca8b474aa5cf7ec1bec5bc1904a5e18f642 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Fri, 2 Nov 2012 19:01:48 +0100 Subject: ARM: mxs: apf28dev: Add LCD and backlight support Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Julien Boibessot Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts index 8e765ae..1643d25 100644 --- a/arch/arm/boot/dts/imx28-apf28dev.dts +++ b/arch/arm/boot/dts/imx28-apf28dev.dts @@ -46,6 +46,26 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; + + lcdif_pins_apf28dev: lcdif-apf28dev@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + + lcdif@80030000 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_16bit_pins_a + &lcdif_pins_apf28dev>; + status = "okay"; }; }; @@ -110,4 +130,12 @@ linux,default-trigger = "heartbeat"; }; }; + + backlight { + compatible = "pwm-backlight"; + + pwms = <&pwm 3 191000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; }; diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 48c2eba..67ef355 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -100,6 +100,25 @@ static struct fb_videomode apx4devkit_video_modes[] = { }, }; +static struct fb_videomode apf28dev_video_modes[] = { + { + .name = "LW700", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 30303, /* picosecond */ + .left_margin = 96, + .right_margin = 96, /* at least 3 & 1 */ + .upper_margin = 0x14, + .lower_margin = 0x15, + .hsync_len = 64, + .vsync_len = 4, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | + FB_SYNC_DATA_ENABLE_HIGH_ACT | + FB_SYNC_DOTCLK_FAILING_ACT, + }, +}; + static struct mxsfb_platform_data mxsfb_pdata __initdata; /* @@ -374,6 +393,11 @@ static void __init cfa10049_init(void) static void __init apf28_init(void) { enable_clk_enet_out(); + + mxsfb_pdata.mode_list = apf28dev_video_modes; + mxsfb_pdata.mode_count = ARRAY_SIZE(apf28dev_video_modes); + mxsfb_pdata.default_bpp = 16; + mxsfb_pdata.ld_intf_width = STMLCDIF_16BIT; } static void __init mxs_machine_init(void) -- cgit v0.10.2 From c241d0a3ba78d50da08bd0c8236433b7653a86c7 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 3 Nov 2012 16:59:07 +0100 Subject: ARM: dts: cfa10036: Use pinctrl for power led The leds-gpio driver recently got pinctrl support, so setup the power led gpio muxing through pinctrl. This avoids the warning: leds-gpio leds.X: pins are not configured from the driver Signed-off-by: Maxime Ripard Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts index c03a577..3a28077 100644 --- a/arch/arm/boot/dts/imx28-cfa10036.dts +++ b/arch/arm/boot/dts/imx28-cfa10036.dts @@ -22,6 +22,18 @@ apb@80000000 { apbh@80000000 { + pinctrl@80018000 { + led_pins_cfa10036: leds-10036@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3043 /* MX28_PAD_AUART1_RX__GPIO_3_4 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + ssp0: ssp@80010000 { compatible = "fsl,imx28-mmc"; pinctrl-names = "default"; @@ -43,6 +55,8 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_cfa10036>; power { gpios = <&gpio3 4 1>; -- cgit v0.10.2 From 24196d5c597272b1e5c57903f2e3c7996e607117 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 3 Nov 2012 16:59:08 +0100 Subject: ARM: dts: mxs: Add hog pins to Crystalfontz boards Use a hog_pins pinctrl group to force the muxing of GPIOs used on the Crystalfonz CFA10036 and CFA10049 boards. Signed-off-by: Maxime Ripard Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts index 3a28077..794fc9f 100644 --- a/arch/arm/boot/dts/imx28-cfa10036.dts +++ b/arch/arm/boot/dts/imx28-cfa10036.dts @@ -23,6 +23,19 @@ apb@80000000 { apbh@80000000 { pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_cfa10036>; + + hog_pins_cfa10036: hog-10036@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2073 /* MX28_PAD_SSP0_D7__GPIO_2_7 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + led_pins_cfa10036: leds-10036@0 { reg = <0>; fsl,pinmux-ids = < diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index 5549c6c..b222614 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -22,6 +22,22 @@ apb@80000000 { apbh@80000000 { pinctrl@80018000 { + pinctrl-names = "default", "default"; + pinctrl-1 = <&hog_pins_cfa10049>; + + hog_pins_cfa10049: hog-10049@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ + 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */ + 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */ + 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + spi3_pins_cfa10049: spi3-cfa10049@0 { reg = <0>; fsl,pinmux-ids = < -- cgit v0.10.2 From 03e07595febc4857b2b6ad756826f369c7628ec8 Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Wed, 31 Oct 2012 11:11:59 -0600 Subject: ARM: zynq: move arm-specific sys_timer out of ttc Move the sys_timer definition out of ttc driver and make it part of the common zynq code. This is preparation for renaming and COMMON_CLK support. Signed-off-by: Josh Cartwright Tested-by: Michal Simek diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index ba8d14f..6f058258 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include @@ -93,6 +94,18 @@ static struct map_desc io_desc[] __initdata = { }; +static void __init xilinx_zynq_timer_init(void) +{ + xttcpss_timer_init(); +} + +/* + * Instantiate and initialize the system timer structure + */ +static struct sys_timer xttcpss_sys_timer = { + .init = xilinx_zynq_timer_init, +}; + /** * xilinx_map_io() - Create memory mappings needed for early I/O. */ diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h index a009644..954b91c 100644 --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h @@ -17,8 +17,6 @@ #ifndef __MACH_ZYNQ_COMMON_H__ #define __MACH_ZYNQ_COMMON_H__ -#include - -extern struct sys_timer xttcpss_sys_timer; +void __init xttcpss_timer_init(void); #endif diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index c2c96cc..c93cbe5 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c @@ -24,7 +24,6 @@ #include #include -#include #include #include "common.h" @@ -269,7 +268,7 @@ static struct clock_event_device xttcpss_clockevent = { * Initializes the timer hardware and register the clock source and clock event * timers with Linux kernal timer framework **/ -static void __init xttcpss_timer_init(void) +void __init xttcpss_timer_init(void) { xttcpss_timer_hardware_init(); clocksource_register_hz(&clocksource_xttcpss, TIMER_RATE); @@ -289,10 +288,3 @@ static void __init xttcpss_timer_init(void) xttcpss_clockevent.cpumask = cpumask_of(0); clockevents_register_device(&xttcpss_clockevent); } - -/* - * Instantiate and initialize the system timer structure - */ -struct sys_timer xttcpss_sys_timer = { - .init = xttcpss_timer_init, -}; -- cgit v0.10.2 From 78d6785db13572f22d287d8c1739ceb4edf54bdc Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Wed, 31 Oct 2012 13:45:17 -0600 Subject: ARM: zynq: dts: add description of the second uart The zynq-7000 has an additional UART at 0xE0001000. Describe it in the device tree. Signed-off-by: Josh Cartwright Acked-by: Michal Simek diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq-ep107.dts index 574bc04..5caf100 100644 --- a/arch/arm/boot/dts/zynq-ep107.dts +++ b/arch/arm/boot/dts/zynq-ep107.dts @@ -59,5 +59,12 @@ interrupts = <0 27 4>; clock = <50000000>; }; + + uart1: uart@e0001000 { + compatible = "xlnx,xuartps"; + reg = <0xE0001000 0x1000>; + interrupts = <0 50 4>; + clock = <50000000>; + }; }; }; -- cgit v0.10.2 From 0f7238a1a4727ed515785cc45a55aa88d9933440 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Tue, 6 Nov 2012 15:09:04 +0900 Subject: ARM: dts: Add support for EXYNOS4X12 SoCs This patch adds device tree sources for EXYNOS4X12 SoC series (currently EXYNOS4212 and EXYNOS4412) and enables mach-exynos4-dt to support these SoCs. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi new file mode 100644 index 0000000..c6ae200 --- /dev/null +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -0,0 +1,28 @@ +/* + * Samsung's Exynos4212 SoC device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/include/ "exynos4x12.dtsi" + +/ { + compatible = "samsung,exynos4212"; + + gic:interrupt-controller@10490000 { + cpu-offset = <0x8000>; + }; +}; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi new file mode 100644 index 0000000..d7dfe31 --- /dev/null +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -0,0 +1,28 @@ +/* + * Samsung's Exynos4412 SoC device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/include/ "exynos4x12.dtsi" + +/ { + compatible = "samsung,exynos4412"; + + gic:interrupt-controller@10490000 { + cpu-offset = <0x4000>; + }; +}; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi new file mode 100644 index 0000000..906fe84 --- /dev/null +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -0,0 +1,30 @@ +/* + * Samsung's Exynos4x12 SoCs device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/include/ "exynos4.dtsi" + +/ { + combiner:interrupt-controller@10440000 { + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, + <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>; + }; +}; diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c index eadf4b5..2890bf7 100644 --- a/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -94,6 +94,8 @@ static void __init exynos4_dt_machine_init(void) static char const *exynos4_dt_compat[] __initdata = { "samsung,exynos4210", + "samsung,exynos4212", + "samsung,exynos4412", NULL }; -- cgit v0.10.2 From 86666adc1e594a3e98407da21f5f2bac587ff0cf Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Wed, 7 Nov 2012 08:17:43 +0900 Subject: ARM: dts: add board dts file for EXYNOS4412 based SMDK board Add a minimal board dts file for Samsung EXYNOS4412 based SMDK board. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f37cf9f..36488a5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -23,6 +23,7 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-trats.dtb \ + exynos4412-smdk4412.dtb \ exynos5250-smdk5250.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts new file mode 100644 index 0000000..f05bf57 --- /dev/null +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -0,0 +1,45 @@ +/* + * Samsung's Exynos4412 based SMDK board device tree source + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Samsung's SMDK4412 board which is based on + * Samsung's Exynos4412 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +/include/ "exynos4412.dtsi" + +/ { + model = "Samsung SMDK evaluation board based on Exynos4412"; + compatible = "samsung,smdk4412", "samsung,exynos4412"; + + memory { + reg = <0x40000000 0x40000000>; + }; + + chosen { + bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; + }; + + serial@13800000 { + status = "okay"; + }; + + serial@13810000 { + status = "okay"; + }; + + serial@13820000 { + status = "okay"; + }; + + serial@13830000 { + status = "okay"; + }; +}; -- cgit v0.10.2 From ab7b51ff9e3713995fb5f5a2ded22af06aed2847 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Wed, 7 Nov 2012 08:44:51 +0900 Subject: ARM: EXYNOS: Skip wakeup-int setup if pinctrl driver is used on EXYNOS4X12 This patch modifies the old wakeup interrupt initialization code to detect pinctrl driver by using for_each_matching_node instead of for_each_compatible_node and adds match table for both EXYNOS4210 and EXYNOS4X12. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Acked-by: Thomas Abraham Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 1947be8..4af8284 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -997,11 +997,14 @@ static int __init exynos_init_irq_eint(void) * platforms switch over to using the pinctrl driver, the wakeup * interrupt support code here can be completely removed. */ + static const struct of_device_id exynos_pinctrl_ids[] = { + { .compatible = "samsung,pinctrl-exynos4210", }, + { .compatible = "samsung,pinctrl-exynos4x12", }, + }; struct device_node *pctrl_np, *wkup_np; - const char *pctrl_compat = "samsung,pinctrl-exynos4210"; const char *wkup_compat = "samsung,exynos4210-wakeup-eint"; - for_each_compatible_node(pctrl_np, NULL, pctrl_compat) { + for_each_matching_node(pctrl_np, exynos_pinctrl_ids) { if (of_device_is_available(pctrl_np)) { wkup_np = of_find_compatible_node(pctrl_np, NULL, wkup_compat); -- cgit v0.10.2 From ba51bdd306a21ab0fabbea3a92541af0ee9fb8f6 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Wed, 7 Nov 2012 08:44:55 +0900 Subject: gpio: samsung: Skip registration if pinctrl driver is present on EXYNOS4X12 This patch modifies the Samsung GPIO driver to check for pinctrl driver presence earlier and use generic matching instead of a single compatible value. This allows us to fix warning about unrecognized SoC in case of EXYNOS4X12, which is not supported by this driver. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Acked-by: Thomas Abraham Acked-by: Linus Walleij Signed-off-by: Kukjin Kim diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c index a006f0d..88f41e5 100644 --- a/drivers/gpio/gpio-samsung.c +++ b/drivers/gpio/gpio-samsung.c @@ -2797,27 +2797,6 @@ static __init void exynos4_gpiolib_init(void) int group = 0; void __iomem *gpx_base; -#ifdef CONFIG_PINCTRL_SAMSUNG - /* - * This gpio driver includes support for device tree support and - * there are platforms using it. In order to maintain - * compatibility with those platforms, and to allow non-dt - * Exynos4210 platforms to use this gpiolib support, a check - * is added to find out if there is a active pin-controller - * driver support available. If it is available, this gpiolib - * support is ignored and the gpiolib support available in - * pin-controller driver is used. This is a temporary check and - * will go away when all of the Exynos4210 platforms have - * switched to using device tree and the pin-ctrl driver. - */ - struct device_node *pctrl_np; - const char *pctrl_compat = "samsung,pinctrl-exynos4210"; - pctrl_np = of_find_compatible_node(NULL, NULL, pctrl_compat); - if (pctrl_np) - if (of_device_is_available(pctrl_np)) - return; -#endif - /* gpio part1 */ gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K); if (gpio_base1 == NULL) { @@ -3032,6 +3011,28 @@ static __init int samsung_gpiolib_init(void) int i, nr_chips; int group = 0; +#ifdef CONFIG_PINCTRL_SAMSUNG + /* + * This gpio driver includes support for device tree support and there + * are platforms using it. In order to maintain compatibility with those + * platforms, and to allow non-dt Exynos4210 platforms to use this + * gpiolib support, a check is added to find out if there is a active + * pin-controller driver support available. If it is available, this + * gpiolib support is ignored and the gpiolib support available in + * pin-controller driver is used. This is a temporary check and will go + * away when all of the Exynos4210 platforms have switched to using + * device tree and the pin-ctrl driver. + */ + struct device_node *pctrl_np; + static const struct of_device_id exynos_pinctrl_ids[] = { + { .compatible = "samsung,pinctrl-exynos4210", }, + { .compatible = "samsung,pinctrl-exynos4x12", }, + }; + for_each_matching_node(pctrl_np, exynos_pinctrl_ids) + if (pctrl_np && of_device_is_available(pctrl_np)) + return -ENODEV; +#endif + samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs)); if (soc_is_s3c24xx()) { -- cgit v0.10.2 From aaf5e0be79e37d5a8509f09852788fa6a82522b2 Mon Sep 17 00:00:00 2001 From: Nick Bowler Date: Mon, 5 Nov 2012 16:45:49 -0500 Subject: ARM: zynq: Allow UART1 to be used as DEBUG_LL console. The main UART on the Xilinx ZC702 board is UART1, located at address e0001000. Add a Kconfig option to select this device as the low-level debugging port. This allows the really early boot printouts to reach the USB serial adaptor on this board. For consistency's sake, add a choice entry for UART0 even though it is the the default if UART1 is not selected. Signed-off-by: Nick Bowler Tested-by: Josh Cartwright Acked-by: Michal Simek diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index b0f3857..7754d51 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -132,6 +132,23 @@ choice their output to UART1 serial port on DaVinci TNETV107X devices. + config DEBUG_ZYNQ_UART0 + bool "Kernel low-level debugging on Xilinx Zynq using UART0" + depends on ARCH_ZYNQ + help + Say Y here if you want the debug print routines to direct + their output to UART0 on the Zynq platform. + + config DEBUG_ZYNQ_UART1 + bool "Kernel low-level debugging on Xilinx Zynq using UART1" + depends on ARCH_ZYNQ + help + Say Y here if you want the debug print routines to direct + their output to UART1 on the Zynq platform. + + If you have a ZC702 board and want early boot messages to + appear on the USB serial adaptor, select this option. + config DEBUG_DC21285_PORT bool "Kernel low-level debugging messages via footbridge serial port" depends on FOOTBRIDGE diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 6f058258..f0eef84 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -85,9 +85,9 @@ static struct map_desc io_desc[] __initdata = { #ifdef CONFIG_DEBUG_LL { - .virtual = UART0_VIRT, - .pfn = __phys_to_pfn(UART0_PHYS), - .length = UART0_SIZE, + .virtual = LL_UART_VADDR, + .pfn = __phys_to_pfn(LL_UART_PADDR), + .length = UART_SIZE, .type = MT_DEVICE, }, #endif diff --git a/arch/arm/mach-zynq/include/mach/zynq_soc.h b/arch/arm/mach-zynq/include/mach/zynq_soc.h index 1b8bf0e..5ebbd8e 100644 --- a/arch/arm/mach-zynq/include/mach/zynq_soc.h +++ b/arch/arm/mach-zynq/include/mach/zynq_soc.h @@ -25,8 +25,9 @@ * address that is known to work. */ #define UART0_PHYS 0xE0000000 -#define UART0_SIZE SZ_4K -#define UART0_VIRT 0xF0001000 +#define UART1_PHYS 0xE0001000 +#define UART_SIZE SZ_4K +#define UART_VIRT 0xF0001000 #define TTC0_PHYS 0xF8001000 #define TTC0_SIZE SZ_4K @@ -36,12 +37,17 @@ #define SCU_PERIPH_SIZE SZ_8K #define SCU_PERIPH_VIRT (TTC0_VIRT - SCU_PERIPH_SIZE) +#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1) +# define LL_UART_PADDR UART1_PHYS +#else +# define LL_UART_PADDR UART0_PHYS +#endif + +#define LL_UART_VADDR UART_VIRT + /* The following are intended for the devices that are mapped early */ #define TTC0_BASE IOMEM(TTC0_VIRT) #define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) -#define LL_UART_PADDR UART0_PHYS -#define LL_UART_VADDR UART0_VIRT - #endif -- cgit v0.10.2 From 67948adad178a041cd545c3f9b2bd077b1c5d7a1 Mon Sep 17 00:00:00 2001 From: Stanislav Meduna Date: Thu, 8 Nov 2012 23:39:14 +0100 Subject: ARM: mxs: Setup scheduler clock Setup scheduler clock on ARM MXS platforms with a 32-bit timrot such as i.MX28. This allows the scheduler to use sub-jiffy resolution. The corresponding change for 16-bit v1 timrots is not possible at the moment due to rounding issues with clock values wrapping faster than once per several seconds in the common ARM platform code. Signed-off-by: Stanislav Meduna Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c index 7c37926..856f4c7 100644 --- a/arch/arm/mach-mxs/timer.c +++ b/arch/arm/mach-mxs/timer.c @@ -29,6 +29,7 @@ #include #include +#include #include #include @@ -233,15 +234,22 @@ static struct clocksource clocksource_mxs = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; +static u32 notrace mxs_read_sched_clock_v2(void) +{ + return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1)); +} + static int __init mxs_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); if (timrot_is_v1()) clocksource_register_hz(&clocksource_mxs, c); - else + else { clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1), "mxs_timer", c, 200, 32, clocksource_mmio_readl_down); + setup_sched_clock(mxs_read_sched_clock_v2, 32, c); + } return 0; } -- cgit v0.10.2 From ac8e44ced54a9eb7fa1c2b02befc80a934d4cbe8 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Fri, 9 Nov 2012 13:42:41 +0100 Subject: ARM: mxs: apf28dev: Add I2C and SPI support Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts index 1643d25..6d8865b 100644 --- a/arch/arm/boot/dts/imx28-apf28dev.dts +++ b/arch/arm/boot/dts/imx28-apf28dev.dts @@ -27,6 +27,13 @@ status = "okay"; }; + ssp2: ssp@80014000 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + }; + pinctrl@80018000 { pinctrl-names = "default"; pinctrl-0 = <&hog_pins_apf28dev>; @@ -74,6 +81,12 @@ status = "okay"; }; + i2c0: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + }; + pwm: pwm@80064000 { pinctrl-names = "default"; pinctrl-0 = <&pwm3_pins_a &pwm4_pins_a>; -- cgit v0.10.2 From f6d3346f950f49b23c174931786d10d8aba51c8c Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 9 Oct 2012 10:04:57 +0200 Subject: ARM i.MX25: Add missing clock gates This completes the list of clock gates on the i.MX25. There are several clocks marked as reserved in the datasheet, but nevertheless used in the Freescale kernel. Add some comments to their positions and add 'reservedx' entries to the clk enum. This way we can replace them with the real names should we need them later. Adding the reserved entry names will help us keeping the clk numbers when moving to devicetree. Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index bc88580..78a754f 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -64,14 +64,20 @@ enum mx25_clks { per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel, per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5, per6, per7, per8, per9, per10, per11, per12, per13, per14, per15, - csi_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per, gpt_ipg_per, i2c_ipg_per, - lcdc_ipg_per, nfc_ipg_per, ssi1_ipg_per, ssi2_ipg_per, uart_ipg_per, - csi_ahb, esdhc1_ahb, esdhc2_ahb, fec_ahb, lcdc_ahb, sdma_ahb, - usbotg_ahb, can1_ipg, can2_ipg, csi_ipg, cspi1_ipg, cspi2_ipg, - cspi3_ipg, dryice_ipg, esdhc1_ipg, esdhc2_ipg, fec_ipg, iim_ipg, - kpp_ipg, lcdc_ipg, pwm1_ipg, pwm2_ipg, pwm3_ipg, pwm4_ipg, sdma_ipg, - ssi1_ipg, ssi2_ipg, tsc_ipg, uart1_ipg, uart2_ipg, uart3_ipg, - uart4_ipg, uart5_ipg, wdt_ipg, clk_max + csi_ipg_per, epit_ipg_per, esai_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per, + gpt_ipg_per, i2c_ipg_per, lcdc_ipg_per, nfc_ipg_per, owire_ipg_per, + pwm_ipg_per, sim1_ipg_per, sim2_ipg_per, ssi1_ipg_per, ssi2_ipg_per, + uart_ipg_per, ata_ahb, reserved1, csi_ahb, emi_ahb, esai_ahb, esdhc1_ahb, + esdhc2_ahb, fec_ahb, lcdc_ahb, rtic_ahb, sdma_ahb, slcdc_ahb, usbotg_ahb, + reserved2, reserved3, reserved4, reserved5, can1_ipg, can2_ipg, csi_ipg, + cspi1_ipg, cspi2_ipg, cspi3_ipg, dryice_ipg, ect_ipg, epit1_ipg, epit2_ipg, + reserved6, esdhc1_ipg, esdhc2_ipg, fec_ipg, reserved7, reserved8, reserved9, + gpt1_ipg, gpt2_ipg, gpt3_ipg, gpt4_ipg, reserved10, reserved11, reserved12, + iim_ipg, reserved13, reserved14, kpp_ipg, lcdc_ipg, reserved15, pwm1_ipg, + pwm2_ipg, pwm3_ipg, pwm4_ipg, rngb_ipg, reserved16, scc_ipg, sdma_ipg, + sim1_ipg, sim2_ipg, slcdc_ipg, spba_ipg, ssi1_ipg, ssi2_ipg, tsc_ipg, + uart1_ipg, uart2_ipg, uart3_ipg, uart4_ipg, uart5_ipg, reserved17, + wdt_ipg, clk_max }; static struct clk *clk[clk_max]; @@ -123,22 +129,36 @@ int __init mx25_clocks_init(void) clk[per14] = imx_clk_divider("per14", "per14_sel", ccm(CCM_PCDR3), 16, 6); clk[per15] = imx_clk_divider("per15", "per15_sel", ccm(CCM_PCDR3), 24, 6); clk[csi_ipg_per] = imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0); + clk[epit_ipg_per] = imx_clk_gate("epit_ipg_per", "per1", ccm(CCM_CGCR0), 1); + clk[esai_ipg_per] = imx_clk_gate("esai_ipg_per", "per2", ccm(CCM_CGCR0), 2); clk[esdhc1_ipg_per] = imx_clk_gate("esdhc1_ipg_per", "per3", ccm(CCM_CGCR0), 3); clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0), 4); clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0), 5); clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0), 6); clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", ccm(CCM_CGCR0), 7); clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "per8", ccm(CCM_CGCR0), 8); + clk[owire_ipg_per] = imx_clk_gate("owire_ipg_per", "per9", ccm(CCM_CGCR0), 9); + clk[pwm_ipg_per] = imx_clk_gate("pwm_ipg_per", "per10", ccm(CCM_CGCR0), 10); + clk[sim1_ipg_per] = imx_clk_gate("sim1_ipg_per", "per11", ccm(CCM_CGCR0), 11); + clk[sim2_ipg_per] = imx_clk_gate("sim2_ipg_per", "per12", ccm(CCM_CGCR0), 12); clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13); clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14); clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15); + clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16); + /* CCM_CGCR0(17): reserved */ clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18); + clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19); + clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20); clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21); clk[esdhc2_ahb] = imx_clk_gate("esdhc2_ahb", "ahb", ccm(CCM_CGCR0), 22); clk[fec_ahb] = imx_clk_gate("fec_ahb", "ahb", ccm(CCM_CGCR0), 23); clk[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", ccm(CCM_CGCR0), 24); + clk[rtic_ahb] = imx_clk_gate("rtic_ahb", "ahb", ccm(CCM_CGCR0), 25); clk[sdma_ahb] = imx_clk_gate("sdma_ahb", "ahb", ccm(CCM_CGCR0), 26); + clk[slcdc_ahb] = imx_clk_gate("slcdc_ahb", "ahb", ccm(CCM_CGCR0), 27); clk[usbotg_ahb] = imx_clk_gate("usbotg_ahb", "ahb", ccm(CCM_CGCR0), 28); + /* CCM_CGCR0(29-31): reserved */ + /* CCM_CGCR1(0): reserved in datasheet, used as audmux in FSL kernel */ clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1), 2); clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1), 3); clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1), 4); @@ -146,17 +166,41 @@ int __init mx25_clocks_init(void) clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1), 6); clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1), 7); clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1), 8); + clk[ect_ipg] = imx_clk_gate("ect_ipg", "ipg", ccm(CCM_CGCR1), 9); + clk[epit1_ipg] = imx_clk_gate("epit1_ipg", "ipg", ccm(CCM_CGCR1), 10); + clk[epit2_ipg] = imx_clk_gate("epit2_ipg", "ipg", ccm(CCM_CGCR1), 11); + /* CCM_CGCR1(12): reserved in datasheet, used as esai in FSL kernel */ clk[esdhc1_ipg] = imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13); clk[esdhc2_ipg] = imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14); clk[fec_ipg] = imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15); + /* CCM_CGCR1(16): reserved in datasheet, used as gpio1 in FSL kernel */ + /* CCM_CGCR1(17): reserved in datasheet, used as gpio2 in FSL kernel */ + /* CCM_CGCR1(18): reserved in datasheet, used as gpio3 in FSL kernel */ + clk[gpt1_ipg] = imx_clk_gate("gpt1_ipg", "ipg", ccm(CCM_CGCR1), 19); + clk[gpt2_ipg] = imx_clk_gate("gpt2_ipg", "ipg", ccm(CCM_CGCR1), 20); + clk[gpt3_ipg] = imx_clk_gate("gpt3_ipg", "ipg", ccm(CCM_CGCR1), 21); + clk[gpt4_ipg] = imx_clk_gate("gpt4_ipg", "ipg", ccm(CCM_CGCR1), 22); + /* CCM_CGCR1(23): reserved in datasheet, used as i2c1 in FSL kernel */ + /* CCM_CGCR1(24): reserved in datasheet, used as i2c2 in FSL kernel */ + /* CCM_CGCR1(25): reserved in datasheet, used as i2c3 in FSL kernel */ clk[iim_ipg] = imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26); + /* CCM_CGCR1(27): reserved in datasheet, used as iomuxc in FSL kernel */ + /* CCM_CGCR1(28): reserved in datasheet, used as kpp in FSL kernel */ clk[kpp_ipg] = imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28); clk[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29); + /* CCM_CGCR1(30): reserved in datasheet, used as owire in FSL kernel */ clk[pwm1_ipg] = imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31); clk[pwm2_ipg] = imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2), 0); clk[pwm3_ipg] = imx_clk_gate("pwm3_ipg", "ipg", ccm(CCM_CGCR2), 1); clk[pwm4_ipg] = imx_clk_gate("pwm4_ipg", "ipg", ccm(CCM_CGCR2), 2); + clk[rngb_ipg] = imx_clk_gate("rngb_ipg", "ipg", ccm(CCM_CGCR2), 3); + /* CCM_CGCR2(4): reserved in datasheet, used as rtic in FSL kernel */ + clk[scc_ipg] = imx_clk_gate("scc_ipg", "ipg", ccm(CCM_CGCR2), 5); clk[sdma_ipg] = imx_clk_gate("sdma_ipg", "ipg", ccm(CCM_CGCR2), 6); + clk[sim1_ipg] = imx_clk_gate("sim1_ipg", "ipg", ccm(CCM_CGCR2), 7); + clk[sim2_ipg] = imx_clk_gate("sim2_ipg", "ipg", ccm(CCM_CGCR2), 8); + clk[slcdc_ipg] = imx_clk_gate("slcdc_ipg", "ipg", ccm(CCM_CGCR2), 9); + clk[spba_ipg] = imx_clk_gate("spba_ipg", "ipg", ccm(CCM_CGCR2), 10); clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11); clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12); clk[tsc_ipg] = imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13); @@ -165,6 +209,7 @@ int __init mx25_clocks_init(void) clk[uart3_ipg] = imx_clk_gate("uart3_ipg", "ipg", ccm(CCM_CGCR2), 16); clk[uart4_ipg] = imx_clk_gate("uart4_ipg", "ipg", ccm(CCM_CGCR2), 17); clk[uart5_ipg] = imx_clk_gate("uart5_ipg", "ipg", ccm(CCM_CGCR2), 18); + /* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */ clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19); for (i = 0; i < ARRAY_SIZE(clk); i++) @@ -172,6 +217,8 @@ int __init mx25_clocks_init(void) pr_err("i.MX25 clk %d: register failed with %ld\n", i, PTR_ERR(clk[i])); + clk_prepare_enable(clk[emi_ahb]); + /* i.mx25 has the i.mx21 type uart */ clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0"); clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0"); -- cgit v0.10.2 From ef4bac5532fcc678a77ee2b16836458f58407056 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 20 Sep 2012 14:59:36 +0200 Subject: ARM i.MX25: Add devicetree support This adds a i.MX25 dt machine descriptor and changes the clock support to optionally initialize from dt. Signed-off-by: Sascha Hauer Acked-by: Shawn Guo diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index f1bf610..ff702c3 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -272,6 +272,13 @@ config MACH_EUKREA_MBIMXSD25_BASEBOARD endchoice +config MACH_IMX25_DT + bool "Support i.MX25 platforms from device tree" + select SOC_IMX25 + help + Include support for Freescale i.MX25 based platforms + using the device tree for discovery + comment "MX27 platforms:" config MACH_MX27ADS diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index fe47b71..0634b31 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o obj-$(CONFIG_MACH_EUKREA_CPUIMX25SD) += mach-eukrea_cpuimx25.o obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o +obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o # i.MX27 based machines obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index 78a754f..b197aa7 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -23,6 +23,9 @@ #include #include #include +#include +#include +#include #include "clk.h" #include "common.h" @@ -55,6 +58,8 @@ #define ccm(x) (CRM_BASE + (x)) +static struct clk_onecell_data clk_data; + static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", }; static const char *per_sel_clks[] = { "ahb", "upll", }; @@ -82,12 +87,12 @@ enum mx25_clks { static struct clk *clk[clk_max]; -int __init mx25_clocks_init(void) +static int __init __mx25_clocks_init(unsigned long osc_rate) { int i; clk[dummy] = imx_clk_fixed("dummy", 0); - clk[osc] = imx_clk_fixed("osc", 24000000); + clk[osc] = imx_clk_fixed("osc", osc_rate); clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL)); clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL)); clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); @@ -219,6 +224,16 @@ int __init mx25_clocks_init(void) clk_prepare_enable(clk[emi_ahb]); + clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); + clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); + + return 0; +} + +int __init mx25_clocks_init(void) +{ + __mx25_clocks_init(24000000); + /* i.mx25 has the i.mx21 type uart */ clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0"); clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0"); @@ -230,8 +245,6 @@ int __init mx25_clocks_init(void) clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3"); clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4"); clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4"); - clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); - clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0"); clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); @@ -289,5 +302,40 @@ int __init mx25_clocks_init(void) clk_register_clkdev(clk[iim_ipg], "iim", NULL); mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1); + + return 0; +} + +int __init mx25_clocks_init_dt(void) +{ + struct device_node *np; + void __iomem *base; + int irq; + unsigned long osc_rate = 24000000; + + /* retrieve the freqency of fixed clocks from device tree */ + for_each_compatible_node(np, NULL, "fixed-clock") { + u32 rate; + if (of_property_read_u32(np, "clock-frequency", &rate)) + continue; + + if (of_device_is_compatible(np, "fsl,imx-osc")) + osc_rate = rate; + } + + np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm"); + clk_data.clks = clk; + clk_data.clk_num = ARRAY_SIZE(clk); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + + __mx25_clocks_init(osc_rate); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt"); + base = of_iomap(np, 0); + WARN_ON(!base); + irq = irq_of_parse_and_map(np, 0); + + mxc_timer_init(base, irq); + return 0; } diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index ef8db6b..7191ab4 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -66,6 +66,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); +extern int mx25_clocks_init_dt(void); extern int mx27_clocks_init_dt(void); extern int mx31_clocks_init_dt(void); extern int mx51_clocks_init_dt(void); diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c new file mode 100644 index 0000000..e17dfbc --- /dev/null +++ b/arch/arm/mach-imx/imx25-dt.c @@ -0,0 +1,48 @@ +/* + * Copyright 2012 Sascha Hauer, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include "common.h" +#include "mx25.h" + +static void __init imx25_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static void __init imx25_timer_init(void) +{ + mx25_clocks_init_dt(); +} + +static struct sys_timer imx25_timer = { + .init = imx25_timer_init, +}; + +static const char * const imx25_dt_board_compat[] __initconst = { + "fsl,imx25", + NULL +}; + +DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)") + .map_io = mx25_map_io, + .init_early = imx25_init_early, + .init_irq = mx25_init_irq, + .handle_irq = imx25_handle_irq, + .timer = &imx25_timer, + .init_machine = imx25_dt_init, + .dt_compat = imx25_dt_board_compat, + .restart = mxc_restart, +MACHINE_END -- cgit v0.10.2 From 5658a68fb578df8c9b9dd3071b2a56bf92c15324 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 20 Sep 2012 15:04:33 +0200 Subject: ARM i.MX25: Add devicetree This adds a i.MX25 dtsi file along with the i.MX25 clock tree documentation. The devicetree should be fairly complete for: - uart - fec - i2c - spi - pwm - nand - gpio - wdog - esdhc - flexcan The more exotic devices currently miss clock bindings. Signed-off-by: Sascha Hauer Acked-by: Shawn Guo diff --git a/Documentation/devicetree/bindings/clock/imx25-clock.txt b/Documentation/devicetree/bindings/clock/imx25-clock.txt new file mode 100644 index 0000000..c2a3525 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx25-clock.txt @@ -0,0 +1,162 @@ +* Clock bindings for Freescale i.MX25 + +Required properties: +- compatible: Should be "fsl,imx25-ccm" +- reg: Address and length of the register set +- interrupts: Should contain CCM interrupt +- #clock-cells: Should be <1> + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. The following is a full list of i.MX25 +clocks and IDs. + + Clock ID + --------------------------- + dummy 0 + osc 1 + mpll 2 + upll 3 + mpll_cpu_3_4 4 + cpu_sel 5 + cpu 6 + ahb 7 + usb_div 8 + ipg 9 + per0_sel 10 + per1_sel 11 + per2_sel 12 + per3_sel 13 + per4_sel 14 + per5_sel 15 + per6_sel 16 + per7_sel 17 + per8_sel 18 + per9_sel 19 + per10_sel 20 + per11_sel 21 + per12_sel 22 + per13_sel 23 + per14_sel 24 + per15_sel 25 + per0 26 + per1 27 + per2 28 + per3 29 + per4 30 + per5 31 + per6 32 + per7 33 + per8 34 + per9 35 + per10 36 + per11 37 + per12 38 + per13 39 + per14 40 + per15 41 + csi_ipg_per 42 + epit_ipg_per 43 + esai_ipg_per 44 + esdhc1_ipg_per 45 + esdhc2_ipg_per 46 + gpt_ipg_per 47 + i2c_ipg_per 48 + lcdc_ipg_per 49 + nfc_ipg_per 50 + owire_ipg_per 51 + pwm_ipg_per 52 + sim1_ipg_per 53 + sim2_ipg_per 54 + ssi1_ipg_per 55 + ssi2_ipg_per 56 + uart_ipg_per 57 + ata_ahb 58 + reserved 59 + csi_ahb 60 + emi_ahb 61 + esai_ahb 62 + esdhc1_ahb 63 + esdhc2_ahb 64 + fec_ahb 65 + lcdc_ahb 66 + rtic_ahb 67 + sdma_ahb 68 + slcdc_ahb 69 + usbotg_ahb 70 + reserved 71 + reserved 72 + reserved 73 + reserved 74 + can1_ipg 75 + can2_ipg 76 + csi_ipg 77 + cspi1_ipg 78 + cspi2_ipg 79 + cspi3_ipg 80 + dryice_ipg 81 + ect_ipg 82 + epit1_ipg 83 + epit2_ipg 84 + reserved 85 + esdhc1_ipg 86 + esdhc2_ipg 87 + fec_ipg 88 + reserved 89 + reserved 90 + reserved 91 + gpt1_ipg 92 + gpt2_ipg 93 + gpt3_ipg 94 + gpt4_ipg 95 + reserved 96 + reserved 97 + reserved 98 + iim_ipg 99 + reserved 100 + reserved 101 + kpp_ipg 102 + lcdc_ipg 103 + reserved 104 + pwm1_ipg 105 + pwm2_ipg 106 + pwm3_ipg 107 + pwm4_ipg 108 + rngb_ipg 109 + reserved 110 + scc_ipg 111 + sdma_ipg 112 + sim1_ipg 113 + sim2_ipg 114 + slcdc_ipg 115 + spba_ipg 116 + ssi1_ipg 117 + ssi2_ipg 118 + tsc_ipg 119 + uart1_ipg 120 + uart2_ipg 121 + uart3_ipg 122 + uart4_ipg 123 + uart5_ipg 124 + reserved 125 + wdt_ipg 126 + +Examples: + +clks: ccm@53f80000 { + compatible = "fsl,imx25-ccm"; + reg = <0x53f80000 0x4000>; + interrupts = <31>; + clock-output-names = ... + "uart_ipg", + "uart_serial", + ...; +}; + +uart1: serial@43f90000 { + compatible = "fsl,imx25-uart", "fsl,imx21-uart"; + reg = <0x43f90000 0x4000>; + interrupts = <45>; + clocks = <&clks 79>, <&clks 50>; + clock-names = "ipg", "per"; + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi new file mode 100644 index 0000000..e1b13eb --- /dev/null +++ b/arch/arm/boot/dts/imx25.dtsi @@ -0,0 +1,515 @@ +/* + * Copyright 2012 Sascha Hauer, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + usb0 = &usbotg; + usb1 = &usbhost1; + }; + + asic: asic-interrupt-controller@68000000 { + compatible = "fsl,imx25-asic", "fsl,avic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x68000000 0x8000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc { + compatible = "fsl,imx-osc", "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&asic>; + ranges; + + aips@43f00000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x43f00000 0x100000>; + ranges; + + i2c1: i2c@43f80000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; + reg = <0x43f80000 0x4000>; + clocks = <&clks 48>; + clock-names = ""; + interrupts = <3>; + status = "disabled"; + }; + + i2c3: i2c@43f84000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; + reg = <0x43f84000 0x4000>; + clocks = <&clks 48>; + clock-names = ""; + interrupts = <10>; + status = "disabled"; + }; + + can1: can@43f88000 { + compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan"; + reg = <0x43f88000 0x4000>; + interrupts = <43>; + clocks = <&clks 75>, <&clks 75>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can2: can@43f8c000 { + compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan"; + reg = <0x43f8c000 0x4000>; + interrupts = <44>; + clocks = <&clks 76>, <&clks 76>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@43f90000 { + compatible = "fsl,imx25-uart", "fsl,imx21-uart"; + reg = <0x43f90000 0x4000>; + interrupts = <45>; + clocks = <&clks 120>, <&clks 57>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@43f94000 { + compatible = "fsl,imx25-uart", "fsl,imx21-uart"; + reg = <0x43f94000 0x4000>; + interrupts = <32>; + clocks = <&clks 121>, <&clks 57>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c2: i2c@43f98000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; + reg = <0x43f98000 0x4000>; + clocks = <&clks 48>; + clock-names = ""; + interrupts = <4>; + status = "disabled"; + }; + + owire@43f9c000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x43f9c000 0x4000>; + clocks = <&clks 51>; + clock-names = ""; + interrupts = <2>; + status = "disabled"; + }; + + spi1: cspi@43fa4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; + reg = <0x43fa4000 0x4000>; + clocks = <&clks 62>; + clock-names = "ipg"; + interrupts = <14>; + status = "disabled"; + }; + + kpp@43fa8000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x43fa8000 0x4000>; + clocks = <&clks 102>; + clock-names = ""; + interrupts = <24>; + status = "disabled"; + }; + + iomuxc@43fac000{ + compatible = "fsl,imx25-iomuxc"; + reg = <0x43fac000 0x4000>; + }; + + audmux@43fb0000 { + compatible = "fsl,imx25-audmux", "fsl,imx31-audmux"; + reg = <0x43fb0000 0x4000>; + status = "disabled"; + }; + }; + + spba@50000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x40000>; + ranges; + + spi3: cspi@50004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; + reg = <0x50004000 0x4000>; + interrupts = <0>; + clocks = <&clks 80>; + clock-names = "ipg"; + status = "disabled"; + }; + + uart4: serial@50008000 { + compatible = "fsl,imx25-uart", "fsl,imx21-uart"; + reg = <0x50008000 0x4000>; + interrupts = <5>; + clocks = <&clks 123>, <&clks 57>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@5000c000 { + compatible = "fsl,imx25-uart", "fsl,imx21-uart"; + reg = <0x5000c000 0x4000>; + interrupts = <18>; + clocks = <&clks 122>, <&clks 57>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + spi2: cspi@50010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; + reg = <0x50010000 0x4000>; + clocks = <&clks 79>; + clock-names = "ipg"; + interrupts = <13>; + status = "disabled"; + }; + + ssi2: ssi@50014000 { + compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; + reg = <0x50014000 0x4000>; + interrupts = <11>; + status = "disabled"; + }; + + esai@50018000 { + reg = <0x50018000 0x4000>; + interrupts = <7>; + }; + + uart5: serial@5002c000 { + compatible = "fsl,imx25-uart", "fsl,imx21-uart"; + reg = <0x5002c000 0x4000>; + interrupts = <40>; + clocks = <&clks 124>, <&clks 57>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + tsc: tsc@50030000 { + compatible = "fsl,imx25-adc", "fsl,imx21-tsc"; + reg = <0x50030000 0x4000>; + interrupts = <46>; + clocks = <&clks 119>; + clock-names = "ipg"; + status = "disabled"; + }; + + ssi1: ssi@50034000 { + compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; + reg = <0x50034000 0x4000>; + interrupts = <12>; + status = "disabled"; + }; + + fec: ethernet@50038000 { + compatible = "fsl,imx25-fec"; + reg = <0x50038000 0x4000>; + interrupts = <57>; + clocks = <&clks 88>, <&clks 65>; + clock-names = "ipg", "ahb"; + status = "disabled"; + }; + }; + + aips@53f00000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x53f00000 0x100000>; + ranges; + + clks: ccm@53f80000 { + compatible = "fsl,imx25-ccm"; + reg = <0x53f80000 0x4000>; + interrupts = <31>; + #clock-cells = <1>; + }; + + gpt4: timer@53f84000 { + compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; + reg = <0x53f84000 0x4000>; + clocks = <&clks 9>, <&clks 45>; + clock-names = "ipg", "per"; + interrupts = <1>; + }; + + gpt3: timer@53f88000 { + compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; + reg = <0x53f88000 0x4000>; + clocks = <&clks 9>, <&clks 47>; + clock-names = "ipg", "per"; + interrupts = <29>; + }; + + gpt2: timer@53f8c000 { + compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; + reg = <0x53f8c000 0x4000>; + clocks = <&clks 9>, <&clks 47>; + clock-names = "ipg", "per"; + interrupts = <53>; + }; + + gpt1: timer@53f90000 { + compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; + reg = <0x53f90000 0x4000>; + clocks = <&clks 9>, <&clks 47>; + clock-names = "ipg", "per"; + interrupts = <54>; + }; + + epit1: timer@53f94000 { + compatible = "fsl,imx25-epit"; + reg = <0x53f94000 0x4000>; + interrupts = <28>; + }; + + epit2: timer@53f98000 { + compatible = "fsl,imx25-epit"; + reg = <0x53f98000 0x4000>; + interrupts = <27>; + }; + + gpio4: gpio@53f9c000 { + compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; + reg = <0x53f9c000 0x4000>; + interrupts = <23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pwm2: pwm@53fa0000 { + compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; + #pwm-cells = <2>; + reg = <0x53fa0000 0x4000>; + clocks = <&clks 106>, <&clks 36>; + clock-names = "ipg", "per"; + interrupts = <36>; + }; + + gpio3: gpio@53fa4000 { + compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; + reg = <0x53fa4000 0x4000>; + interrupts = <16>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pwm3: pwm@53fa8000 { + compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; + #pwm-cells = <2>; + reg = <0x53fa8000 0x4000>; + clocks = <&clks 107>, <&clks 36>; + clock-names = "ipg", "per"; + interrupts = <41>; + }; + + esdhc1: esdhc@53fb4000 { + compatible = "fsl,imx25-esdhc"; + reg = <0x53fb4000 0x4000>; + interrupts = <9>; + clocks = <&clks 86>, <&clks 63>, <&clks 45>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + esdhc2: esdhc@53fb8000 { + compatible = "fsl,imx25-esdhc"; + reg = <0x53fb8000 0x4000>; + interrupts = <8>; + clocks = <&clks 87>, <&clks 64>, <&clks 46>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + lcdc@53fbc000 { + reg = <0x53fbc000 0x4000>; + interrupts = <39>; + clocks = <&clks 103>, <&clks 66>, <&clks 49>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + slcdc@53fc0000 { + reg = <0x53fc0000 0x4000>; + interrupts = <38>; + status = "disabled"; + }; + + pwm4: pwm@53fc8000 { + compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; + reg = <0x53fc8000 0x4000>; + clocks = <&clks 108>, <&clks 36>; + clock-names = "ipg", "per"; + interrupts = <42>; + }; + + gpio1: gpio@53fcc000 { + compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; + reg = <0x53fcc000 0x4000>; + interrupts = <52>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@53fd0000 { + compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; + reg = <0x53fd0000 0x4000>; + interrupts = <51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sdma@53fd4000 { + compatible = "fsl,imx25-sdma", "fsl,imx35-sdma"; + reg = <0x53fd4000 0x4000>; + clocks = <&clks 112>, <&clks 68>; + clock-names = "ipg", "ahb"; + interrupts = <34>; + }; + + wdog@53fdc000 { + compatible = "fsl,imx25-wdt", "fsl,imx21-wdt"; + reg = <0x53fdc000 0x4000>; + clocks = <&clks 126>; + clock-names = ""; + interrupts = <55>; + }; + + pwm1: pwm@53fe0000 { + compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; + #pwm-cells = <2>; + reg = <0x53fe0000 0x4000>; + clocks = <&clks 105>, <&clks 36>; + clock-names = "ipg", "per"; + interrupts = <26>; + }; + + usbphy1: usbphy@1 { + compatible = "nop-usbphy"; + status = "disabled"; + }; + + usbphy2: usbphy@2 { + compatible = "nop-usbphy"; + status = "disabled"; + }; + + usbotg: usb@53ff4000 { + compatible = "fsl,imx25-usb", "fsl,imx27-usb"; + reg = <0x53ff4000 0x0200>; + interrupts = <37>; + clocks = <&clks 9>, <&clks 70>, <&clks 8>; + clock-names = "ipg", "ahb", "per"; + fsl,usbmisc = <&usbmisc 0>; + status = "disabled"; + }; + + usbhost1: usb@53ff4400 { + compatible = "fsl,imx25-usb", "fsl,imx27-usb"; + reg = <0x53ff4400 0x0200>; + interrupts = <35>; + clocks = <&clks 9>, <&clks 70>, <&clks 8>; + clock-names = "ipg", "ahb", "per"; + fsl,usbmisc = <&usbmisc 1>; + status = "disabled"; + }; + + usbmisc: usbmisc@53ff4600 { + #index-cells = <1>; + compatible = "fsl,imx25-usbmisc"; + clocks = <&clks 9>, <&clks 70>, <&clks 8>; + clock-names = "ipg", "ahb", "per"; + reg = <0x53ff4600 0x00f>; + status = "disabled"; + }; + + dryice@53ffc000 { + compatible = "fsl,imx25-dryice", "fsl,imx25-rtc"; + reg = <0x53ffc000 0x4000>; + clocks = <&clks 81>; + clock-names = "ipg"; + interrupts = <25>; + }; + }; + + emi@80000000 { + compatible = "fsl,emi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80000000 0x3b002000>; + ranges; + + nand@bb000000 { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "fsl,imx25-nand"; + reg = <0xbb000000 0x2000>; + clocks = <&clks 50>; + clock-names = ""; + interrupts = <33>; + status = "disabled"; + }; + }; + }; +}; -- cgit v0.10.2 From 62300cbf982a5aba4ef22c5c68e1f658e8b324aa Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 12 Nov 2012 11:58:51 +0100 Subject: ARM i.MX: Add Ka-Ro TX25 devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Basic support for the Ka-Ro i.MX25 based TX25 board. Signed-off-by: Sascha Hauer Cc: Lothar Waßmann diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts new file mode 100644 index 0000000..d81f8a0 --- /dev/null +++ b/arch/arm/boot/dts/imx25-karo-tx25.dts @@ -0,0 +1,44 @@ +/* + * Copyright 2012 Sascha Hauer, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx25.dtsi" + +/ { + model = "Ka-Ro TX25"; + compatible = "karo,imx25-tx25", "fsl,imx25"; + + memory { + reg = <0x80000000 0x02000000 0x90000000 0x02000000>; + }; + + soc { + aips@43f00000 { + uart1: serial@43f90000 { + status = "okay"; + }; + }; + + spba@50000000 { + fec: ethernet@50038000 { + status = "okay"; + phy-mode = "rmii"; + }; + }; + + emi@80000000 { + nand@bb000000 { + nand-on-flash-bbt; + status = "okay"; + }; + }; + }; +}; -- cgit v0.10.2 From e06f1a9ed7ebff170ba05d2606d079fb36c6a52d Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Wed, 31 Oct 2012 12:24:48 -0600 Subject: ARM: zynq: dts: split up device tree The purpose of the created zynq-7000.dtsi file is to describe the hardware common to all Zynq 7000-based boards. Also, get rid of the zynq-ep107 device tree, since it is not hardware anyone can purchase. Add a zc702 dts file based on the zynq-7000.dtsi. Add it to the dts/Makefile so it is built with the 'dtbs' target. Signed-off-by: Josh Cartwright Acked-by: Michal Simek diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f37cf9f..76ed11e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -103,5 +103,6 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ wm8505-ref.dtb \ wm8650-mid.dtb +dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb endif diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi new file mode 100644 index 0000000..8b30e59 --- /dev/null +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/include/ "skeleton.dtsi" + +/ { + compatible = "xlnx,zynq-7000"; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + intc: interrupt-controller@f8f01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xF8F01000 0x1000>, + <0xF8F00100 0x100>; + }; + + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xF8F02000 0x1000>; + arm,data-latency = <2 3 2>; + arm,tag-latency = <2 3 2>; + cache-unified; + cache-level = <2>; + }; + + uart0: uart@e0000000 { + compatible = "xlnx,xuartps"; + reg = <0xE0000000 0x1000>; + interrupts = <0 27 4>; + clock = <50000000>; + }; + + uart1: uart@e0001000 { + compatible = "xlnx,xuartps"; + reg = <0xE0001000 0x1000>; + interrupts = <0 50 4>; + clock = <50000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq-ep107.dts deleted file mode 100644 index 5caf100..0000000 --- a/arch/arm/boot/dts/zynq-ep107.dts +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2011 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; -/ { - model = "Xilinx Zynq EP107"; - compatible = "xlnx,zynq-ep107"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - memory { - device_type = "memory"; - reg = <0x0 0x10000000>; - }; - - chosen { - bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk"; - linux,stdout-path = &uart0; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - intc: interrupt-controller@f8f01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0xF8F01000 0x1000>, - <0xF8F00100 0x100>; - }; - - L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0xF8F02000 0x1000>; - arm,data-latency = <2 3 2>; - arm,tag-latency = <2 3 2>; - cache-unified; - cache-level = <2>; - }; - - uart0: uart@e0000000 { - compatible = "xlnx,xuartps"; - reg = <0xE0000000 0x1000>; - interrupts = <0 27 4>; - clock = <50000000>; - }; - - uart1: uart@e0001000 { - compatible = "xlnx,xuartps"; - reg = <0xE0001000 0x1000>; - interrupts = <0 50 4>; - clock = <50000000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts new file mode 100644 index 0000000..e25a307 --- /dev/null +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2011 Xilinx + * Copyright (C) 2012 National Instruments Corp. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Zynq ZC702 Development Board"; + compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + bootargs = "console=ttyPS1,115200 earlyprintk"; + }; + +}; diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index f0eef84..5441323 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -115,7 +115,8 @@ static void __init xilinx_map_io(void) } static const char *xilinx_dt_match[] = { - "xlnx,zynq-ep107", + "xlnx,zynq-zc702", + "xlnx,zynq-7000", NULL }; -- cgit v0.10.2 From b7d41c937ed742b0995e4824ed2d0be085f80c1d Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Wed, 14 Nov 2012 13:59:45 +0100 Subject: ARM: LPC32xx: Add the motor PWM to base dts file Signed-off-by: Alban Bedel Signed-off-by: Roland Stigge diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index e5ffe96..1582f48 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -182,6 +182,13 @@ pnx,timeout = <0x64>; }; + mpwm: mpwm@400E8000 { + compatible = "nxp,lpc3220-motor-pwm"; + reg = <0x400E8000 0x78>; + status = "disabled"; + #pwm-cells = <2>; + }; + i2cusb: i2c@31020300 { compatible = "nxp,pnx-i2c"; reg = <0x31020300 0x100>; -- cgit v0.10.2 From 45aa2c27ada4829bc91bd80455bc67059ac06bc5 Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Tue, 13 Nov 2012 17:26:48 -0600 Subject: clk: Add support for fundamental zynq clks Provide simplified models for the necessary clocks on the zynq-7000 platform. Currently, the PLLs, the CPU clock network, and the basic peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled. OF bindings are also provided and documented. Signed-off-by: Josh Cartwright Signed-off-by: Soren Brinkmann Acked-by: Mike Turquette Acked-by: Michal Simek diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt new file mode 100644 index 0000000..23ae1db --- /dev/null +++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt @@ -0,0 +1,55 @@ +Device Tree Clock bindings for the Zynq 7000 EPP + +The Zynq EPP has several different clk providers, each with there own bindings. +The purpose of this document is to document their usage. + +See clock_bindings.txt for more information on the generic clock bindings. +See Chapter 25 of Zynq TRM for more information about Zynq clocks. + +== PLLs == + +Used to describe the ARM_PLL, DDR_PLL, and IO_PLL. + +Required properties: +- #clock-cells : shall be 0 (only one clock is output from this node) +- compatible : "xlnx,zynq-pll" +- reg : pair of u32 values, which are the address offsets within the SLCR + of the relevant PLL_CTRL register and PLL_CFG register respectively +- clocks : phandle for parent clock. should be the phandle for ps_clk + +Optional properties: +- clock-output-names : name of the output clock + +Example: + armpll: armpll { + #clock-cells = <0>; + compatible = "xlnx,zynq-pll"; + clocks = <&ps_clk>; + reg = <0x100 0x110>; + clock-output-names = "armpll"; + }; + +== Peripheral clocks == + +Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks. + +Required properties: +- #clock-cells : shall be 1 +- compatible : "xlnx,zynq-periph-clock" +- reg : a single u32 value, describing the offset within the SLCR where + the CLK_CTRL register is found for this peripheral +- clocks : phandle for parent clocks. should hold phandles for + the IO_PLL, ARM_PLL, and DDR_PLL in order +- clock-output-names : names of the output clock(s). For peripherals that have + two output clocks (for example, the UART), two clocks + should be listed. + +Example: + uart_clk: uart_clk { + #clock-cells = <1>; + compatible = "xlnx,zynq-periph-clock"; + clocks = <&iopll &armpll &ddrpll>; + reg = <0x154>; + clock-output-names = "uart0_ref_clk", + "uart1_ref_clk"; + }; diff --git a/drivers/clk/clk-zynq.c b/drivers/clk/clk-zynq.c new file mode 100644 index 0000000..37a3051 --- /dev/null +++ b/drivers/clk/clk-zynq.c @@ -0,0 +1,383 @@ +/* + * Copyright (c) 2012 National Instruments + * + * Josh Cartwright + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ +#include +#include +#include +#include +#include + +static void __iomem *slcr_base; + +struct zynq_pll_clk { + struct clk_hw hw; + void __iomem *pll_ctrl; + void __iomem *pll_cfg; +}; + +#define to_zynq_pll_clk(hw) container_of(hw, struct zynq_pll_clk, hw) + +#define CTRL_PLL_FDIV(x) ((x) >> 12) + +static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct zynq_pll_clk *pll = to_zynq_pll_clk(hw); + return parent_rate * CTRL_PLL_FDIV(ioread32(pll->pll_ctrl)); +} + +static const struct clk_ops zynq_pll_clk_ops = { + .recalc_rate = zynq_pll_recalc_rate, +}; + +static void __init zynq_pll_clk_setup(struct device_node *np) +{ + struct clk_init_data init; + struct zynq_pll_clk *pll; + const char *parent_name; + struct clk *clk; + u32 regs[2]; + int ret; + + ret = of_property_read_u32_array(np, "reg", regs, ARRAY_SIZE(regs)); + if (WARN_ON(ret)) + return; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (WARN_ON(!pll)) + return; + + pll->pll_ctrl = slcr_base + regs[0]; + pll->pll_cfg = slcr_base + regs[1]; + + of_property_read_string(np, "clock-output-names", &init.name); + + init.ops = &zynq_pll_clk_ops; + parent_name = of_clk_get_parent_name(np, 0); + init.parent_names = &parent_name; + init.num_parents = 1; + + pll->hw.init = &init; + + clk = clk_register(NULL, &pll->hw); + if (WARN_ON(IS_ERR(clk))) + return; + + ret = of_clk_add_provider(np, of_clk_src_simple_get, clk); + if (WARN_ON(ret)) + return; +} + +struct zynq_periph_clk { + struct clk_hw hw; + struct clk_onecell_data onecell_data; + struct clk *gates[2]; + void __iomem *clk_ctrl; + spinlock_t clkact_lock; +}; + +#define to_zynq_periph_clk(hw) container_of(hw, struct zynq_periph_clk, hw) + +static const u8 periph_clk_parent_map[] = { + 0, 0, 1, 2 +}; +#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 0x30) >> 4]) +#define PERIPH_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8) + +static unsigned long zynq_periph_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct zynq_periph_clk *periph = to_zynq_periph_clk(hw); + return parent_rate / PERIPH_CLK_CTRL_DIV(ioread32(periph->clk_ctrl)); +} + +static u8 zynq_periph_get_parent(struct clk_hw *hw) +{ + struct zynq_periph_clk *periph = to_zynq_periph_clk(hw); + return PERIPH_CLK_CTRL_SRC(ioread32(periph->clk_ctrl)); +} + +static const struct clk_ops zynq_periph_clk_ops = { + .recalc_rate = zynq_periph_recalc_rate, + .get_parent = zynq_periph_get_parent, +}; + +static void __init zynq_periph_clk_setup(struct device_node *np) +{ + struct zynq_periph_clk *periph; + const char *parent_names[3]; + struct clk_init_data init; + int clk_num = 0, err; + const char *name; + struct clk *clk; + u32 reg; + int i; + + err = of_property_read_u32(np, "reg", ®); + if (WARN_ON(err)) + return; + + periph = kzalloc(sizeof(*periph), GFP_KERNEL); + if (WARN_ON(!periph)) + return; + + periph->clk_ctrl = slcr_base + reg; + spin_lock_init(&periph->clkact_lock); + + init.name = np->name; + init.ops = &zynq_periph_clk_ops; + for (i = 0; i < ARRAY_SIZE(parent_names); i++) + parent_names[i] = of_clk_get_parent_name(np, i); + init.parent_names = parent_names; + init.num_parents = ARRAY_SIZE(parent_names); + + periph->hw.init = &init; + + clk = clk_register(NULL, &periph->hw); + if (WARN_ON(IS_ERR(clk))) + return; + + err = of_clk_add_provider(np, of_clk_src_simple_get, clk); + if (WARN_ON(err)) + return; + + err = of_property_read_string_index(np, "clock-output-names", 0, + &name); + if (WARN_ON(err)) + return; + + periph->gates[0] = clk_register_gate(NULL, name, np->name, 0, + periph->clk_ctrl, 0, 0, + &periph->clkact_lock); + if (WARN_ON(IS_ERR(periph->gates[0]))) + return; + clk_num++; + + /* some periph clks have 2 downstream gates */ + err = of_property_read_string_index(np, "clock-output-names", 1, + &name); + if (err != -ENODATA) { + periph->gates[1] = clk_register_gate(NULL, name, np->name, 0, + periph->clk_ctrl, 1, 0, + &periph->clkact_lock); + if (WARN_ON(IS_ERR(periph->gates[1]))) + return; + clk_num++; + } + + periph->onecell_data.clks = periph->gates; + periph->onecell_data.clk_num = clk_num; + + err = of_clk_add_provider(np, of_clk_src_onecell_get, + &periph->onecell_data); + if (WARN_ON(err)) + return; +} + +/* CPU Clock domain is modelled as a mux with 4 children subclks, whose + * derivative rates depend on CLK_621_TRUE + */ + +struct zynq_cpu_clk { + struct clk_hw hw; + struct clk_onecell_data onecell_data; + struct clk *subclks[4]; + void __iomem *clk_ctrl; + spinlock_t clkact_lock; +}; + +#define to_zynq_cpu_clk(hw) container_of(hw, struct zynq_cpu_clk, hw) + +static const u8 zynq_cpu_clk_parent_map[] = { + 1, 1, 2, 0 +}; +#define CPU_CLK_SRCSEL(x) (zynq_cpu_clk_parent_map[(((x) & 0x30) >> 4)]) +#define CPU_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8) + +static u8 zynq_cpu_clk_get_parent(struct clk_hw *hw) +{ + struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw); + return CPU_CLK_SRCSEL(ioread32(cpuclk->clk_ctrl)); +} + +static unsigned long zynq_cpu_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw); + return parent_rate / CPU_CLK_CTRL_DIV(ioread32(cpuclk->clk_ctrl)); +} + +static const struct clk_ops zynq_cpu_clk_ops = { + .get_parent = zynq_cpu_clk_get_parent, + .recalc_rate = zynq_cpu_clk_recalc_rate, +}; + +struct zynq_cpu_subclk { + struct clk_hw hw; + void __iomem *clk_621; + enum { + CPU_SUBCLK_6X4X, + CPU_SUBCLK_3X2X, + CPU_SUBCLK_2X, + CPU_SUBCLK_1X, + } which; +}; + +#define CLK_621_TRUE(x) ((x) & 1) + +#define to_zynq_cpu_subclk(hw) container_of(hw, struct zynq_cpu_subclk, hw); + +static unsigned long zynq_cpu_subclk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned long uninitialized_var(rate); + struct zynq_cpu_subclk *subclk; + bool is_621; + + subclk = to_zynq_cpu_subclk(hw) + is_621 = CLK_621_TRUE(ioread32(subclk->clk_621)); + + switch (subclk->which) { + case CPU_SUBCLK_6X4X: + rate = parent_rate; + break; + case CPU_SUBCLK_3X2X: + rate = parent_rate / 2; + break; + case CPU_SUBCLK_2X: + rate = parent_rate / (is_621 ? 3 : 2); + break; + case CPU_SUBCLK_1X: + rate = parent_rate / (is_621 ? 6 : 4); + break; + }; + + return rate; +} + +static const struct clk_ops zynq_cpu_subclk_ops = { + .recalc_rate = zynq_cpu_subclk_recalc_rate, +}; + +static struct clk *zynq_cpu_subclk_setup(struct device_node *np, u8 which, + void __iomem *clk_621) +{ + struct zynq_cpu_subclk *subclk; + struct clk_init_data init; + struct clk *clk; + int err; + + err = of_property_read_string_index(np, "clock-output-names", + which, &init.name); + if (WARN_ON(err)) + goto err_read_output_name; + + subclk = kzalloc(sizeof(*subclk), GFP_KERNEL); + if (!subclk) + goto err_subclk_alloc; + + subclk->clk_621 = clk_621; + subclk->which = which; + + init.ops = &zynq_cpu_subclk_ops; + init.parent_names = &np->name; + init.num_parents = 1; + + subclk->hw.init = &init; + + clk = clk_register(NULL, &subclk->hw); + if (WARN_ON(IS_ERR(clk))) + goto err_clk_register; + + return clk; + +err_clk_register: + kfree(subclk); +err_subclk_alloc: +err_read_output_name: + return ERR_PTR(-EINVAL); +} + +static void __init zynq_cpu_clk_setup(struct device_node *np) +{ + struct zynq_cpu_clk *cpuclk; + const char *parent_names[3]; + struct clk_init_data init; + void __iomem *clk_621; + struct clk *clk; + u32 reg[2]; + int err; + int i; + + err = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg)); + if (WARN_ON(err)) + return; + + cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL); + if (WARN_ON(!cpuclk)) + return; + + cpuclk->clk_ctrl = slcr_base + reg[0]; + clk_621 = slcr_base + reg[1]; + spin_lock_init(&cpuclk->clkact_lock); + + init.name = np->name; + init.ops = &zynq_cpu_clk_ops; + for (i = 0; i < ARRAY_SIZE(parent_names); i++) + parent_names[i] = of_clk_get_parent_name(np, i); + init.parent_names = parent_names; + init.num_parents = ARRAY_SIZE(parent_names); + + cpuclk->hw.init = &init; + + clk = clk_register(NULL, &cpuclk->hw); + if (WARN_ON(IS_ERR(clk))) + return; + + err = of_clk_add_provider(np, of_clk_src_simple_get, clk); + if (WARN_ON(err)) + return; + + for (i = 0; i < 4; i++) { + cpuclk->subclks[i] = zynq_cpu_subclk_setup(np, i, clk_621); + if (WARN_ON(IS_ERR(cpuclk->subclks[i]))) + return; + } + + cpuclk->onecell_data.clks = cpuclk->subclks; + cpuclk->onecell_data.clk_num = i; + + err = of_clk_add_provider(np, of_clk_src_onecell_get, + &cpuclk->onecell_data); + if (WARN_ON(err)) + return; +} + +static const __initconst struct of_device_id zynq_clk_match[] = { + { .compatible = "fixed-clock", .data = of_fixed_clk_setup, }, + { .compatible = "xlnx,zynq-pll", .data = zynq_pll_clk_setup, }, + { .compatible = "xlnx,zynq-periph-clock", + .data = zynq_periph_clk_setup, }, + { .compatible = "xlnx,zynq-cpu-clock", .data = zynq_cpu_clk_setup, }, + {} +}; + +void __init xilinx_zynq_clocks_init(void __iomem *slcr) +{ + slcr_base = slcr; + of_clk_init(zynq_clk_match); +} diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h new file mode 100644 index 0000000..56be7cd --- /dev/null +++ b/include/linux/clk/zynq.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2012 National Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __LINUX_CLK_ZYNQ_H_ +#define __LINUX_CLK_ZYNQ_H_ + +void __init xilinx_zynq_clocks_init(void __iomem *slcr); + +#endif -- cgit v0.10.2 From 0f586fbf6f6a9119392a5cb0f193ac11c753b09e Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Thu, 8 Nov 2012 12:04:26 -0600 Subject: ARM: zynq: use zynq clk bindings Make the Zynq platform use the newly created zynq clk bindings. Signed-off-by: Josh Cartwright Acked-by: Michal Simek diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 21ed87b..ccfe0ab 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -959,6 +959,7 @@ config ARCH_ZYNQ bool "Xilinx Zynq ARM Cortex A9 Platform" select ARM_AMBA select ARM_GIC + select COMMON_CLK select CPU_V7 select GENERIC_CLOCKEVENTS select ICST diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 8b30e59..bb3085c 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -53,5 +53,61 @@ interrupts = <0 50 4>; clock = <50000000>; }; + + slcr: slcr@f8000000 { + compatible = "xlnx,zynq-slcr"; + reg = <0xF8000000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ps_clk: ps_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* clock-frequency set in board-specific file */ + clock-output-names = "ps_clk"; + }; + armpll: armpll { + #clock-cells = <0>; + compatible = "xlnx,zynq-pll"; + clocks = <&ps_clk>; + reg = <0x100 0x110>; + clock-output-names = "armpll"; + }; + ddrpll: ddrpll { + #clock-cells = <0>; + compatible = "xlnx,zynq-pll"; + clocks = <&ps_clk>; + reg = <0x104 0x114>; + clock-output-names = "ddrpll"; + }; + iopll: iopll { + #clock-cells = <0>; + compatible = "xlnx,zynq-pll"; + clocks = <&ps_clk>; + reg = <0x108 0x118>; + clock-output-names = "iopll"; + }; + uart_clk: uart_clk { + #clock-cells = <1>; + compatible = "xlnx,zynq-periph-clock"; + clocks = <&iopll &armpll &ddrpll>; + reg = <0x154>; + clock-output-names = "uart0_ref_clk", + "uart1_ref_clk"; + }; + cpu_clk: cpu_clk { + #clock-cells = <1>; + compatible = "xlnx,zynq-cpu-clock"; + clocks = <&iopll &armpll &ddrpll>; + reg = <0x120 0x1C4>; + clock-output-names = "cpu_6x4x", + "cpu_3x2x", + "cpu_2x", + "cpu_1x"; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index e25a307..86f44d5 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -28,3 +28,7 @@ }; }; + +&ps_clk { + clock-frequency = <33333330>; +}; diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 5441323..79bf5fb 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include #include #include #include @@ -96,6 +98,15 @@ static struct map_desc io_desc[] __initdata = { static void __init xilinx_zynq_timer_init(void) { + struct device_node *np; + void __iomem *slcr; + + np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); + slcr = of_iomap(np, 0); + WARN_ON(!slcr); + + xilinx_zynq_clocks_init(slcr); + xttcpss_timer_init(); } diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 71a25b9..d35a34c58 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -19,6 +19,7 @@ endif obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o +obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o # Chip specific obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o -- cgit v0.10.2 From 91dc985c5e51af7036c1ccf9cea1b05662c96791 Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Wed, 31 Oct 2012 13:56:14 -0600 Subject: ARM: zynq: add clk binding support to the ttc Add support for retrieving TTC configuration from device tree. This includes the ability to pull information about the driving clocks from the of_clk bindings. Signed-off-by: Josh Cartwright Acked-by: Michal Simek diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index bb3085c..401c126 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -109,5 +109,58 @@ }; }; }; + + ttc0: ttc0@f8001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "xlnx,ttc"; + reg = <0xF8001000 0x1000>; + clocks = <&cpu_clk 3>; + clock-names = "cpu_1x"; + clock-ranges; + + ttc0_0: ttc0.0 { + status = "disabled"; + reg = <0>; + interrupts = <0 10 4>; + }; + ttc0_1: ttc0.1 { + status = "disabled"; + reg = <1>; + interrupts = <0 11 4>; + }; + ttc0_2: ttc0.2 { + status = "disabled"; + reg = <2>; + interrupts = <0 12 4>; + }; + }; + + ttc1: ttc1@f8002000 { + #interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "xlnx,ttc"; + reg = <0xF8002000 0x1000>; + clocks = <&cpu_clk 3>; + clock-names = "cpu_1x"; + clock-ranges; + + ttc1_0: ttc1.0 { + status = "disabled"; + reg = <0>; + interrupts = <0 37 4>; + }; + ttc1_1: ttc1.1 { + status = "disabled"; + reg = <1>; + interrupts = <0 38 4>; + }; + ttc1_2: ttc1.2 { + status = "disabled"; + reg = <2>; + interrupts = <0 39 4>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 86f44d5..c772942 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -32,3 +32,13 @@ &ps_clk { clock-frequency = <33333330>; }; + +&ttc0_0 { + status = "ok"; + compatible = "xlnx,ttc-counter-clocksource"; +}; + +&ttc0_1 { + status = "ok"; + compatible = "xlnx,ttc-counter-clockevent"; +}; diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index c93cbe5..9662306 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c @@ -23,31 +23,15 @@ #include #include #include +#include +#include +#include +#include +#include #include #include "common.h" -#define IRQ_TIMERCOUNTER0 42 - -/* - * This driver configures the 2 16-bit count-up timers as follows: - * - * T1: Timer 1, clocksource for generic timekeeping - * T2: Timer 2, clockevent source for hrtimers - * T3: Timer 3, - * - * The input frequency to the timer module for emulation is 2.5MHz which is - * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, - * the timers are clocked at 78.125KHz (12.8 us resolution). - * - * The input frequency to the timer module in silicon will be 200MHz. With the - * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution). - */ -#define XTTCPSS_CLOCKSOURCE 0 /* Timer 1 as a generic timekeeping */ -#define XTTCPSS_CLOCKEVENT 1 /* Timer 2 as a clock event */ - -#define XTTCPSS_TIMER_BASE TTC0_BASE -#define XTTCPCC_EVENT_TIMER_IRQ (IRQ_TIMERCOUNTER0 + 1) /* * Timer Register Offset Definitions of Timer 1, Increment base address by 4 * and use same offsets for Timer 2 @@ -64,9 +48,14 @@ #define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1 -/* Setup the timers to use pre-scaling */ - -#define TIMER_RATE (PERIPHERAL_CLOCK_RATE / 32) +/* Setup the timers to use pre-scaling, using a fixed value for now that will + * work across most input frequency, but it may need to be more dynamic + */ +#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ +#define PRESCALE 2048 /* The exponent must match this */ +#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) +#define CLK_CNTRL_PRESCALE_EN 1 +#define CNT_CNTRL_RESET (1<<4) /** * struct xttcpss_timer - This definition defines local timer structure @@ -74,11 +63,25 @@ * @base_addr: Base address of timer **/ struct xttcpss_timer { - void __iomem *base_addr; + void __iomem *base_addr; +}; + +struct xttcpss_timer_clocksource { + struct xttcpss_timer xttc; + struct clocksource cs; }; -static struct xttcpss_timer timers[2]; -static struct clock_event_device xttcpss_clockevent; +#define to_xttcpss_timer_clksrc(x) \ + container_of(x, struct xttcpss_timer_clocksource, cs) + +struct xttcpss_timer_clockevent { + struct xttcpss_timer xttc; + struct clock_event_device ce; + struct clk *clk; +}; + +#define to_xttcpss_timer_clkevent(x) \ + container_of(x, struct xttcpss_timer_clockevent, ce) /** * xttcpss_set_interval - Set the timer interval value @@ -100,7 +103,7 @@ static void xttcpss_set_interval(struct xttcpss_timer *timer, /* Reset the counter (0x10) so that it starts from 0, one-shot mode makes this needed for timing to be right. */ - ctrl_reg |= 0x10; + ctrl_reg |= CNT_CNTRL_RESET; ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK; __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); } @@ -115,90 +118,31 @@ static void xttcpss_set_interval(struct xttcpss_timer *timer, **/ static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id) { - struct clock_event_device *evt = &xttcpss_clockevent; - struct xttcpss_timer *timer = dev_id; + struct xttcpss_timer_clockevent *xttce = dev_id; + struct xttcpss_timer *timer = &xttce->xttc; /* Acknowledge the interrupt and call event handler */ __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET), timer->base_addr + XTTCPSS_ISR_OFFSET); - evt->event_handler(evt); + xttce->ce.event_handler(&xttce->ce); return IRQ_HANDLED; } -static struct irqaction event_timer_irq = { - .name = "xttcpss clockevent", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = xttcpss_clock_event_interrupt, -}; - /** - * xttcpss_timer_hardware_init - Initialize the timer hardware - * - * Initialize the hardware to start the clock source, get the clock - * event timer ready to use, and hook up the interrupt. - **/ -static void __init xttcpss_timer_hardware_init(void) -{ - /* Setup the clock source counter to be an incrementing counter - * with no interrupt and it rolls over at 0xFFFF. Pre-scale - it by 32 also. Let it start running now. - */ - timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE; - - __raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr + - XTTCPSS_IER_OFFSET); - __raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr + - XTTCPSS_CLK_CNTRL_OFFSET); - __raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr + - XTTCPSS_CNT_CNTRL_OFFSET); - - /* Setup the clock event timer to be an interval timer which - * is prescaled by 32 using the interval interrupt. Leave it - * disabled for now. - */ - - timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4; - - __raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr + - XTTCPSS_CNT_CNTRL_OFFSET); - __raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr + - XTTCPSS_CLK_CNTRL_OFFSET); - __raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr + - XTTCPSS_IER_OFFSET); - - /* Setup IRQ the clock event timer */ - event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT]; - setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq); -} - -/** - * __raw_readl_cycles - Reads the timer counter register + * __xttc_clocksource_read - Reads the timer counter register * * returns: Current timer counter register value **/ -static cycle_t __raw_readl_cycles(struct clocksource *cs) +static cycle_t __xttc_clocksource_read(struct clocksource *cs) { - struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE]; + struct xttcpss_timer *timer = &to_xttcpss_timer_clksrc(cs)->xttc; return (cycle_t)__raw_readl(timer->base_addr + XTTCPSS_COUNT_VAL_OFFSET); } - -/* - * Instantiate and initialize the clock source structure - */ -static struct clocksource clocksource_xttcpss = { - .name = "xttcpss_timer1", - .rating = 200, /* Reasonable clock source */ - .read = __raw_readl_cycles, - .mask = CLOCKSOURCE_MASK(16), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - - /** * xttcpss_set_next_event - Sets the time interval for next event * @@ -210,7 +154,8 @@ static struct clocksource clocksource_xttcpss = { static int xttcpss_set_next_event(unsigned long cycles, struct clock_event_device *evt) { - struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT]; + struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt); + struct xttcpss_timer *timer = &xttce->xttc; xttcpss_set_interval(timer, cycles); return 0; @@ -225,12 +170,15 @@ static int xttcpss_set_next_event(unsigned long cycles, static void xttcpss_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { - struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT]; + struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt); + struct xttcpss_timer *timer = &xttce->xttc; u32 ctrl_reg; switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - xttcpss_set_interval(timer, TIMER_RATE / HZ); + xttcpss_set_interval(timer, + DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk), + PRESCALE * HZ)); break; case CLOCK_EVT_MODE_ONESHOT: case CLOCK_EVT_MODE_UNUSED: @@ -251,15 +199,106 @@ static void xttcpss_set_mode(enum clock_event_mode mode, } } -/* - * Instantiate and initialize the clock event structure - */ -static struct clock_event_device xttcpss_clockevent = { - .name = "xttcpss_timer2", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = xttcpss_set_next_event, - .set_mode = xttcpss_set_mode, - .rating = 200, +static void __init zynq_ttc_setup_clocksource(struct device_node *np, + void __iomem *base) +{ + struct xttcpss_timer_clocksource *ttccs; + struct clk *clk; + int err; + u32 reg; + + ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); + if (WARN_ON(!ttccs)) + return; + + err = of_property_read_u32(np, "reg", ®); + if (WARN_ON(err)) + return; + + clk = of_clk_get_by_name(np, "cpu_1x"); + if (WARN_ON(IS_ERR(clk))) + return; + + err = clk_prepare_enable(clk); + if (WARN_ON(err)) + return; + + ttccs->xttc.base_addr = base + reg * 4; + + ttccs->cs.name = np->name; + ttccs->cs.rating = 200; + ttccs->cs.read = __xttc_clocksource_read; + ttccs->cs.mask = CLOCKSOURCE_MASK(16); + ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; + + __raw_writel(0x0, ttccs->xttc.base_addr + XTTCPSS_IER_OFFSET); + __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, + ttccs->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET); + __raw_writel(CNT_CNTRL_RESET, + ttccs->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + + err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE); + if (WARN_ON(err)) + return; +} + +static void __init zynq_ttc_setup_clockevent(struct device_node *np, + void __iomem *base) +{ + struct xttcpss_timer_clockevent *ttcce; + int err, irq; + u32 reg; + + ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL); + if (WARN_ON(!ttcce)) + return; + + err = of_property_read_u32(np, "reg", ®); + if (WARN_ON(err)) + return; + + ttcce->xttc.base_addr = base + reg * 4; + + ttcce->clk = of_clk_get_by_name(np, "cpu_1x"); + if (WARN_ON(IS_ERR(ttcce->clk))) + return; + + err = clk_prepare_enable(ttcce->clk); + if (WARN_ON(err)) + return; + + irq = irq_of_parse_and_map(np, 0); + if (WARN_ON(!irq)) + return; + + ttcce->ce.name = np->name; + ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + ttcce->ce.set_next_event = xttcpss_set_next_event; + ttcce->ce.set_mode = xttcpss_set_mode; + ttcce->ce.rating = 200; + ttcce->ce.irq = irq; + + __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, + ttcce->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET); + __raw_writel(0x1, ttcce->xttc.base_addr + XTTCPSS_IER_OFFSET); + + err = request_irq(irq, xttcpss_clock_event_interrupt, IRQF_TIMER, + np->name, ttcce); + if (WARN_ON(err)) + return; + + clockevents_config_and_register(&ttcce->ce, + clk_get_rate(ttcce->clk) / PRESCALE, + 1, 0xfffe); +} + +static const __initconst struct of_device_id zynq_ttc_match[] = { + { .compatible = "xlnx,ttc-counter-clocksource", + .data = zynq_ttc_setup_clocksource, }, + { .compatible = "xlnx,ttc-counter-clockevent", + .data = zynq_ttc_setup_clockevent, }, + {} }; /** @@ -270,21 +309,25 @@ static struct clock_event_device xttcpss_clockevent = { **/ void __init xttcpss_timer_init(void) { - xttcpss_timer_hardware_init(); - clocksource_register_hz(&clocksource_xttcpss, TIMER_RATE); - - /* Calculate the parameters to allow the clockevent to operate using - integer math - */ - clockevents_calc_mult_shift(&xttcpss_clockevent, TIMER_RATE, 4); - - xttcpss_clockevent.max_delta_ns = - clockevent_delta2ns(0xfffe, &xttcpss_clockevent); - xttcpss_clockevent.min_delta_ns = - clockevent_delta2ns(1, &xttcpss_clockevent); - - /* Indicate that clock event is on 1st CPU as SMP boot needs it */ - - xttcpss_clockevent.cpumask = cpumask_of(0); - clockevents_register_device(&xttcpss_clockevent); + struct device_node *np; + + for_each_compatible_node(np, NULL, "xlnx,ttc") { + struct device_node *np_chld; + void __iomem *base; + + base = of_iomap(np, 0); + if (WARN_ON(!base)) + return; + + for_each_available_child_of_node(np, np_chld) { + int (*cb)(struct device_node *np, void __iomem *base); + const struct of_device_id *match; + + match = of_match_node(zynq_ttc_match, np_chld); + if (match) { + cb = match->data; + cb(np_chld, base); + } + } + } } -- cgit v0.10.2 From da2fc651e4c133490e4941623716087d60046874 Mon Sep 17 00:00:00 2001 From: Wei Ni Date: Fri, 21 Sep 2012 16:54:57 +0800 Subject: ARM: dt: t20 seaboard: turn on the power for wlan Enable the SDHCI1 controller. This is connected to the WiFi module. Signed-off-by: Wei Ni Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 33ae813..eafeca6 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -561,6 +561,12 @@ status = "okay"; }; + sdhci@c8000000 { + status = "okay"; + power-gpios = <&gpio 86 0>; /* gpio PK6 */ + bus-width = <4>; + }; + sdhci@c8000400 { status = "okay"; cd-gpios = <&gpio 69 0>; /* gpio PI5 */ -- cgit v0.10.2 From c729429e0c3d9c68872c4d1b72c8fadb377cfba2 Mon Sep 17 00:00:00 2001 From: Wei Ni Date: Fri, 21 Sep 2012 16:54:58 +0800 Subject: ARM: dt: t20 ventana: set pinmux and power for wlan Configure pinmux as required for WiFi. Enable the SDHCI1 controller, which is connectted to the WiFi module. Signed-off-by: Wei Ni Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 86854f1..bec8bb2 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -237,6 +237,16 @@ "ld23_22"; nvidia,pull = <1>; }; + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <1>; + nvidia,low-power-mode = <3>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <3>; + nvidia,slew-rate-falling = <3>; + }; }; }; @@ -425,6 +435,12 @@ status = "okay"; }; + sdhci@c8000000 { + status = "okay"; + power-gpios = <&gpio 86 0>; /* gpio PK6 */ + bus-width = <4>; + }; + sdhci@c8000400 { status = "okay"; cd-gpios = <&gpio 69 0>; /* gpio PI5 */ -- cgit v0.10.2 From 6fb11131ef3400364381661186a55a73b782c3be Mon Sep 17 00:00:00 2001 From: Wei Ni Date: Fri, 21 Sep 2012 16:54:59 +0800 Subject: ARM: dt: t30 cardhu: set pinmux and power for wlan Configure pinmux as required for WiFi. Enable the SDHCI1 controller for a02 and a04 board, which is connected to the WiFi module. For now, always enable the regulator that provides power to the Wifi module. Signed-off-by: Wei Ni Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts index dd4222f..adc88aa 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts @@ -83,5 +83,11 @@ gpio = <&gpio 83 0>; /* GPIO PK3 */ }; }; + + sdhci@78000400 { + status = "okay"; + power-gpios = <&gpio 28 0>; /* gpio PD4 */ + bus-width = <4>; + }; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts index 0828f09..08163e1 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -95,4 +95,10 @@ gpio = <&gpio 232 0>; /* GPIO PDD0 */ }; }; + + sdhci@78000400 { + status = "okay"; + power-gpios = <&gpio 27 0>; /* gpio PD3 */ + bus-width = <4>; + }; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index b1271a8..b245e6c 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -52,6 +52,22 @@ nvidia,pull = <2>; nvidia,tristate = <0>; }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; sdmmc4_clk_pcc4 { nvidia,pins = "sdmmc4_clk_pcc4", "sdmmc4_rst_n_pcc3"; @@ -81,6 +97,15 @@ nvidia,pull = <0>; nvidia,tristate = <0>; }; + sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <0>; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <1>; + nvidia,slew-rate-falling = <1>; + }; }; }; @@ -384,6 +409,8 @@ regulator-name = "vdd_com"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; enable-active-high; gpio = <&gpio 24 0>; /* gpio PD0 */ vin-supply = <&sys_3v3_reg>; -- cgit v0.10.2 From cf63346401c61d7910263d2537bb2d8d265156fa Mon Sep 17 00:00:00 2001 From: Mark Zhang Date: Thu, 25 Oct 2012 14:52:30 +0800 Subject: ARM: dt: tegra: ventana: define pinmux for ddc Tegra 2's I2C2 controller can be routed to either the PTA or DDC pin group on Ventana. So: - Remove the HDMI function definition of pta pingroup - Define child i2c adapters(ddc & pta) for I2C2 controller Signed-off-by: Mark Zhang Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index bec8bb2..1dde0d3 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -64,11 +64,6 @@ nvidia,pins = "dap4"; nvidia,function = "dap4"; }; - ddc { - nvidia,pins = "ddc", "owc", "spdi", "spdo", - "uac"; - nvidia,function = "rsvd2"; - }; dta { nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; nvidia,function = "vi"; @@ -98,7 +93,7 @@ nvidia,function = "pcie"; }; hdint { - nvidia,pins = "hdint", "pta"; + nvidia,pins = "hdint"; nvidia,function = "hdmi"; }; i2cp { @@ -129,6 +124,10 @@ "lspi", "lvp1", "lvs"; nvidia,function = "displaya"; }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; pmc { nvidia,pins = "pmc"; nvidia,function = "pwr_on"; @@ -248,6 +247,39 @@ nvidia,slew-rate-falling = <3>; }; }; + + state_i2cmux_ddc: pinmux_i2cmux_ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux_i2cmux_pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + + state_i2cmux_idle: pinmux_i2cmux_idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; }; i2s@70002800 { @@ -291,6 +323,31 @@ clock-frequency = <400000>; }; + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + i2c@7000c500 { status = "okay"; clock-frequency = <400000>; -- cgit v0.10.2 From a86b0db3c0eef34707a98efc0ae16ef62f93c110 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 30 Oct 2012 12:35:23 +0530 Subject: ARM: tegra: dts: add slink controller dt entry Add slink controller details in the dts file of Tegra20 and Tegra30. Signed-off-by: Laxman Dewangan Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index f40cfba..514ee28 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -174,6 +174,46 @@ status = "disabled"; }; + spi@7000d400 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d400 0x200>; + interrupts = <0 59 0x04>; + nvidia,dma-request-selector = <&apbdma 15>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi@7000d600 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d600 0x200>; + interrupts = <0 82 0x04>; + nvidia,dma-request-selector = <&apbdma 16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi@7000d800 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d480 0x200>; + interrupts = <0 83 0x04>; + nvidia,dma-request-selector = <&apbdma 17>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi@7000da00 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000da00 0x200>; + interrupts = <0 93 0x04>; + nvidia,dma-request-selector = <&apbdma 18>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pmc { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 148371b..9c08c1b 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -177,6 +177,66 @@ status = "disabled"; }; + spi@7000d400 { + compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + reg = <0x7000d400 0x200>; + interrupts = <0 59 0x04>; + nvidia,dma-request-selector = <&apbdma 15>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi@7000d600 { + compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + reg = <0x7000d600 0x200>; + interrupts = <0 82 0x04>; + nvidia,dma-request-selector = <&apbdma 16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi@7000d800 { + compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + reg = <0x7000d480 0x200>; + interrupts = <0 83 0x04>; + nvidia,dma-request-selector = <&apbdma 17>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi@7000da00 { + compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + reg = <0x7000da00 0x200>; + interrupts = <0 93 0x04>; + nvidia,dma-request-selector = <&apbdma 18>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi@7000dc00 { + compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + reg = <0x7000dc00 0x200>; + interrupts = <0 94 0x04>; + nvidia,dma-request-selector = <&apbdma 27>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi@7000de00 { + compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + reg = <0x7000de00 0x200>; + interrupts = <0 79 0x04>; + nvidia,dma-request-selector = <&apbdma 28>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pmc { compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; reg = <0x7000e400 0x400>; -- cgit v0.10.2 From c42cb1c379a6e59e2a04380616f530713658c68b Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 31 Oct 2012 14:32:54 +0530 Subject: ARM: tegra: dts: cardhu: enable SLINK4 Enable SLINK4 and connected device in Tegra30 based platform Cardhu. Setting maximum spi frequency to 25MHz. SPI serial flash is connected on CS1 of SLINK4 on cardhu platform. Signed-off-by: Laxman Dewangan [swarren: swapped reg/compatible order to be consistent] Signed-off-by: Stephen Warren diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 9de2b9f..ac2c2c4 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -51,4 +51,5 @@ ti Texas Instruments via VIA Technologies, Inc. wlf Wolfson Microelectronics wm Wondermedia Technologies, Inc. +winbond Winbond Electronics corp. xlnx Xilinx diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index b245e6c..bdb2a66 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -275,6 +275,16 @@ }; }; + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + spi-flash@1 { + compatible = "winbond,w25q32"; + reg = <1>; + spi-max-frequency = <20000000>; + }; + }; + ahub { i2s@70080400 { status = "okay"; -- cgit v0.10.2 From ec319903726322198972dd6f95674fdff8d39336 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 9 Nov 2012 14:04:50 +0100 Subject: ARM: tegra: tamonten: Add DDC/PTA pinmux This commit allows the I2C2 controller on Tegra20 to be routed either to the DDC or the PTA pin group at runtime. On Tamonten this allows the I2C bus to be used for the DDC of the HDMI connector or to access I2C chips on the carrier board. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 5b3d8b1..c3540e0 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -62,10 +62,6 @@ nvidia,pins = "dap4"; nvidia,function = "dap4"; }; - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; dta { nvidia,pins = "dta", "dtd"; nvidia,function = "sdio2"; @@ -91,7 +87,7 @@ nvidia,function = "pcie"; }; hdint { - nvidia,pins = "hdint", "pta"; + nvidia,pins = "hdint"; nvidia,function = "hdmi"; }; i2cp { @@ -230,6 +226,39 @@ nvidia,pull = <1>; }; }; + + state_i2cmux_ddc: pinmux_i2cmux_ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux_i2cmux_pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + + state_i2cmux_idle: pinmux_i2cmux_idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; }; i2s@70002800 { @@ -246,6 +275,36 @@ status = "okay"; }; + i2c@7000c400 { + clock-frequency = <100000>; + status = "okay"; + }; + + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + i2c@7000d000 { clock-frequency = <400000>; status = "okay"; -- cgit v0.10.2 From b28113e24975ef5307594bcc528401bef6ede9b8 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 9 Nov 2012 14:04:51 +0100 Subject: ARM: tegra: tec: Remove redundant DT properties These properties are already set by the tegra20-tamonten.dtsi, so they don't need to be repeated. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts index 9aff31b..916bec1 100644 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -7,9 +7,6 @@ compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; i2c@7000c000 { - clock-frequency = <400000>; - status = "okay"; - wm8903: wm8903@1a { compatible = "wlf,wm8903"; reg = <0x1a>; -- cgit v0.10.2 From 42d2534a92360908fb9ba5ef77a5cf8938ed2170 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 9 Nov 2012 22:58:43 +0100 Subject: ARM: tegra: harmony: Add ADT7641 temperature sensor The Harmony board has an Analog Devices ADT7461 temperature sensor connected to the DVC bus. It can be used to monitor the ambient (local) and on-die (remote) temperatures. Signed-off-by: Thierry Reding Tested-by: Stephen Warren Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 74b8a47..a3f2f38 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -396,6 +396,11 @@ }; }; }; + + temperature-sensor@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; }; pmc { -- cgit v0.10.2 From 840a40807f17ac6b8f2e1f19e495cab9896b19bc Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 9 Nov 2012 23:00:08 +0100 Subject: ARM: tegra: tamonten: Add NCT1008 temperature sensor The Tamonten SOM has an ON Semiconductor NCT1008 connected to the DVC bus which is used to measure the ambient (local) temperature as well as the on-die (remote) temperature. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index c3540e0..95df80e 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -440,6 +440,11 @@ }; }; }; + + temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + }; }; pmc { -- cgit v0.10.2 From ee9f726040466180909c9b0f85cfcc54910c8253 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 9 Nov 2012 23:01:21 +0100 Subject: ARM: tegra: ventana: Add NCT1008 temperature sensor The Harmony board has an ON Semiconductors NCT1008 temperature sensor connected to the DVC bus. It can be used to monitor the ambient (local) and on-die (remote) temperatures. Signed-off-by: Thierry Reding Tested-by: Stephen Warren Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 1dde0d3..adc4754 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -473,6 +473,11 @@ }; }; }; + + temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + }; }; pmc { -- cgit v0.10.2 From fa98a114bf0d1623d502b1ae1e9963ef97808214 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 13 Nov 2012 10:33:39 +0530 Subject: ARM: tegra: dts: add sflash controller dt entry Nvidia's Tegra20 have the SPI (SFLASH) controller to interface with spi flash device which is used for system boot. Add DT entry for this controller. Signed-off-by: Laxman Dewangan [swarren: move sflash node to keep file sorted] Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 514ee28..7850df8 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -147,6 +147,16 @@ status = "disabled"; }; + spi@7000c380 { + compatible = "nvidia,tegra20-sflash"; + reg = <0x7000c380 0x80>; + interrupts = <0 39 0x04>; + nvidia,dma-request-selector = <&apbdma 11>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c@7000c400 { compatible = "nvidia,tegra20-i2c"; reg = <0x7000c400 0x100>; -- cgit v0.10.2 From fea221e254e9842df0740688f30f1ce5a692a775 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 12 Nov 2012 12:51:22 -0700 Subject: ARM: tegra: trimslice: enable SPI flash TrimSlice contains a 1MiB SPI flash. Represent this in the device tree. Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 27fb8a6..f4e0428 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -254,6 +254,16 @@ clock-frequency = <400000>; }; + spi@7000c380 { + status = "okay"; + spi-max-frequency = <48000000>; + spi-flash@0 { + compatible = "winbond,w25q80bl"; + reg = <0>; + spi-max-frequency = <48000000>; + }; + }; + i2c@7000c400 { status = "okay"; clock-frequency = <400000>; -- cgit v0.10.2 From ed821f07090ce13a45ea0aaf8945bcdbc59548c0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 15 Nov 2012 22:07:54 +0100 Subject: ARM: tegra: Add Tegra20 host1x support Add the host1x node along with its children to the Tegra20 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 7850df8..fba998e 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -4,6 +4,93 @@ compatible = "nvidia,tegra20"; interrupt-parent = <&intc>; + host1x { + compatible = "nvidia,tegra20-host1x", "simple-bus"; + reg = <0x50000000 0x00024000>; + interrupts = <0 65 0x04 /* mpcore syncpt */ + 0 67 0x04>; /* mpcore general */ + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x04000000>; + + mpe { + compatible = "nvidia,tegra20-mpe"; + reg = <0x54040000 0x00040000>; + interrupts = <0 68 0x04>; + }; + + vi { + compatible = "nvidia,tegra20-vi"; + reg = <0x54080000 0x00040000>; + interrupts = <0 69 0x04>; + }; + + epp { + compatible = "nvidia,tegra20-epp"; + reg = <0x540c0000 0x00040000>; + interrupts = <0 70 0x04>; + }; + + isp { + compatible = "nvidia,tegra20-isp"; + reg = <0x54100000 0x00040000>; + interrupts = <0 71 0x04>; + }; + + gr2d { + compatible = "nvidia,tegra20-gr2d"; + reg = <0x54140000 0x00040000>; + interrupts = <0 72 0x04>; + }; + + gr3d { + compatible = "nvidia,tegra20-gr3d"; + reg = <0x54180000 0x00040000>; + }; + + dc@54200000 { + compatible = "nvidia,tegra20-dc"; + reg = <0x54200000 0x00040000>; + interrupts = <0 73 0x04>; + + rgb { + status = "disabled"; + }; + }; + + dc@54240000 { + compatible = "nvidia,tegra20-dc"; + reg = <0x54240000 0x00040000>; + interrupts = <0 74 0x04>; + + rgb { + status = "disabled"; + }; + }; + + hdmi { + compatible = "nvidia,tegra20-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = <0 75 0x04>; + status = "disabled"; + }; + + tvo { + compatible = "nvidia,tegra20-tvo"; + reg = <0x542c0000 0x00040000>; + interrupts = <0 76 0x04>; + status = "disabled"; + }; + + dsi { + compatible = "nvidia,tegra20-dsi"; + reg = <0x54300000 0x00040000>; + status = "disabled"; + }; + }; + cache-controller@50043000 { compatible = "arm,pl310-cache"; reg = <0x50043000 0x1000>; -- cgit v0.10.2 From ed39097c2ad97688d2734600ca20b7d66c311b92 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 15 Nov 2012 22:07:57 +0100 Subject: ARM: tegra: Add Tegra30 host1x support Add the host1x node along with its children to the Tegra30 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 9c08c1b..1f7f49a 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -4,6 +4,93 @@ compatible = "nvidia,tegra30"; interrupt-parent = <&intc>; + host1x { + compatible = "nvidia,tegra30-host1x", "simple-bus"; + reg = <0x50000000 0x00024000>; + interrupts = <0 65 0x04 /* mpcore syncpt */ + 0 67 0x04>; /* mpcore general */ + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x04000000>; + + mpe { + compatible = "nvidia,tegra30-mpe"; + reg = <0x54040000 0x00040000>; + interrupts = <0 68 0x04>; + }; + + vi { + compatible = "nvidia,tegra30-vi"; + reg = <0x54080000 0x00040000>; + interrupts = <0 69 0x04>; + }; + + epp { + compatible = "nvidia,tegra30-epp"; + reg = <0x540c0000 0x00040000>; + interrupts = <0 70 0x04>; + }; + + isp { + compatible = "nvidia,tegra30-isp"; + reg = <0x54100000 0x00040000>; + interrupts = <0 71 0x04>; + }; + + gr2d { + compatible = "nvidia,tegra30-gr2d"; + reg = <0x54140000 0x00040000>; + interrupts = <0 72 0x04>; + }; + + gr3d { + compatible = "nvidia,tegra30-gr3d"; + reg = <0x54180000 0x00040000>; + }; + + dc@54200000 { + compatible = "nvidia,tegra30-dc"; + reg = <0x54200000 0x00040000>; + interrupts = <0 73 0x04>; + + rgb { + status = "disabled"; + }; + }; + + dc@54240000 { + compatible = "nvidia,tegra30-dc"; + reg = <0x54240000 0x00040000>; + interrupts = <0 74 0x04>; + + rgb { + status = "disabled"; + }; + }; + + hdmi { + compatible = "nvidia,tegra30-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = <0 75 0x04>; + status = "disabled"; + }; + + tvo { + compatible = "nvidia,tegra30-tvo"; + reg = <0x542c0000 0x00040000>; + interrupts = <0 76 0x04>; + status = "disabled"; + }; + + dsi { + compatible = "nvidia,tegra30-dsi"; + reg = <0x54300000 0x00040000>; + status = "disabled"; + }; + }; + cache-controller@50043000 { compatible = "arm,pl310-cache"; reg = <0x50043000 0x1000>; -- cgit v0.10.2 From c104b6a2ed27210e1756e075b5fcbf20c17a71ca Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 25 Sep 2012 11:49:33 +0200 Subject: ARM i.MX dtsi: Add default bus-width property for esdhc controller According to Documentation/devicetree/bindings/mmc/mmc.txt bus-width is a mandatory property. While this is currently enforced nowhere, it's a good habit to just add the property now to allow to add common helper functionality for the mmc property parsing later. Signed-off-by: Sascha Hauer Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 54aea74..0bc8ae7 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -87,6 +87,7 @@ compatible = "fsl,imx51-esdhc"; reg = <0x70008000 0x4000>; interrupts = <2>; + bus-width = <4>; status = "disabled"; }; @@ -119,6 +120,7 @@ compatible = "fsl,imx51-esdhc"; reg = <0x70020000 0x4000>; interrupts = <3>; + bus-width = <4>; status = "disabled"; }; @@ -126,6 +128,7 @@ compatible = "fsl,imx51-esdhc"; reg = <0x70024000 0x4000>; interrupts = <4>; + bus-width = <4>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index caf09ff..a5dd4ce 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -85,6 +85,7 @@ compatible = "fsl,imx53-esdhc"; reg = <0x50004000 0x4000>; interrupts = <1>; + bus-width = <4>; status = "disabled"; }; @@ -92,6 +93,7 @@ compatible = "fsl,imx53-esdhc"; reg = <0x50008000 0x4000>; interrupts = <2>; + bus-width = <4>; status = "disabled"; }; @@ -124,6 +126,7 @@ compatible = "fsl,imx53-esdhc"; reg = <0x50020000 0x4000>; interrupts = <3>; + bus-width = <4>; status = "disabled"; }; @@ -131,6 +134,7 @@ compatible = "fsl,imx53-esdhc"; reg = <0x50024000 0x4000>; interrupts = <4>; + bus-width = <4>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index f604a44..663fb86 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -849,6 +849,7 @@ interrupts = <0 22 0x04>; clocks = <&clks 163>, <&clks 163>, <&clks 163>; clock-names = "ipg", "ahb", "per"; + bus-width = <4>; status = "disabled"; }; @@ -858,6 +859,7 @@ interrupts = <0 23 0x04>; clocks = <&clks 164>, <&clks 164>, <&clks 164>; clock-names = "ipg", "ahb", "per"; + bus-width = <4>; status = "disabled"; }; @@ -867,6 +869,7 @@ interrupts = <0 24 0x04>; clocks = <&clks 165>, <&clks 165>, <&clks 165>; clock-names = "ipg", "ahb", "per"; + bus-width = <4>; status = "disabled"; }; @@ -876,6 +879,7 @@ interrupts = <0 25 0x04>; clocks = <&clks 166>, <&clks 166>, <&clks 166>; clock-names = "ipg", "ahb", "per"; + bus-width = <4>; status = "disabled"; }; -- cgit v0.10.2 From e9dc615c50fc6436741889b82380b4bde3765a87 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 26 Sep 2012 20:27:35 -0300 Subject: ARM: dts: imx53-qsb: Use pinctrl for gpio-led Since commit 8fe4554f (leds: leds-gpio: adopt pinctrl support) gpio-led driver has pinctrl support, so setup the gpio led pin via pinctrl and avoid the following warning: leds-gpio leds.2: pins are not configured from the driver Signed-off-by: Fabio Estevam Reviewed-by: Marek Vasut Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index 08948af..5bae4c7 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts @@ -60,10 +60,16 @@ 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ + >; + }; + + led_pin_gpio7_7: led_gpio7_7@0 { + fsl,pins = < 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */ >; }; }; + }; uart1: serial@53fbc000 { @@ -216,6 +222,8 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_gpio7_7>; user { label = "Heartbeat"; -- cgit v0.10.2 From 2a3246713560344254bf96aa00def0cae26d564f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 26 Sep 2012 20:27:36 -0300 Subject: ARM: dts: imx53-qsb: Make DA9053 regulator functional Setup the GPIO7_11 pin as interrupt to the DA9053 and also rename the regulator nodes so that they match with the datasheet. This allows probing of DA9053 to succeed. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index 5bae4c7..b007553 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts @@ -60,6 +60,7 @@ 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ + 1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */ >; }; @@ -106,76 +107,93 @@ pmic: dialog@48 { compatible = "dlg,da9053-aa", "dlg,da9052"; reg = <0x48>; + interrupt-parent = <&gpio7>; + interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */ regulators { - buck0 { + buck1_reg: buck1 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <2075000>; + regulator-always-on; }; - buck1 { + buck2_reg: buck2 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <2075000>; + regulator-always-on; }; - buck2 { + buck3_reg: buck3 { regulator-min-microvolt = <925000>; regulator-max-microvolt = <2500000>; + regulator-always-on; }; - buck3 { + buck4_reg: buck4 { regulator-min-microvolt = <925000>; regulator-max-microvolt = <2500000>; + regulator-always-on; }; - ldo4 { + ldo1_reg: ldo1 { regulator-min-microvolt = <600000>; regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; }; - ldo5 { + ldo2_reg: ldo2 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo3_reg: ldo3 { regulator-min-microvolt = <600000>; regulator-max-microvolt = <1800000>; + regulator-always-on; }; - ldo6 { + ldo4_reg: ldo4 { regulator-min-microvolt = <1725000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; - ldo7 { + ldo5_reg: ldo5 { regulator-min-microvolt = <1725000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; - ldo8 { + ldo6_reg: ldo6 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3600000>; + regulator-always-on; }; - ldo9 { + ldo7_reg: ldo7 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3600000>; + regulator-always-on; }; - ldo10 { + ldo8_reg: ldo8 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3600000>; + regulator-always-on; }; - ldo11 { + ldo9_reg: ldo9 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3600000>; + regulator-always-on; }; - ldo12 { + ldo10_reg: ldo10 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3650000>; - }; - - ldo13 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; + regulator-always-on; }; }; }; -- cgit v0.10.2 From 49c9e60eaaa966cdb02ac9e989eeb6f940691c5d Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 8 Oct 2012 13:44:29 +0800 Subject: ARM: imx6q: let users input debug uart port number imx6q gets 5 uart ports in total. Different board design may choose different port as debug uart. For example, imx6q-sabresd uses UART1, imx6q-sabrelite uses UART2 and imx6q-arm2 uses UART4. Rather than bloating DEBUG_LL choice list with all these uart ports, the patch introduces DEBUG_IMX6Q_UART_PORT for users to input uart port number when DEBUG_IMX6Q_UART is selected inside DEBUG_LL choice. Signed-off-by: Shawn Guo diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 5566520..5dc7109 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -209,20 +209,12 @@ choice Say Y here if you want kernel low-level debugging support on i.MX50 or i.MX53. - config DEBUG_IMX6Q_UART2 - bool "i.MX6Q Debug UART2" + config DEBUG_IMX6Q_UART + bool "i.MX6Q Debug UART" depends on SOC_IMX6Q help Say Y here if you want kernel low-level debugging support - on i.MX6Q UART2. This is correct for e.g. the SabreLite - board. - - config DEBUG_IMX6Q_UART4 - bool "i.MX6Q Debug UART4" - depends on SOC_IMX6Q - help - Say Y here if you want kernel low-level debugging support - on i.MX6Q UART4. + on i.MX6Q. config DEBUG_MMP_UART2 bool "Kernel low-level debugging message via MMP UART2" @@ -409,6 +401,15 @@ choice endchoice +config DEBUG_IMX6Q_UART_PORT + int "i.MX6Q Debug UART Port (1-5)" if DEBUG_IMX6Q_UART + range 1 5 + default 1 + depends on SOC_IMX6Q + help + Choose UART port on which kernel low-level debug messages + should be output. + config DEBUG_LL_INCLUDE string default "debug/icedcc.S" if DEBUG_ICEDCC @@ -418,8 +419,7 @@ config DEBUG_LL_INCLUDE DEBUG_IMX31_IMX35_UART || \ DEBUG_IMX51_UART || \ DEBUG_IMX50_IMX53_UART ||\ - DEBUG_IMX6Q_UART2 || \ - DEBUG_IMX6Q_UART4 + DEBUG_IMX6Q_UART default "debug/highbank.S" if DEBUG_HIGHBANK_UART default "debug/mvebu.S" if DEBUG_MVEBU_UART default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART diff --git a/arch/arm/include/debug/imx.S b/arch/arm/include/debug/imx.S index 0b65d79..0c4e17d 100644 --- a/arch/arm/include/debug/imx.S +++ b/arch/arm/include/debug/imx.S @@ -10,6 +10,20 @@ * published by the Free Software Foundation. * */ +#define IMX6Q_UART1_BASE_ADDR 0x02020000 +#define IMX6Q_UART2_BASE_ADDR 0x021e8000 +#define IMX6Q_UART3_BASE_ADDR 0x021ec000 +#define IMX6Q_UART4_BASE_ADDR 0x021f0000 +#define IMX6Q_UART5_BASE_ADDR 0x021f4000 + +/* + * IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion + * of IMX6Q_UART##n##_BASE_ADDR. + */ +#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR +#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n) +#define IMX6Q_DEBUG_UART_BASE IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT) + #ifdef CONFIG_DEBUG_IMX1_UART #define UART_PADDR 0x00206000 #elif defined (CONFIG_DEBUG_IMX25_UART) @@ -22,10 +36,8 @@ #define UART_PADDR 0x73fbc000 #elif defined (CONFIG_DEBUG_IMX50_IMX53_UART) #define UART_PADDR 0x53fbc000 -#elif defined (CONFIG_DEBUG_IMX6Q_UART2) -#define UART_PADDR 0x021e8000 -#elif defined (CONFIG_DEBUG_IMX6Q_UART4) -#define UART_PADDR 0x021f0000 +#elif defined (CONFIG_DEBUG_IMX6Q_UART) +#define UART_PADDR IMX6Q_DEBUG_UART_BASE #endif /* diff --git a/arch/arm/mach-imx/lluart.c b/arch/arm/mach-imx/lluart.c index 5f15103..2fdc9bf 100644 --- a/arch/arm/mach-imx/lluart.c +++ b/arch/arm/mach-imx/lluart.c @@ -17,17 +17,25 @@ #include "hardware.h" +#define IMX6Q_UART1_BASE_ADDR 0x02020000 +#define IMX6Q_UART2_BASE_ADDR 0x021e8000 +#define IMX6Q_UART3_BASE_ADDR 0x021ec000 +#define IMX6Q_UART4_BASE_ADDR 0x021f0000 +#define IMX6Q_UART5_BASE_ADDR 0x021f4000 + +/* + * IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion + * of IMX6Q_UART##n##_BASE_ADDR. + */ +#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR +#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n) +#define IMX6Q_DEBUG_UART_BASE IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT) + static struct map_desc imx_lluart_desc = { -#ifdef CONFIG_DEBUG_IMX6Q_UART2 - .virtual = MX6Q_IO_P2V(MX6Q_UART2_BASE_ADDR), - .pfn = __phys_to_pfn(MX6Q_UART2_BASE_ADDR), - .length = MX6Q_UART2_SIZE, - .type = MT_DEVICE, -#endif -#ifdef CONFIG_DEBUG_IMX6Q_UART4 - .virtual = MX6Q_IO_P2V(MX6Q_UART4_BASE_ADDR), - .pfn = __phys_to_pfn(MX6Q_UART4_BASE_ADDR), - .length = MX6Q_UART4_SIZE, +#ifdef CONFIG_DEBUG_IMX6Q_UART + .virtual = IMX_IO_P2V(IMX6Q_DEBUG_UART_BASE), + .pfn = __phys_to_pfn(IMX6Q_DEBUG_UART_BASE), + .length = 0x4000, .type = MT_DEVICE, #endif }; diff --git a/arch/arm/mach-imx/mx6q.h b/arch/arm/mach-imx/mx6q.h index f7e7dba..19d3f54 100644 --- a/arch/arm/mach-imx/mx6q.h +++ b/arch/arm/mach-imx/mx6q.h @@ -27,9 +27,5 @@ #define MX6Q_CCM_SIZE 0x4000 #define MX6Q_ANATOP_BASE_ADDR 0x020c8000 #define MX6Q_ANATOP_SIZE 0x1000 -#define MX6Q_UART2_BASE_ADDR 0x021e8000 -#define MX6Q_UART2_SIZE 0x4000 -#define MX6Q_UART4_BASE_ADDR 0x021f0000 -#define MX6Q_UART4_SIZE 0x4000 #endif /* __MACH_MX6Q_H__ */ -- cgit v0.10.2 From 5c70cb01b89895189025f8de8ee2823f516eab6a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 7 Oct 2012 14:12:49 -0300 Subject: ARM: dts: imx6q-sabreauto: Add basic support mx6qsabreauto is a board based on mx6q SoC with the following features: - 2GB of DDR3 - 2 USB ports - 1 HDMI output port - SPI NOR - 2 LVDS LCD ports - Gigabit Ethernet - Camera - eMMC and SD card slot - Multichannel Audio - CAN - SATA - NAND - PCIE - Video Input Add very basic support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index ac9e751..f798187 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -41,6 +41,10 @@ i.MX6 Quad SABRE Smart Device Board Required root node properties: - compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; +i.MX6 Quad SABRE Automotive Board +Required root node properties: + - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; + Generic i.MX boards ------------------- diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c1ce813..ccafe36 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -49,6 +49,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \ imx53-qsb.dtb \ imx53-smd.dtb \ imx6q-arm2.dtb \ + imx6q-sabreauto.dtb \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts new file mode 100644 index 0000000..826e4ad --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabreauto.dts @@ -0,0 +1,64 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx6q.dtsi" + +/ { + model = "Freescale i.MX6 Quad SABRE Automotive Board"; + compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x80000000>; + }; + + soc { + aips-bus@02000000 { /* AIPS1 */ + iomuxc@020e0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */ + 13 0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */ + >; + }; + }; + }; + }; + + aips-bus@02100000 { /* AIPS2 */ + uart4: serial@021f0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_1>; + status = "okay"; + }; + + ethernet@02188000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_2>; + phy-mode = "rgmii"; + status = "okay"; + }; + + usdhc@02198000 { /* uSDHC3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + cd-gpios = <&gpio6 15 0>; + wp-gpios = <&gpio1 13 0>; + status = "okay"; + }; + }; + }; +}; -- cgit v0.10.2 From c92503886c9e566708a05f92a99c9c3fe71f4348 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 2 Jul 2012 20:13:03 +0800 Subject: ARM: dts: imx6q: enable snvs lp rtc Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 663fb86..255f56b 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -505,8 +505,16 @@ }; snvs@020cc000 { - reg = <0x020cc000 0x4000>; - interrupts = <0 19 0x04 0 20 0x04>; + compatible = "fsl,sec-v4.0-mon", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x020cc000 0x4000>; + + snvs-rtc-lp@34 { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + reg = <0x34 0x58>; + interrupts = <0 19 0x04 0 20 0x04>; + }; }; epit@020d0000 { /* EPIT1 */ -- cgit v0.10.2 From d90df97863c7838847abd0f144c71db60aa00643 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 19 Jul 2012 23:16:30 +0800 Subject: ARM: imx: enable cpufreq for imx6q It enables cpufreq support for imx6q with generic cpufreq-cpu0 driver. Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 255f56b..1565aea 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -36,6 +36,14 @@ compatible = "arm,cortex-a9"; reg = <0>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 792000 1100000 + 396000 950000 + 198000 850000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + cpu0-supply = <®_cpu>; }; cpu@1 { @@ -447,7 +455,7 @@ anatop-max-voltage = <2750000>; }; - regulator-vddcore@140 { + reg_cpu: regulator-vddcore@140 { compatible = "fsl,anatop-regulator"; regulator-name = "cpu"; regulator-min-microvolt = <725000>; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index f1bf610..01bf72c 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -829,6 +829,8 @@ config SOC_IMX53 config SOC_IMX6Q bool "i.MX6 Quad support" + select ARCH_HAS_CPUFREQ + select ARCH_HAS_OPP select ARM_CPU_SUSPEND if PM select ARM_GIC select COMMON_CLK @@ -841,6 +843,7 @@ config SOC_IMX6Q select MFD_SYSCON select PINCTRL select PINCTRL_IMX6Q + select PM_OPP if PM help This enables support for Freescale i.MX6 Quad processor. diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index e5a82bb..5f9f591 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -406,6 +406,7 @@ int __init mx6q_clocks_init(void) clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); clk_register_clkdev(clk[ahb], "ahb", NULL); clk_register_clkdev(clk[cko1], "cko1", NULL); + clk_register_clkdev(clk[arm], NULL, "cpu0"); /* * The gpmi needs 100MHz frequency in the EDO/Sync mode, -- cgit v0.10.2 From a1fff236b43dfe6394fd04b0302f5a261e1cc3e5 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Thu, 25 Oct 2012 13:26:39 +0200 Subject: ARM: dts: imx53: pinctl update This patch supplements pinctl support on i.MX53. Signed-off-by: Roland Stigge Acked-by: Sascha Hauer Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index a5dd4ce..8b33195 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -320,6 +320,24 @@ }; }; + can1 { + pinctrl_can1_1: can1grp-1 { + fsl,pins = < + 847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */ + 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */ + >; + }; + }; + + can2 { + pinctrl_can2_1: can2grp-1 { + fsl,pins = < + 67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */ + 74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */ + >; + }; + }; + i2c1 { pinctrl_i2c1_1: i2c1grp-1 { fsl,pins = < @@ -338,6 +356,15 @@ }; }; + i2c3 { + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + 1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */ + 1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */ + >; + }; + }; + uart1 { pinctrl_uart1_1: uart1grp-1 { fsl,pins = < @@ -373,6 +400,25 @@ >; }; }; + + uart4 { + pinctrl_uart4_1: uart4grp-1 { + fsl,pins = < + 11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */ + 18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */ + >; + }; + }; + + uart5 { + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + 24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */ + 31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */ + >; + }; + }; + }; uart1: serial@53fbc000 { -- cgit v0.10.2 From 82c45705743c8f9e9662bc42f02d34731f0a24df Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Mon, 12 Nov 2012 16:26:18 +0800 Subject: ARM: dts: imx6q-sabresd: add volume up/down gpio keys Add volume up/down gpio keys support in imx6q-sabresd.dts. Signed-off-by: Liu Ying Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts index e596c28c..a424025 100644 --- a/arch/arm/boot/dts/imx6q-sabresd.dts +++ b/arch/arm/boot/dts/imx6q-sabresd.dts @@ -38,6 +38,8 @@ hog { pinctrl_hog: hoggrp { fsl,pins = < + 1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */ + 1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */ 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */ 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */ 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */ @@ -73,4 +75,20 @@ }; }; }; + + gpio-keys { + compatible = "gpio-keys"; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 4 0>; + linux,code = <115>; /* KEY_VOLUMEUP */ + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 5 0>; + linux,code = <114>; /* KEY_VOLUMEDOWN */ + }; + }; }; -- cgit v0.10.2 From 7b7d6727344a2a7727255d61fa1bd3ff447c4f6c Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 15 Nov 2012 09:31:52 +0100 Subject: ARM i.MX dts: Consistently add labels to devicenodes Having labels before each node allows board bindings to reference to nodes by using the &nodename {} notation. This way boards do not have to resemble the whole devicetree layout. Due to less indention needed the board files also get better readability. Since the label make the documentation behind the nodes unnecessary it is removed. Signed-off-by: Sascha Hauer Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 67d6727..b8d3905 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -58,7 +58,7 @@ reg = <0x10000000 0x10000000>; ranges; - wdog@10002000 { + wdog: wdog@10002000 { compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; reg = <0x10002000 0x4000>; interrupts = <27>; @@ -218,7 +218,8 @@ status = "disabled"; }; }; - nand@d8000000 { + + nfc: nand@d8000000 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 0bc8ae7..1fdee31 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -76,14 +76,14 @@ reg = <0x70000000 0x40000>; ranges; - esdhc@70004000 { /* ESDHC1 */ + esdhc1: esdhc@70004000 { compatible = "fsl,imx51-esdhc"; reg = <0x70004000 0x4000>; interrupts = <1>; status = "disabled"; }; - esdhc@70008000 { /* ESDHC2 */ + esdhc2: esdhc@70008000 { compatible = "fsl,imx51-esdhc"; reg = <0x70008000 0x4000>; interrupts = <2>; @@ -98,7 +98,7 @@ status = "disabled"; }; - ecspi@70010000 { /* ECSPI1 */ + ecspi1: ecspi@70010000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx51-ecspi"; @@ -116,7 +116,7 @@ status = "disabled"; }; - esdhc@70020000 { /* ESDHC3 */ + esdhc3: esdhc@70020000 { compatible = "fsl,imx51-esdhc"; reg = <0x70020000 0x4000>; interrupts = <3>; @@ -124,7 +124,7 @@ status = "disabled"; }; - esdhc@70024000 { /* ESDHC4 */ + esdhc4: esdhc@70024000 { compatible = "fsl,imx51-esdhc"; reg = <0x70024000 0x4000>; interrupts = <4>; @@ -133,28 +133,28 @@ }; }; - usb@73f80000 { + usbotg: usb@73f80000 { compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80000 0x0200>; interrupts = <18>; status = "disabled"; }; - usb@73f80200 { + usbh1: usb@73f80200 { compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80200 0x0200>; interrupts = <14>; status = "disabled"; }; - usb@73f80400 { + usbh2: usb@73f80400 { compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80400 0x0200>; interrupts = <16>; status = "disabled"; }; - usb@73f80600 { + usbh3: usb@73f80600 { compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80600 0x0200>; interrupts = <17>; @@ -201,20 +201,20 @@ #interrupt-cells = <2>; }; - wdog@73f98000 { /* WDOG1 */ + wdog1: wdog@73f98000 { compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f98000 0x4000>; interrupts = <58>; }; - wdog@73f9c000 { /* WDOG2 */ + wdog2: wdog@73f9c000 { compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f9c000 0x4000>; interrupts = <59>; status = "disabled"; }; - iomuxc@73fa8000 { + iomuxc: iomuxc@73fa8000 { compatible = "fsl,imx51-iomuxc"; reg = <0x73fa8000 0x4000>; @@ -352,7 +352,7 @@ reg = <0x80000000 0x10000000>; ranges; - ecspi@83fac000 { /* ECSPI2 */ + ecspi2: ecspi@83fac000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx51-ecspi"; @@ -361,14 +361,14 @@ status = "disabled"; }; - sdma@83fb0000 { + sdma: sdma@83fb0000 { compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; reg = <0x83fb0000 0x4000>; interrupts = <6>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; }; - cspi@83fc0000 { + cspi: cspi@83fc0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; @@ -377,7 +377,7 @@ status = "disabled"; }; - i2c@83fc4000 { /* I2C2 */ + i2c2: i2c@83fc4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; @@ -386,7 +386,7 @@ status = "disabled"; }; - i2c@83fc8000 { /* I2C1 */ + i2c1: i2c@83fc8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; @@ -404,13 +404,13 @@ status = "disabled"; }; - audmux@83fd0000 { + audmux: audmux@83fd0000 { compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; reg = <0x83fd0000 0x4000>; status = "disabled"; }; - nand@83fdb000 { + nfc: nand@83fdb000 { compatible = "fsl,imx51-nand"; reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; interrupts = <8>; @@ -426,7 +426,7 @@ status = "disabled"; }; - ethernet@83fec000 { + fec: ethernet@83fec000 { compatible = "fsl,imx51-fec", "fsl,imx27-fec"; reg = <0x83fec000 0x4000>; interrupts = <87>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 8b33195..f45d4b1 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -81,7 +81,7 @@ reg = <0x50000000 0x40000>; ranges; - esdhc@50004000 { /* ESDHC1 */ + esdhc1: esdhc@50004000 { compatible = "fsl,imx53-esdhc"; reg = <0x50004000 0x4000>; interrupts = <1>; @@ -89,7 +89,7 @@ status = "disabled"; }; - esdhc@50008000 { /* ESDHC2 */ + esdhc2: esdhc@50008000 { compatible = "fsl,imx53-esdhc"; reg = <0x50008000 0x4000>; interrupts = <2>; @@ -104,7 +104,7 @@ status = "disabled"; }; - ecspi@50010000 { /* ECSPI1 */ + ecspi1: ecspi@50010000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; @@ -122,7 +122,7 @@ status = "disabled"; }; - esdhc@50020000 { /* ESDHC3 */ + esdhc3: esdhc@50020000 { compatible = "fsl,imx53-esdhc"; reg = <0x50020000 0x4000>; interrupts = <3>; @@ -130,7 +130,7 @@ status = "disabled"; }; - esdhc@50024000 { /* ESDHC4 */ + esdhc4: esdhc@50024000 { compatible = "fsl,imx53-esdhc"; reg = <0x50024000 0x4000>; interrupts = <4>; @@ -139,28 +139,28 @@ }; }; - usb@53f80000 { + usbotg: usb@53f80000 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80000 0x0200>; interrupts = <18>; status = "disabled"; }; - usb@53f80200 { + usbh1: usb@53f80200 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80200 0x0200>; interrupts = <14>; status = "disabled"; }; - usb@53f80400 { + usbh2: usb@53f80400 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80400 0x0200>; interrupts = <16>; status = "disabled"; }; - usb@53f80600 { + usbh3: usb@53f80600 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80600 0x0200>; interrupts = <17>; @@ -207,20 +207,20 @@ #interrupt-cells = <2>; }; - wdog@53f98000 { /* WDOG1 */ + wdog1: wdog@53f98000 { compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f98000 0x4000>; interrupts = <58>; }; - wdog@53f9c000 { /* WDOG2 */ + wdog2: wdog@53f9c000 { compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f9c000 0x4000>; interrupts = <59>; status = "disabled"; }; - iomuxc@53fa8000 { + iomuxc: iomuxc@53fa8000 { compatible = "fsl,imx53-iomuxc"; reg = <0x53fa8000 0x4000>; @@ -479,7 +479,7 @@ #interrupt-cells = <2>; }; - i2c@53fec000 { /* I2C3 */ + i2c3: i2c@53fec000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; @@ -510,7 +510,7 @@ status = "disabled"; }; - ecspi@63fac000 { /* ECSPI2 */ + ecspi2: ecspi@63fac000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; @@ -519,14 +519,14 @@ status = "disabled"; }; - sdma@63fb0000 { + sdma: sdma@63fb0000 { compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; reg = <0x63fb0000 0x4000>; interrupts = <6>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; }; - cspi@63fc0000 { + cspi: cspi@63fc0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; @@ -535,7 +535,7 @@ status = "disabled"; }; - i2c@63fc4000 { /* I2C2 */ + i2c2: i2c@63fc4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; @@ -544,7 +544,7 @@ status = "disabled"; }; - i2c@63fc8000 { /* I2C1 */ + i2c1: i2c@63fc8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; @@ -562,13 +562,13 @@ status = "disabled"; }; - audmux@63fd0000 { + audmux: audmux@63fd0000 { compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; reg = <0x63fd0000 0x4000>; status = "disabled"; }; - nand@63fdb000 { + nfc: nand@63fdb000 { compatible = "fsl,imx53-nand"; reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; interrupts = <8>; @@ -584,7 +584,7 @@ status = "disabled"; }; - ethernet@63fec000 { + fec: ethernet@63fec000 { compatible = "fsl,imx53-fec", "fsl,imx25-fec"; reg = <0x63fec000 0x4000>; interrupts = <87>; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 1565aea..6dfeaed 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -108,7 +108,7 @@ clocks = <&clks 106>; }; - gpmi-nand@00112000 { + nfc: gpmi-nand@00112000 { compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; @@ -152,12 +152,12 @@ reg = <0x02000000 0x40000>; ranges; - spdif@02004000 { + spdif: spdif@02004000 { reg = <0x02004000 0x4000>; interrupts = <0 52 0x04>; }; - ecspi@02008000 { /* eCSPI1 */ + ecspi1: ecspi@02008000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -168,7 +168,7 @@ status = "disabled"; }; - ecspi@0200c000 { /* eCSPI2 */ + ecspi2: ecspi@0200c000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -179,7 +179,7 @@ status = "disabled"; }; - ecspi@02010000 { /* eCSPI3 */ + ecspi3: ecspi@02010000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -190,7 +190,7 @@ status = "disabled"; }; - ecspi@02014000 { /* eCSPI4 */ + ecspi4: ecspi@02014000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -201,7 +201,7 @@ status = "disabled"; }; - ecspi@02018000 { /* eCSPI5 */ + ecspi5: ecspi@02018000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -221,7 +221,7 @@ status = "disabled"; }; - esai@02024000 { + esai: esai@02024000 { reg = <0x02024000 0x4000>; interrupts = <0 51 0x04>; }; @@ -256,7 +256,7 @@ status = "disabled"; }; - asrc@02034000 { + asrc: asrc@02034000 { reg = <0x02034000 0x4000>; interrupts = <0 50 0x04>; }; @@ -266,7 +266,7 @@ }; }; - vpu@02040000 { + vpu: vpu@02040000 { reg = <0x02040000 0x3c000>; interrupts = <0 3 0x04 0 12 0x04>; }; @@ -275,37 +275,37 @@ reg = <0x0207c000 0x4000>; }; - pwm@02080000 { /* PWM1 */ + pwm1: pwm@02080000 { reg = <0x02080000 0x4000>; interrupts = <0 83 0x04>; }; - pwm@02084000 { /* PWM2 */ + pwm2: pwm@02084000 { reg = <0x02084000 0x4000>; interrupts = <0 84 0x04>; }; - pwm@02088000 { /* PWM3 */ + pwm3: pwm@02088000 { reg = <0x02088000 0x4000>; interrupts = <0 85 0x04>; }; - pwm@0208c000 { /* PWM4 */ + pwm4: pwm@0208c000 { reg = <0x0208c000 0x4000>; interrupts = <0 86 0x04>; }; - flexcan@02090000 { /* CAN1 */ + can1: flexcan@02090000 { reg = <0x02090000 0x4000>; interrupts = <0 110 0x04>; }; - flexcan@02094000 { /* CAN2 */ + can2: flexcan@02094000 { reg = <0x02094000 0x4000>; interrupts = <0 111 0x04>; }; - gpt@02098000 { + gpt: gpt@02098000 { compatible = "fsl,imx6q-gpt"; reg = <0x02098000 0x4000>; interrupts = <0 55 0x04>; @@ -381,19 +381,19 @@ #interrupt-cells = <2>; }; - kpp@020b8000 { + kpp: kpp@020b8000 { reg = <0x020b8000 0x4000>; interrupts = <0 82 0x04>; }; - wdog@020bc000 { /* WDOG1 */ + wdog1: wdog@020bc000 { compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <0 80 0x04>; clocks = <&clks 0>; }; - wdog@020c0000 { /* WDOG2 */ + wdog2: wdog@020c0000 { compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <0 81 0x04>; @@ -525,23 +525,23 @@ }; }; - epit@020d0000 { /* EPIT1 */ + epit1: epit@020d0000 { /* EPIT1 */ reg = <0x020d0000 0x4000>; interrupts = <0 56 0x04>; }; - epit@020d4000 { /* EPIT2 */ + epit2: epit@020d4000 { /* EPIT2 */ reg = <0x020d4000 0x4000>; interrupts = <0 57 0x04>; }; - src@020d8000 { + src: src@020d8000 { compatible = "fsl,imx6q-src"; reg = <0x020d8000 0x4000>; interrupts = <0 91 0x04 0 96 0x04>; }; - gpc@020dc000 { + gpc: gpc@020dc000 { compatible = "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; interrupts = <0 89 0x04 0 90 0x04>; @@ -552,7 +552,7 @@ reg = <0x020e0000 0x38>; }; - iomuxc@020e0000 { + iomuxc: iomuxc@020e0000 { compatible = "fsl,imx6q-iomuxc"; reg = <0x020e0000 0x4000>; @@ -764,17 +764,17 @@ }; }; - dcic@020e4000 { /* DCIC1 */ + dcic1: dcic@020e4000 { reg = <0x020e4000 0x4000>; interrupts = <0 124 0x04>; }; - dcic@020e8000 { /* DCIC2 */ + dcic2: dcic@020e8000 { reg = <0x020e8000 0x4000>; interrupts = <0 125 0x04>; }; - sdma@020ec000 { + sdma: sdma@020ec000 { compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = <0 2 0x04>; @@ -800,7 +800,7 @@ reg = <0x0217c000 0x4000>; }; - usb@02184000 { /* USB OTG */ + usbotg: usb@02184000 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; interrupts = <0 43 0x04>; @@ -810,7 +810,7 @@ status = "disabled"; }; - usb@02184200 { /* USB1 */ + usbh1: usb@02184200 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; interrupts = <0 40 0x04>; @@ -820,7 +820,7 @@ status = "disabled"; }; - usb@02184400 { /* USB2 */ + usbh2: usb@02184400 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184400 0x200>; interrupts = <0 41 0x04>; @@ -829,7 +829,7 @@ status = "disabled"; }; - usb@02184600 { /* USB3 */ + usbh3: usb@02184600 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184600 0x200>; interrupts = <0 42 0x04>; @@ -838,14 +838,14 @@ status = "disabled"; }; - usbmisc: usbmisc@02184800 { + usbmisc: usbmisc: usbmisc@02184800 { #index-cells = <1>; compatible = "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; clocks = <&clks 162>; }; - ethernet@02188000 { + fec: ethernet@02188000 { compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; interrupts = <0 118 0x04 0 119 0x04>; @@ -859,7 +859,7 @@ interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; }; - usdhc@02190000 { /* uSDHC1 */ + usdhc1: usdhc@02190000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02190000 0x4000>; interrupts = <0 22 0x04>; @@ -869,7 +869,7 @@ status = "disabled"; }; - usdhc@02194000 { /* uSDHC2 */ + usdhc2: usdhc@02194000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02194000 0x4000>; interrupts = <0 23 0x04>; @@ -879,7 +879,7 @@ status = "disabled"; }; - usdhc@02198000 { /* uSDHC3 */ + usdhc3: usdhc@02198000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02198000 0x4000>; interrupts = <0 24 0x04>; @@ -889,7 +889,7 @@ status = "disabled"; }; - usdhc@0219c000 { /* uSDHC4 */ + usdhc4: usdhc@0219c000 { compatible = "fsl,imx6q-usdhc"; reg = <0x0219c000 0x4000>; interrupts = <0 25 0x04>; @@ -899,7 +899,7 @@ status = "disabled"; }; - i2c@021a0000 { /* I2C1 */ + i2c1: i2c@021a0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; @@ -909,7 +909,7 @@ status = "disabled"; }; - i2c@021a4000 { /* I2C2 */ + i2c2: i2c@021a4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; @@ -919,7 +919,7 @@ status = "disabled"; }; - i2c@021a8000 { /* I2C3 */ + i2c3: i2c@021a8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; @@ -933,12 +933,12 @@ reg = <0x021ac000 0x4000>; }; - mmdc@021b0000 { /* MMDC0 */ + mmdc0: mmdc@021b0000 { /* MMDC0 */ compatible = "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; }; - mmdc@021b4000 { /* MMDC1 */ + mmdc1: mmdc@021b4000 { /* MMDC1 */ reg = <0x021b4000 0x4000>; }; @@ -966,7 +966,7 @@ interrupts = <0 109 0x04>; }; - audmux@021d8000 { + audmux: audmux@021d8000 { compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; reg = <0x021d8000 0x4000>; status = "disabled"; -- cgit v0.10.2 From b29b3e6f6c5a71a48475ac5ea7015ff267d60af8 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 23 Oct 2012 19:00:39 +0800 Subject: ARM: imx6q: print silicon version on boot i.MX6Q has 3 revisions 1.0, 1.1 and 1.2. Print revision on boot. Signed-off-by: Drew Moseley [drew: add proper error checking for function imx6q_revision()] Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 978b6dd..9511142 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -38,6 +38,40 @@ #include "cpuidle.h" #include "hardware.h" +#define IMX6Q_ANALOG_DIGPROG 0x260 + +static int imx6q_revision(void) +{ + struct device_node *np; + void __iomem *base; + static u32 rev; + + if (!rev) { + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); + if (!np) + return IMX_CHIP_REVISION_UNKNOWN; + base = of_iomap(np, 0); + if (!base) { + of_node_put(np); + return IMX_CHIP_REVISION_UNKNOWN; + } + rev = readl_relaxed(base + IMX6Q_ANALOG_DIGPROG); + iounmap(base); + of_node_put(np); + } + + switch (rev & 0xff) { + case 0: + return IMX_CHIP_REVISION_1_0; + case 1: + return IMX_CHIP_REVISION_1_1; + case 2: + return IMX_CHIP_REVISION_1_2; + default: + return IMX_CHIP_REVISION_UNKNOWN; + } +} + void imx6q_restart(char mode, const char *cmd) { struct device_node *np; @@ -192,6 +226,7 @@ static void __init imx6q_timer_init(void) { mx6q_clocks_init(); twd_local_timer_of_register(); + imx_print_silicon_rev("i.MX6Q", imx6q_revision()); } static struct sys_timer imx6q_timer = { -- cgit v0.10.2 From 96efb44e471250592ee865ce5b870bc6f860921f Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 23 Oct 2012 19:44:34 +0800 Subject: ARM: imx6q: select ARM and PL310 errata ARM core r2p10 and PL310 r3p2 are integrated on imx6q. Select corresponding errata. Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 01bf72c..0737269 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -832,6 +832,11 @@ config SOC_IMX6Q select ARCH_HAS_CPUFREQ select ARCH_HAS_OPP select ARM_CPU_SUSPEND if PM + select ARM_ERRATA_743622 + select ARM_ERRATA_751472 + select ARM_ERRATA_754322 + select ARM_ERRATA_764369 if SMP + select ARM_ERRATA_775420 select ARM_GIC select COMMON_CLK select CPU_V7 @@ -843,6 +848,9 @@ config SOC_IMX6Q select MFD_SYSCON select PINCTRL select PINCTRL_IMX6Q + select PL310_ERRATA_588369 if CACHE_PL310 + select PL310_ERRATA_727915 if CACHE_PL310 + select PL310_ERRATA_769419 if CACHE_PL310 select PM_OPP if PM help -- cgit v0.10.2 From 4e556c046df2bd8d6eef6403c25bf8e52f64be93 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 7 Oct 2012 14:16:23 -0300 Subject: ARM: mxs_defconfig: Improve USB related support Select the following USB related options: - USB Ethernet adapter (needed for mx23-olinuxino) - Native language support (needed for mounting USB pen drives, for example) Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 048aaca..7bf5351 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig @@ -61,6 +61,8 @@ CONFIG_MTD_NAND_GPMI_NAND=y CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_ENC28J60=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_SMSC95XX=y # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_WLAN is not set @@ -158,6 +160,10 @@ CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y CONFIG_PRINTK_TIME=y CONFIG_FRAME_WARN=2048 CONFIG_MAGIC_SYSRQ=y -- cgit v0.10.2 From 632506a21a3b5f0596e89d55cda6b482bec331a3 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Mon, 12 Nov 2012 21:28:33 +0100 Subject: Add device tree file for the armadeus apf27 Signed-off-by: Philippe Reynes Signed-off-by: Eric Jarrige Signed-off-by: Sascha Hauer diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts new file mode 100644 index 0000000..c0327c0 --- /dev/null +++ b/arch/arm/boot/dts/imx27-apf27.dts @@ -0,0 +1,89 @@ +/* + * Copyright 2012 Philippe Reynes + * Copyright 2012 Armadeus Systems + * + * Based on code which is: Copyright 2012 Sascha Hauer, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx27.dtsi" + +/ { + model = "Armadeus Systems APF27 module"; + compatible = "armadeus,imx27-apf27", "fsl,imx27"; + + memory { + reg = <0xa0000000 0x04000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc26m { + compatible = "fsl,imx-osc26m", "fixed-clock"; + clock-frequency = <0>; + }; + }; + + soc { + aipi@10000000 { + serial@1000a000 { + status = "okay"; + }; + + ethernet@1002b000 { + status = "okay"; + }; + }; + + nand@d8000000 { + status = "okay"; + nand-bus-width = <16>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "env"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "env2"; + reg = <0x180000 0x80000>; + }; + + partition@200000 { + label = "firmware"; + reg = <0x200000 0x80000>; + }; + + partition@280000 { + label = "dtb"; + reg = <0x280000 0x80000>; + }; + + partition@300000 { + label = "kernel"; + reg = <0x300000 0x500000>; + }; + + partition@800000 { + label = "rootfs"; + reg = <0x800000 0xf800000>; + }; + }; + }; +}; -- cgit v0.10.2 From 8cf70f3dc04a9303e73eecd523550c647e5ddbd0 Mon Sep 17 00:00:00 2001 From: Fabio Porcedda Date: Mon, 12 Nov 2012 09:09:29 +0100 Subject: ARM: at91: dt: evk-pro3: enable uart0 and uart2 Signed-off-by: Fabio Porcedda Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts index b7354e6..cf98b42 100644 --- a/arch/arm/boot/dts/evk-pro3.dts +++ b/arch/arm/boot/dts/evk-pro3.dts @@ -22,6 +22,14 @@ status = "okay"; }; + usart0: serial@fffb0000 { + status = "okay"; + }; + + usart2: serial@fffb8000 { + status = "okay"; + }; + usb1: gadget@fffa4000 { atmel,vbus-gpio = <&pioC 5 0>; status = "okay"; -- cgit v0.10.2 From be49bbae13ba9128ac69dd4b98027f6412155abe Mon Sep 17 00:00:00 2001 From: Fabio Porcedda Date: Mon, 12 Nov 2012 09:37:25 +0100 Subject: watchdog: at91sam9_wdt: add device tree support Tested on an at91sam9260 board (evk-pro3) Signed-off-by: Fabio Porcedda Signed-off-by: Nicolas Ferre diff --git a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt new file mode 100644 index 0000000..2957ebb --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt @@ -0,0 +1,15 @@ +* Atmel Watchdog Timers + +** at91sam9-wdt + +Required properties: +- compatible: must be "atmel,at91sam9260-wdt". +- reg: physical base address of the controller and length of memory mapped + region. + +Example: + + watchdog@fffffd40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffd40 0x10>; + }; diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index 05e1be8..dc42e44 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -32,6 +32,7 @@ #include #include #include +#include #include "at91sam9_wdt.h" @@ -302,11 +303,21 @@ static int __exit at91wdt_remove(struct platform_device *pdev) return res; } +#if defined(CONFIG_OF) +static const struct of_device_id at91_wdt_dt_ids[] __initconst = { + { .compatible = "atmel,at91sam9260-wdt" }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, at91_wdt_dt_ids); +#endif + static struct platform_driver at91wdt_driver = { .remove = __exit_p(at91wdt_remove), .driver = { .name = "at91_wdt", .owner = THIS_MODULE, + .of_match_table = of_match_ptr(at91_wdt_dt_ids), }, }; -- cgit v0.10.2 From 7492e7ca0f954e26b3d0d44374240b66c21427e9 Mon Sep 17 00:00:00 2001 From: Fabio Porcedda Date: Mon, 12 Nov 2012 09:37:26 +0100 Subject: ARM: at91/dts: add at91sam9_wdt driver to at91sam926x, at91sam9g45 Tested on an at91sam9260 board (evk-pro3). Signed-off-by: Fabio Porcedda Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index d410581..bfb5bb6 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -246,6 +246,12 @@ trigger-external; }; }; + + watchdog@fffffd40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffd40 0x10>; + status = "disabled"; + }; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 3e6e5c1..ff54612 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -195,6 +195,12 @@ #size-cells = <0>; status = "disabled"; }; + + watchdog@fffffd40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffd40 0x10>; + status = "disabled"; + }; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 3add030..a98c00a 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -262,6 +262,12 @@ trigger-value = <0x6>; }; }; + + watchdog@fffffd40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffd40 0x10>; + status = "disabled"; + }; }; nand0: nand@40000000 { -- cgit v0.10.2 From 824b43968fed4b5a200cfef06129c0470eef306a Mon Sep 17 00:00:00 2001 From: Fabio Porcedda Date: Mon, 12 Nov 2012 09:37:27 +0100 Subject: ARM: at91/dts: evk-pro3: enable watchdog Tested on evk-pro3. Signed-off-by: Fabio Porcedda Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts index cf98b42..96e50f5 100644 --- a/arch/arm/boot/dts/evk-pro3.dts +++ b/arch/arm/boot/dts/evk-pro3.dts @@ -34,6 +34,10 @@ atmel,vbus-gpio = <&pioC 5 0>; status = "okay"; }; + + watchdog@fffffd40 { + status = "okay"; + }; }; usb0: ohci@00500000 { -- cgit v0.10.2 From 20ffbd7d6b357ee2f8a607c63805fb2c1f78effb Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 9 Nov 2012 16:58:11 -0700 Subject: ARM: tegra: harmony: enable HDMI port Enable host1x, and the HDMI output. Harmony also has an optional LCD, and a VGA output. The former isn't enabled due to potential issues with having multiple outputs enabled. The latter isn't enabled since the driver doesn't support VGA yet anyway. Correct DDC I2C frequency to 100KHz. Based on work by Thierry Reding for TrimSlice. Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index a3f2f38..43eb72a 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -10,6 +10,18 @@ reg = <0x00000000 0x40000000>; }; + host1x { + hdmi { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + }; + }; + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -262,9 +274,9 @@ }; }; - i2c@7000c400 { + hdmi_ddc: i2c@7000c400 { status = "okay"; - clock-frequency = <400000>; + clock-frequency = <100000>; }; i2c@7000c500 { @@ -369,13 +381,13 @@ regulator-max-microvolt = <1800000>; }; - ldo7 { + hdmi_vdd_reg: ldo7 { regulator-name = "vdd_ldo7,avdd_hdmi"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - ldo8 { + hdmi_pll_reg: ldo8 { regulator-name = "vdd_ldo8,avdd_hdmi_pll"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; -- cgit v0.10.2 From dced3e3ee5833109c04ecf8687ae44960c65ca73 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 20 Sep 2012 10:39:20 +0200 Subject: ARM: tegra: trimslice: enable HDMI port Enable host1x, and the HDMI output. Harmony also has a DVI port with an HDMI form-factor connector, driven by Tegra's LVDS output. This isn't enabled yet, due to potential issues with having multiple outputs enabled. Correct DDC I2C frequency to 100KHz. Add dummy/fixed regulators to satisfy the HDMI driver. Signed-off-by: Thierry Reding [swarren: add commit description, remove enable of DVI port] Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index f4e0428..b70b4cb 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -10,6 +10,18 @@ reg = <0x00000000 0x40000000>; }; + host1x { + hdmi { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + }; + }; + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -249,9 +261,9 @@ clock-frequency = <216000000>; }; - i2c@7000c000 { + dvi_ddc: i2c@7000c000 { status = "okay"; - clock-frequency = <400000>; + clock-frequency = <100000>; }; spi@7000c380 { @@ -264,9 +276,9 @@ }; }; - i2c@7000c400 { + hdmi_ddc: i2c@7000c400 { status = "okay"; - clock-frequency = <400000>; + clock-frequency = <100000>; }; i2c@7000c500 { @@ -310,6 +322,30 @@ bus-width = <4>; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_vdd_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + hdmi_pll_reg: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + sound { compatible = "nvidia,tegra-audio-trimslice"; nvidia,i2s-controller = <&tegra_i2s1>; -- cgit v0.10.2 From e6f097960621828bdce238aef7a7fc5404bfca71 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 16 Nov 2012 16:56:50 +0100 Subject: ARM: tegra: tamonten: Add host1x support Hook up the required regulators, I2C DDC adapter and hotplug detect GPIO to the Tamonten HDMI output. Carrier boards still need to explicitly enable the output to use it. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 95df80e..a239ccd 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -8,6 +8,16 @@ reg = <0x00000000 0x20000000>; }; + host1x { + hdmi { + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + }; + }; + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -292,7 +302,7 @@ pinctrl-1 = <&state_i2cmux_pta>; pinctrl-2 = <&state_i2cmux_idle>; - i2c@0 { + hdmi_ddc: i2c@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; @@ -407,13 +417,13 @@ regulator-max-microvolt = <2850000>; }; - ldo7 { + hdmi_vdd_reg: ldo7 { regulator-name = "vdd_ldo7,avdd_hdmi"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - ldo8 { + hdmi_pll_reg: ldo8 { regulator-name = "vdd_ldo8,avdd_hdmi_pll"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; -- cgit v0.10.2 From 358f88937dad397bca25b12118870b06f9f47df1 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 16 Nov 2012 16:56:51 +0100 Subject: ARM: tegra: plutux: Enable HDMI output Enable the HDMI output found on Plutux boards. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts index 331a3ef..2894800 100644 --- a/arch/arm/boot/dts/tegra20-plutux.dts +++ b/arch/arm/boot/dts/tegra20-plutux.dts @@ -6,6 +6,12 @@ model = "Avionic Design Plutux board"; compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; + host1x { + hdmi { + status = "okay"; + }; + }; + i2c@7000c000 { wm8903: wm8903@1a { compatible = "wlf,wm8903"; -- cgit v0.10.2 From cab2ed62fe378be22c9de12ff8a616622b68c70c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 16 Nov 2012 16:56:52 +0100 Subject: ARM: tegra: tec: Enable HDMI output Enable the HDMI output found on Tamonten Evaluation Carrier boards. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts index 916bec1..402b210 100644 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -6,6 +6,12 @@ model = "Avionic Design Tamonten Evaluation Carrier"; compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; + host1x { + hdmi { + status = "okay"; + }; + }; + i2c@7000c000 { wm8903: wm8903@1a { compatible = "wlf,wm8903"; -- cgit v0.10.2 From 2658ef15b27e0fb166f4b7b997b027a223cd0793 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 16 Nov 2012 10:53:04 -0700 Subject: ARM: tegra: whistler: enable HDMI port Enable host1x, and the HDMI output. Whistler also has a DSI-based LCD, and a VGA output. tegradrm doesn't support either of those output types yet. Based on work by Thierry Reding for TrimSlice. Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index 94a71c9..20d576e 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -10,6 +10,18 @@ reg = <0x00000000 0x20000000>; }; + host1x { + hdmi { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + }; + }; + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -246,6 +258,11 @@ clock-frequency = <216000000>; }; + hdmi_ddc: i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + i2c@7000d000 { status = "okay"; clock-frequency = <100000>; @@ -356,7 +373,7 @@ regulator-always-on; }; - ldo6 { + hdmi_pll_reg: ldo6 { regulator-name = "nvvdd_ldo6,avdd_hdmi_pll"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -388,7 +405,7 @@ regulator-always-on; }; - ldo11 { + hdmi_vdd_reg: ldo11 { regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; -- cgit v0.10.2 From 64a574344dadbee5d01819d9d73b594d3cbe448e Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Wed, 7 Nov 2012 08:50:40 +0900 Subject: ARM: dts: Add nodes for pin controllers for exynos4x12 This patch adds nodes for pin controllers available on EXYNOS4X12 SoCs supported by pinctrl-samsung driver. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Acked-by: Thomas Abraham Acked-by: Linus Walleij Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi new file mode 100644 index 0000000..56f4669 --- /dev/null +++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi @@ -0,0 +1,965 @@ +/* + * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/ { + pinctrl@11400000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj1: gpj1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <0x2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_fctl: uart2-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart_audio_a: uart-audio-a { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart3_data: uart3-data { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart_audio_b: uart-audio-b { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpb-0", "gpb-2", "gpb-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpb-0", "gpb-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpb-4", "gpb-6", "gpb-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c5_bus: i2c5-bus { + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm1_bus: pcm1-bus { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + ac97_bus: ac97-bus { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2s2_bus: i2s2-bus { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm2_bus: pcm2-bus { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spdif_bus: spdif-bus { + samsung,pins = "gpc1-0", "gpc1-1"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c6_bus: i2c6-bus { + samsung,pins = "gpc1-3", "gpc1-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; + samsung,pin-function = <5>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + pwm0_out: pwm0-out { + samsung,pins = "gpd0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm1_out: pwm1-out { + samsung,pins = "gpd0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + lcd_ctrl: lcd-ctrl { + samsung,pins = "gpd0-0", "gpd0-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c7_bus: i2c7-bus { + samsung,pins = "gpd0-2", "gpd0-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + pwm2_out: pwm2-out { + samsung,pins = "gpd0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm3_out: pwm3-out { + samsung,pins = "gpd0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpd1-0", "gpd1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + mipi0_clk: mipi0-clk { + samsung,pins = "gpd1-0", "gpd1-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + mipi1_clk: mipi1-clk { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + lcd_clk: lcd-clk { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + lcd_data16: lcd-data-width16 { + samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", + "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", + "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + lcd_data18: lcd-data-width18 { + samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", + "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", + "gpf3-2", "gpf3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + lcd_data24: lcd-data-width24 { + samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", + "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + lcd_ldi: lcd-ldi { + samsung,pins = "gpf3-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_port_a: cam-port-a { + samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", + "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", + "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-3", + "gpj1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl@11000000 { + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk1: gpk1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk2: gpk2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk3: gpk3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl0: gpl0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl1: gpl1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl2: gpl2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm0: gpm0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm1: gpm1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm2: gpm2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm3: gpm3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm4: gpm4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; + #interrupt-cells = <2>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + #interrupt-cells = <2>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpk0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpk0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpk0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpk0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd4_clk: sd4-clk { + samsung,pins = "gpk0-0"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd4_cmd: sd4-cmd { + samsung,pins = "gpk0-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd4_cd: sd4-cd { + samsung,pins = "gpk0-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd4_bus1: sd4-bus-width1 { + samsung,pins = "gpk0-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd4_bus4: sd4-bus-width4 { + samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd4_bus8: sd4-bus-width8 { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = <3>; + samsung,pin-pud = <4>; + samsung,pin-drv = <0>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpk1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpk1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd1_cd: sd1-cd { + samsung,pins = "gpk1-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpk1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpk2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpk2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpk2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpk2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd2_bus8: sd2-bus-width8 { + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd3_clk: sd3-clk { + samsung,pins = "gpk3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd3_cmd: sd3-cmd { + samsung,pins = "gpk3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd3_cd: sd3-cd { + samsung,pins = "gpk3-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd3_bus1: sd3-bus-width1 { + samsung,pins = "gpk3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd3_bus4: sd3-bus-width4 { + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + keypad_col0: keypad-col0 { + samsung,pins = "gpl2-0"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + keypad_col1: keypad-col1 { + samsung,pins = "gpl2-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + keypad_col2: keypad-col2 { + samsung,pins = "gpl2-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + keypad_col3: keypad-col3 { + samsung,pins = "gpl2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + keypad_col4: keypad-col4 { + samsung,pins = "gpl2-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + keypad_col5: keypad-col5 { + samsung,pins = "gpl2-5"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + keypad_col6: keypad-col6 { + samsung,pins = "gpl2-6"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + keypad_col7: keypad-col7 { + samsung,pins = "gpl2-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_port_b: cam-port-b { + samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", + "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", + "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1", + "gpm2-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + eint0: ext-int0 { + samsung,pins = "gpx0-0"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + eint8: ext-int8 { + samsung,pins = "gpx1-0"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + eint15: ext-int15 { + samsung,pins = "gpx1-7"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + eint16: ext-int16 { + samsung,pins = "gpx2-0"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + eint31: ext-int31 { + samsung,pins = "gpx3-7"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl@03860000 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2s0_bus: i2s0-bus { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4", "gpz-5", "gpz-6"; + samsung,pin-function = <0x2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm0_bus: pcm0-bus { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4"; + samsung,pin-function = <0x3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl@106E0000 { + gpv0: gpv0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv1: gpv1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv2: gpv2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv3: gpv3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv4: gpv4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + c2c_bus: c2c-bus { + samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", + "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", + "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", + "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7", + "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", + "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", + "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", + "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7", + "gpv4-0", "gpv4-1"; + samsung,pin-function = <0x2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 906fe84..179a62e 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -18,8 +18,16 @@ */ /include/ "exynos4.dtsi" +/include/ "exynos4x12-pinctrl.dtsi" / { + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + }; + combiner:interrupt-controller@10440000 { interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, @@ -27,4 +35,35 @@ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>; }; + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,pinctrl-exynos4x12"; + reg = <0x11400000 0x1000>; + interrupts = <0 47 0>; + }; + + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,pinctrl-exynos4x12"; + reg = <0x11000000 0x1000>; + interrupts = <0 46 0>; + + wakup_eint: wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; + }; + + pinctrl_2: pinctrl@03860000 { + compatible = "samsung,pinctrl-exynos4x12"; + reg = <0x03860000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <10 0>; + }; + + pinctrl_3: pinctrl@106E0000 { + compatible = "samsung,pinctrl-exynos4x12"; + reg = <0x106E0000 0x1000>; + interrupts = <0 72 0>; + }; }; -- cgit v0.10.2 From 3fcdc0555f5043eded6312efce14cd8dd66f30f8 Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Mon, 19 Nov 2012 22:25:59 -0800 Subject: ARM: davinci: move dtb targets to common location The dtb targets belong in arch/arm/boot/dts/Makefile now, so move the newly added davinci targets there. Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7fd1336..a008e63 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -17,6 +17,8 @@ dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \ usb_a9263.dtb \ usb_a9g20.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb +dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ + da850-evm.dtb dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ dove-cubox.dtb \ dove-dove-db.dtb diff --git a/arch/arm/mach-davinci/Makefile.boot b/arch/arm/mach-davinci/Makefile.boot index 5c5a95a..04a6c4e 100644 --- a/arch/arm/mach-davinci/Makefile.boot +++ b/arch/arm/mach-davinci/Makefile.boot @@ -11,5 +11,3 @@ else params_phys-y := 0x80000100 initrd_phys-y := 0x80800000 endif - -dtb-$(CONFIG_MACH_DA8XX_DT) += da850-enbw-cmc.dtb da850-evm.dtb -- cgit v0.10.2 From e92501263c03144a553327ac95cf9a760a6661bc Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Tue, 20 Nov 2012 16:26:17 +0900 Subject: ARM: dts: Update for pinctrl-samsung driver for exynos4210-trats This patch updates all parts of Trats dts related to pin configuration to use new GPIO and pinctrl bindings, instead of (now unsupported on Exynos4) legacy gpio-samsung bindings. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index a21511c..661854b 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -35,7 +35,7 @@ regulator-name = "VMEM_VDD_2.8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&gpk0 2 1 0 0>; + gpio = <&gpk0 2 0>; enable-active-high; }; @@ -43,16 +43,8 @@ bus-width = <8>; non-removable; broken-voltage; - gpios = <&gpk0 0 2 0 3>, - <&gpk0 1 2 0 3>, - <&gpk0 3 2 2 3>, - <&gpk0 4 2 2 3>, - <&gpk0 5 2 2 3>, - <&gpk0 6 2 2 3>, - <&gpk1 3 3 3 3>, - <&gpk1 4 3 3 3>, - <&gpk1 5 3 3 3>, - <&gpk1 6 3 3 3>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; + pinctrl-names = "default"; vmmc-supply = <&vemmc_reg>; status = "okay"; }; @@ -77,8 +69,8 @@ samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; samsung,i2c-max-bus-freq = <100000>; - gpios = <&gpb 6 3 3 0>, - <&gpb 7 3 3 0>; + pinctrl-0 = <&i2c5_bus>; + pinctrl-names = "default"; status = "okay"; max8997_pmic@66 { @@ -93,9 +85,9 @@ max8997,pmic-ignore-gpiodvs-side-effect; max8997,pmic-buck125-default-dvs-idx = <0>; - max8997,pmic-buck125-dvs-gpios = <&gpx0 5 1 0 0>, - <&gpx0 6 1 0 0>, - <&gpl0 0 1 0 0>; + max8997,pmic-buck125-dvs-gpios = <&gpx0 5 0>, + <&gpx0 6 0>, + <&gpl0 0 0>; max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, <1250000>, <1200000>, -- cgit v0.10.2 From 9eb61020a08d8269c2bc9454f7baf42e00b01c87 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Tue, 20 Nov 2012 16:26:17 +0900 Subject: ARM: dts: Add nodes for GPIO keys available on Trats This patch extends dts file of Samsung Trats board to add support for available GPIO keys using gpio-keys driver. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 661854b..dcfa04b 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -65,6 +65,39 @@ status = "okay"; }; + gpio-keys { + compatible = "gpio-keys"; + + vol-down-key { + gpios = <&gpx2 1 1>; + linux,code = <114>; + label = "volume down"; + debounce-interval = <10>; + }; + + vol-up-key { + gpios = <&gpx2 0 1>; + linux,code = <115>; + label = "volume up"; + debounce-interval = <10>; + }; + + power-key { + gpios = <&gpx2 7 1>; + linux,code = <116>; + label = "power"; + debounce-interval = <10>; + gpio-key,wakeup; + }; + + ok-key { + gpios = <&gpx3 5 1>; + linux,code = <352>; + label = "ok"; + debounce-interval = <10>; + }; + }; + i2c@138B0000 { samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; -- cgit v0.10.2 From b74cbbc7b6ecf29265a3dbdbdf257e86b4a1f380 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Tue, 20 Nov 2012 16:26:17 +0900 Subject: ARM: dts: Add node for i2c3 bus for exynos4210-trats This patch adds device tree node for i2c3 bus to device tree source of Samsung Trats board. This bus is used by mms114 touchscreen controller, for which support will be added in separate patch. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index dcfa04b..1d502bd 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -98,6 +98,15 @@ }; }; + i2c@13890000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + status = "okay"; + }; + i2c@138B0000 { samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; -- cgit v0.10.2 From 50528aa1473a2e5d2cb1a82641afa3aa269e3ddc Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Tue, 20 Nov 2012 16:26:18 +0900 Subject: ARM: dts: Add node for touchscreen voltage regulator for exynos4210-trats This patch adds device tree node for a fixed voltage regulator used for touchscreen on Samsung Trats board. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 1d502bd..5dfd231 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -98,6 +98,15 @@ }; }; + tsp_reg: voltage-regulator { + compatible = "regulator-fixed"; + regulator-name = "TSP_FIXED_VOLTAGES"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpl0 3 0>; + enable-active-high; + }; + i2c@13890000 { samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; -- cgit v0.10.2 From 0d09bf69fc9f99f0d56c420acb1abb018292632c Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Tue, 20 Nov 2012 16:26:18 +0900 Subject: ARM: dts: Add node for touchscreen for exynos4210-trats This patch adds a device tree node for the Melfas MMS114-controlled touchscreen present on Samsung Trats board. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 5dfd231..dab2e08 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -114,6 +114,17 @@ pinctrl-0 = <&i2c3_bus>; pinctrl-names = "default"; status = "okay"; + + mms114-touchscreen@48 { + compatible = "melfas,mms114"; + reg = <0x48>; + interrupt-parent = <&gpx0>; + interrupts = <4 2>; + x-size = <720>; + y-size = <1280>; + avdd-supply = <&tsp_reg>; + vdd-supply = <&tsp_reg>; + }; }; i2c@138B0000 { -- cgit v0.10.2 From d36bb0f0401b60f5484700da84a4cf760cd82fe3 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Tue, 20 Nov 2012 20:17:20 +0900 Subject: ARM: dts: Remove broken-voltage property from sdhci node for exynos4210-trats The broken voltage property has been replaced with auto detection based on voltages available on vmmc voltage regulator, so there is no use for it now. This patch removes the now unused property from Trats Device Tree sources. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index dab2e08..c346b64 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -42,7 +42,6 @@ sdhci_emmc: sdhci@12510000 { bus-width = <8>; non-removable; - broken-voltage; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; pinctrl-names = "default"; vmmc-supply = <&vemmc_reg>; -- cgit v0.10.2 From c47d244a646d08e2161b7fa22c5512e7988762ae Mon Sep 17 00:00:00 2001 From: Vasanth Ananthan Date: Tue, 20 Nov 2012 21:02:11 +0900 Subject: ARM: EXYNOS: DT Support for SATA and SATA PHY This patch adds Device Nodes for SATA and SATA PHY device. Signed-off-by: Vasanth Ananthan [kgene.kim@samsung.com: removed address definitions as per comments] Signed-off-by: Kukjin Kim diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt new file mode 100644 index 0000000..37824fa --- /dev/null +++ b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt @@ -0,0 +1,14 @@ +* Samsung SATA PHY Controller + +SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers. +Each SATA PHY controller should have its own node. + +Required properties: +- compatible : compatible list, contains "samsung,exynos5-sata-phy" +- reg : + +Example: + sata@ffe07000 { + compatible = "samsung,exynos5-sata-phy"; + reg = <0xffe07000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt b/Documentation/devicetree/bindings/ata/exynos-sata.txt new file mode 100644 index 0000000..0849f10 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/exynos-sata.txt @@ -0,0 +1,17 @@ +* Samsung AHCI SATA Controller + +SATA nodes are defined to describe on-chip Serial ATA controllers. +Each SATA controller should have its own node. + +Required properties: +- compatible : compatible list, contains "samsung,exynos5-sata" +- interrupts : +- reg : +- samsung,sata-freq : + +Example: + sata@ffe08000 { + compatible = "samsung,exynos5-sata"; + reg = <0xffe08000 0x1000>; + interrupts = <115>; + }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 21d4ccd..3f8c2ab 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -55,6 +55,21 @@ }; }; + i2c@121D0000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <40000>; + samsung,i2c-slave-addr = <0x38>; + + sata-phy { + compatible = "samsung,sata-phy"; + reg = <0x38>; + }; + }; + + sata@122F0000 { + samsung,sata-freq = <66>; + }; + i2c@12C80000 { status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 670dfdb..e913525 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -104,6 +104,17 @@ interrupts = <0 54 0>; }; + sata@122F0000 { + compatible = "samsung,exynos5-sata-ahci"; + reg = <0x122F0000 0x1ff>; + interrupts = <0 115 0>; + }; + + sata-phy@12170000 { + compatible = "samsung,exynos5-sata-phy"; + reg = <0x12170000 0x1ff>; + }; + i2c@12C60000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C60000 0x100>; @@ -168,6 +179,13 @@ #size-cells = <0>; }; + i2c@121D0000 { + compatible = "samsung,exynos5-sata-phy-i2c"; + reg = <0x121D0000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + }; + spi_0: spi@12d20000 { compatible = "samsung,exynos4210-spi"; reg = <0x12d20000 0x100>; diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 4c0f336..a88c19f 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -64,6 +64,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { "exynos4210-spi.1", NULL), OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2, "exynos4210-spi.2", NULL), + OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000, + "exynos5-sata", NULL), + OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000, + "exynos5-sata-phy", NULL), + OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000, + "exynos5-sata-phy-i2c", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), -- cgit v0.10.2 From a04878645f54d238821fff85e46d7603f45a0a1f Mon Sep 17 00:00:00 2001 From: Fadil Berisha Date: Sat, 17 Nov 2012 16:52:32 -0500 Subject: ARM: imx23-olinuxino: Add spi support imx23-olinuxino board has spi pins exposed on external connector. This patch add spi support. Signed-off-by: Fadil Berisha Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts index 8bd56fc..7c43b8e 100644 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/imx23-olinuxino.dts @@ -56,6 +56,15 @@ fsl,pull-up = <0>; }; }; + + ssp1: ssp@80034000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx23-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + }; }; apbx@80040000 { diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 9ca4ca7..83f0019 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -278,6 +278,19 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; + + spi2_pins_a: spi2@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0182 /* MX23_PAD_GPMI_WRN__SSP2_SCK */ + 0x0142 /* MX23_PAD_GPMI_RDY1__SSP2_CMD */ + 0x0002 /* MX23_PAD_GPMI_D00__SSP2_DATA0 */ + 0x0032 /* MX23_PAD_GPMI_D03__SSP2_DATA3 */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; }; digctl@8001c000 { -- cgit v0.10.2 From 160d5f27605f5acac8f426d862e8f8a499eef2b5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 18 Nov 2012 22:08:29 +0100 Subject: ARM: mxs: Add SchulerControl SPS1 DTS file Add DTS file for this custom board. Signed-off-by: Marek Vasut Cc: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b451a79..73f0a61 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -61,6 +61,7 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx28-cfa10049.dtb \ imx28-evk.dtb \ imx28-m28evk.dtb \ + imx28-sps1.dtb \ imx28-tx28.dtb dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ omap3-beagle-xm.dtb \ diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts new file mode 100644 index 0000000..e6cde8a --- /dev/null +++ b/arch/arm/boot/dts/imx28-sps1.dts @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2012 Marek Vasut + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx28.dtsi" + +/ { + model = "SchulerControl GmbH, SC SPS 1"; + compatible = "schulercontrol,imx28-sps1", "fsl,imx28"; + + memory { + reg = <0x40000000 0x08000000>; + }; + + apb@80000000 { + apbh@80000000 { + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0003 /* MX28_PAD_GPMI_D00__GPIO_0_0 */ + 0x0033 /* MX28_PAD_GPMI_D03__GPIO_0_3 */ + 0x0063 /* MX28_PAD_GPMI_D06__GPIO_0_6 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + }; + + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a>; + bus-width = <4>; + status = "okay"; + }; + + ssp2: ssp@80014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "everspin,mr25h256", "mr25h256"; + spi-max-frequency = <40000000>; + reg = <0>; + }; + }; + }; + + apbx@80040000 { + i2c0: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + clock-frequency = <400000>; + status = "okay"; + + rtc: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + eeprom: eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + pagesize = <32>; + }; + }; + + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + + auart0: serial@8006a000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + vbus-supply = <®_usb0_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&usbphy0_pins_b>; + status = "okay"; + }; + + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + status = "okay"; + }; + + mac1: ethernet@800f4000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_usb0_vbus: usb0_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 9 0>; + }; + }; + + leds { + #address-cells = <1>; + #size-cells = <0>; + compatible = "gpio-leds"; + status = "okay"; + + led@1 { + label = "sps1-1:yellow:user"; + gpios = <&gpio0 6 0>; + linux,default-trigger = "heartbeat"; + reg = <0>; + }; + + led@2 { + label = "sps1-2:red:user"; + gpios = <&gpio0 3 0>; + linux,default-trigger = "heartbeat"; + reg = <1>; + }; + + led@3 { + label = "sps1-3:red:user"; + gpios = <&gpio0 0 0>; + default-trigger = "heartbeat"; + reg = <2>; + }; + + }; +}; diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 67ef355..9807037 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -290,6 +290,11 @@ static void __init m28evk_init(void) mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT; } +static void __init sc_sps1_init(void) +{ + enable_clk_enet_out(); +} + static int apx4devkit_phy_fixup(struct phy_device *phy) { phy->dev_flags |= MICREL_PHY_50MHZ_CLK; @@ -414,6 +419,8 @@ static void __init mxs_machine_init(void) cfa10049_init(); else if (of_machine_is_compatible("armadeus,imx28-apf28")) apf28_init(); + else if (of_machine_is_compatible("schulercontrol,imx28-sps1")) + sc_sps1_init(); of_platform_populate(NULL, of_default_bus_match_table, mxs_auxdata_lookup, NULL); -- cgit v0.10.2 From 65d6f6f35cb534913dad0a26099713e2aa0c2820 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 25 Sep 2012 12:04:51 +0100 Subject: ARM: ux500: Move regulator-name properties out to board DTS files Regulator supply names should be allocated by board rather than per SoC, as the same SoC could be wired differently on varying hardware. Here we push all regulator-name allocation out to the dbx5x0 subordinate board files; HREF and Snowball. Requested-by: Mark Brown Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts index a01ac8f..a958482 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -30,5 +30,137 @@ reset-gpio = <&gpio4 15 0x4>; }; }; + + prcmu@80157000 { + db8500-prcmu-regulators { + db8500_vape_reg: db8500_vape { + regulator-name = "db8500-vape"; + }; + + db8500_varm_reg: db8500_varm { + regulator-name = "db8500-varm"; + }; + + db8500_vmodem_reg: db8500_vmodem { + regulator-name = "db8500-vmodem"; + }; + + db8500_vpll_reg: db8500_vpll { + regulator-name = "db8500-vpll"; + }; + + db8500_vsmps1_reg: db8500_vsmps1 { + regulator-name = "db8500-vsmps1"; + }; + + db8500_vsmps2_reg: db8500_vsmps2 { + regulator-name = "db8500-vsmps2"; + }; + + db8500_vsmps3_reg: db8500_vsmps3 { + regulator-name = "db8500-vsmps3"; + }; + + db8500_vrf1_reg: db8500_vrf1 { + regulator-name = "db8500-vrf1"; + }; + + db8500_sva_mmdsp_reg: db8500_sva_mmdsp { + regulator-name = "db8500-sva-mmdsp"; + }; + + db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { + regulator-name = "db8500-sva-mmdsp-ret"; + }; + + db8500_sva_pipe_reg: db8500_sva_pipe { + regulator-name = "db8500_sva_pipe"; + }; + + db8500_sia_mmdsp_reg: db8500_sia_mmdsp { + regulator-name = "db8500_sia_mmdsp"; + }; + + db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { + regulator-name = "db8500-sia-mmdsp-ret"; + }; + + db8500_sia_pipe_reg: db8500_sia_pipe { + regulator-name = "db8500-sia-pipe"; + }; + + db8500_sga_reg: db8500_sga { + regulator-name = "db8500-sga"; + }; + + db8500_b2r2_mcde_reg: db8500_b2r2_mcde { + regulator-name = "db8500-b2r2-mcde"; + }; + + db8500_esram12_reg: db8500_esram12 { + regulator-name = "db8500-esram12"; + }; + + db8500_esram12_ret_reg: db8500_esram12_ret { + regulator-name = "db8500-esram12-ret"; + }; + + db8500_esram34_reg: db8500_esram34 { + regulator-name = "db8500-esram34"; + }; + + db8500_esram34_ret_reg: db8500_esram34_ret { + regulator-name = "db8500-esram34-ret"; + }; + }; + + ab8500@5 { + ab8500-regulators { + ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { + regulator-name = "V-DISPLAY"; + }; + + ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { + regulator-name = "V-eMMC1"; + }; + + ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { + regulator-name = "V-MMC-SD"; + }; + + ab8500_ldo_initcore_reg: ab8500_ldo_initcore { + regulator-name = "V-INTCORE"; + }; + + ab8500_ldo_tvout_reg: ab8500_ldo_tvout { + regulator-name = "V-TVOUT"; + }; + + ab8500_ldo_usb_reg: ab8500_ldo_usb { + regulator-name = "dummy"; + }; + + ab8500_ldo_audio_reg: ab8500_ldo_audio { + regulator-name = "V-AUD"; + }; + + ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { + regulator-name = "V-AMIC1"; + }; + + ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { + regulator-name = "V-AMIC2"; + }; + + ab8500_ldo_dmic_reg: ab8500_ldo_dmic { + regulator-name = "V-DMIC"; + }; + + ab8500_ldo_ana_reg: ab8500_ldo_ana { + regulator-name = "V-CSI/DSI"; + }; + }; + }; + }; }; }; -- cgit v0.10.2 From 7127c57fd35d99849367682d1d67428636ea0a48 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 14 Sep 2012 15:27:41 +0100 Subject: ARM: ux500: Add SDI (MMC) support to the HREF Device Tree Here we add the Device Tree nodes which are required to successfully probe the MMCI driver which will enable the four cards available on ST-Ericsson's HREF hardware development platform. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts index a958482..55f4191 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -31,6 +31,50 @@ }; }; + // External Micro SD slot + sdi0_per1@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + mmc-cap-sd-highspeed; + mmc-cap-mmc-highspeed; + vmmc-supply = <&ab8500_ldo_aux3_reg>; + + cd-gpios = <&tc3589x_gpio 3 0x4>; + + status = "okay"; + }; + + // WLAN SDIO channel + sdi1_per2@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + + status = "okay"; + }; + + // PoP:ed eMMC + sdi2_per3@80005000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <8>; + mmc-cap-mmc-highspeed; + + status = "okay"; + }; + + // On-board eMMC + sdi4_per2@80114000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <8>; + mmc-cap-mmc-highspeed; + vmmc-supply = <&ab8500_ldo_aux2_reg>; + + status = "okay"; + }; + prcmu@80157000 { db8500-prcmu-regulators { db8500_vape_reg: db8500_vape { -- cgit v0.10.2 From 0c32e98fbcbb4002142988e56b6bc387494e783e Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 8 Oct 2012 09:14:13 +0100 Subject: ARM: ux500: Add skeleton DTS file for the u9540 This patch sees the creation of a sparse Device Tree file for ST-Ericsson's latest development board supporting the latest dual-core Cortex-a9 u9540 SoC. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/u9540.dts b/arch/arm/boot/dts/u9540.dts new file mode 100644 index 0000000..0a66f34 --- /dev/null +++ b/arch/arm/boot/dts/u9540.dts @@ -0,0 +1,26 @@ +/* + * Copyright 2012 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "dbx5x0.dtsi" + +/ { + model = "ST-Ericsson U9540 platform with Device Tree"; + compatible = "st-ericsson,u9540"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + soc-u9500 { + }; + +}; -- cgit v0.10.2 From cc3ad84aa00189d557c90f736f51573842ab452a Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 8 Oct 2012 09:19:31 +0100 Subject: ARM: ux500: Add UART support to the u9540 Device Tree Add the 3 UART nodes required to enable serial ports on the u9540. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/u9540.dts b/arch/arm/boot/dts/u9540.dts index 0a66f34..28efe20 100644 --- a/arch/arm/boot/dts/u9540.dts +++ b/arch/arm/boot/dts/u9540.dts @@ -21,6 +21,17 @@ }; soc-u9500 { - }; + uart@80120000 { + status = "okay"; + }; + + uart@80121000 { + status = "okay"; + }; + + uart@80007000 { + status = "okay"; + }; + }; }; -- cgit v0.10.2 From 80c70c68216f78b45e022893753555f54315de78 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 8 Oct 2012 14:09:05 +0100 Subject: ARM: ux500: Enable SDI4 port on the u9540 when booting with Device Tree Here we add the device node for the SDI4 (MMC) port to the u9540 Device Tree source file. This will allow successful probing of the internal MMC storage device when booting with DT enabled. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/u9540.dts b/arch/arm/boot/dts/u9540.dts index 28efe20..2dade76 100644 --- a/arch/arm/boot/dts/u9540.dts +++ b/arch/arm/boot/dts/u9540.dts @@ -21,7 +21,6 @@ }; soc-u9500 { - uart@80120000 { status = "okay"; }; @@ -33,5 +32,16 @@ uart@80007000 { status = "okay"; }; + + // On-board eMMC + sdi4_per2@80114000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <8>; + mmc-cap-mmc-highspeed; + vmmc-supply = <&ab8500_ldo_aux2_reg>; + + status = "okay"; + }; }; }; -- cgit v0.10.2 From 79b1c9e69de27813c7b270b1fbe0880c7b537def Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 10 Oct 2012 09:38:26 +0100 Subject: ARM: ux500: Enable all MMC devices on the u9540 when booting with DT The u9540 supports 3 MMC devices. This patch enables two of them and updates the configuration of the already enabled SDI4 port. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/u9540.dts b/arch/arm/boot/dts/u9540.dts index 2dade76..95892ec 100644 --- a/arch/arm/boot/dts/u9540.dts +++ b/arch/arm/boot/dts/u9540.dts @@ -33,10 +33,35 @@ status = "okay"; }; + // External Micro SD slot + sdi0_per1@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + mmc-cap-sd-highspeed; + mmc-cap-mmc-highspeed; + vmmc-supply = <&ab8500_ldo_aux3_reg>; + + cd-gpios = <&gpio7 6 0x4>; // 230 + cd-inverted; + + status = "okay"; + }; + + + // WLAN SDIO channel + sdi1_per2@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + + status = "okay"; + }; + // On-board eMMC sdi4_per2@80114000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; + max-frequency = <100000000>; bus-width = <8>; mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux2_reg>; -- cgit v0.10.2 From cece5c4009355323c6f453ef6814e7dd85a0f896 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Sat, 3 Nov 2012 13:37:15 +0100 Subject: ARM: ux500: Describe UART platform registering issues more accurately UARTs no longer require call-back information, since the reset call-back was removed in 43b5f0d69291374f602ad8e1817f329573a59010. The only AUXDATA dependencies remaining for UARTs are DMA settings. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 4a0c40a..d2076ce 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -262,11 +262,10 @@ static struct device * __init u8500_of_init_devices(void) static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { /* Requires call-back bindings. */ OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata), - /* Requires DMA and call-back bindings. */ + /* Requires DMA bindings. */ OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat), OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat), - /* Requires DMA bindings. */ OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data), -- cgit v0.10.2 From de0f42beef2a9e6742488c3c35be34d86ad9c2ed Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Wed, 21 Nov 2012 13:31:32 +0900 Subject: ARM: dts: Move the dwmmc aliases from smdk5250 dts to exynos The aliases for dwmmc were placed in the SMDK5250 dts file but really should be common for all exynos5250 boards. Move it to the common CPU file. Signed-off-by: Doug Anderson Acked-by: Olof Johansson Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 3f8c2ab..371182f 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -17,10 +17,6 @@ compatible = "samsung,smdk5250", "samsung,exynos5250"; aliases { - mshc0 = &dwmmc_0; - mshc1 = &dwmmc_1; - mshc2 = &dwmmc_2; - mshc3 = &dwmmc_3; }; memory { @@ -94,7 +90,7 @@ status = "disabled"; }; - dwmmc_0: dwmmc0@12200000 { + dwmmc0@12200000 { num-slots = <1>; supports-highspeed; broken-cd; @@ -115,11 +111,11 @@ }; }; - dwmmc_1: dwmmc1@12210000 { + dwmmc1@12210000 { status = "disabled"; }; - dwmmc_2: dwmmc2@12220000 { + dwmmc2@12220000 { num-slots = <1>; supports-highspeed; fifo-depth = <0x80>; @@ -140,7 +136,7 @@ }; }; - dwmmc_3: dwmmc3@12230000 { + dwmmc3@12230000 { status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index e913525..71a3e0b 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -31,6 +31,10 @@ gsc1 = &gsc_1; gsc2 = &gsc_2; gsc3 = &gsc_3; + mshc0 = &dwmmc_0; + mshc1 = &dwmmc_1; + mshc2 = &dwmmc_2; + mshc3 = &dwmmc_3; }; gic:interrupt-controller@10481000 { @@ -216,7 +220,7 @@ #size-cells = <0>; }; - dwmmc0@12200000 { + dwmmc_0: dwmmc0@12200000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12200000 0x1000>; interrupts = <0 75 0>; @@ -224,7 +228,7 @@ #size-cells = <0>; }; - dwmmc1@12210000 { + dwmmc_1: dwmmc1@12210000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12210000 0x1000>; interrupts = <0 76 0>; @@ -232,7 +236,7 @@ #size-cells = <0>; }; - dwmmc2@12220000 { + dwmmc_2: dwmmc2@12220000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12220000 0x1000>; interrupts = <0 77 0>; @@ -240,7 +244,7 @@ #size-cells = <0>; }; - dwmmc3@12230000 { + dwmmc_3: dwmmc3@12230000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12230000 0x1000>; interrupts = <0 78 0>; -- cgit v0.10.2 From 95e82941b73b4a8811299ad7b639157822c8c59d Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Wed, 21 Nov 2012 13:32:21 +0900 Subject: ARM: dts: Add board dts file for Snow board (ARM Chromebook) This dts file is based on the Snow dts file in the Chromium OS kernel tree with the following changes: * Some details have been updated to match the exynos5250-smdk5250.dts file from linux-next (as of c11068538994430547722dc9fb515a0ceefd5cb9). * This file doesn't include references to hardware whose upstream support isn't quite there yet. That includes most i2c devices. Note that most i2c busses have been included with no devices. The Snow dts file is mostly just an include of the "cros5250" dts file which describes a class of similar boards. Support for other boards has not yet been send upstream. With this file and a change to use UART3 for serial output I can: * Boot to a command line using either SD or EMMC as a root filesystem * See the power button and lid switch using evtest. Signed-off-by: Doug Anderson Acked-by: Olof Johansson Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 36488a5..e70cd37 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -24,7 +24,8 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-trats.dtb \ exynos4412-smdk4412.dtb \ - exynos5250-smdk5250.dtb + exynos5250-smdk5250.dtb \ + exynos5250-snow.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ integratorcp.dtb diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi new file mode 100644 index 0000000..fddd174 --- /dev/null +++ b/arch/arm/boot/dts/cros5250-common.dtsi @@ -0,0 +1,184 @@ +/* + * Common device tree include for all Exynos 5250 boards based off of Daisy. + * + * Copyright (c) 2012 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/ { + aliases { + }; + + memory { + reg = <0x40000000 0x80000000>; + }; + + chosen { + }; + + i2c@12C60000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + gpios = <&gpb3 0 2 3 0>, + <&gpb3 1 2 3 0>; + }; + + i2c@12C70000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + gpios = <&gpb3 2 2 3 0>, + <&gpb3 3 2 3 0>; + }; + + i2c@12C80000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + + /* + * Disabled pullups since external part has its own pullups and + * double-pulling gets us out of spec in some cases. + */ + gpios = <&gpa0 6 3 0 0>, + <&gpa0 7 3 0 0>; + + hdmiddc@50 { + compatible = "samsung,exynos5-hdmiddc"; + reg = <0x50>; + }; + }; + + i2c@12C90000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + gpios = <&gpa1 2 3 3 0>, + <&gpa1 3 3 3 0>; + }; + + i2c@12CA0000 { + status = "disabled"; + }; + + i2c@12CB0000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + gpios = <&gpa2 2 3 3 0>, + <&gpa2 3 3 3 0>; + }; + + i2c@12CC0000 { + status = "disabled"; + }; + + i2c@12CD0000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + gpios = <&gpb2 2 3 3 0>, + <&gpb2 3 3 3 0>; + }; + + i2c@12CE0000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + + hdmiphy@38 { + compatible = "samsung,exynos5-hdmiphy"; + reg = <0x38>; + }; + }; + + dwmmc0@12200000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + fifo-depth = <0x80>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3 3>; + samsung,dw-mshc-ddr-timing = <1 2 3>; + + slot@0 { + reg = <0>; + bus-width = <8>; + gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>, + <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>, + <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>, + <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>, + <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>; + }; + }; + + dwmmc1@12210000 { + status = "disabled"; + }; + + dwmmc2@12220000 { + num-slots = <1>; + supports-highspeed; + fifo-depth = <0x80>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3 3>; + samsung,dw-mshc-ddr-timing = <1 2 3>; + + slot@0 { + reg = <0>; + bus-width = <4>; + samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>; + wp-gpios = <&gpc2 1 0 0 3>; + gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>, + <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>, + <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>; + }; + }; + + dwmmc3@12230000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + fifo-depth = <0x80>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3 3>; + samsung,dw-mshc-ddr-timing = <1 2 3>; + + slot@0 { + reg = <0>; + bus-width = <4>; + /* See board-specific dts files for GPIOs */ + }; + }; + + spi_0: spi@12d20000 { + status = "disabled"; + }; + + spi_1: spi@12d30000 { + gpios = <&gpa2 4 2 3 0>, + <&gpa2 6 2 3 0>, + <&gpa2 7 2 3 0>; + samsung,spi-src-clk = <0>; + num-cs = <1>; + }; + + spi_2: spi@12d40000 { + status = "disabled"; + }; + + hdmi { + hpd-gpio = <&gpx3 7 0xf 1 3>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpx1 3 0 0x10000 0>; + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts new file mode 100644 index 0000000..17dd951 --- /dev/null +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -0,0 +1,43 @@ +/* + * Google Snow board device tree source + * + * Copyright (c) 2012 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +/include/ "exynos5250.dtsi" +/include/ "cros5250-common.dtsi" + +/ { + model = "Google Snow"; + compatible = "google,snow", "samsung,exynos5250"; + + gpio-keys { + compatible = "gpio-keys"; + + lid-switch { + label = "Lid"; + gpios = <&gpx3 5 0 0x10000 0>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0>; /* SW_LID */ + debounce-interval = <1>; + gpio-key,wakeup; + }; + }; + + /* + * On Snow we've got SIP WiFi and so can keep drive strengths low to + * reduce EMI. + */ + dwmmc3@12230000 { + slot@0 { + gpios = <&gpc4 0 2 0 0>, <&gpc4 1 2 3 0>, + <&gpc4 3 2 3 0>, <&gpc4 4 2 3 0>, + <&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>; + }; + }; +}; -- cgit v0.10.2 From 34db4990e025fe03b565f6a7aa7977ac356771e1 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Wed, 21 Nov 2012 13:35:46 +0900 Subject: ARM: dts: Add aliases for i2c controller for exynos4 This is similar to a recent commit for exynos5250 titled: ARM: EXYNOS: Add aliases for i2c controller Adding aliases will be useful to prevent warnings in a future change. See: i2c: s3c2410: Get the i2c bus number from alias id Signed-off-by: Doug Anderson Acked-by: Olof Johansson Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index a26c3dd..824d362 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -28,6 +28,14 @@ spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; + i2c0 = &i2c_0; + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &i2c_7; }; gic:interrupt-controller@10490000 { @@ -121,7 +129,7 @@ status = "disabled"; }; - i2c@13860000 { + i2c_0: i2c@13860000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; @@ -130,7 +138,7 @@ status = "disabled"; }; - i2c@13870000 { + i2c_1: i2c@13870000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; @@ -139,7 +147,7 @@ status = "disabled"; }; - i2c@13880000 { + i2c_2: i2c@13880000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; @@ -148,7 +156,7 @@ status = "disabled"; }; - i2c@13890000 { + i2c_3: i2c@13890000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; @@ -157,7 +165,7 @@ status = "disabled"; }; - i2c@138A0000 { + i2c_4: i2c@138A0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; @@ -166,7 +174,7 @@ status = "disabled"; }; - i2c@138B0000 { + i2c_5: i2c@138B0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; @@ -175,7 +183,7 @@ status = "disabled"; }; - i2c@138C0000 { + i2c_6: i2c@138C0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; @@ -184,7 +192,7 @@ status = "disabled"; }; - i2c@138D0000 { + i2c_7: i2c@138D0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; -- cgit v0.10.2 From f5298e0776e5a25338aa2a55fb66fb3d958be42a Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Wed, 21 Nov 2012 13:45:52 +0900 Subject: ARM: EXYNOS: add all i2c busses to auxdata for DT Needed to match device ids for clocks, etc. Signed-off-by: Olof Johansson Signed-off-by: Doug Anderson Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index a88c19f..a032678 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -50,6 +50,16 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { "s3c2440-i2c.0", NULL), OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1), "s3c2440-i2c.1", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3), + "s3c2440-i2c.3", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4), + "s3c2440-i2c.4", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5), + "s3c2440-i2c.5", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6), + "s3c2440-i2c.6", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7), + "s3c2440-i2c.7", NULL), OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0, "dw_mmc.0", NULL), OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1, -- cgit v0.10.2 From 49ed67a42d206966661a7f2af8b8d86966466e1f Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Thu, 22 Nov 2012 00:15:40 +0900 Subject: ARM: dts: Split memory sections for exynos4210-origen This patch changes memory configuration defined in dts file of Origen board from single 1 GiB section into four 256 MiB sections to match section size limit. Signed-off-by: Tomasz Figa Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index f16c99f..0cade3e 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -22,7 +22,10 @@ compatible = "insignal,origen", "samsung,exynos4210"; memory { - reg = <0x40000000 0x40000000>; + reg = <0x40000000 0x10000000 + 0x50000000 0x10000000 + 0x60000000 0x10000000 + 0x70000000 0x10000000>; }; chosen { -- cgit v0.10.2 From 41d8bdf67c4dcacb9406fb329c3fd180649ae543 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Thu, 22 Nov 2012 00:15:40 +0900 Subject: ARM: dts: Update for pinctrl-samsung driver for exynos4210-origen This patch updates all parts of Origen dts related to pin configuration to use new GPIO and pinctrl bindings, instead of (now unsupported on Exynos4) legacy gpio-samsung bindings. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 0cade3e..d19a127 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -36,13 +36,8 @@ samsung,sdhci-bus-width = <4>; linux,mmc_cap_4_bit_data; samsung,sdhci-cd-internal; - gpio-cd = <&gpk2 2 2 3 3>; - gpios = <&gpk2 0 2 0 3>, - <&gpk2 1 2 0 3>, - <&gpk2 3 2 3 3>, - <&gpk2 4 2 3 3>, - <&gpk2 5 2 3 3>, - <&gpk2 6 2 3 3>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; + pinctrl-names = "default"; status = "okay"; }; @@ -50,13 +45,8 @@ samsung,sdhci-bus-width = <4>; linux,mmc_cap_4_bit_data; samsung,sdhci-cd-internal; - gpio-cd = <&gpk0 2 2 3 3>; - gpios = <&gpk0 0 2 0 3>, - <&gpk0 1 2 0 3>, - <&gpk0 3 2 3 3>, - <&gpk0 4 2 3 3>, - <&gpk0 5 2 3 3>, - <&gpk0 6 2 3 3>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>; + pinctrl-names = "default"; status = "okay"; }; @@ -83,35 +73,35 @@ up { label = "Up"; - gpios = <&gpx2 0 0 0x10000 2>; + gpios = <&gpx2 0 1>; linux,code = <103>; gpio-key,wakeup; }; down { label = "Down"; - gpios = <&gpx2 1 0 0x10000 2>; + gpios = <&gpx2 1 1>; linux,code = <108>; gpio-key,wakeup; }; back { label = "Back"; - gpios = <&gpx1 7 0 0x10000 2>; + gpios = <&gpx1 7 1>; linux,code = <158>; gpio-key,wakeup; }; home { label = "Home"; - gpios = <&gpx1 6 0 0x10000 2>; + gpios = <&gpx1 6 1>; linux,code = <102>; gpio-key,wakeup; }; menu { label = "Menu"; - gpios = <&gpx1 5 0 0x10000 2>; + gpios = <&gpx1 5 1>; linux,code = <139>; gpio-key,wakeup; }; @@ -120,7 +110,7 @@ leds { compatible = "gpio-leds"; status { - gpios = <&gpx1 3 0 0x10000 2>; + gpios = <&gpx1 3 1>; linux,default-trigger = "heartbeat"; }; }; -- cgit v0.10.2 From 6475daad9afdd22b79ed7847312bd274c989a2f5 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Thu, 22 Nov 2012 00:15:40 +0900 Subject: ARM: dts: Update sdhci nodes for current bindings for exynos4210-origen This patch modifies sdhci nodes present in Origen device tree source to use current generic mmc bindings. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index d19a127..7390f8c 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -33,18 +33,14 @@ }; sdhci@12530000 { - samsung,sdhci-bus-width = <4>; - linux,mmc_cap_4_bit_data; - samsung,sdhci-cd-internal; + bus-width = <4>; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; pinctrl-names = "default"; status = "okay"; }; sdhci@12510000 { - samsung,sdhci-bus-width = <4>; - linux,mmc_cap_4_bit_data; - samsung,sdhci-cd-internal; + bus-width = <4>; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>; pinctrl-names = "default"; status = "okay"; -- cgit v0.10.2 From cf7c397b62b1afa6d17c890641d067d5999daeb9 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Thu, 22 Nov 2012 00:15:40 +0900 Subject: ARM: dts: Add vmmc fixed voltage regulator for exynos4210-origen This patch adds fixed voltage vmmc regulator to dts file of Origen board. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 7390f8c..f271001 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -32,10 +32,20 @@ bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; }; + mmc_reg: voltage-regulator { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpx1 1 0>; + enable-active-high; + }; + sdhci@12530000 { bus-width = <4>; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; pinctrl-names = "default"; + vmmc-supply = <&mmc_reg>; status = "okay"; }; @@ -43,6 +53,7 @@ bus-width = <4>; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>; pinctrl-names = "default"; + vmmc-supply = <&mmc_reg>; status = "okay"; }; -- cgit v0.10.2 From 2ed5f236716cbd20f51bdc87ddd91bad259c81a6 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Thu, 22 Nov 2012 00:21:08 +0900 Subject: ARM: EXYNOS: Detect power domain state on registration from DT Initial state of power domains might vary on different boards and with different bootloaders. This patch adds detection of initial state of power domains when being registered from DT. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt index 6528e21..843b546 100644 --- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt +++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt @@ -9,10 +9,6 @@ Required Properties: - reg: physical base address of the controller and length of memory mapped region. -Optional Properties: -- samsung,exynos4210-pd-off: Specifies that the power domain is in turned-off - state during boot and remains to be turned-off until explicitly turned-on. - Example: lcd0: power-domain-lcd0 { diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index c0bc83a..d1abc1a 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -89,6 +89,7 @@ static __init int exynos_pm_dt_parse_domains(void) for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") { struct exynos_pm_domain *pd; + int on; pd = kzalloc(sizeof(*pd), GFP_KERNEL); if (!pd) { @@ -97,14 +98,15 @@ static __init int exynos_pm_dt_parse_domains(void) return -ENOMEM; } - if (of_get_property(np, "samsung,exynos4210-pd-off", NULL)) - pd->is_off = true; pd->name = np->name; pd->base = of_iomap(np, 0); pd->pd.power_off = exynos_pd_power_off; pd->pd.power_on = exynos_pd_power_on; pd->pd.of_node = np; - pm_genpd_init(&pd->pd, NULL, false); + + on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN; + + pm_genpd_init(&pd->pd, NULL, !on); } return 0; } -- cgit v0.10.2 From 7add0ec0fef19d5b7a3ae38c5deb80819a065a17 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Thu, 22 Nov 2012 00:21:12 +0900 Subject: ARM: EXYNOS: Fix power domain name initialization This patch adds initialization of name field in generic power domain struct. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index d1abc1a..5b7ce7e 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -98,7 +98,8 @@ static __init int exynos_pm_dt_parse_domains(void) return -ENOMEM; } - pd->name = np->name; + pd->pd.name = kstrdup(np->name, GFP_KERNEL); + pd->name = pd->pd.name; pd->base = of_iomap(np, 0); pd->pd.power_off = exynos_pd_power_off; pd->pd.power_on = exynos_pd_power_on; -- cgit v0.10.2 From 8a65d2365df0635da13ae30c01e217c477c9ce3e Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Thu, 22 Nov 2012 00:21:17 +0900 Subject: ARM: EXYNOS: Bind devices to power domains using DT This patch adds a way to specify bindings between devices and power domains using device tree. A device can be bound to particular power domain by adding a power-domain property containing a phandle to the domain. The device will be bound to the domain before binding a driver to it and unbound after unbinding a driver from it. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt index 843b546..5216b41 100644 --- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt +++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt @@ -4,14 +4,25 @@ Exynos processors include support for multiple power domains which are used to gate power to one or more peripherals on the processor. Required Properties: -- compatiable: should be one of the following. +- compatible: should be one of the following. * samsung,exynos4210-pd - for exynos4210 type power domain. - reg: physical base address of the controller and length of memory mapped region. +Node of a device using power domains must have a samsung,power-domain property +defined with a phandle to respective power domain. + Example: lcd0: power-domain-lcd0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C00 0x10>; }; + +Example of the node using power domain: + + node { + /* ... */ + samsung,power-domain = <&lcd0>; + /* ... */ + }; diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index 5b7ce7e..9f1351d 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include #include #include @@ -83,14 +85,89 @@ static struct exynos_pm_domain PD = { \ } #ifdef CONFIG_OF +static void exynos_add_device_to_domain(struct exynos_pm_domain *pd, + struct device *dev) +{ + int ret; + + dev_dbg(dev, "adding to power domain %s\n", pd->pd.name); + + while (1) { + ret = pm_genpd_add_device(&pd->pd, dev); + if (ret != -EAGAIN) + break; + cond_resched(); + } + + pm_genpd_dev_need_restore(dev, true); +} + +static void exynos_remove_device_from_domain(struct device *dev) +{ + struct generic_pm_domain *genpd = dev_to_genpd(dev); + int ret; + + dev_dbg(dev, "removing from power domain %s\n", genpd->name); + + while (1) { + ret = pm_genpd_remove_device(genpd, dev); + if (ret != -EAGAIN) + break; + cond_resched(); + } +} + +static void exynos_read_domain_from_dt(struct device *dev) +{ + struct platform_device *pd_pdev; + struct exynos_pm_domain *pd; + struct device_node *node; + + node = of_parse_phandle(dev->of_node, "samsung,power-domain", 0); + if (!node) + return; + pd_pdev = of_find_device_by_node(node); + if (!pd_pdev) + return; + pd = platform_get_drvdata(pd_pdev); + exynos_add_device_to_domain(pd, dev); +} + +static int exynos_pm_notifier_call(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct device *dev = data; + + switch (event) { + case BUS_NOTIFY_BIND_DRIVER: + if (dev->of_node) + exynos_read_domain_from_dt(dev); + + break; + + case BUS_NOTIFY_UNBOUND_DRIVER: + exynos_remove_device_from_domain(dev); + + break; + } + return NOTIFY_DONE; +} + +static struct notifier_block platform_nb = { + .notifier_call = exynos_pm_notifier_call, +}; + static __init int exynos_pm_dt_parse_domains(void) { + struct platform_device *pdev; struct device_node *np; for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") { struct exynos_pm_domain *pd; int on; + pdev = of_find_device_by_node(np); + pd = kzalloc(sizeof(*pd), GFP_KERNEL); if (!pd) { pr_err("%s: failed to allocate memory for domain\n", @@ -105,10 +182,15 @@ static __init int exynos_pm_dt_parse_domains(void) pd->pd.power_on = exynos_pd_power_on; pd->pd.of_node = np; + platform_set_drvdata(pdev, pd); + on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN; pm_genpd_init(&pd->pd, NULL, !on); } + + bus_register_notifier(&platform_bus_type, &platform_nb); + return 0; } #else -- cgit v0.10.2 From 91d88f038ec61bc2d66f72c615629827350c5df1 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Thu, 22 Nov 2012 00:22:09 +0900 Subject: ARM: dts: Set up power domains for exynos4 This patch adds device tree nodes for power domains available on EXYNOS4 SoCs. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 824d362..3428f1a 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -38,6 +38,36 @@ i2c7 = &i2c_7; }; + pd_mfc: mfc-power-domain@10023C40 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C40 0x20>; + }; + + pd_g3d: g3d-power-domain@10023C60 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C60 0x20>; + }; + + pd_lcd0: lcd0-power-domain@10023C80 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C80 0x20>; + }; + + pd_tv: tv-power-domain@10023C20 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C20 0x20>; + }; + + pd_cam: cam-power-domain@10023C00 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C00 0x20>; + }; + + pd_gps: gps-power-domain@10023CE0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023CE0 0x20>; + }; + gic:interrupt-controller@10490000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 939f639..e31bfc4 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -31,6 +31,11 @@ pinctrl2 = &pinctrl_2; }; + pd_lcd1: lcd1-power-domain@10023CA0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023CA0 0x20>; + }; + gic:interrupt-controller@10490000 { cpu-offset = <0x8000>; }; -- cgit v0.10.2 From d80162eccd56c40228e1232de8a203e8553b20a4 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Thu, 22 Nov 2012 00:29:47 +0900 Subject: ARM: dts: Use drive strength 3 for SD pins for exynos4 This patch modifies pin control groups of SD pins on EXYNOS4210 and EXYNOS4X12 to use drive strength 3 as a default value which corresponds to S5P_GPIO_DRVSTR_LV4 in legacy non-DT code. This is needed at least on Origen board for sdhci2 to work and if any other drive strength is required on each board, we can overide it. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park [kgene.kim@samsung.com: edited commit message] Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index 6a4a1a0..55a2efb 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -482,196 +482,196 @@ samsung,pins = "gpk0-0"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd0_cmd: sd0-cmd { samsung,pins = "gpk0-1"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd0_cd: sd0-cd { samsung,pins = "gpk0-2"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpk0-3"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_clk: sd4-clk { samsung,pins = "gpk0-0"; samsung,pin-function = <3>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_cmd: sd4-cmd { samsung,pins = "gpk0-1"; samsung,pin-function = <3>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_cd: sd4-cd { samsung,pins = "gpk0-2"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_bus1: sd4-bus-width1 { samsung,pins = "gpk0-3"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_bus4: sd4-bus-width4 { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_bus8: sd4-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <3>; samsung,pin-pud = <4>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd1_clk: sd1-clk { samsung,pins = "gpk1-0"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd1_cmd: sd1-cmd { samsung,pins = "gpk1-1"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd1_cd: sd1-cd { samsung,pins = "gpk1-2"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpk1-3"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_clk: sd2-clk { samsung,pins = "gpk2-0"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_cmd: sd2-cmd { samsung,pins = "gpk2-1"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_cd: sd2-cd { samsung,pins = "gpk2-2"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpk2-3"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_bus8: sd2-bus-width8 { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd3_clk: sd3-clk { samsung,pins = "gpk3-0"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd3_cmd: sd3-cmd { samsung,pins = "gpk3-1"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd3_cd: sd3-cd { samsung,pins = "gpk3-2"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd3_bus1: sd3-bus-width1 { samsung,pins = "gpk3-3"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd3_bus4: sd3-bus-width4 { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; eint0: ext-int0 { diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index 56f4669..8e6115a 100644 --- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi @@ -586,196 +586,196 @@ samsung,pins = "gpk0-0"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd0_cmd: sd0-cmd { samsung,pins = "gpk0-1"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd0_cd: sd0-cd { samsung,pins = "gpk0-2"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpk0-3"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_clk: sd4-clk { samsung,pins = "gpk0-0"; samsung,pin-function = <3>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_cmd: sd4-cmd { samsung,pins = "gpk0-1"; samsung,pin-function = <3>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_cd: sd4-cd { samsung,pins = "gpk0-2"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_bus1: sd4-bus-width1 { samsung,pins = "gpk0-3"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_bus4: sd4-bus-width4 { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_bus8: sd4-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <3>; samsung,pin-pud = <4>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd1_clk: sd1-clk { samsung,pins = "gpk1-0"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd1_cmd: sd1-cmd { samsung,pins = "gpk1-1"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd1_cd: sd1-cd { samsung,pins = "gpk1-2"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpk1-3"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_clk: sd2-clk { samsung,pins = "gpk2-0"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_cmd: sd2-cmd { samsung,pins = "gpk2-1"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_cd: sd2-cd { samsung,pins = "gpk2-2"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpk2-3"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_bus8: sd2-bus-width8 { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd3_clk: sd3-clk { samsung,pins = "gpk3-0"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd3_cmd: sd3-cmd { samsung,pins = "gpk3-1"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd3_cd: sd3-cd { samsung,pins = "gpk3-2"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd3_bus1: sd3-bus-width1 { samsung,pins = "gpk3-3"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd3_bus4: sd3-bus-width4 { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; keypad_col0: keypad-col0 { -- cgit v0.10.2 From 25d6dd859e73248432051257b4b4d2a3d51b295b Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 31 Oct 2012 10:12:54 +0100 Subject: ARM: dts: mxs: add oled support for the cfa-10036 Signed-off-by: Maxime Ripard Cc: Brian Lilly Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts index 794fc9f..1594694 100644 --- a/arch/arm/boot/dts/imx28-cfa10036.dts +++ b/arch/arm/boot/dts/imx28-cfa10036.dts @@ -58,11 +58,30 @@ }; apbx@80040000 { + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm4_pins_a>; + status = "okay"; + }; + duart: serial@80074000 { pinctrl-names = "default"; pinctrl-0 = <&duart_pins_b>; status = "okay"; }; + + i2c0: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_b>; + status = "okay"; + + ssd1307: oled@3c { + compatible = "solomon,ssd1307fb-i2c"; + reg = <0x3c>; + pwms = <&pwm 4 3000>; + reset-gpios = <&gpio2 7 0>; + }; + }; }; }; -- cgit v0.10.2 From 77dae54ab385033e488d8b07045bc7f8d931740f Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 20 Oct 2012 13:10:00 +0200 Subject: ARM: Kirkwood: ehci-orion: Add device tree binding Based on previous work by Michael Walle and Jason Cooper. Made their work actually work, which required added interrupt from DT and auxdata, along with setting the dma_mask, which DT does not currently do. Signed-off-by: Andrew Lunn Tested-by: Sebastian Hesselbarth Acked-by: Alan Stern Signed-off-by: Jason Cooper diff --git a/Documentation/devicetree/bindings/usb/ehci-orion.txt b/Documentation/devicetree/bindings/usb/ehci-orion.txt new file mode 100644 index 0000000..6bc09ec --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ehci-orion.txt @@ -0,0 +1,15 @@ +* EHCI controller, Orion Marvell variants + +Required properties: +- compatible: must be "marvell,orion-ehci" +- reg: physical base address of the controller and length of memory mapped + region. +- interrupts: The EHCI interrupt + +Example: + + ehci@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x1000>; + interrupts = <19>; + }; diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c index 9c2717d..e7e8275 100644 --- a/drivers/usb/host/ehci-orion.c +++ b/drivers/usb/host/ehci-orion.c @@ -14,6 +14,9 @@ #include #include #include +#include +#include +#include #define rdl(off) __raw_readl(hcd->regs + (off)) #define wrl(off, val) __raw_writel((val), hcd->regs + (off)) @@ -181,6 +184,8 @@ ehci_orion_conf_mbus_windows(struct usb_hcd *hcd, } } +static u64 ehci_orion_dma_mask = DMA_BIT_MASK(32); + static int __devinit ehci_orion_drv_probe(struct platform_device *pdev) { struct orion_ehci_data *pd = pdev->dev.platform_data; @@ -191,13 +196,17 @@ static int __devinit ehci_orion_drv_probe(struct platform_device *pdev) struct clk *clk; void __iomem *regs; int irq, err; + enum orion_ehci_phy_ver phy_version; if (usb_disabled()) return -ENODEV; pr_debug("Initializing Orion-SoC USB Host Controller\n"); - irq = platform_get_irq(pdev, 0); + if (pdev->dev.of_node) + irq = irq_of_parse_and_map(pdev->dev.of_node, 0); + else + irq = platform_get_irq(pdev, 0); if (irq <= 0) { dev_err(&pdev->dev, "Found HC with no IRQ. Check %s setup!\n", @@ -215,6 +224,14 @@ static int __devinit ehci_orion_drv_probe(struct platform_device *pdev) goto err1; } + /* + * Right now device-tree probed devices don't get dma_mask + * set. Since shared usb code relies on it, set it here for + * now. Once we have dma capability bindings this can go away. + */ + if (!pdev->dev.dma_mask) + pdev->dev.dma_mask = &ehci_orion_dma_mask; + if (!request_mem_region(res->start, resource_size(res), ehci_orion_hc_driver.description)) { dev_dbg(&pdev->dev, "controller already in use\n"); @@ -262,7 +279,12 @@ static int __devinit ehci_orion_drv_probe(struct platform_device *pdev) /* * setup Orion USB controller. */ - switch (pd->phy_version) { + if (pdev->dev.of_node) + phy_version = EHCI_PHY_NA; + else + phy_version = pd->phy_version; + + switch (phy_version) { case EHCI_PHY_NA: /* dont change USB phy settings */ break; case EHCI_PHY_ORION: @@ -317,9 +339,19 @@ static int __exit ehci_orion_drv_remove(struct platform_device *pdev) MODULE_ALIAS("platform:orion-ehci"); +static const struct of_device_id ehci_orion_dt_ids[] __devinitdata = { + { .compatible = "marvell,orion-ehci", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ehci_orion_dt_ids); + static struct platform_driver ehci_orion_driver = { .probe = ehci_orion_drv_probe, .remove = __exit_p(ehci_orion_drv_remove), .shutdown = usb_hcd_platform_shutdown, - .driver.name = "orion-ehci", + .driver = { + .name = "orion-ehci", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(ehci_orion_dt_ids), + }, }; -- cgit v0.10.2 From b6cf80704d065931f906db61776a1fb8d8609d63 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 20 Oct 2012 13:10:01 +0200 Subject: ARM: Kirkwood: Convert all DT boards to EHCI via DT. Now that the EHCI driver has DT support, drop old style configuration of it and add DT in its place. Since all the boards enable the EHCI, enable it by default in kirkwood.dtsi. Any new boards which don't have USB can specifically disable it. Signed-off-by: Andrew Lunn Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 4e5b815..4fc7a8e 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -77,6 +77,13 @@ status = "okay"; }; + ehci@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x1000>; + interrupts = <19>; + status = "okay"; + }; + sata@80000 { compatible = "marvell,orion-sata"; reg = <0x80000 0x5000>; diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c index 43d16d6..2ac6c60 100644 --- a/arch/arm/mach-kirkwood/board-dnskw.c +++ b/arch/arm/mach-kirkwood/board-dnskw.c @@ -78,7 +78,6 @@ void __init dnskw_init(void) { kirkwood_mpp_conf(dnskw_mpp_config); - kirkwood_ehci_init(); kirkwood_ge00_init(&dnskw_ge00_data); /* Register power-off GPIO. */ diff --git a/arch/arm/mach-kirkwood/board-dockstar.c b/arch/arm/mach-kirkwood/board-dockstar.c index f2fbb02..e94782d 100644 --- a/arch/arm/mach-kirkwood/board-dockstar.c +++ b/arch/arm/mach-kirkwood/board-dockstar.c @@ -55,7 +55,6 @@ void __init dockstar_dt_init(void) if (gpio_request(29, "USB Power Enable") != 0 || gpio_direction_output(29, 1) != 0) pr_err("can't setup GPIO 29 (USB Power Enable)\n"); - kirkwood_ehci_init(); kirkwood_ge00_init(&dockstar_ge00_data); } diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c index 20af53a..acdc04a 100644 --- a/arch/arm/mach-kirkwood/board-dreamplug.c +++ b/arch/arm/mach-kirkwood/board-dreamplug.c @@ -64,7 +64,6 @@ void __init dreamplug_init(void) */ kirkwood_mpp_conf(dreamplug_mpp_config); - kirkwood_ehci_init(); kirkwood_ge00_init(&dreamplug_ge00_data); kirkwood_ge01_init(&dreamplug_ge01_data); kirkwood_sdio_init(&dreamplug_mvsdio_data); diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c index 001ca8c..d388bea 100644 --- a/arch/arm/mach-kirkwood/board-goflexnet.c +++ b/arch/arm/mach-kirkwood/board-goflexnet.c @@ -65,7 +65,6 @@ void __init goflexnet_init(void) if (gpio_request(29, "USB Power Enable") != 0 || gpio_direction_output(29, 1) != 0) pr_err("can't setup GPIO 29 (USB Power Enable)\n"); - kirkwood_ehci_init(); kirkwood_ge00_init(&goflexnet_ge00_data); } diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c index cfc47f8..db08e37 100644 --- a/arch/arm/mach-kirkwood/board-ib62x0.c +++ b/arch/arm/mach-kirkwood/board-ib62x0.c @@ -61,7 +61,6 @@ void __init ib62x0_init(void) */ kirkwood_mpp_conf(ib62x0_mpp_config); - kirkwood_ehci_init(); kirkwood_ge00_init(&ib62x0_ge00_data); if (gpio_request(IB62X0_GPIO_POWER_OFF, "ib62x0:power:off") == 0 && gpio_direction_output(IB62X0_GPIO_POWER_OFF, 0) == 0) diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c index d084b1e..8275fb0 100644 --- a/arch/arm/mach-kirkwood/board-iconnect.c +++ b/arch/arm/mach-kirkwood/board-iconnect.c @@ -45,7 +45,6 @@ void __init iconnect_init(void) { kirkwood_mpp_conf(iconnect_mpp_config); - kirkwood_ehci_init(); kirkwood_ge00_init(&iconnect_ge00_data); } diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c index 158fb97..a6f3d29 100644 --- a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c +++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c @@ -51,7 +51,5 @@ void __init iomega_ix2_200_init(void) */ kirkwood_mpp_conf(iomega_ix2_200_mpp_config); - kirkwood_ehci_init(); - kirkwood_ge01_init(&iomega_ix2_200_ge00_data); } diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c index f7d3283..1e9ac4b 100644 --- a/arch/arm/mach-kirkwood/board-km_kirkwood.c +++ b/arch/arm/mach-kirkwood/board-km_kirkwood.c @@ -52,6 +52,5 @@ void __init km_kirkwood_init(void) if (!IS_ERR(sata_clk)) sata_clk->flags |= CLK_IGNORE_UNUSED; - kirkwood_ehci_init(); kirkwood_ge00_init(&km_kirkwood_ge00_data); } diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c index a29b8bf..b6fbdaa 100644 --- a/arch/arm/mach-kirkwood/board-lsxl.c +++ b/arch/arm/mach-kirkwood/board-lsxl.c @@ -75,7 +75,6 @@ void __init lsxl_init(void) gpio_set_value(LSXL_GPIO_USB_POWER, 1); gpio_set_value(LSXL_GPIO_HDD_POWER, 1); - kirkwood_ehci_init(); kirkwood_ge00_init(&lsxl_ge00_data); kirkwood_ge01_init(&lsxl_ge01_data); diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c index 1750e68..5a031b9 100644 --- a/arch/arm/mach-kirkwood/board-ts219.c +++ b/arch/arm/mach-kirkwood/board-ts219.c @@ -66,7 +66,6 @@ void __init qnap_dt_ts219_init(void) qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0); kirkwood_ge00_init(&qnap_ts219_ge00_data); - kirkwood_ehci_init(); pm_power_off = qnap_tsx1x_power_off; } -- cgit v0.10.2 From f4a00139b7cbeff538e616a21f6b57249a9d3ed8 Mon Sep 17 00:00:00 2001 From: Jamie Lentin Date: Thu, 1 Nov 2012 21:57:01 +0000 Subject: ARM: kirkwood: Increase NAND chip-delay for DNS-32[05] The default chip-delay of 25us is a bit too tight for some DNS-320's, and D-Link seem to specify 30us in their kernels for both devices. Increase to 35us to make sure the NAND is stable. Signed-off-by: Jamie Lentin Acked-by: Andrew Lunn Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index 9b32d02..fd23e63 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -43,6 +43,7 @@ nand@3000000 { status = "okay"; + chip-delay = <35>; partition@0 { label = "u-boot"; -- cgit v0.10.2 From 96ff0f5c7efd4a2205c48a76a6a1fcd2731e6128 Mon Sep 17 00:00:00 2001 From: Jamie Lentin Date: Sat, 17 Nov 2012 09:51:04 +0100 Subject: power: Add simple poweroff-gpio driver Given appropriate devicetree bindings, this driver registers a pm_power_off function to set a GPIO line high/low to power down your board. Signed-off-by: Jamie Lentin Signed-off-by: Andrew Lunn Tested-by:Simon Baatz Signed-off-by: Jason Cooper diff --git a/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt b/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt new file mode 100644 index 0000000..558cdf3 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt @@ -0,0 +1,22 @@ +GPIO line that should be set high/low to power off a device + +Required properties: +- compatible : should be "gpio-poweroff". +- gpios : The GPIO to set high/low, see "gpios property" in + Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be + low to power down the board set it to "Active Low", otherwise set + gpio to "Active High". + +Optional properties: +- input : Initially configure the GPIO line as an input. Only reconfigure + it to an output when the pm_power_off function is called. If this optional + property is not specified, the GPIO is initialized as an output in its + inactive state. + + +Examples: + +gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio 4 0>; /* GPIO 4 Active Low */ +}; diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 49a8939..b1d956d 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -335,6 +335,9 @@ config AB8500_BATTERY_THERM_ON_BATCTRL help Say Y to enable battery temperature measurements using thermistor connected on BATCTRL ADC. + +source "drivers/power/reset/Kconfig" + endif # POWER_SUPPLY source "drivers/power/avs/Kconfig" diff --git a/drivers/power/Makefile b/drivers/power/Makefile index b949cf8..f1d99f4 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -49,3 +49,4 @@ obj-$(CONFIG_CHARGER_MAX8997) += max8997_charger.o obj-$(CONFIG_CHARGER_MAX8998) += max8998_charger.o obj-$(CONFIG_POWER_AVS) += avs/ obj-$(CONFIG_CHARGER_SMB347) += smb347-charger.o +obj-$(CONFIG_POWER_RESET) += reset/ diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig new file mode 100644 index 0000000..6461b48 --- /dev/null +++ b/drivers/power/reset/Kconfig @@ -0,0 +1,15 @@ +menuconfig POWER_RESET + bool "Board level reset or power off" + help + Provides a number of drivers which either reset a complete board + or shut it down, by manipulating the main power supply on the board. + + Say Y here to enable board reset and power off + +config POWER_RESET_GPIO + bool "GPIO power-off driver" + depends on OF_GPIO && POWER_RESET + help + This driver supports turning off your board via a GPIO line. + If your board needs a GPIO high/low to power down, say Y and + create a binding in your devicetree. diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile new file mode 100644 index 0000000..751488a --- /dev/null +++ b/drivers/power/reset/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o diff --git a/drivers/power/reset/gpio-poweroff.c b/drivers/power/reset/gpio-poweroff.c new file mode 100644 index 0000000..0491e53 --- /dev/null +++ b/drivers/power/reset/gpio-poweroff.c @@ -0,0 +1,129 @@ +/* + * Toggles a GPIO pin to power down a device + * + * Jamie Lentin + * Andrew Lunn + * + * Copyright (C) 2012 Jamie Lentin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Hold configuration here, cannot be more than one instance of the driver + * since pm_power_off itself is global. + */ +static int gpio_num = -1; +static int gpio_active_low; + +static void gpio_poweroff_do_poweroff(void) +{ + BUG_ON(gpio_num == -1); + + /* drive it active */ + gpio_direction_output(gpio_num, !gpio_active_low); + mdelay(100); + /* rising edge or drive inactive */ + gpio_set_value(gpio_num, gpio_active_low); + mdelay(100); + /* falling edge */ + gpio_set_value(gpio_num, !gpio_active_low); + + /* give it some time */ + mdelay(3000); + + WARN_ON(1); +} + +static int __devinit gpio_poweroff_probe(struct platform_device *pdev) +{ + enum of_gpio_flags flags; + bool input = false; + int ret; + + /* If a pm_power_off function has already been added, leave it alone */ + if (pm_power_off != NULL) { + pr_err("%s: pm_power_off function already registered", + __func__); + return -EBUSY; + } + + gpio_num = of_get_gpio_flags(pdev->dev.of_node, 0, &flags); + if (gpio_num < 0) { + pr_err("%s: Could not get GPIO configuration: %d", + __func__, gpio_num); + return -ENODEV; + } + gpio_active_low = flags & OF_GPIO_ACTIVE_LOW; + + if (of_get_property(pdev->dev.of_node, "input", NULL)) + input = true; + + ret = gpio_request(gpio_num, "poweroff-gpio"); + if (ret) { + pr_err("%s: Could not get GPIO %d", __func__, gpio_num); + return ret; + } + if (input) { + if (gpio_direction_input(gpio_num)) { + pr_err("Could not set direction of GPIO %d to input", + gpio_num); + goto err; + } + } else { + if (gpio_direction_output(gpio_num, gpio_active_low)) { + pr_err("Could not set direction of GPIO %d", gpio_num); + goto err; + } + } + + pm_power_off = &gpio_poweroff_do_poweroff; + return 0; + +err: + gpio_free(gpio_num); + return -ENODEV; +} + +static int __devexit gpio_poweroff_remove(struct platform_device *pdev) +{ + if (gpio_num != -1) + gpio_free(gpio_num); + if (pm_power_off == &gpio_poweroff_do_poweroff) + pm_power_off = NULL; + + return 0; +} + +static const struct of_device_id of_gpio_poweroff_match[] = { + { .compatible = "gpio-poweroff", }, + {}, +}; + +static struct platform_driver gpio_poweroff_driver = { + .probe = gpio_poweroff_probe, + .remove = __devexit_p(gpio_poweroff_remove), + .driver = { + .name = "poweroff-gpio", + .owner = THIS_MODULE, + .of_match_table = of_gpio_poweroff_match, + }, +}; + +module_platform_driver(gpio_poweroff_driver); + +MODULE_AUTHOR("Jamie Lentin "); +MODULE_DESCRIPTION("GPIO poweroff driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:poweroff-gpio"); -- cgit v0.10.2 From 2c0e7ee61b335dea4bd2678591923c02703f4eeb Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 09:51:05 +0100 Subject: ARM: Kirkwood: Convert DNSKW to use gpio-poweroff. Also enable the gpio-poweroff driver when DT is used. Signed-off-by: Andrew Lunn Tested-by: Jamie Lentin Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index fd23e63..28263a1 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -35,6 +35,11 @@ 6000 2>; }; + gpio_poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio1 4 0>; + }; + ocp@f1000000 { sata@80000 { status = "okay"; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index d018ad4..35b3258 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -46,6 +46,9 @@ config MACH_GURUPLUG config ARCH_KIRKWOOD_DT bool "Marvell Kirkwood Flattened Device Tree" + select POWER_SUPPLY + select POWER_RESET + select POWER_RESET_GPIO select USE_OF help Say 'Y' here if you want your kernel to support the diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c index 2ac6c60..9036801 100644 --- a/arch/arm/mach-kirkwood/board-dnskw.c +++ b/arch/arm/mach-kirkwood/board-dnskw.c @@ -57,11 +57,6 @@ static unsigned int dnskw_mpp_config[] __initdata = { 0 }; -static void dnskw_power_off(void) -{ - gpio_set_value(36, 1); -} - /* Register any GPIO for output and set the value */ static void __init dnskw_gpio_register(unsigned gpio, char *name, int def) { @@ -80,13 +75,6 @@ void __init dnskw_init(void) kirkwood_ge00_init(&dnskw_ge00_data); - /* Register power-off GPIO. */ - if (gpio_request(36, "dnskw:power:off") == 0 - && gpio_direction_output(36, 0) == 0) - pm_power_off = dnskw_power_off; - else - pr_err("dnskw: failed to configure power-off GPIO\n"); - /* Ensure power is supplied to both HDDs */ dnskw_gpio_register(39, "dnskw:power:sata0", 1); dnskw_gpio_register(40, "dnskw:power:sata1", 1); -- cgit v0.10.2 From 2104035214b51d007db7e040906550eb608aaa44 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 09:51:06 +0100 Subject: ARM: Kirkwood: Convert IB62x0 to use gpio-poweroff. Signed-off-by: Andrew Lunn Tested-by: Simon Baatz Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index 66794ed..6a9558d 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -79,4 +79,10 @@ gpios = <&gpio0 27 0>; }; }; + gpio_poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 24 0>; + }; + + }; diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c index db08e37..2a58b4fc 100644 --- a/arch/arm/mach-kirkwood/board-ib62x0.c +++ b/arch/arm/mach-kirkwood/board-ib62x0.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -25,8 +24,6 @@ #include "common.h" #include "mpp.h" -#define IB62X0_GPIO_POWER_OFF 24 - static struct mv643xx_eth_platform_data ib62x0_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; @@ -49,11 +46,6 @@ static unsigned int ib62x0_mpp_config[] __initdata = { 0 }; -static void ib62x0_power_off(void) -{ - gpio_set_value(IB62X0_GPIO_POWER_OFF, 1); -} - void __init ib62x0_init(void) { /* @@ -62,9 +54,4 @@ void __init ib62x0_init(void) kirkwood_mpp_conf(ib62x0_mpp_config); kirkwood_ge00_init(&ib62x0_ge00_data); - if (gpio_request(IB62X0_GPIO_POWER_OFF, "ib62x0:power:off") == 0 && - gpio_direction_output(IB62X0_GPIO_POWER_OFF, 0) == 0) - pm_power_off = ib62x0_power_off; - else - pr_err("board-ib62x0: failed to configure power-off GPIO\n"); } -- cgit v0.10.2 From c7064a05bdbf9d542b3aa9d4439d30c624967b66 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 15:46:10 +0100 Subject: ARM: Kirkwood: Enable regulator and fixed regulators. A few boards use a GPIO line to enable power to subsystems, eg USB or SATA devices. Pull in the regulator framework as the first step to controlling these GPIO lines are regulators. Signed-off-by: Andrew Lunn Signed-off-by: Jason Cooper diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 35b3258..503d7dd 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -49,6 +49,8 @@ config ARCH_KIRKWOOD_DT select POWER_SUPPLY select POWER_RESET select POWER_RESET_GPIO + select REGULATOR + select REGULATOR_FIXED_VOLTAGE select USE_OF help Say 'Y' here if you want your kernel to support the -- cgit v0.10.2 From 5c2734a30c0838c9ba9b6b95fb18533cea3c1a5a Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 15:46:11 +0100 Subject: ARM: Kirkwood: Convert DNSKW to use regulators Control the power to SATA0 and SATA1 using a fixed regulator. Signed-off-by: Andrew Lunn Tested-by: Jamie Lentin Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index 28263a1..d11054f 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -82,4 +82,33 @@ }; }; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + sata0_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 7 0>; + }; + sata1_power: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 8 0>; + }; + }; }; diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c index 9036801..6c4028c 100644 --- a/arch/arm/mach-kirkwood/board-dnskw.c +++ b/arch/arm/mach-kirkwood/board-dnskw.c @@ -75,10 +75,6 @@ void __init dnskw_init(void) kirkwood_ge00_init(&dnskw_ge00_data); - /* Ensure power is supplied to both HDDs */ - dnskw_gpio_register(39, "dnskw:power:sata0", 1); - dnskw_gpio_register(40, "dnskw:power:sata1", 1); - /* Set NAS to turn back on after a power failure */ dnskw_gpio_register(37, "dnskw:power:recover", 1); } -- cgit v0.10.2 From c3ff813ac9d72f588166b8e802f31f85e8cf731b Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 15:46:12 +0100 Subject: ARM: Kirkwood: Convert Dockstar to use regulators Control the power to USB using a fixed regulator. Signed-off-by: Andrew Lunn Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index 08a5824..c0fbfdc 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -54,4 +54,21 @@ gpios = <&gpio1 15 1>; }; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 29 0>; + }; + }; }; diff --git a/arch/arm/mach-kirkwood/board-dockstar.c b/arch/arm/mach-kirkwood/board-dockstar.c index e94782d..410452a 100644 --- a/arch/arm/mach-kirkwood/board-dockstar.c +++ b/arch/arm/mach-kirkwood/board-dockstar.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -52,9 +51,5 @@ void __init dockstar_dt_init(void) */ kirkwood_mpp_conf(dockstar_mpp_config); - if (gpio_request(29, "USB Power Enable") != 0 || - gpio_direction_output(29, 1) != 0) - pr_err("can't setup GPIO 29 (USB Power Enable)\n"); - kirkwood_ge00_init(&dockstar_ge00_data); } -- cgit v0.10.2 From 280b348d9157b77cceb1aafd6b0e9ac6eb6c3b44 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 15:46:13 +0100 Subject: ARM: Kirkwood: Convert GoFlexNet to use regulators Control the power to USB using a fixed regulator. Signed-off-by: Andrew Lunn Tested-by: Josh Coombs Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index 7c8238f..84de887 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -96,4 +96,21 @@ gpios = <&gpio1 9 0>; }; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 29 0>; + }; + }; }; diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c index d388bea..5ff4392 100644 --- a/arch/arm/mach-kirkwood/board-goflexnet.c +++ b/arch/arm/mach-kirkwood/board-goflexnet.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -62,9 +61,5 @@ void __init goflexnet_init(void) */ kirkwood_mpp_conf(goflexnet_mpp_config); - if (gpio_request(29, "USB Power Enable") != 0 || - gpio_direction_output(29, 1) != 0) - pr_err("can't setup GPIO 29 (USB Power Enable)\n"); - kirkwood_ge00_init(&goflexnet_ge00_data); } -- cgit v0.10.2 From 423b89595de34f81061d106c34cfca58cde497da Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 15:46:14 +0100 Subject: ARM: Kirkwood: Convert LSXL to use regulators Control the power to USB and HDD using a fixed regulator. Signed-off-by: Andrew Lunn Tested-by: Michael Walle Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index 798e60e..32d302e 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi @@ -105,4 +105,33 @@ 5000 0>; alarm-gpios = <&gpio1 8 0>; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 11 0>; + }; + hdd_power: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "HDD Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 10 0>; + }; + }; }; diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c index b6fbdaa..f780e2e 100644 --- a/arch/arm/mach-kirkwood/board-lsxl.c +++ b/arch/arm/mach-kirkwood/board-lsxl.c @@ -19,7 +19,6 @@ #include #include #include -#include #include "common.h" #include "mpp.h" @@ -61,9 +60,6 @@ static void lsxl_power_off(void) kirkwood_restart('h', NULL); } -#define LSXL_GPIO_HDD_POWER 10 -#define LSXL_GPIO_USB_POWER 11 - void __init lsxl_init(void) { /* @@ -71,10 +67,6 @@ void __init lsxl_init(void) */ kirkwood_mpp_conf(lsxl_mpp_config); - /* usb and sata power on */ - gpio_set_value(LSXL_GPIO_USB_POWER, 1); - gpio_set_value(LSXL_GPIO_HDD_POWER, 1); - kirkwood_ge00_init(&lsxl_ge00_data); kirkwood_ge01_init(&lsxl_ge01_data); -- cgit v0.10.2 From 78f9f3b12c6a25a668c43f026f42596c88d6d0bd Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Mon, 19 Nov 2012 10:39:53 +0100 Subject: pinctrl: mvebu: fix iomem pointer for dove pinctrl There has been a change in readl/writel to require registers addresses marked as IOMEM(). This patch takes care of this and also replaces ORing address offsets with adding them. Signed-off-by: Sebastian Hesselbarth Acked-by: Thomas Petazzoni Acked-by: Linus Walleij Signed-off-by: Jason Cooper diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c index ffe74b2..34693f6 100644 --- a/drivers/pinctrl/mvebu/pinctrl-dove.c +++ b/drivers/pinctrl/mvebu/pinctrl-dove.c @@ -22,22 +22,22 @@ #include "pinctrl-mvebu.h" -#define DOVE_SB_REGS_VIRT_BASE 0xfde00000 -#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200) +#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) +#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) #define DOVE_AU0_AC97_SEL BIT(16) -#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C) +#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) #define DOVE_TWSI_ENABLE_OPTION1 BIT(7) -#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030) +#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) #define DOVE_TWSI_ENABLE_OPTION2 BIT(20) #define DOVE_TWSI_ENABLE_OPTION3 BIT(21) #define DOVE_TWSI_OPTION3_GPIO BIT(22) -#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034) +#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) #define DOVE_SSP_ON_AU1 BIT(0) -#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) +#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) #define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) #define DOVE_NAND_GPIO_EN BIT(0) -#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) +#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) #define DOVE_SPI_GPIO_SEL BIT(5) #define DOVE_UART1_GPIO_SEL BIT(4) -- cgit v0.10.2 From 63ace077b427a86464da34855d35addfa308e807 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Mon, 19 Nov 2012 10:39:54 +0100 Subject: pinctrl: mvebu: Fix dove_audio1_ctrl_set function When setting audio1 pinmux the bits in the corresponding registers are not cleared. This fix first clears all bits and then sets the required bits according to the selected function. Signed-off-by: Axel Lin Signed-off-by: Sebastian Hesselbarth Acked-by: Linus Walleij Signed-off-by: Jason Cooper diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c index 34693f6..40c9c3e 100644 --- a/drivers/pinctrl/mvebu/pinctrl-dove.c +++ b/drivers/pinctrl/mvebu/pinctrl-dove.c @@ -234,6 +234,14 @@ static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl, unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); + /* + * clear all audio1 related bits before configure + */ + gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO; + gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN; + sspc1 &= ~DOVE_SSP_ON_AU1; + mpp4 &= ~DOVE_AU1_GPIO_SEL; + if (config & BIT(0)) gcfg2 |= DOVE_TWSI_OPTION3_GPIO; if (config & BIT(1)) -- cgit v0.10.2 From 9139acd1c4e5e545d4ba820f70400960126b2613 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Mon, 19 Nov 2012 10:39:55 +0100 Subject: ARM: Dove: Convert to DT GPIO and pinctrl Following the ongoing conversion of Orion SoCs to DT, make use of gpio and pinctrl drivers through DT. The main dtsi for Dove is prepared to allow board specific descriptors to make use of pinctrl muxing. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ade7e92..ca2b418 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -536,6 +536,8 @@ config ARCH_DOVE select CPU_V7 select GENERIC_CLOCKEVENTS select MIGHT_HAVE_PCI + select PINCTRL + select PINCTRL_DOVE select PLAT_ORION_LEGACY select USB_ARCH_HAS_EHCI help diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 5a00022..61f3914 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -4,6 +4,12 @@ compatible = "marvell,dove"; model = "Marvell Armada 88AP510 SoC"; + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + soc@f1000000 { compatible = "simple-bus"; #address-cells = <1>; @@ -72,7 +78,8 @@ #gpio-cells = <2>; gpio-controller; reg = <0xd0400 0x20>; - ngpio = <32>; + ngpios = <32>; + interrupt-controller; interrupts = <12>, <13>, <14>, <60>; }; @@ -81,7 +88,8 @@ #gpio-cells = <2>; gpio-controller; reg = <0xd0420 0x20>; - ngpio = <32>; + ngpios = <32>; + interrupt-controller; interrupts = <61>; }; @@ -90,7 +98,12 @@ #gpio-cells = <2>; gpio-controller; reg = <0xe8400 0x0c>; - ngpio = <8>; + ngpios = <8>; + }; + + pinctrl: pinctrl@d0200 { + compatible = "marvell,dove-pinctrl"; + reg = <0xd0200 0x10>; }; spi0: spi@10600 { -- cgit v0.10.2 From e7cd8f8721bcae6e0d4bef52559b7babf75fbc3e Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Mon, 19 Nov 2012 10:39:56 +0100 Subject: ARM: Dove: Add CuBox pinhog for led SolidRun CuBox has a led on a gpio pin. As there is now DT pinctrl support for Dove, make use of a pinhog to ensure the pin is set to gpio. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index 0adbd5a..fed7d3f 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -40,3 +40,13 @@ reg = <0>; }; }; + +&pinctrl { + pinctrl-0 = <&pmx_gpio_18>; + pinctrl-names = "default"; + + pmx_gpio_18: pmx-gpio-18 { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; +}; -- cgit v0.10.2 From 49e928d6cfd4a27f2b2e0ea6cdcb9e853360a9a1 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 17:00:43 +0100 Subject: GPIO: mvebu: Allow all plat-orion platforms. Kirkwood & Dove can also use this driver, so expand the scope to include all platform orion devices. Signed-off-by: Andrew Lunn Signed-off-by: Jason Cooper diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index f11d8e3..6dbc403 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -152,7 +152,7 @@ config GPIO_MSM_V2 config GPIO_MVEBU def_bool y - depends on ARCH_MVEBU + depends on PLAT_ORION select GPIO_GENERIC select GENERIC_IRQ_CHIP -- cgit v0.10.2 From f9e7592230b72acb703e6c29691d587341b6c710 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 17:00:44 +0100 Subject: ARM: Kirkwood: Make use of mvebu pincltl and gpio drivers Select the generic mvebu kirkwood pincltr driver and generic mvebu gpio driver. This requires minor changes to the DT, and the calls to configure plat-orion gpio driver are removed. Signed-off-by: Andrew Lunn Tested-by: Michael Walle Tested-by: Simon Baatz Tested-by: Jamie Lentin Tested-by: Joshua Coombs Signed-off-by: Jason Cooper diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ca2b418..3cf5742 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -549,6 +549,8 @@ config ARCH_KIRKWOOD select CPU_FEROCEON select GENERIC_CLOCKEVENTS select PCI + select PINCTRL + select PINCTRL_KIRKWOOD select PLAT_ORION_LEGACY help Support for the following Marvell Kirkwood series SoCs: diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 4fc7a8e..a990c30 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -4,6 +4,10 @@ compatible = "marvell,kirkwood"; interrupt-parent = <&intc>; + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + }; intc: interrupt-controller { compatible = "marvell,orion-intc", "marvell,intc"; interrupt-controller; @@ -24,7 +28,8 @@ #gpio-cells = <2>; gpio-controller; reg = <0x10100 0x40>; - ngpio = <32>; + ngpios = <32>; + interrupt-controller; interrupts = <35>, <36>, <37>, <38>; }; @@ -33,7 +38,8 @@ #gpio-cells = <2>; gpio-controller; reg = <0x10140 0x40>; - ngpio = <18>; + ngpios = <18>; + interrupt-controller; interrupts = <39>, <40>, <41>; }; diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c index 1867944..8db0b98 100644 --- a/arch/arm/plat-orion/irq.c +++ b/arch/arm/plat-orion/irq.c @@ -41,7 +41,7 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) static int __init orion_add_irq_domain(struct device_node *np, struct device_node *interrupt_parent) { - int i = 0, irq_gpio; + int i = 0; void __iomem *base; do { @@ -54,10 +54,6 @@ static int __init orion_add_irq_domain(struct device_node *np, irq_domain_add_legacy(np, i * 32, 0, 0, &irq_domain_simple_ops, NULL); - - irq_gpio = i * 32; - orion_gpio_of_init(irq_gpio); - return 0; } -- cgit v0.10.2 From 82bb2da1787a1ec797626dcbb49ae9f171109c9b Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 17:00:45 +0100 Subject: ARM: Kirkwood: Add DTSI files for pinctrl There are a couple of different variants of Kirkwood, which differ in the pin muxing. These DTSI files set the correct compatibility and define commonly used groups of pins, which board dbs files can reference. Signed-off-by: Andrew Lunn Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi new file mode 100644 index 0000000..b0fe682 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -0,0 +1,39 @@ +/ { + ocp@f1000000 { + pinctrl: pinctrl@10000 { + compatible = "marvell,88f6281-pinctrl"; + reg = <0x10000 0x20>; + + pmx_nand: pmx-nand { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp18", + "mpp19"; + marvell,function = "nand"; + }; + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp5", "mpp21", "mpp23"; + marvell,function = "sata0"; + }; + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp4", "mpp20", "mpp22"; + marvell,function = "sata1"; + }; + pmx_spi: pmx-spi { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; + marvell,function = "spi"; + }; + pmx_twsi0: pmx-twsi0 { + marvell,pins = "mpp8", "mpp9"; + marvell,function = "twsi0"; + }; + pmx_uart0: pmx-uart0 { + marvell,pins = "mpp10", "mpp11"; + marvell,function = "uart0"; + }; + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp13", "mpp14"; + marvell,function = "uart1"; + }; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi new file mode 100644 index 0000000..d6a4145 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -0,0 +1,35 @@ +/ { + ocp@f1000000 { + + pinctrl: pinctrl@10000 { + compatible = "marvell,88f6282-pinctrl"; + reg = <0x10000 0x20>; + + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp5", "mpp21", "mpp23"; + marvell,function = "sata0"; + }; + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp4", "mpp20", "mpp22"; + marvell,function = "sata1"; + }; + pmx_spi: pmx-spi { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; + marvell,function = "spi"; + }; + pmx_twsi0: pmx-twsi0 { + marvell,pins = "mpp8", "mpp9"; + marvell,function = "twsi0"; + }; + pmx_uart0: pmx-uart0 { + marvell,pins = "mpp10", "mpp11"; + marvell,function = "uart0"; + }; + + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp13", "mpp14"; + marvell,function = "uart1"; + }; + }; + }; +}; \ No newline at end of file -- cgit v0.10.2 From 1f6e46bf6e4d6284605f48d5116068b5e72b4bb2 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 17:00:46 +0100 Subject: ARM: Kirkwood: Convert TS219 to pinctrl. Make use of the pinctrl driver for configuring all the pins, instead of using the Orion mpp code. Signed-off-by: Andrew Lunn Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts index ccbf327..8295c83 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts @@ -1,8 +1,39 @@ /dts-v1/; /include/ "kirkwood-ts219.dtsi" +/include/ "kirkwood-6281.dtsi" / { + ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi + &pmx_twsi0 &pmx_sata0 &pmx_sata1 + &pmx_ram_size &pmx_reset_button + &pmx_USB_copy_button &pmx_board_id>; + pinctrl-names = "default"; + + pmx_ram_size: pmx-ram-size { + /* RAM: 0: 256 MB, 1: 512 MB */ + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + pmx_USB_copy_button: pmx-USB-copy-button { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + pmx_reset_button: pmx-reset-button { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + pmx_board_id: pmx-board-id { + /* 0: TS-11x, 1: TS-21x */ + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + }; + }; + gpio_keys { compatible = "gpio-keys"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts index fbe9932..df3f95d 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts @@ -1,8 +1,39 @@ /dts-v1/; /include/ "kirkwood-ts219.dtsi" +/include/ "kirkwood-6282.dtsi" / { + ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi + &pmx_twsi0 &pmx_sata0 &pmx_sata1 + &pmx_ram_size &pmx_reset_button + &pmx_USB_copy_button &pmx_board_id>; + pinctrl-names = "default"; + + pmx_ram_size: pmx-ram-size { + /* RAM: 0: 256 MB, 1: 512 MB */ + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + pmx_reset_button: pmx-reset-button { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + pmx_USB_copy_button: pmx-USB-copy-button { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_board_id: pmx-board-id { + /* 0: TS-11x, 1: TS-21x */ + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + }; + }; + gpio_keys { compatible = "gpio-keys"; #address-cells = <1>; diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c index 5a031b9..329ff68 100644 --- a/arch/arm/mach-kirkwood/board-ts219.c +++ b/arch/arm/mach-kirkwood/board-ts219.c @@ -26,41 +26,16 @@ #include #include #include "common.h" -#include "mpp.h" #include "tsx1x-common.h" static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; -static unsigned int qnap_ts219_mpp_config[] __initdata = { - MPP0_SPI_SCn, - MPP1_SPI_MOSI, - MPP2_SPI_SCK, - MPP3_SPI_MISO, - MPP4_SATA1_ACTn, - MPP5_SATA0_ACTn, - MPP8_TW0_SDA, - MPP9_TW0_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP13_UART1_TXD, /* PIC controller */ - MPP14_UART1_RXD, /* PIC controller */ - MPP15_GPIO, /* USB Copy button (on devices with 88F6281) */ - MPP16_GPIO, /* Reset button (on devices with 88F6281) */ - MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ - MPP37_GPIO, /* Reset button (on devices with 88F6282) */ - MPP43_GPIO, /* USB Copy button (on devices with 88F6282) */ - MPP44_GPIO, /* Board ID: 0: TS-11x, 1: TS-21x */ - 0 -}; - void __init qnap_dt_ts219_init(void) { u32 dev, rev; - kirkwood_mpp_conf(qnap_ts219_mpp_config); - kirkwood_pcie_id(&dev, &rev); if (dev == MV88F6282_DEV_ID) qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0); -- cgit v0.10.2 From 2601c2549713ad0601e7e92350733930abf0693c Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 17:00:47 +0100 Subject: ARM: Kirkwood: Convert iConnect to pinctrl. Signed-off-by: Andrew Lunn Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index d97cd9d..504f16b 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -1,6 +1,7 @@ /dts-v1/; /include/ "kirkwood.dtsi" +/include/ "kirkwood-6281.dtsi" / { model = "Iomega Iconnect"; @@ -18,6 +19,56 @@ }; ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pinctrl-0 = < &pmx_gpio_12 &pmx_gpio_35 + &pmx_gpio_41 &pmx_gpio_42 + &pmx_gpio_43 &pmx_gpio_44 + &pmx_gpio_45 &pmx_gpio_46 + &pmx_gpio_47 &pmx_gpio_48 >; + pinctrl-names = "default"; + + pmx_gpio_12: pmx-gpio-12 { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + pmx_gpio_35: pmx-gpio-35 { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + pmx_gpio_41: pmx-gpio-41 { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + pmx_gpio_42: pmx-gpio-42 { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + pmx_gpio_43: pmx-gpio-43 { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_gpio_44: pmx-gpio-44 { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + pmx_gpio_45: pmx-gpio-45 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + pmx_gpio_46: pmx-gpio-46 { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_gpio_47: pmx-gpio-47 { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + pmx_gpio_48: pmx-gpio-48 { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + }; i2c@11000 { status = "okay"; diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c index 8275fb0..7d3c54c 100644 --- a/arch/arm/mach-kirkwood/board-iconnect.c +++ b/arch/arm/mach-kirkwood/board-iconnect.c @@ -21,30 +21,13 @@ #include #include #include "common.h" -#include "mpp.h" static struct mv643xx_eth_platform_data iconnect_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(11), }; -static unsigned int iconnect_mpp_config[] __initdata = { - MPP12_GPIO, - MPP35_GPIO, - MPP41_GPIO, - MPP42_GPIO, - MPP43_GPIO, - MPP44_GPIO, - MPP45_GPIO, - MPP46_GPIO, - MPP47_GPIO, - MPP48_GPIO, - 0 -}; - void __init iconnect_init(void) { - kirkwood_mpp_conf(iconnect_mpp_config); - kirkwood_ge00_init(&iconnect_ge00_data); } -- cgit v0.10.2 From f83065fa43c19600752a380f6d861b787a30d905 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 17:00:48 +0100 Subject: ARM: Kirkwood: Convert dnskw to pinctrl Signed-off-by: Andrew Lunn Signed-off-by: Jamie Lentin Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index d11054f..6875ac0 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -1,4 +1,5 @@ /include/ "kirkwood.dtsi" +/include/ "kirkwood-6281.dtsi" / { model = "D-Link DNS NASes (kirkwood-based)"; @@ -41,6 +42,110 @@ }; ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pinctrl-0 = < &pmx_nand &pmx_uart1 + &pmx_sata0 &pmx_sata1 + &pmx_led_power + &pmx_led_red_right_hdd + &pmx_led_red_left_hdd + &pmx_led_red_usb_325 + &pmx_button_power + &pmx_led_red_usb_320 + &pmx_power_off &pmx_power_back_on + &pmx_power_sata0 &pmx_power_sata1 + &pmx_present_sata0 &pmx_present_sata1 + &pmx_led_white_usb &pmx_fan_tacho + &pmx_fan_high_speed &pmx_fan_low_speed + &pmx_button_unmount &pmx_button_reset + &pmx_temp_alarm >; + pinctrl-names = "default"; + + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp20"; + marvell,function = "sata1"; + }; + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp21"; + marvell,function = "sata0"; + }; + pmx_led_power: pmx-led-power { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + pmx_led_red_right_hdd: pmx-led-red-right-hdd { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; + pmx_led_red_left_hdd: pmx-led-red-left-hdd { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + pmx_led_red_usb_325: pmx-led-red-usb-325 { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + pmx_button_power: pmx-button-power { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + pmx_led_red_usb_320: pmx-led-red-usb-320 { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + pmx_power_off: pmx-power-off { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + pmx_power_back_on: pmx-power-back-on { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + pmx_power_sata0: pmx-power-sata0 { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + pmx_power_sata1: pmx-power-sata1 { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + pmx_present_sata0: pmx-present-sata0 { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + pmx_present_sata1: pmx-present-sata1 { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + pmx_led_white_usb: pmx-led-white-usb { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_fan_tacho: pmx-fan-tacho { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + pmx_fan_high_speed: pmx-fan-high-speed { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + pmx_fan_low_speed: pmx-fan-low-speed { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_button_unmount: pmx-button-unmount { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + pmx_button_reset: pmx-button-reset { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + pmx_temp_alarm: pmx-temp-alarm { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + }; sata@80000 { status = "okay"; nr-ports = <2>; diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c index 6c4028c..a1aa87f 100644 --- a/arch/arm/mach-kirkwood/board-dnskw.c +++ b/arch/arm/mach-kirkwood/board-dnskw.c @@ -17,46 +17,11 @@ #include #include #include "common.h" -#include "mpp.h" static struct mv643xx_eth_platform_data dnskw_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; -static unsigned int dnskw_mpp_config[] __initdata = { - MPP13_UART1_TXD, /* Custom ... */ - MPP14_UART1_RXD, /* ... Controller (DNS-320 only) */ - MPP20_SATA1_ACTn, /* LED: White Right HDD */ - MPP21_SATA0_ACTn, /* LED: White Left HDD */ - MPP24_GPIO, - MPP25_GPIO, - MPP26_GPIO, /* LED: Power */ - MPP27_GPIO, /* LED: Red Right HDD */ - MPP28_GPIO, /* LED: Red Left HDD */ - MPP29_GPIO, /* LED: Red USB (DNS-325 only) */ - MPP30_GPIO, - MPP31_GPIO, - MPP32_GPIO, - MPP33_GPO, - MPP34_GPIO, /* Button: Front power */ - MPP35_GPIO, /* LED: Red USB (DNS-320 only) */ - MPP36_GPIO, /* Power: Turn off board */ - MPP37_GPIO, /* Power: Turn back on after power failure */ - MPP38_GPIO, - MPP39_GPIO, /* Power: SATA0 */ - MPP40_GPIO, /* Power: SATA1 */ - MPP41_GPIO, /* SATA0 present */ - MPP42_GPIO, /* SATA1 present */ - MPP43_GPIO, /* LED: White USB */ - MPP44_GPIO, /* Fan: Tachometer Pin */ - MPP45_GPIO, /* Fan: high speed */ - MPP46_GPIO, /* Fan: low speed */ - MPP47_GPIO, /* Button: Back unmount */ - MPP48_GPIO, /* Button: Back reset */ - MPP49_GPIO, /* Temp Alarm (DNS-325) Pin of U5 (DNS-320) */ - 0 -}; - /* Register any GPIO for output and set the value */ static void __init dnskw_gpio_register(unsigned gpio, char *name, int def) { @@ -71,8 +36,6 @@ static void __init dnskw_gpio_register(unsigned gpio, char *name, int def) void __init dnskw_init(void) { - kirkwood_mpp_conf(dnskw_mpp_config); - kirkwood_ge00_init(&dnskw_ge00_data); /* Set NAS to turn back on after a power failure */ -- cgit v0.10.2 From 1bf370a827175665d9b0e591a99243de0f6bb4e3 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 17:00:49 +0100 Subject: ARM: Kirkwood: Convert dockstar to pinctrl. Signed-off-by: Andrew Lunn Tested-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index c0fbfdc..2e3dd34 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -1,6 +1,7 @@ /dts-v1/; /include/ "kirkwood.dtsi" +/include/ "kirkwood-6281.dtsi" / { model = "Seagate FreeAgent Dockstar"; @@ -16,6 +17,25 @@ }; ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pinctrl-0 = < &pmx_usb_power_enable + &pmx_led_green &pmx_led_orange >; + pinctrl-names = "default"; + + pmx_usb_power_enable: pmx-usb-power-enable { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + pmx_led_green: pmx-led-green { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_led_orange: pmx-led-orange { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + }; serial@12000 { clock-frequency = <200000000>; status = "ok"; diff --git a/arch/arm/mach-kirkwood/board-dockstar.c b/arch/arm/mach-kirkwood/board-dockstar.c index 410452a..726cfc4 100644 --- a/arch/arm/mach-kirkwood/board-dockstar.c +++ b/arch/arm/mach-kirkwood/board-dockstar.c @@ -31,25 +31,15 @@ #include #include #include "common.h" -#include "mpp.h" static struct mv643xx_eth_platform_data dockstar_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(0), }; -static unsigned int dockstar_mpp_config[] __initdata = { - MPP29_GPIO, /* USB Power Enable */ - MPP46_GPIO, /* LED green */ - MPP47_GPIO, /* LED orange */ - 0 -}; - void __init dockstar_dt_init(void) { /* * Basic setup. Needs to be called early. */ - kirkwood_mpp_conf(dockstar_mpp_config); - kirkwood_ge00_init(&dockstar_ge00_data); } -- cgit v0.10.2 From 56942287bea45afdc331f95975fbafab37dfd595 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 17:00:50 +0100 Subject: ARM: Kirkwood: Convert dreamplug to pinctrl. Signed-off-by: Andrew Lunn Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts index 26e281f..f2d386c 100644 --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts @@ -1,6 +1,7 @@ /dts-v1/; /include/ "kirkwood.dtsi" +/include/ "kirkwood-6281.dtsi" / { model = "Globalscale Technologies Dreamplug"; @@ -16,6 +17,26 @@ }; ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pinctrl-0 = < &pmx_spi + &pmx_led_bluetooth &pmx_led_wifi + &pmx_led_wifi_ap >; + pinctrl-names = "default"; + + pmx_led_bluetooth: pmx-led-bluetooth { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + pmx_led_wifi: pmx-led-wifi { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + pmx_led_wifi_ap: pmx-led-wifi-ap { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + }; serial@12000 { clock-frequency = <200000000>; status = "ok"; diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c index acdc04a..3e2d95d 100644 --- a/arch/arm/mach-kirkwood/board-dreamplug.c +++ b/arch/arm/mach-kirkwood/board-dreamplug.c @@ -32,7 +32,6 @@ #include #include #include "common.h" -#include "mpp.h" static struct mv643xx_eth_platform_data dreamplug_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(0), @@ -46,24 +45,11 @@ static struct mvsdio_platform_data dreamplug_mvsdio_data = { /* unfortunately the CD signal has not been connected */ }; -static unsigned int dreamplug_mpp_config[] __initdata = { - MPP0_SPI_SCn, - MPP1_SPI_MOSI, - MPP2_SPI_SCK, - MPP3_SPI_MISO, - MPP47_GPIO, /* Bluetooth LED */ - MPP48_GPIO, /* Wifi LED */ - MPP49_GPIO, /* Wifi AP LED */ - 0 -}; - void __init dreamplug_init(void) { /* * Basic setup. Needs to be called early. */ - kirkwood_mpp_conf(dreamplug_mpp_config); - kirkwood_ge00_init(&dreamplug_ge00_data); kirkwood_ge01_init(&dreamplug_ge01_data); kirkwood_sdio_init(&dreamplug_mvsdio_data); -- cgit v0.10.2 From 5d183ef9100ca6005b4bb250db75bc006110b18a Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 17:00:51 +0100 Subject: ARM: Kirkwood: Convert GoFlex Net to pinctrl. Signed-off-by: Andrew Lunn Tested-by: Joshua Coombs Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index 84de887..1b133e0 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -1,6 +1,7 @@ /dts-v1/; /include/ "kirkwood.dtsi" +/include/ "kirkwood-6281.dtsi" / { model = "Seagate GoFlex Net"; @@ -16,6 +17,61 @@ }; ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange + &pmx_led_left_cap_0 &pmx_led_left_cap_1 + &pmx_led_left_cap_2 &pmx_led_left_cap_3 + &pmx_led_right_cap_0 &pmx_led_right_cap_1 + &pmx_led_right_cap_2 &pmx_led_right_cap_3 + >; + pinctrl-names = "default"; + + pmx_usb_power_enable: pmx-usb-power-enable { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + pmx_led_right_cap_0: pmx-led_right_cap_0 { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + pmx_led_right_cap_1: pmx-led_right_cap_1 { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + pmx_led_right_cap_2: pmx-led_right_cap_2 { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + pmx_led_right_cap_3: pmx-led_right_cap_3 { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + pmx_led_left_cap_0: pmx-led_left_cap_0 { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + pmx_led_left_cap_1: pmx-led_left_cap_1 { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_led_left_cap_2: pmx-led_left_cap_2 { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + pmx_led_left_cap_3: pmx-led_left_cap_3 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + pmx_led_green: pmx-led_green { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_led_orange: pmx-led_orange { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + }; serial@12000 { clock-frequency = <200000000>; status = "ok"; diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c index 5ff4392..3b96618 100644 --- a/arch/arm/mach-kirkwood/board-goflexnet.c +++ b/arch/arm/mach-kirkwood/board-goflexnet.c @@ -33,33 +33,15 @@ #include #include #include "common.h" -#include "mpp.h" static struct mv643xx_eth_platform_data goflexnet_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(0), }; -static unsigned int goflexnet_mpp_config[] __initdata = { - MPP29_GPIO, /* USB Power Enable */ - MPP47_GPIO, /* LED Orange */ - MPP46_GPIO, /* LED Green */ - MPP45_GPIO, /* LED Left Capacity 3 */ - MPP44_GPIO, /* LED Left Capacity 2 */ - MPP43_GPIO, /* LED Left Capacity 1 */ - MPP42_GPIO, /* LED Left Capacity 0 */ - MPP41_GPIO, /* LED Right Capacity 3 */ - MPP40_GPIO, /* LED Right Capacity 2 */ - MPP39_GPIO, /* LED Right Capacity 1 */ - MPP38_GPIO, /* LED Right Capacity 0 */ - 0 -}; - void __init goflexnet_init(void) { /* * Basic setup. Needs to be called early. */ - kirkwood_mpp_conf(goflexnet_mpp_config); - kirkwood_ge00_init(&goflexnet_ge00_data); } -- cgit v0.10.2 From d1d0c04b951e8eb650e84925bcbd78c6b331cfc0 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 17:00:52 +0100 Subject: ARM: Kirkwood: Convert ib62x0 to pinctrl. Signed-off-by: Andrew Lunn Tested-by: Simon Baatz Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index 6a9558d..71902da 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -1,6 +1,7 @@ /dts-v1/; /include/ "kirkwood.dtsi" +/include/ "kirkwood-6281.dtsi" / { model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; @@ -16,6 +17,39 @@ }; ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pinctrl-0 = < &pmx_nand + &pmx_led_os_red &pmx_power_off + &pmx_led_os_green &pmx_led_usb_transfer + &pmx_button_reset &pmx_button_usb_copy >; + pinctrl-names = "default"; + + pmx_led_os_red: pmx-led-os-red { + marvell,pins = "mpp22"; + marvell,function = "gpio"; + }; + pmx_power_off: pmx-power-off { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + pmx_led_os_green: pmx-led-os-green { + marvell,pins = "mpp25"; + marvell,function = "gpio"; + }; + pmx_led_usb_transfer: pmx-led-usb-transfer { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; + pmx_button_reset: pmx-button-reset { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + pmx_button_usb_copy: pmx-button-usb-copy { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + }; serial@12000 { clock-frequency = <200000000>; status = "okay"; diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c index 2a58b4fc..b6e5db9 100644 --- a/arch/arm/mach-kirkwood/board-ib62x0.c +++ b/arch/arm/mach-kirkwood/board-ib62x0.c @@ -22,36 +22,15 @@ #include #include #include "common.h" -#include "mpp.h" static struct mv643xx_eth_platform_data ib62x0_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; -static unsigned int ib62x0_mpp_config[] __initdata = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP22_GPIO, /* OS LED red */ - MPP24_GPIO, /* Power off device */ - MPP25_GPIO, /* OS LED green */ - MPP27_GPIO, /* USB transfer LED */ - MPP28_GPIO, /* Reset button */ - MPP29_GPIO, /* USB Copy button */ - 0 -}; - void __init ib62x0_init(void) { /* * Basic setup. Needs to be called early. */ - kirkwood_mpp_conf(ib62x0_mpp_config); - kirkwood_ge00_init(&ib62x0_ge00_data); } -- cgit v0.10.2 From 8d72b4a6cf3d1bac5e2d61acb6abaee254426779 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 17:00:53 +0100 Subject: ARM: Kirkwood: Convert lsxl boards to pinctrl. Signed-off-by: Andrew Lunn Tested-by: Michael Walle Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index 32d302e..37d45c4 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi @@ -1,4 +1,5 @@ /include/ "kirkwood.dtsi" +/include/ "kirkwood-6281.dtsi" / { chosen { @@ -6,6 +7,71 @@ }; ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pinctrl-0 = < &pmx_power_hdd &pmx_usb_vbus + &pmx_fan_low &pmx_fan_high + &pmx_led_function_red &pmx_led_alarm + &pmx_led_info &pmx_led_power + &pmx_fan_lock &pmx_button_function + &pmx_power_switch &pmx_power_auto_switch + &pmx_led_function_blue >; + pinctrl-names = "default"; + + pmx_power_hdd: pmx-power-hdd { + marvell,pins = "mpp10"; + marvell,function = "gpo"; + }; + pmx_usb_vbus: pmx-usb-vbus { + marvell,pins = "mpp11"; + marvell,function = "gpio"; + }; + pmx_fan_high: pmx-fan-high { + marvell,pins = "mpp18"; + marvell,function = "gpo"; + }; + pmx_fan_low: pmx-fan-low { + marvell,pins = "mpp19"; + marvell,function = "gpo"; + }; + pmx_led_function_blue: pmx-led-function-blue { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + pmx_led_alarm: pmx-led-alarm { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + pmx_led_info: pmx-led-info { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + pmx_led_power: pmx-led-power { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + pmx_fan_lock: pmx-fan-lock { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + pmx_button_function: pmx-button-function { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + pmx_power_switch: pmx-power-switch { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + pmx_power_auto_switch: pmx-power-auto-switch { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_led_function_red: pmx-led-function_red { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + + }; sata@80000 { status = "okay"; nr-ports = <1>; diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c index f780e2e..d60cdab 100644 --- a/arch/arm/mach-kirkwood/board-lsxl.c +++ b/arch/arm/mach-kirkwood/board-lsxl.c @@ -20,7 +20,6 @@ #include #include #include "common.h" -#include "mpp.h" static struct mv643xx_eth_platform_data lsxl_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(0), @@ -30,23 +29,6 @@ static struct mv643xx_eth_platform_data lsxl_ge01_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; -static unsigned int lsxl_mpp_config[] __initdata = { - MPP10_GPO, /* HDD Power Enable */ - MPP11_GPIO, /* USB Vbus Enable */ - MPP18_GPO, /* FAN High Enable# */ - MPP19_GPO, /* FAN Low Enable# */ - MPP36_GPIO, /* Function Blue LED */ - MPP37_GPIO, /* Alarm LED */ - MPP38_GPIO, /* Info LED */ - MPP39_GPIO, /* Power LED */ - MPP40_GPIO, /* Fan Lock */ - MPP41_GPIO, /* Function Button */ - MPP42_GPIO, /* Power Switch */ - MPP43_GPIO, /* Power Auto Switch */ - MPP48_GPIO, /* Function Red LED */ - 0 -}; - /* * On the LS-XHL/LS-CHLv2, the shutdown process is following: * - Userland monitors key events until the power switch goes to off position @@ -65,7 +47,6 @@ void __init lsxl_init(void) /* * Basic setup. Needs to be called early. */ - kirkwood_mpp_conf(lsxl_mpp_config); kirkwood_ge00_init(&lsxl_ge00_data); kirkwood_ge01_init(&lsxl_ge01_data); -- cgit v0.10.2 From a93d3ad2e34718a83f5c537eafdfe3a74806060c Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 17:00:54 +0100 Subject: ARM: Kirkwood: Convert IX2-200 to pinctrl. Signed-off-by: Andrew Lunn Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 865aeec..6cae459 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -1,6 +1,7 @@ /dts-v1/; /include/ "kirkwood.dtsi" +/include/ "kirkwood-6281.dtsi" / { model = "Iomega StorCenter ix2-200"; @@ -16,6 +17,94 @@ }; ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pinctrl-0 = < &pmx_button_reset &pmx_button_power + &pmx_led_backup &pmx_led_power + &pmx_button_otb &pmx_led_rebuild + &pmx_led_health + &pmx_led_sata_brt_ctrl_1 + &pmx_led_sata_brt_ctrl_2 + &pmx_led_backup_brt_ctrl_1 + &pmx_led_backup_brt_ctrl_2 + &pmx_led_power_brt_ctrl_1 + &pmx_led_power_brt_ctrl_2 + &pmx_led_health_brt_ctrl_1 + &pmx_led_health_brt_ctrl_2 + &pmx_led_rebuild_brt_ctrl_1 + &pmx_led_rebuild_brt_ctrl_2 >; + pinctrl-names = "default"; + + pmx_button_reset: pmx-button-reset { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + pmx_button_power: pmx-button-power { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + pmx_led_backup: pmx-led-backup { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + pmx_led_power: pmx-led-power { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + pmx_button_otb: pmx-button-otb { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + pmx_led_rebuild: pmx-led-rebuild { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + pmx_led_health: pmx-led_health { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + pmx_led_sata_brt_ctrl_1: pmx-led-sata-brt-ctrl-1 { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + pmx_led_sata_brt_ctrl_2: pmx-led-sata-brt-ctrl-2 { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + pmx_led_backup_brt_ctrl_1: pmx-led-backup-brt-ctrl-1 { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + pmx_led_backup_brt_ctrl_2: pmx-led-backup-brt-ctrl-2 { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + pmx_led_power_brt_ctrl_1: pmx-led-power-brt-ctrl-1 { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + pmx_led_power_brt_ctrl_2: pmx-led-power-brt-ctrl-2 { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_led_health_brt_ctrl_1: pmx-led-health-brt-ctrl-1 { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + pmx_led_health_brt_ctrl_2: pmx-led-health-brt-ctrl-2 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + }; i2c@11000 { status = "okay"; diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c index a6f3d29..22b8649 100644 --- a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c +++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c @@ -15,7 +15,6 @@ #include #include #include "common.h" -#include "mpp.h" static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = { .phy_addr = MV643XX_ETH_PHY_NONE, @@ -23,33 +22,10 @@ static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = { .duplex = DUPLEX_FULL, }; -static unsigned int iomega_ix2_200_mpp_config[] __initdata = { - MPP12_GPIO, /* Reset Button */ - MPP14_GPIO, /* Power Button */ - MPP15_GPIO, /* Backup LED (blue) */ - MPP16_GPIO, /* Power LED (white) */ - MPP35_GPIO, /* OTB Button */ - MPP36_GPIO, /* Rebuild LED (white) */ - MPP37_GPIO, /* Health LED (red) */ - MPP38_GPIO, /* SATA LED brightness control 1 */ - MPP39_GPIO, /* SATA LED brightness control 2 */ - MPP40_GPIO, /* Backup LED brightness control 1 */ - MPP41_GPIO, /* Backup LED brightness control 2 */ - MPP42_GPIO, /* Power LED brightness control 1 */ - MPP43_GPIO, /* Power LED brightness control 2 */ - MPP44_GPIO, /* Health LED brightness control 1 */ - MPP45_GPIO, /* Health LED brightness control 2 */ - MPP46_GPIO, /* Rebuild LED brightness control 1 */ - MPP47_GPIO, /* Rebuild LED brightness control 2 */ - 0 -}; - void __init iomega_ix2_200_init(void) { /* * Basic setup. Needs to be called early. */ - kirkwood_mpp_conf(iomega_ix2_200_mpp_config); - kirkwood_ge01_init(&iomega_ix2_200_ge00_data); } -- cgit v0.10.2 From 4e5bc99ce97fec27466a0654b35d4d3ae0afb054 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Sat, 17 Nov 2012 17:00:55 +0100 Subject: ARM: Kirkwood: support 98DX412x kirkwoods with pinctrl The Marvell 98DX412x SoC embed a kirkwood variant that does not have pinctrl support yet. Even though this kirkwood is very similar to the 88f6281, on the MPP front a lot of pins are not available. That's why a new kirkwood pinctrl variant is needed. Signed-off-by: Valentin Longchamp Signed-off-by: Andrew Lunn Signed-off-by: Jason Cooper diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt index 361bccb..95daf63 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt @@ -7,8 +7,10 @@ Required properties: - compatible: "marvell,88f6180-pinctrl", "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl", "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl" + "marvell,98dx4122-pinctrl" This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x. +It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs. Available mpp pins/groups and functions: Note: brackets (x) are not part of the mpp name for marvell,function and given @@ -277,3 +279,40 @@ mpp46 46 gpio, ts(mp10), tdm(fs), lcd(hsync) mpp47 47 gpio, ts(mp11), tdm(drx), lcd(vsync) mpp48 48 gpio, ts(mp12), tdm(dtx), lcd(d16) mpp49 49 gpo, tdm(rx0ql), pex(clkreq), lcd(d17) + +* Marvell Bobcat 98dx4122 + +name pins functions +================================================================================ +mpp0 0 gpio, nand(io2), spi(cs) +mpp1 1 gpo, nand(io3), spi(mosi) +mpp2 2 gpo, nand(io4), spi(sck) +mpp3 3 gpo, nand(io5), spi(miso) +mpp4 4 gpio, nand(io6), uart0(rxd) +mpp5 5 gpo, nand(io7), uart0(txd) +mpp6 6 sysrst(out), spi(mosi) +mpp7 7 gpo, pex(rsto), spi(cs) +mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts) +mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts) +mpp10 10 gpo, spi(sck), uart0(txd) +mpp11 11 gpio, spi(miso), uart0(rxd) +mpp13 13 gpio, uart1(txd) +mpp14 14 gpio, uart1(rxd) +mpp15 15 gpio, uart0(rts) +mpp16 16 gpio, uart0(cts) +mpp18 18 gpo, nand(io0) +mpp19 19 gpo, nand(io1) +mpp34 34 gpio +mpp35 35 gpio +mpp36 36 gpio +mpp37 37 gpio +mpp38 38 gpio +mpp39 39 gpio +mpp40 40 gpio +mpp41 41 gpio +mpp42 42 gpio +mpp43 43 gpio +mpp44 44 gpio +mpp45 45 gpio +mpp49 49 gpio + diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi new file mode 100644 index 0000000..3271e4c --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi @@ -0,0 +1,31 @@ +/ { + ocp@f1000000 { + pinctrl: pinctrl@10000 { + compatible = "marvell,98dx4122-pinctrl"; + reg = <0x10000 0x20>; + + pmx_nand: pmx-nand { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp18", + "mpp19"; + marvell,function = "nand"; + }; + pmx_spi: pmx-spi { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; + marvell,function = "spi"; + }; + pmx_twsi0: pmx-twsi0 { + marvell,pins = "mpp8", "mpp9"; + marvell,function = "twsi0"; + }; + pmx_uart0: pmx-uart0 { + marvell,pins = "mpp10", "mpp11"; + marvell,function = "uart0"; + }; + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp13", "mpp14"; + marvell,function = "uart1"; + }; + }; + }; +}; diff --git a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c index 9a74ef6..fa6ce31 100644 --- a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c +++ b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c @@ -21,340 +21,341 @@ #include "pinctrl-mvebu.h" -#define V(f6180, f6190, f6192, f6281, f6282) \ +#define V(f6180, f6190, f6192, f6281, f6282, dx4122) \ ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \ - (f6281 << 3) | (f6282 << 4)) + (f6281 << 3) | (f6282 << 4) | (dx4122 << 5)) enum kirkwood_variant { - VARIANT_MV88F6180 = V(1, 0, 0, 0, 0), - VARIANT_MV88F6190 = V(0, 1, 0, 0, 0), - VARIANT_MV88F6192 = V(0, 0, 1, 0, 0), - VARIANT_MV88F6281 = V(0, 0, 0, 1, 0), - VARIANT_MV88F6282 = V(0, 0, 0, 0, 1), + VARIANT_MV88F6180 = V(1, 0, 0, 0, 0, 0), + VARIANT_MV88F6190 = V(0, 1, 0, 0, 0, 0), + VARIANT_MV88F6192 = V(0, 0, 1, 0, 0, 0), + VARIANT_MV88F6281 = V(0, 0, 0, 1, 0, 0), + VARIANT_MV88F6282 = V(0, 0, 0, 0, 1, 0), + VARIANT_MV98DX4122 = V(0, 0, 0, 0, 0, 1), }; static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = { MPP_MODE(0, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "nand", "io2", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "nand", "io2", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1, 1))), MPP_MODE(1, - MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "nand", "io3", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1))), + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "nand", "io3", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1, 1))), MPP_MODE(2, - MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "nand", "io4", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1))), + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "nand", "io4", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1, 1))), MPP_MODE(3, - MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "nand", "io5", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1))), + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "nand", "io5", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1, 1))), MPP_MODE(4, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "nand", "io6", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "uart0", "rxd", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1)), - MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "nand", "io6", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "uart0", "rxd", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0, 0))), MPP_MODE(5, - MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "nand", "io7", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "uart0", "txd", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x4, "ptp", "trig", V(1, 1, 1, 1, 0)), - MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "nand", "io7", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "uart0", "txd", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x4, "ptp", "trig", V(1, 1, 1, 1, 0, 0)), + MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1, 0))), MPP_MODE(6, - MPP_VAR_FUNCTION(0x0, "sysrst", "out", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "spi", "mosi", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "ptp", "trig", V(1, 1, 1, 1, 0))), + MPP_VAR_FUNCTION(0x0, "sysrst", "out", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "spi", "mosi", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "ptp", "trig", V(1, 1, 1, 1, 0, 0))), MPP_MODE(7, - MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "pex", "rsto", V(1, 1, 1, 1, 0)), - MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "ptp", "trig", V(1, 1, 1, 1, 0)), - MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "pex", "rsto", V(1, 1, 1, 1, 0, 1)), + MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x3, "ptp", "trig", V(1, 1, 1, 1, 0, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1, 0))), MPP_MODE(8, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "twsi0", "sda", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "uart1", "rts", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x4, "mii-1", "rxerr", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0xc, "ptp", "clk", V(1, 1, 1, 1, 0)), - MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "twsi0", "sda", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x3, "uart1", "rts", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x4, "mii-1", "rxerr", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xc, "ptp", "clk", V(1, 1, 1, 1, 0, 0)), + MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1, 0))), MPP_MODE(9, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "twsi0", "sck", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "uart1", "cts", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0xc, "ptp", "evreq", V(1, 1, 1, 1, 0)), - MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "twsi0", "sck", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x3, "uart1", "cts", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xc, "ptp", "evreq", V(1, 1, 1, 1, 0, 0)), + MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1, 0))), MPP_MODE(10, - MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0X3, "uart0", "txd", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0xc, "ptp", "trig", V(1, 1, 1, 1, 0))), + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0X3, "uart0", "txd", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xc, "ptp", "trig", V(1, 1, 1, 1, 0, 0))), MPP_MODE(11, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "uart0", "rxd", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x4, "ptp-1", "evreq", V(1, 1, 1, 1, 0)), - MPP_VAR_FUNCTION(0xc, "ptp-2", "trig", V(1, 1, 1, 1, 0)), - MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0)), - MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x3, "uart0", "rxd", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x4, "ptp-1", "evreq", V(1, 1, 1, 1, 0, 0)), + MPP_VAR_FUNCTION(0xc, "ptp-2", "trig", V(1, 1, 1, 1, 0, 0)), + MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0, 0)), + MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0))), MPP_MODE(12, - MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 0, 1)), - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0)), - MPP_VAR_FUNCTION(0x1, "sdio", "clk", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1)), - MPP_VAR_FUNCTION(0xb, "spi", "mosi", V(0, 0, 0, 0, 1)), - MPP_VAR_FUNCTION(0xd, "twsi1", "sda", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 0, 1, 0)), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0, 0)), + MPP_VAR_FUNCTION(0x1, "sdio", "clk", V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xb, "spi", "mosi", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xd, "twsi1", "sda", V(0, 0, 0, 0, 1, 0))), MPP_MODE(13, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "sdio", "cmd", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0xa, "audio", "rmclk", V(0, 0, 0, 0, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "sdio", "cmd", V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0xa, "audio", "rmclk", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1, 0))), MPP_MODE(14, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "sdio", "d0", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1)), - MPP_VAR_FUNCTION(0xb, "audio-1", "sdi", V(0, 0, 0, 0, 1)), - MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "sdio", "d0", V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xb, "audio-1", "sdi", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1, 0))), MPP_MODE(15, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "sdio", "d1", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x4, "sata0", "act", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "spi", "cs", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "sdio", "d1", V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "sata0", "act", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "spi", "cs", V(0, 0, 0, 0, 1, 0))), MPP_MODE(16, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "sdio", "d2", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x4, "sata1", "act", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "extclk", V(0, 0, 0, 0, 1)), - MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "sdio", "d2", V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "sata1", "act", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "extclk", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1, 0))), MPP_MODE(17, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "sdio", "d3", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0xa, "sata1", "act", V(0, 0, 0, 0, 1)), - MPP_VAR_FUNCTION(0xd, "twsi1", "sck", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "sdio", "d3", V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xa, "sata1", "act", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xd, "twsi1", "sck", V(0, 0, 0, 0, 1, 0))), MPP_MODE(18, - MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "nand", "io0", V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "pex", "clkreq", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "nand", "io0", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "pex", "clkreq", V(0, 0, 0, 0, 1, 0))), MPP_MODE(19, - MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "nand", "io1", V(1, 1, 1, 1, 1))), + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "nand", "io1", V(1, 1, 1, 1, 1, 1))), MPP_MODE(20, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "ge1", "txd0", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d0", V(0, 0, 0, 0, 1)), - MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(1, 0, 0, 0, 0))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "txd0", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d0", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(1, 0, 0, 0, 0, 0))), MPP_MODE(21, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "ge1", "txd1", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 0, 0)), - MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d1", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "txd1", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d1", V(0, 0, 0, 0, 1, 0))), MPP_MODE(22, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "ge1", "txd2", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 0, 0)), - MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d2", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "txd2", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d2", V(0, 0, 0, 0, 1, 0))), MPP_MODE(23, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "ge1", "txd3", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(1, 0, 0, 0, 0)), - MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d3", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "txd3", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d3", V(0, 0, 0, 0, 1, 0))), MPP_MODE(24, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "ge1", "rxd0", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(1, 0, 0, 0, 0)), - MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d4", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "rxd0", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d4", V(0, 0, 0, 0, 1, 0))), MPP_MODE(25, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "ge1", "rxd1", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(1, 0, 0, 0, 0)), - MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d5", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "rxd1", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d5", V(0, 0, 0, 0, 1, 0))), MPP_MODE(26, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "ge1", "rxd2", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(1, 0, 0, 0, 0)), - MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d6", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "rxd2", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d6", V(0, 0, 0, 0, 1, 0))), MPP_MODE(27, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "ge1", "rxd3", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(1, 0, 0, 0, 0)), - MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d7", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "rxd3", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d7", V(0, 0, 0, 0, 1, 0))), MPP_MODE(28, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "ge1", "col", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(1, 0, 0, 0, 0)), - MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d8", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "col", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d8", V(0, 0, 0, 0, 1, 0))), MPP_MODE(29, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "ge1", "txclk", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 0, 0)), - MPP_VAR_FUNCTION(0xb, "lcd", "d9", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "txclk", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d9", V(0, 0, 0, 0, 1, 0))), MPP_MODE(30, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "ge1", "rxctl", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d10", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "rxctl", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d10", V(0, 0, 0, 0, 1, 0))), MPP_MODE(31, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "ge1", "rxclk", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d11", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "rxclk", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d11", V(0, 0, 0, 0, 1, 0))), MPP_MODE(32, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "ge1", "txclko", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d12", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "txclko", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d12", V(0, 0, 0, 0, 1, 0))), MPP_MODE(33, - MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "ge1", "txctl", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d13", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "txctl", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d13", V(0, 0, 0, 0, 1, 0))), MPP_MODE(34, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "ge1", "txen", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d14", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "txen", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d14", V(0, 0, 0, 0, 1, 0))), MPP_MODE(35, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1)), - MPP_VAR_FUNCTION(0x3, "ge1", "rxerr", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d15", V(0, 0, 0, 0, 1)), - MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(0, 1, 1, 1, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "rxerr", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d15", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(0, 1, 1, 1, 1, 0))), MPP_MODE(36, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0xb, "twsi1", "sda", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "twsi1", "sda", V(0, 0, 0, 0, 1, 0))), MPP_MODE(37, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0xb, "twsi1", "sck", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "twsi1", "sck", V(0, 0, 0, 0, 1, 0))), MPP_MODE(38, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d18", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d18", V(0, 0, 0, 0, 1, 0))), MPP_MODE(39, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d19", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d19", V(0, 0, 0, 0, 1, 0))), MPP_MODE(40, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d20", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d20", V(0, 0, 0, 0, 1, 0))), MPP_MODE(41, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d21", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d21", V(0, 0, 0, 0, 1, 0))), MPP_MODE(42, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d22", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d22", V(0, 0, 0, 0, 1, 0))), MPP_MODE(43, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d23", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d23", V(0, 0, 0, 0, 1, 0))), MPP_MODE(44, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "clk", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "clk", V(0, 0, 0, 0, 1, 0))), MPP_MODE(45, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "e", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "e", V(0, 0, 0, 0, 1, 0))), MPP_MODE(46, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1, 0))), MPP_MODE(47, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1, 0))), MPP_MODE(48, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d16", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d16", V(0, 0, 0, 0, 1, 0))), MPP_MODE(49, - MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0)), - MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 0, 0, 0, 1)), - MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 0)), - MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 0, 1, 1)), - MPP_VAR_FUNCTION(0x5, "ptp", "clk", V(0, 0, 0, 1, 0)), - MPP_VAR_FUNCTION(0xa, "pex", "clkreq", V(0, 0, 0, 0, 1)), - MPP_VAR_FUNCTION(0xb, "lcd", "d17", V(0, 0, 0, 0, 1))), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0, 1)), + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 0, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x5, "ptp", "clk", V(0, 0, 0, 1, 0, 0)), + MPP_VAR_FUNCTION(0xa, "pex", "clkreq", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d17", V(0, 0, 0, 0, 1, 0))), }; static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = { @@ -433,12 +434,23 @@ static struct mvebu_pinctrl_soc_info mv88f6282_info = { .ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges), }; +static struct mvebu_pinctrl_soc_info mv98dx4122_info = { + .variant = VARIANT_MV98DX4122, + .controls = mv88f628x_mpp_controls, + .ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls), + .modes = mv88f6xxx_mpp_modes, + .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes), + .gpioranges = mv88f628x_gpio_ranges, + .ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges), +}; + static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata = { { .compatible = "marvell,88f6180-pinctrl", .data = &mv88f6180_info }, { .compatible = "marvell,88f6190-pinctrl", .data = &mv88f6190_info }, { .compatible = "marvell,88f6192-pinctrl", .data = &mv88f6192_info }, { .compatible = "marvell,88f6281-pinctrl", .data = &mv88f6281_info }, { .compatible = "marvell,88f6282-pinctrl", .data = &mv88f6282_info }, + { .compatible = "marvell,98dx4122-pinctrl", .data = &mv98dx4122_info }, { } }; -- cgit v0.10.2 From 9891b3f63d551bcc249a4121f4bb5813dfda94db Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Sat, 17 Nov 2012 17:00:56 +0100 Subject: ARM: Kirkwood: Convert km_kirkwood to pinctrl Signed-off-by: Valentin Longchamp Signed-off-by: Andrew Lunn Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts index 75bdb93..8db3123 100644 --- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts @@ -1,6 +1,7 @@ /dts-v1/; /include/ "kirkwood.dtsi" +/include/ "kirkwood-98dx4122.dtsi" / { model = "Keymile Kirkwood Reference Design"; @@ -16,6 +17,22 @@ }; ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pinctrl-0 = < &pmx_nand &pmx_i2c_gpio_sda + &pmx_i2c_gpio_scl >; + pinctrl-names = "default"; + + pmx_i2c_gpio_sda: pmx-gpio-sda { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + pmx_i2c_gpio_scl: pmx-gpio-scl { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + }; + serial@12000 { clock-frequency = <200000000>; status = "ok"; diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c index 1e9ac4b..44e4605 100644 --- a/arch/arm/mach-kirkwood/board-km_kirkwood.c +++ b/arch/arm/mach-kirkwood/board-km_kirkwood.c @@ -18,27 +18,15 @@ #include #include #include "common.h" -#include "mpp.h" static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(0), }; -static unsigned int km_kirkwood_mpp_config[] __initdata = { - MPP8_GPIO, /* I2C SDA */ - MPP9_GPIO, /* I2C SCL */ - 0 -}; - void __init km_kirkwood_init(void) { struct clk *sata_clk; /* - * Basic setup. Needs to be called early. - */ - kirkwood_mpp_conf(km_kirkwood_mpp_config); - - /* * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing * SATA bits (14-15) of the Clock Gating Control Register. Since these * devices are also not present in this variant, their clocks get -- cgit v0.10.2 From de64ee5eabad1d7857890c730b21489561bd202e Mon Sep 17 00:00:00 2001 From: Stefan Peter Date: Mon, 19 Nov 2012 16:00:02 +0100 Subject: ARM: kirkwood: Convert mplcec4 board to pinctrl Signed-off-by: Stefan Peter Acked-by: Andrew Lunn Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index b0fe682..d6c9d65 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -34,6 +34,11 @@ marvell,pins = "mpp13", "mpp14"; marvell,function = "uart1"; }; + pmx_sdio: pmx-sdio { + marvell,pins = "mpp12", "mpp13", "mpp14", + "mpp15", "mpp16", "mpp17"; + marvell,function = "sdio"; + }; }; }; -}; \ No newline at end of file +}; diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index ac3c080..262c654 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -1,6 +1,7 @@ /dts-v1/; /include/ "kirkwood.dtsi" +/include/ "kirkwood-6281.dtsi" / { model = "MPL CEC4"; @@ -16,6 +17,64 @@ }; ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pinctrl-0 = < &pmx_nand &pmx_uart0 + &pmx_led_health &pmx_sdio + &pmx_sata0 &pmx_sata1 + &pmx_led_user1o + &pmx_led_user1g &pmx_led_user0o + &pmx_led_user0g &pmx_led_misc + &pmx_sdio_cd + >; + pinctrl-names = "default"; + + pmx_led_health: pmx-led-health { + marvell,pins = "mpp7"; + marvell,function = "gpo"; + }; + + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp34"; + marvell,function = "sata1"; + }; + + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp35"; + marvell,function = "sata0"; + }; + + pmx_led_user1o: pmx-led-user1o { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + pmx_led_user1g: pmx-led-user1g { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + pmx_led_user0o: pmx-led-user0o { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_led_user0g: pmx-led-user0g { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_led_misc: pmx-led-misc { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + }; + i2c@11000 { status = "okay"; diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c index e78a227..47e7181 100644 --- a/arch/arm/mach-kirkwood/board-mplcec4.c +++ b/arch/arm/mach-kirkwood/board-mplcec4.c @@ -24,51 +24,16 @@ static struct mv643xx_eth_platform_data mplcec4_ge01_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(2), }; -static unsigned int mplcec4_mpp_config[] __initdata = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_GPO, /* Status LED Green High Active */ - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_SD_CLK, - MPP13_SD_CMD, /* Alt UART1_TXD */ - MPP14_SD_D0, /* Alt UART1_RXD */ - MPP15_SD_D1, - MPP16_SD_D2, - MPP17_SD_D3, - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP28_GPIO, /* Input SYS_POR_DET (active High) */ - MPP29_GPIO, /* Input SYS_RTC_INT (active High) */ - MPP34_SATA1_ACTn, - MPP35_SATA0_ACTn, - MPP40_GPIO, /* LED User1 orange */ - MPP41_GPIO, /* LED User1 green */ - MPP44_GPIO, /* LED User0 orange */ - MPP45_GPIO, /* LED User0 green */ - MPP46_GPIO, /* Status LED Yellow High Active */ - MPP47_GPIO, /* SD_CD# (in/IRQ)*/ - 0 -}; - - static struct mvsdio_platform_data mplcec4_mvsdio_data = { .gpio_card_detect = 47, /* MPP47 used as SD card detect */ }; - void __init mplcec4_init(void) { /* * Basic setup. Needs to be called early. */ - kirkwood_mpp_conf(mplcec4_mpp_config); kirkwood_ehci_init(); kirkwood_ge00_init(&mplcec4_ge00_data); kirkwood_ge01_init(&mplcec4_ge01_data); -- cgit v0.10.2 From 083651f278ab250504b5aa10d0e351a203648673 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 23 Nov 2012 06:58:34 +0900 Subject: ARM: kirkwood: Add support DT of second I2C bus Second I2C bus is supported by 88f6282 and 88f6283. This creates kirkwood-6282.dtsi, and defines DT table of second I2C bus. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index d6a4145..9ae2004 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -31,5 +31,15 @@ marvell,function = "uart1"; }; }; + + i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <32>; + clock-frequency = <100000>; + status = "disabled"; + }; }; -}; \ No newline at end of file +}; -- cgit v0.10.2 From 1fd7b4dd8b107aec9ec28d2682ef1967e696d6a6 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 23 Nov 2012 06:30:10 +0900 Subject: ARM: kirkwood: Add support second I2C bus and RTC on OpenBlocks A6 OpenBlocks A6 uses second I2C with RTC of s35390a. This supports them. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index 9a2606c..bada756 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -1,6 +1,7 @@ /dts-v1/; /include/ "kirkwood.dtsi" +/include/ "kirkwood-6282.dtsi" / { model = "Plat'Home OpenBlocksA6"; @@ -35,5 +36,14 @@ nr-ports = <1>; status = "okay"; }; + + i2c@11100 { + status = "okay"; + + s35390a: s35390a@30 { + compatible = "s35390a"; + reg = <0x30>; + }; + }; }; }; -- cgit v0.10.2 From a6e9ed9f09a98c7e85f7dc04829eca5faeb1ea36 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 23 Nov 2012 06:30:11 +0900 Subject: ARM: kirkwood: Add NAND partiton map for OpenBlocks A6 Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index bada756..e80c9d0 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -30,6 +30,36 @@ nand@3000000 { chip-delay = <25>; status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0 0x90000>; + }; + + partition@90000 { + label = "env"; + reg = <0x90000 0x44000>; + }; + + partition@d4000 { + label = "test"; + reg = <0xd4000 0x24000>; + }; + + partition@f4000 { + label = "conf"; + reg = <0xf4000 0x400000>; + }; + + partition@4f4000 { + label = "linux"; + reg = <0x4f4000 0x1d20000>; + }; + + partition@2214000 { + label = "user"; + reg = <0x2214000 0x1dec000>; + }; }; sata@80000 { -- cgit v0.10.2 From 5cd0e6e79bc1064f26a137a33217a7dfbd541a50 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 23 Nov 2012 06:30:12 +0900 Subject: ARM: Kirkwood: Convert to EHCI via DT for OpenBlocks A6 EHCI driver enables by default in kirkwood.dtsi. This removes kirkwood_ehci_init function. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Jason Cooper diff --git a/arch/arm/mach-kirkwood/board-openblocks_a6.c b/arch/arm/mach-kirkwood/board-openblocks_a6.c index e807e8c..e71f984 100644 --- a/arch/arm/mach-kirkwood/board-openblocks_a6.c +++ b/arch/arm/mach-kirkwood/board-openblocks_a6.c @@ -66,6 +66,5 @@ void __init openblocks_a6_init(void) * Basic setup. Needs to be called early. */ kirkwood_mpp_conf(openblocks_a6_mpp_config); - kirkwood_ehci_init(); kirkwood_ge00_init(&openblocks_ge00_data); } -- cgit v0.10.2 From 155acbe7f7bf7563239ff4d188634930512d0c02 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sat, 24 Nov 2012 05:24:09 +0900 Subject: ARM: Kirkwood: Add support LED of OpenBlocks A6 OpenBlocks A6 has three leds via GPIO. This supports them. And this fix typo about led, because hardware manual has typo. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index e80c9d0..49d3d74 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -76,4 +76,23 @@ }; }; }; + + gpio-leds { + compatible = "gpio-leds"; + + led-red { + label = "obsa6:red:stat"; + gpios = <&gpio1 9 1>; + }; + + led-green { + label = "obsa6:green:stat"; + gpios = <&gpio1 10 1>; + }; + + led-yellow { + label = "obsa6:yellow:stat"; + gpios = <&gpio1 11 1>; + }; + }; }; diff --git a/arch/arm/mach-kirkwood/board-openblocks_a6.c b/arch/arm/mach-kirkwood/board-openblocks_a6.c index e71f984..815fc64 100644 --- a/arch/arm/mach-kirkwood/board-openblocks_a6.c +++ b/arch/arm/mach-kirkwood/board-openblocks_a6.c @@ -55,8 +55,8 @@ static unsigned int openblocks_a6_mpp_config[] __initdata = { MPP38_GPIO, /* INIT */ MPP39_GPIO, /* USB OC */ MPP41_GPIO, /* LED: Red */ - MPP42_GPIO, /* LED: Yellow */ - MPP43_GPIO, /* LED: Green */ + MPP42_GPIO, /* LED: Green */ + MPP43_GPIO, /* LED: Yellow */ 0, }; -- cgit v0.10.2 From 2a18588c0ce336933be3c99c91e74e21db56a0fe Mon Sep 17 00:00:00 2001 From: Jason Cooper Date: Sat, 24 Nov 2012 03:58:12 +0000 Subject: ARM: Kirkwood: remove kirkwood_ehci_init() from new boards ehci-orion initialization moved to DT. New boards don't need to call kirkwood_ehci_init(). Signed-off-by: Jason Cooper diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c index 47e7181..56bfe5a 100644 --- a/arch/arm/mach-kirkwood/board-mplcec4.c +++ b/arch/arm/mach-kirkwood/board-mplcec4.c @@ -34,7 +34,6 @@ void __init mplcec4_init(void) /* * Basic setup. Needs to be called early. */ - kirkwood_ehci_init(); kirkwood_ge00_init(&mplcec4_ge00_data); kirkwood_ge01_init(&mplcec4_ge01_data); kirkwood_sdio_init(&mplcec4_mvsdio_data); diff --git a/arch/arm/mach-kirkwood/board-ns2.c b/arch/arm/mach-kirkwood/board-ns2.c index 78596c4..8821720 100644 --- a/arch/arm/mach-kirkwood/board-ns2.c +++ b/arch/arm/mach-kirkwood/board-ns2.c @@ -73,7 +73,6 @@ void __init ns2_init(void) */ kirkwood_mpp_conf(ns2_mpp_config); - kirkwood_ehci_init(); if (of_machine_is_compatible("lacie,netspace_lite_v2") || of_machine_is_compatible("lacie,netspace_mini_v2")) ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0); diff --git a/arch/arm/mach-kirkwood/board-nsa310.c b/arch/arm/mach-kirkwood/board-nsa310.c index 027ce83..f58d2e1 100644 --- a/arch/arm/mach-kirkwood/board-nsa310.c +++ b/arch/arm/mach-kirkwood/board-nsa310.c @@ -85,10 +85,6 @@ void __init nsa310_init(void) nsa310_gpio_init(); - /* this can be removed once the mainline kirkwood.dtsi gets - * the ehci configuration by default */ - kirkwood_ehci_init(); - kirkwood_pcie_id(&dev, &rev); i2c_register_board_info(0, ARRAY_AND_SIZE(nsa310_i2c_info)); diff --git a/arch/arm/mach-kirkwood/board-usi_topkick.c b/arch/arm/mach-kirkwood/board-usi_topkick.c index e2ec9d8..15e69fc 100644 --- a/arch/arm/mach-kirkwood/board-usi_topkick.c +++ b/arch/arm/mach-kirkwood/board-usi_topkick.c @@ -76,7 +76,6 @@ void __init usi_topkick_init(void) /* SATA0 power enable */ gpio_set_value(TOPKICK_SATA0_PWR_ENABLE, 1); - kirkwood_ehci_init(); kirkwood_ge00_init(&topkick_ge00_data); kirkwood_sdio_init(&topkick_mvsdio_data); } -- cgit v0.10.2 From c94a4ab7af3f07424e3db0c77f6b532d0a7202de Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 15 Nov 2012 13:02:16 +0000 Subject: ARM: ux500: Disable the MMCI gpio-regulator by default Not all supported boards will require a MMCI gpio-regulator, therefore it's a good idea to only enable the node when and if it is required. Let's disable it by default. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index 7ce45fc..d8ba489 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -642,6 +642,8 @@ gpio-enable = <&tc3589x_gpio 17 0x4>; states = <1800000 0x1 2900000 0x0>; + + status = "disabled"; }; }; }; -- cgit v0.10.2 From 8ad49c65f551c15af3f1049d10ccbdcd376a295d Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 15 Nov 2012 13:07:02 +0000 Subject: ARM: ux500: Move board specific GPIO info out to subordinate DTS files GPIO numbers for the newly created gpio-regulator will differ from board to board. Therefore it's not sensible to leave this information in the top level DTSI file. Let's move them out to the DTS files where they can correctly vary. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index d8ba489..9f55363 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -638,8 +638,6 @@ regulator-name = "mmci-reg"; regulator-type = "voltage"; - gpios = <&tc3589x_gpio 18 0x4>; - gpio-enable = <&tc3589x_gpio 17 0x4>; states = <1800000 0x1 2900000 0x0>; diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts index b398946..eec29c4 100644 --- a/arch/arm/boot/dts/hrefprev60.dts +++ b/arch/arm/boot/dts/hrefprev60.dts @@ -37,5 +37,12 @@ reset-gpio = <&tc3589x_gpio 13 0x4>; }; }; + + vmmci: regulator-gpio { + gpios = <&tc3589x_gpio 18 0x4>; + gpio-enable = <&tc3589x_gpio 17 0x4>; + + status = "okay"; + }; }; }; -- cgit v0.10.2 From 065871f152298b5fd385990b799cdbd7dc4121bd Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 14 Sep 2012 16:16:55 +0100 Subject: ARM: ux500: Stop registering the PCM driver from platform code We now initialise the PCM driver through the MSP DAI, so there is no need to register it though platform code anymore. This patch strips out all PCM platform registration. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c index 070629a..7adbed5 100644 --- a/arch/arm/mach-ux500/board-mop500-audio.c +++ b/arch/arm/mach-ux500/board-mop500-audio.c @@ -150,15 +150,6 @@ static struct platform_device snd_soc_mop500 = { }, }; -/* Platform device for Ux500-PCM */ -static struct platform_device ux500_pcm = { - .name = "ux500-pcm", - .id = 0, - .dev = { - .platform_data = NULL, - }, -}; - struct msp_i2s_platform_data msp2_platform_data = { .id = MSP_I2S_2, .msp_i2s_dma_rx = &msp2_dma_rx, @@ -186,10 +177,3 @@ void mop500_audio_init(struct device *parent) db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, &msp3_platform_data); } - -/* Due for removal once the MSP driver has been fully DT:ed. */ -void mop500_of_audio_init(struct device *parent) -{ - pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__); - platform_device_register(&ux500_pcm); -} diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index d772082..eaa605f 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -104,8 +104,6 @@ void __init mop500_pinmaps_init(void); void __init snowball_pinmaps_init(void); void __init hrefv60_pinmaps_init(void); void mop500_audio_init(struct device *parent); -/* Due for removal once the MSP driver has been fully DT:ed. */ -void mop500_of_audio_init(struct device *parent); int __init mop500_uib_init(void); void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, -- cgit v0.10.2 From d3fed7bd60eb4a45afe43c6e8dfc592a30e7e33f Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Mon, 26 Nov 2012 11:34:30 +0100 Subject: ARM: dts: add missing ux500 device trees This adds hrefprev60, hrefv60plus and ccu9540 to device trees compiled during build. Acked-by: Linus Walleij Acked-by: Lee Jones Signed-off-by: Fabio Baltieri diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f37cf9f..01433b9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -74,7 +74,10 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ am335x-evm.dtb \ am335x-bone.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb -dtb-$(CONFIG_ARCH_U8500) += snowball.dtb +dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \ + hrefprev60.dtb \ + hrefv60plus.dtb \ + ccu9540.dtb dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ r8a7740-armadillo800eva.dtb \ sh73a0-kzm9g.dtb -- cgit v0.10.2 From e13316d60658aee7987b51025f342649baa33487 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 22 Nov 2012 16:20:02 +0000 Subject: ARM: ux500: Rename dbx500 cpufreq code to be more generic The cpufreq driver doesn't only handle the db8500 anymore. There are new variants which rely on it too, so we've renamed the driver to be more generic. Acked-by: Linus Walleij Signed-off-by: Lee Jones diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index d2076ce..4c6ce01 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -222,7 +222,7 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500) db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); platform_device_register_data(parent, - "cpufreq-u8500", -1, NULL, 0); + "cpufreq-ux500", -1, NULL, 0); for (i = 0; i < ARRAY_SIZE(platform_devs); i++) platform_devs[i]->dev.parent = parent; @@ -244,7 +244,7 @@ static struct device * __init u8500_of_init_devices(void) db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); platform_device_register_data(parent, - "cpufreq-u8500", -1, NULL, 0); + "cpufreq-ux500", -1, NULL, 0); u8500_dma40_device.dev.parent = parent; -- cgit v0.10.2