From f571eff0a24ed97a919f2b61bb4afdeab4b43002 Mon Sep 17 00:00:00 2001 From: "Kevin D. Kissell" Date: Fri, 3 Aug 2007 19:38:03 +0200 Subject: [MIPS] IRQ Affinity Support for SMTC on Malta Platform Signed-off-by: Kevin D. Kissell Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3b807b4..b09eee2 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1378,6 +1378,19 @@ config MIPS_MT_SMTC_IM_BACKSTOP impact on interrupt service overhead. Disable it only if you know what you are doing. +config MIPS_MT_SMTC_IRQAFF + bool "Support IRQ affinity API" + depends on MIPS_MT_SMTC + default n + help + Enables SMP IRQ affinity API (/proc/irq/*/smp_affinity, etc.) + for SMTC Linux kernel. Requires platform support, of which + an example can be found in the MIPS kernel i8259 and Malta + platform code. It is recommended that MIPS_MT_SMTC_INSTANT_REPLAY + be enabled if MIPS_MT_SMTC_IRQAFF is used. Adds overhead to + interrupt dispatch, and should be used only if you know what + you are doing. + config MIPS_VPE_LOADER_TOM bool "Load VPE program into memory hidden from linux" depends on MIPS_VPE_LOADER diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index 3a2d255..4f4359b 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c @@ -39,6 +39,9 @@ static struct irq_chip i8259A_chip = { .disable = disable_8259A_irq, .unmask = enable_8259A_irq, .mask_ack = mask_and_ack_8259A, +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF + .set_affinity = plat_set_irq_affinity, +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ }; /* diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index f094043..fe22387 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -606,6 +606,60 @@ int setup_irq_smtc(unsigned int irq, struct irqaction * new, return setup_irq(irq, new); } +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF +/* + * Support for IRQ affinity to TCs + */ + +void smtc_set_irq_affinity(unsigned int irq, cpumask_t affinity) +{ + /* + * If a "fast path" cache of quickly decodable affinity state + * is maintained, this is where it gets done, on a call up + * from the platform affinity code. + */ +} + +void smtc_forward_irq(unsigned int irq) +{ + int target; + + /* + * OK wise guy, now figure out how to get the IRQ + * to be serviced on an authorized "CPU". + * + * Ideally, to handle the situation where an IRQ has multiple + * eligible CPUS, we would maintain state per IRQ that would + * allow a fair distribution of service requests. Since the + * expected use model is any-or-only-one, for simplicity + * and efficiency, we just pick the easiest one to find. + */ + + target = first_cpu(irq_desc[irq].affinity); + + /* + * We depend on the platform code to have correctly processed + * IRQ affinity change requests to ensure that the IRQ affinity + * mask has been purged of bits corresponding to nonexistent and + * offline "CPUs", and to TCs bound to VPEs other than the VPE + * connected to the physical interrupt input for the interrupt + * in question. Otherwise we have a nasty problem with interrupt + * mask management. This is best handled in non-performance-critical + * platform IRQ affinity setting code, to minimize interrupt-time + * checks. + */ + + /* If no one is eligible, service locally */ + if (target >= NR_CPUS) { + do_IRQ_no_affinity(irq); + return; + } + + smtc_send_ipi(target, IRQ_AFFINITY_IPI, irq); +} + +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ + /* * IPI model for SMTC is tricky, because interrupts aren't TC-specific. * Within a VPE one TC can interrupt another by different approaches. @@ -830,6 +884,15 @@ void ipi_decode(struct smtc_ipi *pipi) break; } break; +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF + case IRQ_AFFINITY_IPI: + /* + * Accept a "forwarded" interrupt that was initially + * taken by a TC who doesn't have affinity for the IRQ. + */ + do_IRQ_no_affinity((int)arg_copy); + break; +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ default: printk("Impossible SMTC IPI Type 0x%x\n", type_copy); break; diff --git a/arch/mips/mips-boards/malta/malta_smtc.c b/arch/mips/mips-boards/malta/malta_smtc.c index ae05d05..5c980f4 100644 --- a/arch/mips/mips-boards/malta/malta_smtc.c +++ b/arch/mips/mips-boards/malta/malta_smtc.c @@ -88,3 +88,53 @@ void __cpuinit prom_smp_finish(void) void prom_cpus_done(void) { } + +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF +/* + * IRQ affinity hook + */ + + +void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity) +{ + cpumask_t tmask = affinity; + int cpu = 0; + void smtc_set_irq_affinity(unsigned int irq, cpumask_t aff); + + /* + * On the legacy Malta development board, all I/O interrupts + * are routed through the 8259 and combined in a single signal + * to the CPU daughterboard, and on the CoreFPGA2/3 34K models, + * that signal is brought to IP2 of both VPEs. To avoid racing + * concurrent interrupt service events, IP2 is enabled only on + * one VPE, by convention VPE0. So long as no bits are ever + * cleared in the affinity mask, there will never be any + * interrupt forwarding. But as soon as a program or operator + * sets affinity for one of the related IRQs, we need to make + * sure that we don't ever try to forward across the VPE boundry, + * at least not until we engineer a system where the interrupt + * _ack() or _end() function can somehow know that it corresponds + * to an interrupt taken on another VPE, and perform the appropriate + * restoration of Status.IM state using MFTR/MTTR instead of the + * normal local behavior. We also ensure that no attempt will + * be made to forward to an offline "CPU". + */ + + for_each_cpu_mask(cpu, affinity) { + if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu)) + cpu_clear(cpu, tmask); + } + irq_desc[irq].affinity = tmask; + + if (cpus_empty(tmask)) + /* + * We could restore a default mask here, but the + * runtime code can anyway deal with the null set + */ + printk(KERN_WARNING + "IRQ affinity leaves no legal CPU for IRQ %d\n", irq); + + /* Do any generic SMTC IRQ affinity setup */ + smtc_set_irq_affinity(irq, tmask); +} +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h index 2cb52cf..a58f0ee 100644 --- a/include/asm-mips/irq.h +++ b/include/asm-mips/irq.h @@ -46,6 +46,38 @@ static inline void smtc_im_ack_irq(unsigned int irq) #endif /* CONFIG_MIPS_MT_SMTC */ +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF +#include + +extern void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity); +extern void smtc_forward_irq(unsigned int irq); + +/* + * IRQ affinity hook invoked at the beginning of interrupt dispatch + * if option is enabled. + * + * Up through Linux 2.6.22 (at least) cpumask operations are very + * inefficient on MIPS. Initial prototypes of SMTC IRQ affinity + * used a "fast path" per-IRQ-descriptor cache of affinity information + * to reduce latency. As there is a project afoot to optimize the + * cpumask implementations, this version is optimistically assuming + * that cpumask.h macro overhead is reasonable during interrupt dispatch. + */ +#define IRQ_AFFINITY_HOOK(irq) \ +do { \ + if (!cpu_isset(smp_processor_id(), irq_desc[irq].affinity)) { \ + smtc_forward_irq(irq); \ + irq_exit(); \ + return; \ + } \ +} while (0) + +#else /* Not doing SMTC affinity */ + +#define IRQ_AFFINITY_HOOK(irq) do { } while (0) + +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ + #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP /* @@ -56,13 +88,27 @@ static inline void smtc_im_ack_irq(unsigned int irq) */ #define __DO_IRQ_SMTC_HOOK(irq) \ do { \ + IRQ_AFFINITY_HOOK(irq); \ if (irq_hwmask[irq] & 0x0000ff00) \ write_c0_tccontext(read_c0_tccontext() & \ - ~(irq_hwmask[irq] & 0x0000ff00)); \ + ~(irq_hwmask[irq] & 0x0000ff00)); \ +} while (0) + +#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) \ +do { \ + if (irq_hwmask[irq] & 0x0000ff00) \ + write_c0_tccontext(read_c0_tccontext() & \ + ~(irq_hwmask[irq] & 0x0000ff00)); \ } while (0) + #else -#define __DO_IRQ_SMTC_HOOK(irq) do { } while (0) +#define __DO_IRQ_SMTC_HOOK(irq) \ +do { \ + IRQ_AFFINITY_HOOK(irq); \ +} while (0) +#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0) + #endif /* @@ -81,6 +127,23 @@ do { \ irq_exit(); \ } while (0) +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF +/* + * To avoid inefficient and in some cases pathological re-checking of + * IRQ affinity, we have this variant that skips the affinity check. + */ + + +#define do_IRQ_no_affinity(irq) \ +do { \ + irq_enter(); \ + __NO_AFFINITY_IRQ_SMTC_HOOK(irq); \ + generic_handle_irq(irq); \ + irq_exit(); \ +} while (0) + +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ + extern void arch_init_irq(void); extern void spurious_interrupt(void); diff --git a/include/asm-mips/smtc_ipi.h b/include/asm-mips/smtc_ipi.h index a52a4a7..e09131a 100644 --- a/include/asm-mips/smtc_ipi.h +++ b/include/asm-mips/smtc_ipi.h @@ -34,6 +34,7 @@ struct smtc_ipi { #define LINUX_SMP_IPI 1 #define SMTC_CLOCK_TICK 2 +#define IRQ_AFFINITY_IPI 3 /* * A queue of IPI messages -- cgit v0.10.2 From 61a33168bebb6ce5343a5f34ab421971dbfae9fa Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Tue, 7 Aug 2007 00:09:17 +0900 Subject: [MIPS] vr41xx: add cpu_wait Add cpu_wait for NEC VR41xx Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/arch/mips/vr41xx/common/pmu.c b/arch/mips/vr41xx/common/pmu.c index 5e46979..e0ffbe9 100644 --- a/arch/mips/vr41xx/common/pmu.c +++ b/arch/mips/vr41xx/common/pmu.c @@ -1,7 +1,7 @@ /* * pmu.c, Power Management Unit routines for NEC VR4100 series. * - * Copyright (C) 2003-2005 Yoichi Yuasa + * Copyright (C) 2003-2007 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,11 +22,12 @@ #include #include #include -#include +#include #include #include #include +#include #include #include @@ -44,6 +45,18 @@ static void __iomem *pmu_base; #define pmu_read(offset) readw(pmu_base + (offset)) #define pmu_write(offset, value) writew((value), pmu_base + (offset)) +static void vr41xx_cpu_wait(void) +{ + local_irq_disable(); + if (!need_resched()) + /* + * "standby" sets IE bit of the CP0_STATUS to 1. + */ + __asm__("standby;\n"); + else + local_irq_enable(); +} + static inline void software_reset(void) { uint16_t pmucnt2; @@ -113,6 +126,7 @@ static int __init vr41xx_pmu_init(void) return -EBUSY; } + cpu_wait = vr41xx_cpu_wait; _machine_restart = vr41xx_restart; _machine_halt = vr41xx_halt; pm_power_off = vr41xx_power_off; -- cgit v0.10.2 From d87d0c930a1591617e4c7c78296b4ba029150188 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:45:58 +0100 Subject: [MIPS] SMTC: Microoptimize atomic_postincrement for non-weak consistency. Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index fe22387..137183b 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -713,7 +713,7 @@ static __inline__ int atomic_postincrement(unsigned int *pv) " addu %1, %0, 1 \n" " sc %1, %2 \n" " beqz %1, 1b \n" - " sync \n" + __WEAK_LLSC_MB : "=&r" (result), "=&r" (temp), "=m" (*pv) : "m" (*pv) : "memory"); -- cgit v0.10.2 From 8c67316e706cabc2145d6c8e97f0bd8f2a86d8a1 Mon Sep 17 00:00:00 2001 From: Franck Bui-Huu Date: Thu, 15 Feb 2007 12:06:47 +0100 Subject: [MIPS] Remove '-mno-explicit-relocs' option when CONFIG_BUILD_ELF64 This patch removes '-mno-explicit-relocs' usage when CONFIG_BUILD_ELF64 is set since this option was only required with the old hack to truncate addresses at the assembly level where "-mabi=64 -Wa,-mabi=32" was used. This should yield a small code size improvement for inline assembly, where the R constraint is used. The idea is coming from Maciej . Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 32c1c8f..d5d5831 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -60,9 +60,7 @@ vmlinux-32 = vmlinux.32 vmlinux-64 = vmlinux cflags-y += -mabi=64 -ifdef CONFIG_BUILD_ELF64 -cflags-y += $(call cc-option,-mno-explicit-relocs) -else +ifndef CONFIG_BUILD_ELF64 cflags-y += $(call cc-option,-msym32) endif endif -- cgit v0.10.2 From adff90a9333004d5459823665e8bcf6cb9214f79 Mon Sep 17 00:00:00 2001 From: Franck Bui-Huu Date: Thu, 15 Feb 2007 12:06:48 +0100 Subject: [MIPS] Automatically set CONFIG_BUILD_ELF64 We do not rely on user anymore to setup this config correctly. Instead we make our choice depending on the load address. If we want to force Kbuild to use ELF64 format whatever the load address we can still do: $ make BUILD_ELF32=no Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b09eee2..492f581 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1853,21 +1853,6 @@ source "fs/Kconfig.binfmt" config TRAD_SIGNALS bool -config BUILD_ELF64 - bool "Use 64-bit ELF format for building" - depends on 64BIT - help - A 64-bit kernel is usually built using the 64-bit ELF binary object - format as it's one that allows arbitrary 64-bit constructs. For - kernels that are loaded within the KSEG compatibility segments the - 32-bit ELF format can optionally be used resulting in a somewhat - smaller binary, but this option is not explicitly supported by the - toolchain and since binutils 2.14 it does not even work at all. - - Say Y to use the 64-bit format or N to use the 32-bit one. - - If unsure say Y. - config BINFMT_IRIX bool "Include IRIX binary compatibility" depends on CPU_BIG_ENDIAN && 32BIT && BROKEN diff --git a/arch/mips/Makefile b/arch/mips/Makefile index d5d5831..4337c49 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -60,9 +60,6 @@ vmlinux-32 = vmlinux.32 vmlinux-64 = vmlinux cflags-y += -mabi=64 -ifndef CONFIG_BUILD_ELF64 -cflags-y += $(call cc-option,-msym32) -endif endif all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32) @@ -576,6 +573,26 @@ else JIFFIES = jiffies_64 endif +# +# Automatically detect the build format. By default we choose +# the elf format according to the load address. +# We can always force a build with a 64-bits symbol format by +# passing 'BUILD_ELF32=no' option to the make's command line. +# +ifdef CONFIG_64BIT + ifndef BUILD_ELF32 + ifeq ($(shell expr $(load-y) \< 0xffffffff80000000), 0) + BUILD_ELF32 = y + endif + endif + + ifeq ($(BUILD_ELF32), y) + cflags-y += -msym32 + else + cflags-y += -DCONFIG_BUILD_ELF64 + endif +endif + AFLAGS += $(cflags-y) CFLAGS += $(cflags-y) \ -D"VMLINUX_LOAD_ADDRESS=$(load-y)" diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index e3301e5..b92dd8c 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -142,7 +142,7 @@ typedef struct { unsigned long pgprot; } pgprot_t; /* * __pa()/__va() should be used only during mem init. */ -#ifdef CONFIG_64BIT +#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) #define __pa(x) \ ({ \ unsigned long __x = (unsigned long)(x); \ -- cgit v0.10.2 From 054c51b4368648406f487f54b7ed6ba75bbb3f8b Mon Sep 17 00:00:00 2001 From: Franck Bui-Huu Date: Thu, 15 Feb 2007 14:21:36 +0100 Subject: [MIPS] Rename CONFIG_BUILD_ELF64 into KBUILD_64BIT_SYM32 This patch renames it for 3 reasons: - "CONFIG" pattern is used by Kconfig. Now this macro is no more defined by Kconfig but by Kbuild itself make this clear by translating "CONFIG" into "KBUILD". - "ELF32" word is improper because it is irrelevant to ELF format and it makes confusion with CONFIG_BOOT_ELF32. So translate it with SYM32. - Add "64BIT" part to make clear that this macro implies a 64 bits kernel. Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 4337c49..ce7e02e 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -577,19 +577,17 @@ endif # Automatically detect the build format. By default we choose # the elf format according to the load address. # We can always force a build with a 64-bits symbol format by -# passing 'BUILD_ELF32=no' option to the make's command line. +# passing 'KBUILD_SYM32=no' option to the make's command line. # ifdef CONFIG_64BIT - ifndef BUILD_ELF32 + ifndef KBUILD_SYM32 ifeq ($(shell expr $(load-y) \< 0xffffffff80000000), 0) - BUILD_ELF32 = y + KBUILD_SYM32 = y endif endif - ifeq ($(BUILD_ELF32), y) - cflags-y += -msym32 - else - cflags-y += -DCONFIG_BUILD_ELF64 + ifeq ($(KBUILD_SYM32), y) + cflags-y += -msym32 -DKBUILD_64BIT_SYM32 endif endif diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index b92dd8c..c90fe56 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -142,7 +142,7 @@ typedef struct { unsigned long pgprot; } pgprot_t; /* * __pa()/__va() should be used only during mem init. */ -#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) +#ifdef KBUILD_64BIT_SYM32 #define __pa(x) \ ({ \ unsigned long __x = (unsigned long)(x); \ diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h index 49f5a1a..a8aed9c 100644 --- a/include/asm-mips/pgtable-64.h +++ b/include/asm-mips/pgtable-64.h @@ -104,7 +104,7 @@ #define VMALLOC_START MAP_BASE #define VMALLOC_END \ (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE) -#if defined(CONFIG_MODULES) && !defined(CONFIG_BUILD_ELF64) && \ +#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \ VMALLOC_START != CKSSEG /* Load modules into 32bit-compatible segment. */ #define MODULE_START CKSSEG diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index ed33366..59334f5 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h @@ -91,14 +91,14 @@ #else MFC0 k0, CP0_CONTEXT #endif -#if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4) +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) + lui k1, %hi(kernelsp) +#else lui k1, %highest(kernelsp) daddiu k1, %higher(kernelsp) dsll k1, 16 daddiu k1, %hi(kernelsp) dsll k1, 16 -#else - lui k1, %hi(kernelsp) #endif LONG_SRL k0, PTEBASE_SHIFT LONG_ADDU k1, k0 @@ -116,14 +116,14 @@ .endm #else .macro get_saved_sp /* Uniprocessor variation */ -#if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4) +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) + lui k1, %hi(kernelsp) +#else lui k1, %highest(kernelsp) daddiu k1, %higher(kernelsp) dsll k1, k1, 16 daddiu k1, %hi(kernelsp) dsll k1, k1, 16 -#else - lui k1, %hi(kernelsp) #endif LONG_L k1, %lo(kernelsp)(k1) .endm -- cgit v0.10.2 From 2f2a2d9987c4836493bfb2a80960056ef86742d2 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Thu, 16 Aug 2007 22:20:11 +0900 Subject: [MIPS] VR41xx: Add default restart routine. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/arch/mips/vr41xx/common/pmu.c b/arch/mips/vr41xx/common/pmu.c index e0ffbe9..ba0a4f6 100644 --- a/arch/mips/vr41xx/common/pmu.c +++ b/arch/mips/vr41xx/common/pmu.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include @@ -70,6 +71,11 @@ static inline void software_reset(void) pmu_write(PMUCNT2REG, pmucnt2); break; default: + set_c0_status(ST0_BEV | ST0_ERL); + change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); + flush_cache_all(); + write_c0_wired(0); + __asm__("jr %0"::"r"(0xbfc00000)); break; } } @@ -78,7 +84,6 @@ static void vr41xx_restart(char *command) { local_irq_disable(); software_reset(); - printk(KERN_NOTICE "\nYou can reset your system\n"); while (1) ; } -- cgit v0.10.2 From fa41780606e7a5999a9096269c0ad8e7cee2b95b Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Thu, 16 Aug 2007 22:27:05 +0900 Subject: [MIPS] VR41xx: replace infinite loop with hibernate Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/arch/mips/vr41xx/common/pmu.c b/arch/mips/vr41xx/common/pmu.c index ba0a4f6..ad5b6db 100644 --- a/arch/mips/vr41xx/common/pmu.c +++ b/arch/mips/vr41xx/common/pmu.c @@ -91,14 +91,7 @@ static void vr41xx_halt(void) { local_irq_disable(); printk(KERN_NOTICE "\nYou can turn off the power supply\n"); - while (1) ; -} - -static void vr41xx_power_off(void) -{ - local_irq_disable(); - printk(KERN_NOTICE "\nYou can turn off the power supply\n"); - while (1) ; + __asm__("hibernate;\n"); } static int __init vr41xx_pmu_init(void) @@ -134,7 +127,7 @@ static int __init vr41xx_pmu_init(void) cpu_wait = vr41xx_cpu_wait; _machine_restart = vr41xx_restart; _machine_halt = vr41xx_halt; - pm_power_off = vr41xx_power_off; + pm_power_off = vr41xx_halt; return 0; } -- cgit v0.10.2 From ddcf4efb7a5a38c2d82decbdfd99c43bbf226551 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Thu, 16 Aug 2007 22:54:02 +0900 Subject: [MIPS] IP27: remove duplicate extern dump_tlb_all() prototype Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/arch/mips/sgi-ip27/ip27-berr.c b/arch/mips/sgi-ip27/ip27-berr.c index 123141a..7d05e68 100644 --- a/arch/mips/sgi-ip27/ip27-berr.c +++ b/arch/mips/sgi-ip27/ip27-berr.c @@ -21,8 +21,6 @@ #include #include -extern void dump_tlb_all(void); - static void dump_hub_information(unsigned long errst0, unsigned long errst1) { static char *err_type[2][8] = { -- cgit v0.10.2 From 4c6d0fc2f6ce44161f3fac3b34d262c0dd06cf0c Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Thu, 16 Aug 2007 22:56:04 +0900 Subject: [MIPS] remove unused include/asm-mips/ip32/machine.h Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/include/asm-mips/ip32/machine.h b/include/asm-mips/ip32/machine.h deleted file mode 100644 index 1b631b8..0000000 --- a/include/asm-mips/ip32/machine.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * machine.h -- Machine/group probing for ip32 - * - * Copyright (C) 2001 Keith M Wesolowski - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ -#ifndef _ASM_IP32_MACHINE_H -#define _ASM_IP32_MACHINE_H - - -#ifdef CONFIG_SGI_IP32 - -#define SGI_MACH_O2 0x3201 - -#endif /* CONFIG_SGI_IP32 */ - -#endif /* _ASM_SGI_MACHINE_H */ -- cgit v0.10.2 From 0caf583398309398ec05fc76bff15c711e9f936d Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Thu, 16 Aug 2007 23:15:42 +0900 Subject: [MIPS] fix ABI check in include/asm-mips/arv/hinv.h Fix ABI check in include/asm-mips/arv/hinv.h Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/include/asm-mips/arc/hinv.h b/include/asm-mips/arc/hinv.h index ee792bf..1862912 100644 --- a/include/asm-mips/arc/hinv.h +++ b/include/asm-mips/arc/hinv.h @@ -4,6 +4,7 @@ #ifndef _ASM_ARC_HINV_H #define _ASM_ARC_HINV_H +#include #include /* configuration query defines */ @@ -110,7 +111,7 @@ union key_u { ULONG FullKey; }; -#if _MIPS_SIM == _ABI64 +#if _MIPS_SIM == _MIPS_SIM_ABI64 #define SGI_ARCS_VERS 64 /* sgi 64-bit version */ #define SGI_ARCS_REV 0 /* rev .00 */ #else -- cgit v0.10.2 From 1f21d2bde0046e959b53756f74d96dfd040a803b Mon Sep 17 00:00:00 2001 From: Brian Murphy Date: Tue, 21 Aug 2007 22:34:16 +0200 Subject: [MIPS] Add back support for LASAT platforms Signed-off-by: Brian Murphy Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 492f581..bb3fb40 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -107,6 +107,20 @@ config MACH_JAZZ Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and Olivetti M700-10 workstations. +config LASAT + bool "LASAT Networks platforms" + select DMA_NONCOHERENT + select SYS_HAS_EARLY_PRINTK + select HW_HAS_PCI + select PCI_GT64XXX_PCI0 + select MIPS_NILE4 + select R5000_CPU_SCACHE + select SYS_HAS_CPU_R5000 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if BROKEN + select SYS_SUPPORTS_LITTLE_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ + config LEMOTE_FULONG bool "Lemote Fulong mini-PC" select ARCH_SPARSEMEM_ENABLE @@ -599,6 +613,7 @@ endchoice source "arch/mips/au1000/Kconfig" source "arch/mips/jazz/Kconfig" +source "arch/mips/lasat/Kconfig" source "arch/mips/pmc-sierra/Kconfig" source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" @@ -706,6 +721,9 @@ config MIPS_BONITO64 config MIPS_MSC bool +config MIPS_NILE4 + bool + config MIPS_DISABLE_OBSOLETE_IDE bool diff --git a/arch/mips/Makefile b/arch/mips/Makefile index ce7e02e..6dcdbfb 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -362,6 +362,13 @@ cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite load-$(CONFIG_BASLER_EXCITE) += 0x80100000 # +# LASAT platforms +# +core-$(CONFIG_LASAT) += arch/mips/lasat/ +cflags-$(CONFIG_LASAT) += -Iinclude/asm-mips/mach-lasat +load-$(CONFIG_LASAT) += 0xffffffff80000000 + +# # Common VR41xx # core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/ @@ -628,6 +635,11 @@ core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/ drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ +ifdef CONFIG_LASAT +rom.bin rom.sw: vmlinux + $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@ +endif + # # Some machines like the Indy need 32-bit ELF binaries for booting purposes. # Other need ECOFF, so we build a 32-bit ELF binary for them which we then @@ -671,6 +683,7 @@ endif archclean: @$(MAKE) $(clean)=arch/mips/boot + @$(MAKE) $(clean)=arch/mips/lasat define archhelp echo ' vmlinux.ecoff - ECOFF boot image' diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig new file mode 100644 index 0000000..2c665fcef --- /dev/null +++ b/arch/mips/configs/lasat_defconfig @@ -0,0 +1,828 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.23-rc3 +# Sat Aug 18 17:37:58 2007 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +CONFIG_LASAT=y +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_WR_PPMC is not set +CONFIG_PICVUE=y +CONFIG_PICVUE_PROC=y +CONFIG_DS1603=y +CONFIG_LASAT_SYSCTL=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +# CONFIG_HOTPLUG_CPU is not set +CONFIG_MIPS_NILE4=y +# CONFIG_NO_IOPORT is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_PCI_GT64XXX_PCI0=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +CONFIG_CPU_R5000=y +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_R5000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_BOARD_SCACHE=y +CONFIG_R5000_CPU_SCACHE=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +# CONFIG_SECCOMP is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_KALLSYMS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_LASAT=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_IDE=y +CONFIG_IDE_MAX_HWIFS=4 +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=y +CONFIG_IDEDISK_MULTI_MODE=y +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=y +CONFIG_BLK_DEV_IDEPCI=y +# CONFIG_IDEPCI_SHARE_IRQ is not set +CONFIG_IDEPCI_PCIBUS_ORDER=y +# CONFIG_BLK_DEV_OFFBOARD is not set +CONFIG_BLK_DEV_GENERIC=y +# CONFIG_BLK_DEV_OPTI621 is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_IDEDMA_FORCED is not set +# CONFIG_IDEDMA_ONLYDISK is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +CONFIG_BLK_DEV_CMD64X=y +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT34X is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT8213 is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_TC86C001 is not set +# CONFIG_IDE_ARM is not set +CONFIG_BLK_DEV_IDEDMA=y +# CONFIG_IDEDMA_IVB is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_DM9000 is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +CONFIG_PCNET32=y +# CONFIG_PCNET32_NAPI is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_TC35815 is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set + +# +# Sound +# +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_INFINIBAND is not set +# CONFIG_RTC_CLASS is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# Userspace I/O +# +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +CONFIG_CONFIGFS_FS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/mips/lasat/Kconfig b/arch/mips/lasat/Kconfig new file mode 100644 index 0000000..1d2ee8a --- /dev/null +++ b/arch/mips/lasat/Kconfig @@ -0,0 +1,15 @@ +config PICVUE + tristate "PICVUE LCD display driver" + depends on LASAT + +config PICVUE_PROC + tristate "PICVUE LCD display driver /proc interface" + depends on PICVUE + +config DS1603 + bool "DS1603 RTC driver" + depends on LASAT + +config LASAT_SYSCTL + bool "LASAT sysctl interface" + depends on LASAT diff --git a/arch/mips/lasat/Makefile b/arch/mips/lasat/Makefile new file mode 100644 index 0000000..3379160 --- /dev/null +++ b/arch/mips/lasat/Makefile @@ -0,0 +1,16 @@ +# +# Makefile for the LASAT specific kernel interface routines under Linux. +# + +obj-y += reset.o setup.o prom.o lasat_board.o \ + at93c.o interrupt.o serial.o + +obj-$(CONFIG_LASAT_SYSCTL) += sysctl.o +obj-$(CONFIG_DS1603) += ds1603.o +obj-$(CONFIG_PICVUE) += picvue.o +obj-$(CONFIG_PICVUE_PROC) += picvue_proc.o + +clean: + make -C image clean + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/lasat/at93c.c b/arch/mips/lasat/at93c.c new file mode 100644 index 0000000..793e234 --- /dev/null +++ b/arch/mips/lasat/at93c.c @@ -0,0 +1,149 @@ +/* + * Atmel AT93C46 serial eeprom driver + * + * Brian Murphy + * + */ +#include +#include +#include +#include +#include + +#include "at93c.h" + +#define AT93C_ADDR_SHIFT 7 +#define AT93C_ADDR_MAX ((1 << AT93C_ADDR_SHIFT) - 1) +#define AT93C_RCMD (0x6 << AT93C_ADDR_SHIFT) +#define AT93C_WCMD (0x5 << AT93C_ADDR_SHIFT) +#define AT93C_WENCMD 0x260 +#define AT93C_WDSCMD 0x200 + +struct at93c_defs *at93c; + +static void at93c_reg_write(u32 val) +{ + *at93c->reg = val; +} + +static u32 at93c_reg_read(void) +{ + u32 tmp = *at93c->reg; + return tmp; +} + +static u32 at93c_datareg_read(void) +{ + u32 tmp = *at93c->rdata_reg; + return tmp; +} + +static void at93c_cycle_clk(u32 data) +{ + at93c_reg_write(data | at93c->clk); + lasat_ndelay(250); + at93c_reg_write(data & ~at93c->clk); + lasat_ndelay(250); +} + +static void at93c_write_databit(u8 bit) +{ + u32 data = at93c_reg_read(); + if (bit) + data |= 1 << at93c->wdata_shift; + else + data &= ~(1 << at93c->wdata_shift); + + at93c_reg_write(data); + lasat_ndelay(100); + at93c_cycle_clk(data); +} + +static unsigned int at93c_read_databit(void) +{ + u32 data; + + at93c_cycle_clk(at93c_reg_read()); + data = (at93c_datareg_read() >> at93c->rdata_shift) & 1; + return data; +} + +static u8 at93c_read_byte(void) +{ + int i; + u8 data = 0; + + for (i = 0; i <= 7; i++) { + data <<= 1; + data |= at93c_read_databit(); + } + return data; +} + +static void at93c_write_bits(u32 data, int size) +{ + int i; + int shift = size - 1; + u32 mask = (1 << shift); + + for (i = 0; i < size; i++) { + at93c_write_databit((data & mask) >> shift); + data <<= 1; + } +} + +static void at93c_init_op(void) +{ + at93c_reg_write((at93c_reg_read() | at93c->cs) & + ~at93c->clk & ~(1 << at93c->rdata_shift)); + lasat_ndelay(50); +} + +static void at93c_end_op(void) +{ + at93c_reg_write(at93c_reg_read() & ~at93c->cs); + lasat_ndelay(250); +} + +static void at93c_wait(void) +{ + at93c_init_op(); + while (!at93c_read_databit()) + ; + at93c_end_op(); +}; + +static void at93c_disable_wp(void) +{ + at93c_init_op(); + at93c_write_bits(AT93C_WENCMD, 10); + at93c_end_op(); +} + +static void at93c_enable_wp(void) +{ + at93c_init_op(); + at93c_write_bits(AT93C_WDSCMD, 10); + at93c_end_op(); +} + +u8 at93c_read(u8 addr) +{ + u8 byte; + at93c_init_op(); + at93c_write_bits((addr & AT93C_ADDR_MAX)|AT93C_RCMD, 10); + byte = at93c_read_byte(); + at93c_end_op(); + return byte; +} + +void at93c_write(u8 addr, u8 data) +{ + at93c_disable_wp(); + at93c_init_op(); + at93c_write_bits((addr & AT93C_ADDR_MAX)|AT93C_WCMD, 10); + at93c_write_bits(data, 8); + at93c_end_op(); + at93c_wait(); + at93c_enable_wp(); +} diff --git a/arch/mips/lasat/at93c.h b/arch/mips/lasat/at93c.h new file mode 100644 index 0000000..cfe2f99 --- /dev/null +++ b/arch/mips/lasat/at93c.h @@ -0,0 +1,18 @@ +/* + * Atmel AT93C46 serial eeprom driver + * + * Brian Murphy + * + */ + +extern struct at93c_defs { + volatile u32 *reg; + volatile u32 *rdata_reg; + int rdata_shift; + int wdata_shift; + u32 cs; + u32 clk; +} *at93c; + +u8 at93c_read(u8 addr); +void at93c_write(u8 addr, u8 data); diff --git a/arch/mips/lasat/ds1603.c b/arch/mips/lasat/ds1603.c new file mode 100644 index 0000000..0b315f5 --- /dev/null +++ b/arch/mips/lasat/ds1603.c @@ -0,0 +1,183 @@ +/* + * Dallas Semiconductors 1603 RTC driver + * + * Brian Murphy + * + */ +#include +#include +#include +#include +#include + +#include "ds1603.h" + +#define READ_TIME_CMD 0x81 +#define SET_TIME_CMD 0x80 +#define TRIMMER_SET_CMD 0xC0 +#define TRIMMER_VALUE_MASK 0x38 +#define TRIMMER_SHIFT 3 + +struct ds_defs *ds1603; + +/* HW specific register functions */ +static void rtc_reg_write(unsigned long val) +{ + *ds1603->reg = val; +} + +static unsigned long rtc_reg_read(void) +{ + unsigned long tmp = *ds1603->reg; + return tmp; +} + +static unsigned long rtc_datareg_read(void) +{ + unsigned long tmp = *ds1603->data_reg; + return tmp; +} + +static void rtc_nrst_high(void) +{ + rtc_reg_write(rtc_reg_read() | ds1603->rst); +} + +static void rtc_nrst_low(void) +{ + rtc_reg_write(rtc_reg_read() & ~ds1603->rst); +} + +static void rtc_cycle_clock(unsigned long data) +{ + data |= ds1603->clk; + rtc_reg_write(data); + lasat_ndelay(250); + if (ds1603->data_reversed) + data &= ~ds1603->data; + else + data |= ds1603->data; + data &= ~ds1603->clk; + rtc_reg_write(data); + lasat_ndelay(250 + ds1603->huge_delay); +} + +static void rtc_write_databit(unsigned int bit) +{ + unsigned long data = rtc_reg_read(); + if (ds1603->data_reversed) + bit = !bit; + if (bit) + data |= ds1603->data; + else + data &= ~ds1603->data; + + rtc_reg_write(data); + lasat_ndelay(50 + ds1603->huge_delay); + rtc_cycle_clock(data); +} + +static unsigned int rtc_read_databit(void) +{ + unsigned int data; + + data = (rtc_datareg_read() & (1 << ds1603->data_read_shift)) + >> ds1603->data_read_shift; + rtc_cycle_clock(rtc_reg_read()); + return data; +} + +static void rtc_write_byte(unsigned int byte) +{ + int i; + + for (i = 0; i <= 7; i++) { + rtc_write_databit(byte & 1L); + byte >>= 1; + } +} + +static void rtc_write_word(unsigned long word) +{ + int i; + + for (i = 0; i <= 31; i++) { + rtc_write_databit(word & 1L); + word >>= 1; + } +} + +static unsigned long rtc_read_word(void) +{ + int i; + unsigned long word = 0; + unsigned long shift = 0; + + for (i = 0; i <= 31; i++) { + word |= rtc_read_databit() << shift; + shift++; + } + return word; +} + +static void rtc_init_op(void) +{ + rtc_nrst_high(); + + rtc_reg_write(rtc_reg_read() & ~ds1603->clk); + + lasat_ndelay(50); +} + +static void rtc_end_op(void) +{ + rtc_nrst_low(); + lasat_ndelay(1000); +} + +/* interface */ +unsigned long ds1603_read(void) +{ + unsigned long word; + unsigned long flags; + + spin_lock_irqsave(&rtc_lock, flags); + rtc_init_op(); + rtc_write_byte(READ_TIME_CMD); + word = rtc_read_word(); + rtc_end_op(); + spin_unlock_irqrestore(&rtc_lock, flags); + return word; +} + +int ds1603_set(unsigned long time) +{ + unsigned long flags; + + spin_lock_irqsave(&rtc_lock, flags); + rtc_init_op(); + rtc_write_byte(SET_TIME_CMD); + rtc_write_word(time); + rtc_end_op(); + spin_unlock_irqrestore(&rtc_lock, flags); + + return 0; +} + +void ds1603_set_trimmer(unsigned int trimval) +{ + rtc_init_op(); + rtc_write_byte(((trimval << TRIMMER_SHIFT) & TRIMMER_VALUE_MASK) + | (TRIMMER_SET_CMD)); + rtc_end_op(); +} + +void ds1603_disable(void) +{ + ds1603_set_trimmer(TRIMMER_DISABLE_RTC); +} + +void ds1603_enable(void) +{ + ds1603_set_trimmer(TRIMMER_DEFAULT); +} diff --git a/arch/mips/lasat/ds1603.h b/arch/mips/lasat/ds1603.h new file mode 100644 index 0000000..c2e5c76 --- /dev/null +++ b/arch/mips/lasat/ds1603.h @@ -0,0 +1,33 @@ +/* + * Dallas Semiconductors 1603 RTC driver + * + * Brian Murphy + * + */ +#ifndef __DS1603_H +#define __DS1603_H + +struct ds_defs { + volatile u32 *reg; + volatile u32 *data_reg; + u32 rst; + u32 clk; + u32 data; + u32 data_read_shift; + char data_reversed; + u32 huge_delay; +}; + +extern struct ds_defs *ds1603; + +unsigned long ds1603_read(void); +int ds1603_set(unsigned long); +void ds1603_set_trimmer(unsigned int); +void ds1603_enable(void); +void ds1603_disable(void); +void ds1603_init(struct ds_defs *); + +#define TRIMMER_DEFAULT 3 +#define TRIMMER_DISABLE_RTC 0 + +#endif diff --git a/arch/mips/lasat/image/Makefile b/arch/mips/lasat/image/Makefile new file mode 100644 index 0000000..5332449 --- /dev/null +++ b/arch/mips/lasat/image/Makefile @@ -0,0 +1,54 @@ +# +# MAKEFILE FOR THE MIPS LINUX BOOTLOADER AND ROM DEBUGGER +# +# i-data Networks +# +# Author: Thomas Horsten +# + +ifndef Version + Version = "$(USER)-test" +endif + +MKLASATIMG = mklasatimg +MKLASATIMG_ARCH = mq2,mqpro,sp100,sp200 +KERNEL_IMAGE = $(TOPDIR)/vmlinux +KERNEL_START = $(shell $(NM) $(KERNEL_IMAGE) | grep " _text" | cut -f1 -d\ ) +KERNEL_ENTRY = $(shell $(NM) $(KERNEL_IMAGE) | grep kernel_entry | cut -f1 -d\ ) + +LDSCRIPT= -L$(obj) -Tromscript.normal + +HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \ + -D_kernel_entry=0x$(KERNEL_ENTRY) \ + -D VERSION="\"$(Version)\"" \ + -D TIMESTAMP=$(shell date +%s) + +$(obj)/head.o: $(obj)/head.S $(KERNEL_IMAGE) + $(CC) -fno-pic $(HEAD_DEFINES) -I$(TOPDIR)/include -c -o $@ $< + +OBJECTS = head.o kImage.o + +rom.sw: $(obj)/rom.sw +rom.bin: $(obj)/rom.bin + +$(obj)/rom.sw: $(obj)/rom.bin + $(MKLASATIMG) -o $@ -k $^ -m $(MKLASATIMG_ARCH) + +$(obj)/rom.bin: $(obj)/rom + $(OBJCOPY) -O binary -S $^ $@ + +# Rule to make the bootloader +$(obj)/rom: $(addprefix $(obj)/,$(OBJECTS)) + $(LD) $(LDFLAGS) $(LDSCRIPT) -o $@ $^ + +$(obj)/%.o: $(obj)/%.gz + $(LD) -r -o $@ -b binary $< + +$(obj)/%.gz: $(obj)/%.bin + gzip -cf -9 $< > $@ + +$(obj)/kImage.bin: $(KERNEL_IMAGE) + $(OBJCOPY) -O binary -S $^ $@ + +clean: + rm -f rom rom.bin rom.sw kImage.bin kImage.o diff --git a/arch/mips/lasat/image/head.S b/arch/mips/lasat/image/head.S new file mode 100644 index 0000000..efb95f2 --- /dev/null +++ b/arch/mips/lasat/image/head.S @@ -0,0 +1,31 @@ +#include + + .text + .section .text.start, "ax" + .set noreorder + .set mips3 + + /* Magic words identifying a software image */ + .word LASAT_K_MAGIC0_VAL + .word LASAT_K_MAGIC1_VAL + + /* Image header version */ + .word 0x00000002 + + /* image start and size */ + .word _image_start + .word _image_size + + /* start of kernel and entrypoint in uncompressed image */ + .word _kernel_start + .word _kernel_entry + + /* Here we have room for future flags */ + + .org 0x40 +reldate: + .word TIMESTAMP + + .org 0x50 +release: + .string VERSION diff --git a/arch/mips/lasat/image/romscript.normal b/arch/mips/lasat/image/romscript.normal new file mode 100644 index 0000000..988f8ad --- /dev/null +++ b/arch/mips/lasat/image/romscript.normal @@ -0,0 +1,23 @@ +OUTPUT_ARCH(mips) + +SECTIONS +{ + .text : + { + *(.text.start) + } + + /* Data in ROM */ + + .data ALIGN(0x10) : + { + *(.data) + } + _image_start = ADDR(.data); + _image_size = SIZEOF(.data); + + .other : + { + *(.*) + } +} diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c new file mode 100644 index 0000000..5f35289 --- /dev/null +++ b/arch/mips/lasat/interrupt.c @@ -0,0 +1,130 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Routines for generic manipulation of the interrupts found on the + * Lasat boards. + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static volatile int *lasat_int_status; +static volatile int *lasat_int_mask; +static volatile int lasat_int_mask_shift; + +void disable_lasat_irq(unsigned int irq_nr) +{ + *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift; +} + +void enable_lasat_irq(unsigned int irq_nr) +{ + *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift; +} + +static struct irq_chip lasat_irq_type = { + .name = "Lasat", + .ack = disable_lasat_irq, + .mask = disable_lasat_irq, + .mask_ack = disable_lasat_irq, + .unmask = enable_lasat_irq, +}; + +static inline int ls1bit32(unsigned int x) +{ + int b = 31, s; + + s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s; + s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s; + s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s; + s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s; + s = 1; if (x << 1 == 0) s = 0; b -= s; + + return b; +} + +static unsigned long (*get_int_status)(void); + +static unsigned long get_int_status_100(void) +{ + return *lasat_int_status & *lasat_int_mask; +} + +static unsigned long get_int_status_200(void) +{ + unsigned long int_status; + + int_status = *lasat_int_status; + int_status &= (int_status >> LASATINT_MASK_SHIFT_200) & 0xffff; + return int_status; +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned long int_status; + unsigned int cause = read_c0_cause(); + int irq; + + if (cause & CAUSEF_IP7) { /* R4000 count / compare IRQ */ + ll_timer_interrupt(7); + return; + } + + int_status = get_int_status(); + + /* if int_status == 0, then the interrupt has already been cleared */ + if (int_status) { + irq = ls1bit32(int_status); + + do_IRQ(irq); + } +} + +void __init arch_init_irq(void) +{ + int i; + + switch (mips_machtype) { + case MACH_LASAT_100: + lasat_int_status = (void *)LASAT_INT_STATUS_REG_100; + lasat_int_mask = (void *)LASAT_INT_MASK_REG_100; + lasat_int_mask_shift = LASATINT_MASK_SHIFT_100; + get_int_status = get_int_status_100; + *lasat_int_mask = 0; + break; + case MACH_LASAT_200: + lasat_int_status = (void *)LASAT_INT_STATUS_REG_200; + lasat_int_mask = (void *)LASAT_INT_MASK_REG_200; + lasat_int_mask_shift = LASATINT_MASK_SHIFT_200; + get_int_status = get_int_status_200; + *lasat_int_mask &= 0xffff; + break; + default: + panic("arch_init_irq: mips_machtype incorrect"); + } + + for (i = 0; i <= LASATINT_END; i++) + set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq); +} diff --git a/arch/mips/lasat/lasat_board.c b/arch/mips/lasat/lasat_board.c new file mode 100644 index 0000000..ec2f658 --- /dev/null +++ b/arch/mips/lasat/lasat_board.c @@ -0,0 +1,280 @@ +/* + * Thomas Horsten + * Copyright (C) 2000 LASAT Networks A/S. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Routines specific to the LASAT boards + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "at93c.h" +/* New model description table */ +#include "lasat_models.h" + +#define EEPROM_CRC(data, len) (~crc32(~0, data, len)) + +struct lasat_info lasat_board_info; + +void update_bcastaddr(void); + +int EEPROMRead(unsigned int pos, unsigned char *data, int len) +{ + int i; + + for (i = 0; i < len; i++) + *data++ = at93c_read(pos++); + + return 0; +} + +int EEPROMWrite(unsigned int pos, unsigned char *data, int len) +{ + int i; + + for (i = 0; i < len; i++) + at93c_write(pos++, *data++); + + return 0; +} + +static void init_flash_sizes(void) +{ + unsigned long *lb = lasat_board_info.li_flashpart_base; + unsigned long *ls = lasat_board_info.li_flashpart_size; + int i; + + ls[LASAT_MTD_BOOTLOADER] = 0x40000; + ls[LASAT_MTD_SERVICE] = 0xC0000; + ls[LASAT_MTD_NORMAL] = 0x100000; + + if (mips_machtype == MACH_LASAT_100) { + lasat_board_info.li_flash_base = 0x1e000000; + + lb[LASAT_MTD_BOOTLOADER] = 0x1e400000; + + if (lasat_board_info.li_flash_size > 0x200000) { + ls[LASAT_MTD_CONFIG] = 0x100000; + ls[LASAT_MTD_FS] = 0x500000; + } + } else { + lasat_board_info.li_flash_base = 0x10000000; + + if (lasat_board_info.li_flash_size < 0x1000000) { + lb[LASAT_MTD_BOOTLOADER] = 0x10000000; + ls[LASAT_MTD_CONFIG] = 0x100000; + if (lasat_board_info.li_flash_size >= 0x400000) + ls[LASAT_MTD_FS] = + lasat_board_info.li_flash_size - 0x300000; + } + } + + for (i = 1; i < LASAT_MTD_LAST; i++) + lb[i] = lb[i-1] + ls[i-1]; +} + +int lasat_init_board_info(void) +{ + int c; + unsigned long crc; + unsigned long cfg0, cfg1; + const struct product_info *ppi; + int i_n_base_models = N_BASE_MODELS; + const char * const * i_txt_base_models = txt_base_models; + int i_n_prids = N_PRIDS; + + memset(&lasat_board_info, 0, sizeof(lasat_board_info)); + + /* First read the EEPROM info */ + EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info, + sizeof(struct lasat_eeprom_struct)); + + /* Check the CRC */ + crc = EEPROM_CRC((unsigned char *)(&lasat_board_info.li_eeprom_info), + sizeof(struct lasat_eeprom_struct) - 4); + + if (crc != lasat_board_info.li_eeprom_info.crc32) { + printk(KERN_WARNING "WARNING...\nWARNING...\nEEPROM CRC does " + "not match calculated, attempting to soldier on...\n"); + } + + if (lasat_board_info.li_eeprom_info.version != LASAT_EEPROM_VERSION) { + printk(KERN_WARNING "WARNING...\nWARNING...\nEEPROM version " + "%d, wanted version %d, attempting to soldier on...\n", + (unsigned int)lasat_board_info.li_eeprom_info.version, + LASAT_EEPROM_VERSION); + } + + cfg0 = lasat_board_info.li_eeprom_info.cfg[0]; + cfg1 = lasat_board_info.li_eeprom_info.cfg[1]; + + if (LASAT_W0_DSCTYPE(cfg0) != 1) { + printk(KERN_WARNING "WARNING...\nWARNING...\n" + "Invalid configuration read from EEPROM, attempting to " + "soldier on..."); + } + /* We have a valid configuration */ + + switch (LASAT_W0_SDRAMBANKSZ(cfg0)) { + case 0: + lasat_board_info.li_memsize = 0x0800000; + break; + case 1: + lasat_board_info.li_memsize = 0x1000000; + break; + case 2: + lasat_board_info.li_memsize = 0x2000000; + break; + case 3: + lasat_board_info.li_memsize = 0x4000000; + break; + case 4: + lasat_board_info.li_memsize = 0x8000000; + break; + default: + lasat_board_info.li_memsize = 0; + } + + switch (LASAT_W0_SDRAMBANKS(cfg0)) { + case 0: + break; + case 1: + lasat_board_info.li_memsize *= 2; + break; + default: + break; + } + + switch (LASAT_W0_BUSSPEED(cfg0)) { + case 0x0: + lasat_board_info.li_bus_hz = 60000000; + break; + case 0x1: + lasat_board_info.li_bus_hz = 66000000; + break; + case 0x2: + lasat_board_info.li_bus_hz = 66666667; + break; + case 0x3: + lasat_board_info.li_bus_hz = 80000000; + break; + case 0x4: + lasat_board_info.li_bus_hz = 83333333; + break; + case 0x5: + lasat_board_info.li_bus_hz = 100000000; + break; + } + + switch (LASAT_W0_CPUCLK(cfg0)) { + case 0x0: + lasat_board_info.li_cpu_hz = + lasat_board_info.li_bus_hz; + break; + case 0x1: + lasat_board_info.li_cpu_hz = + lasat_board_info.li_bus_hz + + (lasat_board_info.li_bus_hz >> 1); + break; + case 0x2: + lasat_board_info.li_cpu_hz = + lasat_board_info.li_bus_hz + + lasat_board_info.li_bus_hz; + break; + case 0x3: + lasat_board_info.li_cpu_hz = + lasat_board_info.li_bus_hz + + lasat_board_info.li_bus_hz + + (lasat_board_info.li_bus_hz >> 1); + break; + case 0x4: + lasat_board_info.li_cpu_hz = + lasat_board_info.li_bus_hz + + lasat_board_info.li_bus_hz + + lasat_board_info.li_bus_hz; + break; + } + + /* Flash size */ + switch (LASAT_W1_FLASHSIZE(cfg1)) { + case 0: + lasat_board_info.li_flash_size = 0x200000; + break; + case 1: + lasat_board_info.li_flash_size = 0x400000; + break; + case 2: + lasat_board_info.li_flash_size = 0x800000; + break; + case 3: + lasat_board_info.li_flash_size = 0x1000000; + break; + case 4: + lasat_board_info.li_flash_size = 0x2000000; + break; + } + + init_flash_sizes(); + + lasat_board_info.li_bmid = LASAT_W0_BMID(cfg0); + lasat_board_info.li_prid = lasat_board_info.li_eeprom_info.prid; + if (lasat_board_info.li_prid == 0xffff || lasat_board_info.li_prid == 0) + lasat_board_info.li_prid = lasat_board_info.li_bmid; + + /* Base model stuff */ + if (lasat_board_info.li_bmid > i_n_base_models) + lasat_board_info.li_bmid = i_n_base_models; + strcpy(lasat_board_info.li_bmstr, + i_txt_base_models[lasat_board_info.li_bmid]); + + /* Product ID dependent values */ + c = lasat_board_info.li_prid; + if (c >= i_n_prids) { + strcpy(lasat_board_info.li_namestr, "Unknown Model"); + strcpy(lasat_board_info.li_typestr, "Unknown Type"); + } else { + ppi = &vendor_info_table[0].vi_product_info[c]; + strcpy(lasat_board_info.li_namestr, ppi->pi_name); + if (ppi->pi_type) + strcpy(lasat_board_info.li_typestr, ppi->pi_type); + else + sprintf(lasat_board_info.li_typestr, "%d", 10 * c); + } + +#if defined(CONFIG_INET) && defined(CONFIG_SYSCTL) + update_bcastaddr(); +#endif + + return 0; +} + +void lasat_write_eeprom_info(void) +{ + unsigned long crc; + + /* Generate the CRC */ + crc = EEPROM_CRC((unsigned char *)(&lasat_board_info.li_eeprom_info), + sizeof(struct lasat_eeprom_struct) - 4); + lasat_board_info.li_eeprom_info.crc32 = crc; + + /* Write the EEPROM info */ + EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info, + sizeof(struct lasat_eeprom_struct)); +} diff --git a/arch/mips/lasat/lasat_models.h b/arch/mips/lasat/lasat_models.h new file mode 100644 index 0000000..e1cbd26 --- /dev/null +++ b/arch/mips/lasat/lasat_models.h @@ -0,0 +1,67 @@ +/* + * Model description tables + */ +#include + +struct product_info { + const char *pi_name; + const char *pi_type; +}; + +struct vendor_info { + const char *vi_name; + const struct product_info *vi_product_info; +}; + +/* + * Base models + */ +static const char * const txt_base_models[] = { + "MQ 2", "MQ Pro", "SP 25", "SP 50", "SP 100", "SP 5000", "SP 7000", + "SP 1000", "Unknown" +}; +#define N_BASE_MODELS (ARRAY_SIZE(txt_base_models) - 1) + +/* + * Eicon Networks + */ +static const char txt_en_mq[] = "Masquerade"; +static const char txt_en_sp[] = "Safepipe"; + +static const struct product_info product_info_eicon[] = { + { txt_en_mq, "II" }, /* 0 */ + { txt_en_mq, "Pro" }, /* 1 */ + { txt_en_sp, "25" }, /* 2 */ + { txt_en_sp, "50" }, /* 3 */ + { txt_en_sp, "100" }, /* 4 */ + { txt_en_sp, "5000" }, /* 5 */ + { txt_en_sp, "7000" }, /* 6 */ + { txt_en_sp, "30" }, /* 7 */ + { txt_en_sp, "5100" }, /* 8 */ + { txt_en_sp, "7100" }, /* 9 */ + { txt_en_sp, "1110" }, /* 10 */ + { txt_en_sp, "3020" }, /* 11 */ + { txt_en_sp, "3030" }, /* 12 */ + { txt_en_sp, "5020" }, /* 13 */ + { txt_en_sp, "5030" }, /* 14 */ + { txt_en_sp, "1120" }, /* 15 */ + { txt_en_sp, "1130" }, /* 16 */ + { txt_en_sp, "6010" }, /* 17 */ + { txt_en_sp, "6110" }, /* 18 */ + { txt_en_sp, "6210" }, /* 19 */ + { txt_en_sp, "1020" }, /* 20 */ + { txt_en_sp, "1040" }, /* 21 */ + { txt_en_sp, "1050" }, /* 22 */ + { txt_en_sp, "1060" }, /* 23 */ +}; + +#define N_PRIDS ARRAY_SIZE(product_info_eicon) + +/* + * The vendor table + */ +static struct vendor_info const vendor_info_table[] = { + { "Eicon Networks", product_info_eicon }, +}; + +#define N_VENDORS ARRAY_SIZE(vendor_info_table) diff --git a/arch/mips/lasat/picvue.c b/arch/mips/lasat/picvue.c new file mode 100644 index 0000000..6471d06 --- /dev/null +++ b/arch/mips/lasat/picvue.c @@ -0,0 +1,244 @@ +/* + * Picvue PVC160206 display driver + * + * Brian Murphy + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "picvue.h" + +#define PVC_BUSY 0x80 +#define PVC_NLINES 2 +#define PVC_DISPMEM 80 +#define PVC_LINELEN PVC_DISPMEM / PVC_NLINES + +struct pvc_defs *picvue; + +DECLARE_MUTEX(pvc_sem); + +static void pvc_reg_write(u32 val) +{ + *picvue->reg = val; +} + +static u32 pvc_reg_read(void) +{ + u32 tmp = *picvue->reg; + return tmp; +} + +static void pvc_write_byte(u32 data, u8 byte) +{ + data |= picvue->e; + pvc_reg_write(data); + data &= ~picvue->data_mask; + data |= byte << picvue->data_shift; + pvc_reg_write(data); + ndelay(220); + pvc_reg_write(data & ~picvue->e); + ndelay(220); +} + +static u8 pvc_read_byte(u32 data) +{ + u8 byte; + + data |= picvue->e; + pvc_reg_write(data); + ndelay(220); + byte = (pvc_reg_read() & picvue->data_mask) >> picvue->data_shift; + data &= ~picvue->e; + pvc_reg_write(data); + ndelay(220); + return byte; +} + +static u8 pvc_read_data(void) +{ + u32 data = pvc_reg_read(); + u8 byte; + data |= picvue->rw; + data &= ~picvue->rs; + pvc_reg_write(data); + ndelay(40); + byte = pvc_read_byte(data); + data |= picvue->rs; + pvc_reg_write(data); + return byte; +} + +#define TIMEOUT 1000 +static int pvc_wait(void) +{ + int i = TIMEOUT; + int err = 0; + + while ((pvc_read_data() & PVC_BUSY) && i) + i--; + if (i == 0) + err = -ETIME; + + return err; +} + +#define MODE_INST 0 +#define MODE_DATA 1 +static void pvc_write(u8 byte, int mode) +{ + u32 data = pvc_reg_read(); + data &= ~picvue->rw; + if (mode == MODE_DATA) + data |= picvue->rs; + else + data &= ~picvue->rs; + pvc_reg_write(data); + ndelay(40); + pvc_write_byte(data, byte); + if (mode == MODE_DATA) + data &= ~picvue->rs; + else + data |= picvue->rs; + pvc_reg_write(data); + pvc_wait(); +} + +void pvc_write_string(const unsigned char *str, u8 addr, int line) +{ + int i = 0; + + if (line > 0 && (PVC_NLINES > 1)) + addr += 0x40 * line; + pvc_write(0x80 | addr, MODE_INST); + + while (*str != 0 && i < PVC_LINELEN) { + pvc_write(*str++, MODE_DATA); + i++; + } +} + +void pvc_write_string_centered(const unsigned char *str, int line) +{ + int len = strlen(str); + u8 addr; + + if (len > PVC_VISIBLE_CHARS) + addr = 0; + else + addr = (PVC_VISIBLE_CHARS - strlen(str))/2; + + pvc_write_string(str, addr, line); +} + +void pvc_dump_string(const unsigned char *str) +{ + int len = strlen(str); + + pvc_write_string(str, 0, 0); + if (len > PVC_VISIBLE_CHARS) + pvc_write_string(&str[PVC_VISIBLE_CHARS], 0, 1); +} + +#define BM_SIZE 8 +#define MAX_PROGRAMMABLE_CHARS 8 +int pvc_program_cg(int charnum, u8 bitmap[BM_SIZE]) +{ + int i; + int addr; + + if (charnum > MAX_PROGRAMMABLE_CHARS) + return -ENOENT; + + addr = charnum * 8; + pvc_write(0x40 | addr, MODE_INST); + + for (i = 0; i < BM_SIZE; i++) + pvc_write(bitmap[i], MODE_DATA); + return 0; +} + +#define FUNC_SET_CMD 0x20 +#define EIGHT_BYTE (1 << 4) +#define FOUR_BYTE 0 +#define TWO_LINES (1 << 3) +#define ONE_LINE 0 +#define LARGE_FONT (1 << 2) +#define SMALL_FONT 0 + +static void pvc_funcset(u8 cmd) +{ + pvc_write(FUNC_SET_CMD | (cmd & (EIGHT_BYTE|TWO_LINES|LARGE_FONT)), + MODE_INST); +} + +#define ENTRYMODE_CMD 0x4 +#define AUTO_INC (1 << 1) +#define AUTO_DEC 0 +#define CURSOR_FOLLOWS_DISP (1 << 0) + +static void pvc_entrymode(u8 cmd) +{ + pvc_write(ENTRYMODE_CMD | (cmd & (AUTO_INC|CURSOR_FOLLOWS_DISP)), + MODE_INST); +} + +#define DISP_CNT_CMD 0x08 +#define DISP_OFF 0 +#define DISP_ON (1 << 2) +#define CUR_ON (1 << 1) +#define CUR_BLINK (1 << 0) +void pvc_dispcnt(u8 cmd) +{ + pvc_write(DISP_CNT_CMD | (cmd & (DISP_ON|CUR_ON|CUR_BLINK)), MODE_INST); +} + +#define MOVE_CMD 0x10 +#define DISPLAY (1 << 3) +#define CURSOR 0 +#define RIGHT (1 << 2) +#define LEFT 0 +void pvc_move(u8 cmd) +{ + pvc_write(MOVE_CMD | (cmd & (DISPLAY|RIGHT)), MODE_INST); +} + +#define CLEAR_CMD 0x1 +void pvc_clear(void) +{ + pvc_write(CLEAR_CMD, MODE_INST); +} + +#define HOME_CMD 0x2 +void pvc_home(void) +{ + pvc_write(HOME_CMD, MODE_INST); +} + +int pvc_init(void) +{ + u8 cmd = EIGHT_BYTE; + + if (PVC_NLINES == 2) + cmd |= (SMALL_FONT|TWO_LINES); + else + cmd |= (LARGE_FONT|ONE_LINE); + pvc_funcset(cmd); + pvc_dispcnt(DISP_ON); + pvc_entrymode(AUTO_INC); + + pvc_clear(); + pvc_write_string_centered("Display", 0); + pvc_write_string_centered("Initialized", 1); + + return 0; +} + +module_init(pvc_init); +MODULE_LICENSE("GPL"); diff --git a/arch/mips/lasat/picvue.h b/arch/mips/lasat/picvue.h new file mode 100644 index 0000000..2a96bf9 --- /dev/null +++ b/arch/mips/lasat/picvue.h @@ -0,0 +1,48 @@ +/* + * Picvue PVC160206 display driver + * + * Brian Murphy + * + */ +#include + +struct pvc_defs { + volatile u32 *reg; + u32 data_shift; + u32 data_mask; + u32 e; + u32 rw; + u32 rs; +}; + +extern struct pvc_defs *picvue; + +#define PVC_NLINES 2 +#define PVC_DISPMEM 80 +#define PVC_LINELEN PVC_DISPMEM / PVC_NLINES +#define PVC_VISIBLE_CHARS 16 + +void pvc_write_string(const unsigned char *str, u8 addr, int line); +void pvc_write_string_centered(const unsigned char *str, int line); +void pvc_dump_string(const unsigned char *str); + +#define BM_SIZE 8 +#define MAX_PROGRAMMABLE_CHARS 8 +int pvc_program_cg(int charnum, u8 bitmap[BM_SIZE]); + +void pvc_dispcnt(u8 cmd); +#define DISP_OFF 0 +#define DISP_ON (1 << 2) +#define CUR_ON (1 << 1) +#define CUR_BLINK (1 << 0) + +void pvc_move(u8 cmd); +#define DISPLAY (1 << 3) +#define CURSOR 0 +#define RIGHT (1 << 2) +#define LEFT 0 + +void pvc_clear(void); +void pvc_home(void); + +extern struct semaphore pvc_sem; diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c new file mode 100644 index 0000000..9947c15 --- /dev/null +++ b/arch/mips/lasat/picvue_proc.c @@ -0,0 +1,191 @@ +/* + * Picvue PVC160206 display driver + * + * Brian Murphy + * + */ +#include +#include +#include +#include + +#include +#include + +#include + +#include "picvue.h" + +static char pvc_lines[PVC_NLINES][PVC_LINELEN+1]; +static int pvc_linedata[PVC_NLINES]; +static struct proc_dir_entry *pvc_display_dir; +static char *pvc_linename[PVC_NLINES] = {"line1", "line2"}; +#define DISPLAY_DIR_NAME "display" +static int scroll_dir, scroll_interval; + +static struct timer_list timer; + +static void pvc_display(unsigned long data) +{ + int i; + + pvc_clear(); + for (i = 0; i < PVC_NLINES; i++) + pvc_write_string(pvc_lines[i], 0, i); +} + +static DECLARE_TASKLET(pvc_display_tasklet, &pvc_display, 0); + +static int pvc_proc_read_line(char *page, char **start, + off_t off, int count, + int *eof, void *data) +{ + char *origpage = page; + int lineno = *(int *)data; + + if (lineno < 0 || lineno > PVC_NLINES) { + printk(KERN_WARNING "proc_read_line: invalid lineno %d\n", lineno); + return 0; + } + + down(&pvc_sem); + page += sprintf(page, "%s\n", pvc_lines[lineno]); + up(&pvc_sem); + + return page - origpage; +} + +static int pvc_proc_write_line(struct file *file, const char *buffer, + unsigned long count, void *data) +{ + int origcount = count; + int lineno = *(int *)data; + + if (lineno < 0 || lineno > PVC_NLINES) { + printk(KERN_WARNING "proc_write_line: invalid lineno %d\n", + lineno); + return origcount; + } + + if (count > PVC_LINELEN) + count = PVC_LINELEN; + + if (buffer[count-1] == '\n') + count--; + + down(&pvc_sem); + strncpy(pvc_lines[lineno], buffer, count); + pvc_lines[lineno][count] = '\0'; + up(&pvc_sem); + + tasklet_schedule(&pvc_display_tasklet); + + return origcount; +} + +static int pvc_proc_write_scroll(struct file *file, const char *buffer, + unsigned long count, void *data) +{ + int origcount = count; + int cmd = simple_strtol(buffer, NULL, 10); + + down(&pvc_sem); + if (scroll_interval != 0) + del_timer(&timer); + + if (cmd == 0) { + scroll_dir = 0; + scroll_interval = 0; + } else { + if (cmd < 0) { + scroll_dir = -1; + scroll_interval = -cmd; + } else { + scroll_dir = 1; + scroll_interval = cmd; + } + add_timer(&timer); + } + up(&pvc_sem); + + return origcount; +} + +static int pvc_proc_read_scroll(char *page, char **start, + off_t off, int count, + int *eof, void *data) +{ + char *origpage = page; + + down(&pvc_sem); + page += sprintf(page, "%d\n", scroll_dir * scroll_interval); + up(&pvc_sem); + + return page - origpage; +} + + +void pvc_proc_timerfunc(unsigned long data) +{ + if (scroll_dir < 0) + pvc_move(DISPLAY|RIGHT); + else if (scroll_dir > 0) + pvc_move(DISPLAY|LEFT); + + timer.expires = jiffies + scroll_interval; + add_timer(&timer); +} + +static void pvc_proc_cleanup(void) +{ + int i; + for (i = 0; i < PVC_NLINES; i++) + remove_proc_entry(pvc_linename[i], pvc_display_dir); + remove_proc_entry("scroll", pvc_display_dir); + remove_proc_entry(DISPLAY_DIR_NAME, NULL); + + del_timer(&timer); +} + +static int __init pvc_proc_init(void) +{ + struct proc_dir_entry *proc_entry; + int i; + + pvc_display_dir = proc_mkdir(DISPLAY_DIR_NAME, NULL); + if (pvc_display_dir == NULL) + goto error; + + for (i = 0; i < PVC_NLINES; i++) { + strcpy(pvc_lines[i], ""); + pvc_linedata[i] = i; + } + for (i = 0; i < PVC_NLINES; i++) { + proc_entry = create_proc_entry(pvc_linename[i], 0644, + pvc_display_dir); + if (proc_entry == NULL) + goto error; + + proc_entry->read_proc = pvc_proc_read_line; + proc_entry->write_proc = pvc_proc_write_line; + proc_entry->data = &pvc_linedata[i]; + } + proc_entry = create_proc_entry("scroll", 0644, pvc_display_dir); + if (proc_entry == NULL) + goto error; + + proc_entry->write_proc = pvc_proc_write_scroll; + proc_entry->read_proc = pvc_proc_read_scroll; + + init_timer(&timer); + timer.function = pvc_proc_timerfunc; + + return 0; +error: + pvc_proc_cleanup(); + return -ENOMEM; +} + +module_init(pvc_proc_init); +module_exit(pvc_proc_cleanup); +MODULE_LICENSE("GPL"); diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c new file mode 100644 index 0000000..4b80fff --- /dev/null +++ b/arch/mips/lasat/prom.c @@ -0,0 +1,128 @@ +/* + * PROM interface routines. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "at93c.h" +#include +#include "prom.h" + +#define RESET_VECTOR 0xbfc00000 +#define PROM_JUMP_TABLE_ENTRY(n) (*((u32 *)(RESET_VECTOR + 0x20) + n)) +#define PROM_DISPLAY_ADDR PROM_JUMP_TABLE_ENTRY(0) +#define PROM_PUTC_ADDR PROM_JUMP_TABLE_ENTRY(1) +#define PROM_MONITOR_ADDR PROM_JUMP_TABLE_ENTRY(2) + +static void null_prom_display(const char *string, int pos, int clear) +{ +} + +static void null_prom_monitor(void) +{ +} + +static void null_prom_putc(char c) +{ +} + +/* these are functions provided by the bootloader */ +static void (*__prom_putc)(char c) = null_prom_putc; + +void prom_putchar(char c) +{ + __prom_putc(c); +} + +void (*prom_display)(const char *string, int pos, int clear) = + null_prom_display; +void (*prom_monitor)(void) = null_prom_monitor; + +unsigned int lasat_ndelay_divider; + +static void setup_prom_vectors(void) +{ + u32 version = *(u32 *)(RESET_VECTOR + 0x90); + + if (version >= 307) { + prom_display = (void *)PROM_DISPLAY_ADDR; + __prom_putc = (void *)PROM_PUTC_ADDR; + prom_monitor = (void *)PROM_MONITOR_ADDR; + } + printk(KERN_DEBUG "prom vectors set up\n"); +} + +static struct at93c_defs at93c_defs[N_MACHTYPES] = { + { + .reg = (void *)AT93C_REG_100, + .rdata_reg = (void *)AT93C_RDATA_REG_100, + .rdata_shift = AT93C_RDATA_SHIFT_100, + .wdata_shift = AT93C_WDATA_SHIFT_100, + .cs = AT93C_CS_M_100, + .clk = AT93C_CLK_M_100 + }, { + .reg = (void *)AT93C_REG_200, + .rdata_reg = (void *)AT93C_RDATA_REG_200, + .rdata_shift = AT93C_RDATA_SHIFT_200, + .wdata_shift = AT93C_WDATA_SHIFT_200, + .cs = AT93C_CS_M_200, + .clk = AT93C_CLK_M_200 + }, +}; + +void __init prom_init(void) +{ + int argc = fw_arg0; + char **argv = (char **) fw_arg1; + + setup_prom_vectors(); + + if (current_cpu_data.cputype == CPU_R5000) { + printk(KERN_INFO "LASAT 200 board\n"); + mips_machtype = MACH_LASAT_200; + lasat_ndelay_divider = LASAT_200_DIVIDER; + } else { + printk(KERN_INFO "LASAT 100 board\n"); + mips_machtype = MACH_LASAT_100; + lasat_ndelay_divider = LASAT_100_DIVIDER; + } + + at93c = &at93c_defs[mips_machtype]; + + lasat_init_board_info(); /* Read info from EEPROM */ + + mips_machgroup = MACH_GROUP_LASAT; + + /* Get the command line */ + if (argc > 0) { + strncpy(arcs_cmdline, argv[0], CL_SIZE-1); + arcs_cmdline[CL_SIZE-1] = '\0'; + } + + /* Set the I/O base address */ + set_io_port_base(KSEG1); + + /* Set memory regions */ + ioport_resource.start = 0; + ioport_resource.end = 0xffffffff; /* Wrong, fixme. */ + + add_memory_region(0, lasat_board_info.li_memsize, BOOT_MEM_RAM); +} + +void __init prom_free_prom_memory(void) +{ +} + +const char *get_system_type(void) +{ + return lasat_board_info.li_bmstr; +} diff --git a/arch/mips/lasat/prom.h b/arch/mips/lasat/prom.h new file mode 100644 index 0000000..337acbc --- /dev/null +++ b/arch/mips/lasat/prom.h @@ -0,0 +1,7 @@ +#ifndef __PROM_H +#define __PROM_H + +extern void (*prom_display)(const char *string, int pos, int clear); +extern void (*prom_monitor)(void); + +#endif /* __PROM_H */ diff --git a/arch/mips/lasat/reset.c b/arch/mips/lasat/reset.c new file mode 100644 index 0000000..b1e7a89 --- /dev/null +++ b/arch/mips/lasat/reset.c @@ -0,0 +1,61 @@ +/* + * Thomas Horsten + * Copyright (C) 2000 LASAT Networks A/S. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Reset the LASAT board. + */ +#include +#include + +#include +#include +#include + +#include "picvue.h" +#include "prom.h" + +static void lasat_machine_restart(char *command); +static void lasat_machine_halt(void); + +/* Used to set machine to boot in service mode via /proc interface */ +int lasat_boot_to_service; + +static void lasat_machine_restart(char *command) +{ + local_irq_disable(); + + if (lasat_boot_to_service) { + *(volatile unsigned int *)0xa0000024 = 0xdeadbeef; + *(volatile unsigned int *)0xa00000fc = 0xfedeabba; + } + *lasat_misc->reset_reg = 0xbedead; + for (;;) ; +} + +static void lasat_machine_halt(void) +{ + local_irq_disable(); + + prom_monitor(); + for (;;) ; +} + +void lasat_reboot_setup(void) +{ + _machine_restart = lasat_machine_restart; + _machine_halt = lasat_machine_halt; + pm_power_off = lasat_machine_halt; +} diff --git a/arch/mips/lasat/serial.c b/arch/mips/lasat/serial.c new file mode 100644 index 0000000..205bd39 --- /dev/null +++ b/arch/mips/lasat/serial.c @@ -0,0 +1,94 @@ +/* + * Registration of Lasat UART platform device. + * + * Copyright (C) 2007 Brian Murphy + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include + +#include +#include +#include + +static struct resource lasat_serial_res[2] __initdata; + +static struct plat_serial8250_port lasat_serial8250_port[] = { + { + .iotype = UPIO_MEM, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | + UPF_SKIP_TEST, + }, + {}, +}; + +static __init int lasat_uart_add(void) +{ + struct platform_device *pdev; + int retval; + + pdev = platform_device_alloc("serial8250", -1); + if (!pdev) + return -ENOMEM; + + if (mips_machtype == MACH_LASAT_100) { + lasat_serial_res[0].start = KSEG1ADDR(LASAT_UART_REGS_BASE_100); + lasat_serial_res[0].end = lasat_serial_res[0].start + LASAT_UART_REGS_SHIFT_100 * 8 - 1; + lasat_serial_res[0].flags = IORESOURCE_MEM; + lasat_serial_res[1].start = LASATINT_UART_100; + lasat_serial_res[1].end = LASATINT_UART_100; + lasat_serial_res[1].flags = IORESOURCE_IRQ; + + lasat_serial8250_port[0].mapbase = LASAT_UART_REGS_BASE_100; + lasat_serial8250_port[0].uartclk = LASAT_BASE_BAUD_100 * 16; + lasat_serial8250_port[0].regshift = LASAT_UART_REGS_SHIFT_100; + lasat_serial8250_port[0].irq = LASATINT_UART_100; + } else { + lasat_serial_res[0].start = KSEG1ADDR(LASAT_UART_REGS_BASE_200); + lasat_serial_res[0].end = lasat_serial_res[0].start + LASAT_UART_REGS_SHIFT_200 * 8 - 1; + lasat_serial_res[0].flags = IORESOURCE_MEM; + lasat_serial_res[1].start = LASATINT_UART_200; + lasat_serial_res[1].end = LASATINT_UART_200; + lasat_serial_res[1].flags = IORESOURCE_IRQ; + + lasat_serial8250_port[0].mapbase = LASAT_UART_REGS_BASE_200; + lasat_serial8250_port[0].uartclk = LASAT_BASE_BAUD_200 * 16; + lasat_serial8250_port[0].regshift = LASAT_UART_REGS_SHIFT_200; + lasat_serial8250_port[0].irq = LASATINT_UART_200; + } + + pdev->id = PLAT8250_DEV_PLATFORM; + pdev->dev.platform_data = lasat_serial8250_port; + + retval = platform_device_add_resources(pdev, lasat_serial_res, ARRAY_SIZE(lasat_serial_res)); + if (retval) + goto err_free_device; + + retval = platform_device_add(pdev); + if (retval) + goto err_free_device; + + return 0; + +err_free_device: + platform_device_put(pdev); + + return retval; +} +device_initcall(lasat_uart_add); diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c new file mode 100644 index 0000000..187e378 --- /dev/null +++ b/arch/mips/lasat/setup.c @@ -0,0 +1,158 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. + * + * Thomas Horsten + * Copyright (C) 2000 LASAT Networks A/S. + * + * Brian Murphy + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Lasat specific setup. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_PICVUE +#include +#endif + +#include "ds1603.h" +#include +#include +#include + +#include "prom.h" + +int lasat_command_line; +void lasatint_init(void); + +extern void lasat_reboot_setup(void); +extern void pcisetup(void); +extern void edhac_init(void *, void *, void *); +extern void addrflt_init(void); + +struct lasat_misc lasat_misc_info[N_MACHTYPES] = { + { + .reset_reg = (void *)KSEG1ADDR(0x1c840000), + .flash_wp_reg = (void *)KSEG1ADDR(0x1c800000), 2 + }, { + .reset_reg = (void *)KSEG1ADDR(0x11080000), + .flash_wp_reg = (void *)KSEG1ADDR(0x11000000), 6 + } +}; + +struct lasat_misc *lasat_misc; + +#ifdef CONFIG_DS1603 +static struct ds_defs ds_defs[N_MACHTYPES] = { + { (void *)DS1603_REG_100, (void *)DS1603_REG_100, + DS1603_RST_100, DS1603_CLK_100, DS1603_DATA_100, + DS1603_DATA_SHIFT_100, 0, 0 }, + { (void *)DS1603_REG_200, (void *)DS1603_DATA_REG_200, + DS1603_RST_200, DS1603_CLK_200, DS1603_DATA_200, + DS1603_DATA_READ_SHIFT_200, 1, 2000 } +}; +#endif + +#ifdef CONFIG_PICVUE +#include "picvue.h" +static struct pvc_defs pvc_defs[N_MACHTYPES] = { + { (void *)PVC_REG_100, PVC_DATA_SHIFT_100, PVC_DATA_M_100, + PVC_E_100, PVC_RW_100, PVC_RS_100 }, + { (void *)PVC_REG_200, PVC_DATA_SHIFT_200, PVC_DATA_M_200, + PVC_E_200, PVC_RW_200, PVC_RS_200 } +}; +#endif + +static int lasat_panic_display(struct notifier_block *this, + unsigned long event, void *ptr) +{ +#ifdef CONFIG_PICVUE + unsigned char *string = ptr; + if (string == NULL) + string = "Kernel Panic"; + pvc_dump_string(string); +#endif + return NOTIFY_DONE; +} + +static int lasat_panic_prom_monitor(struct notifier_block *this, + unsigned long event, void *ptr) +{ + prom_monitor(); + return NOTIFY_DONE; +} + +static struct notifier_block lasat_panic_block[] = +{ + { + .notifier_call = lasat_panic_display, + .priority = INT_MAX + }, { + .notifier_call = lasat_panic_prom_monitor, + .priority = INT_MIN + } +}; + +static void lasat_time_init(void) +{ + mips_hpt_frequency = lasat_board_info.li_cpu_hz / 2; +} + +void __init plat_timer_setup(struct irqaction *irq) +{ + change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5); +} + +void __init plat_mem_setup(void) +{ + int i; + lasat_misc = &lasat_misc_info[mips_machtype]; +#ifdef CONFIG_PICVUE + picvue = &pvc_defs[mips_machtype]; +#endif + + /* Set up panic notifier */ + for (i = 0; i < ARRAY_SIZE(lasat_panic_block); i++) + atomic_notifier_chain_register(&panic_notifier_list, + &lasat_panic_block[i]); + + lasat_reboot_setup(); + + board_time_init = lasat_time_init; + +#ifdef CONFIG_DS1603 + ds1603 = &ds_defs[mips_machtype]; + rtc_mips_get_time = ds1603_read; + rtc_mips_set_time = ds1603_set; +#endif + +#ifdef DYNAMIC_SERIAL_INIT + serial_init(); +#endif + + pr_info("Lasat specific initialization complete\n"); +} diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c new file mode 100644 index 0000000..4575a82 --- /dev/null +++ b/arch/mips/lasat/sysctl.c @@ -0,0 +1,454 @@ +/* + * Thomas Horsten + * Copyright (C) 2000 LASAT Networks A/S. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Routines specific to the LASAT boards + */ +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sysctl.h" +#include "ds1603.h" + +static DEFINE_MUTEX(lasat_info_mutex); + +/* Strategy function to write EEPROM after changing string entry */ +int sysctl_lasatstring(ctl_table *table, int *name, int nlen, + void *oldval, size_t *oldlenp, + void *newval, size_t newlen) +{ + int r; + + mutex_lock(&lasat_info_mutex); + r = sysctl_string(table, name, + nlen, oldval, oldlenp, newval, newlen); + if (r < 0) { + mutex_unlock(&lasat_info_mutex); + return r; + } + if (newval && newlen) + lasat_write_eeprom_info(); + mutex_unlock(&lasat_info_mutex); + + return 1; +} + + +/* And the same for proc */ +int proc_dolasatstring(ctl_table *table, int write, struct file *filp, + void *buffer, size_t *lenp, loff_t *ppos) +{ + int r; + + mutex_lock(&lasat_info_mutex); + r = proc_dostring(table, write, filp, buffer, lenp, ppos); + if ((!write) || r) { + mutex_unlock(&lasat_info_mutex); + return r; + } + lasat_write_eeprom_info(); + mutex_unlock(&lasat_info_mutex); + + return 0; +} + +/* proc function to write EEPROM after changing int entry */ +int proc_dolasatint(ctl_table *table, int write, struct file *filp, + void *buffer, size_t *lenp, loff_t *ppos) +{ + int r; + + mutex_lock(&lasat_info_mutex); + r = proc_dointvec(table, write, filp, buffer, lenp, ppos); + if ((!write) || r) { + mutex_unlock(&lasat_info_mutex); + return r; + } + lasat_write_eeprom_info(); + mutex_unlock(&lasat_info_mutex); + + return 0; +} + +static int rtctmp; + +#ifdef CONFIG_DS1603 +/* proc function to read/write RealTime Clock */ +int proc_dolasatrtc(ctl_table *table, int write, struct file *filp, + void *buffer, size_t *lenp, loff_t *ppos) +{ + int r; + + mutex_lock(&lasat_info_mutex); + if (!write) { + rtctmp = ds1603_read(); + /* check for time < 0 and set to 0 */ + if (rtctmp < 0) + rtctmp = 0; + } + r = proc_dointvec(table, write, filp, buffer, lenp, ppos); + if ((!write) || r) { + mutex_unlock(&lasat_info_mutex); + return r; + } + ds1603_set(rtctmp); + mutex_unlock(&lasat_info_mutex); + + return 0; +} +#endif + +/* Sysctl for setting the IP addresses */ +int sysctl_lasat_intvec(ctl_table *table, int *name, int nlen, + void *oldval, size_t *oldlenp, + void *newval, size_t newlen) +{ + int r; + + mutex_lock(&lasat_info_mutex); + r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen); + if (r < 0) { + mutex_unlock(&lasat_info_mutex); + return r; + } + if (newval && newlen) + lasat_write_eeprom_info(); + mutex_unlock(&lasat_info_mutex); + + return 1; +} + +#ifdef CONFIG_DS1603 +/* Same for RTC */ +int sysctl_lasat_rtc(ctl_table *table, int *name, int nlen, + void *oldval, size_t *oldlenp, + void *newval, size_t newlen) +{ + int r; + + mutex_lock(&lasat_info_mutex); + rtctmp = ds1603_read(); + if (rtctmp < 0) + rtctmp = 0; + r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen); + if (r < 0) { + mutex_unlock(&lasat_info_mutex); + return r; + } + if (newval && newlen) + ds1603_set(rtctmp); + mutex_unlock(&lasat_info_mutex); + + return 1; +} +#endif + +#ifdef CONFIG_INET +static char lasat_bcastaddr[16]; + +void update_bcastaddr(void) +{ + unsigned int ip; + + ip = (lasat_board_info.li_eeprom_info.ipaddr & + lasat_board_info.li_eeprom_info.netmask) | + ~lasat_board_info.li_eeprom_info.netmask; + + sprintf(lasat_bcastaddr, "%d.%d.%d.%d", + (ip) & 0xff, + (ip >> 8) & 0xff, + (ip >> 16) & 0xff, + (ip >> 24) & 0xff); +} + +static char proc_lasat_ipbuf[32]; + +/* Parsing of IP address */ +int proc_lasat_ip(ctl_table *table, int write, struct file *filp, + void *buffer, size_t *lenp, loff_t *ppos) +{ + unsigned int ip; + char *p, c; + int len; + + if (!table->data || !table->maxlen || !*lenp || + (*ppos && !write)) { + *lenp = 0; + return 0; + } + + mutex_lock(&lasat_info_mutex); + if (write) { + len = 0; + p = buffer; + while (len < *lenp) { + if (get_user(c, p++)) { + mutex_unlock(&lasat_info_mutex); + return -EFAULT; + } + if (c == 0 || c == '\n') + break; + len++; + } + if (len >= sizeof(proc_lasat_ipbuf)-1) + len = sizeof(proc_lasat_ipbuf) - 1; + if (copy_from_user(proc_lasat_ipbuf, buffer, len)) { + mutex_unlock(&lasat_info_mutex); + return -EFAULT; + } + proc_lasat_ipbuf[len] = 0; + *ppos += *lenp; + /* Now see if we can convert it to a valid IP */ + ip = in_aton(proc_lasat_ipbuf); + *(unsigned int *)(table->data) = ip; + lasat_write_eeprom_info(); + } else { + ip = *(unsigned int *)(table->data); + sprintf(proc_lasat_ipbuf, "%d.%d.%d.%d", + (ip) & 0xff, + (ip >> 8) & 0xff, + (ip >> 16) & 0xff, + (ip >> 24) & 0xff); + len = strlen(proc_lasat_ipbuf); + if (len > *lenp) + len = *lenp; + if (len) + if (copy_to_user(buffer, proc_lasat_ipbuf, len)) { + mutex_unlock(&lasat_info_mutex); + return -EFAULT; + } + if (len < *lenp) { + if (put_user('\n', ((char *) buffer) + len)) { + mutex_unlock(&lasat_info_mutex); + return -EFAULT; + } + len++; + } + *lenp = len; + *ppos += len; + } + update_bcastaddr(); + mutex_unlock(&lasat_info_mutex); + + return 0; +} +#endif /* defined(CONFIG_INET) */ + +static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen, + void *oldval, size_t *oldlenp, + void *newval, size_t newlen) +{ + int r; + + mutex_lock(&lasat_info_mutex); + r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen); + if (r < 0) { + mutex_unlock(&lasat_info_mutex); + return r; + } + + if (newval && newlen) { + if (name && *name == LASAT_PRID) + lasat_board_info.li_eeprom_info.prid = *(int *)newval; + + lasat_write_eeprom_info(); + lasat_init_board_info(); + } + mutex_unlock(&lasat_info_mutex); + + return 0; +} + +int proc_lasat_eeprom_value(ctl_table *table, int write, struct file *filp, + void *buffer, size_t *lenp, loff_t *ppos) +{ + int r; + + mutex_lock(&lasat_info_mutex); + r = proc_dointvec(table, write, filp, buffer, lenp, ppos); + if ((!write) || r) { + mutex_unlock(&lasat_info_mutex); + return r; + } + if (filp && filp->f_path.dentry) { + if (!strcmp(filp->f_path.dentry->d_name.name, "prid")) + lasat_board_info.li_eeprom_info.prid = + lasat_board_info.li_prid; + if (!strcmp(filp->f_path.dentry->d_name.name, "debugaccess")) + lasat_board_info.li_eeprom_info.debugaccess = + lasat_board_info.li_debugaccess; + } + lasat_write_eeprom_info(); + mutex_unlock(&lasat_info_mutex); + + return 0; +} + +extern int lasat_boot_to_service; + +#ifdef CONFIG_SYSCTL + +static ctl_table lasat_table[] = { + { + .ctl_name = CTL_UNNUMBERED, + .procname = "cpu-hz", + .data = &lasat_board_info.li_cpu_hz, + .maxlen = sizeof(int), + .mode = 0444, + .proc_handler = &proc_dointvec, + .strategy = &sysctl_intvec + }, + { + .ctl_name = CTL_UNNUMBERED, + .procname = "bus-hz", + .data = &lasat_board_info.li_bus_hz, + .maxlen = sizeof(int), + .mode = 0444, + .proc_handler = &proc_dointvec, + .strategy = &sysctl_intvec + }, + { + .ctl_name = CTL_UNNUMBERED, + .procname = "bmid", + .data = &lasat_board_info.li_bmid, + .maxlen = sizeof(int), + .mode = 0444, + .proc_handler = &proc_dointvec, + .strategy = &sysctl_intvec + }, + { + .ctl_name = CTL_UNNUMBERED, + .procname = "prid", + .data = &lasat_board_info.li_prid, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &proc_lasat_eeprom_value, + .strategy = &sysctl_lasat_eeprom_value + }, +#ifdef CONFIG_INET + { + .ctl_name = CTL_UNNUMBERED, + .procname = "ipaddr", + .data = &lasat_board_info.li_eeprom_info.ipaddr, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &proc_lasat_ip, + .strategy = &sysctl_lasat_intvec + }, + { + .ctl_name = LASAT_NETMASK, + .procname = "netmask", + .data = &lasat_board_info.li_eeprom_info.netmask, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &proc_lasat_ip, + .strategy = &sysctl_lasat_intvec + }, + { + .ctl_name = CTL_UNNUMBERED, + .procname = "bcastaddr", + .data = &lasat_bcastaddr, + .maxlen = sizeof(lasat_bcastaddr), + .mode = 0600, + .proc_handler = &proc_dostring, + .strategy = &sysctl_string + }, +#endif + { + .ctl_name = CTL_UNNUMBERED, + .procname = "passwd_hash", + .data = &lasat_board_info.li_eeprom_info.passwd_hash, + .maxlen = + sizeof(lasat_board_info.li_eeprom_info.passwd_hash), + .mode = 0600, + .proc_handler = &proc_dolasatstring, + .strategy = &sysctl_lasatstring + }, + { + .ctl_name = CTL_UNNUMBERED, + .procname = "boot-service", + .data = &lasat_boot_to_service, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &proc_dointvec, + .strategy = &sysctl_intvec + }, +#ifdef CONFIG_DS1603 + { + .ctl_name = CTL_UNNUMBERED, + .procname = "rtc", + .data = &rtctmp, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &proc_dolasatrtc, + .strategy = &sysctl_lasat_rtc + }, +#endif + { + .ctl_name = CTL_UNNUMBERED, + .procname = "namestr", + .data = &lasat_board_info.li_namestr, + .maxlen = sizeof(lasat_board_info.li_namestr), + .mode = 0444, + .proc_handler = &proc_dostring, + .strategy = &sysctl_string + }, + { + .ctl_name = CTL_UNNUMBERED, + .procname = "typestr", + .data = &lasat_board_info.li_typestr, + .maxlen = sizeof(lasat_board_info.li_typestr), + .mode = 0444, + .proc_handler = &proc_dostring, + .strategy = &sysctl_string + }, + {} +}; + +static ctl_table lasat_root_table[] = { + { + .ctl_name = CTL_UNNUMBERED, + .procname = "lasat", + .mode = 0555, + .child = lasat_table + }, + {} +}; + +static int __init lasat_register_sysctl(void) +{ + struct ctl_table_header *lasat_table_header; + + lasat_table_header = + register_sysctl_table(lasat_root_table); + + return 0; +} + +__initcall(lasat_register_sysctl); +#endif /* CONFIG_SYSCTL */ diff --git a/arch/mips/lasat/sysctl.h b/arch/mips/lasat/sysctl.h new file mode 100644 index 0000000..341b979 --- /dev/null +++ b/arch/mips/lasat/sysctl.h @@ -0,0 +1,24 @@ +/* + * LASAT sysctl values + */ + +#ifndef _LASAT_SYSCTL_H +#define _LASAT_SYSCTL_H + +/* /proc/sys/lasat */ +enum { + LASAT_CPU_HZ = 1, + LASAT_BUS_HZ, + LASAT_MODEL, + LASAT_PRID, + LASAT_IPADDR, + LASAT_NETMASK, + LASAT_BCAST, + LASAT_PASSWORD, + LASAT_SBOOT, + LASAT_RTC, + LASAT_NAMESTR, + LASAT_TYPESTR, +}; + +#endif /* _LASAT_SYSCTL_H */ diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 4ee6800..ed0c076 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -10,6 +10,7 @@ obj-y += pci.o obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o obj-$(CONFIG_MIPS_MSC) += ops-msc.o +obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o @@ -19,6 +20,7 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o # These are still pretty much in the old state, watch, go blind. # obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o +obj-$(CONFIG_LASAT) += pci-lasat.o obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o diff --git a/arch/mips/pci/ops-nile4.c b/arch/mips/pci/ops-nile4.c new file mode 100644 index 0000000..b7f0fb0 --- /dev/null +++ b/arch/mips/pci/ops-nile4.c @@ -0,0 +1,147 @@ +#include +#include +#include +#include + +#include +#include +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +#define LO(reg) (reg / 4) +#define HI(reg) (reg / 4 + 1) + +volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE; + +static DEFINE_SPINLOCK(nile4_pci_lock); + +static int nile4_pcibios_config_access(unsigned char access_type, + struct pci_bus *bus, unsigned int devfn, int where, u32 *val) +{ + unsigned char busnum = bus->number; + u32 adr, mask, err; + + if ((busnum == 0) && (PCI_SLOT(devfn) > 8)) + /* The addressing scheme chosen leaves room for just + * 8 devices on the first busnum (besides the PCI + * controller itself) */ + return PCIBIOS_DEVICE_NOT_FOUND; + + if ((busnum == 0) && (devfn == PCI_DEVFN(0, 0))) { + /* Access controller registers directly */ + if (access_type == PCI_ACCESS_WRITE) { + vrc_pciregs[(0x200 + where) >> 2] = *val; + } else { + *val = vrc_pciregs[(0x200 + where) >> 2]; + } + return PCIBIOS_SUCCESSFUL; + } + + /* Temporarily map PCI Window 1 to config space */ + mask = vrc_pciregs[LO(NILE4_PCIINIT1)]; + vrc_pciregs[LO(NILE4_PCIINIT1)] = 0x0000001a | (busnum ? 0x200 : 0); + + /* Clear PCI Error register. This also clears the Error Type + * bits in the Control register */ + vrc_pciregs[LO(NILE4_PCIERR)] = 0; + vrc_pciregs[HI(NILE4_PCIERR)] = 0; + + /* Setup address */ + if (busnum == 0) + adr = + KSEG1ADDR(PCI_WINDOW1) + + ((1 << (PCI_SLOT(devfn) + 15)) | (PCI_FUNC(devfn) << 8) + | (where & ~3)); + else + adr = KSEG1ADDR(PCI_WINDOW1) | (busnum << 16) | (devfn << 8) | + (where & ~3); + + if (access_type == PCI_ACCESS_WRITE) + *(u32 *) adr = *val; + else + *val = *(u32 *) adr; + + /* Check for master or target abort */ + err = (vrc_pciregs[HI(NILE4_PCICTRL)] >> 5) & 0x7; + + /* Restore PCI Window 1 */ + vrc_pciregs[LO(NILE4_PCIINIT1)] = mask; + + if (err) + return PCIBIOS_DEVICE_NOT_FOUND; + + return PCIBIOS_SUCCESSFUL; +} + +static int nile4_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + unsigned long flags; + u32 data = 0; + int err; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + spin_lock_irqsave(&nile4_pci_lock, flags); + err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, + &data); + spin_unlock_irqrestore(&nile4_pci_lock, flags); + + if (err) + return err; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + +static int nile4_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + unsigned long flags; + u32 data = 0; + int err; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + spin_lock_irqsave(&nile4_pci_lock, flags); + err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, + &data); + spin_unlock_irqrestore(&nile4_pci_lock, flags); + + if (err) + return err; + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else + data = val; + + if (nile4_pcibios_config_access + (PCI_ACCESS_WRITE, bus, devfn, where, &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops nile4_pci_ops = { + .read = nile4_pcibios_read, + .write = nile4_pcibios_write, +}; diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c new file mode 100644 index 0000000..5abd5c7 --- /dev/null +++ b/arch/mips/pci/pci-lasat.c @@ -0,0 +1,91 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000, 2001, 04 Keith M Wesolowski + */ +#include +#include +#include +#include +#include + +extern struct pci_ops nile4_pci_ops; +extern struct pci_ops gt64xxx_pci0_ops; +static struct resource lasat_pci_mem_resource = { + .name = "LASAT PCI MEM", + .start = 0x18000000, + .end = 0x19ffffff, + .flags = IORESOURCE_MEM, +}; + +static struct resource lasat_pci_io_resource = { + .name = "LASAT PCI IO", + .start = 0x1a000000, + .end = 0x1bffffff, + .flags = IORESOURCE_IO, +}; + +static struct pci_controller lasat_pci_controller = { + .mem_resource = &lasat_pci_mem_resource, + .io_resource = &lasat_pci_io_resource, +}; + +static int __init lasat_pci_setup(void) +{ + printk(KERN_DEBUG "PCI: starting\n"); + + switch (mips_machtype) { + case MACH_LASAT_100: + lasat_pci_controller.pci_ops = >64xxx_pci0_ops; + break; + case MACH_LASAT_200: + lasat_pci_controller.pci_ops = &nile4_pci_ops; + break; + default: + panic("pcibios_init: mips_machtype incorrect"); + } + + register_pci_controller(&lasat_pci_controller); + + return 0; +} + +arch_initcall(lasat_pci_setup); + +#define LASATINT_ETH1 0 +#define LASATINT_ETH0 1 +#define LASATINT_HDC 2 +#define LASATINT_COMP 3 +#define LASATINT_HDLC 4 +#define LASATINT_PCIA 5 +#define LASATINT_PCIB 6 +#define LASATINT_PCIC 7 +#define LASATINT_PCID 8 + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + switch (slot) { + case 1: + case 2: + case 3: + return LASATINT_PCIA + (((slot-1) + (pin-1)) % 4); + case 4: + return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */ + case 5: + return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */ + case 6: + return LASATINT_HDC; /* IDE controller */ + default: + return 0xff; /* Illegal */ + } + + return -1; +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index c0f052b..1bb4bf6 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -175,6 +175,13 @@ #define MACH_HP_LASERJET 1 /* + * Valid machtype for group LASAT + */ +#define MACH_GROUP_LASAT 21 +#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */ +#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */ + +/* * Valid machtype for group TITAN */ #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ diff --git a/include/asm-mips/lasat/ds1603.h b/include/asm-mips/lasat/ds1603.h new file mode 100644 index 0000000..edcd754 --- /dev/null +++ b/include/asm-mips/lasat/ds1603.h @@ -0,0 +1,18 @@ +#include + +/* Lasat 100 */ +#define DS1603_REG_100 (KSEG1ADDR(0x1c810000)) +#define DS1603_RST_100 (1 << 2) +#define DS1603_CLK_100 (1 << 0) +#define DS1603_DATA_SHIFT_100 1 +#define DS1603_DATA_100 (1 << DS1603_DATA_SHIFT_100) + +/* Lasat 200 */ +#define DS1603_REG_200 (KSEG1ADDR(0x11000000)) +#define DS1603_RST_200 (1 << 3) +#define DS1603_CLK_200 (1 << 4) +#define DS1603_DATA_200 (1 << 5) + +#define DS1603_DATA_REG_200 (DS1603_REG_200 + 0x10000) +#define DS1603_DATA_READ_SHIFT_200 9 +#define DS1603_DATA_READ_200 (1 << DS1603_DATA_READ_SHIFT_200) diff --git a/include/asm-mips/lasat/eeprom.h b/include/asm-mips/lasat/eeprom.h new file mode 100644 index 0000000..3dac2036 --- /dev/null +++ b/include/asm-mips/lasat/eeprom.h @@ -0,0 +1,17 @@ +#include + +/* lasat 100 */ +#define AT93C_REG_100 KSEG1ADDR(0x1c810000) +#define AT93C_RDATA_REG_100 AT93C_REG_100 +#define AT93C_RDATA_SHIFT_100 4 +#define AT93C_WDATA_SHIFT_100 4 +#define AT93C_CS_M_100 (1 << 5) +#define AT93C_CLK_M_100 (1 << 3) + +/* lasat 200 */ +#define AT93C_REG_200 KSEG1ADDR(0x11000000) +#define AT93C_RDATA_REG_200 (AT93C_REG_200+0x10000) +#define AT93C_RDATA_SHIFT_200 8 +#define AT93C_WDATA_SHIFT_200 2 +#define AT93C_CS_M_200 (1 << 0) +#define AT93C_CLK_M_200 (1 << 1) diff --git a/include/asm-mips/lasat/head.h b/include/asm-mips/lasat/head.h new file mode 100644 index 0000000..f5589f3 --- /dev/null +++ b/include/asm-mips/lasat/head.h @@ -0,0 +1,22 @@ +/* + * Image header stuff + */ +#ifndef _HEAD_H +#define _HEAD_H + +#define LASAT_K_MAGIC0_VAL 0xfedeabba +#define LASAT_K_MAGIC1_VAL 0x00bedead + +#ifndef _LANGUAGE_ASSEMBLY +#include +struct bootloader_header { + u32 magic[2]; + u32 version; + u32 image_start; + u32 image_size; + u32 kernel_start; + u32 kernel_entry; +}; +#endif + +#endif /* _HEAD_H */ diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h new file mode 100644 index 0000000..ea04d92 --- /dev/null +++ b/include/asm-mips/lasat/lasat.h @@ -0,0 +1,256 @@ +/* + * lasat.h + * + * Thomas Horsten + * Copyright (C) 2000 LASAT Networks A/S. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Configuration for LASAT boards, loads the appropriate include files. + */ +#ifndef _LASAT_H +#define _LASAT_H + +#ifndef _LANGUAGE_ASSEMBLY + +extern struct lasat_misc { + volatile u32 *reset_reg; + volatile u32 *flash_wp_reg; + u32 flash_wp_bit; +} *lasat_misc; + +enum lasat_mtdparts { + LASAT_MTD_BOOTLOADER, + LASAT_MTD_SERVICE, + LASAT_MTD_NORMAL, + LASAT_MTD_CONFIG, + LASAT_MTD_FS, + LASAT_MTD_LAST +}; + +/* + * The format of the data record in the EEPROM. + * See Documentation/LASAT/eeprom.txt for a detailed description + * of the fields in this struct, and the LASAT Hardware Configuration + * field specification for a detailed description of the config + * field. + */ +#include + +#define LASAT_EEPROM_VERSION 7 +struct lasat_eeprom_struct { + unsigned int version; + unsigned int cfg[3]; + unsigned char hwaddr[6]; + unsigned char print_partno[12]; + unsigned char term0; + unsigned char print_serial[14]; + unsigned char term1; + unsigned char prod_partno[12]; + unsigned char term2; + unsigned char prod_serial[14]; + unsigned char term3; + unsigned char passwd_hash[16]; + unsigned char pwdnull; + unsigned char vendid; + unsigned char ts_ref; + unsigned char ts_signoff; + unsigned char reserved[11]; + unsigned char debugaccess; + unsigned short prid; + unsigned int serviceflag; + unsigned int ipaddr; + unsigned int netmask; + unsigned int crc32; +}; + +struct lasat_eeprom_struct_pre7 { + unsigned int version; + unsigned int flags[3]; + unsigned char hwaddr0[6]; + unsigned char hwaddr1[6]; + unsigned char print_partno[9]; + unsigned char term0; + unsigned char print_serial[14]; + unsigned char term1; + unsigned char prod_partno[9]; + unsigned char term2; + unsigned char prod_serial[14]; + unsigned char term3; + unsigned char passwd_hash[24]; + unsigned char pwdnull; + unsigned char vendor; + unsigned char ts_ref; + unsigned char ts_signoff; + unsigned char reserved[6]; + unsigned int writecount; + unsigned int ipaddr; + unsigned int netmask; + unsigned int crc32; +}; + +/* Configuration descriptor encoding - see the doc for details */ + +#define LASAT_W0_DSCTYPE(v) (((v)) & 0xf) +#define LASAT_W0_BMID(v) (((v) >> 0x04) & 0xf) +#define LASAT_W0_CPUTYPE(v) (((v) >> 0x08) & 0xf) +#define LASAT_W0_BUSSPEED(v) (((v) >> 0x0c) & 0xf) +#define LASAT_W0_CPUCLK(v) (((v) >> 0x10) & 0xf) +#define LASAT_W0_SDRAMBANKSZ(v) (((v) >> 0x14) & 0xf) +#define LASAT_W0_SDRAMBANKS(v) (((v) >> 0x18) & 0xf) +#define LASAT_W0_L2CACHE(v) (((v) >> 0x1c) & 0xf) + +#define LASAT_W1_EDHAC(v) (((v)) & 0xf) +#define LASAT_W1_HIFN(v) (((v) >> 0x04) & 0x1) +#define LASAT_W1_ISDN(v) (((v) >> 0x05) & 0x1) +#define LASAT_W1_IDE(v) (((v) >> 0x06) & 0x1) +#define LASAT_W1_HDLC(v) (((v) >> 0x07) & 0x1) +#define LASAT_W1_USVERSION(v) (((v) >> 0x08) & 0x1) +#define LASAT_W1_4MACS(v) (((v) >> 0x09) & 0x1) +#define LASAT_W1_EXTSERIAL(v) (((v) >> 0x0a) & 0x1) +#define LASAT_W1_FLASHSIZE(v) (((v) >> 0x0c) & 0xf) +#define LASAT_W1_PCISLOTS(v) (((v) >> 0x10) & 0xf) +#define LASAT_W1_PCI1OPT(v) (((v) >> 0x14) & 0xf) +#define LASAT_W1_PCI2OPT(v) (((v) >> 0x18) & 0xf) +#define LASAT_W1_PCI3OPT(v) (((v) >> 0x1c) & 0xf) + +/* Routines specific to LASAT boards */ + +#define LASAT_BMID_MASQUERADE2 0 +#define LASAT_BMID_MASQUERADEPRO 1 +#define LASAT_BMID_SAFEPIPE25 2 +#define LASAT_BMID_SAFEPIPE50 3 +#define LASAT_BMID_SAFEPIPE100 4 +#define LASAT_BMID_SAFEPIPE5000 5 +#define LASAT_BMID_SAFEPIPE7000 6 +#define LASAT_BMID_SAFEPIPE1000 7 +#if 0 +#define LASAT_BMID_SAFEPIPE30 7 +#define LASAT_BMID_SAFEPIPE5100 8 +#define LASAT_BMID_SAFEPIPE7100 9 +#endif +#define LASAT_BMID_UNKNOWN 0xf +#define LASAT_MAX_BMID_NAMES 9 /* no larger than 15! */ + +#define LASAT_HAS_EDHAC (1 << 0) +#define LASAT_EDHAC_FAST (1 << 1) +#define LASAT_HAS_EADI (1 << 2) +#define LASAT_HAS_HIFN (1 << 3) +#define LASAT_HAS_ISDN (1 << 4) +#define LASAT_HAS_LEASEDLINE_IF (1 << 5) +#define LASAT_HAS_HDC (1 << 6) + +#define LASAT_PRID_MASQUERADE2 0 +#define LASAT_PRID_MASQUERADEPRO 1 +#define LASAT_PRID_SAFEPIPE25 2 +#define LASAT_PRID_SAFEPIPE50 3 +#define LASAT_PRID_SAFEPIPE100 4 +#define LASAT_PRID_SAFEPIPE5000 5 +#define LASAT_PRID_SAFEPIPE7000 6 +#define LASAT_PRID_SAFEPIPE30 7 +#define LASAT_PRID_SAFEPIPE5100 8 +#define LASAT_PRID_SAFEPIPE7100 9 + +#define LASAT_PRID_SAFEPIPE1110 10 +#define LASAT_PRID_SAFEPIPE3020 11 +#define LASAT_PRID_SAFEPIPE3030 12 +#define LASAT_PRID_SAFEPIPE5020 13 +#define LASAT_PRID_SAFEPIPE5030 14 +#define LASAT_PRID_SAFEPIPE1120 15 +#define LASAT_PRID_SAFEPIPE1130 16 +#define LASAT_PRID_SAFEPIPE6010 17 +#define LASAT_PRID_SAFEPIPE6110 18 +#define LASAT_PRID_SAFEPIPE6210 19 +#define LASAT_PRID_SAFEPIPE1020 20 +#define LASAT_PRID_SAFEPIPE1040 21 +#define LASAT_PRID_SAFEPIPE1060 22 + +struct lasat_info { + unsigned int li_cpu_hz; + unsigned int li_bus_hz; + unsigned int li_bmid; + unsigned int li_memsize; + unsigned int li_flash_size; + unsigned int li_prid; + unsigned char li_bmstr[16]; + unsigned char li_namestr[32]; + unsigned char li_typestr[16]; + /* Info on the Flash layout */ + unsigned int li_flash_base; + unsigned long li_flashpart_base[LASAT_MTD_LAST]; + unsigned long li_flashpart_size[LASAT_MTD_LAST]; + struct lasat_eeprom_struct li_eeprom_info; + unsigned int li_eeprom_upgrade_version; + unsigned int li_debugaccess; +}; + +extern struct lasat_info lasat_board_info; + +static inline unsigned long lasat_flash_partition_start(int partno) +{ + if (partno < 0 || partno >= LASAT_MTD_LAST) + return 0; + + return lasat_board_info.li_flashpart_base[partno]; +} + +static inline unsigned long lasat_flash_partition_size(int partno) +{ + if (partno < 0 || partno >= LASAT_MTD_LAST) + return 0; + + return lasat_board_info.li_flashpart_size[partno]; +} + +/* Called from setup() to initialize the global board_info struct */ +extern int lasat_init_board_info(void); + +/* Write the modified EEPROM info struct */ +extern void lasat_write_eeprom_info(void); + +#define N_MACHTYPES 2 +/* for calibration of delays */ + +/* the lasat_ndelay function is necessary because it is used at an + * early stage of the boot process where ndelay is not calibrated. + * It is used for the bit-banging rtc and eeprom drivers */ + +#include + +/* calculating with the slowest board with 100 MHz clock */ +#define LASAT_100_DIVIDER 20 +/* All 200's run at 250 MHz clock */ +#define LASAT_200_DIVIDER 8 + +extern unsigned int lasat_ndelay_divider; + +static inline void lasat_ndelay(unsigned int ns) +{ + __delay(ns / lasat_ndelay_divider); +} + +#endif /* !defined (_LANGUAGE_ASSEMBLY) */ + +#define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef +#define LASAT_SERVICEMODE_MAGIC_2 0xfedeabba + +/* Lasat 100 boards */ +#define LASAT_GT_BASE (KSEG1ADDR(0x14000000)) + +/* Lasat 200 boards */ +#define Vrc5074_PHYS_BASE 0x1fa00000 +#define Vrc5074_BASE (KSEG1ADDR(Vrc5074_PHYS_BASE)) +#define PCI_WINDOW1 0x1a000000 + +#endif /* _LASAT_H */ diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h new file mode 100644 index 0000000..065474f --- /dev/null +++ b/include/asm-mips/lasat/lasatint.h @@ -0,0 +1,12 @@ +#define LASATINT_END 16 + +/* lasat 100 */ +#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000)) +#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000)) +#define LASATINT_MASK_SHIFT_100 0 + +/* lasat 200 */ +#define LASAT_INT_STATUS_REG_200 (KSEG1ADDR(0x1104003c)) +#define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c)) +#define LASATINT_MASK_SHIFT_200 16 + diff --git a/include/asm-mips/lasat/picvue.h b/include/asm-mips/lasat/picvue.h new file mode 100644 index 0000000..42a492e --- /dev/null +++ b/include/asm-mips/lasat/picvue.h @@ -0,0 +1,15 @@ +/* Lasat 100 */ +#define PVC_REG_100 KSEG1ADDR(0x1c820000) +#define PVC_DATA_SHIFT_100 0 +#define PVC_DATA_M_100 0xFF +#define PVC_E_100 (1 << 8) +#define PVC_RW_100 (1 << 9) +#define PVC_RS_100 (1 << 10) + +/* Lasat 200 */ +#define PVC_REG_200 KSEG1ADDR(0x11000000) +#define PVC_DATA_SHIFT_200 24 +#define PVC_DATA_M_200 (0xFF << PVC_DATA_SHIFT_200) +#define PVC_E_200 (1 << 16) +#define PVC_RW_200 (1 << 17) +#define PVC_RS_200 (1 << 18) diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h new file mode 100644 index 0000000..bafe68b --- /dev/null +++ b/include/asm-mips/lasat/serial.h @@ -0,0 +1,13 @@ +#include + +/* Lasat 100 boards serial configuration */ +#define LASAT_BASE_BAUD_100 (7372800 / 16) +#define LASAT_UART_REGS_BASE_100 0x1c8b0000 +#define LASAT_UART_REGS_SHIFT_100 2 +#define LASATINT_UART_100 8 + +/* * LASAT 200 boards serial configuration */ +#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) +#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300) +#define LASAT_UART_REGS_SHIFT_200 3 +#define LASATINT_UART_200 13 diff --git a/include/asm-mips/mach-lasat/mach-gt64120.h b/include/asm-mips/mach-lasat/mach-gt64120.h new file mode 100644 index 0000000..1a9ad45 --- /dev/null +++ b/include/asm-mips/mach-lasat/mach-gt64120.h @@ -0,0 +1,27 @@ +/* + * This is a direct copy of the ev96100.h file, with a global + * search and replace. The numbers are the same. + * + * The reason I'm duplicating this is so that the 64120/96100 + * defines won't be confusing in the source code. + */ +#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H +#define _ASM_GT64120_LASAT_GT64120_DEP_H + +/* + * GT64120 config space base address on Lasat 100 + */ +#define GT64120_BASE (KSEG1ADDR(0x14000000)) + +/* + * PCI Bus allocation + * + * (Guessing ...) + */ +#define GT_PCI_MEM_BASE 0x12000000UL +#define GT_PCI_MEM_SIZE 0x02000000UL +#define GT_PCI_IO_BASE 0x10000000UL +#define GT_PCI_IO_SIZE 0x02000000UL +#define GT_ISA_IO_BASE PCI_IO_BASE + +#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */ diff --git a/include/asm-mips/nile4.h b/include/asm-mips/nile4.h new file mode 100644 index 0000000..c3ca959 --- /dev/null +++ b/include/asm-mips/nile4.h @@ -0,0 +1,310 @@ +/* + * asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions + * + * Copyright (C) 2000 Geert Uytterhoeven + * Sony Software Development Center Europe (SDCE), Brussels + * + * This file is based on the following documentation: + * + * NEC Vrc 5074 System Controller Data Sheet, June 1998 + */ + +#ifndef _ASM_NILE4_H +#define _ASM_NILE4_H + +#define NILE4_BASE 0xbfa00000 +#define NILE4_SIZE 0x00200000 /* 2 MB */ + + + /* + * Physical Device Address Registers (PDARs) + */ + +#define NILE4_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */ +#define NILE4_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */ +#define NILE4_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */ +#define NILE4_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */ +#define NILE4_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */ +#define NILE4_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */ +#define NILE4_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */ +#define NILE4_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */ +#define NILE4_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */ +#define NILE4_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */ +#define NILE4_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */ +#define NILE4_INTCS 0x0070 /* Controller Internal Registers and Devices */ + /* [R/W] */ +#define NILE4_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */ + + + /* + * CPU Interface Registers + */ + +#define NILE4_CPUSTAT 0x0080 /* CPU Status [R/W] */ +#define NILE4_INTCTRL 0x0088 /* Interrupt Control [R/W] */ +#define NILE4_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */ +#define NILE4_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */ + /* Enable [R/W] */ +#define NILE4_INTCLR 0x00A0 /* Interrupt Clear [R/W] */ +#define NILE4_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */ + + + /* + * Memory-Interface Registers + */ + +#define NILE4_MEMCTRL 0x00C0 /* Memory Control */ +#define NILE4_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */ +#define NILE4_CHKERR 0x00D0 /* Memory Check Error Status [R] */ + + + /* + * PCI-Bus Registers + */ + +#define NILE4_PCICTRL 0x00E0 /* PCI Control [R/W] */ +#define NILE4_PCIARB 0x00E8 /* PCI Arbiter [R/W] */ +#define NILE4_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */ +#define NILE4_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */ +#define NILE4_PCIERR 0x00B8 /* PCI Error [R/W] */ + + + /* + * Local-Bus Registers + */ + +#define NILE4_LCNFG 0x0100 /* Local Bus Configuration [R/W] */ +#define NILE4_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */ +#define NILE4_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */ +#define NILE4_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */ +#define NILE4_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */ +#define NILE4_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */ +#define NILE4_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */ +#define NILE4_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */ +#define NILE4_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */ + /* Enables [R/W] */ +#define NILE4_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */ +#define NILE4_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */ + + + /* + * DMA Registers + */ + +#define NILE4_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */ +#define NILE4_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */ +#define NILE4_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */ +#define NILE4_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */ +#define NILE4_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */ +#define NILE4_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */ + + + /* + * Timer Registers + */ + +#define NILE4_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */ +#define NILE4_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */ +#define NILE4_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */ +#define NILE4_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */ +#define NILE4_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */ +#define NILE4_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */ +#define NILE4_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */ +#define NILE4_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */ + + + /* + * PCI Configuration Space Registers + */ + +#define NILE4_PCI_BASE 0x0200 + +#define NILE4_VID 0x0200 /* PCI Vendor ID [R] */ +#define NILE4_DID 0x0202 /* PCI Device ID [R] */ +#define NILE4_PCICMD 0x0204 /* PCI Command [R/W] */ +#define NILE4_PCISTS 0x0206 /* PCI Status [R/W] */ +#define NILE4_REVID 0x0208 /* PCI Revision ID [R] */ +#define NILE4_CLASS 0x0209 /* PCI Class Code [R] */ +#define NILE4_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */ +#define NILE4_MLTIM 0x020D /* PCI Latency Timer [R/W] */ +#define NILE4_HTYPE 0x020E /* PCI Header Type [R] */ +#define NILE4_BIST 0x020F /* BIST [R] (unimplemented) */ +#define NILE4_BARC 0x0210 /* PCI Base Address Register Control [R/W] */ +#define NILE4_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */ +#define NILE4_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */ +#define NILE4_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */ + /* (unimplemented) */ +#define NILE4_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */ +#define NILE4_SSID 0x022E /* PCI Sub-System ID [R/W] */ +#define NILE4_ROM 0x0230 /* Expansion ROM Base Address [R] */ + /* (unimplemented) */ +#define NILE4_INTLIN 0x023C /* PCI Interrupt Line [R/W] */ +#define NILE4_INTPIN 0x023D /* PCI Interrupt Pin [R] */ +#define NILE4_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */ +#define NILE4_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */ +#define NILE4_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */ +#define NILE4_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */ +#define NILE4_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */ +#define NILE4_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */ +#define NILE4_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */ +#define NILE4_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */ +#define NILE4_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */ +#define NILE4_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */ + + + /* + * Serial-Port Registers + */ + +#define NILE4_UART_BASE 0x0300 + +#define NILE4_UARTRBR 0x0300 /* UART Receiver Data Buffer [R] */ +#define NILE4_UARTTHR 0x0300 /* UART Transmitter Data Holding [W] */ +#define NILE4_UARTIER 0x0308 /* UART Interrupt Enable [R/W] */ +#define NILE4_UARTDLL 0x0300 /* UART Divisor Latch LSB [R/W] */ +#define NILE4_UARTDLM 0x0308 /* UART Divisor Latch MSB [R/W] */ +#define NILE4_UARTIIR 0x0310 /* UART Interrupt ID [R] */ +#define NILE4_UARTFCR 0x0310 /* UART FIFO Control [W] */ +#define NILE4_UARTLCR 0x0318 /* UART Line Control [R/W] */ +#define NILE4_UARTMCR 0x0320 /* UART Modem Control [R/W] */ +#define NILE4_UARTLSR 0x0328 /* UART Line Status [R/W] */ +#define NILE4_UARTMSR 0x0330 /* UART Modem Status [R/W] */ +#define NILE4_UARTSCR 0x0338 /* UART Scratch [R/W] */ + +#define NILE4_UART_BASE_BAUD 520833 /* 100 MHz / 12 / 16 */ + + + /* + * Interrupt Lines + */ + +#define NILE4_INT_CPCE 0 /* CPU-Interface Parity-Error Interrupt */ +#define NILE4_INT_CNTD 1 /* CPU No-Target Decode Interrupt */ +#define NILE4_INT_MCE 2 /* Memory-Check Error Interrupt */ +#define NILE4_INT_DMA 3 /* DMA Controller Interrupt */ +#define NILE4_INT_UART 4 /* UART Interrupt */ +#define NILE4_INT_WDOG 5 /* Watchdog Timer Interrupt */ +#define NILE4_INT_GPT 6 /* General-Purpose Timer Interrupt */ +#define NILE4_INT_LBRTD 7 /* Local-Bus Ready Timer Interrupt */ +#define NILE4_INT_INTA 8 /* PCI Interrupt Signal INTA# */ +#define NILE4_INT_INTB 9 /* PCI Interrupt Signal INTB# */ +#define NILE4_INT_INTC 10 /* PCI Interrupt Signal INTC# */ +#define NILE4_INT_INTD 11 /* PCI Interrupt Signal INTD# */ +#define NILE4_INT_INTE 12 /* PCI Interrupt Signal INTE# (ISA cascade) */ +#define NILE4_INT_RESV 13 /* Reserved */ +#define NILE4_INT_PCIS 14 /* PCI SERR# Interrupt */ +#define NILE4_INT_PCIE 15 /* PCI Internal Error Interrupt */ + + + /* + * Nile 4 Register Access + */ + +static inline void nile4_sync(void) +{ + volatile u32 *p = (volatile u32 *)0xbfc00000; + (void)(*p); +} + +static inline void nile4_out32(u32 offset, u32 val) +{ + *(volatile u32 *)(NILE4_BASE+offset) = val; + nile4_sync(); +} + +static inline u32 nile4_in32(u32 offset) +{ + u32 val = *(volatile u32 *)(NILE4_BASE+offset); + nile4_sync(); + return val; +} + +static inline void nile4_out16(u32 offset, u16 val) +{ + *(volatile u16 *)(NILE4_BASE+offset) = val; + nile4_sync(); +} + +static inline u16 nile4_in16(u32 offset) +{ + u16 val = *(volatile u16 *)(NILE4_BASE+offset); + nile4_sync(); + return val; +} + +static inline void nile4_out8(u32 offset, u8 val) +{ + *(volatile u8 *)(NILE4_BASE+offset) = val; + nile4_sync(); +} + +static inline u8 nile4_in8(u32 offset) +{ + u8 val = *(volatile u8 *)(NILE4_BASE+offset); + nile4_sync(); + return val; +} + + + /* + * Physical Device Address Registers + */ + +extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width, + int on_memory_bus, int visible); + + + /* + * PCI Master Registers + */ + +#define NILE4_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */ +#define NILE4_PCICMD_IO 1 /* PCI I/O Space */ +#define NILE4_PCICMD_MEM 3 /* PCI Memory Space */ +#define NILE4_PCICMD_CFG 5 /* PCI Configuration Space */ + + + /* + * PCI Address Spaces + * + * Note that these are multiplexed using PCIINIT[01]! + */ + +#define NILE4_PCI_IO_BASE 0xa6000000 +#define NILE4_PCI_MEM_BASE 0xa8000000 +#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE +#define NILE4_PCI_IACK_BASE NILE4_PCI_IO_BASE + + +extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr); + + + /* + * Interrupt Programming + */ + +#define NUM_I8259_INTERRUPTS 16 +#define NUM_NILE4_INTERRUPTS 16 + +#define IRQ_I8259_CASCADE NILE4_INT_INTE +#define is_i8259_irq(irq) ((irq) < NUM_I8259_INTERRUPTS) +#define nile4_to_irq(n) ((n)+NUM_I8259_INTERRUPTS) +#define irq_to_nile4(n) ((n)-NUM_I8259_INTERRUPTS) + +extern void nile4_map_irq(int nile4_irq, int cpu_irq); +extern void nile4_map_irq_all(int cpu_irq); +extern void nile4_enable_irq(unsigned int nile4_irq); +extern void nile4_disable_irq(unsigned int nile4_irq); +extern void nile4_disable_irq_all(void); +extern u16 nile4_get_irq_stat(int cpu_irq); +extern void nile4_enable_irq_output(int cpu_irq); +extern void nile4_disable_irq_output(int cpu_irq); +extern void nile4_set_pci_irq_polarity(int pci_irq, int high); +extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level); +extern void nile4_clear_irq(int nile4_irq); +extern void nile4_clear_irq_mask(u32 mask); +extern u8 nile4_i8259_iack(void); +extern void nile4_dump_irq_status(void); /* Debug */ + +#endif + -- cgit v0.10.2 From ea202c632a52c4a83f1bd82d8d06bc8e04f2689a Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Sat, 25 Aug 2007 11:01:50 +0200 Subject: [MIPS] JAZZ fixes - restructured irq handling - switched vdma to use memory allocated via get_free_pages - setup platform devices for serial, jazz_esp and jazzsonic - fixed cmos rtc access Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index bb3fb40..a8bdc08 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -93,6 +93,7 @@ config MACH_JAZZ select ARC32 select ARCH_MAY_HAVE_PC_FDC select GENERIC_ISA_DMA + select IRQ_CPU select I8259 select ISA select PCSPEAKER diff --git a/arch/mips/jazz/Makefile b/arch/mips/jazz/Makefile index 575a944..5aee0c2 100644 --- a/arch/mips/jazz/Makefile +++ b/arch/mips/jazz/Makefile @@ -2,6 +2,6 @@ # Makefile for the Jazz family specific parts of the kernel # -obj-y := irq.o jazzdma.o jazz-platform.o reset.o setup.o +obj-y := irq.o jazzdma.o reset.o setup.o EXTRA_CFLAGS += -Werror diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index 015cf4b..5623541 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c @@ -11,15 +11,17 @@ #include #include +#include #include #include #include +#include static DEFINE_SPINLOCK(r4030_lock); static void enable_r4030_irq(unsigned int irq) { - unsigned int mask = 1 << (irq - JAZZ_PARALLEL_IRQ); + unsigned int mask = 1 << (irq - JAZZ_IRQ_START); unsigned long flags; spin_lock_irqsave(&r4030_lock, flags); @@ -30,7 +32,7 @@ static void enable_r4030_irq(unsigned int irq) void disable_r4030_irq(unsigned int irq) { - unsigned int mask = ~(1 << (irq - JAZZ_PARALLEL_IRQ)); + unsigned int mask = ~(1 << (irq - JAZZ_IRQ_START)); unsigned long flags; spin_lock_irqsave(&r4030_lock, flags); @@ -51,7 +53,7 @@ void __init init_r4030_ints(void) { int i; - for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++) + for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++) set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq); r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); @@ -66,82 +68,40 @@ void __init init_r4030_ints(void) */ void __init arch_init_irq(void) { + /* + * this is a hack to get back the still needed wired mapping + * killed by init_mm() + */ + + /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */ + add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K); + /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */ + add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M); + /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */ + add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M); + init_i8259_irqs(); /* Integrated i8259 */ + mips_cpu_irq_init(); init_r4030_ints(); - change_c0_status(ST0_IM, IE_IRQ4 | IE_IRQ3 | IE_IRQ2 | IE_IRQ1); -} - -static void loc_call(unsigned int irq, unsigned int mask) -{ - r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, - r4030_read_reg16(JAZZ_IO_IRQ_ENABLE) & mask); - do_IRQ(irq); - r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, - r4030_read_reg16(JAZZ_IO_IRQ_ENABLE) | mask); -} - -static void ll_local_dev(void) -{ - switch (r4030_read_reg32(JAZZ_IO_IRQ_SOURCE)) { - case 0: - panic("Unimplemented loc_no_irq handler"); - break; - case 4: - loc_call(JAZZ_PARALLEL_IRQ, JAZZ_IE_PARALLEL); - break; - case 8: - loc_call(JAZZ_PARALLEL_IRQ, JAZZ_IE_FLOPPY); - break; - case 12: - panic("Unimplemented loc_sound handler"); - break; - case 16: - panic("Unimplemented loc_video handler"); - break; - case 20: - loc_call(JAZZ_ETHERNET_IRQ, JAZZ_IE_ETHERNET); - break; - case 24: - loc_call(JAZZ_SCSI_IRQ, JAZZ_IE_SCSI); - break; - case 28: - loc_call(JAZZ_KEYBOARD_IRQ, JAZZ_IE_KEYBOARD); - break; - case 32: - loc_call(JAZZ_MOUSE_IRQ, JAZZ_IE_MOUSE); - break; - case 36: - loc_call(JAZZ_SERIAL1_IRQ, JAZZ_IE_SERIAL1); - break; - case 40: - loc_call(JAZZ_SERIAL2_IRQ, JAZZ_IE_SERIAL2); - break; - } + change_c0_status(ST0_IM, IE_IRQ2 | IE_IRQ1); } asmlinkage void plat_irq_dispatch(void) { unsigned int pending = read_c0_cause() & read_c0_status(); + unsigned int irq; - if (pending & IE_IRQ5) - write_c0_compare(0); - else if (pending & IE_IRQ4) { + if (pending & IE_IRQ4) { r4030_read_reg32(JAZZ_TIMER_REGISTER); do_IRQ(JAZZ_TIMER_IRQ); - } else if (pending & IE_IRQ3) - panic("Unimplemented ISA NMI handler"); - else if (pending & IE_IRQ2) + } else if (pending & IE_IRQ2) do_IRQ(r4030_read_reg32(JAZZ_EISA_IRQ_ACK)); else if (pending & IE_IRQ1) { - ll_local_dev(); - } else if (unlikely(pending & IE_IRQ0)) - panic("Unimplemented local_dma handler"); - else if (pending & IE_SW1) { - clear_c0_cause(IE_SW1); - panic("Unimplemented sw1 handler"); - } else if (pending & IE_SW0) { - clear_c0_cause(IE_SW0); - panic("Unimplemented sw0 handler"); + irq = *(volatile u8 *)JAZZ_IO_IRQ_SOURCE >> 2; + if (likely(irq > 0)) + do_IRQ(irq + JAZZ_IRQ_START - 1); + else + panic("Unimplemented loc_no_irq handler"); } } diff --git a/arch/mips/jazz/jazz-platform.c b/arch/mips/jazz/jazz-platform.c deleted file mode 100644 index fd73670..0000000 --- a/arch/mips/jazz/jazz-platform.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) - */ -#include -#include -#include - -#include - -/* - * Confusion ... It seems the original Microsoft Jazz machine used to have a - * 4.096MHz clock for its UART while the MIPS Magnum and Millenium systems - * had 8MHz. The Olivetti M700-10 and the Acer PICA have 1.8432MHz like PCs. - */ -#ifdef CONFIG_OLIVETTI_M700 -#define JAZZ_BASE_BAUD 1843200 -#else -#define JAZZ_BASE_BAUD 8000000 /* 3072000 */ -#endif - -#define JAZZ_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) - -#define JAZZ_PORT(base, int) \ -{ \ - .mapbase = base, \ - .irq = int, \ - .uartclk = JAZZ_BASE_BAUD, \ - .iotype = UPIO_MEM, \ - .flags = JAZZ_UART_FLAGS, \ - .regshift = 0, \ -} - -static struct plat_serial8250_port uart8250_data[] = { - JAZZ_PORT(JAZZ_SERIAL1_BASE, JAZZ_SERIAL1_IRQ), - JAZZ_PORT(JAZZ_SERIAL2_BASE, JAZZ_SERIAL2_IRQ), - { }, -}; - -static struct platform_device uart8250_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = uart8250_data, - }, -}; - -static int __init uart8250_init(void) -{ - return platform_device_register(&uart8250_device); -} - -module_init(uart8250_init); - -MODULE_AUTHOR("Ralf Baechle "); -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("8250 UART probe driver for the Jazz family"); diff --git a/arch/mips/jazz/jazzdma.c b/arch/mips/jazz/jazzdma.c index e8e0ffb..c672c08 100644 --- a/arch/mips/jazz/jazzdma.c +++ b/arch/mips/jazz/jazzdma.c @@ -27,7 +27,7 @@ */ #define CONF_DEBUG_VDMA 0 -static unsigned long vdma_pagetable_start; +static VDMA_PGTBL_ENTRY *pgtbl; static DEFINE_SPINLOCK(vdma_lock); @@ -46,7 +46,6 @@ static int debuglvl = 3; */ static inline void vdma_pgtbl_init(void) { - VDMA_PGTBL_ENTRY *pgtbl = (VDMA_PGTBL_ENTRY *) vdma_pagetable_start; unsigned long paddr = 0; int i; @@ -60,31 +59,31 @@ static inline void vdma_pgtbl_init(void) /* * Initialize the Jazz R4030 dma controller */ -void __init vdma_init(void) +static int __init vdma_init(void) { /* * Allocate 32k of memory for DMA page tables. This needs to be page * aligned and should be uncached to avoid cache flushing after every * update. */ - vdma_pagetable_start = - (unsigned long) alloc_bootmem_low_pages(VDMA_PGTBL_SIZE); - if (!vdma_pagetable_start) + pgtbl = (VDMA_PGTBL_ENTRY *)__get_free_pages(GFP_KERNEL | GFP_DMA, + get_order(VDMA_PGTBL_SIZE)); + if (!pgtbl) BUG(); - dma_cache_wback_inv(vdma_pagetable_start, VDMA_PGTBL_SIZE); - vdma_pagetable_start = KSEG1ADDR(vdma_pagetable_start); + dma_cache_wback_inv((unsigned long)pgtbl, VDMA_PGTBL_SIZE); + pgtbl = (VDMA_PGTBL_ENTRY *)KSEG1ADDR(pgtbl); /* * Clear the R4030 translation table */ vdma_pgtbl_init(); - r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE, - CPHYSADDR(vdma_pagetable_start)); + r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE, CPHYSADDR(pgtbl)); r4030_write_reg32(JAZZ_R4030_TRSTBL_LIM, VDMA_PGTBL_SIZE); r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0); - printk("VDMA: R4030 DMA pagetables initialized.\n"); + printk(KERN_INFO "VDMA: R4030 DMA pagetables initialized.\n"); + return 0; } /* @@ -92,7 +91,6 @@ void __init vdma_init(void) */ unsigned long vdma_alloc(unsigned long paddr, unsigned long size) { - VDMA_PGTBL_ENTRY *entry = (VDMA_PGTBL_ENTRY *) vdma_pagetable_start; int first, last, pages, frame, i; unsigned long laddr, flags; @@ -114,10 +112,10 @@ unsigned long vdma_alloc(unsigned long paddr, unsigned long size) /* * Find free chunk */ - pages = (size + 4095) >> 12; /* no. of pages to allocate */ + pages = VDMA_PAGE(paddr + size) - VDMA_PAGE(paddr) + 1; first = 0; while (1) { - while (entry[first].owner != VDMA_PAGE_EMPTY && + while (pgtbl[first].owner != VDMA_PAGE_EMPTY && first < VDMA_PGTBL_ENTRIES) first++; if (first + pages > VDMA_PGTBL_ENTRIES) { /* nothing free */ spin_unlock_irqrestore(&vdma_lock, flags); @@ -125,12 +123,13 @@ unsigned long vdma_alloc(unsigned long paddr, unsigned long size) } last = first + 1; - while (entry[last].owner == VDMA_PAGE_EMPTY + while (pgtbl[last].owner == VDMA_PAGE_EMPTY && last - first < pages) last++; if (last - first == pages) break; /* found */ + first = last + 1; } /* @@ -140,8 +139,8 @@ unsigned long vdma_alloc(unsigned long paddr, unsigned long size) frame = paddr & ~(VDMA_PAGESIZE - 1); for (i = first; i < last; i++) { - entry[i].frame = frame; - entry[i].owner = laddr; + pgtbl[i].frame = frame; + pgtbl[i].owner = laddr; frame += VDMA_PAGESIZE; } @@ -160,10 +159,10 @@ unsigned long vdma_alloc(unsigned long paddr, unsigned long size) printk("%08x ", i << 12); printk("\nPADDR: "); for (i = first; i < last; i++) - printk("%08x ", entry[i].frame); + printk("%08x ", pgtbl[i].frame); printk("\nOWNER: "); for (i = first; i < last; i++) - printk("%08x ", entry[i].owner); + printk("%08x ", pgtbl[i].owner); printk("\n"); } @@ -181,7 +180,6 @@ EXPORT_SYMBOL(vdma_alloc); */ int vdma_free(unsigned long laddr) { - VDMA_PGTBL_ENTRY *pgtbl = (VDMA_PGTBL_ENTRY *) vdma_pagetable_start; int i; i = laddr >> 12; @@ -213,8 +211,6 @@ EXPORT_SYMBOL(vdma_free); */ int vdma_remap(unsigned long laddr, unsigned long paddr, unsigned long size) { - VDMA_PGTBL_ENTRY *pgtbl = - (VDMA_PGTBL_ENTRY *) vdma_pagetable_start; int first, pages, npages; if (laddr > 0xffffff) { @@ -289,8 +285,6 @@ unsigned long vdma_phys2log(unsigned long paddr) { int i; int frame; - VDMA_PGTBL_ENTRY *pgtbl = - (VDMA_PGTBL_ENTRY *) vdma_pagetable_start; frame = paddr & ~(VDMA_PAGESIZE - 1); @@ -312,9 +306,6 @@ EXPORT_SYMBOL(vdma_phys2log); */ unsigned long vdma_log2phys(unsigned long laddr) { - VDMA_PGTBL_ENTRY *pgtbl = - (VDMA_PGTBL_ENTRY *) vdma_pagetable_start; - return pgtbl[laddr >> 12].frame + (laddr & (VDMA_PAGESIZE - 1)); } @@ -564,3 +555,5 @@ int vdma_get_enable(int channel) return enable; } + +arch_initcall(vdma_init); diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c index 798279e..5c6271a 100644 --- a/arch/mips/jazz/setup.c +++ b/arch/mips/jazz/setup.c @@ -7,6 +7,7 @@ * * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle * Copyright (C) 2001 MIPS Technologies, Inc. + * Copyright (C) 2007 by Thomas Bogendoerfer */ #include #include @@ -20,6 +21,8 @@ #include #include #include +#include +#include #include #include @@ -30,6 +33,7 @@ #include #include #include +#include extern asmlinkage void jazz_handle_int(void); @@ -72,10 +76,8 @@ void __init plat_mem_setup(void) /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */ add_wired_entry (0x02000017, 0x03c00017, 0xe0000000, PM_64K); - /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */ add_wired_entry (0x02400017, 0x02440017, 0xe2000000, PM_16M); - /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */ add_wired_entry (0x01800017, 0x01000017, 0xe4000000, PM_4M); @@ -94,6 +96,7 @@ void __init plat_mem_setup(void) _machine_restart = jazz_machine_restart; +#ifdef CONFIG_VT screen_info = (struct screen_info) { 0, 0, /* orig-x, orig-y */ 0, /* unused */ @@ -105,6 +108,112 @@ void __init plat_mem_setup(void) 0, /* orig_video_isVGA */ 16 /* orig_video_points */ }; +#endif - vdma_init(); + add_preferred_console("ttyS", 0, "9600"); } + +#ifdef CONFIG_OLIVETTI_M700 +#define UART_CLK 1843200 +#else +/* Some Jazz machines seem to have an 8MHz crystal clock but I don't know + exactly which ones ... XXX */ +#define UART_CLK (8000000 / 16) /* ( 3072000 / 16) */ +#endif + +#define MEMPORT(_base, _irq) \ + { \ + .mapbase = (_base), \ + .membase = (void *)(_base), \ + .irq = (_irq), \ + .uartclk = UART_CLK, \ + .iotype = UPIO_MEM, \ + .flags = UPF_BOOT_AUTOCONF, \ + } + +static struct plat_serial8250_port jazz_serial_data[] = { + MEMPORT(JAZZ_SERIAL1_BASE, JAZZ_SERIAL1_IRQ), + MEMPORT(JAZZ_SERIAL2_BASE, JAZZ_SERIAL2_IRQ), + { }, +}; + +static struct platform_device jazz_serial8250_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = jazz_serial_data, + }, +}; + +static struct resource jazz_esp_rsrc[] = { + { + .start = JAZZ_SCSI_BASE, + .end = JAZZ_SCSI_BASE + 31, + .flags = IORESOURCE_MEM + }, + { + .start = JAZZ_SCSI_DMA, + .end = JAZZ_SCSI_DMA, + .flags = IORESOURCE_MEM + }, + { + .start = JAZZ_SCSI_IRQ, + .end = JAZZ_SCSI_IRQ, + .flags = IORESOURCE_IRQ + } +}; + +static struct platform_device jazz_esp_pdev = { + .name = "jazz_esp", + .num_resources = ARRAY_SIZE(jazz_esp_rsrc), + .resource = jazz_esp_rsrc +}; + +static struct resource jazz_sonic_rsrc[] = { + { + .start = JAZZ_ETHERNET_BASE, + .end = JAZZ_ETHERNET_BASE + 0xff, + .flags = IORESOURCE_MEM + }, + { + .start = JAZZ_ETHERNET_IRQ, + .end = JAZZ_ETHERNET_IRQ, + .flags = IORESOURCE_IRQ + } +}; + +static struct platform_device jazz_sonic_pdev = { + .name = "jazzsonic", + .num_resources = ARRAY_SIZE(jazz_sonic_rsrc), + .resource = jazz_sonic_rsrc +}; + +static struct resource jazz_cmos_rsrc[] = { + { + .start = 0x70, + .end = 0x71, + .flags = IORESOURCE_IO + }, + { + .start = 8, + .end = 8, + .flags = IORESOURCE_IRQ + } +}; + +static struct platform_device jazz_cmos_pdev = { + .name = "rtc_cmos", + .num_resources = ARRAY_SIZE(jazz_cmos_rsrc), + .resource = jazz_cmos_rsrc +}; + +static int __init jazz_setup_devinit(void) +{ + platform_device_register(&jazz_serial8250_device); + platform_device_register(&jazz_esp_pdev); + platform_device_register(&jazz_sonic_pdev); + platform_device_register(&jazz_cmos_pdev); + return 0; +} + +device_initcall(jazz_setup_devinit); diff --git a/include/asm-mips/jazz.h b/include/asm-mips/jazz.h index 81cbf00..83f449d 100644 --- a/include/asm-mips/jazz.h +++ b/include/asm-mips/jazz.h @@ -185,37 +185,25 @@ typedef struct { #define JAZZ_IO_IRQ_ENABLE 0xe0010002 /* - * JAZZ interrupt enable bits - */ -#define JAZZ_IE_PARALLEL (1 << 0) -#define JAZZ_IE_FLOPPY (1 << 1) -#define JAZZ_IE_SOUND (1 << 2) -#define JAZZ_IE_VIDEO (1 << 3) -#define JAZZ_IE_ETHERNET (1 << 4) -#define JAZZ_IE_SCSI (1 << 5) -#define JAZZ_IE_KEYBOARD (1 << 6) -#define JAZZ_IE_MOUSE (1 << 7) -#define JAZZ_IE_SERIAL1 (1 << 8) -#define JAZZ_IE_SERIAL2 (1 << 9) - -/* * JAZZ Interrupt Level definitions * * This is somewhat broken. For reasons which nobody can remember anymore * we remap the Jazz interrupts to the usual ISA style interrupt numbers. */ -#define JAZZ_PARALLEL_IRQ 16 -#define JAZZ_FLOPPY_IRQ 17 -#define JAZZ_SOUND_IRQ 18 -#define JAZZ_VIDEO_IRQ 19 -#define JAZZ_ETHERNET_IRQ 20 -#define JAZZ_SCSI_IRQ 21 -#define JAZZ_KEYBOARD_IRQ 22 -#define JAZZ_MOUSE_IRQ 23 -#define JAZZ_SERIAL1_IRQ 24 -#define JAZZ_SERIAL2_IRQ 25 - -#define JAZZ_TIMER_IRQ 31 +#define JAZZ_IRQ_START 24 +#define JAZZ_IRQ_END (24 + 9) +#define JAZZ_PARALLEL_IRQ (JAZZ_IRQ_START + 0) +#define JAZZ_FLOPPY_IRQ (JAZZ_IRQ_START + 1) +#define JAZZ_SOUND_IRQ (JAZZ_IRQ_START + 2) +#define JAZZ_VIDEO_IRQ (JAZZ_IRQ_START + 3) +#define JAZZ_ETHERNET_IRQ (JAZZ_IRQ_START + 4) +#define JAZZ_SCSI_IRQ (JAZZ_IRQ_START + 5) +#define JAZZ_KEYBOARD_IRQ (JAZZ_IRQ_START + 6) +#define JAZZ_MOUSE_IRQ (JAZZ_IRQ_START + 7) +#define JAZZ_SERIAL1_IRQ (JAZZ_IRQ_START + 8) +#define JAZZ_SERIAL2_IRQ (JAZZ_IRQ_START + 9) + +#define JAZZ_TIMER_IRQ (MIPS_CPU_IRQ_BASE+6) /* diff --git a/include/asm-mips/jazzdma.h b/include/asm-mips/jazzdma.h index 0a205b7..8bb37bb 100644 --- a/include/asm-mips/jazzdma.h +++ b/include/asm-mips/jazzdma.h @@ -7,7 +7,6 @@ /* * Prototypes and macros */ -extern void vdma_init(void); extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size); extern int vdma_free(unsigned long laddr); extern int vdma_remap(unsigned long laddr, unsigned long paddr, diff --git a/include/asm-mips/mach-jazz/mc146818rtc.h b/include/asm-mips/mach-jazz/mc146818rtc.h index f44fdba..987f727 100644 --- a/include/asm-mips/mach-jazz/mc146818rtc.h +++ b/include/asm-mips/mach-jazz/mc146818rtc.h @@ -4,12 +4,15 @@ * for more details. * * Copyright (C) 1998, 2001, 03 by Ralf Baechle + * Copyright (C) 2007 Thomas Bogendoerfer * * RTC routines for Jazz style attached Dallas chip. */ #ifndef __ASM_MACH_JAZZ_MC146818RTC_H #define __ASM_MACH_JAZZ_MC146818RTC_H +#include + #include #include @@ -19,16 +22,17 @@ static inline unsigned char CMOS_READ(unsigned long addr) { outb_p(addr, RTC_PORT(0)); - - return *(char *)JAZZ_RTC_BASE; + return *(volatile char *)JAZZ_RTC_BASE; } static inline void CMOS_WRITE(unsigned char data, unsigned long addr) { outb_p(addr, RTC_PORT(0)); - *(char *)JAZZ_RTC_BASE = data; + *(volatile char *)JAZZ_RTC_BASE = data; } #define RTC_ALWAYS_BCD 0 +#define mc146818_decode_year(year) ((year) + 1980) + #endif /* __ASM_MACH_JAZZ_MC146818RTC_H */ -- cgit v0.10.2 From 1c0c13eb935c95fd2ca0b0aca6dd4860487fb242 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 25 Sep 2007 15:40:12 +0200 Subject: [MIPS] Add support for BCM47XX CPUs. Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch Cc: Felix Fietkau Cc: Florian Schirmer Signed-off-by: Aurelien Jarno Signed-off-by: Andrew Morton Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a8bdc08..6648f9b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -44,6 +44,20 @@ config BASLER_EXCITE_PROTOTYPE note that a kernel built with this option selected will not be able to run on normal units. +config BCM47XX + bool "BCM47XX based boards" + select DMA_NONCOHERENT + select HW_HAS_PCI + select IRQ_CPU + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SSB + select SSB_DRIVER_MIPS + select GENERIC_GPIO + help + Support for BCM47XX based boards + config MIPS_COBALT bool "Cobalt Server" select DMA_NONCOHERENT diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 6dcdbfb..7b936ed 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -535,6 +535,13 @@ libs-$(CONFIG_SIBYTE_BIGSUR) += arch/mips/sibyte/swarm/ load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000 # +# Broadcom BCM47XX boards +# +core-$(CONFIG_BCM47XX) += arch/mips/bcm47xx/ +cflags-$(CONFIG_BCM47XX) += -Iinclude/asm-mips/mach-bcm47xx +load-$(CONFIG_BCM47XX) := 0xffffffff80001000 + +# # SNI RM # core-$(CONFIG_SNI_RM) += arch/mips/sni/ diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile new file mode 100644 index 0000000..dc035f9 --- /dev/null +++ b/arch/mips/bcm47xx/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for the BCM47XX specific kernel interface routines +# under Linux. +# + +obj-y := irq.o prom.o serial.o setup.o time.o diff --git a/arch/mips/bcm47xx/irq.c b/arch/mips/bcm47xx/irq.c new file mode 100644 index 0000000..325757a --- /dev/null +++ b/arch/mips/bcm47xx/irq.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2004 Florian Schirmer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +void plat_irq_dispatch(void) +{ + u32 cause; + + cause = read_c0_cause() & read_c0_status() & CAUSEF_IP; + + clear_c0_status(cause); + + if (cause & CAUSEF_IP7) + do_IRQ(7); + if (cause & CAUSEF_IP2) + do_IRQ(2); + if (cause & CAUSEF_IP3) + do_IRQ(3); + if (cause & CAUSEF_IP4) + do_IRQ(4); + if (cause & CAUSEF_IP5) + do_IRQ(5); + if (cause & CAUSEF_IP6) + do_IRQ(6); +} + +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(); +} diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c new file mode 100644 index 0000000..41ac9dd --- /dev/null +++ b/arch/mips/bcm47xx/prom.c @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2004 Florian Schirmer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +const char *get_system_type(void) +{ + return "Broadcom BCM47XX"; +} + +void __init prom_init(void) +{ + unsigned long mem; + + /* Figure out memory size by finding aliases */ + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) { + if (*(unsigned long *)((unsigned long)(prom_init) + mem) == + *(unsigned long *)(prom_init)) + break; + } + + add_memory_region(0, mem, BOOT_MEM_RAM); +} + +void __init prom_free_prom_memory(void) +{ +} diff --git a/arch/mips/bcm47xx/serial.c b/arch/mips/bcm47xx/serial.c new file mode 100644 index 0000000..59c11af --- /dev/null +++ b/arch/mips/bcm47xx/serial.c @@ -0,0 +1,52 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 Aurelien Jarno + */ + +#include +#include +#include +#include +#include +#include + +static struct plat_serial8250_port uart8250_data[5]; + +static struct platform_device uart8250_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = uart8250_data, + }, +}; + +static int __init uart8250_init(void) +{ + int i; + struct ssb_mipscore *mcore = &(ssb_bcm47xx.mipscore); + + memset(&uart8250_data, 0, sizeof(uart8250_data)); + + for (i = 0; i < mcore->nr_serial_ports; i++) { + struct plat_serial8250_port *p = &(uart8250_data[i]); + struct ssb_serial_port *ssb_port = &(mcore->serial_ports[i]); + + p->mapbase = (unsigned int) ssb_port->regs; + p->membase = (void *) ssb_port->regs; + p->irq = ssb_port->irq + 2; + p->uartclk = ssb_port->baud_base; + p->regshift = ssb_port->reg_shift; + p->iotype = UPIO_MEM; + p->flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; + } + return platform_device_register(&uart8250_device); +} + +module_init(uart8250_init); + +MODULE_AUTHOR("Aurelien Jarno "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("8250 UART probe driver for the BCM47XX platforms"); diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c new file mode 100644 index 0000000..dfc580a --- /dev/null +++ b/arch/mips/bcm47xx/setup.c @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2004 Florian Schirmer + * Copyright (C) 2005 Waldemar Brodkorb + * Copyright (C) 2006 Felix Fietkau + * Copyright (C) 2006 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include + +struct ssb_bus ssb_bcm47xx; +EXPORT_SYMBOL(ssb_bcm47xx); + +static void bcm47xx_machine_restart(char *command) +{ + printk(KERN_ALERT "Please stand by while rebooting the system...\n"); + local_irq_disable(); + /* Set the watchdog timer to reset immediately */ + ssb_chipco_watchdog_timer_set(&ssb_bcm47xx.chipco, 1); + while (1) + cpu_relax(); +} + +static void bcm47xx_machine_halt(void) +{ + /* Disable interrupts and watchdog and spin forever */ + local_irq_disable(); + ssb_chipco_watchdog_timer_set(&ssb_bcm47xx.chipco, 0); + while (1) + cpu_relax(); +} + +static int bcm47xx_get_invariants(struct ssb_bus *bus, + struct ssb_init_invariants *iv) +{ + /* TODO: fill ssb_init_invariants using boardtype/boardrev + * CFE environment variables. + */ + return 0; +} + +void __init plat_mem_setup(void) +{ + int err; + + err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE, + bcm47xx_get_invariants); + if (err) + panic("Failed to initialize SSB bus (err %d)\n", err); + + _machine_restart = bcm47xx_machine_restart; + _machine_halt = bcm47xx_machine_halt; + pm_power_off = bcm47xx_machine_halt; + board_time_init = bcm47xx_time_init; +} + diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c new file mode 100644 index 0000000..b27d07f --- /dev/null +++ b/arch/mips/bcm47xx/time.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2004 Florian Schirmer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + + +#include +#include +#include +#include + +void __init +bcm47xx_time_init(void) +{ + unsigned long hz; + + /* + * Use deterministic values for initial counter interrupt + * so that calibrate delay avoids encountering a counter wrap. + */ + write_c0_count(0); + write_c0_compare(0xffff); + + hz = ssb_cpu_clock(&ssb_bcm47xx.mipscore) / 2; + if (!hz) + hz = 100000000; + + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */ + mips_hpt_frequency = hz; +} + +void __init +plat_timer_setup(struct irqaction *irq) +{ + /* Enable the timer interrupt */ + setup_irq(7, irq); +} diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 3e00416..97c0386 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -159,6 +159,7 @@ static inline void check_wait(void) case CPU_5KC: case CPU_25KF: case CPU_PR4450: + case CPU_BCM3302: cpu_wait = r4k_wait; break; @@ -793,6 +794,22 @@ static inline void cpu_probe_philips(struct cpuinfo_mips *c) } +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c) +{ + decode_configs(c); + switch (c->processor_id & 0xff00) { + case PRID_IMP_BCM3302: + c->cputype = CPU_BCM3302; + break; + case PRID_IMP_BCM4710: + c->cputype = CPU_BCM4710; + break; + default: + c->cputype = CPU_UNKNOWN; + break; + } +} + __init void cpu_probe(void) { struct cpuinfo_mips *c = ¤t_cpu_data; @@ -815,6 +832,9 @@ __init void cpu_probe(void) case PRID_COMP_SIBYTE: cpu_probe_sibyte(c); break; + case PRID_COMP_BROADCOM: + cpu_probe_broadcom(c); + break; case PRID_COMP_SANDCRAFT: cpu_probe_sandcraft(c); break; diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index ec04f5a..accd520 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -82,6 +82,8 @@ static const char *cpu_name[] = { [CPU_VR4181] = "NEC VR4181", [CPU_VR4181A] = "NEC VR4181A", [CPU_SR71000] = "Sandcraft SR71000", + [CPU_BCM3302] = "Broadcom BCM3302", + [CPU_BCM4710] = "Broadcom BCM4710", [CPU_PR4450] = "Philips PR4450", [CPU_LOONGSON2] = "ICT Loongson-2", }; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 6c425b0..b2c6b9e 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -908,6 +908,8 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, case CPU_4KSC: case CPU_20KC: case CPU_25KF: + case CPU_BCM3302: + case CPU_BCM4710: case CPU_LOONGSON2: if (m4kc_tlbp_war()) i_nop(p); diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index 1bb4bf6..efa8158 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -215,6 +215,12 @@ #define MACH_GROUP_WINDRIVER 28 /* Windriver boards */ #define MACH_WRPPMC 1 +/* + * Valid machtype for group Broadcom + */ +#define MACH_GROUP_BRCM 23 /* Broadcom */ +#define MACH_BCM47XX 1 /* Broadcom BCM47XX */ + #define CL_SIZE COMMAND_LINE_SIZE const char *get_system_type(void); diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 3857358..d67f43b 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -106,6 +106,13 @@ #define PRID_IMP_SR71000 0x0400 /* + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM + */ + +#define PRID_IMP_BCM4710 0x4000 +#define PRID_IMP_BCM3302 0x9000 + +/* * Definitions for 7:0 on legacy processors */ @@ -217,8 +224,9 @@ #define CPU_R14000 64 #define CPU_LOONGSON1 65 #define CPU_LOONGSON2 66 - -#define CPU_LAST 66 +#define CPU_BCM3302 67 +#define CPU_BCM4710 68 +#define CPU_LAST 68 /* * ISA Level encodings diff --git a/include/asm-mips/mach-bcm47xx/bcm47xx.h b/include/asm-mips/mach-bcm47xx/bcm47xx.h new file mode 100644 index 0000000..a2fb5e8 --- /dev/null +++ b/include/asm-mips/mach-bcm47xx/bcm47xx.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2007 Aurelien Jarno + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef __ASM_BCM47XX_H +#define __ASM_BCM47XX_H + +/* SSB bus */ +extern struct ssb_bus ssb_bcm47xx; + +extern void bcm47xx_time_init(void); + +#endif /* __ASM_BCM47XX_H */ -- cgit v0.10.2 From 4e45171c4e31578157189ca22cfb7b2bcc5f69f2 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 28 Aug 2007 09:03:01 +0000 Subject: [MIPS] cleanup struct irqaction initializers Signed-off-by: Thomas Gleixner CC: Ralf Baechle Signed-off-by: Ralf Baechle diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c index 950ad1e..48763cd 100644 --- a/arch/mips/cobalt/irq.c +++ b/arch/mips/cobalt/irq.c @@ -92,7 +92,9 @@ asmlinkage void plat_irq_dispatch(void) } static struct irqaction irq_via = { - no_action, 0, { { 0, } }, "cascade", NULL, NULL + .handler = no_action, + .mask = CPU_MASK_NONE, + .name = "cascade" }; void __init arch_init_irq(void) diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c index d9efe69..3a47e8c 100644 --- a/arch/mips/jmr3927/rbhma3100/irq.c +++ b/arch/mips/jmr3927/rbhma3100/irq.c @@ -104,7 +104,9 @@ static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id) } static struct irqaction ioc_action = { - jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL, + .handler = jmr3927_ioc_interrupt, + .mask = CPU_MASK_NONE, + .name = "IOC", }; static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) @@ -116,7 +118,9 @@ static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } static struct irqaction pcierr_action = { - jmr3927_pcierr_interrupt, 0, CPU_MASK_NONE, "PCI error", NULL, NULL, + .handler = jmr3927_pcierr_interrupt, + .mask = CPU_MASK_NONE, + .name = "PCI error", }; static void __init jmr3927_irq_init(void); diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index 4f4359b..6002164 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c @@ -303,7 +303,9 @@ void init_8259A(int auto_eoi) * IRQ2 is cascade interrupt to second interrupt controller */ static struct irqaction irq2 = { - no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL + .handler = no_action, + .mask = CPU_MASK_NONE, + .name = "cascade", }; static struct resource pic1_io_resource = { diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index fb9da9a..5bad1b7 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c @@ -117,10 +117,18 @@ static void inline flush_mace_bus(void) extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); -struct irqaction memerr_irq = { crime_memerr_intr, IRQF_DISABLED, - CPU_MASK_NONE, "CRIME memory error", NULL, NULL }; -struct irqaction cpuerr_irq = { crime_cpuerr_intr, IRQF_DISABLED, - CPU_MASK_NONE, "CRIME CPU error", NULL, NULL }; +struct irqaction memerr_irq = { + .handler = crime_memerr_intr, + .flags = IRQF_DISABLED, + .mask = CPU_MASK_NONE, + .name = "CRIME memory error", +}; +struct irqaction cpuerr_irq = { + .handler = crime_cpuerr_intr, + .flags = IRQF_DISABLED, + .mask = CPU_MASK_NONE, + .name = "CRIME CPU error", +}; /* * For interrupts wired from a single device to the CPU. Only the clock diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c index 9607ad5..5512356 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c @@ -243,10 +243,12 @@ int toshiba_rbtx4927_irq_nested(int sw_irq) return (sw_irq); } -//#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL } -#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, IRQF_SHARED, CPU_MASK_NONE, s, NULL, NULL } -static struct irqaction toshiba_rbtx4927_irq_ioc_action = -TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME); +static struct irqaction toshiba_rbtx4927_irq_ioc_action = { + .handler = no_action, + .flags = IRQF_SHARED, + .mask = CPU_MASK_NONE, + .name = TOSHIBA_RBTX4927_IOC_NAME +}; /**********************************************************************************/ -- cgit v0.10.2 From a02eb8da02741f43efb6f06adf534f9f2b913d80 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Tue, 28 Aug 2007 00:28:09 +0900 Subject: [MIPS] tx4927: Cleanup unused macros and non-standard IO accessors. This patch removes many unused constants, replaces non-standard IO accessors with standard ones, and kills terrible tx4927_mips.h file. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle diff --git a/arch/mips/tx4927/common/tx4927_dbgio.c b/arch/mips/tx4927/common/tx4927_dbgio.c index 09bdf2b..d8423e0 100644 --- a/arch/mips/tx4927/common/tx4927_dbgio.c +++ b/arch/mips/tx4927/common/tx4927_dbgio.c @@ -31,7 +31,6 @@ #include #include -#include u8 getDebugChar(void) { diff --git a/arch/mips/tx4927/common/tx4927_prom.c b/arch/mips/tx4927/common/tx4927_prom.c index 7d4cbf5..6eed53d 100644 --- a/arch/mips/tx4927/common/tx4927_prom.c +++ b/arch/mips/tx4927/common/tx4927_prom.c @@ -38,7 +38,7 @@ #include #include -static unsigned int __init tx4927_process_sdccr(u64 * addr) +static unsigned int __init tx4927_process_sdccr(unsigned long addr) { u64 val; unsigned int sdccr_ce; @@ -52,7 +52,7 @@ static unsigned int __init tx4927_process_sdccr(u64 * addr) unsigned int mw = 0; unsigned int msize = 0; - val = (*((vu64 *) (addr))); + val = __raw_readq((void __iomem *)addr); /* MVMCP -- need #defs for these bits masks */ sdccr_ce = ((val & (1 << 10)) >> 10); @@ -136,10 +136,10 @@ unsigned int __init tx4927_get_mem_size(void) unsigned int total; /* MVMCP -- need #defs for these registers */ - c0 = tx4927_process_sdccr((u64 *) 0xff1f8000); - c1 = tx4927_process_sdccr((u64 *) 0xff1f8008); - c2 = tx4927_process_sdccr((u64 *) 0xff1f8010); - c3 = tx4927_process_sdccr((u64 *) 0xff1f8018); + c0 = tx4927_process_sdccr(0xff1f8000); + c1 = tx4927_process_sdccr(0xff1f8008); + c2 = tx4927_process_sdccr(0xff1f8010); + c3 = tx4927_process_sdccr(0xff1f8018); total = c0 + c1 + c2 + c3; return (total); diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c index c8e49fe..b18ed58 100644 --- a/arch/mips/tx4927/common/tx4927_setup.c +++ b/arch/mips/tx4927/common/tx4927_setup.c @@ -124,10 +124,10 @@ dump_cp0(char *key) return; } -void print_pic(char *key, u32 reg, char *name) +void print_pic(char *key, unsigned long reg, char *name) { - printk("%s pic:0x%08x:%s=0x%08x\n", key, reg, name, - TX4927_RD(reg)); + printk(KERN_INFO "%s pic:0x%08lx:%s=0x%08x\n", key, reg, name, + __raw_readl((void __iomem *)reg)); return; } @@ -166,9 +166,10 @@ void dump_pic(char *key) } -void print_addr(char *hdr, char *key, u32 addr) +void print_addr(char *hdr, char *key, unsigned long addr) { - printk("%s %s:0x%08x=0x%08x\n", hdr, key, addr, TX4927_RD(addr)); + printk(KERN_INFO "%s %s:0x%08lx=0x%08x\n", hdr, key, addr, + __raw_readl((void __iomem *)addr)); return; } diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c index 5512356..305eb12 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c @@ -204,8 +204,8 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { .mask_ack = toshiba_rbtx4927_irq_ioc_disable, .unmask = toshiba_rbtx4927_irq_ioc_enable, }; -#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000 -#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006 +#define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL +#define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL u32 bit2num(u32 num) @@ -224,7 +224,7 @@ int toshiba_rbtx4927_irq_nested(int sw_irq) { u32 level3; - level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; + level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; if (level3) { sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3); if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) { @@ -288,9 +288,9 @@ static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) panic("\n"); } - v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); + v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); - TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); + writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); } @@ -308,9 +308,10 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) panic("\n"); } - v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); + v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); - TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); + writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); + mmiowb(); } @@ -387,12 +388,12 @@ void toshiba_rbtx4927_irq_dump_pics(char *s) level1_m = level0_m; level1_s = level0_s & 0x87; - level2 = TX4927_RD(0xff1ff6a0); + level2 = __raw_readl((void __iomem *)0xff1ff6a0UL); level2_p = (((level2 & 0x10000)) ? 0 : 1); level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f)); - level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f; - level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; + level3_m = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f; + level3_s = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; level4_m = inb(0x21); outb(0x0A, 0x20); diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c index 3e84237..4f30206 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c @@ -679,25 +679,30 @@ void __init tx4927_pci_setup(void) #endif /* CONFIG_PCI */ +static void __noreturn wait_forever(void) +{ + while (1) + if (cpu_wait) + (*cpu_wait)(); +} + void toshiba_rbtx4927_restart(char *command) { printk(KERN_NOTICE "System Rebooting...\n"); /* enable the s/w reset register */ - reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET); + writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE); /* wait for enable to be seen */ - while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) & + while ((readb(RBTX4927_SW_RESET_ENABLE) & RBTX4927_SW_RESET_ENABLE_SET) == 0x00); /* do a s/w reset */ - reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET); + writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO); /* do something passive while waiting for reset */ local_irq_disable(); - while (1) - asm_wait(); - + wait_forever(); /* no return */ } @@ -706,9 +711,7 @@ void toshiba_rbtx4927_halt(void) { printk(KERN_NOTICE "System Halted\n"); local_irq_disable(); - while (1) { - asm_wait(); - } + wait_forever(); /* no return */ } @@ -720,7 +723,7 @@ void toshiba_rbtx4927_power_off(void) void __init toshiba_rbtx4927_setup(void) { - vu32 cp0_config; + u32 cp0_config; char *argptr; printk("CPU is %s\n", toshiba_name); @@ -747,15 +750,6 @@ void __init toshiba_rbtx4927_setup(void) } #endif - /* setup serial stuff */ - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - ":Setting up tx4927 sio.\n"); - TX4927_WR(0xff1ff314, 0x00000000); /* h/w flow control off */ - TX4927_WR(0xff1ff414, 0x00000000); /* h/w flow control off */ - - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - "+\n"); - set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, ":mips_io_port_base=0x%08lx\n", diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h index a606495..b188a65 100644 --- a/include/asm-mips/tx4927/toshiba_rbtx4927.h +++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h @@ -28,24 +28,20 @@ #define __ASM_TX4927_TOSHIBA_RBTX4927_H #include -#include #ifdef CONFIG_PCI #include #endif -#define TOSHIBA_RBTX4927_WR08(a,b) do { TX4927_WR08(a,b); wbflush(); } while ( 0 ) - - #ifdef CONFIG_PCI #define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO #else #define TBTX4927_ISA_IO_OFFSET 0 #endif -#define RBTX4927_SW_RESET_DO 0xbc00f000 +#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL #define RBTX4927_SW_RESET_DO_SET 0x01 -#define RBTX4927_SW_RESET_ENABLE 0xbc00f002 +#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL #define RBTX4927_SW_RESET_ENABLE_SET 0x01 diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h index 4bd4368..193e80a 100644 --- a/include/asm-mips/tx4927/tx4927.h +++ b/include/asm-mips/tx4927/tx4927.h @@ -27,447 +27,8 @@ #ifndef __ASM_TX4927_TX4927_H #define __ASM_TX4927_TX4927_H -#include #include -/* - This register naming came from the integrated CPU/controller name TX4927 - followed by the device name from table 4.2.2 on page 4-3 and then followed - by the register name from table 4.2.3 on pages 4-4 to 4-8. The manaul - used was "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001". - */ - -#define TX4927_SIO_0_BASE - -/* TX4927 controller */ -#define TX4927_BASE 0xfff1f0000 -#define TX4927_BASE 0xfff1f0000 -#define TX4927_LIMIT 0xfff1fffff - - -/* TX4927 SDRAM controller (64-bit registers) */ -#define TX4927_SDRAMC_BASE 0x8000 -#define TX4927_SDRAMC_SDCCR0 0x8000 -#define TX4927_SDRAMC_SDCCR1 0x8008 -#define TX4927_SDRAMC_SDCCR2 0x8010 -#define TX4927_SDRAMC_SDCCR3 0x8018 -#define TX4927_SDRAMC_SDCTR 0x8040 -#define TX4927_SDRAMC_SDCMD 0x8058 -#define TX4927_SDRAMC_LIMIT 0x8fff - - -/* TX4927 external bus controller (64-bit registers) */ -#define TX4927_EBUSC_BASE 0x9000 -#define TX4927_EBUSC_EBCCR0 0x9000 -#define TX4927_EBUSC_EBCCR1 0x9008 -#define TX4927_EBUSC_EBCCR2 0x9010 -#define TX4927_EBUSC_EBCCR3 0x9018 -#define TX4927_EBUSC_EBCCR4 0x9020 -#define TX4927_EBUSC_EBCCR5 0x9028 -#define TX4927_EBUSC_EBCCR6 0x9030 -#define TX4927_EBUSC_EBCCR7 0x9008 -#define TX4927_EBUSC_LIMIT 0x9fff - - -/* TX4927 SDRRAM Error Check Correction (64-bit registers) */ -#define TX4927_ECC_BASE 0xa000 -#define TX4927_ECC_ECCCR 0xa000 -#define TX4927_ECC_ECCSR 0xa008 -#define TX4927_ECC_LIMIT 0xafff - - -/* TX4927 DMA Controller (64-bit registers) */ -#define TX4927_DMAC_BASE 0xb000 -#define TX4927_DMAC_TBD 0xb000 -#define TX4927_DMAC_LIMIT 0xbfff - - -/* TX4927 PCI Controller (32-bit registers) */ -#define TX4927_PCIC_BASE 0xd000 -#define TX4927_PCIC_TBD 0xb000 -#define TX4927_PCIC_LIMIT 0xdfff - - -/* TX4927 Configuration registers (64-bit registers) */ -#define TX4927_CONFIG_BASE 0xe000 -#define TX4927_CONFIG_CCFG 0xe000 -#define TX4927_CONFIG_CCFG_RESERVED_42_63 BM_63_42 -#define TX4927_CONFIG_CCFG_WDRST BM_41_41 -#define TX4927_CONFIG_CCFG_WDREXEN BM_40_40 -#define TX4927_CONFIG_CCFG_BCFG BM_39_32 -#define TX4927_CONFIG_CCFG_RESERVED_27_31 BM_31_27 -#define TX4927_CONFIG_CCFG_GTOT BM_26_25 -#define TX4927_CONFIG_CCFG_GTOT_4096 BM_26_25 -#define TX4927_CONFIG_CCFG_GTOT_2048 BM_26_26 -#define TX4927_CONFIG_CCFG_GTOT_1024 BM_25_25 -#define TX4927_CONFIG_CCFG_GTOT_0512 (~BM_26_25) -#define TX4927_CONFIG_CCFG_TINTDIS BM_24_24 -#define TX4927_CONFIG_CCFG_PCI66 BM_23_23 -#define TX4927_CONFIG_CCFG_PCIMODE BM_22_22 -#define TX4927_CONFIG_CCFG_RESERVED_20_21 BM_21_20 -#define TX4927_CONFIG_CCFG_DIVMODE BM_19_17 -#define TX4927_CONFIG_CCFG_DIVMODE_2_0 BM_19_19 -#define TX4927_CONFIG_CCFG_DIVMODE_3_0 (BM_19_19|BM_17_17) -#define TX4927_CONFIG_CCFG_DIVMODE_4_0 BM_19_18 -#define TX4927_CONFIG_CCFG_DIVMODE_2_5 BM_19_17 -#define TX4927_CONFIG_CCFG_DIVMODE_8_0 (~BM_19_17) -#define TX4927_CONFIG_CCFG_DIVMODE_12_0 BM_17_17 -#define TX4927_CONFIG_CCFG_DIVMODE_16_0 BM_18_18 -#define TX4927_CONFIG_CCFG_DIVMODE_10_0 BM_18_17 -#define TX4927_CONFIG_CCFG_BEOW BM_16_16 -#define TX4927_CONFIG_CCFG_WR BM_15_15 -#define TX4927_CONFIG_CCFG_TOE BM_14_14 -#define TX4927_CONFIG_CCFG_PCIARB BM_13_13 -#define TX4927_CONFIG_CCFG_PCIDIVMODE BM_12_11 -#define TX4927_CONFIG_CCFG_RESERVED_08_10 BM_10_08 -#define TX4927_CONFIG_CCFG_SYSSP BM_07_06 -#define TX4927_CONFIG_CCFG_RESERVED_03_05 BM_05_03 -#define TX4927_CONFIG_CCFG_ENDIAN BM_02_02 -#define TX4927_CONFIG_CCFG_ARMODE BM_01_01 -#define TX4927_CONFIG_CCFG_ACEHOLD BM_00_00 -#define TX4927_CONFIG_REVID 0xe008 -#define TX4927_CONFIG_REVID_RESERVED_32_63 BM_32_63 -#define TX4927_CONFIG_REVID_PCODE BM_16_31 -#define TX4927_CONFIG_REVID_MJERREV BM_12_15 -#define TX4927_CONFIG_REVID_MINEREV BM_08_11 -#define TX4927_CONFIG_REVID_MJREV BM_04_07 -#define TX4927_CONFIG_REVID_MINREV BM_00_03 -#define TX4927_CONFIG_PCFG 0xe010 -#define TX4927_CONFIG_PCFG_RESERVED_57_63 BM_57_63 -#define TX4927_CONFIG_PCFG_DRVDATA BM_56_56 -#define TX4927_CONFIG_PCFG_DRVCB BM_55_55 -#define TX4927_CONFIG_PCFG_DRVDQM BM_54_54 -#define TX4927_CONFIG_PCFG_DRVADDR BM_53_53 -#define TX4927_CONFIG_PCFG_DRVCKE BM_52_52 -#define TX4927_CONFIG_PCFG_DRVRAS BM_51_51 -#define TX4927_CONFIG_PCFG_DRVCAS BM_50_50 -#define TX4927_CONFIG_PCFG_DRVWE BM_49_49 -#define TX4927_CONFIG_PCFG_DRVCS3 BM_48_48 -#define TX4927_CONFIG_PCFG_DRVCS2 BM_47_47 -#define TX4927_CONFIG_PCFG_DRVCS1 BM_46_4k -#define TX4927_CONFIG_PCFG_DRVCS0 BM_45_45 -#define TX4927_CONFIG_PCFG_DRVCK3 BM_44_44 -#define TX4927_CONFIG_PCFG_DRVCK2 BM_43_43 -#define TX4927_CONFIG_PCFG_DRVCK1 BM_42_42 -#define TX4927_CONFIG_PCFG_DRVCK0 BM_41_41 -#define TX4927_CONFIG_PCFG_DRVCKIN BM_40_40 -#define TX4927_CONFIG_PCFG_RESERVED_33_39 BM_33_39 -#define TX4927_CONFIG_PCFG_BYPASS_PLL BM_32_32 -#define TX4927_CONFIG_PCFG_RESERVED_30_31 BM_30_31 -#define TX4927_CONFIG_PCFG_SDCLKDLY BM_28_29 -#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_1 (~BM_28_29) -#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_2 BM_28_28 -#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_3 BM_29_29 -#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_4 BM_28_29 -#define TX4927_CONFIG_PCFG_SYSCLKEN BM_27_27 -#define TX4927_CONFIG_PCFG_SDCLKEN3 BM_26_26 -#define TX4927_CONFIG_PCFG_SDCLKEN2 BM_25_25 -#define TX4927_CONFIG_PCFG_SDCLKEN1 BM_24_24 -#define TX4927_CONFIG_PCFG_SDCLKEN0 BM_23_23 -#define TX4927_CONFIG_PCFG_SDCLKINEN BM_22_22 -#define TX4927_CONFIG_PCFG_PCICLKEN5 BM_21_21 -#define TX4927_CONFIG_PCFG_PCICLKEN4 BM_20_20 -#define TX4927_CONFIG_PCFG_PCICLKEN3 BM_19_19 -#define TX4927_CONFIG_PCFG_PCICLKEN2 BM_18_18 -#define TX4927_CONFIG_PCFG_PCICLKEN1 BM_17_17 -#define TX4927_CONFIG_PCFG_PCICLKEN0 BM_16_16 -#define TX4927_CONFIG_PCFG_RESERVED_10_15 BM_10_15 -#define TX4927_CONFIG_PCFG_SEL2 BM_09_09 -#define TX4927_CONFIG_PCFG_SEL1 BM_08_08 -#define TX4927_CONFIG_PCFG_DMASEL3 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL3_DMAREQ3 (~BM_06_07) -#define TX4927_CONFIG_PCFG_DMASEL3_SIO0 BM_06_06 -#define TX4927_CONFIG_PCFG_DMASEL3_ACLC3 BM_07_07 -#define TX4927_CONFIG_PCFG_DMASEL3_ACLC1 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL2 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_DMAREQ2 (~BM_06_07) -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_SIO0 BM_06_06 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_10 BM_07_07 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_11 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC1 (~BM_06_07) -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_SIO0 BM_06_06 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC2 BM_07_07 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC0 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL1 BM_02_03 -#define TX4927_CONFIG_PCFG_DMASEL1_DMAREQ1 (~BM_02_03) -#define TX4927_CONFIG_PCFG_DMASEL1_SIO1 BM_02_02 -#define TX4927_CONFIG_PCFG_DMASEL1_ACLC1 BM_03_03 -#define TX4927_CONFIG_PCFG_DMASEL1_ACLC3 BM_02_03 -#define TX4927_CONFIG_PCFG_DMASEL0 BM_00_01 -#define TX4927_CONFIG_PCFG_DMASEL0_DMAREQ0 (~BM_00_01) -#define TX4927_CONFIG_PCFG_DMASEL0_SIO1 BM_00_00 -#define TX4927_CONFIG_PCFG_DMASEL0_ACLC0 BM_01_01 -#define TX4927_CONFIG_PCFG_DMASEL0_ACLC2 BM_00_01 -#define TX4927_CONFIG_TOEA 0xe018 -#define TX4927_CONFIG_TOEA_RESERVED_36_63 BM_36_63 -#define TX4927_CONFIG_TOEA_TOEA BM_00_35 -#define TX4927_CONFIG_CLKCTR 0xe020 -#define TX4927_CONFIG_CLKCTR_RESERVED_26_63 BM_26_63 -#define TX4927_CONFIG_CLKCTR_ACLCKD BM_25_25 -#define TX4927_CONFIG_CLKCTR_PIOCKD BM_24_24 -#define TX4927_CONFIG_CLKCTR_DMACKD BM_23_23 -#define TX4927_CONFIG_CLKCTR_PCICKD BM_22_22 -#define TX4927_CONFIG_CLKCTR_SET_21 BM_21_21 -#define TX4927_CONFIG_CLKCTR_TM0CKD BM_20_20 -#define TX4927_CONFIG_CLKCTR_TM1CKD BM_19_19 -#define TX4927_CONFIG_CLKCTR_TM2CKD BM_18_18 -#define TX4927_CONFIG_CLKCTR_SIO0CKD BM_17_17 -#define TX4927_CONFIG_CLKCTR_SIO1CKD BM_16_16 -#define TX4927_CONFIG_CLKCTR_RESERVED_10_15 BM_10_15 -#define TX4927_CONFIG_CLKCTR_ACLRST BM_09_09 -#define TX4927_CONFIG_CLKCTR_PIORST BM_08_08 -#define TX4927_CONFIG_CLKCTR_DMARST BM_07_07 -#define TX4927_CONFIG_CLKCTR_PCIRST BM_06_06 -#define TX4927_CONFIG_CLKCTR_RESERVED_05_05 BM_05_05 -#define TX4927_CONFIG_CLKCTR_TM0RST BM_04_04 -#define TX4927_CONFIG_CLKCTR_TM1RST BM_03_03 -#define TX4927_CONFIG_CLKCTR_TM2RST BM_02_02 -#define TX4927_CONFIG_CLKCTR_SIO0RST BM_01_01 -#define TX4927_CONFIG_CLKCTR_SIO1RST BM_00_00 -#define TX4927_CONFIG_GARBC 0xe030 -#define TX4927_CONFIG_GARBC_RESERVED_10_63 BM_10_63 -#define TX4927_CONFIG_GARBC_SET_09 BM_09_09 -#define TX4927_CONFIG_GARBC_ARBMD BM_08_08 -#define TX4927_CONFIG_GARBC_RESERVED_06_07 BM_06_07 -#define TX4927_CONFIG_GARBC_PRIORITY_H1 BM_04_05 -#define TX4927_CONFIG_GARBC_PRIORITY_H1_PCI (~BM_04_05) -#define TX4927_CONFIG_GARBC_PRIORITY_H1_PDMAC BM_04_04 -#define TX4927_CONFIG_GARBC_PRIORITY_H1_DMAC BM_05_05 -#define TX4927_CONFIG_GARBC_PRIORITY_H1_BAD_VALUE BM_04_05 -#define TX4927_CONFIG_GARBC_PRIORITY_H2 BM_02_03 -#define TX4927_CONFIG_GARBC_PRIORITY_H2_PCI (~BM_02_03) -#define TX4927_CONFIG_GARBC_PRIORITY_H2_PDMAC BM_02_02 -#define TX4927_CONFIG_GARBC_PRIORITY_H2_DMAC BM_03_03 -#define TX4927_CONFIG_GARBC_PRIORITY_H2_BAD_VALUE BM_02_03 -#define TX4927_CONFIG_GARBC_PRIORITY_H3 BM_00_01 -#define TX4927_CONFIG_GARBC_PRIORITY_H3_PCI (~BM_00_01) -#define TX4927_CONFIG_GARBC_PRIORITY_H3_PDMAC BM_00_00 -#define TX4927_CONFIG_GARBC_PRIORITY_H3_DMAC BM_01_01 -#define TX4927_CONFIG_GARBC_PRIORITY_H3_BAD_VALUE BM_00_01 -#define TX4927_CONFIG_RAMP 0xe048 -#define TX4927_CONFIG_RAMP_RESERVED_20_63 BM_20_63 -#define TX4927_CONFIG_RAMP_RAMP BM_00_19 -#define TX4927_CONFIG_LIMIT 0xefff - - -/* TX4927 Timer 0 (32-bit registers) */ -#define TX4927_TMR0_BASE 0xf000 -#define TX4927_TMR0_TMTCR0 0xf000 -#define TX4927_TMR0_TMTISR0 0xf004 -#define TX4927_TMR0_TMCPRA0 0xf008 -#define TX4927_TMR0_TMCPRB0 0xf00c -#define TX4927_TMR0_TMITMR0 0xf010 -#define TX4927_TMR0_TMCCDR0 0xf020 -#define TX4927_TMR0_TMPGMR0 0xf030 -#define TX4927_TMR0_TMTRR0 0xf0f0 -#define TX4927_TMR0_LIMIT 0xf0ff - - -/* TX4927 Timer 1 (32-bit registers) */ -#define TX4927_TMR1_BASE 0xf100 -#define TX4927_TMR1_TMTCR1 0xf100 -#define TX4927_TMR1_TMTISR1 0xf104 -#define TX4927_TMR1_TMCPRA1 0xf108 -#define TX4927_TMR1_TMCPRB1 0xf10c -#define TX4927_TMR1_TMITMR1 0xf110 -#define TX4927_TMR1_TMCCDR1 0xf120 -#define TX4927_TMR1_TMPGMR1 0xf130 -#define TX4927_TMR1_TMTRR1 0xf1f0 -#define TX4927_TMR1_LIMIT 0xf1ff - - -/* TX4927 Timer 2 (32-bit registers) */ -#define TX4927_TMR2_BASE 0xf200 -#define TX4927_TMR2_TMTCR2 0xf200 -#define TX4927_TMR2_TMTISR2 0xf204 -#define TX4927_TMR2_TMCPRA2 0xf208 -#define TX4927_TMR2_TMITMR2 0xf210 -#define TX4927_TMR2_TMCCDR2 0xf220 -#define TX4927_TMR2_TMWTMR2 0xf240 -#define TX4927_TMR2_TMTRR2 0xf2f0 -#define TX4927_TMR2_LIMIT 0xf2ff - - -/* TX4927 serial port 0 (32-bit registers) */ -#define TX4927_SIO0_BASE 0xf300 -#define TX4927_SIO0_SILCR0 0xf300 -#define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31 -#define TX4927_SIO0_SILCR0_RWUB BM_15_15 -#define TX4927_SIO0_SILCR0_TWUB BM_14_14 -#define TX4927_SIO0_SILCR0_UODE BM_13_13 -#define TX4927_SIO0_SILCR0_RESERVED_07_12 BM_07_12 -#define TX4927_SIO0_SILCR0_SCS BM_05_06 -#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_IC (~BM_05_06) -#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_BRG BM_05_05 -#define TX4927_SIO0_SILCR0_SCS_SCLK_EC BM_06_06 -#define TX4927_SIO0_SILCR0_SCS_SCLK_BRG BM_05_06 -#define TX4927_SIO0_SILCR0_UEPS BM_04_04 -#define TX4927_SIO0_SILCR0_UPEN BM_03_03 -#define TX4927_SIO0_SILCR0_USBL BM_02_02 -#define TX4927_SIO0_SILCR0_UMODE BM_00_01 -#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT BM_00_01 -#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01) -#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01 -#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01 -#define TX4927_SIO0_SIDICR0 0xf304 -#define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31 -#define TX4927_SIO0_SIDICR0_TDE BM_15_15 -#define TX4927_SIO0_SIDICR0_RDE BM_14_14 -#define TX4927_SIO0_SIDICR0_TIE BM_13_13 -#define TX4927_SIO0_SIDICR0_RIE BM_12_12 -#define TX4927_SIO0_SIDICR0_SPIE BM_11_11 -#define TX4927_SIO0_SIDICR0_CTSAC BM_09_10 -#define TX4927_SIO0_SIDICR0_CTSAC_NONE (~BM_09_10) -#define TX4927_SIO0_SIDICR0_CTSAC_RISE BM_09_09 -#define TX4927_SIO0_SIDICR0_CTSAC_FALL BM_10_10 -#define TX4927_SIO0_SIDICR0_CTSAC_BOTH BM_09_10 -#define TX4927_SIO0_SIDICR0_RESERVED_06_08 BM_06_08 -#define TX4927_SIO0_SIDICR0_STIE BM_00_05 -#define TX4927_SIO0_SIDICR0_STIE_NONE (~BM_00_05) -#define TX4927_SIO0_SIDICR0_STIE_OERS BM_05_05 -#define TX4927_SIO0_SIDICR0_STIE_CTSAC BM_04_04 -#define TX4927_SIO0_SIDICR0_STIE_RBRKD BM_03_03 -#define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02 -#define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01 -#define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00 -#define TX4927_SIO0_SIDISR0 0xf308 -#define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31 -#define TX4927_SIO0_SIDISR0_UBRK BM_15_15 -#define TX4927_SIO0_SIDISR0_UVALID BM_14_14 -#define TX4927_SIO0_SIDISR0_UFER BM_13_13 -#define TX4927_SIO0_SIDISR0_UPER BM_12_12 -#define TX4927_SIO0_SIDISR0_UOER BM_11_11 -#define TX4927_SIO0_SIDISR0_ERI BM_10_10 -#define TX4927_SIO0_SIDISR0_TOUT BM_09_09 -#define TX4927_SIO0_SIDISR0_TDIS BM_08_08 -#define TX4927_SIO0_SIDISR0_RDIS BM_07_07 -#define TX4927_SIO0_SIDISR0_STIS BM_06_06 -#define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05 -#define TX4927_SIO0_SIDISR0_RFDN BM_00_04 -#define TX4927_SIO0_SISCISR0 0xf30c -#define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31 -#define TX4927_SIO0_SISCISR0_OERS BM_05_05 -#define TX4927_SIO0_SISCISR0_CTSS BM_04_04 -#define TX4927_SIO0_SISCISR0_RBRKD BM_03_03 -#define TX4927_SIO0_SISCISR0_TRDY BM_02_02 -#define TX4927_SIO0_SISCISR0_TXALS BM_01_01 -#define TX4927_SIO0_SISCISR0_UBRKD BM_00_00 -#define TX4927_SIO0_SIFCR0 0xf310 -#define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31 -#define TX4927_SIO0_SIFCR0_SWRST BM_16_31 -#define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14 -#define TX4927_SIO0_SIFCR0_RDIL BM_16_31 -#define TX4927_SIO0_SIFCR0_RDIL_BYTES_1 (~BM_07_08) -#define TX4927_SIO0_SIFCR0_RDIL_BYTES_4 BM_07_07 -#define TX4927_SIO0_SIFCR0_RDIL_BYTES_8 BM_08_08 -#define TX4927_SIO0_SIFCR0_RDIL_BYTES_12 BM_07_08 -#define TX4927_SIO0_SIFCR0_RESERVED_05_06 BM_05_06 -#define TX4927_SIO0_SIFCR0_TDIL BM_03_04 -#define TX4927_SIO0_SIFCR0_TDIL_BYTES_1 (~BM_03_04) -#define TX4927_SIO0_SIFCR0_TDIL_BYTES_4 BM_03_03 -#define TX4927_SIO0_SIFCR0_TDIL_BYTES_8 BM_04_04 -#define TX4927_SIO0_SIFCR0_TDIL_BYTES_0 BM_03_04 -#define TX4927_SIO0_SIFCR0_TFRST BM_02_02 -#define TX4927_SIO0_SIFCR0_RFRST BM_01_01 -#define TX4927_SIO0_SIFCR0_FRSTE BM_00_00 -#define TX4927_SIO0_SIFLCR0 0xf314 -#define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31 -#define TX4927_SIO0_SIFLCR0_RCS BM_12_12 -#define TX4927_SIO0_SIFLCR0_TES BM_11_11 -#define TX4927_SIO0_SIFLCR0_RESERVED_10_10 BM_10_10 -#define TX4927_SIO0_SIFLCR0_RTSSC BM_09_09 -#define TX4927_SIO0_SIFLCR0_RSDE BM_08_08 -#define TX4927_SIO0_SIFLCR0_TSDE BM_07_07 -#define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06 -#define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04 -#define TX4927_SIO0_SIFLCR0_TBRK BM_00_00 -#define TX4927_SIO0_SIBGR0 0xf318 -#define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31 -#define TX4927_SIO0_SIBGR0_BCLK BM_08_09 -#define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09) -#define TX4927_SIO0_SIBGR0_BCLK_T2 BM_08_08 -#define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09 -#define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09 -#define TX4927_SIO0_SIBGR0_BRD BM_00_07 -#define TX4927_SIO0_SITFIF00 0xf31c -#define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31 -#define TX4927_SIO0_SITFIF00_TXD BM_00_07 -#define TX4927_SIO0_SIRFIFO0 0xf320 -#define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31 -#define TX4927_SIO0_SIRFIFO0_RXD BM_00_07 -#define TX4927_SIO0_SIRFIFO0 0xf320 -#define TX4927_SIO0_LIMIT 0xf3ff - - -/* TX4927 serial port 1 (32-bit registers) */ -#define TX4927_SIO1_BASE 0xf400 -#define TX4927_SIO1_SILCR1 0xf400 -#define TX4927_SIO1_SIDICR1 0xf404 -#define TX4927_SIO1_SIDISR1 0xf408 -#define TX4927_SIO1_SISCISR1 0xf40c -#define TX4927_SIO1_SIFCR1 0xf410 -#define TX4927_SIO1_SIFLCR1 0xf414 -#define TX4927_SIO1_SIBGR1 0xf418 -#define TX4927_SIO1_SITFIF01 0xf41c -#define TX4927_SIO1_SIRFIFO1 0xf420 -#define TX4927_SIO1_LIMIT 0xf4ff - - -/* TX4927 parallel port (32-bit registers) */ -#define TX4927_PIO_BASE 0xf500 -#define TX4927_PIO_PIOD0 0xf500 -#define TX4927_PIO_PIODI 0xf504 -#define TX4927_PIO_PIODIR 0xf508 -#define TX4927_PIO_PIOOD 0xf50c -#define TX4927_PIO_LIMIT 0xf50f - - -/* TX4927 AC-link controller (32-bit registers) */ -#define TX4927_ACLC_BASE 0xf700 -#define TX4927_ACLC_ACCTLEN 0xf700 -#define TX4927_ACLC_ACCTLDIS 0xf704 -#define TX4927_ACLC_ACREGACC 0xf708 -#define TX4927_ACLC_ACINTSTS 0xf710 -#define TX4927_ACLC_ACINTMSTS 0xf714 -#define TX4927_ACLC_ACINTEN 0xf718 -#define TX4927_ACLC_ACINTDIS 0xf71c -#define TX4927_ACLC_ACSEMAPH 0xf720 -#define TX4927_ACLC_ACGPIDAT 0xf740 -#define TX4927_ACLC_ACGPODAT 0xf744 -#define TX4927_ACLC_ACSLTEN 0xf748 -#define TX4927_ACLC_ACSLTDIS 0xf74c -#define TX4927_ACLC_ACFIFOSTS 0xf750 -#define TX4927_ACLC_ACDMASTS 0xf780 -#define TX4927_ACLC_ACDMASEL 0xf784 -#define TX4927_ACLC_ACAUDODAT 0xf7a0 -#define TX4927_ACLC_ACSURRDAT 0xf7a4 -#define TX4927_ACLC_ACCENTDAT 0xf7a8 -#define TX4927_ACLC_ACLFEDAT 0xf7ac -#define TX4927_ACLC_ACAUDIDAT 0xf7b0 -#define TX4927_ACLC_ACMODODAT 0xf7b8 -#define TX4927_ACLC_ACMODIDAT 0xf7bc -#define TX4927_ACLC_ACREVID 0xf7fc -#define TX4927_ACLC_LIMIT 0xf7ff - - -#define TX4927_REG(x) ((TX4927_BASE)+(x)) - -#define TX4927_RD08( reg ) (*(vu08*)(reg)) -#define TX4927_WR08( reg, val ) ((*(vu08*)(reg))=(val)) - -#define TX4927_RD16( reg ) (*(vu16*)(reg)) -#define TX4927_WR16( reg, val ) ((*(vu16*)(reg))=(val)) - -#define TX4927_RD32( reg ) (*(vu32*)(reg)) -#define TX4927_WR32( reg, val ) ((*(vu32*)(reg))=(val)) - -#define TX4927_RD64( reg ) (*(vu64*)(reg)) -#define TX4927_WR64( reg, val ) ((*(vu64*)(reg))=(val)) - -#define TX4927_RD( reg ) TX4927_RD32( reg ) -#define TX4927_WR( reg, val ) TX4927_WR32( reg, val ) - - #define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE #define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) diff --git a/include/asm-mips/tx4927/tx4927_mips.h b/include/asm-mips/tx4927/tx4927_mips.h deleted file mode 100644 index 242ab93..0000000 --- a/include/asm-mips/tx4927/tx4927_mips.h +++ /dev/null @@ -1,4177 +0,0 @@ -/* - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __ASM_TX4927_TX4927_MIPS_H -#define __ASM_TX4927_TX4927_MIPS_H - -#ifndef __ASSEMBLY__ - -static inline void asm_wait(void) -{ - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -#define reg_rd08(r) ((u8 )(*((vu8 *)(r)))) -#define reg_rd16(r) ((u16)(*((vu16*)(r)))) -#define reg_rd32(r) ((u32)(*((vu32*)(r)))) -#define reg_rd64(r) ((u64)(*((vu64*)(r)))) - -#define reg_wr08(r,v) ((*((vu8 *)(r)))=((u8 )(v))) -#define reg_wr16(r,v) ((*((vu16*)(r)))=((u16)(v))) -#define reg_wr32(r,v) ((*((vu32*)(r)))=((u32)(v))) -#define reg_wr64(r,v) ((*((vu64*)(r)))=((u64)(v))) - -typedef volatile __signed char vs8; -typedef volatile unsigned char vu8; - -typedef volatile __signed short vs16; -typedef volatile unsigned short vu16; - -typedef volatile __signed int vs32; -typedef volatile unsigned int vu32; - -typedef s8 s08; -typedef vs8 vs08; - -typedef u8 u08; -typedef vu8 vu08; - - -#if (_MIPS_SZLONG == 64) - -typedef volatile __signed__ long vs64; -typedef volatile unsigned long vu64; - -#else - -typedef volatile __signed__ long long vs64; -typedef volatile unsigned long long vu64; - -#endif - - -#define BM_00_00 0x0000000000000001 -#define BM_01_00 0x0000000000000003 -#define BM_00_01 BM_01_00 -#define BM_02_00 0x0000000000000007 -#define BM_00_02 BM_02_00 -#define BM_03_00 0x000000000000000f -#define BM_00_03 BM_03_00 -#define BM_04_00 0x000000000000001f -#define BM_00_04 BM_04_00 -#define BM_05_00 0x000000000000003f -#define BM_00_05 BM_05_00 -#define BM_06_00 0x000000000000007f -#define BM_00_06 BM_06_00 -#define BM_07_00 0x00000000000000ff -#define BM_00_07 BM_07_00 -#define BM_08_00 0x00000000000001ff -#define BM_00_08 BM_08_00 -#define BM_09_00 0x00000000000003ff -#define BM_00_09 BM_09_00 -#define BM_10_00 0x00000000000007ff -#define BM_00_10 BM_10_00 -#define BM_11_00 0x0000000000000fff -#define BM_00_11 BM_11_00 -#define BM_12_00 0x0000000000001fff -#define BM_00_12 BM_12_00 -#define BM_13_00 0x0000000000003fff -#define BM_00_13 BM_13_00 -#define BM_14_00 0x0000000000007fff -#define BM_00_14 BM_14_00 -#define BM_15_00 0x000000000000ffff -#define BM_00_15 BM_15_00 -#define BM_16_00 0x000000000001ffff -#define BM_00_16 BM_16_00 -#define BM_17_00 0x000000000003ffff -#define BM_00_17 BM_17_00 -#define BM_18_00 0x000000000007ffff -#define BM_00_18 BM_18_00 -#define BM_19_00 0x00000000000fffff -#define BM_00_19 BM_19_00 -#define BM_20_00 0x00000000001fffff -#define BM_00_20 BM_20_00 -#define BM_21_00 0x00000000003fffff -#define BM_00_21 BM_21_00 -#define BM_22_00 0x00000000007fffff -#define BM_00_22 BM_22_00 -#define BM_23_00 0x0000000000ffffff -#define BM_00_23 BM_23_00 -#define BM_24_00 0x0000000001ffffff -#define BM_00_24 BM_24_00 -#define BM_25_00 0x0000000003ffffff -#define BM_00_25 BM_25_00 -#define BM_26_00 0x0000000007ffffff -#define BM_00_26 BM_26_00 -#define BM_27_00 0x000000000fffffff -#define BM_00_27 BM_27_00 -#define BM_28_00 0x000000001fffffff -#define BM_00_28 BM_28_00 -#define BM_29_00 0x000000003fffffff -#define BM_00_29 BM_29_00 -#define BM_30_00 0x000000007fffffff -#define BM_00_30 BM_30_00 -#define BM_31_00 0x00000000ffffffff -#define BM_00_31 BM_31_00 -#define BM_32_00 0x00000001ffffffff -#define BM_00_32 BM_32_00 -#define BM_33_00 0x00000003ffffffff -#define BM_00_33 BM_33_00 -#define BM_34_00 0x00000007ffffffff -#define BM_00_34 BM_34_00 -#define BM_35_00 0x0000000fffffffff -#define BM_00_35 BM_35_00 -#define BM_36_00 0x0000001fffffffff -#define BM_00_36 BM_36_00 -#define BM_37_00 0x0000003fffffffff -#define BM_00_37 BM_37_00 -#define BM_38_00 0x0000007fffffffff -#define BM_00_38 BM_38_00 -#define BM_39_00 0x000000ffffffffff -#define BM_00_39 BM_39_00 -#define BM_40_00 0x000001ffffffffff -#define BM_00_40 BM_40_00 -#define BM_41_00 0x000003ffffffffff -#define BM_00_41 BM_41_00 -#define BM_42_00 0x000007ffffffffff -#define BM_00_42 BM_42_00 -#define BM_43_00 0x00000fffffffffff -#define BM_00_43 BM_43_00 -#define BM_44_00 0x00001fffffffffff -#define BM_00_44 BM_44_00 -#define BM_45_00 0x00003fffffffffff -#define BM_00_45 BM_45_00 -#define BM_46_00 0x00007fffffffffff -#define BM_00_46 BM_46_00 -#define BM_47_00 0x0000ffffffffffff -#define BM_00_47 BM_47_00 -#define BM_48_00 0x0001ffffffffffff -#define BM_00_48 BM_48_00 -#define BM_49_00 0x0003ffffffffffff -#define BM_00_49 BM_49_00 -#define BM_50_00 0x0007ffffffffffff -#define BM_00_50 BM_50_00 -#define BM_51_00 0x000fffffffffffff -#define BM_00_51 BM_51_00 -#define BM_52_00 0x001fffffffffffff -#define BM_00_52 BM_52_00 -#define BM_53_00 0x003fffffffffffff -#define BM_00_53 BM_53_00 -#define BM_54_00 0x007fffffffffffff -#define BM_00_54 BM_54_00 -#define BM_55_00 0x00ffffffffffffff -#define BM_00_55 BM_55_00 -#define BM_56_00 0x01ffffffffffffff -#define BM_00_56 BM_56_00 -#define BM_57_00 0x03ffffffffffffff -#define BM_00_57 BM_57_00 -#define BM_58_00 0x07ffffffffffffff -#define BM_00_58 BM_58_00 -#define BM_59_00 0x0fffffffffffffff -#define BM_00_59 BM_59_00 -#define BM_60_00 0x1fffffffffffffff -#define BM_00_60 BM_60_00 -#define BM_61_00 0x3fffffffffffffff -#define BM_00_61 BM_61_00 -#define BM_62_00 0x7fffffffffffffff -#define BM_00_62 BM_62_00 -#define BM_63_00 0xffffffffffffffff -#define BM_00_63 BM_63_00 -#define BM_01_01 0x0000000000000002 -#define BM_02_01 0x0000000000000006 -#define BM_01_02 BM_02_01 -#define BM_03_01 0x000000000000000e -#define BM_01_03 BM_03_01 -#define BM_04_01 0x000000000000001e -#define BM_01_04 BM_04_01 -#define BM_05_01 0x000000000000003e -#define BM_01_05 BM_05_01 -#define BM_06_01 0x000000000000007e -#define BM_01_06 BM_06_01 -#define BM_07_01 0x00000000000000fe -#define BM_01_07 BM_07_01 -#define BM_08_01 0x00000000000001fe -#define BM_01_08 BM_08_01 -#define BM_09_01 0x00000000000003fe -#define BM_01_09 BM_09_01 -#define BM_10_01 0x00000000000007fe -#define BM_01_10 BM_10_01 -#define BM_11_01 0x0000000000000ffe -#define BM_01_11 BM_11_01 -#define BM_12_01 0x0000000000001ffe -#define BM_01_12 BM_12_01 -#define BM_13_01 0x0000000000003ffe -#define BM_01_13 BM_13_01 -#define BM_14_01 0x0000000000007ffe -#define BM_01_14 BM_14_01 -#define BM_15_01 0x000000000000fffe -#define BM_01_15 BM_15_01 -#define BM_16_01 0x000000000001fffe -#define BM_01_16 BM_16_01 -#define BM_17_01 0x000000000003fffe -#define BM_01_17 BM_17_01 -#define BM_18_01 0x000000000007fffe -#define BM_01_18 BM_18_01 -#define BM_19_01 0x00000000000ffffe -#define BM_01_19 BM_19_01 -#define BM_20_01 0x00000000001ffffe -#define BM_01_20 BM_20_01 -#define BM_21_01 0x00000000003ffffe -#define BM_01_21 BM_21_01 -#define BM_22_01 0x00000000007ffffe -#define BM_01_22 BM_22_01 -#define BM_23_01 0x0000000000fffffe -#define BM_01_23 BM_23_01 -#define BM_24_01 0x0000000001fffffe -#define BM_01_24 BM_24_01 -#define BM_25_01 0x0000000003fffffe -#define BM_01_25 BM_25_01 -#define BM_26_01 0x0000000007fffffe -#define BM_01_26 BM_26_01 -#define BM_27_01 0x000000000ffffffe -#define BM_01_27 BM_27_01 -#define BM_28_01 0x000000001ffffffe -#define BM_01_28 BM_28_01 -#define BM_29_01 0x000000003ffffffe -#define BM_01_29 BM_29_01 -#define BM_30_01 0x000000007ffffffe -#define BM_01_30 BM_30_01 -#define BM_31_01 0x00000000fffffffe -#define BM_01_31 BM_31_01 -#define BM_32_01 0x00000001fffffffe -#define BM_01_32 BM_32_01 -#define BM_33_01 0x00000003fffffffe -#define BM_01_33 BM_33_01 -#define BM_34_01 0x00000007fffffffe -#define BM_01_34 BM_34_01 -#define BM_35_01 0x0000000ffffffffe -#define BM_01_35 BM_35_01 -#define BM_36_01 0x0000001ffffffffe -#define BM_01_36 BM_36_01 -#define BM_37_01 0x0000003ffffffffe -#define BM_01_37 BM_37_01 -#define BM_38_01 0x0000007ffffffffe -#define BM_01_38 BM_38_01 -#define BM_39_01 0x000000fffffffffe -#define BM_01_39 BM_39_01 -#define BM_40_01 0x000001fffffffffe -#define BM_01_40 BM_40_01 -#define BM_41_01 0x000003fffffffffe -#define BM_01_41 BM_41_01 -#define BM_42_01 0x000007fffffffffe -#define BM_01_42 BM_42_01 -#define BM_43_01 0x00000ffffffffffe -#define BM_01_43 BM_43_01 -#define BM_44_01 0x00001ffffffffffe -#define BM_01_44 BM_44_01 -#define BM_45_01 0x00003ffffffffffe -#define BM_01_45 BM_45_01 -#define BM_46_01 0x00007ffffffffffe -#define BM_01_46 BM_46_01 -#define BM_47_01 0x0000fffffffffffe -#define BM_01_47 BM_47_01 -#define BM_48_01 0x0001fffffffffffe -#define BM_01_48 BM_48_01 -#define BM_49_01 0x0003fffffffffffe -#define BM_01_49 BM_49_01 -#define BM_50_01 0x0007fffffffffffe -#define BM_01_50 BM_50_01 -#define BM_51_01 0x000ffffffffffffe -#define BM_01_51 BM_51_01 -#define BM_52_01 0x001ffffffffffffe -#define BM_01_52 BM_52_01 -#define BM_53_01 0x003ffffffffffffe -#define BM_01_53 BM_53_01 -#define BM_54_01 0x007ffffffffffffe -#define BM_01_54 BM_54_01 -#define BM_55_01 0x00fffffffffffffe -#define BM_01_55 BM_55_01 -#define BM_56_01 0x01fffffffffffffe -#define BM_01_56 BM_56_01 -#define BM_57_01 0x03fffffffffffffe -#define BM_01_57 BM_57_01 -#define BM_58_01 0x07fffffffffffffe -#define BM_01_58 BM_58_01 -#define BM_59_01 0x0ffffffffffffffe -#define BM_01_59 BM_59_01 -#define BM_60_01 0x1ffffffffffffffe -#define BM_01_60 BM_60_01 -#define BM_61_01 0x3ffffffffffffffe -#define BM_01_61 BM_61_01 -#define BM_62_01 0x7ffffffffffffffe -#define BM_01_62 BM_62_01 -#define BM_63_01 0xfffffffffffffffe -#define BM_01_63 BM_63_01 -#define BM_02_02 0x0000000000000004 -#define BM_03_02 0x000000000000000c -#define BM_02_03 BM_03_02 -#define BM_04_02 0x000000000000001c -#define BM_02_04 BM_04_02 -#define BM_05_02 0x000000000000003c -#define BM_02_05 BM_05_02 -#define BM_06_02 0x000000000000007c -#define BM_02_06 BM_06_02 -#define BM_07_02 0x00000000000000fc -#define BM_02_07 BM_07_02 -#define BM_08_02 0x00000000000001fc -#define BM_02_08 BM_08_02 -#define BM_09_02 0x00000000000003fc -#define BM_02_09 BM_09_02 -#define BM_10_02 0x00000000000007fc -#define BM_02_10 BM_10_02 -#define BM_11_02 0x0000000000000ffc -#define BM_02_11 BM_11_02 -#define BM_12_02 0x0000000000001ffc -#define BM_02_12 BM_12_02 -#define BM_13_02 0x0000000000003ffc -#define BM_02_13 BM_13_02 -#define BM_14_02 0x0000000000007ffc -#define BM_02_14 BM_14_02 -#define BM_15_02 0x000000000000fffc -#define BM_02_15 BM_15_02 -#define BM_16_02 0x000000000001fffc -#define BM_02_16 BM_16_02 -#define BM_17_02 0x000000000003fffc -#define BM_02_17 BM_17_02 -#define BM_18_02 0x000000000007fffc -#define BM_02_18 BM_18_02 -#define BM_19_02 0x00000000000ffffc -#define BM_02_19 BM_19_02 -#define BM_20_02 0x00000000001ffffc -#define BM_02_20 BM_20_02 -#define BM_21_02 0x00000000003ffffc -#define BM_02_21 BM_21_02 -#define BM_22_02 0x00000000007ffffc -#define BM_02_22 BM_22_02 -#define BM_23_02 0x0000000000fffffc -#define BM_02_23 BM_23_02 -#define BM_24_02 0x0000000001fffffc -#define BM_02_24 BM_24_02 -#define BM_25_02 0x0000000003fffffc -#define BM_02_25 BM_25_02 -#define BM_26_02 0x0000000007fffffc -#define BM_02_26 BM_26_02 -#define BM_27_02 0x000000000ffffffc -#define BM_02_27 BM_27_02 -#define BM_28_02 0x000000001ffffffc -#define BM_02_28 BM_28_02 -#define BM_29_02 0x000000003ffffffc -#define BM_02_29 BM_29_02 -#define BM_30_02 0x000000007ffffffc -#define BM_02_30 BM_30_02 -#define BM_31_02 0x00000000fffffffc -#define BM_02_31 BM_31_02 -#define BM_32_02 0x00000001fffffffc -#define BM_02_32 BM_32_02 -#define BM_33_02 0x00000003fffffffc -#define BM_02_33 BM_33_02 -#define BM_34_02 0x00000007fffffffc -#define BM_02_34 BM_34_02 -#define BM_35_02 0x0000000ffffffffc -#define BM_02_35 BM_35_02 -#define BM_36_02 0x0000001ffffffffc -#define BM_02_36 BM_36_02 -#define BM_37_02 0x0000003ffffffffc -#define BM_02_37 BM_37_02 -#define BM_38_02 0x0000007ffffffffc -#define BM_02_38 BM_38_02 -#define BM_39_02 0x000000fffffffffc -#define BM_02_39 BM_39_02 -#define BM_40_02 0x000001fffffffffc -#define BM_02_40 BM_40_02 -#define BM_41_02 0x000003fffffffffc -#define BM_02_41 BM_41_02 -#define BM_42_02 0x000007fffffffffc -#define BM_02_42 BM_42_02 -#define BM_43_02 0x00000ffffffffffc -#define BM_02_43 BM_43_02 -#define BM_44_02 0x00001ffffffffffc -#define BM_02_44 BM_44_02 -#define BM_45_02 0x00003ffffffffffc -#define BM_02_45 BM_45_02 -#define BM_46_02 0x00007ffffffffffc -#define BM_02_46 BM_46_02 -#define BM_47_02 0x0000fffffffffffc -#define BM_02_47 BM_47_02 -#define BM_48_02 0x0001fffffffffffc -#define BM_02_48 BM_48_02 -#define BM_49_02 0x0003fffffffffffc -#define BM_02_49 BM_49_02 -#define BM_50_02 0x0007fffffffffffc -#define BM_02_50 BM_50_02 -#define BM_51_02 0x000ffffffffffffc -#define BM_02_51 BM_51_02 -#define BM_52_02 0x001ffffffffffffc -#define BM_02_52 BM_52_02 -#define BM_53_02 0x003ffffffffffffc -#define BM_02_53 BM_53_02 -#define BM_54_02 0x007ffffffffffffc -#define BM_02_54 BM_54_02 -#define BM_55_02 0x00fffffffffffffc -#define BM_02_55 BM_55_02 -#define BM_56_02 0x01fffffffffffffc -#define BM_02_56 BM_56_02 -#define BM_57_02 0x03fffffffffffffc -#define BM_02_57 BM_57_02 -#define BM_58_02 0x07fffffffffffffc -#define BM_02_58 BM_58_02 -#define BM_59_02 0x0ffffffffffffffc -#define BM_02_59 BM_59_02 -#define BM_60_02 0x1ffffffffffffffc -#define BM_02_60 BM_60_02 -#define BM_61_02 0x3ffffffffffffffc -#define BM_02_61 BM_61_02 -#define BM_62_02 0x7ffffffffffffffc -#define BM_02_62 BM_62_02 -#define BM_63_02 0xfffffffffffffffc -#define BM_02_63 BM_63_02 -#define BM_03_03 0x0000000000000008 -#define BM_04_03 0x0000000000000018 -#define BM_03_04 BM_04_03 -#define BM_05_03 0x0000000000000038 -#define BM_03_05 BM_05_03 -#define BM_06_03 0x0000000000000078 -#define BM_03_06 BM_06_03 -#define BM_07_03 0x00000000000000f8 -#define BM_03_07 BM_07_03 -#define BM_08_03 0x00000000000001f8 -#define BM_03_08 BM_08_03 -#define BM_09_03 0x00000000000003f8 -#define BM_03_09 BM_09_03 -#define BM_10_03 0x00000000000007f8 -#define BM_03_10 BM_10_03 -#define BM_11_03 0x0000000000000ff8 -#define BM_03_11 BM_11_03 -#define BM_12_03 0x0000000000001ff8 -#define BM_03_12 BM_12_03 -#define BM_13_03 0x0000000000003ff8 -#define BM_03_13 BM_13_03 -#define BM_14_03 0x0000000000007ff8 -#define BM_03_14 BM_14_03 -#define BM_15_03 0x000000000000fff8 -#define BM_03_15 BM_15_03 -#define BM_16_03 0x000000000001fff8 -#define BM_03_16 BM_16_03 -#define BM_17_03 0x000000000003fff8 -#define BM_03_17 BM_17_03 -#define BM_18_03 0x000000000007fff8 -#define BM_03_18 BM_18_03 -#define BM_19_03 0x00000000000ffff8 -#define BM_03_19 BM_19_03 -#define BM_20_03 0x00000000001ffff8 -#define BM_03_20 BM_20_03 -#define BM_21_03 0x00000000003ffff8 -#define BM_03_21 BM_21_03 -#define BM_22_03 0x00000000007ffff8 -#define BM_03_22 BM_22_03 -#define BM_23_03 0x0000000000fffff8 -#define BM_03_23 BM_23_03 -#define BM_24_03 0x0000000001fffff8 -#define BM_03_24 BM_24_03 -#define BM_25_03 0x0000000003fffff8 -#define BM_03_25 BM_25_03 -#define BM_26_03 0x0000000007fffff8 -#define BM_03_26 BM_26_03 -#define BM_27_03 0x000000000ffffff8 -#define BM_03_27 BM_27_03 -#define BM_28_03 0x000000001ffffff8 -#define BM_03_28 BM_28_03 -#define BM_29_03 0x000000003ffffff8 -#define BM_03_29 BM_29_03 -#define BM_30_03 0x000000007ffffff8 -#define BM_03_30 BM_30_03 -#define BM_31_03 0x00000000fffffff8 -#define BM_03_31 BM_31_03 -#define BM_32_03 0x00000001fffffff8 -#define BM_03_32 BM_32_03 -#define BM_33_03 0x00000003fffffff8 -#define BM_03_33 BM_33_03 -#define BM_34_03 0x00000007fffffff8 -#define BM_03_34 BM_34_03 -#define BM_35_03 0x0000000ffffffff8 -#define BM_03_35 BM_35_03 -#define BM_36_03 0x0000001ffffffff8 -#define BM_03_36 BM_36_03 -#define BM_37_03 0x0000003ffffffff8 -#define BM_03_37 BM_37_03 -#define BM_38_03 0x0000007ffffffff8 -#define BM_03_38 BM_38_03 -#define BM_39_03 0x000000fffffffff8 -#define BM_03_39 BM_39_03 -#define BM_40_03 0x000001fffffffff8 -#define BM_03_40 BM_40_03 -#define BM_41_03 0x000003fffffffff8 -#define BM_03_41 BM_41_03 -#define BM_42_03 0x000007fffffffff8 -#define BM_03_42 BM_42_03 -#define BM_43_03 0x00000ffffffffff8 -#define BM_03_43 BM_43_03 -#define BM_44_03 0x00001ffffffffff8 -#define BM_03_44 BM_44_03 -#define BM_45_03 0x00003ffffffffff8 -#define BM_03_45 BM_45_03 -#define BM_46_03 0x00007ffffffffff8 -#define BM_03_46 BM_46_03 -#define BM_47_03 0x0000fffffffffff8 -#define BM_03_47 BM_47_03 -#define BM_48_03 0x0001fffffffffff8 -#define BM_03_48 BM_48_03 -#define BM_49_03 0x0003fffffffffff8 -#define BM_03_49 BM_49_03 -#define BM_50_03 0x0007fffffffffff8 -#define BM_03_50 BM_50_03 -#define BM_51_03 0x000ffffffffffff8 -#define BM_03_51 BM_51_03 -#define BM_52_03 0x001ffffffffffff8 -#define BM_03_52 BM_52_03 -#define BM_53_03 0x003ffffffffffff8 -#define BM_03_53 BM_53_03 -#define BM_54_03 0x007ffffffffffff8 -#define BM_03_54 BM_54_03 -#define BM_55_03 0x00fffffffffffff8 -#define BM_03_55 BM_55_03 -#define BM_56_03 0x01fffffffffffff8 -#define BM_03_56 BM_56_03 -#define BM_57_03 0x03fffffffffffff8 -#define BM_03_57 BM_57_03 -#define BM_58_03 0x07fffffffffffff8 -#define BM_03_58 BM_58_03 -#define BM_59_03 0x0ffffffffffffff8 -#define BM_03_59 BM_59_03 -#define BM_60_03 0x1ffffffffffffff8 -#define BM_03_60 BM_60_03 -#define BM_61_03 0x3ffffffffffffff8 -#define BM_03_61 BM_61_03 -#define BM_62_03 0x7ffffffffffffff8 -#define BM_03_62 BM_62_03 -#define BM_63_03 0xfffffffffffffff8 -#define BM_03_63 BM_63_03 -#define BM_04_04 0x0000000000000010 -#define BM_05_04 0x0000000000000030 -#define BM_04_05 BM_05_04 -#define BM_06_04 0x0000000000000070 -#define BM_04_06 BM_06_04 -#define BM_07_04 0x00000000000000f0 -#define BM_04_07 BM_07_04 -#define BM_08_04 0x00000000000001f0 -#define BM_04_08 BM_08_04 -#define BM_09_04 0x00000000000003f0 -#define BM_04_09 BM_09_04 -#define BM_10_04 0x00000000000007f0 -#define BM_04_10 BM_10_04 -#define BM_11_04 0x0000000000000ff0 -#define BM_04_11 BM_11_04 -#define BM_12_04 0x0000000000001ff0 -#define BM_04_12 BM_12_04 -#define BM_13_04 0x0000000000003ff0 -#define BM_04_13 BM_13_04 -#define BM_14_04 0x0000000000007ff0 -#define BM_04_14 BM_14_04 -#define BM_15_04 0x000000000000fff0 -#define BM_04_15 BM_15_04 -#define BM_16_04 0x000000000001fff0 -#define BM_04_16 BM_16_04 -#define BM_17_04 0x000000000003fff0 -#define BM_04_17 BM_17_04 -#define BM_18_04 0x000000000007fff0 -#define BM_04_18 BM_18_04 -#define BM_19_04 0x00000000000ffff0 -#define BM_04_19 BM_19_04 -#define BM_20_04 0x00000000001ffff0 -#define BM_04_20 BM_20_04 -#define BM_21_04 0x00000000003ffff0 -#define BM_04_21 BM_21_04 -#define BM_22_04 0x00000000007ffff0 -#define BM_04_22 BM_22_04 -#define BM_23_04 0x0000000000fffff0 -#define BM_04_23 BM_23_04 -#define BM_24_04 0x0000000001fffff0 -#define BM_04_24 BM_24_04 -#define BM_25_04 0x0000000003fffff0 -#define BM_04_25 BM_25_04 -#define BM_26_04 0x0000000007fffff0 -#define BM_04_26 BM_26_04 -#define BM_27_04 0x000000000ffffff0 -#define BM_04_27 BM_27_04 -#define BM_28_04 0x000000001ffffff0 -#define BM_04_28 BM_28_04 -#define BM_29_04 0x000000003ffffff0 -#define BM_04_29 BM_29_04 -#define BM_30_04 0x000000007ffffff0 -#define BM_04_30 BM_30_04 -#define BM_31_04 0x00000000fffffff0 -#define BM_04_31 BM_31_04 -#define BM_32_04 0x00000001fffffff0 -#define BM_04_32 BM_32_04 -#define BM_33_04 0x00000003fffffff0 -#define BM_04_33 BM_33_04 -#define BM_34_04 0x00000007fffffff0 -#define BM_04_34 BM_34_04 -#define BM_35_04 0x0000000ffffffff0 -#define BM_04_35 BM_35_04 -#define BM_36_04 0x0000001ffffffff0 -#define BM_04_36 BM_36_04 -#define BM_37_04 0x0000003ffffffff0 -#define BM_04_37 BM_37_04 -#define BM_38_04 0x0000007ffffffff0 -#define BM_04_38 BM_38_04 -#define BM_39_04 0x000000fffffffff0 -#define BM_04_39 BM_39_04 -#define BM_40_04 0x000001fffffffff0 -#define BM_04_40 BM_40_04 -#define BM_41_04 0x000003fffffffff0 -#define BM_04_41 BM_41_04 -#define BM_42_04 0x000007fffffffff0 -#define BM_04_42 BM_42_04 -#define BM_43_04 0x00000ffffffffff0 -#define BM_04_43 BM_43_04 -#define BM_44_04 0x00001ffffffffff0 -#define BM_04_44 BM_44_04 -#define BM_45_04 0x00003ffffffffff0 -#define BM_04_45 BM_45_04 -#define BM_46_04 0x00007ffffffffff0 -#define BM_04_46 BM_46_04 -#define BM_47_04 0x0000fffffffffff0 -#define BM_04_47 BM_47_04 -#define BM_48_04 0x0001fffffffffff0 -#define BM_04_48 BM_48_04 -#define BM_49_04 0x0003fffffffffff0 -#define BM_04_49 BM_49_04 -#define BM_50_04 0x0007fffffffffff0 -#define BM_04_50 BM_50_04 -#define BM_51_04 0x000ffffffffffff0 -#define BM_04_51 BM_51_04 -#define BM_52_04 0x001ffffffffffff0 -#define BM_04_52 BM_52_04 -#define BM_53_04 0x003ffffffffffff0 -#define BM_04_53 BM_53_04 -#define BM_54_04 0x007ffffffffffff0 -#define BM_04_54 BM_54_04 -#define BM_55_04 0x00fffffffffffff0 -#define BM_04_55 BM_55_04 -#define BM_56_04 0x01fffffffffffff0 -#define BM_04_56 BM_56_04 -#define BM_57_04 0x03fffffffffffff0 -#define BM_04_57 BM_57_04 -#define BM_58_04 0x07fffffffffffff0 -#define BM_04_58 BM_58_04 -#define BM_59_04 0x0ffffffffffffff0 -#define BM_04_59 BM_59_04 -#define BM_60_04 0x1ffffffffffffff0 -#define BM_04_60 BM_60_04 -#define BM_61_04 0x3ffffffffffffff0 -#define BM_04_61 BM_61_04 -#define BM_62_04 0x7ffffffffffffff0 -#define BM_04_62 BM_62_04 -#define BM_63_04 0xfffffffffffffff0 -#define BM_04_63 BM_63_04 -#define BM_05_05 0x0000000000000020 -#define BM_06_05 0x0000000000000060 -#define BM_05_06 BM_06_05 -#define BM_07_05 0x00000000000000e0 -#define BM_05_07 BM_07_05 -#define BM_08_05 0x00000000000001e0 -#define BM_05_08 BM_08_05 -#define BM_09_05 0x00000000000003e0 -#define BM_05_09 BM_09_05 -#define BM_10_05 0x00000000000007e0 -#define BM_05_10 BM_10_05 -#define BM_11_05 0x0000000000000fe0 -#define BM_05_11 BM_11_05 -#define BM_12_05 0x0000000000001fe0 -#define BM_05_12 BM_12_05 -#define BM_13_05 0x0000000000003fe0 -#define BM_05_13 BM_13_05 -#define BM_14_05 0x0000000000007fe0 -#define BM_05_14 BM_14_05 -#define BM_15_05 0x000000000000ffe0 -#define BM_05_15 BM_15_05 -#define BM_16_05 0x000000000001ffe0 -#define BM_05_16 BM_16_05 -#define BM_17_05 0x000000000003ffe0 -#define BM_05_17 BM_17_05 -#define BM_18_05 0x000000000007ffe0 -#define BM_05_18 BM_18_05 -#define BM_19_05 0x00000000000fffe0 -#define BM_05_19 BM_19_05 -#define BM_20_05 0x00000000001fffe0 -#define BM_05_20 BM_20_05 -#define BM_21_05 0x00000000003fffe0 -#define BM_05_21 BM_21_05 -#define BM_22_05 0x00000000007fffe0 -#define BM_05_22 BM_22_05 -#define BM_23_05 0x0000000000ffffe0 -#define BM_05_23 BM_23_05 -#define BM_24_05 0x0000000001ffffe0 -#define BM_05_24 BM_24_05 -#define BM_25_05 0x0000000003ffffe0 -#define BM_05_25 BM_25_05 -#define BM_26_05 0x0000000007ffffe0 -#define BM_05_26 BM_26_05 -#define BM_27_05 0x000000000fffffe0 -#define BM_05_27 BM_27_05 -#define BM_28_05 0x000000001fffffe0 -#define BM_05_28 BM_28_05 -#define BM_29_05 0x000000003fffffe0 -#define BM_05_29 BM_29_05 -#define BM_30_05 0x000000007fffffe0 -#define BM_05_30 BM_30_05 -#define BM_31_05 0x00000000ffffffe0 -#define BM_05_31 BM_31_05 -#define BM_32_05 0x00000001ffffffe0 -#define BM_05_32 BM_32_05 -#define BM_33_05 0x00000003ffffffe0 -#define BM_05_33 BM_33_05 -#define BM_34_05 0x00000007ffffffe0 -#define BM_05_34 BM_34_05 -#define BM_35_05 0x0000000fffffffe0 -#define BM_05_35 BM_35_05 -#define BM_36_05 0x0000001fffffffe0 -#define BM_05_36 BM_36_05 -#define BM_37_05 0x0000003fffffffe0 -#define BM_05_37 BM_37_05 -#define BM_38_05 0x0000007fffffffe0 -#define BM_05_38 BM_38_05 -#define BM_39_05 0x000000ffffffffe0 -#define BM_05_39 BM_39_05 -#define BM_40_05 0x000001ffffffffe0 -#define BM_05_40 BM_40_05 -#define BM_41_05 0x000003ffffffffe0 -#define BM_05_41 BM_41_05 -#define BM_42_05 0x000007ffffffffe0 -#define BM_05_42 BM_42_05 -#define BM_43_05 0x00000fffffffffe0 -#define BM_05_43 BM_43_05 -#define BM_44_05 0x00001fffffffffe0 -#define BM_05_44 BM_44_05 -#define BM_45_05 0x00003fffffffffe0 -#define BM_05_45 BM_45_05 -#define BM_46_05 0x00007fffffffffe0 -#define BM_05_46 BM_46_05 -#define BM_47_05 0x0000ffffffffffe0 -#define BM_05_47 BM_47_05 -#define BM_48_05 0x0001ffffffffffe0 -#define BM_05_48 BM_48_05 -#define BM_49_05 0x0003ffffffffffe0 -#define BM_05_49 BM_49_05 -#define BM_50_05 0x0007ffffffffffe0 -#define BM_05_50 BM_50_05 -#define BM_51_05 0x000fffffffffffe0 -#define BM_05_51 BM_51_05 -#define BM_52_05 0x001fffffffffffe0 -#define BM_05_52 BM_52_05 -#define BM_53_05 0x003fffffffffffe0 -#define BM_05_53 BM_53_05 -#define BM_54_05 0x007fffffffffffe0 -#define BM_05_54 BM_54_05 -#define BM_55_05 0x00ffffffffffffe0 -#define BM_05_55 BM_55_05 -#define BM_56_05 0x01ffffffffffffe0 -#define BM_05_56 BM_56_05 -#define BM_57_05 0x03ffffffffffffe0 -#define BM_05_57 BM_57_05 -#define BM_58_05 0x07ffffffffffffe0 -#define BM_05_58 BM_58_05 -#define BM_59_05 0x0fffffffffffffe0 -#define BM_05_59 BM_59_05 -#define BM_60_05 0x1fffffffffffffe0 -#define BM_05_60 BM_60_05 -#define BM_61_05 0x3fffffffffffffe0 -#define BM_05_61 BM_61_05 -#define BM_62_05 0x7fffffffffffffe0 -#define BM_05_62 BM_62_05 -#define BM_63_05 0xffffffffffffffe0 -#define BM_05_63 BM_63_05 -#define BM_06_06 0x0000000000000040 -#define BM_07_06 0x00000000000000c0 -#define BM_06_07 BM_07_06 -#define BM_08_06 0x00000000000001c0 -#define BM_06_08 BM_08_06 -#define BM_09_06 0x00000000000003c0 -#define BM_06_09 BM_09_06 -#define BM_10_06 0x00000000000007c0 -#define BM_06_10 BM_10_06 -#define BM_11_06 0x0000000000000fc0 -#define BM_06_11 BM_11_06 -#define BM_12_06 0x0000000000001fc0 -#define BM_06_12 BM_12_06 -#define BM_13_06 0x0000000000003fc0 -#define BM_06_13 BM_13_06 -#define BM_14_06 0x0000000000007fc0 -#define BM_06_14 BM_14_06 -#define BM_15_06 0x000000000000ffc0 -#define BM_06_15 BM_15_06 -#define BM_16_06 0x000000000001ffc0 -#define BM_06_16 BM_16_06 -#define BM_17_06 0x000000000003ffc0 -#define BM_06_17 BM_17_06 -#define BM_18_06 0x000000000007ffc0 -#define BM_06_18 BM_18_06 -#define BM_19_06 0x00000000000fffc0 -#define BM_06_19 BM_19_06 -#define BM_20_06 0x00000000001fffc0 -#define BM_06_20 BM_20_06 -#define BM_21_06 0x00000000003fffc0 -#define BM_06_21 BM_21_06 -#define BM_22_06 0x00000000007fffc0 -#define BM_06_22 BM_22_06 -#define BM_23_06 0x0000000000ffffc0 -#define BM_06_23 BM_23_06 -#define BM_24_06 0x0000000001ffffc0 -#define BM_06_24 BM_24_06 -#define BM_25_06 0x0000000003ffffc0 -#define BM_06_25 BM_25_06 -#define BM_26_06 0x0000000007ffffc0 -#define BM_06_26 BM_26_06 -#define BM_27_06 0x000000000fffffc0 -#define BM_06_27 BM_27_06 -#define BM_28_06 0x000000001fffffc0 -#define BM_06_28 BM_28_06 -#define BM_29_06 0x000000003fffffc0 -#define BM_06_29 BM_29_06 -#define BM_30_06 0x000000007fffffc0 -#define BM_06_30 BM_30_06 -#define BM_31_06 0x00000000ffffffc0 -#define BM_06_31 BM_31_06 -#define BM_32_06 0x00000001ffffffc0 -#define BM_06_32 BM_32_06 -#define BM_33_06 0x00000003ffffffc0 -#define BM_06_33 BM_33_06 -#define BM_34_06 0x00000007ffffffc0 -#define BM_06_34 BM_34_06 -#define BM_35_06 0x0000000fffffffc0 -#define BM_06_35 BM_35_06 -#define BM_36_06 0x0000001fffffffc0 -#define BM_06_36 BM_36_06 -#define BM_37_06 0x0000003fffffffc0 -#define BM_06_37 BM_37_06 -#define BM_38_06 0x0000007fffffffc0 -#define BM_06_38 BM_38_06 -#define BM_39_06 0x000000ffffffffc0 -#define BM_06_39 BM_39_06 -#define BM_40_06 0x000001ffffffffc0 -#define BM_06_40 BM_40_06 -#define BM_41_06 0x000003ffffffffc0 -#define BM_06_41 BM_41_06 -#define BM_42_06 0x000007ffffffffc0 -#define BM_06_42 BM_42_06 -#define BM_43_06 0x00000fffffffffc0 -#define BM_06_43 BM_43_06 -#define BM_44_06 0x00001fffffffffc0 -#define BM_06_44 BM_44_06 -#define BM_45_06 0x00003fffffffffc0 -#define BM_06_45 BM_45_06 -#define BM_46_06 0x00007fffffffffc0 -#define BM_06_46 BM_46_06 -#define BM_47_06 0x0000ffffffffffc0 -#define BM_06_47 BM_47_06 -#define BM_48_06 0x0001ffffffffffc0 -#define BM_06_48 BM_48_06 -#define BM_49_06 0x0003ffffffffffc0 -#define BM_06_49 BM_49_06 -#define BM_50_06 0x0007ffffffffffc0 -#define BM_06_50 BM_50_06 -#define BM_51_06 0x000fffffffffffc0 -#define BM_06_51 BM_51_06 -#define BM_52_06 0x001fffffffffffc0 -#define BM_06_52 BM_52_06 -#define BM_53_06 0x003fffffffffffc0 -#define BM_06_53 BM_53_06 -#define BM_54_06 0x007fffffffffffc0 -#define BM_06_54 BM_54_06 -#define BM_55_06 0x00ffffffffffffc0 -#define BM_06_55 BM_55_06 -#define BM_56_06 0x01ffffffffffffc0 -#define BM_06_56 BM_56_06 -#define BM_57_06 0x03ffffffffffffc0 -#define BM_06_57 BM_57_06 -#define BM_58_06 0x07ffffffffffffc0 -#define BM_06_58 BM_58_06 -#define BM_59_06 0x0fffffffffffffc0 -#define BM_06_59 BM_59_06 -#define BM_60_06 0x1fffffffffffffc0 -#define BM_06_60 BM_60_06 -#define BM_61_06 0x3fffffffffffffc0 -#define BM_06_61 BM_61_06 -#define BM_62_06 0x7fffffffffffffc0 -#define BM_06_62 BM_62_06 -#define BM_63_06 0xffffffffffffffc0 -#define BM_06_63 BM_63_06 -#define BM_07_07 0x0000000000000080 -#define BM_08_07 0x0000000000000180 -#define BM_07_08 BM_08_07 -#define BM_09_07 0x0000000000000380 -#define BM_07_09 BM_09_07 -#define BM_10_07 0x0000000000000780 -#define BM_07_10 BM_10_07 -#define BM_11_07 0x0000000000000f80 -#define BM_07_11 BM_11_07 -#define BM_12_07 0x0000000000001f80 -#define BM_07_12 BM_12_07 -#define BM_13_07 0x0000000000003f80 -#define BM_07_13 BM_13_07 -#define BM_14_07 0x0000000000007f80 -#define BM_07_14 BM_14_07 -#define BM_15_07 0x000000000000ff80 -#define BM_07_15 BM_15_07 -#define BM_16_07 0x000000000001ff80 -#define BM_07_16 BM_16_07 -#define BM_17_07 0x000000000003ff80 -#define BM_07_17 BM_17_07 -#define BM_18_07 0x000000000007ff80 -#define BM_07_18 BM_18_07 -#define BM_19_07 0x00000000000fff80 -#define BM_07_19 BM_19_07 -#define BM_20_07 0x00000000001fff80 -#define BM_07_20 BM_20_07 -#define BM_21_07 0x00000000003fff80 -#define BM_07_21 BM_21_07 -#define BM_22_07 0x00000000007fff80 -#define BM_07_22 BM_22_07 -#define BM_23_07 0x0000000000ffff80 -#define BM_07_23 BM_23_07 -#define BM_24_07 0x0000000001ffff80 -#define BM_07_24 BM_24_07 -#define BM_25_07 0x0000000003ffff80 -#define BM_07_25 BM_25_07 -#define BM_26_07 0x0000000007ffff80 -#define BM_07_26 BM_26_07 -#define BM_27_07 0x000000000fffff80 -#define BM_07_27 BM_27_07 -#define BM_28_07 0x000000001fffff80 -#define BM_07_28 BM_28_07 -#define BM_29_07 0x000000003fffff80 -#define BM_07_29 BM_29_07 -#define BM_30_07 0x000000007fffff80 -#define BM_07_30 BM_30_07 -#define BM_31_07 0x00000000ffffff80 -#define BM_07_31 BM_31_07 -#define BM_32_07 0x00000001ffffff80 -#define BM_07_32 BM_32_07 -#define BM_33_07 0x00000003ffffff80 -#define BM_07_33 BM_33_07 -#define BM_34_07 0x00000007ffffff80 -#define BM_07_34 BM_34_07 -#define BM_35_07 0x0000000fffffff80 -#define BM_07_35 BM_35_07 -#define BM_36_07 0x0000001fffffff80 -#define BM_07_36 BM_36_07 -#define BM_37_07 0x0000003fffffff80 -#define BM_07_37 BM_37_07 -#define BM_38_07 0x0000007fffffff80 -#define BM_07_38 BM_38_07 -#define BM_39_07 0x000000ffffffff80 -#define BM_07_39 BM_39_07 -#define BM_40_07 0x000001ffffffff80 -#define BM_07_40 BM_40_07 -#define BM_41_07 0x000003ffffffff80 -#define BM_07_41 BM_41_07 -#define BM_42_07 0x000007ffffffff80 -#define BM_07_42 BM_42_07 -#define BM_43_07 0x00000fffffffff80 -#define BM_07_43 BM_43_07 -#define BM_44_07 0x00001fffffffff80 -#define BM_07_44 BM_44_07 -#define BM_45_07 0x00003fffffffff80 -#define BM_07_45 BM_45_07 -#define BM_46_07 0x00007fffffffff80 -#define BM_07_46 BM_46_07 -#define BM_47_07 0x0000ffffffffff80 -#define BM_07_47 BM_47_07 -#define BM_48_07 0x0001ffffffffff80 -#define BM_07_48 BM_48_07 -#define BM_49_07 0x0003ffffffffff80 -#define BM_07_49 BM_49_07 -#define BM_50_07 0x0007ffffffffff80 -#define BM_07_50 BM_50_07 -#define BM_51_07 0x000fffffffffff80 -#define BM_07_51 BM_51_07 -#define BM_52_07 0x001fffffffffff80 -#define BM_07_52 BM_52_07 -#define BM_53_07 0x003fffffffffff80 -#define BM_07_53 BM_53_07 -#define BM_54_07 0x007fffffffffff80 -#define BM_07_54 BM_54_07 -#define BM_55_07 0x00ffffffffffff80 -#define BM_07_55 BM_55_07 -#define BM_56_07 0x01ffffffffffff80 -#define BM_07_56 BM_56_07 -#define BM_57_07 0x03ffffffffffff80 -#define BM_07_57 BM_57_07 -#define BM_58_07 0x07ffffffffffff80 -#define BM_07_58 BM_58_07 -#define BM_59_07 0x0fffffffffffff80 -#define BM_07_59 BM_59_07 -#define BM_60_07 0x1fffffffffffff80 -#define BM_07_60 BM_60_07 -#define BM_61_07 0x3fffffffffffff80 -#define BM_07_61 BM_61_07 -#define BM_62_07 0x7fffffffffffff80 -#define BM_07_62 BM_62_07 -#define BM_63_07 0xffffffffffffff80 -#define BM_07_63 BM_63_07 -#define BM_08_08 0x0000000000000100 -#define BM_09_08 0x0000000000000300 -#define BM_08_09 BM_09_08 -#define BM_10_08 0x0000000000000700 -#define BM_08_10 BM_10_08 -#define BM_11_08 0x0000000000000f00 -#define BM_08_11 BM_11_08 -#define BM_12_08 0x0000000000001f00 -#define BM_08_12 BM_12_08 -#define BM_13_08 0x0000000000003f00 -#define BM_08_13 BM_13_08 -#define BM_14_08 0x0000000000007f00 -#define BM_08_14 BM_14_08 -#define BM_15_08 0x000000000000ff00 -#define BM_08_15 BM_15_08 -#define BM_16_08 0x000000000001ff00 -#define BM_08_16 BM_16_08 -#define BM_17_08 0x000000000003ff00 -#define BM_08_17 BM_17_08 -#define BM_18_08 0x000000000007ff00 -#define BM_08_18 BM_18_08 -#define BM_19_08 0x00000000000fff00 -#define BM_08_19 BM_19_08 -#define BM_20_08 0x00000000001fff00 -#define BM_08_20 BM_20_08 -#define BM_21_08 0x00000000003fff00 -#define BM_08_21 BM_21_08 -#define BM_22_08 0x00000000007fff00 -#define BM_08_22 BM_22_08 -#define BM_23_08 0x0000000000ffff00 -#define BM_08_23 BM_23_08 -#define BM_24_08 0x0000000001ffff00 -#define BM_08_24 BM_24_08 -#define BM_25_08 0x0000000003ffff00 -#define BM_08_25 BM_25_08 -#define BM_26_08 0x0000000007ffff00 -#define BM_08_26 BM_26_08 -#define BM_27_08 0x000000000fffff00 -#define BM_08_27 BM_27_08 -#define BM_28_08 0x000000001fffff00 -#define BM_08_28 BM_28_08 -#define BM_29_08 0x000000003fffff00 -#define BM_08_29 BM_29_08 -#define BM_30_08 0x000000007fffff00 -#define BM_08_30 BM_30_08 -#define BM_31_08 0x00000000ffffff00 -#define BM_08_31 BM_31_08 -#define BM_32_08 0x00000001ffffff00 -#define BM_08_32 BM_32_08 -#define BM_33_08 0x00000003ffffff00 -#define BM_08_33 BM_33_08 -#define BM_34_08 0x00000007ffffff00 -#define BM_08_34 BM_34_08 -#define BM_35_08 0x0000000fffffff00 -#define BM_08_35 BM_35_08 -#define BM_36_08 0x0000001fffffff00 -#define BM_08_36 BM_36_08 -#define BM_37_08 0x0000003fffffff00 -#define BM_08_37 BM_37_08 -#define BM_38_08 0x0000007fffffff00 -#define BM_08_38 BM_38_08 -#define BM_39_08 0x000000ffffffff00 -#define BM_08_39 BM_39_08 -#define BM_40_08 0x000001ffffffff00 -#define BM_08_40 BM_40_08 -#define BM_41_08 0x000003ffffffff00 -#define BM_08_41 BM_41_08 -#define BM_42_08 0x000007ffffffff00 -#define BM_08_42 BM_42_08 -#define BM_43_08 0x00000fffffffff00 -#define BM_08_43 BM_43_08 -#define BM_44_08 0x00001fffffffff00 -#define BM_08_44 BM_44_08 -#define BM_45_08 0x00003fffffffff00 -#define BM_08_45 BM_45_08 -#define BM_46_08 0x00007fffffffff00 -#define BM_08_46 BM_46_08 -#define BM_47_08 0x0000ffffffffff00 -#define BM_08_47 BM_47_08 -#define BM_48_08 0x0001ffffffffff00 -#define BM_08_48 BM_48_08 -#define BM_49_08 0x0003ffffffffff00 -#define BM_08_49 BM_49_08 -#define BM_50_08 0x0007ffffffffff00 -#define BM_08_50 BM_50_08 -#define BM_51_08 0x000fffffffffff00 -#define BM_08_51 BM_51_08 -#define BM_52_08 0x001fffffffffff00 -#define BM_08_52 BM_52_08 -#define BM_53_08 0x003fffffffffff00 -#define BM_08_53 BM_53_08 -#define BM_54_08 0x007fffffffffff00 -#define BM_08_54 BM_54_08 -#define BM_55_08 0x00ffffffffffff00 -#define BM_08_55 BM_55_08 -#define BM_56_08 0x01ffffffffffff00 -#define BM_08_56 BM_56_08 -#define BM_57_08 0x03ffffffffffff00 -#define BM_08_57 BM_57_08 -#define BM_58_08 0x07ffffffffffff00 -#define BM_08_58 BM_58_08 -#define BM_59_08 0x0fffffffffffff00 -#define BM_08_59 BM_59_08 -#define BM_60_08 0x1fffffffffffff00 -#define BM_08_60 BM_60_08 -#define BM_61_08 0x3fffffffffffff00 -#define BM_08_61 BM_61_08 -#define BM_62_08 0x7fffffffffffff00 -#define BM_08_62 BM_62_08 -#define BM_63_08 0xffffffffffffff00 -#define BM_08_63 BM_63_08 -#define BM_09_09 0x0000000000000200 -#define BM_10_09 0x0000000000000600 -#define BM_09_10 BM_10_09 -#define BM_11_09 0x0000000000000e00 -#define BM_09_11 BM_11_09 -#define BM_12_09 0x0000000000001e00 -#define BM_09_12 BM_12_09 -#define BM_13_09 0x0000000000003e00 -#define BM_09_13 BM_13_09 -#define BM_14_09 0x0000000000007e00 -#define BM_09_14 BM_14_09 -#define BM_15_09 0x000000000000fe00 -#define BM_09_15 BM_15_09 -#define BM_16_09 0x000000000001fe00 -#define BM_09_16 BM_16_09 -#define BM_17_09 0x000000000003fe00 -#define BM_09_17 BM_17_09 -#define BM_18_09 0x000000000007fe00 -#define BM_09_18 BM_18_09 -#define BM_19_09 0x00000000000ffe00 -#define BM_09_19 BM_19_09 -#define BM_20_09 0x00000000001ffe00 -#define BM_09_20 BM_20_09 -#define BM_21_09 0x00000000003ffe00 -#define BM_09_21 BM_21_09 -#define BM_22_09 0x00000000007ffe00 -#define BM_09_22 BM_22_09 -#define BM_23_09 0x0000000000fffe00 -#define BM_09_23 BM_23_09 -#define BM_24_09 0x0000000001fffe00 -#define BM_09_24 BM_24_09 -#define BM_25_09 0x0000000003fffe00 -#define BM_09_25 BM_25_09 -#define BM_26_09 0x0000000007fffe00 -#define BM_09_26 BM_26_09 -#define BM_27_09 0x000000000ffffe00 -#define BM_09_27 BM_27_09 -#define BM_28_09 0x000000001ffffe00 -#define BM_09_28 BM_28_09 -#define BM_29_09 0x000000003ffffe00 -#define BM_09_29 BM_29_09 -#define BM_30_09 0x000000007ffffe00 -#define BM_09_30 BM_30_09 -#define BM_31_09 0x00000000fffffe00 -#define BM_09_31 BM_31_09 -#define BM_32_09 0x00000001fffffe00 -#define BM_09_32 BM_32_09 -#define BM_33_09 0x00000003fffffe00 -#define BM_09_33 BM_33_09 -#define BM_34_09 0x00000007fffffe00 -#define BM_09_34 BM_34_09 -#define BM_35_09 0x0000000ffffffe00 -#define BM_09_35 BM_35_09 -#define BM_36_09 0x0000001ffffffe00 -#define BM_09_36 BM_36_09 -#define BM_37_09 0x0000003ffffffe00 -#define BM_09_37 BM_37_09 -#define BM_38_09 0x0000007ffffffe00 -#define BM_09_38 BM_38_09 -#define BM_39_09 0x000000fffffffe00 -#define BM_09_39 BM_39_09 -#define BM_40_09 0x000001fffffffe00 -#define BM_09_40 BM_40_09 -#define BM_41_09 0x000003fffffffe00 -#define BM_09_41 BM_41_09 -#define BM_42_09 0x000007fffffffe00 -#define BM_09_42 BM_42_09 -#define BM_43_09 0x00000ffffffffe00 -#define BM_09_43 BM_43_09 -#define BM_44_09 0x00001ffffffffe00 -#define BM_09_44 BM_44_09 -#define BM_45_09 0x00003ffffffffe00 -#define BM_09_45 BM_45_09 -#define BM_46_09 0x00007ffffffffe00 -#define BM_09_46 BM_46_09 -#define BM_47_09 0x0000fffffffffe00 -#define BM_09_47 BM_47_09 -#define BM_48_09 0x0001fffffffffe00 -#define BM_09_48 BM_48_09 -#define BM_49_09 0x0003fffffffffe00 -#define BM_09_49 BM_49_09 -#define BM_50_09 0x0007fffffffffe00 -#define BM_09_50 BM_50_09 -#define BM_51_09 0x000ffffffffffe00 -#define BM_09_51 BM_51_09 -#define BM_52_09 0x001ffffffffffe00 -#define BM_09_52 BM_52_09 -#define BM_53_09 0x003ffffffffffe00 -#define BM_09_53 BM_53_09 -#define BM_54_09 0x007ffffffffffe00 -#define BM_09_54 BM_54_09 -#define BM_55_09 0x00fffffffffffe00 -#define BM_09_55 BM_55_09 -#define BM_56_09 0x01fffffffffffe00 -#define BM_09_56 BM_56_09 -#define BM_57_09 0x03fffffffffffe00 -#define BM_09_57 BM_57_09 -#define BM_58_09 0x07fffffffffffe00 -#define BM_09_58 BM_58_09 -#define BM_59_09 0x0ffffffffffffe00 -#define BM_09_59 BM_59_09 -#define BM_60_09 0x1ffffffffffffe00 -#define BM_09_60 BM_60_09 -#define BM_61_09 0x3ffffffffffffe00 -#define BM_09_61 BM_61_09 -#define BM_62_09 0x7ffffffffffffe00 -#define BM_09_62 BM_62_09 -#define BM_63_09 0xfffffffffffffe00 -#define BM_09_63 BM_63_09 -#define BM_10_10 0x0000000000000400 -#define BM_11_10 0x0000000000000c00 -#define BM_10_11 BM_11_10 -#define BM_12_10 0x0000000000001c00 -#define BM_10_12 BM_12_10 -#define BM_13_10 0x0000000000003c00 -#define BM_10_13 BM_13_10 -#define BM_14_10 0x0000000000007c00 -#define BM_10_14 BM_14_10 -#define BM_15_10 0x000000000000fc00 -#define BM_10_15 BM_15_10 -#define BM_16_10 0x000000000001fc00 -#define BM_10_16 BM_16_10 -#define BM_17_10 0x000000000003fc00 -#define BM_10_17 BM_17_10 -#define BM_18_10 0x000000000007fc00 -#define BM_10_18 BM_18_10 -#define BM_19_10 0x00000000000ffc00 -#define BM_10_19 BM_19_10 -#define BM_20_10 0x00000000001ffc00 -#define BM_10_20 BM_20_10 -#define BM_21_10 0x00000000003ffc00 -#define BM_10_21 BM_21_10 -#define BM_22_10 0x00000000007ffc00 -#define BM_10_22 BM_22_10 -#define BM_23_10 0x0000000000fffc00 -#define BM_10_23 BM_23_10 -#define BM_24_10 0x0000000001fffc00 -#define BM_10_24 BM_24_10 -#define BM_25_10 0x0000000003fffc00 -#define BM_10_25 BM_25_10 -#define BM_26_10 0x0000000007fffc00 -#define BM_10_26 BM_26_10 -#define BM_27_10 0x000000000ffffc00 -#define BM_10_27 BM_27_10 -#define BM_28_10 0x000000001ffffc00 -#define BM_10_28 BM_28_10 -#define BM_29_10 0x000000003ffffc00 -#define BM_10_29 BM_29_10 -#define BM_30_10 0x000000007ffffc00 -#define BM_10_30 BM_30_10 -#define BM_31_10 0x00000000fffffc00 -#define BM_10_31 BM_31_10 -#define BM_32_10 0x00000001fffffc00 -#define BM_10_32 BM_32_10 -#define BM_33_10 0x00000003fffffc00 -#define BM_10_33 BM_33_10 -#define BM_34_10 0x00000007fffffc00 -#define BM_10_34 BM_34_10 -#define BM_35_10 0x0000000ffffffc00 -#define BM_10_35 BM_35_10 -#define BM_36_10 0x0000001ffffffc00 -#define BM_10_36 BM_36_10 -#define BM_37_10 0x0000003ffffffc00 -#define BM_10_37 BM_37_10 -#define BM_38_10 0x0000007ffffffc00 -#define BM_10_38 BM_38_10 -#define BM_39_10 0x000000fffffffc00 -#define BM_10_39 BM_39_10 -#define BM_40_10 0x000001fffffffc00 -#define BM_10_40 BM_40_10 -#define BM_41_10 0x000003fffffffc00 -#define BM_10_41 BM_41_10 -#define BM_42_10 0x000007fffffffc00 -#define BM_10_42 BM_42_10 -#define BM_43_10 0x00000ffffffffc00 -#define BM_10_43 BM_43_10 -#define BM_44_10 0x00001ffffffffc00 -#define BM_10_44 BM_44_10 -#define BM_45_10 0x00003ffffffffc00 -#define BM_10_45 BM_45_10 -#define BM_46_10 0x00007ffffffffc00 -#define BM_10_46 BM_46_10 -#define BM_47_10 0x0000fffffffffc00 -#define BM_10_47 BM_47_10 -#define BM_48_10 0x0001fffffffffc00 -#define BM_10_48 BM_48_10 -#define BM_49_10 0x0003fffffffffc00 -#define BM_10_49 BM_49_10 -#define BM_50_10 0x0007fffffffffc00 -#define BM_10_50 BM_50_10 -#define BM_51_10 0x000ffffffffffc00 -#define BM_10_51 BM_51_10 -#define BM_52_10 0x001ffffffffffc00 -#define BM_10_52 BM_52_10 -#define BM_53_10 0x003ffffffffffc00 -#define BM_10_53 BM_53_10 -#define BM_54_10 0x007ffffffffffc00 -#define BM_10_54 BM_54_10 -#define BM_55_10 0x00fffffffffffc00 -#define BM_10_55 BM_55_10 -#define BM_56_10 0x01fffffffffffc00 -#define BM_10_56 BM_56_10 -#define BM_57_10 0x03fffffffffffc00 -#define BM_10_57 BM_57_10 -#define BM_58_10 0x07fffffffffffc00 -#define BM_10_58 BM_58_10 -#define BM_59_10 0x0ffffffffffffc00 -#define BM_10_59 BM_59_10 -#define BM_60_10 0x1ffffffffffffc00 -#define BM_10_60 BM_60_10 -#define BM_61_10 0x3ffffffffffffc00 -#define BM_10_61 BM_61_10 -#define BM_62_10 0x7ffffffffffffc00 -#define BM_10_62 BM_62_10 -#define BM_63_10 0xfffffffffffffc00 -#define BM_10_63 BM_63_10 -#define BM_11_11 0x0000000000000800 -#define BM_12_11 0x0000000000001800 -#define BM_11_12 BM_12_11 -#define BM_13_11 0x0000000000003800 -#define BM_11_13 BM_13_11 -#define BM_14_11 0x0000000000007800 -#define BM_11_14 BM_14_11 -#define BM_15_11 0x000000000000f800 -#define BM_11_15 BM_15_11 -#define BM_16_11 0x000000000001f800 -#define BM_11_16 BM_16_11 -#define BM_17_11 0x000000000003f800 -#define BM_11_17 BM_17_11 -#define BM_18_11 0x000000000007f800 -#define BM_11_18 BM_18_11 -#define BM_19_11 0x00000000000ff800 -#define BM_11_19 BM_19_11 -#define BM_20_11 0x00000000001ff800 -#define BM_11_20 BM_20_11 -#define BM_21_11 0x00000000003ff800 -#define BM_11_21 BM_21_11 -#define BM_22_11 0x00000000007ff800 -#define BM_11_22 BM_22_11 -#define BM_23_11 0x0000000000fff800 -#define BM_11_23 BM_23_11 -#define BM_24_11 0x0000000001fff800 -#define BM_11_24 BM_24_11 -#define BM_25_11 0x0000000003fff800 -#define BM_11_25 BM_25_11 -#define BM_26_11 0x0000000007fff800 -#define BM_11_26 BM_26_11 -#define BM_27_11 0x000000000ffff800 -#define BM_11_27 BM_27_11 -#define BM_28_11 0x000000001ffff800 -#define BM_11_28 BM_28_11 -#define BM_29_11 0x000000003ffff800 -#define BM_11_29 BM_29_11 -#define BM_30_11 0x000000007ffff800 -#define BM_11_30 BM_30_11 -#define BM_31_11 0x00000000fffff800 -#define BM_11_31 BM_31_11 -#define BM_32_11 0x00000001fffff800 -#define BM_11_32 BM_32_11 -#define BM_33_11 0x00000003fffff800 -#define BM_11_33 BM_33_11 -#define BM_34_11 0x00000007fffff800 -#define BM_11_34 BM_34_11 -#define BM_35_11 0x0000000ffffff800 -#define BM_11_35 BM_35_11 -#define BM_36_11 0x0000001ffffff800 -#define BM_11_36 BM_36_11 -#define BM_37_11 0x0000003ffffff800 -#define BM_11_37 BM_37_11 -#define BM_38_11 0x0000007ffffff800 -#define BM_11_38 BM_38_11 -#define BM_39_11 0x000000fffffff800 -#define BM_11_39 BM_39_11 -#define BM_40_11 0x000001fffffff800 -#define BM_11_40 BM_40_11 -#define BM_41_11 0x000003fffffff800 -#define BM_11_41 BM_41_11 -#define BM_42_11 0x000007fffffff800 -#define BM_11_42 BM_42_11 -#define BM_43_11 0x00000ffffffff800 -#define BM_11_43 BM_43_11 -#define BM_44_11 0x00001ffffffff800 -#define BM_11_44 BM_44_11 -#define BM_45_11 0x00003ffffffff800 -#define BM_11_45 BM_45_11 -#define BM_46_11 0x00007ffffffff800 -#define BM_11_46 BM_46_11 -#define BM_47_11 0x0000fffffffff800 -#define BM_11_47 BM_47_11 -#define BM_48_11 0x0001fffffffff800 -#define BM_11_48 BM_48_11 -#define BM_49_11 0x0003fffffffff800 -#define BM_11_49 BM_49_11 -#define BM_50_11 0x0007fffffffff800 -#define BM_11_50 BM_50_11 -#define BM_51_11 0x000ffffffffff800 -#define BM_11_51 BM_51_11 -#define BM_52_11 0x001ffffffffff800 -#define BM_11_52 BM_52_11 -#define BM_53_11 0x003ffffffffff800 -#define BM_11_53 BM_53_11 -#define BM_54_11 0x007ffffffffff800 -#define BM_11_54 BM_54_11 -#define BM_55_11 0x00fffffffffff800 -#define BM_11_55 BM_55_11 -#define BM_56_11 0x01fffffffffff800 -#define BM_11_56 BM_56_11 -#define BM_57_11 0x03fffffffffff800 -#define BM_11_57 BM_57_11 -#define BM_58_11 0x07fffffffffff800 -#define BM_11_58 BM_58_11 -#define BM_59_11 0x0ffffffffffff800 -#define BM_11_59 BM_59_11 -#define BM_60_11 0x1ffffffffffff800 -#define BM_11_60 BM_60_11 -#define BM_61_11 0x3ffffffffffff800 -#define BM_11_61 BM_61_11 -#define BM_62_11 0x7ffffffffffff800 -#define BM_11_62 BM_62_11 -#define BM_63_11 0xfffffffffffff800 -#define BM_11_63 BM_63_11 -#define BM_12_12 0x0000000000001000 -#define BM_13_12 0x0000000000003000 -#define BM_12_13 BM_13_12 -#define BM_14_12 0x0000000000007000 -#define BM_12_14 BM_14_12 -#define BM_15_12 0x000000000000f000 -#define BM_12_15 BM_15_12 -#define BM_16_12 0x000000000001f000 -#define BM_12_16 BM_16_12 -#define BM_17_12 0x000000000003f000 -#define BM_12_17 BM_17_12 -#define BM_18_12 0x000000000007f000 -#define BM_12_18 BM_18_12 -#define BM_19_12 0x00000000000ff000 -#define BM_12_19 BM_19_12 -#define BM_20_12 0x00000000001ff000 -#define BM_12_20 BM_20_12 -#define BM_21_12 0x00000000003ff000 -#define BM_12_21 BM_21_12 -#define BM_22_12 0x00000000007ff000 -#define BM_12_22 BM_22_12 -#define BM_23_12 0x0000000000fff000 -#define BM_12_23 BM_23_12 -#define BM_24_12 0x0000000001fff000 -#define BM_12_24 BM_24_12 -#define BM_25_12 0x0000000003fff000 -#define BM_12_25 BM_25_12 -#define BM_26_12 0x0000000007fff000 -#define BM_12_26 BM_26_12 -#define BM_27_12 0x000000000ffff000 -#define BM_12_27 BM_27_12 -#define BM_28_12 0x000000001ffff000 -#define BM_12_28 BM_28_12 -#define BM_29_12 0x000000003ffff000 -#define BM_12_29 BM_29_12 -#define BM_30_12 0x000000007ffff000 -#define BM_12_30 BM_30_12 -#define BM_31_12 0x00000000fffff000 -#define BM_12_31 BM_31_12 -#define BM_32_12 0x00000001fffff000 -#define BM_12_32 BM_32_12 -#define BM_33_12 0x00000003fffff000 -#define BM_12_33 BM_33_12 -#define BM_34_12 0x00000007fffff000 -#define BM_12_34 BM_34_12 -#define BM_35_12 0x0000000ffffff000 -#define BM_12_35 BM_35_12 -#define BM_36_12 0x0000001ffffff000 -#define BM_12_36 BM_36_12 -#define BM_37_12 0x0000003ffffff000 -#define BM_12_37 BM_37_12 -#define BM_38_12 0x0000007ffffff000 -#define BM_12_38 BM_38_12 -#define BM_39_12 0x000000fffffff000 -#define BM_12_39 BM_39_12 -#define BM_40_12 0x000001fffffff000 -#define BM_12_40 BM_40_12 -#define BM_41_12 0x000003fffffff000 -#define BM_12_41 BM_41_12 -#define BM_42_12 0x000007fffffff000 -#define BM_12_42 BM_42_12 -#define BM_43_12 0x00000ffffffff000 -#define BM_12_43 BM_43_12 -#define BM_44_12 0x00001ffffffff000 -#define BM_12_44 BM_44_12 -#define BM_45_12 0x00003ffffffff000 -#define BM_12_45 BM_45_12 -#define BM_46_12 0x00007ffffffff000 -#define BM_12_46 BM_46_12 -#define BM_47_12 0x0000fffffffff000 -#define BM_12_47 BM_47_12 -#define BM_48_12 0x0001fffffffff000 -#define BM_12_48 BM_48_12 -#define BM_49_12 0x0003fffffffff000 -#define BM_12_49 BM_49_12 -#define BM_50_12 0x0007fffffffff000 -#define BM_12_50 BM_50_12 -#define BM_51_12 0x000ffffffffff000 -#define BM_12_51 BM_51_12 -#define BM_52_12 0x001ffffffffff000 -#define BM_12_52 BM_52_12 -#define BM_53_12 0x003ffffffffff000 -#define BM_12_53 BM_53_12 -#define BM_54_12 0x007ffffffffff000 -#define BM_12_54 BM_54_12 -#define BM_55_12 0x00fffffffffff000 -#define BM_12_55 BM_55_12 -#define BM_56_12 0x01fffffffffff000 -#define BM_12_56 BM_56_12 -#define BM_57_12 0x03fffffffffff000 -#define BM_12_57 BM_57_12 -#define BM_58_12 0x07fffffffffff000 -#define BM_12_58 BM_58_12 -#define BM_59_12 0x0ffffffffffff000 -#define BM_12_59 BM_59_12 -#define BM_60_12 0x1ffffffffffff000 -#define BM_12_60 BM_60_12 -#define BM_61_12 0x3ffffffffffff000 -#define BM_12_61 BM_61_12 -#define BM_62_12 0x7ffffffffffff000 -#define BM_12_62 BM_62_12 -#define BM_63_12 0xfffffffffffff000 -#define BM_12_63 BM_63_12 -#define BM_13_13 0x0000000000002000 -#define BM_14_13 0x0000000000006000 -#define BM_13_14 BM_14_13 -#define BM_15_13 0x000000000000e000 -#define BM_13_15 BM_15_13 -#define BM_16_13 0x000000000001e000 -#define BM_13_16 BM_16_13 -#define BM_17_13 0x000000000003e000 -#define BM_13_17 BM_17_13 -#define BM_18_13 0x000000000007e000 -#define BM_13_18 BM_18_13 -#define BM_19_13 0x00000000000fe000 -#define BM_13_19 BM_19_13 -#define BM_20_13 0x00000000001fe000 -#define BM_13_20 BM_20_13 -#define BM_21_13 0x00000000003fe000 -#define BM_13_21 BM_21_13 -#define BM_22_13 0x00000000007fe000 -#define BM_13_22 BM_22_13 -#define BM_23_13 0x0000000000ffe000 -#define BM_13_23 BM_23_13 -#define BM_24_13 0x0000000001ffe000 -#define BM_13_24 BM_24_13 -#define BM_25_13 0x0000000003ffe000 -#define BM_13_25 BM_25_13 -#define BM_26_13 0x0000000007ffe000 -#define BM_13_26 BM_26_13 -#define BM_27_13 0x000000000fffe000 -#define BM_13_27 BM_27_13 -#define BM_28_13 0x000000001fffe000 -#define BM_13_28 BM_28_13 -#define BM_29_13 0x000000003fffe000 -#define BM_13_29 BM_29_13 -#define BM_30_13 0x000000007fffe000 -#define BM_13_30 BM_30_13 -#define BM_31_13 0x00000000ffffe000 -#define BM_13_31 BM_31_13 -#define BM_32_13 0x00000001ffffe000 -#define BM_13_32 BM_32_13 -#define BM_33_13 0x00000003ffffe000 -#define BM_13_33 BM_33_13 -#define BM_34_13 0x00000007ffffe000 -#define BM_13_34 BM_34_13 -#define BM_35_13 0x0000000fffffe000 -#define BM_13_35 BM_35_13 -#define BM_36_13 0x0000001fffffe000 -#define BM_13_36 BM_36_13 -#define BM_37_13 0x0000003fffffe000 -#define BM_13_37 BM_37_13 -#define BM_38_13 0x0000007fffffe000 -#define BM_13_38 BM_38_13 -#define BM_39_13 0x000000ffffffe000 -#define BM_13_39 BM_39_13 -#define BM_40_13 0x000001ffffffe000 -#define BM_13_40 BM_40_13 -#define BM_41_13 0x000003ffffffe000 -#define BM_13_41 BM_41_13 -#define BM_42_13 0x000007ffffffe000 -#define BM_13_42 BM_42_13 -#define BM_43_13 0x00000fffffffe000 -#define BM_13_43 BM_43_13 -#define BM_44_13 0x00001fffffffe000 -#define BM_13_44 BM_44_13 -#define BM_45_13 0x00003fffffffe000 -#define BM_13_45 BM_45_13 -#define BM_46_13 0x00007fffffffe000 -#define BM_13_46 BM_46_13 -#define BM_47_13 0x0000ffffffffe000 -#define BM_13_47 BM_47_13 -#define BM_48_13 0x0001ffffffffe000 -#define BM_13_48 BM_48_13 -#define BM_49_13 0x0003ffffffffe000 -#define BM_13_49 BM_49_13 -#define BM_50_13 0x0007ffffffffe000 -#define BM_13_50 BM_50_13 -#define BM_51_13 0x000fffffffffe000 -#define BM_13_51 BM_51_13 -#define BM_52_13 0x001fffffffffe000 -#define BM_13_52 BM_52_13 -#define BM_53_13 0x003fffffffffe000 -#define BM_13_53 BM_53_13 -#define BM_54_13 0x007fffffffffe000 -#define BM_13_54 BM_54_13 -#define BM_55_13 0x00ffffffffffe000 -#define BM_13_55 BM_55_13 -#define BM_56_13 0x01ffffffffffe000 -#define BM_13_56 BM_56_13 -#define BM_57_13 0x03ffffffffffe000 -#define BM_13_57 BM_57_13 -#define BM_58_13 0x07ffffffffffe000 -#define BM_13_58 BM_58_13 -#define BM_59_13 0x0fffffffffffe000 -#define BM_13_59 BM_59_13 -#define BM_60_13 0x1fffffffffffe000 -#define BM_13_60 BM_60_13 -#define BM_61_13 0x3fffffffffffe000 -#define BM_13_61 BM_61_13 -#define BM_62_13 0x7fffffffffffe000 -#define BM_13_62 BM_62_13 -#define BM_63_13 0xffffffffffffe000 -#define BM_13_63 BM_63_13 -#define BM_14_14 0x0000000000004000 -#define BM_15_14 0x000000000000c000 -#define BM_14_15 BM_15_14 -#define BM_16_14 0x000000000001c000 -#define BM_14_16 BM_16_14 -#define BM_17_14 0x000000000003c000 -#define BM_14_17 BM_17_14 -#define BM_18_14 0x000000000007c000 -#define BM_14_18 BM_18_14 -#define BM_19_14 0x00000000000fc000 -#define BM_14_19 BM_19_14 -#define BM_20_14 0x00000000001fc000 -#define BM_14_20 BM_20_14 -#define BM_21_14 0x00000000003fc000 -#define BM_14_21 BM_21_14 -#define BM_22_14 0x00000000007fc000 -#define BM_14_22 BM_22_14 -#define BM_23_14 0x0000000000ffc000 -#define BM_14_23 BM_23_14 -#define BM_24_14 0x0000000001ffc000 -#define BM_14_24 BM_24_14 -#define BM_25_14 0x0000000003ffc000 -#define BM_14_25 BM_25_14 -#define BM_26_14 0x0000000007ffc000 -#define BM_14_26 BM_26_14 -#define BM_27_14 0x000000000fffc000 -#define BM_14_27 BM_27_14 -#define BM_28_14 0x000000001fffc000 -#define BM_14_28 BM_28_14 -#define BM_29_14 0x000000003fffc000 -#define BM_14_29 BM_29_14 -#define BM_30_14 0x000000007fffc000 -#define BM_14_30 BM_30_14 -#define BM_31_14 0x00000000ffffc000 -#define BM_14_31 BM_31_14 -#define BM_32_14 0x00000001ffffc000 -#define BM_14_32 BM_32_14 -#define BM_33_14 0x00000003ffffc000 -#define BM_14_33 BM_33_14 -#define BM_34_14 0x00000007ffffc000 -#define BM_14_34 BM_34_14 -#define BM_35_14 0x0000000fffffc000 -#define BM_14_35 BM_35_14 -#define BM_36_14 0x0000001fffffc000 -#define BM_14_36 BM_36_14 -#define BM_37_14 0x0000003fffffc000 -#define BM_14_37 BM_37_14 -#define BM_38_14 0x0000007fffffc000 -#define BM_14_38 BM_38_14 -#define BM_39_14 0x000000ffffffc000 -#define BM_14_39 BM_39_14 -#define BM_40_14 0x000001ffffffc000 -#define BM_14_40 BM_40_14 -#define BM_41_14 0x000003ffffffc000 -#define BM_14_41 BM_41_14 -#define BM_42_14 0x000007ffffffc000 -#define BM_14_42 BM_42_14 -#define BM_43_14 0x00000fffffffc000 -#define BM_14_43 BM_43_14 -#define BM_44_14 0x00001fffffffc000 -#define BM_14_44 BM_44_14 -#define BM_45_14 0x00003fffffffc000 -#define BM_14_45 BM_45_14 -#define BM_46_14 0x00007fffffffc000 -#define BM_14_46 BM_46_14 -#define BM_47_14 0x0000ffffffffc000 -#define BM_14_47 BM_47_14 -#define BM_48_14 0x0001ffffffffc000 -#define BM_14_48 BM_48_14 -#define BM_49_14 0x0003ffffffffc000 -#define BM_14_49 BM_49_14 -#define BM_50_14 0x0007ffffffffc000 -#define BM_14_50 BM_50_14 -#define BM_51_14 0x000fffffffffc000 -#define BM_14_51 BM_51_14 -#define BM_52_14 0x001fffffffffc000 -#define BM_14_52 BM_52_14 -#define BM_53_14 0x003fffffffffc000 -#define BM_14_53 BM_53_14 -#define BM_54_14 0x007fffffffffc000 -#define BM_14_54 BM_54_14 -#define BM_55_14 0x00ffffffffffc000 -#define BM_14_55 BM_55_14 -#define BM_56_14 0x01ffffffffffc000 -#define BM_14_56 BM_56_14 -#define BM_57_14 0x03ffffffffffc000 -#define BM_14_57 BM_57_14 -#define BM_58_14 0x07ffffffffffc000 -#define BM_14_58 BM_58_14 -#define BM_59_14 0x0fffffffffffc000 -#define BM_14_59 BM_59_14 -#define BM_60_14 0x1fffffffffffc000 -#define BM_14_60 BM_60_14 -#define BM_61_14 0x3fffffffffffc000 -#define BM_14_61 BM_61_14 -#define BM_62_14 0x7fffffffffffc000 -#define BM_14_62 BM_62_14 -#define BM_63_14 0xffffffffffffc000 -#define BM_14_63 BM_63_14 -#define BM_15_15 0x0000000000008000 -#define BM_16_15 0x0000000000018000 -#define BM_15_16 BM_16_15 -#define BM_17_15 0x0000000000038000 -#define BM_15_17 BM_17_15 -#define BM_18_15 0x0000000000078000 -#define BM_15_18 BM_18_15 -#define BM_19_15 0x00000000000f8000 -#define BM_15_19 BM_19_15 -#define BM_20_15 0x00000000001f8000 -#define BM_15_20 BM_20_15 -#define BM_21_15 0x00000000003f8000 -#define BM_15_21 BM_21_15 -#define BM_22_15 0x00000000007f8000 -#define BM_15_22 BM_22_15 -#define BM_23_15 0x0000000000ff8000 -#define BM_15_23 BM_23_15 -#define BM_24_15 0x0000000001ff8000 -#define BM_15_24 BM_24_15 -#define BM_25_15 0x0000000003ff8000 -#define BM_15_25 BM_25_15 -#define BM_26_15 0x0000000007ff8000 -#define BM_15_26 BM_26_15 -#define BM_27_15 0x000000000fff8000 -#define BM_15_27 BM_27_15 -#define BM_28_15 0x000000001fff8000 -#define BM_15_28 BM_28_15 -#define BM_29_15 0x000000003fff8000 -#define BM_15_29 BM_29_15 -#define BM_30_15 0x000000007fff8000 -#define BM_15_30 BM_30_15 -#define BM_31_15 0x00000000ffff8000 -#define BM_15_31 BM_31_15 -#define BM_32_15 0x00000001ffff8000 -#define BM_15_32 BM_32_15 -#define BM_33_15 0x00000003ffff8000 -#define BM_15_33 BM_33_15 -#define BM_34_15 0x00000007ffff8000 -#define BM_15_34 BM_34_15 -#define BM_35_15 0x0000000fffff8000 -#define BM_15_35 BM_35_15 -#define BM_36_15 0x0000001fffff8000 -#define BM_15_36 BM_36_15 -#define BM_37_15 0x0000003fffff8000 -#define BM_15_37 BM_37_15 -#define BM_38_15 0x0000007fffff8000 -#define BM_15_38 BM_38_15 -#define BM_39_15 0x000000ffffff8000 -#define BM_15_39 BM_39_15 -#define BM_40_15 0x000001ffffff8000 -#define BM_15_40 BM_40_15 -#define BM_41_15 0x000003ffffff8000 -#define BM_15_41 BM_41_15 -#define BM_42_15 0x000007ffffff8000 -#define BM_15_42 BM_42_15 -#define BM_43_15 0x00000fffffff8000 -#define BM_15_43 BM_43_15 -#define BM_44_15 0x00001fffffff8000 -#define BM_15_44 BM_44_15 -#define BM_45_15 0x00003fffffff8000 -#define BM_15_45 BM_45_15 -#define BM_46_15 0x00007fffffff8000 -#define BM_15_46 BM_46_15 -#define BM_47_15 0x0000ffffffff8000 -#define BM_15_47 BM_47_15 -#define BM_48_15 0x0001ffffffff8000 -#define BM_15_48 BM_48_15 -#define BM_49_15 0x0003ffffffff8000 -#define BM_15_49 BM_49_15 -#define BM_50_15 0x0007ffffffff8000 -#define BM_15_50 BM_50_15 -#define BM_51_15 0x000fffffffff8000 -#define BM_15_51 BM_51_15 -#define BM_52_15 0x001fffffffff8000 -#define BM_15_52 BM_52_15 -#define BM_53_15 0x003fffffffff8000 -#define BM_15_53 BM_53_15 -#define BM_54_15 0x007fffffffff8000 -#define BM_15_54 BM_54_15 -#define BM_55_15 0x00ffffffffff8000 -#define BM_15_55 BM_55_15 -#define BM_56_15 0x01ffffffffff8000 -#define BM_15_56 BM_56_15 -#define BM_57_15 0x03ffffffffff8000 -#define BM_15_57 BM_57_15 -#define BM_58_15 0x07ffffffffff8000 -#define BM_15_58 BM_58_15 -#define BM_59_15 0x0fffffffffff8000 -#define BM_15_59 BM_59_15 -#define BM_60_15 0x1fffffffffff8000 -#define BM_15_60 BM_60_15 -#define BM_61_15 0x3fffffffffff8000 -#define BM_15_61 BM_61_15 -#define BM_62_15 0x7fffffffffff8000 -#define BM_15_62 BM_62_15 -#define BM_63_15 0xffffffffffff8000 -#define BM_15_63 BM_63_15 -#define BM_16_16 0x0000000000010000 -#define BM_17_16 0x0000000000030000 -#define BM_16_17 BM_17_16 -#define BM_18_16 0x0000000000070000 -#define BM_16_18 BM_18_16 -#define BM_19_16 0x00000000000f0000 -#define BM_16_19 BM_19_16 -#define BM_20_16 0x00000000001f0000 -#define BM_16_20 BM_20_16 -#define BM_21_16 0x00000000003f0000 -#define BM_16_21 BM_21_16 -#define BM_22_16 0x00000000007f0000 -#define BM_16_22 BM_22_16 -#define BM_23_16 0x0000000000ff0000 -#define BM_16_23 BM_23_16 -#define BM_24_16 0x0000000001ff0000 -#define BM_16_24 BM_24_16 -#define BM_25_16 0x0000000003ff0000 -#define BM_16_25 BM_25_16 -#define BM_26_16 0x0000000007ff0000 -#define BM_16_26 BM_26_16 -#define BM_27_16 0x000000000fff0000 -#define BM_16_27 BM_27_16 -#define BM_28_16 0x000000001fff0000 -#define BM_16_28 BM_28_16 -#define BM_29_16 0x000000003fff0000 -#define BM_16_29 BM_29_16 -#define BM_30_16 0x000000007fff0000 -#define BM_16_30 BM_30_16 -#define BM_31_16 0x00000000ffff0000 -#define BM_16_31 BM_31_16 -#define BM_32_16 0x00000001ffff0000 -#define BM_16_32 BM_32_16 -#define BM_33_16 0x00000003ffff0000 -#define BM_16_33 BM_33_16 -#define BM_34_16 0x00000007ffff0000 -#define BM_16_34 BM_34_16 -#define BM_35_16 0x0000000fffff0000 -#define BM_16_35 BM_35_16 -#define BM_36_16 0x0000001fffff0000 -#define BM_16_36 BM_36_16 -#define BM_37_16 0x0000003fffff0000 -#define BM_16_37 BM_37_16 -#define BM_38_16 0x0000007fffff0000 -#define BM_16_38 BM_38_16 -#define BM_39_16 0x000000ffffff0000 -#define BM_16_39 BM_39_16 -#define BM_40_16 0x000001ffffff0000 -#define BM_16_40 BM_40_16 -#define BM_41_16 0x000003ffffff0000 -#define BM_16_41 BM_41_16 -#define BM_42_16 0x000007ffffff0000 -#define BM_16_42 BM_42_16 -#define BM_43_16 0x00000fffffff0000 -#define BM_16_43 BM_43_16 -#define BM_44_16 0x00001fffffff0000 -#define BM_16_44 BM_44_16 -#define BM_45_16 0x00003fffffff0000 -#define BM_16_45 BM_45_16 -#define BM_46_16 0x00007fffffff0000 -#define BM_16_46 BM_46_16 -#define BM_47_16 0x0000ffffffff0000 -#define BM_16_47 BM_47_16 -#define BM_48_16 0x0001ffffffff0000 -#define BM_16_48 BM_48_16 -#define BM_49_16 0x0003ffffffff0000 -#define BM_16_49 BM_49_16 -#define BM_50_16 0x0007ffffffff0000 -#define BM_16_50 BM_50_16 -#define BM_51_16 0x000fffffffff0000 -#define BM_16_51 BM_51_16 -#define BM_52_16 0x001fffffffff0000 -#define BM_16_52 BM_52_16 -#define BM_53_16 0x003fffffffff0000 -#define BM_16_53 BM_53_16 -#define BM_54_16 0x007fffffffff0000 -#define BM_16_54 BM_54_16 -#define BM_55_16 0x00ffffffffff0000 -#define BM_16_55 BM_55_16 -#define BM_56_16 0x01ffffffffff0000 -#define BM_16_56 BM_56_16 -#define BM_57_16 0x03ffffffffff0000 -#define BM_16_57 BM_57_16 -#define BM_58_16 0x07ffffffffff0000 -#define BM_16_58 BM_58_16 -#define BM_59_16 0x0fffffffffff0000 -#define BM_16_59 BM_59_16 -#define BM_60_16 0x1fffffffffff0000 -#define BM_16_60 BM_60_16 -#define BM_61_16 0x3fffffffffff0000 -#define BM_16_61 BM_61_16 -#define BM_62_16 0x7fffffffffff0000 -#define BM_16_62 BM_62_16 -#define BM_63_16 0xffffffffffff0000 -#define BM_16_63 BM_63_16 -#define BM_17_17 0x0000000000020000 -#define BM_18_17 0x0000000000060000 -#define BM_17_18 BM_18_17 -#define BM_19_17 0x00000000000e0000 -#define BM_17_19 BM_19_17 -#define BM_20_17 0x00000000001e0000 -#define BM_17_20 BM_20_17 -#define BM_21_17 0x00000000003e0000 -#define BM_17_21 BM_21_17 -#define BM_22_17 0x00000000007e0000 -#define BM_17_22 BM_22_17 -#define BM_23_17 0x0000000000fe0000 -#define BM_17_23 BM_23_17 -#define BM_24_17 0x0000000001fe0000 -#define BM_17_24 BM_24_17 -#define BM_25_17 0x0000000003fe0000 -#define BM_17_25 BM_25_17 -#define BM_26_17 0x0000000007fe0000 -#define BM_17_26 BM_26_17 -#define BM_27_17 0x000000000ffe0000 -#define BM_17_27 BM_27_17 -#define BM_28_17 0x000000001ffe0000 -#define BM_17_28 BM_28_17 -#define BM_29_17 0x000000003ffe0000 -#define BM_17_29 BM_29_17 -#define BM_30_17 0x000000007ffe0000 -#define BM_17_30 BM_30_17 -#define BM_31_17 0x00000000fffe0000 -#define BM_17_31 BM_31_17 -#define BM_32_17 0x00000001fffe0000 -#define BM_17_32 BM_32_17 -#define BM_33_17 0x00000003fffe0000 -#define BM_17_33 BM_33_17 -#define BM_34_17 0x00000007fffe0000 -#define BM_17_34 BM_34_17 -#define BM_35_17 0x0000000ffffe0000 -#define BM_17_35 BM_35_17 -#define BM_36_17 0x0000001ffffe0000 -#define BM_17_36 BM_36_17 -#define BM_37_17 0x0000003ffffe0000 -#define BM_17_37 BM_37_17 -#define BM_38_17 0x0000007ffffe0000 -#define BM_17_38 BM_38_17 -#define BM_39_17 0x000000fffffe0000 -#define BM_17_39 BM_39_17 -#define BM_40_17 0x000001fffffe0000 -#define BM_17_40 BM_40_17 -#define BM_41_17 0x000003fffffe0000 -#define BM_17_41 BM_41_17 -#define BM_42_17 0x000007fffffe0000 -#define BM_17_42 BM_42_17 -#define BM_43_17 0x00000ffffffe0000 -#define BM_17_43 BM_43_17 -#define BM_44_17 0x00001ffffffe0000 -#define BM_17_44 BM_44_17 -#define BM_45_17 0x00003ffffffe0000 -#define BM_17_45 BM_45_17 -#define BM_46_17 0x00007ffffffe0000 -#define BM_17_46 BM_46_17 -#define BM_47_17 0x0000fffffffe0000 -#define BM_17_47 BM_47_17 -#define BM_48_17 0x0001fffffffe0000 -#define BM_17_48 BM_48_17 -#define BM_49_17 0x0003fffffffe0000 -#define BM_17_49 BM_49_17 -#define BM_50_17 0x0007fffffffe0000 -#define BM_17_50 BM_50_17 -#define BM_51_17 0x000ffffffffe0000 -#define BM_17_51 BM_51_17 -#define BM_52_17 0x001ffffffffe0000 -#define BM_17_52 BM_52_17 -#define BM_53_17 0x003ffffffffe0000 -#define BM_17_53 BM_53_17 -#define BM_54_17 0x007ffffffffe0000 -#define BM_17_54 BM_54_17 -#define BM_55_17 0x00fffffffffe0000 -#define BM_17_55 BM_55_17 -#define BM_56_17 0x01fffffffffe0000 -#define BM_17_56 BM_56_17 -#define BM_57_17 0x03fffffffffe0000 -#define BM_17_57 BM_57_17 -#define BM_58_17 0x07fffffffffe0000 -#define BM_17_58 BM_58_17 -#define BM_59_17 0x0ffffffffffe0000 -#define BM_17_59 BM_59_17 -#define BM_60_17 0x1ffffffffffe0000 -#define BM_17_60 BM_60_17 -#define BM_61_17 0x3ffffffffffe0000 -#define BM_17_61 BM_61_17 -#define BM_62_17 0x7ffffffffffe0000 -#define BM_17_62 BM_62_17 -#define BM_63_17 0xfffffffffffe0000 -#define BM_17_63 BM_63_17 -#define BM_18_18 0x0000000000040000 -#define BM_19_18 0x00000000000c0000 -#define BM_18_19 BM_19_18 -#define BM_20_18 0x00000000001c0000 -#define BM_18_20 BM_20_18 -#define BM_21_18 0x00000000003c0000 -#define BM_18_21 BM_21_18 -#define BM_22_18 0x00000000007c0000 -#define BM_18_22 BM_22_18 -#define BM_23_18 0x0000000000fc0000 -#define BM_18_23 BM_23_18 -#define BM_24_18 0x0000000001fc0000 -#define BM_18_24 BM_24_18 -#define BM_25_18 0x0000000003fc0000 -#define BM_18_25 BM_25_18 -#define BM_26_18 0x0000000007fc0000 -#define BM_18_26 BM_26_18 -#define BM_27_18 0x000000000ffc0000 -#define BM_18_27 BM_27_18 -#define BM_28_18 0x000000001ffc0000 -#define BM_18_28 BM_28_18 -#define BM_29_18 0x000000003ffc0000 -#define BM_18_29 BM_29_18 -#define BM_30_18 0x000000007ffc0000 -#define BM_18_30 BM_30_18 -#define BM_31_18 0x00000000fffc0000 -#define BM_18_31 BM_31_18 -#define BM_32_18 0x00000001fffc0000 -#define BM_18_32 BM_32_18 -#define BM_33_18 0x00000003fffc0000 -#define BM_18_33 BM_33_18 -#define BM_34_18 0x00000007fffc0000 -#define BM_18_34 BM_34_18 -#define BM_35_18 0x0000000ffffc0000 -#define BM_18_35 BM_35_18 -#define BM_36_18 0x0000001ffffc0000 -#define BM_18_36 BM_36_18 -#define BM_37_18 0x0000003ffffc0000 -#define BM_18_37 BM_37_18 -#define BM_38_18 0x0000007ffffc0000 -#define BM_18_38 BM_38_18 -#define BM_39_18 0x000000fffffc0000 -#define BM_18_39 BM_39_18 -#define BM_40_18 0x000001fffffc0000 -#define BM_18_40 BM_40_18 -#define BM_41_18 0x000003fffffc0000 -#define BM_18_41 BM_41_18 -#define BM_42_18 0x000007fffffc0000 -#define BM_18_42 BM_42_18 -#define BM_43_18 0x00000ffffffc0000 -#define BM_18_43 BM_43_18 -#define BM_44_18 0x00001ffffffc0000 -#define BM_18_44 BM_44_18 -#define BM_45_18 0x00003ffffffc0000 -#define BM_18_45 BM_45_18 -#define BM_46_18 0x00007ffffffc0000 -#define BM_18_46 BM_46_18 -#define BM_47_18 0x0000fffffffc0000 -#define BM_18_47 BM_47_18 -#define BM_48_18 0x0001fffffffc0000 -#define BM_18_48 BM_48_18 -#define BM_49_18 0x0003fffffffc0000 -#define BM_18_49 BM_49_18 -#define BM_50_18 0x0007fffffffc0000 -#define BM_18_50 BM_50_18 -#define BM_51_18 0x000ffffffffc0000 -#define BM_18_51 BM_51_18 -#define BM_52_18 0x001ffffffffc0000 -#define BM_18_52 BM_52_18 -#define BM_53_18 0x003ffffffffc0000 -#define BM_18_53 BM_53_18 -#define BM_54_18 0x007ffffffffc0000 -#define BM_18_54 BM_54_18 -#define BM_55_18 0x00fffffffffc0000 -#define BM_18_55 BM_55_18 -#define BM_56_18 0x01fffffffffc0000 -#define BM_18_56 BM_56_18 -#define BM_57_18 0x03fffffffffc0000 -#define BM_18_57 BM_57_18 -#define BM_58_18 0x07fffffffffc0000 -#define BM_18_58 BM_58_18 -#define BM_59_18 0x0ffffffffffc0000 -#define BM_18_59 BM_59_18 -#define BM_60_18 0x1ffffffffffc0000 -#define BM_18_60 BM_60_18 -#define BM_61_18 0x3ffffffffffc0000 -#define BM_18_61 BM_61_18 -#define BM_62_18 0x7ffffffffffc0000 -#define BM_18_62 BM_62_18 -#define BM_63_18 0xfffffffffffc0000 -#define BM_18_63 BM_63_18 -#define BM_19_19 0x0000000000080000 -#define BM_20_19 0x0000000000180000 -#define BM_19_20 BM_20_19 -#define BM_21_19 0x0000000000380000 -#define BM_19_21 BM_21_19 -#define BM_22_19 0x0000000000780000 -#define BM_19_22 BM_22_19 -#define BM_23_19 0x0000000000f80000 -#define BM_19_23 BM_23_19 -#define BM_24_19 0x0000000001f80000 -#define BM_19_24 BM_24_19 -#define BM_25_19 0x0000000003f80000 -#define BM_19_25 BM_25_19 -#define BM_26_19 0x0000000007f80000 -#define BM_19_26 BM_26_19 -#define BM_27_19 0x000000000ff80000 -#define BM_19_27 BM_27_19 -#define BM_28_19 0x000000001ff80000 -#define BM_19_28 BM_28_19 -#define BM_29_19 0x000000003ff80000 -#define BM_19_29 BM_29_19 -#define BM_30_19 0x000000007ff80000 -#define BM_19_30 BM_30_19 -#define BM_31_19 0x00000000fff80000 -#define BM_19_31 BM_31_19 -#define BM_32_19 0x00000001fff80000 -#define BM_19_32 BM_32_19 -#define BM_33_19 0x00000003fff80000 -#define BM_19_33 BM_33_19 -#define BM_34_19 0x00000007fff80000 -#define BM_19_34 BM_34_19 -#define BM_35_19 0x0000000ffff80000 -#define BM_19_35 BM_35_19 -#define BM_36_19 0x0000001ffff80000 -#define BM_19_36 BM_36_19 -#define BM_37_19 0x0000003ffff80000 -#define BM_19_37 BM_37_19 -#define BM_38_19 0x0000007ffff80000 -#define BM_19_38 BM_38_19 -#define BM_39_19 0x000000fffff80000 -#define BM_19_39 BM_39_19 -#define BM_40_19 0x000001fffff80000 -#define BM_19_40 BM_40_19 -#define BM_41_19 0x000003fffff80000 -#define BM_19_41 BM_41_19 -#define BM_42_19 0x000007fffff80000 -#define BM_19_42 BM_42_19 -#define BM_43_19 0x00000ffffff80000 -#define BM_19_43 BM_43_19 -#define BM_44_19 0x00001ffffff80000 -#define BM_19_44 BM_44_19 -#define BM_45_19 0x00003ffffff80000 -#define BM_19_45 BM_45_19 -#define BM_46_19 0x00007ffffff80000 -#define BM_19_46 BM_46_19 -#define BM_47_19 0x0000fffffff80000 -#define BM_19_47 BM_47_19 -#define BM_48_19 0x0001fffffff80000 -#define BM_19_48 BM_48_19 -#define BM_49_19 0x0003fffffff80000 -#define BM_19_49 BM_49_19 -#define BM_50_19 0x0007fffffff80000 -#define BM_19_50 BM_50_19 -#define BM_51_19 0x000ffffffff80000 -#define BM_19_51 BM_51_19 -#define BM_52_19 0x001ffffffff80000 -#define BM_19_52 BM_52_19 -#define BM_53_19 0x003ffffffff80000 -#define BM_19_53 BM_53_19 -#define BM_54_19 0x007ffffffff80000 -#define BM_19_54 BM_54_19 -#define BM_55_19 0x00fffffffff80000 -#define BM_19_55 BM_55_19 -#define BM_56_19 0x01fffffffff80000 -#define BM_19_56 BM_56_19 -#define BM_57_19 0x03fffffffff80000 -#define BM_19_57 BM_57_19 -#define BM_58_19 0x07fffffffff80000 -#define BM_19_58 BM_58_19 -#define BM_59_19 0x0ffffffffff80000 -#define BM_19_59 BM_59_19 -#define BM_60_19 0x1ffffffffff80000 -#define BM_19_60 BM_60_19 -#define BM_61_19 0x3ffffffffff80000 -#define BM_19_61 BM_61_19 -#define BM_62_19 0x7ffffffffff80000 -#define BM_19_62 BM_62_19 -#define BM_63_19 0xfffffffffff80000 -#define BM_19_63 BM_63_19 -#define BM_20_20 0x0000000000100000 -#define BM_21_20 0x0000000000300000 -#define BM_20_21 BM_21_20 -#define BM_22_20 0x0000000000700000 -#define BM_20_22 BM_22_20 -#define BM_23_20 0x0000000000f00000 -#define BM_20_23 BM_23_20 -#define BM_24_20 0x0000000001f00000 -#define BM_20_24 BM_24_20 -#define BM_25_20 0x0000000003f00000 -#define BM_20_25 BM_25_20 -#define BM_26_20 0x0000000007f00000 -#define BM_20_26 BM_26_20 -#define BM_27_20 0x000000000ff00000 -#define BM_20_27 BM_27_20 -#define BM_28_20 0x000000001ff00000 -#define BM_20_28 BM_28_20 -#define BM_29_20 0x000000003ff00000 -#define BM_20_29 BM_29_20 -#define BM_30_20 0x000000007ff00000 -#define BM_20_30 BM_30_20 -#define BM_31_20 0x00000000fff00000 -#define BM_20_31 BM_31_20 -#define BM_32_20 0x00000001fff00000 -#define BM_20_32 BM_32_20 -#define BM_33_20 0x00000003fff00000 -#define BM_20_33 BM_33_20 -#define BM_34_20 0x00000007fff00000 -#define BM_20_34 BM_34_20 -#define BM_35_20 0x0000000ffff00000 -#define BM_20_35 BM_35_20 -#define BM_36_20 0x0000001ffff00000 -#define BM_20_36 BM_36_20 -#define BM_37_20 0x0000003ffff00000 -#define BM_20_37 BM_37_20 -#define BM_38_20 0x0000007ffff00000 -#define BM_20_38 BM_38_20 -#define BM_39_20 0x000000fffff00000 -#define BM_20_39 BM_39_20 -#define BM_40_20 0x000001fffff00000 -#define BM_20_40 BM_40_20 -#define BM_41_20 0x000003fffff00000 -#define BM_20_41 BM_41_20 -#define BM_42_20 0x000007fffff00000 -#define BM_20_42 BM_42_20 -#define BM_43_20 0x00000ffffff00000 -#define BM_20_43 BM_43_20 -#define BM_44_20 0x00001ffffff00000 -#define BM_20_44 BM_44_20 -#define BM_45_20 0x00003ffffff00000 -#define BM_20_45 BM_45_20 -#define BM_46_20 0x00007ffffff00000 -#define BM_20_46 BM_46_20 -#define BM_47_20 0x0000fffffff00000 -#define BM_20_47 BM_47_20 -#define BM_48_20 0x0001fffffff00000 -#define BM_20_48 BM_48_20 -#define BM_49_20 0x0003fffffff00000 -#define BM_20_49 BM_49_20 -#define BM_50_20 0x0007fffffff00000 -#define BM_20_50 BM_50_20 -#define BM_51_20 0x000ffffffff00000 -#define BM_20_51 BM_51_20 -#define BM_52_20 0x001ffffffff00000 -#define BM_20_52 BM_52_20 -#define BM_53_20 0x003ffffffff00000 -#define BM_20_53 BM_53_20 -#define BM_54_20 0x007ffffffff00000 -#define BM_20_54 BM_54_20 -#define BM_55_20 0x00fffffffff00000 -#define BM_20_55 BM_55_20 -#define BM_56_20 0x01fffffffff00000 -#define BM_20_56 BM_56_20 -#define BM_57_20 0x03fffffffff00000 -#define BM_20_57 BM_57_20 -#define BM_58_20 0x07fffffffff00000 -#define BM_20_58 BM_58_20 -#define BM_59_20 0x0ffffffffff00000 -#define BM_20_59 BM_59_20 -#define BM_60_20 0x1ffffffffff00000 -#define BM_20_60 BM_60_20 -#define BM_61_20 0x3ffffffffff00000 -#define BM_20_61 BM_61_20 -#define BM_62_20 0x7ffffffffff00000 -#define BM_20_62 BM_62_20 -#define BM_63_20 0xfffffffffff00000 -#define BM_20_63 BM_63_20 -#define BM_21_21 0x0000000000200000 -#define BM_22_21 0x0000000000600000 -#define BM_21_22 BM_22_21 -#define BM_23_21 0x0000000000e00000 -#define BM_21_23 BM_23_21 -#define BM_24_21 0x0000000001e00000 -#define BM_21_24 BM_24_21 -#define BM_25_21 0x0000000003e00000 -#define BM_21_25 BM_25_21 -#define BM_26_21 0x0000000007e00000 -#define BM_21_26 BM_26_21 -#define BM_27_21 0x000000000fe00000 -#define BM_21_27 BM_27_21 -#define BM_28_21 0x000000001fe00000 -#define BM_21_28 BM_28_21 -#define BM_29_21 0x000000003fe00000 -#define BM_21_29 BM_29_21 -#define BM_30_21 0x000000007fe00000 -#define BM_21_30 BM_30_21 -#define BM_31_21 0x00000000ffe00000 -#define BM_21_31 BM_31_21 -#define BM_32_21 0x00000001ffe00000 -#define BM_21_32 BM_32_21 -#define BM_33_21 0x00000003ffe00000 -#define BM_21_33 BM_33_21 -#define BM_34_21 0x00000007ffe00000 -#define BM_21_34 BM_34_21 -#define BM_35_21 0x0000000fffe00000 -#define BM_21_35 BM_35_21 -#define BM_36_21 0x0000001fffe00000 -#define BM_21_36 BM_36_21 -#define BM_37_21 0x0000003fffe00000 -#define BM_21_37 BM_37_21 -#define BM_38_21 0x0000007fffe00000 -#define BM_21_38 BM_38_21 -#define BM_39_21 0x000000ffffe00000 -#define BM_21_39 BM_39_21 -#define BM_40_21 0x000001ffffe00000 -#define BM_21_40 BM_40_21 -#define BM_41_21 0x000003ffffe00000 -#define BM_21_41 BM_41_21 -#define BM_42_21 0x000007ffffe00000 -#define BM_21_42 BM_42_21 -#define BM_43_21 0x00000fffffe00000 -#define BM_21_43 BM_43_21 -#define BM_44_21 0x00001fffffe00000 -#define BM_21_44 BM_44_21 -#define BM_45_21 0x00003fffffe00000 -#define BM_21_45 BM_45_21 -#define BM_46_21 0x00007fffffe00000 -#define BM_21_46 BM_46_21 -#define BM_47_21 0x0000ffffffe00000 -#define BM_21_47 BM_47_21 -#define BM_48_21 0x0001ffffffe00000 -#define BM_21_48 BM_48_21 -#define BM_49_21 0x0003ffffffe00000 -#define BM_21_49 BM_49_21 -#define BM_50_21 0x0007ffffffe00000 -#define BM_21_50 BM_50_21 -#define BM_51_21 0x000fffffffe00000 -#define BM_21_51 BM_51_21 -#define BM_52_21 0x001fffffffe00000 -#define BM_21_52 BM_52_21 -#define BM_53_21 0x003fffffffe00000 -#define BM_21_53 BM_53_21 -#define BM_54_21 0x007fffffffe00000 -#define BM_21_54 BM_54_21 -#define BM_55_21 0x00ffffffffe00000 -#define BM_21_55 BM_55_21 -#define BM_56_21 0x01ffffffffe00000 -#define BM_21_56 BM_56_21 -#define BM_57_21 0x03ffffffffe00000 -#define BM_21_57 BM_57_21 -#define BM_58_21 0x07ffffffffe00000 -#define BM_21_58 BM_58_21 -#define BM_59_21 0x0fffffffffe00000 -#define BM_21_59 BM_59_21 -#define BM_60_21 0x1fffffffffe00000 -#define BM_21_60 BM_60_21 -#define BM_61_21 0x3fffffffffe00000 -#define BM_21_61 BM_61_21 -#define BM_62_21 0x7fffffffffe00000 -#define BM_21_62 BM_62_21 -#define BM_63_21 0xffffffffffe00000 -#define BM_21_63 BM_63_21 -#define BM_22_22 0x0000000000400000 -#define BM_23_22 0x0000000000c00000 -#define BM_22_23 BM_23_22 -#define BM_24_22 0x0000000001c00000 -#define BM_22_24 BM_24_22 -#define BM_25_22 0x0000000003c00000 -#define BM_22_25 BM_25_22 -#define BM_26_22 0x0000000007c00000 -#define BM_22_26 BM_26_22 -#define BM_27_22 0x000000000fc00000 -#define BM_22_27 BM_27_22 -#define BM_28_22 0x000000001fc00000 -#define BM_22_28 BM_28_22 -#define BM_29_22 0x000000003fc00000 -#define BM_22_29 BM_29_22 -#define BM_30_22 0x000000007fc00000 -#define BM_22_30 BM_30_22 -#define BM_31_22 0x00000000ffc00000 -#define BM_22_31 BM_31_22 -#define BM_32_22 0x00000001ffc00000 -#define BM_22_32 BM_32_22 -#define BM_33_22 0x00000003ffc00000 -#define BM_22_33 BM_33_22 -#define BM_34_22 0x00000007ffc00000 -#define BM_22_34 BM_34_22 -#define BM_35_22 0x0000000fffc00000 -#define BM_22_35 BM_35_22 -#define BM_36_22 0x0000001fffc00000 -#define BM_22_36 BM_36_22 -#define BM_37_22 0x0000003fffc00000 -#define BM_22_37 BM_37_22 -#define BM_38_22 0x0000007fffc00000 -#define BM_22_38 BM_38_22 -#define BM_39_22 0x000000ffffc00000 -#define BM_22_39 BM_39_22 -#define BM_40_22 0x000001ffffc00000 -#define BM_22_40 BM_40_22 -#define BM_41_22 0x000003ffffc00000 -#define BM_22_41 BM_41_22 -#define BM_42_22 0x000007ffffc00000 -#define BM_22_42 BM_42_22 -#define BM_43_22 0x00000fffffc00000 -#define BM_22_43 BM_43_22 -#define BM_44_22 0x00001fffffc00000 -#define BM_22_44 BM_44_22 -#define BM_45_22 0x00003fffffc00000 -#define BM_22_45 BM_45_22 -#define BM_46_22 0x00007fffffc00000 -#define BM_22_46 BM_46_22 -#define BM_47_22 0x0000ffffffc00000 -#define BM_22_47 BM_47_22 -#define BM_48_22 0x0001ffffffc00000 -#define BM_22_48 BM_48_22 -#define BM_49_22 0x0003ffffffc00000 -#define BM_22_49 BM_49_22 -#define BM_50_22 0x0007ffffffc00000 -#define BM_22_50 BM_50_22 -#define BM_51_22 0x000fffffffc00000 -#define BM_22_51 BM_51_22 -#define BM_52_22 0x001fffffffc00000 -#define BM_22_52 BM_52_22 -#define BM_53_22 0x003fffffffc00000 -#define BM_22_53 BM_53_22 -#define BM_54_22 0x007fffffffc00000 -#define BM_22_54 BM_54_22 -#define BM_55_22 0x00ffffffffc00000 -#define BM_22_55 BM_55_22 -#define BM_56_22 0x01ffffffffc00000 -#define BM_22_56 BM_56_22 -#define BM_57_22 0x03ffffffffc00000 -#define BM_22_57 BM_57_22 -#define BM_58_22 0x07ffffffffc00000 -#define BM_22_58 BM_58_22 -#define BM_59_22 0x0fffffffffc00000 -#define BM_22_59 BM_59_22 -#define BM_60_22 0x1fffffffffc00000 -#define BM_22_60 BM_60_22 -#define BM_61_22 0x3fffffffffc00000 -#define BM_22_61 BM_61_22 -#define BM_62_22 0x7fffffffffc00000 -#define BM_22_62 BM_62_22 -#define BM_63_22 0xffffffffffc00000 -#define BM_22_63 BM_63_22 -#define BM_23_23 0x0000000000800000 -#define BM_24_23 0x0000000001800000 -#define BM_23_24 BM_24_23 -#define BM_25_23 0x0000000003800000 -#define BM_23_25 BM_25_23 -#define BM_26_23 0x0000000007800000 -#define BM_23_26 BM_26_23 -#define BM_27_23 0x000000000f800000 -#define BM_23_27 BM_27_23 -#define BM_28_23 0x000000001f800000 -#define BM_23_28 BM_28_23 -#define BM_29_23 0x000000003f800000 -#define BM_23_29 BM_29_23 -#define BM_30_23 0x000000007f800000 -#define BM_23_30 BM_30_23 -#define BM_31_23 0x00000000ff800000 -#define BM_23_31 BM_31_23 -#define BM_32_23 0x00000001ff800000 -#define BM_23_32 BM_32_23 -#define BM_33_23 0x00000003ff800000 -#define BM_23_33 BM_33_23 -#define BM_34_23 0x00000007ff800000 -#define BM_23_34 BM_34_23 -#define BM_35_23 0x0000000fff800000 -#define BM_23_35 BM_35_23 -#define BM_36_23 0x0000001fff800000 -#define BM_23_36 BM_36_23 -#define BM_37_23 0x0000003fff800000 -#define BM_23_37 BM_37_23 -#define BM_38_23 0x0000007fff800000 -#define BM_23_38 BM_38_23 -#define BM_39_23 0x000000ffff800000 -#define BM_23_39 BM_39_23 -#define BM_40_23 0x000001ffff800000 -#define BM_23_40 BM_40_23 -#define BM_41_23 0x000003ffff800000 -#define BM_23_41 BM_41_23 -#define BM_42_23 0x000007ffff800000 -#define BM_23_42 BM_42_23 -#define BM_43_23 0x00000fffff800000 -#define BM_23_43 BM_43_23 -#define BM_44_23 0x00001fffff800000 -#define BM_23_44 BM_44_23 -#define BM_45_23 0x00003fffff800000 -#define BM_23_45 BM_45_23 -#define BM_46_23 0x00007fffff800000 -#define BM_23_46 BM_46_23 -#define BM_47_23 0x0000ffffff800000 -#define BM_23_47 BM_47_23 -#define BM_48_23 0x0001ffffff800000 -#define BM_23_48 BM_48_23 -#define BM_49_23 0x0003ffffff800000 -#define BM_23_49 BM_49_23 -#define BM_50_23 0x0007ffffff800000 -#define BM_23_50 BM_50_23 -#define BM_51_23 0x000fffffff800000 -#define BM_23_51 BM_51_23 -#define BM_52_23 0x001fffffff800000 -#define BM_23_52 BM_52_23 -#define BM_53_23 0x003fffffff800000 -#define BM_23_53 BM_53_23 -#define BM_54_23 0x007fffffff800000 -#define BM_23_54 BM_54_23 -#define BM_55_23 0x00ffffffff800000 -#define BM_23_55 BM_55_23 -#define BM_56_23 0x01ffffffff800000 -#define BM_23_56 BM_56_23 -#define BM_57_23 0x03ffffffff800000 -#define BM_23_57 BM_57_23 -#define BM_58_23 0x07ffffffff800000 -#define BM_23_58 BM_58_23 -#define BM_59_23 0x0fffffffff800000 -#define BM_23_59 BM_59_23 -#define BM_60_23 0x1fffffffff800000 -#define BM_23_60 BM_60_23 -#define BM_61_23 0x3fffffffff800000 -#define BM_23_61 BM_61_23 -#define BM_62_23 0x7fffffffff800000 -#define BM_23_62 BM_62_23 -#define BM_63_23 0xffffffffff800000 -#define BM_23_63 BM_63_23 -#define BM_24_24 0x0000000001000000 -#define BM_25_24 0x0000000003000000 -#define BM_24_25 BM_25_24 -#define BM_26_24 0x0000000007000000 -#define BM_24_26 BM_26_24 -#define BM_27_24 0x000000000f000000 -#define BM_24_27 BM_27_24 -#define BM_28_24 0x000000001f000000 -#define BM_24_28 BM_28_24 -#define BM_29_24 0x000000003f000000 -#define BM_24_29 BM_29_24 -#define BM_30_24 0x000000007f000000 -#define BM_24_30 BM_30_24 -#define BM_31_24 0x00000000ff000000 -#define BM_24_31 BM_31_24 -#define BM_32_24 0x00000001ff000000 -#define BM_24_32 BM_32_24 -#define BM_33_24 0x00000003ff000000 -#define BM_24_33 BM_33_24 -#define BM_34_24 0x00000007ff000000 -#define BM_24_34 BM_34_24 -#define BM_35_24 0x0000000fff000000 -#define BM_24_35 BM_35_24 -#define BM_36_24 0x0000001fff000000 -#define BM_24_36 BM_36_24 -#define BM_37_24 0x0000003fff000000 -#define BM_24_37 BM_37_24 -#define BM_38_24 0x0000007fff000000 -#define BM_24_38 BM_38_24 -#define BM_39_24 0x000000ffff000000 -#define BM_24_39 BM_39_24 -#define BM_40_24 0x000001ffff000000 -#define BM_24_40 BM_40_24 -#define BM_41_24 0x000003ffff000000 -#define BM_24_41 BM_41_24 -#define BM_42_24 0x000007ffff000000 -#define BM_24_42 BM_42_24 -#define BM_43_24 0x00000fffff000000 -#define BM_24_43 BM_43_24 -#define BM_44_24 0x00001fffff000000 -#define BM_24_44 BM_44_24 -#define BM_45_24 0x00003fffff000000 -#define BM_24_45 BM_45_24 -#define BM_46_24 0x00007fffff000000 -#define BM_24_46 BM_46_24 -#define BM_47_24 0x0000ffffff000000 -#define BM_24_47 BM_47_24 -#define BM_48_24 0x0001ffffff000000 -#define BM_24_48 BM_48_24 -#define BM_49_24 0x0003ffffff000000 -#define BM_24_49 BM_49_24 -#define BM_50_24 0x0007ffffff000000 -#define BM_24_50 BM_50_24 -#define BM_51_24 0x000fffffff000000 -#define BM_24_51 BM_51_24 -#define BM_52_24 0x001fffffff000000 -#define BM_24_52 BM_52_24 -#define BM_53_24 0x003fffffff000000 -#define BM_24_53 BM_53_24 -#define BM_54_24 0x007fffffff000000 -#define BM_24_54 BM_54_24 -#define BM_55_24 0x00ffffffff000000 -#define BM_24_55 BM_55_24 -#define BM_56_24 0x01ffffffff000000 -#define BM_24_56 BM_56_24 -#define BM_57_24 0x03ffffffff000000 -#define BM_24_57 BM_57_24 -#define BM_58_24 0x07ffffffff000000 -#define BM_24_58 BM_58_24 -#define BM_59_24 0x0fffffffff000000 -#define BM_24_59 BM_59_24 -#define BM_60_24 0x1fffffffff000000 -#define BM_24_60 BM_60_24 -#define BM_61_24 0x3fffffffff000000 -#define BM_24_61 BM_61_24 -#define BM_62_24 0x7fffffffff000000 -#define BM_24_62 BM_62_24 -#define BM_63_24 0xffffffffff000000 -#define BM_24_63 BM_63_24 -#define BM_25_25 0x0000000002000000 -#define BM_26_25 0x0000000006000000 -#define BM_25_26 BM_26_25 -#define BM_27_25 0x000000000e000000 -#define BM_25_27 BM_27_25 -#define BM_28_25 0x000000001e000000 -#define BM_25_28 BM_28_25 -#define BM_29_25 0x000000003e000000 -#define BM_25_29 BM_29_25 -#define BM_30_25 0x000000007e000000 -#define BM_25_30 BM_30_25 -#define BM_31_25 0x00000000fe000000 -#define BM_25_31 BM_31_25 -#define BM_32_25 0x00000001fe000000 -#define BM_25_32 BM_32_25 -#define BM_33_25 0x00000003fe000000 -#define BM_25_33 BM_33_25 -#define BM_34_25 0x00000007fe000000 -#define BM_25_34 BM_34_25 -#define BM_35_25 0x0000000ffe000000 -#define BM_25_35 BM_35_25 -#define BM_36_25 0x0000001ffe000000 -#define BM_25_36 BM_36_25 -#define BM_37_25 0x0000003ffe000000 -#define BM_25_37 BM_37_25 -#define BM_38_25 0x0000007ffe000000 -#define BM_25_38 BM_38_25 -#define BM_39_25 0x000000fffe000000 -#define BM_25_39 BM_39_25 -#define BM_40_25 0x000001fffe000000 -#define BM_25_40 BM_40_25 -#define BM_41_25 0x000003fffe000000 -#define BM_25_41 BM_41_25 -#define BM_42_25 0x000007fffe000000 -#define BM_25_42 BM_42_25 -#define BM_43_25 0x00000ffffe000000 -#define BM_25_43 BM_43_25 -#define BM_44_25 0x00001ffffe000000 -#define BM_25_44 BM_44_25 -#define BM_45_25 0x00003ffffe000000 -#define BM_25_45 BM_45_25 -#define BM_46_25 0x00007ffffe000000 -#define BM_25_46 BM_46_25 -#define BM_47_25 0x0000fffffe000000 -#define BM_25_47 BM_47_25 -#define BM_48_25 0x0001fffffe000000 -#define BM_25_48 BM_48_25 -#define BM_49_25 0x0003fffffe000000 -#define BM_25_49 BM_49_25 -#define BM_50_25 0x0007fffffe000000 -#define BM_25_50 BM_50_25 -#define BM_51_25 0x000ffffffe000000 -#define BM_25_51 BM_51_25 -#define BM_52_25 0x001ffffffe000000 -#define BM_25_52 BM_52_25 -#define BM_53_25 0x003ffffffe000000 -#define BM_25_53 BM_53_25 -#define BM_54_25 0x007ffffffe000000 -#define BM_25_54 BM_54_25 -#define BM_55_25 0x00fffffffe000000 -#define BM_25_55 BM_55_25 -#define BM_56_25 0x01fffffffe000000 -#define BM_25_56 BM_56_25 -#define BM_57_25 0x03fffffffe000000 -#define BM_25_57 BM_57_25 -#define BM_58_25 0x07fffffffe000000 -#define BM_25_58 BM_58_25 -#define BM_59_25 0x0ffffffffe000000 -#define BM_25_59 BM_59_25 -#define BM_60_25 0x1ffffffffe000000 -#define BM_25_60 BM_60_25 -#define BM_61_25 0x3ffffffffe000000 -#define BM_25_61 BM_61_25 -#define BM_62_25 0x7ffffffffe000000 -#define BM_25_62 BM_62_25 -#define BM_63_25 0xfffffffffe000000 -#define BM_25_63 BM_63_25 -#define BM_26_26 0x0000000004000000 -#define BM_27_26 0x000000000c000000 -#define BM_26_27 BM_27_26 -#define BM_28_26 0x000000001c000000 -#define BM_26_28 BM_28_26 -#define BM_29_26 0x000000003c000000 -#define BM_26_29 BM_29_26 -#define BM_30_26 0x000000007c000000 -#define BM_26_30 BM_30_26 -#define BM_31_26 0x00000000fc000000 -#define BM_26_31 BM_31_26 -#define BM_32_26 0x00000001fc000000 -#define BM_26_32 BM_32_26 -#define BM_33_26 0x00000003fc000000 -#define BM_26_33 BM_33_26 -#define BM_34_26 0x00000007fc000000 -#define BM_26_34 BM_34_26 -#define BM_35_26 0x0000000ffc000000 -#define BM_26_35 BM_35_26 -#define BM_36_26 0x0000001ffc000000 -#define BM_26_36 BM_36_26 -#define BM_37_26 0x0000003ffc000000 -#define BM_26_37 BM_37_26 -#define BM_38_26 0x0000007ffc000000 -#define BM_26_38 BM_38_26 -#define BM_39_26 0x000000fffc000000 -#define BM_26_39 BM_39_26 -#define BM_40_26 0x000001fffc000000 -#define BM_26_40 BM_40_26 -#define BM_41_26 0x000003fffc000000 -#define BM_26_41 BM_41_26 -#define BM_42_26 0x000007fffc000000 -#define BM_26_42 BM_42_26 -#define BM_43_26 0x00000ffffc000000 -#define BM_26_43 BM_43_26 -#define BM_44_26 0x00001ffffc000000 -#define BM_26_44 BM_44_26 -#define BM_45_26 0x00003ffffc000000 -#define BM_26_45 BM_45_26 -#define BM_46_26 0x00007ffffc000000 -#define BM_26_46 BM_46_26 -#define BM_47_26 0x0000fffffc000000 -#define BM_26_47 BM_47_26 -#define BM_48_26 0x0001fffffc000000 -#define BM_26_48 BM_48_26 -#define BM_49_26 0x0003fffffc000000 -#define BM_26_49 BM_49_26 -#define BM_50_26 0x0007fffffc000000 -#define BM_26_50 BM_50_26 -#define BM_51_26 0x000ffffffc000000 -#define BM_26_51 BM_51_26 -#define BM_52_26 0x001ffffffc000000 -#define BM_26_52 BM_52_26 -#define BM_53_26 0x003ffffffc000000 -#define BM_26_53 BM_53_26 -#define BM_54_26 0x007ffffffc000000 -#define BM_26_54 BM_54_26 -#define BM_55_26 0x00fffffffc000000 -#define BM_26_55 BM_55_26 -#define BM_56_26 0x01fffffffc000000 -#define BM_26_56 BM_56_26 -#define BM_57_26 0x03fffffffc000000 -#define BM_26_57 BM_57_26 -#define BM_58_26 0x07fffffffc000000 -#define BM_26_58 BM_58_26 -#define BM_59_26 0x0ffffffffc000000 -#define BM_26_59 BM_59_26 -#define BM_60_26 0x1ffffffffc000000 -#define BM_26_60 BM_60_26 -#define BM_61_26 0x3ffffffffc000000 -#define BM_26_61 BM_61_26 -#define BM_62_26 0x7ffffffffc000000 -#define BM_26_62 BM_62_26 -#define BM_63_26 0xfffffffffc000000 -#define BM_26_63 BM_63_26 -#define BM_27_27 0x0000000008000000 -#define BM_28_27 0x0000000018000000 -#define BM_27_28 BM_28_27 -#define BM_29_27 0x0000000038000000 -#define BM_27_29 BM_29_27 -#define BM_30_27 0x0000000078000000 -#define BM_27_30 BM_30_27 -#define BM_31_27 0x00000000f8000000 -#define BM_27_31 BM_31_27 -#define BM_32_27 0x00000001f8000000 -#define BM_27_32 BM_32_27 -#define BM_33_27 0x00000003f8000000 -#define BM_27_33 BM_33_27 -#define BM_34_27 0x00000007f8000000 -#define BM_27_34 BM_34_27 -#define BM_35_27 0x0000000ff8000000 -#define BM_27_35 BM_35_27 -#define BM_36_27 0x0000001ff8000000 -#define BM_27_36 BM_36_27 -#define BM_37_27 0x0000003ff8000000 -#define BM_27_37 BM_37_27 -#define BM_38_27 0x0000007ff8000000 -#define BM_27_38 BM_38_27 -#define BM_39_27 0x000000fff8000000 -#define BM_27_39 BM_39_27 -#define BM_40_27 0x000001fff8000000 -#define BM_27_40 BM_40_27 -#define BM_41_27 0x000003fff8000000 -#define BM_27_41 BM_41_27 -#define BM_42_27 0x000007fff8000000 -#define BM_27_42 BM_42_27 -#define BM_43_27 0x00000ffff8000000 -#define BM_27_43 BM_43_27 -#define BM_44_27 0x00001ffff8000000 -#define BM_27_44 BM_44_27 -#define BM_45_27 0x00003ffff8000000 -#define BM_27_45 BM_45_27 -#define BM_46_27 0x00007ffff8000000 -#define BM_27_46 BM_46_27 -#define BM_47_27 0x0000fffff8000000 -#define BM_27_47 BM_47_27 -#define BM_48_27 0x0001fffff8000000 -#define BM_27_48 BM_48_27 -#define BM_49_27 0x0003fffff8000000 -#define BM_27_49 BM_49_27 -#define BM_50_27 0x0007fffff8000000 -#define BM_27_50 BM_50_27 -#define BM_51_27 0x000ffffff8000000 -#define BM_27_51 BM_51_27 -#define BM_52_27 0x001ffffff8000000 -#define BM_27_52 BM_52_27 -#define BM_53_27 0x003ffffff8000000 -#define BM_27_53 BM_53_27 -#define BM_54_27 0x007ffffff8000000 -#define BM_27_54 BM_54_27 -#define BM_55_27 0x00fffffff8000000 -#define BM_27_55 BM_55_27 -#define BM_56_27 0x01fffffff8000000 -#define BM_27_56 BM_56_27 -#define BM_57_27 0x03fffffff8000000 -#define BM_27_57 BM_57_27 -#define BM_58_27 0x07fffffff8000000 -#define BM_27_58 BM_58_27 -#define BM_59_27 0x0ffffffff8000000 -#define BM_27_59 BM_59_27 -#define BM_60_27 0x1ffffffff8000000 -#define BM_27_60 BM_60_27 -#define BM_61_27 0x3ffffffff8000000 -#define BM_27_61 BM_61_27 -#define BM_62_27 0x7ffffffff8000000 -#define BM_27_62 BM_62_27 -#define BM_63_27 0xfffffffff8000000 -#define BM_27_63 BM_63_27 -#define BM_28_28 0x0000000010000000 -#define BM_29_28 0x0000000030000000 -#define BM_28_29 BM_29_28 -#define BM_30_28 0x0000000070000000 -#define BM_28_30 BM_30_28 -#define BM_31_28 0x00000000f0000000 -#define BM_28_31 BM_31_28 -#define BM_32_28 0x00000001f0000000 -#define BM_28_32 BM_32_28 -#define BM_33_28 0x00000003f0000000 -#define BM_28_33 BM_33_28 -#define BM_34_28 0x00000007f0000000 -#define BM_28_34 BM_34_28 -#define BM_35_28 0x0000000ff0000000 -#define BM_28_35 BM_35_28 -#define BM_36_28 0x0000001ff0000000 -#define BM_28_36 BM_36_28 -#define BM_37_28 0x0000003ff0000000 -#define BM_28_37 BM_37_28 -#define BM_38_28 0x0000007ff0000000 -#define BM_28_38 BM_38_28 -#define BM_39_28 0x000000fff0000000 -#define BM_28_39 BM_39_28 -#define BM_40_28 0x000001fff0000000 -#define BM_28_40 BM_40_28 -#define BM_41_28 0x000003fff0000000 -#define BM_28_41 BM_41_28 -#define BM_42_28 0x000007fff0000000 -#define BM_28_42 BM_42_28 -#define BM_43_28 0x00000ffff0000000 -#define BM_28_43 BM_43_28 -#define BM_44_28 0x00001ffff0000000 -#define BM_28_44 BM_44_28 -#define BM_45_28 0x00003ffff0000000 -#define BM_28_45 BM_45_28 -#define BM_46_28 0x00007ffff0000000 -#define BM_28_46 BM_46_28 -#define BM_47_28 0x0000fffff0000000 -#define BM_28_47 BM_47_28 -#define BM_48_28 0x0001fffff0000000 -#define BM_28_48 BM_48_28 -#define BM_49_28 0x0003fffff0000000 -#define BM_28_49 BM_49_28 -#define BM_50_28 0x0007fffff0000000 -#define BM_28_50 BM_50_28 -#define BM_51_28 0x000ffffff0000000 -#define BM_28_51 BM_51_28 -#define BM_52_28 0x001ffffff0000000 -#define BM_28_52 BM_52_28 -#define BM_53_28 0x003ffffff0000000 -#define BM_28_53 BM_53_28 -#define BM_54_28 0x007ffffff0000000 -#define BM_28_54 BM_54_28 -#define BM_55_28 0x00fffffff0000000 -#define BM_28_55 BM_55_28 -#define BM_56_28 0x01fffffff0000000 -#define BM_28_56 BM_56_28 -#define BM_57_28 0x03fffffff0000000 -#define BM_28_57 BM_57_28 -#define BM_58_28 0x07fffffff0000000 -#define BM_28_58 BM_58_28 -#define BM_59_28 0x0ffffffff0000000 -#define BM_28_59 BM_59_28 -#define BM_60_28 0x1ffffffff0000000 -#define BM_28_60 BM_60_28 -#define BM_61_28 0x3ffffffff0000000 -#define BM_28_61 BM_61_28 -#define BM_62_28 0x7ffffffff0000000 -#define BM_28_62 BM_62_28 -#define BM_63_28 0xfffffffff0000000 -#define BM_28_63 BM_63_28 -#define BM_29_29 0x0000000020000000 -#define BM_30_29 0x0000000060000000 -#define BM_29_30 BM_30_29 -#define BM_31_29 0x00000000e0000000 -#define BM_29_31 BM_31_29 -#define BM_32_29 0x00000001e0000000 -#define BM_29_32 BM_32_29 -#define BM_33_29 0x00000003e0000000 -#define BM_29_33 BM_33_29 -#define BM_34_29 0x00000007e0000000 -#define BM_29_34 BM_34_29 -#define BM_35_29 0x0000000fe0000000 -#define BM_29_35 BM_35_29 -#define BM_36_29 0x0000001fe0000000 -#define BM_29_36 BM_36_29 -#define BM_37_29 0x0000003fe0000000 -#define BM_29_37 BM_37_29 -#define BM_38_29 0x0000007fe0000000 -#define BM_29_38 BM_38_29 -#define BM_39_29 0x000000ffe0000000 -#define BM_29_39 BM_39_29 -#define BM_40_29 0x000001ffe0000000 -#define BM_29_40 BM_40_29 -#define BM_41_29 0x000003ffe0000000 -#define BM_29_41 BM_41_29 -#define BM_42_29 0x000007ffe0000000 -#define BM_29_42 BM_42_29 -#define BM_43_29 0x00000fffe0000000 -#define BM_29_43 BM_43_29 -#define BM_44_29 0x00001fffe0000000 -#define BM_29_44 BM_44_29 -#define BM_45_29 0x00003fffe0000000 -#define BM_29_45 BM_45_29 -#define BM_46_29 0x00007fffe0000000 -#define BM_29_46 BM_46_29 -#define BM_47_29 0x0000ffffe0000000 -#define BM_29_47 BM_47_29 -#define BM_48_29 0x0001ffffe0000000 -#define BM_29_48 BM_48_29 -#define BM_49_29 0x0003ffffe0000000 -#define BM_29_49 BM_49_29 -#define BM_50_29 0x0007ffffe0000000 -#define BM_29_50 BM_50_29 -#define BM_51_29 0x000fffffe0000000 -#define BM_29_51 BM_51_29 -#define BM_52_29 0x001fffffe0000000 -#define BM_29_52 BM_52_29 -#define BM_53_29 0x003fffffe0000000 -#define BM_29_53 BM_53_29 -#define BM_54_29 0x007fffffe0000000 -#define BM_29_54 BM_54_29 -#define BM_55_29 0x00ffffffe0000000 -#define BM_29_55 BM_55_29 -#define BM_56_29 0x01ffffffe0000000 -#define BM_29_56 BM_56_29 -#define BM_57_29 0x03ffffffe0000000 -#define BM_29_57 BM_57_29 -#define BM_58_29 0x07ffffffe0000000 -#define BM_29_58 BM_58_29 -#define BM_59_29 0x0fffffffe0000000 -#define BM_29_59 BM_59_29 -#define BM_60_29 0x1fffffffe0000000 -#define BM_29_60 BM_60_29 -#define BM_61_29 0x3fffffffe0000000 -#define BM_29_61 BM_61_29 -#define BM_62_29 0x7fffffffe0000000 -#define BM_29_62 BM_62_29 -#define BM_63_29 0xffffffffe0000000 -#define BM_29_63 BM_63_29 -#define BM_30_30 0x0000000040000000 -#define BM_31_30 0x00000000c0000000 -#define BM_30_31 BM_31_30 -#define BM_32_30 0x00000001c0000000 -#define BM_30_32 BM_32_30 -#define BM_33_30 0x00000003c0000000 -#define BM_30_33 BM_33_30 -#define BM_34_30 0x00000007c0000000 -#define BM_30_34 BM_34_30 -#define BM_35_30 0x0000000fc0000000 -#define BM_30_35 BM_35_30 -#define BM_36_30 0x0000001fc0000000 -#define BM_30_36 BM_36_30 -#define BM_37_30 0x0000003fc0000000 -#define BM_30_37 BM_37_30 -#define BM_38_30 0x0000007fc0000000 -#define BM_30_38 BM_38_30 -#define BM_39_30 0x000000ffc0000000 -#define BM_30_39 BM_39_30 -#define BM_40_30 0x000001ffc0000000 -#define BM_30_40 BM_40_30 -#define BM_41_30 0x000003ffc0000000 -#define BM_30_41 BM_41_30 -#define BM_42_30 0x000007ffc0000000 -#define BM_30_42 BM_42_30 -#define BM_43_30 0x00000fffc0000000 -#define BM_30_43 BM_43_30 -#define BM_44_30 0x00001fffc0000000 -#define BM_30_44 BM_44_30 -#define BM_45_30 0x00003fffc0000000 -#define BM_30_45 BM_45_30 -#define BM_46_30 0x00007fffc0000000 -#define BM_30_46 BM_46_30 -#define BM_47_30 0x0000ffffc0000000 -#define BM_30_47 BM_47_30 -#define BM_48_30 0x0001ffffc0000000 -#define BM_30_48 BM_48_30 -#define BM_49_30 0x0003ffffc0000000 -#define BM_30_49 BM_49_30 -#define BM_50_30 0x0007ffffc0000000 -#define BM_30_50 BM_50_30 -#define BM_51_30 0x000fffffc0000000 -#define BM_30_51 BM_51_30 -#define BM_52_30 0x001fffffc0000000 -#define BM_30_52 BM_52_30 -#define BM_53_30 0x003fffffc0000000 -#define BM_30_53 BM_53_30 -#define BM_54_30 0x007fffffc0000000 -#define BM_30_54 BM_54_30 -#define BM_55_30 0x00ffffffc0000000 -#define BM_30_55 BM_55_30 -#define BM_56_30 0x01ffffffc0000000 -#define BM_30_56 BM_56_30 -#define BM_57_30 0x03ffffffc0000000 -#define BM_30_57 BM_57_30 -#define BM_58_30 0x07ffffffc0000000 -#define BM_30_58 BM_58_30 -#define BM_59_30 0x0fffffffc0000000 -#define BM_30_59 BM_59_30 -#define BM_60_30 0x1fffffffc0000000 -#define BM_30_60 BM_60_30 -#define BM_61_30 0x3fffffffc0000000 -#define BM_30_61 BM_61_30 -#define BM_62_30 0x7fffffffc0000000 -#define BM_30_62 BM_62_30 -#define BM_63_30 0xffffffffc0000000 -#define BM_30_63 BM_63_30 -#define BM_31_31 0x0000000080000000 -#define BM_32_31 0x0000000180000000 -#define BM_31_32 BM_32_31 -#define BM_33_31 0x0000000380000000 -#define BM_31_33 BM_33_31 -#define BM_34_31 0x0000000780000000 -#define BM_31_34 BM_34_31 -#define BM_35_31 0x0000000f80000000 -#define BM_31_35 BM_35_31 -#define BM_36_31 0x0000001f80000000 -#define BM_31_36 BM_36_31 -#define BM_37_31 0x0000003f80000000 -#define BM_31_37 BM_37_31 -#define BM_38_31 0x0000007f80000000 -#define BM_31_38 BM_38_31 -#define BM_39_31 0x000000ff80000000 -#define BM_31_39 BM_39_31 -#define BM_40_31 0x000001ff80000000 -#define BM_31_40 BM_40_31 -#define BM_41_31 0x000003ff80000000 -#define BM_31_41 BM_41_31 -#define BM_42_31 0x000007ff80000000 -#define BM_31_42 BM_42_31 -#define BM_43_31 0x00000fff80000000 -#define BM_31_43 BM_43_31 -#define BM_44_31 0x00001fff80000000 -#define BM_31_44 BM_44_31 -#define BM_45_31 0x00003fff80000000 -#define BM_31_45 BM_45_31 -#define BM_46_31 0x00007fff80000000 -#define BM_31_46 BM_46_31 -#define BM_47_31 0x0000ffff80000000 -#define BM_31_47 BM_47_31 -#define BM_48_31 0x0001ffff80000000 -#define BM_31_48 BM_48_31 -#define BM_49_31 0x0003ffff80000000 -#define BM_31_49 BM_49_31 -#define BM_50_31 0x0007ffff80000000 -#define BM_31_50 BM_50_31 -#define BM_51_31 0x000fffff80000000 -#define BM_31_51 BM_51_31 -#define BM_52_31 0x001fffff80000000 -#define BM_31_52 BM_52_31 -#define BM_53_31 0x003fffff80000000 -#define BM_31_53 BM_53_31 -#define BM_54_31 0x007fffff80000000 -#define BM_31_54 BM_54_31 -#define BM_55_31 0x00ffffff80000000 -#define BM_31_55 BM_55_31 -#define BM_56_31 0x01ffffff80000000 -#define BM_31_56 BM_56_31 -#define BM_57_31 0x03ffffff80000000 -#define BM_31_57 BM_57_31 -#define BM_58_31 0x07ffffff80000000 -#define BM_31_58 BM_58_31 -#define BM_59_31 0x0fffffff80000000 -#define BM_31_59 BM_59_31 -#define BM_60_31 0x1fffffff80000000 -#define BM_31_60 BM_60_31 -#define BM_61_31 0x3fffffff80000000 -#define BM_31_61 BM_61_31 -#define BM_62_31 0x7fffffff80000000 -#define BM_31_62 BM_62_31 -#define BM_63_31 0xffffffff80000000 -#define BM_31_63 BM_63_31 -#define BM_32_32 0x0000000100000000 -#define BM_33_32 0x0000000300000000 -#define BM_32_33 BM_33_32 -#define BM_34_32 0x0000000700000000 -#define BM_32_34 BM_34_32 -#define BM_35_32 0x0000000f00000000 -#define BM_32_35 BM_35_32 -#define BM_36_32 0x0000001f00000000 -#define BM_32_36 BM_36_32 -#define BM_37_32 0x0000003f00000000 -#define BM_32_37 BM_37_32 -#define BM_38_32 0x0000007f00000000 -#define BM_32_38 BM_38_32 -#define BM_39_32 0x000000ff00000000 -#define BM_32_39 BM_39_32 -#define BM_40_32 0x000001ff00000000 -#define BM_32_40 BM_40_32 -#define BM_41_32 0x000003ff00000000 -#define BM_32_41 BM_41_32 -#define BM_42_32 0x000007ff00000000 -#define BM_32_42 BM_42_32 -#define BM_43_32 0x00000fff00000000 -#define BM_32_43 BM_43_32 -#define BM_44_32 0x00001fff00000000 -#define BM_32_44 BM_44_32 -#define BM_45_32 0x00003fff00000000 -#define BM_32_45 BM_45_32 -#define BM_46_32 0x00007fff00000000 -#define BM_32_46 BM_46_32 -#define BM_47_32 0x0000ffff00000000 -#define BM_32_47 BM_47_32 -#define BM_48_32 0x0001ffff00000000 -#define BM_32_48 BM_48_32 -#define BM_49_32 0x0003ffff00000000 -#define BM_32_49 BM_49_32 -#define BM_50_32 0x0007ffff00000000 -#define BM_32_50 BM_50_32 -#define BM_51_32 0x000fffff00000000 -#define BM_32_51 BM_51_32 -#define BM_52_32 0x001fffff00000000 -#define BM_32_52 BM_52_32 -#define BM_53_32 0x003fffff00000000 -#define BM_32_53 BM_53_32 -#define BM_54_32 0x007fffff00000000 -#define BM_32_54 BM_54_32 -#define BM_55_32 0x00ffffff00000000 -#define BM_32_55 BM_55_32 -#define BM_56_32 0x01ffffff00000000 -#define BM_32_56 BM_56_32 -#define BM_57_32 0x03ffffff00000000 -#define BM_32_57 BM_57_32 -#define BM_58_32 0x07ffffff00000000 -#define BM_32_58 BM_58_32 -#define BM_59_32 0x0fffffff00000000 -#define BM_32_59 BM_59_32 -#define BM_60_32 0x1fffffff00000000 -#define BM_32_60 BM_60_32 -#define BM_61_32 0x3fffffff00000000 -#define BM_32_61 BM_61_32 -#define BM_62_32 0x7fffffff00000000 -#define BM_32_62 BM_62_32 -#define BM_63_32 0xffffffff00000000 -#define BM_32_63 BM_63_32 -#define BM_33_33 0x0000000200000000 -#define BM_34_33 0x0000000600000000 -#define BM_33_34 BM_34_33 -#define BM_35_33 0x0000000e00000000 -#define BM_33_35 BM_35_33 -#define BM_36_33 0x0000001e00000000 -#define BM_33_36 BM_36_33 -#define BM_37_33 0x0000003e00000000 -#define BM_33_37 BM_37_33 -#define BM_38_33 0x0000007e00000000 -#define BM_33_38 BM_38_33 -#define BM_39_33 0x000000fe00000000 -#define BM_33_39 BM_39_33 -#define BM_40_33 0x000001fe00000000 -#define BM_33_40 BM_40_33 -#define BM_41_33 0x000003fe00000000 -#define BM_33_41 BM_41_33 -#define BM_42_33 0x000007fe00000000 -#define BM_33_42 BM_42_33 -#define BM_43_33 0x00000ffe00000000 -#define BM_33_43 BM_43_33 -#define BM_44_33 0x00001ffe00000000 -#define BM_33_44 BM_44_33 -#define BM_45_33 0x00003ffe00000000 -#define BM_33_45 BM_45_33 -#define BM_46_33 0x00007ffe00000000 -#define BM_33_46 BM_46_33 -#define BM_47_33 0x0000fffe00000000 -#define BM_33_47 BM_47_33 -#define BM_48_33 0x0001fffe00000000 -#define BM_33_48 BM_48_33 -#define BM_49_33 0x0003fffe00000000 -#define BM_33_49 BM_49_33 -#define BM_50_33 0x0007fffe00000000 -#define BM_33_50 BM_50_33 -#define BM_51_33 0x000ffffe00000000 -#define BM_33_51 BM_51_33 -#define BM_52_33 0x001ffffe00000000 -#define BM_33_52 BM_52_33 -#define BM_53_33 0x003ffffe00000000 -#define BM_33_53 BM_53_33 -#define BM_54_33 0x007ffffe00000000 -#define BM_33_54 BM_54_33 -#define BM_55_33 0x00fffffe00000000 -#define BM_33_55 BM_55_33 -#define BM_56_33 0x01fffffe00000000 -#define BM_33_56 BM_56_33 -#define BM_57_33 0x03fffffe00000000 -#define BM_33_57 BM_57_33 -#define BM_58_33 0x07fffffe00000000 -#define BM_33_58 BM_58_33 -#define BM_59_33 0x0ffffffe00000000 -#define BM_33_59 BM_59_33 -#define BM_60_33 0x1ffffffe00000000 -#define BM_33_60 BM_60_33 -#define BM_61_33 0x3ffffffe00000000 -#define BM_33_61 BM_61_33 -#define BM_62_33 0x7ffffffe00000000 -#define BM_33_62 BM_62_33 -#define BM_63_33 0xfffffffe00000000 -#define BM_33_63 BM_63_33 -#define BM_34_34 0x0000000400000000 -#define BM_35_34 0x0000000c00000000 -#define BM_34_35 BM_35_34 -#define BM_36_34 0x0000001c00000000 -#define BM_34_36 BM_36_34 -#define BM_37_34 0x0000003c00000000 -#define BM_34_37 BM_37_34 -#define BM_38_34 0x0000007c00000000 -#define BM_34_38 BM_38_34 -#define BM_39_34 0x000000fc00000000 -#define BM_34_39 BM_39_34 -#define BM_40_34 0x000001fc00000000 -#define BM_34_40 BM_40_34 -#define BM_41_34 0x000003fc00000000 -#define BM_34_41 BM_41_34 -#define BM_42_34 0x000007fc00000000 -#define BM_34_42 BM_42_34 -#define BM_43_34 0x00000ffc00000000 -#define BM_34_43 BM_43_34 -#define BM_44_34 0x00001ffc00000000 -#define BM_34_44 BM_44_34 -#define BM_45_34 0x00003ffc00000000 -#define BM_34_45 BM_45_34 -#define BM_46_34 0x00007ffc00000000 -#define BM_34_46 BM_46_34 -#define BM_47_34 0x0000fffc00000000 -#define BM_34_47 BM_47_34 -#define BM_48_34 0x0001fffc00000000 -#define BM_34_48 BM_48_34 -#define BM_49_34 0x0003fffc00000000 -#define BM_34_49 BM_49_34 -#define BM_50_34 0x0007fffc00000000 -#define BM_34_50 BM_50_34 -#define BM_51_34 0x000ffffc00000000 -#define BM_34_51 BM_51_34 -#define BM_52_34 0x001ffffc00000000 -#define BM_34_52 BM_52_34 -#define BM_53_34 0x003ffffc00000000 -#define BM_34_53 BM_53_34 -#define BM_54_34 0x007ffffc00000000 -#define BM_34_54 BM_54_34 -#define BM_55_34 0x00fffffc00000000 -#define BM_34_55 BM_55_34 -#define BM_56_34 0x01fffffc00000000 -#define BM_34_56 BM_56_34 -#define BM_57_34 0x03fffffc00000000 -#define BM_34_57 BM_57_34 -#define BM_58_34 0x07fffffc00000000 -#define BM_34_58 BM_58_34 -#define BM_59_34 0x0ffffffc00000000 -#define BM_34_59 BM_59_34 -#define BM_60_34 0x1ffffffc00000000 -#define BM_34_60 BM_60_34 -#define BM_61_34 0x3ffffffc00000000 -#define BM_34_61 BM_61_34 -#define BM_62_34 0x7ffffffc00000000 -#define BM_34_62 BM_62_34 -#define BM_63_34 0xfffffffc00000000 -#define BM_34_63 BM_63_34 -#define BM_35_35 0x0000000800000000 -#define BM_36_35 0x0000001800000000 -#define BM_35_36 BM_36_35 -#define BM_37_35 0x0000003800000000 -#define BM_35_37 BM_37_35 -#define BM_38_35 0x0000007800000000 -#define BM_35_38 BM_38_35 -#define BM_39_35 0x000000f800000000 -#define BM_35_39 BM_39_35 -#define BM_40_35 0x000001f800000000 -#define BM_35_40 BM_40_35 -#define BM_41_35 0x000003f800000000 -#define BM_35_41 BM_41_35 -#define BM_42_35 0x000007f800000000 -#define BM_35_42 BM_42_35 -#define BM_43_35 0x00000ff800000000 -#define BM_35_43 BM_43_35 -#define BM_44_35 0x00001ff800000000 -#define BM_35_44 BM_44_35 -#define BM_45_35 0x00003ff800000000 -#define BM_35_45 BM_45_35 -#define BM_46_35 0x00007ff800000000 -#define BM_35_46 BM_46_35 -#define BM_47_35 0x0000fff800000000 -#define BM_35_47 BM_47_35 -#define BM_48_35 0x0001fff800000000 -#define BM_35_48 BM_48_35 -#define BM_49_35 0x0003fff800000000 -#define BM_35_49 BM_49_35 -#define BM_50_35 0x0007fff800000000 -#define BM_35_50 BM_50_35 -#define BM_51_35 0x000ffff800000000 -#define BM_35_51 BM_51_35 -#define BM_52_35 0x001ffff800000000 -#define BM_35_52 BM_52_35 -#define BM_53_35 0x003ffff800000000 -#define BM_35_53 BM_53_35 -#define BM_54_35 0x007ffff800000000 -#define BM_35_54 BM_54_35 -#define BM_55_35 0x00fffff800000000 -#define BM_35_55 BM_55_35 -#define BM_56_35 0x01fffff800000000 -#define BM_35_56 BM_56_35 -#define BM_57_35 0x03fffff800000000 -#define BM_35_57 BM_57_35 -#define BM_58_35 0x07fffff800000000 -#define BM_35_58 BM_58_35 -#define BM_59_35 0x0ffffff800000000 -#define BM_35_59 BM_59_35 -#define BM_60_35 0x1ffffff800000000 -#define BM_35_60 BM_60_35 -#define BM_61_35 0x3ffffff800000000 -#define BM_35_61 BM_61_35 -#define BM_62_35 0x7ffffff800000000 -#define BM_35_62 BM_62_35 -#define BM_63_35 0xfffffff800000000 -#define BM_35_63 BM_63_35 -#define BM_36_36 0x0000001000000000 -#define BM_37_36 0x0000003000000000 -#define BM_36_37 BM_37_36 -#define BM_38_36 0x0000007000000000 -#define BM_36_38 BM_38_36 -#define BM_39_36 0x000000f000000000 -#define BM_36_39 BM_39_36 -#define BM_40_36 0x000001f000000000 -#define BM_36_40 BM_40_36 -#define BM_41_36 0x000003f000000000 -#define BM_36_41 BM_41_36 -#define BM_42_36 0x000007f000000000 -#define BM_36_42 BM_42_36 -#define BM_43_36 0x00000ff000000000 -#define BM_36_43 BM_43_36 -#define BM_44_36 0x00001ff000000000 -#define BM_36_44 BM_44_36 -#define BM_45_36 0x00003ff000000000 -#define BM_36_45 BM_45_36 -#define BM_46_36 0x00007ff000000000 -#define BM_36_46 BM_46_36 -#define BM_47_36 0x0000fff000000000 -#define BM_36_47 BM_47_36 -#define BM_48_36 0x0001fff000000000 -#define BM_36_48 BM_48_36 -#define BM_49_36 0x0003fff000000000 -#define BM_36_49 BM_49_36 -#define BM_50_36 0x0007fff000000000 -#define BM_36_50 BM_50_36 -#define BM_51_36 0x000ffff000000000 -#define BM_36_51 BM_51_36 -#define BM_52_36 0x001ffff000000000 -#define BM_36_52 BM_52_36 -#define BM_53_36 0x003ffff000000000 -#define BM_36_53 BM_53_36 -#define BM_54_36 0x007ffff000000000 -#define BM_36_54 BM_54_36 -#define BM_55_36 0x00fffff000000000 -#define BM_36_55 BM_55_36 -#define BM_56_36 0x01fffff000000000 -#define BM_36_56 BM_56_36 -#define BM_57_36 0x03fffff000000000 -#define BM_36_57 BM_57_36 -#define BM_58_36 0x07fffff000000000 -#define BM_36_58 BM_58_36 -#define BM_59_36 0x0ffffff000000000 -#define BM_36_59 BM_59_36 -#define BM_60_36 0x1ffffff000000000 -#define BM_36_60 BM_60_36 -#define BM_61_36 0x3ffffff000000000 -#define BM_36_61 BM_61_36 -#define BM_62_36 0x7ffffff000000000 -#define BM_36_62 BM_62_36 -#define BM_63_36 0xfffffff000000000 -#define BM_36_63 BM_63_36 -#define BM_37_37 0x0000002000000000 -#define BM_38_37 0x0000006000000000 -#define BM_37_38 BM_38_37 -#define BM_39_37 0x000000e000000000 -#define BM_37_39 BM_39_37 -#define BM_40_37 0x000001e000000000 -#define BM_37_40 BM_40_37 -#define BM_41_37 0x000003e000000000 -#define BM_37_41 BM_41_37 -#define BM_42_37 0x000007e000000000 -#define BM_37_42 BM_42_37 -#define BM_43_37 0x00000fe000000000 -#define BM_37_43 BM_43_37 -#define BM_44_37 0x00001fe000000000 -#define BM_37_44 BM_44_37 -#define BM_45_37 0x00003fe000000000 -#define BM_37_45 BM_45_37 -#define BM_46_37 0x00007fe000000000 -#define BM_37_46 BM_46_37 -#define BM_47_37 0x0000ffe000000000 -#define BM_37_47 BM_47_37 -#define BM_48_37 0x0001ffe000000000 -#define BM_37_48 BM_48_37 -#define BM_49_37 0x0003ffe000000000 -#define BM_37_49 BM_49_37 -#define BM_50_37 0x0007ffe000000000 -#define BM_37_50 BM_50_37 -#define BM_51_37 0x000fffe000000000 -#define BM_37_51 BM_51_37 -#define BM_52_37 0x001fffe000000000 -#define BM_37_52 BM_52_37 -#define BM_53_37 0x003fffe000000000 -#define BM_37_53 BM_53_37 -#define BM_54_37 0x007fffe000000000 -#define BM_37_54 BM_54_37 -#define BM_55_37 0x00ffffe000000000 -#define BM_37_55 BM_55_37 -#define BM_56_37 0x01ffffe000000000 -#define BM_37_56 BM_56_37 -#define BM_57_37 0x03ffffe000000000 -#define BM_37_57 BM_57_37 -#define BM_58_37 0x07ffffe000000000 -#define BM_37_58 BM_58_37 -#define BM_59_37 0x0fffffe000000000 -#define BM_37_59 BM_59_37 -#define BM_60_37 0x1fffffe000000000 -#define BM_37_60 BM_60_37 -#define BM_61_37 0x3fffffe000000000 -#define BM_37_61 BM_61_37 -#define BM_62_37 0x7fffffe000000000 -#define BM_37_62 BM_62_37 -#define BM_63_37 0xffffffe000000000 -#define BM_37_63 BM_63_37 -#define BM_38_38 0x0000004000000000 -#define BM_39_38 0x000000c000000000 -#define BM_38_39 BM_39_38 -#define BM_40_38 0x000001c000000000 -#define BM_38_40 BM_40_38 -#define BM_41_38 0x000003c000000000 -#define BM_38_41 BM_41_38 -#define BM_42_38 0x000007c000000000 -#define BM_38_42 BM_42_38 -#define BM_43_38 0x00000fc000000000 -#define BM_38_43 BM_43_38 -#define BM_44_38 0x00001fc000000000 -#define BM_38_44 BM_44_38 -#define BM_45_38 0x00003fc000000000 -#define BM_38_45 BM_45_38 -#define BM_46_38 0x00007fc000000000 -#define BM_38_46 BM_46_38 -#define BM_47_38 0x0000ffc000000000 -#define BM_38_47 BM_47_38 -#define BM_48_38 0x0001ffc000000000 -#define BM_38_48 BM_48_38 -#define BM_49_38 0x0003ffc000000000 -#define BM_38_49 BM_49_38 -#define BM_50_38 0x0007ffc000000000 -#define BM_38_50 BM_50_38 -#define BM_51_38 0x000fffc000000000 -#define BM_38_51 BM_51_38 -#define BM_52_38 0x001fffc000000000 -#define BM_38_52 BM_52_38 -#define BM_53_38 0x003fffc000000000 -#define BM_38_53 BM_53_38 -#define BM_54_38 0x007fffc000000000 -#define BM_38_54 BM_54_38 -#define BM_55_38 0x00ffffc000000000 -#define BM_38_55 BM_55_38 -#define BM_56_38 0x01ffffc000000000 -#define BM_38_56 BM_56_38 -#define BM_57_38 0x03ffffc000000000 -#define BM_38_57 BM_57_38 -#define BM_58_38 0x07ffffc000000000 -#define BM_38_58 BM_58_38 -#define BM_59_38 0x0fffffc000000000 -#define BM_38_59 BM_59_38 -#define BM_60_38 0x1fffffc000000000 -#define BM_38_60 BM_60_38 -#define BM_61_38 0x3fffffc000000000 -#define BM_38_61 BM_61_38 -#define BM_62_38 0x7fffffc000000000 -#define BM_38_62 BM_62_38 -#define BM_63_38 0xffffffc000000000 -#define BM_38_63 BM_63_38 -#define BM_39_39 0x0000008000000000 -#define BM_40_39 0x0000018000000000 -#define BM_39_40 BM_40_39 -#define BM_41_39 0x0000038000000000 -#define BM_39_41 BM_41_39 -#define BM_42_39 0x0000078000000000 -#define BM_39_42 BM_42_39 -#define BM_43_39 0x00000f8000000000 -#define BM_39_43 BM_43_39 -#define BM_44_39 0x00001f8000000000 -#define BM_39_44 BM_44_39 -#define BM_45_39 0x00003f8000000000 -#define BM_39_45 BM_45_39 -#define BM_46_39 0x00007f8000000000 -#define BM_39_46 BM_46_39 -#define BM_47_39 0x0000ff8000000000 -#define BM_39_47 BM_47_39 -#define BM_48_39 0x0001ff8000000000 -#define BM_39_48 BM_48_39 -#define BM_49_39 0x0003ff8000000000 -#define BM_39_49 BM_49_39 -#define BM_50_39 0x0007ff8000000000 -#define BM_39_50 BM_50_39 -#define BM_51_39 0x000fff8000000000 -#define BM_39_51 BM_51_39 -#define BM_52_39 0x001fff8000000000 -#define BM_39_52 BM_52_39 -#define BM_53_39 0x003fff8000000000 -#define BM_39_53 BM_53_39 -#define BM_54_39 0x007fff8000000000 -#define BM_39_54 BM_54_39 -#define BM_55_39 0x00ffff8000000000 -#define BM_39_55 BM_55_39 -#define BM_56_39 0x01ffff8000000000 -#define BM_39_56 BM_56_39 -#define BM_57_39 0x03ffff8000000000 -#define BM_39_57 BM_57_39 -#define BM_58_39 0x07ffff8000000000 -#define BM_39_58 BM_58_39 -#define BM_59_39 0x0fffff8000000000 -#define BM_39_59 BM_59_39 -#define BM_60_39 0x1fffff8000000000 -#define BM_39_60 BM_60_39 -#define BM_61_39 0x3fffff8000000000 -#define BM_39_61 BM_61_39 -#define BM_62_39 0x7fffff8000000000 -#define BM_39_62 BM_62_39 -#define BM_63_39 0xffffff8000000000 -#define BM_39_63 BM_63_39 -#define BM_40_40 0x0000010000000000 -#define BM_41_40 0x0000030000000000 -#define BM_40_41 BM_41_40 -#define BM_42_40 0x0000070000000000 -#define BM_40_42 BM_42_40 -#define BM_43_40 0x00000f0000000000 -#define BM_40_43 BM_43_40 -#define BM_44_40 0x00001f0000000000 -#define BM_40_44 BM_44_40 -#define BM_45_40 0x00003f0000000000 -#define BM_40_45 BM_45_40 -#define BM_46_40 0x00007f0000000000 -#define BM_40_46 BM_46_40 -#define BM_47_40 0x0000ff0000000000 -#define BM_40_47 BM_47_40 -#define BM_48_40 0x0001ff0000000000 -#define BM_40_48 BM_48_40 -#define BM_49_40 0x0003ff0000000000 -#define BM_40_49 BM_49_40 -#define BM_50_40 0x0007ff0000000000 -#define BM_40_50 BM_50_40 -#define BM_51_40 0x000fff0000000000 -#define BM_40_51 BM_51_40 -#define BM_52_40 0x001fff0000000000 -#define BM_40_52 BM_52_40 -#define BM_53_40 0x003fff0000000000 -#define BM_40_53 BM_53_40 -#define BM_54_40 0x007fff0000000000 -#define BM_40_54 BM_54_40 -#define BM_55_40 0x00ffff0000000000 -#define BM_40_55 BM_55_40 -#define BM_56_40 0x01ffff0000000000 -#define BM_40_56 BM_56_40 -#define BM_57_40 0x03ffff0000000000 -#define BM_40_57 BM_57_40 -#define BM_58_40 0x07ffff0000000000 -#define BM_40_58 BM_58_40 -#define BM_59_40 0x0fffff0000000000 -#define BM_40_59 BM_59_40 -#define BM_60_40 0x1fffff0000000000 -#define BM_40_60 BM_60_40 -#define BM_61_40 0x3fffff0000000000 -#define BM_40_61 BM_61_40 -#define BM_62_40 0x7fffff0000000000 -#define BM_40_62 BM_62_40 -#define BM_63_40 0xffffff0000000000 -#define BM_40_63 BM_63_40 -#define BM_41_41 0x0000020000000000 -#define BM_42_41 0x0000060000000000 -#define BM_41_42 BM_42_41 -#define BM_43_41 0x00000e0000000000 -#define BM_41_43 BM_43_41 -#define BM_44_41 0x00001e0000000000 -#define BM_41_44 BM_44_41 -#define BM_45_41 0x00003e0000000000 -#define BM_41_45 BM_45_41 -#define BM_46_41 0x00007e0000000000 -#define BM_41_46 BM_46_41 -#define BM_47_41 0x0000fe0000000000 -#define BM_41_47 BM_47_41 -#define BM_48_41 0x0001fe0000000000 -#define BM_41_48 BM_48_41 -#define BM_49_41 0x0003fe0000000000 -#define BM_41_49 BM_49_41 -#define BM_50_41 0x0007fe0000000000 -#define BM_41_50 BM_50_41 -#define BM_51_41 0x000ffe0000000000 -#define BM_41_51 BM_51_41 -#define BM_52_41 0x001ffe0000000000 -#define BM_41_52 BM_52_41 -#define BM_53_41 0x003ffe0000000000 -#define BM_41_53 BM_53_41 -#define BM_54_41 0x007ffe0000000000 -#define BM_41_54 BM_54_41 -#define BM_55_41 0x00fffe0000000000 -#define BM_41_55 BM_55_41 -#define BM_56_41 0x01fffe0000000000 -#define BM_41_56 BM_56_41 -#define BM_57_41 0x03fffe0000000000 -#define BM_41_57 BM_57_41 -#define BM_58_41 0x07fffe0000000000 -#define BM_41_58 BM_58_41 -#define BM_59_41 0x0ffffe0000000000 -#define BM_41_59 BM_59_41 -#define BM_60_41 0x1ffffe0000000000 -#define BM_41_60 BM_60_41 -#define BM_61_41 0x3ffffe0000000000 -#define BM_41_61 BM_61_41 -#define BM_62_41 0x7ffffe0000000000 -#define BM_41_62 BM_62_41 -#define BM_63_41 0xfffffe0000000000 -#define BM_41_63 BM_63_41 -#define BM_42_42 0x0000040000000000 -#define BM_43_42 0x00000c0000000000 -#define BM_42_43 BM_43_42 -#define BM_44_42 0x00001c0000000000 -#define BM_42_44 BM_44_42 -#define BM_45_42 0x00003c0000000000 -#define BM_42_45 BM_45_42 -#define BM_46_42 0x00007c0000000000 -#define BM_42_46 BM_46_42 -#define BM_47_42 0x0000fc0000000000 -#define BM_42_47 BM_47_42 -#define BM_48_42 0x0001fc0000000000 -#define BM_42_48 BM_48_42 -#define BM_49_42 0x0003fc0000000000 -#define BM_42_49 BM_49_42 -#define BM_50_42 0x0007fc0000000000 -#define BM_42_50 BM_50_42 -#define BM_51_42 0x000ffc0000000000 -#define BM_42_51 BM_51_42 -#define BM_52_42 0x001ffc0000000000 -#define BM_42_52 BM_52_42 -#define BM_53_42 0x003ffc0000000000 -#define BM_42_53 BM_53_42 -#define BM_54_42 0x007ffc0000000000 -#define BM_42_54 BM_54_42 -#define BM_55_42 0x00fffc0000000000 -#define BM_42_55 BM_55_42 -#define BM_56_42 0x01fffc0000000000 -#define BM_42_56 BM_56_42 -#define BM_57_42 0x03fffc0000000000 -#define BM_42_57 BM_57_42 -#define BM_58_42 0x07fffc0000000000 -#define BM_42_58 BM_58_42 -#define BM_59_42 0x0ffffc0000000000 -#define BM_42_59 BM_59_42 -#define BM_60_42 0x1ffffc0000000000 -#define BM_42_60 BM_60_42 -#define BM_61_42 0x3ffffc0000000000 -#define BM_42_61 BM_61_42 -#define BM_62_42 0x7ffffc0000000000 -#define BM_42_62 BM_62_42 -#define BM_63_42 0xfffffc0000000000 -#define BM_42_63 BM_63_42 -#define BM_43_43 0x0000080000000000 -#define BM_44_43 0x0000180000000000 -#define BM_43_44 BM_44_43 -#define BM_45_43 0x0000380000000000 -#define BM_43_45 BM_45_43 -#define BM_46_43 0x0000780000000000 -#define BM_43_46 BM_46_43 -#define BM_47_43 0x0000f80000000000 -#define BM_43_47 BM_47_43 -#define BM_48_43 0x0001f80000000000 -#define BM_43_48 BM_48_43 -#define BM_49_43 0x0003f80000000000 -#define BM_43_49 BM_49_43 -#define BM_50_43 0x0007f80000000000 -#define BM_43_50 BM_50_43 -#define BM_51_43 0x000ff80000000000 -#define BM_43_51 BM_51_43 -#define BM_52_43 0x001ff80000000000 -#define BM_43_52 BM_52_43 -#define BM_53_43 0x003ff80000000000 -#define BM_43_53 BM_53_43 -#define BM_54_43 0x007ff80000000000 -#define BM_43_54 BM_54_43 -#define BM_55_43 0x00fff80000000000 -#define BM_43_55 BM_55_43 -#define BM_56_43 0x01fff80000000000 -#define BM_43_56 BM_56_43 -#define BM_57_43 0x03fff80000000000 -#define BM_43_57 BM_57_43 -#define BM_58_43 0x07fff80000000000 -#define BM_43_58 BM_58_43 -#define BM_59_43 0x0ffff80000000000 -#define BM_43_59 BM_59_43 -#define BM_60_43 0x1ffff80000000000 -#define BM_43_60 BM_60_43 -#define BM_61_43 0x3ffff80000000000 -#define BM_43_61 BM_61_43 -#define BM_62_43 0x7ffff80000000000 -#define BM_43_62 BM_62_43 -#define BM_63_43 0xfffff80000000000 -#define BM_43_63 BM_63_43 -#define BM_44_44 0x0000100000000000 -#define BM_45_44 0x0000300000000000 -#define BM_44_45 BM_45_44 -#define BM_46_44 0x0000700000000000 -#define BM_44_46 BM_46_44 -#define BM_47_44 0x0000f00000000000 -#define BM_44_47 BM_47_44 -#define BM_48_44 0x0001f00000000000 -#define BM_44_48 BM_48_44 -#define BM_49_44 0x0003f00000000000 -#define BM_44_49 BM_49_44 -#define BM_50_44 0x0007f00000000000 -#define BM_44_50 BM_50_44 -#define BM_51_44 0x000ff00000000000 -#define BM_44_51 BM_51_44 -#define BM_52_44 0x001ff00000000000 -#define BM_44_52 BM_52_44 -#define BM_53_44 0x003ff00000000000 -#define BM_44_53 BM_53_44 -#define BM_54_44 0x007ff00000000000 -#define BM_44_54 BM_54_44 -#define BM_55_44 0x00fff00000000000 -#define BM_44_55 BM_55_44 -#define BM_56_44 0x01fff00000000000 -#define BM_44_56 BM_56_44 -#define BM_57_44 0x03fff00000000000 -#define BM_44_57 BM_57_44 -#define BM_58_44 0x07fff00000000000 -#define BM_44_58 BM_58_44 -#define BM_59_44 0x0ffff00000000000 -#define BM_44_59 BM_59_44 -#define BM_60_44 0x1ffff00000000000 -#define BM_44_60 BM_60_44 -#define BM_61_44 0x3ffff00000000000 -#define BM_44_61 BM_61_44 -#define BM_62_44 0x7ffff00000000000 -#define BM_44_62 BM_62_44 -#define BM_63_44 0xfffff00000000000 -#define BM_44_63 BM_63_44 -#define BM_45_45 0x0000200000000000 -#define BM_46_45 0x0000600000000000 -#define BM_45_46 BM_46_45 -#define BM_47_45 0x0000e00000000000 -#define BM_45_47 BM_47_45 -#define BM_48_45 0x0001e00000000000 -#define BM_45_48 BM_48_45 -#define BM_49_45 0x0003e00000000000 -#define BM_45_49 BM_49_45 -#define BM_50_45 0x0007e00000000000 -#define BM_45_50 BM_50_45 -#define BM_51_45 0x000fe00000000000 -#define BM_45_51 BM_51_45 -#define BM_52_45 0x001fe00000000000 -#define BM_45_52 BM_52_45 -#define BM_53_45 0x003fe00000000000 -#define BM_45_53 BM_53_45 -#define BM_54_45 0x007fe00000000000 -#define BM_45_54 BM_54_45 -#define BM_55_45 0x00ffe00000000000 -#define BM_45_55 BM_55_45 -#define BM_56_45 0x01ffe00000000000 -#define BM_45_56 BM_56_45 -#define BM_57_45 0x03ffe00000000000 -#define BM_45_57 BM_57_45 -#define BM_58_45 0x07ffe00000000000 -#define BM_45_58 BM_58_45 -#define BM_59_45 0x0fffe00000000000 -#define BM_45_59 BM_59_45 -#define BM_60_45 0x1fffe00000000000 -#define BM_45_60 BM_60_45 -#define BM_61_45 0x3fffe00000000000 -#define BM_45_61 BM_61_45 -#define BM_62_45 0x7fffe00000000000 -#define BM_45_62 BM_62_45 -#define BM_63_45 0xffffe00000000000 -#define BM_45_63 BM_63_45 -#define BM_46_46 0x0000400000000000 -#define BM_47_46 0x0000c00000000000 -#define BM_46_47 BM_47_46 -#define BM_48_46 0x0001c00000000000 -#define BM_46_48 BM_48_46 -#define BM_49_46 0x0003c00000000000 -#define BM_46_49 BM_49_46 -#define BM_50_46 0x0007c00000000000 -#define BM_46_50 BM_50_46 -#define BM_51_46 0x000fc00000000000 -#define BM_46_51 BM_51_46 -#define BM_52_46 0x001fc00000000000 -#define BM_46_52 BM_52_46 -#define BM_53_46 0x003fc00000000000 -#define BM_46_53 BM_53_46 -#define BM_54_46 0x007fc00000000000 -#define BM_46_54 BM_54_46 -#define BM_55_46 0x00ffc00000000000 -#define BM_46_55 BM_55_46 -#define BM_56_46 0x01ffc00000000000 -#define BM_46_56 BM_56_46 -#define BM_57_46 0x03ffc00000000000 -#define BM_46_57 BM_57_46 -#define BM_58_46 0x07ffc00000000000 -#define BM_46_58 BM_58_46 -#define BM_59_46 0x0fffc00000000000 -#define BM_46_59 BM_59_46 -#define BM_60_46 0x1fffc00000000000 -#define BM_46_60 BM_60_46 -#define BM_61_46 0x3fffc00000000000 -#define BM_46_61 BM_61_46 -#define BM_62_46 0x7fffc00000000000 -#define BM_46_62 BM_62_46 -#define BM_63_46 0xffffc00000000000 -#define BM_46_63 BM_63_46 -#define BM_47_47 0x0000800000000000 -#define BM_48_47 0x0001800000000000 -#define BM_47_48 BM_48_47 -#define BM_49_47 0x0003800000000000 -#define BM_47_49 BM_49_47 -#define BM_50_47 0x0007800000000000 -#define BM_47_50 BM_50_47 -#define BM_51_47 0x000f800000000000 -#define BM_47_51 BM_51_47 -#define BM_52_47 0x001f800000000000 -#define BM_47_52 BM_52_47 -#define BM_53_47 0x003f800000000000 -#define BM_47_53 BM_53_47 -#define BM_54_47 0x007f800000000000 -#define BM_47_54 BM_54_47 -#define BM_55_47 0x00ff800000000000 -#define BM_47_55 BM_55_47 -#define BM_56_47 0x01ff800000000000 -#define BM_47_56 BM_56_47 -#define BM_57_47 0x03ff800000000000 -#define BM_47_57 BM_57_47 -#define BM_58_47 0x07ff800000000000 -#define BM_47_58 BM_58_47 -#define BM_59_47 0x0fff800000000000 -#define BM_47_59 BM_59_47 -#define BM_60_47 0x1fff800000000000 -#define BM_47_60 BM_60_47 -#define BM_61_47 0x3fff800000000000 -#define BM_47_61 BM_61_47 -#define BM_62_47 0x7fff800000000000 -#define BM_47_62 BM_62_47 -#define BM_63_47 0xffff800000000000 -#define BM_47_63 BM_63_47 -#define BM_48_48 0x0001000000000000 -#define BM_49_48 0x0003000000000000 -#define BM_48_49 BM_49_48 -#define BM_50_48 0x0007000000000000 -#define BM_48_50 BM_50_48 -#define BM_51_48 0x000f000000000000 -#define BM_48_51 BM_51_48 -#define BM_52_48 0x001f000000000000 -#define BM_48_52 BM_52_48 -#define BM_53_48 0x003f000000000000 -#define BM_48_53 BM_53_48 -#define BM_54_48 0x007f000000000000 -#define BM_48_54 BM_54_48 -#define BM_55_48 0x00ff000000000000 -#define BM_48_55 BM_55_48 -#define BM_56_48 0x01ff000000000000 -#define BM_48_56 BM_56_48 -#define BM_57_48 0x03ff000000000000 -#define BM_48_57 BM_57_48 -#define BM_58_48 0x07ff000000000000 -#define BM_48_58 BM_58_48 -#define BM_59_48 0x0fff000000000000 -#define BM_48_59 BM_59_48 -#define BM_60_48 0x1fff000000000000 -#define BM_48_60 BM_60_48 -#define BM_61_48 0x3fff000000000000 -#define BM_48_61 BM_61_48 -#define BM_62_48 0x7fff000000000000 -#define BM_48_62 BM_62_48 -#define BM_63_48 0xffff000000000000 -#define BM_48_63 BM_63_48 -#define BM_49_49 0x0002000000000000 -#define BM_50_49 0x0006000000000000 -#define BM_49_50 BM_50_49 -#define BM_51_49 0x000e000000000000 -#define BM_49_51 BM_51_49 -#define BM_52_49 0x001e000000000000 -#define BM_49_52 BM_52_49 -#define BM_53_49 0x003e000000000000 -#define BM_49_53 BM_53_49 -#define BM_54_49 0x007e000000000000 -#define BM_49_54 BM_54_49 -#define BM_55_49 0x00fe000000000000 -#define BM_49_55 BM_55_49 -#define BM_56_49 0x01fe000000000000 -#define BM_49_56 BM_56_49 -#define BM_57_49 0x03fe000000000000 -#define BM_49_57 BM_57_49 -#define BM_58_49 0x07fe000000000000 -#define BM_49_58 BM_58_49 -#define BM_59_49 0x0ffe000000000000 -#define BM_49_59 BM_59_49 -#define BM_60_49 0x1ffe000000000000 -#define BM_49_60 BM_60_49 -#define BM_61_49 0x3ffe000000000000 -#define BM_49_61 BM_61_49 -#define BM_62_49 0x7ffe000000000000 -#define BM_49_62 BM_62_49 -#define BM_63_49 0xfffe000000000000 -#define BM_49_63 BM_63_49 -#define BM_50_50 0x0004000000000000 -#define BM_51_50 0x000c000000000000 -#define BM_50_51 BM_51_50 -#define BM_52_50 0x001c000000000000 -#define BM_50_52 BM_52_50 -#define BM_53_50 0x003c000000000000 -#define BM_50_53 BM_53_50 -#define BM_54_50 0x007c000000000000 -#define BM_50_54 BM_54_50 -#define BM_55_50 0x00fc000000000000 -#define BM_50_55 BM_55_50 -#define BM_56_50 0x01fc000000000000 -#define BM_50_56 BM_56_50 -#define BM_57_50 0x03fc000000000000 -#define BM_50_57 BM_57_50 -#define BM_58_50 0x07fc000000000000 -#define BM_50_58 BM_58_50 -#define BM_59_50 0x0ffc000000000000 -#define BM_50_59 BM_59_50 -#define BM_60_50 0x1ffc000000000000 -#define BM_50_60 BM_60_50 -#define BM_61_50 0x3ffc000000000000 -#define BM_50_61 BM_61_50 -#define BM_62_50 0x7ffc000000000000 -#define BM_50_62 BM_62_50 -#define BM_63_50 0xfffc000000000000 -#define BM_50_63 BM_63_50 -#define BM_51_51 0x0008000000000000 -#define BM_52_51 0x0018000000000000 -#define BM_51_52 BM_52_51 -#define BM_53_51 0x0038000000000000 -#define BM_51_53 BM_53_51 -#define BM_54_51 0x0078000000000000 -#define BM_51_54 BM_54_51 -#define BM_55_51 0x00f8000000000000 -#define BM_51_55 BM_55_51 -#define BM_56_51 0x01f8000000000000 -#define BM_51_56 BM_56_51 -#define BM_57_51 0x03f8000000000000 -#define BM_51_57 BM_57_51 -#define BM_58_51 0x07f8000000000000 -#define BM_51_58 BM_58_51 -#define BM_59_51 0x0ff8000000000000 -#define BM_51_59 BM_59_51 -#define BM_60_51 0x1ff8000000000000 -#define BM_51_60 BM_60_51 -#define BM_61_51 0x3ff8000000000000 -#define BM_51_61 BM_61_51 -#define BM_62_51 0x7ff8000000000000 -#define BM_51_62 BM_62_51 -#define BM_63_51 0xfff8000000000000 -#define BM_51_63 BM_63_51 -#define BM_52_52 0x0010000000000000 -#define BM_53_52 0x0030000000000000 -#define BM_52_53 BM_53_52 -#define BM_54_52 0x0070000000000000 -#define BM_52_54 BM_54_52 -#define BM_55_52 0x00f0000000000000 -#define BM_52_55 BM_55_52 -#define BM_56_52 0x01f0000000000000 -#define BM_52_56 BM_56_52 -#define BM_57_52 0x03f0000000000000 -#define BM_52_57 BM_57_52 -#define BM_58_52 0x07f0000000000000 -#define BM_52_58 BM_58_52 -#define BM_59_52 0x0ff0000000000000 -#define BM_52_59 BM_59_52 -#define BM_60_52 0x1ff0000000000000 -#define BM_52_60 BM_60_52 -#define BM_61_52 0x3ff0000000000000 -#define BM_52_61 BM_61_52 -#define BM_62_52 0x7ff0000000000000 -#define BM_52_62 BM_62_52 -#define BM_63_52 0xfff0000000000000 -#define BM_52_63 BM_63_52 -#define BM_53_53 0x0020000000000000 -#define BM_54_53 0x0060000000000000 -#define BM_53_54 BM_54_53 -#define BM_55_53 0x00e0000000000000 -#define BM_53_55 BM_55_53 -#define BM_56_53 0x01e0000000000000 -#define BM_53_56 BM_56_53 -#define BM_57_53 0x03e0000000000000 -#define BM_53_57 BM_57_53 -#define BM_58_53 0x07e0000000000000 -#define BM_53_58 BM_58_53 -#define BM_59_53 0x0fe0000000000000 -#define BM_53_59 BM_59_53 -#define BM_60_53 0x1fe0000000000000 -#define BM_53_60 BM_60_53 -#define BM_61_53 0x3fe0000000000000 -#define BM_53_61 BM_61_53 -#define BM_62_53 0x7fe0000000000000 -#define BM_53_62 BM_62_53 -#define BM_63_53 0xffe0000000000000 -#define BM_53_63 BM_63_53 -#define BM_54_54 0x0040000000000000 -#define BM_55_54 0x00c0000000000000 -#define BM_54_55 BM_55_54 -#define BM_56_54 0x01c0000000000000 -#define BM_54_56 BM_56_54 -#define BM_57_54 0x03c0000000000000 -#define BM_54_57 BM_57_54 -#define BM_58_54 0x07c0000000000000 -#define BM_54_58 BM_58_54 -#define BM_59_54 0x0fc0000000000000 -#define BM_54_59 BM_59_54 -#define BM_60_54 0x1fc0000000000000 -#define BM_54_60 BM_60_54 -#define BM_61_54 0x3fc0000000000000 -#define BM_54_61 BM_61_54 -#define BM_62_54 0x7fc0000000000000 -#define BM_54_62 BM_62_54 -#define BM_63_54 0xffc0000000000000 -#define BM_54_63 BM_63_54 -#define BM_55_55 0x0080000000000000 -#define BM_56_55 0x0180000000000000 -#define BM_55_56 BM_56_55 -#define BM_57_55 0x0380000000000000 -#define BM_55_57 BM_57_55 -#define BM_58_55 0x0780000000000000 -#define BM_55_58 BM_58_55 -#define BM_59_55 0x0f80000000000000 -#define BM_55_59 BM_59_55 -#define BM_60_55 0x1f80000000000000 -#define BM_55_60 BM_60_55 -#define BM_61_55 0x3f80000000000000 -#define BM_55_61 BM_61_55 -#define BM_62_55 0x7f80000000000000 -#define BM_55_62 BM_62_55 -#define BM_63_55 0xff80000000000000 -#define BM_55_63 BM_63_55 -#define BM_56_56 0x0100000000000000 -#define BM_57_56 0x0300000000000000 -#define BM_56_57 BM_57_56 -#define BM_58_56 0x0700000000000000 -#define BM_56_58 BM_58_56 -#define BM_59_56 0x0f00000000000000 -#define BM_56_59 BM_59_56 -#define BM_60_56 0x1f00000000000000 -#define BM_56_60 BM_60_56 -#define BM_61_56 0x3f00000000000000 -#define BM_56_61 BM_61_56 -#define BM_62_56 0x7f00000000000000 -#define BM_56_62 BM_62_56 -#define BM_63_56 0xff00000000000000 -#define BM_56_63 BM_63_56 -#define BM_57_57 0x0200000000000000 -#define BM_58_57 0x0600000000000000 -#define BM_57_58 BM_58_57 -#define BM_59_57 0x0e00000000000000 -#define BM_57_59 BM_59_57 -#define BM_60_57 0x1e00000000000000 -#define BM_57_60 BM_60_57 -#define BM_61_57 0x3e00000000000000 -#define BM_57_61 BM_61_57 -#define BM_62_57 0x7e00000000000000 -#define BM_57_62 BM_62_57 -#define BM_63_57 0xfe00000000000000 -#define BM_57_63 BM_63_57 -#define BM_58_58 0x0400000000000000 -#define BM_59_58 0x0c00000000000000 -#define BM_58_59 BM_59_58 -#define BM_60_58 0x1c00000000000000 -#define BM_58_60 BM_60_58 -#define BM_61_58 0x3c00000000000000 -#define BM_58_61 BM_61_58 -#define BM_62_58 0x7c00000000000000 -#define BM_58_62 BM_62_58 -#define BM_63_58 0xfc00000000000000 -#define BM_58_63 BM_63_58 -#define BM_59_59 0x0800000000000000 -#define BM_60_59 0x1800000000000000 -#define BM_59_60 BM_60_59 -#define BM_61_59 0x3800000000000000 -#define BM_59_61 BM_61_59 -#define BM_62_59 0x7800000000000000 -#define BM_59_62 BM_62_59 -#define BM_63_59 0xf800000000000000 -#define BM_59_63 BM_63_59 -#define BM_60_60 0x1000000000000000 -#define BM_61_60 0x3000000000000000 -#define BM_60_61 BM_61_60 -#define BM_62_60 0x7000000000000000 -#define BM_60_62 BM_62_60 -#define BM_63_60 0xf000000000000000 -#define BM_60_63 BM_63_60 -#define BM_61_61 0x2000000000000000 -#define BM_62_61 0x6000000000000000 -#define BM_61_62 BM_62_61 -#define BM_63_61 0xe000000000000000 -#define BM_61_63 BM_63_61 -#define BM_62_62 0x4000000000000000 -#define BM_63_62 0xc000000000000000 -#define BM_62_63 BM_63_62 -#define BM_63_63 0x8000000000000000 - -#endif - -#endif /* __ASM_TX4927_TX4927_MIPS_H */ -- cgit v0.10.2 From abb4ae4630633573862934173e5f506771c5d6b1 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:03 +0100 Subject: [MIPS] PCI: Always enable CONFIG_PCI_DOMAINS The cost is just too low. Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6648f9b..ebc7b4b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -381,7 +381,6 @@ config SGI_IP27 select SYS_HAS_EARLY_PRINTK select HW_HAS_PCI select NR_CPUS_DEFAULT_64 - select PCI_DOMAINS select SYS_HAS_CPU_R10000 select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN @@ -513,7 +512,6 @@ config SIBYTE_BIGSUR select BOOT_ELF32 select DMA_COHERENT select NR_CPUS_DEFAULT_4 - select PCI_DOMAINS select SIBYTE_BCM1x80 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 @@ -1808,6 +1806,7 @@ config HW_HAS_PCI config PCI bool "Support for PCI controller" depends on HW_HAS_PCI + select PCI_DOMAINS help Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff inside @@ -1821,7 +1820,6 @@ config PCI config PCI_DOMAINS bool - depends on PCI source "drivers/pci/Kconfig" diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index 4fcc185..301ff2f 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h @@ -150,8 +150,6 @@ pcibios_select_root(struct pci_dev *pdev, struct resource *res) return root; } -#ifdef CONFIG_PCI_DOMAINS - #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index static inline int pci_proc_domain(struct pci_bus *bus) @@ -160,8 +158,6 @@ static inline int pci_proc_domain(struct pci_bus *bus) return hose->need_domain_info; } -#endif /* CONFIG_PCI_DOMAINS */ - #endif /* __KERNEL__ */ /* implement the pci_ DMA API in terms of the generic device dma_ one */ -- cgit v0.10.2 From 7ca16d269a1a4b96d98968b48f137977bcab1522 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:03 +0100 Subject: [MIPS] floppy: Rewrite fd_cacheflush() to use dma_cache_sync(). Signed-off-by: Ralf Baechle diff --git a/include/asm-mips/floppy.h b/include/asm-mips/floppy.h index aa1ef8b..dcadd85 100644 --- a/include/asm-mips/floppy.h +++ b/include/asm-mips/floppy.h @@ -10,9 +10,11 @@ #ifndef _ASM_FLOPPY_H #define _ASM_FLOPPY_H +#include + static inline void fd_cacheflush(char * addr, long size) { - dma_cache_wback_inv((unsigned long)addr,size); + dma_cache_sync(NULL, addr, size, DMA_BIDIRECTIONAL); } #define MAX_BUFFER_SECTORS 24 -- cgit v0.10.2 From bcb0fd94633afde9c1f4f8aca43141ba2c78f04b Mon Sep 17 00:00:00 2001 From: Thiemo Seufer Date: Wed, 5 Sep 2007 17:44:50 +0100 Subject: [MIPS] Define known MIPS ISA overrides for Sibyte and Excite boards. Signed-Off-By: Thiemo Seufer Signed-off-by: Ralf Baechle diff --git a/include/asm-mips/mach-excite/cpu-feature-overrides.h b/include/asm-mips/mach-excite/cpu-feature-overrides.h index 07f4322..107104c 100644 --- a/include/asm-mips/mach-excite/cpu-feature-overrides.h +++ b/include/asm-mips/mach-excite/cpu-feature-overrides.h @@ -34,6 +34,11 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + #define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h index 63d5bf6..1c1f924 100644 --- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h +++ b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h @@ -9,7 +9,7 @@ #define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H /* - * Sibyte are MIPS64 processors weired to a specific configuration + * Sibyte are MIPS64 processors wired to a specific configuration */ #define cpu_has_watch 1 #define cpu_has_mips16 0 @@ -33,6 +33,11 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 1 +#define cpu_has_mips64r2 0 + #define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 -- cgit v0.10.2 From b47bd961e298aff8144a98bff38cf4de4a2834b9 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Sun, 9 Sep 2007 02:50:42 +0900 Subject: [MIPS] Kill redundant EXTRA_AFLAGS Kill redundant EXTRA_AFLAGS added after the commit d2af363cfb94f1bacb3e60327bc44a97881a38c2. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle diff --git a/arch/mips/lemote/lm2e/Makefile b/arch/mips/lemote/lm2e/Makefile index dcaf6f4..d34671d 100644 --- a/arch/mips/lemote/lm2e/Makefile +++ b/arch/mips/lemote/lm2e/Makefile @@ -4,5 +4,4 @@ obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o mem.o -EXTRA_AFLAGS := $(CFLAGS) EXTRA_CFLAGS += -Werror diff --git a/arch/mips/sibyte/common/Makefile b/arch/mips/sibyte/common/Makefile index f8ae300..48a91b9 100644 --- a/arch/mips/sibyte/common/Makefile +++ b/arch/mips/sibyte/common/Makefile @@ -2,5 +2,4 @@ obj-y := obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o -EXTRA_AFLAGS := $(CFLAGS) EXTRA_CFLAGS += -Werror -- cgit v0.10.2 From ec70f65e3b5309e7ac8b5508ff5657050c92b913 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:03 +0100 Subject: [MIPS] Kill useless volatile keyword Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 6379003..3d033e1 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1075,8 +1075,8 @@ void *set_except_vector(int n, void *addr) exception_handlers[n] = handler; if (n == 0 && cpu_has_divec) { - *(volatile u32 *)(ebase + 0x200) = 0x08000000 | - (0x03ffffff & (handler >> 2)); + *(u32 *)(ebase + 0x200) = 0x08000000 | + (0x03ffffff & (handler >> 2)); flush_icache_range(ebase + 0x200, ebase + 0x204); } return (void *)old_handler; -- cgit v0.10.2 From d80c1c0b2207ba326b2c06249dfebddf8ac863bd Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Thu, 13 Sep 2007 11:04:04 +0900 Subject: [MIPS] i8295 cleanups. o Move i8259 function declarations to include/asm-mips/i8259.h o Make i8259.c functions static where possible. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index 6002164..b6e5bb4 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c @@ -30,8 +30,10 @@ static int i8259A_auto_eoi = -1; DEFINE_SPINLOCK(i8259A_lock); -/* some platforms call this... */ -void mask_and_ack_8259A(unsigned int); +static void disable_8259A_irq(unsigned int irq); +static void enable_8259A_irq(unsigned int irq); +static void mask_and_ack_8259A(unsigned int irq); +static void init_8259A(int auto_eoi); static struct irq_chip i8259A_chip = { .name = "XT-PIC", @@ -56,7 +58,7 @@ static unsigned int cached_irq_mask = 0xffff; #define cached_master_mask (cached_irq_mask) #define cached_slave_mask (cached_irq_mask >> 8) -void disable_8259A_irq(unsigned int irq) +static void disable_8259A_irq(unsigned int irq) { unsigned int mask; unsigned long flags; @@ -72,7 +74,7 @@ void disable_8259A_irq(unsigned int irq) spin_unlock_irqrestore(&i8259A_lock, flags); } -void enable_8259A_irq(unsigned int irq) +static void enable_8259A_irq(unsigned int irq) { unsigned int mask; unsigned long flags; @@ -142,7 +144,7 @@ static inline int i8259A_irq_real(unsigned int irq) * first, _then_ send the EOI, and the order of EOI * to the two 8259s is important! */ -void mask_and_ack_8259A(unsigned int irq) +static void mask_and_ack_8259A(unsigned int irq) { unsigned int irqmask; unsigned long flags; @@ -256,7 +258,7 @@ static int __init i8259A_init_sysfs(void) device_initcall(i8259A_init_sysfs); -void init_8259A(int auto_eoi) +static void init_8259A(int auto_eoi) { unsigned long flags; diff --git a/include/asm-mips/hw_irq.h b/include/asm-mips/hw_irq.h index 458d9fd..aca05a4 100644 --- a/include/asm-mips/hw_irq.h +++ b/include/asm-mips/hw_irq.h @@ -8,15 +8,8 @@ #ifndef __ASM_HW_IRQ_H #define __ASM_HW_IRQ_H -#include #include -extern void disable_8259A_irq(unsigned int irq); -extern void enable_8259A_irq(unsigned int irq); -extern int i8259A_irq_pending(unsigned int irq); -extern void make_8259A_irq(unsigned int irq); -extern void init_8259A(int aeoi); - extern atomic_t irq_err_count; /* diff --git a/include/asm-mips/i8259.h b/include/asm-mips/i8259.h index e88a016..8572a2d 100644 --- a/include/asm-mips/i8259.h +++ b/include/asm-mips/i8259.h @@ -37,9 +37,8 @@ extern spinlock_t i8259A_lock; -extern void init_8259A(int auto_eoi); -extern void enable_8259A_irq(unsigned int irq); -extern void disable_8259A_irq(unsigned int irq); +extern int i8259A_irq_pending(unsigned int irq); +extern void make_8259A_irq(unsigned int irq); extern void init_i8259_irqs(void); -- cgit v0.10.2 From 718f05f6ddc171a90fb7a277be6f6f65b4ca82be Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Wed, 12 Sep 2007 23:19:45 +0900 Subject: [MIPS] GT64120: Remove unused definitions Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/include/asm-mips/mach-mips/mach-gt64120.h b/include/asm-mips/mach-mips/mach-gt64120.h index 511f7cf..0f86314 100644 --- a/include/asm-mips/mach-mips/mach-gt64120.h +++ b/include/asm-mips/mach-mips/mach-gt64120.h @@ -16,13 +16,4 @@ extern unsigned long _pcictrl_gt64120; */ #define GT64120_BASE _pcictrl_gt64120 -/* - * PCI Bus allocation - */ -#define GT_PCI_MEM_BASE 0x12000000UL -#define GT_PCI_MEM_SIZE 0x02000000UL -#define GT_PCI_IO_BASE 0x10000000UL -#define GT_PCI_IO_SIZE 0x02000000UL -#define GT_ISA_IO_BASE PCI_IO_BASE - #endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-wrppmc/mach-gt64120.h b/include/asm-mips/mach-wrppmc/mach-gt64120.h index ba9205a..00d8bf6 100644 --- a/include/asm-mips/mach-wrppmc/mach-gt64120.h +++ b/include/asm-mips/mach-wrppmc/mach-gt64120.h @@ -43,7 +43,6 @@ #define GT_PCI_MEM_SIZE 0x02000000UL #define GT_PCI_IO_BASE 0x11000000UL #define GT_PCI_IO_SIZE 0x02000000UL -#define GT_ISA_IO_BASE PCI_IO_BASE /* * PCI interrupts will come in on either the INTA or INTD interrups lines, -- cgit v0.10.2 From d5ab1a6910fe850fa092888f210cf6c43136a7ab Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Thu, 13 Sep 2007 23:51:26 +0900 Subject: [MIPS] Add GT641xx IRQ routines. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ebc7b4b..90b409d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -64,6 +64,7 @@ config MIPS_COBALT select HW_HAS_PCI select I8259 select IRQ_CPU + select IRQ_GT641XX select PCI_GT64XXX_PCI0 select SYS_HAS_CPU_NEVADA select SYS_HAS_EARLY_PRINTK @@ -806,6 +807,9 @@ config IRQ_MSP_CIC config IRQ_TXX9 bool +config IRQ_GT641XX + bool + config MIPS_BOARDS_GEN bool diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c index 48763cd..ac4fb91 100644 --- a/arch/mips/cobalt/irq.c +++ b/arch/mips/cobalt/irq.c @@ -15,104 +15,48 @@ #include #include +#include #include -#include - -/* - * We have two types of interrupts that we handle, ones that come in through - * the CPU interrupt lines, and ones that come in on the via chip. The CPU - * mappings are: - * - * 16 - Software interrupt 0 (unused) IE_SW0 - * 17 - Software interrupt 1 (unused) IE_SW1 - * 18 - Galileo chip (timer) IE_IRQ0 - * 19 - Tulip 0 + NCR SCSI IE_IRQ1 - * 20 - Tulip 1 IE_IRQ2 - * 21 - 16550 UART IE_IRQ3 - * 22 - VIA southbridge PIC IE_IRQ4 - * 23 - unused IE_IRQ5 - * - * The VIA chip is a master/slave 8259 setup and has the following interrupts: - * - * 8 - RTC - * 9 - PCI - * 14 - IDE0 - * 15 - IDE1 - */ - -static inline void galileo_irq(void) -{ - unsigned int mask, pending, devfn; - - mask = GT_READ(GT_INTRMASK_OFS); - pending = GT_READ(GT_INTRCAUSE_OFS) & mask; - - if (pending & GT_INTR_T0EXP_MSK) { - GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK); - do_IRQ(COBALT_GALILEO_IRQ); - } else if (pending & GT_INTR_RETRYCTR0_MSK) { - devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8; - GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK); - printk(KERN_WARNING - "Galileo: PCI retry count exceeded (%02x.%u)\n", - PCI_SLOT(devfn), PCI_FUNC(devfn)); - } else { - GT_WRITE(GT_INTRMASK_OFS, mask & ~pending); - printk(KERN_WARNING - "Galileo: masking unexpected interrupt %08x\n", pending); - } -} - -static inline void via_pic_irq(void) -{ - int irq; - - irq = i8259_irq(); - if (irq >= 0) - do_IRQ(irq); -} +#include asmlinkage void plat_irq_dispatch(void) { - unsigned pending = read_c0_status() & read_c0_cause(); + unsigned pending = read_c0_status() & read_c0_cause() & ST0_IM; + int irq; - if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */ - galileo_irq(); - else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */ - via_pic_irq(); - else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */ - do_IRQ(COBALT_CPU_IRQ + 3); - else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */ - do_IRQ(COBALT_CPU_IRQ + 4); - else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */ - do_IRQ(COBALT_CPU_IRQ + 5); - else if (pending & CAUSEF_IP7) /* IRQ 23 */ - do_IRQ(COBALT_CPU_IRQ + 7); + if (pending & CAUSEF_IP2) + gt641xx_irq_dispatch(); + else if (pending & CAUSEF_IP6) { + irq = i8259_irq(); + if (irq < 0) + spurious_interrupt(); + else + do_IRQ(irq); + } else if (pending & CAUSEF_IP3) + do_IRQ(MIPS_CPU_IRQ_BASE + 3); + else if (pending & CAUSEF_IP4) + do_IRQ(MIPS_CPU_IRQ_BASE + 4); + else if (pending & CAUSEF_IP5) + do_IRQ(MIPS_CPU_IRQ_BASE + 5); + else if (pending & CAUSEF_IP7) + do_IRQ(MIPS_CPU_IRQ_BASE + 7); + else + spurious_interrupt(); } -static struct irqaction irq_via = { - .handler = no_action, - .mask = CPU_MASK_NONE, - .name = "cascade" +static struct irqaction cascade = { + .handler = no_action, + .mask = CPU_MASK_NONE, + .name = "cascade", }; void __init arch_init_irq(void) { - /* - * Mask all Galileo interrupts. The Galileo - * handler is set in cobalt_timer_setup() - */ - GT_WRITE(GT_INTRMASK_OFS, 0); - - init_i8259_irqs(); /* 0 ... 15 */ - mips_cpu_irq_init(); /* 16 ... 23 */ - - /* - * Mask all cpu interrupts - * (except IE4, we already masked those at VIA level) - */ - change_c0_status(ST0_IM, IE_IRQ4); + mips_cpu_irq_init(); + gt641xx_irq_init(); + init_i8259_irqs(); - setup_irq(COBALT_VIA_IRQ, &irq_via); + setup_irq(GT641XX_CASCADE_IRQ, &cascade); + setup_irq(I8259_CASCADE_IRQ, &cascade); } diff --git a/arch/mips/cobalt/rtc.c b/arch/mips/cobalt/rtc.c index 284daef..e70794b 100644 --- a/arch/mips/cobalt/rtc.c +++ b/arch/mips/cobalt/rtc.c @@ -20,6 +20,7 @@ #include #include #include +#include #include static struct resource cobalt_rtc_resource[] __initdata = { @@ -29,8 +30,8 @@ static struct resource cobalt_rtc_resource[] __initdata = { .flags = IORESOURCE_IO, }, { - .start = 8, - .end = 8, + .start = RTC_IRQ, + .end = RTC_IRQ, .flags = IORESOURCE_IRQ, }, }; diff --git a/arch/mips/cobalt/serial.c b/arch/mips/cobalt/serial.c index 08e7397..53b8d0d 100644 --- a/arch/mips/cobalt/serial.c +++ b/arch/mips/cobalt/serial.c @@ -24,6 +24,7 @@ #include #include +#include static struct resource cobalt_uart_resource[] __initdata = { { @@ -32,15 +33,15 @@ static struct resource cobalt_uart_resource[] __initdata = { .flags = IORESOURCE_MEM, }, { - .start = COBALT_SERIAL_IRQ, - .end = COBALT_SERIAL_IRQ, + .start = SERIAL_IRQ, + .end = SERIAL_IRQ, .flags = IORESOURCE_IRQ, }, }; static struct plat_serial8250_port cobalt_serial8250_port[] = { { - .irq = COBALT_SERIAL_IRQ, + .irq = SERIAL_IRQ, .uartclk = 18432000, .iotype = UPIO_MEM, .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c index 7abe45e..fc9cbb2 100644 --- a/arch/mips/cobalt/setup.c +++ b/arch/mips/cobalt/setup.c @@ -20,6 +20,7 @@ #include #include +#include extern void cobalt_machine_restart(char *command); extern void cobalt_machine_halt(void); @@ -45,14 +46,10 @@ void __init plat_timer_setup(struct irqaction *irq) /* Load timer value for HZ (TCLK is 50MHz) */ GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ); - /* Enable timer */ + /* Enable timer0 */ GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); - /* Register interrupt */ - setup_irq(COBALT_GALILEO_IRQ, irq); - - /* Enable interrupt */ - GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS)); + setup_irq(GT641XX_TIMER0_IRQ, irq); } /* diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 2fd96d95..7851b4b 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o +obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o obj-$(CONFIG_32BIT) += scall32-o32.o obj-$(CONFIG_64BIT) += scall64-64.o diff --git a/arch/mips/kernel/irq-gt641xx.c b/arch/mips/kernel/irq-gt641xx.c new file mode 100644 index 0000000..1b81b13 --- /dev/null +++ b/arch/mips/kernel/irq-gt641xx.c @@ -0,0 +1,131 @@ +/* + * GT641xx IRQ routines. + * + * Copyright (C) 2007 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include + +#include + +#define GT641XX_IRQ_TO_BIT(irq) (1U << (irq - GT641XX_IRQ_BASE)) + +static DEFINE_SPINLOCK(gt641xx_irq_lock); + +static void ack_gt641xx_irq(unsigned int irq) +{ + unsigned long flags; + u32 cause; + + spin_lock_irqsave(>641xx_irq_lock, flags); + cause = GT_READ(GT_INTRCAUSE_OFS); + cause &= ~GT641XX_IRQ_TO_BIT(irq); + GT_WRITE(GT_INTRCAUSE_OFS, cause); + spin_unlock_irqrestore(>641xx_irq_lock, flags); +} + +static void mask_gt641xx_irq(unsigned int irq) +{ + unsigned long flags; + u32 mask; + + spin_lock_irqsave(>641xx_irq_lock, flags); + mask = GT_READ(GT_INTRMASK_OFS); + mask &= ~GT641XX_IRQ_TO_BIT(irq); + GT_WRITE(GT_INTRMASK_OFS, mask); + spin_unlock_irqrestore(>641xx_irq_lock, flags); +} + +static void mask_ack_gt641xx_irq(unsigned int irq) +{ + unsigned long flags; + u32 cause, mask; + + spin_lock_irqsave(>641xx_irq_lock, flags); + mask = GT_READ(GT_INTRMASK_OFS); + mask &= ~GT641XX_IRQ_TO_BIT(irq); + GT_WRITE(GT_INTRMASK_OFS, mask); + + cause = GT_READ(GT_INTRCAUSE_OFS); + cause &= ~GT641XX_IRQ_TO_BIT(irq); + GT_WRITE(GT_INTRCAUSE_OFS, cause); + spin_unlock_irqrestore(>641xx_irq_lock, flags); +} + +static void unmask_gt641xx_irq(unsigned int irq) +{ + unsigned long flags; + u32 mask; + + spin_lock_irqsave(>641xx_irq_lock, flags); + mask = GT_READ(GT_INTRMASK_OFS); + mask |= GT641XX_IRQ_TO_BIT(irq); + GT_WRITE(GT_INTRMASK_OFS, mask); + spin_unlock_irqrestore(>641xx_irq_lock, flags); +} + +static struct irq_chip gt641xx_irq_chip = { + .name = "GT641xx", + .ack = ack_gt641xx_irq, + .mask = mask_gt641xx_irq, + .mask_ack = mask_ack_gt641xx_irq, + .unmask = unmask_gt641xx_irq, +}; + +void gt641xx_irq_dispatch(void) +{ + u32 cause, mask; + int i; + + cause = GT_READ(GT_INTRCAUSE_OFS); + mask = GT_READ(GT_INTRMASK_OFS); + cause &= mask; + + /* + * bit0 : logical or of all the interrupt bits. + * bit30: logical or of bits[29:26,20:1]. + * bit31: logical or of bits[25:1]. + */ + for (i = 1; i < 30; i++) { + if (cause & (1U << i)) { + do_IRQ(GT641XX_IRQ_BASE + i); + return; + } + } + + atomic_inc(&irq_err_count); +} + +void __init gt641xx_irq_init(void) +{ + int i; + + GT_WRITE(GT_INTRMASK_OFS, 0); + GT_WRITE(GT_INTRCAUSE_OFS, 0); + + /* + * bit0 : logical or of all the interrupt bits. + * bit30: logical or of bits[29:26,20:1]. + * bit31: logical or of bits[25:1]. + */ + for (i = 1; i < 30; i++) + set_irq_chip_and_handler(GT641XX_IRQ_BASE + i, + >641xx_irq_chip, handle_level_irq); +} diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c index 76b4f0f..4eb5410 100644 --- a/arch/mips/pci/fixup-cobalt.c +++ b/arch/mips/pci/fixup-cobalt.c @@ -18,6 +18,7 @@ #include #include +#include static void qube_raq_galileo_early_fixup(struct pci_dev *dev) { @@ -132,29 +133,29 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, static char irq_tab_qube1[] __initdata = { [COBALT_PCICONF_CPU] = 0, - [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ, - [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ, + [COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ, + [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ, [COBALT_PCICONF_VIA] = 0, - [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, + [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, [COBALT_PCICONF_ETH1] = 0 }; static char irq_tab_cobalt[] __initdata = { [COBALT_PCICONF_CPU] = 0, - [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, - [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ, + [COBALT_PCICONF_ETH0] = ETH0_IRQ, + [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ, [COBALT_PCICONF_VIA] = 0, - [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, - [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ + [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, + [COBALT_PCICONF_ETH1] = ETH1_IRQ }; static char irq_tab_raq2[] __initdata = { [COBALT_PCICONF_CPU] = 0, - [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, - [COBALT_PCICONF_RAQSCSI] = COBALT_RAQ_SCSI_IRQ, + [COBALT_PCICONF_ETH0] = ETH0_IRQ, + [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ, [COBALT_PCICONF_VIA] = 0, - [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, - [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ + [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, + [COBALT_PCICONF_ETH1] = ETH1_IRQ }; int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) diff --git a/include/asm-mips/irq_gt641xx.h b/include/asm-mips/irq_gt641xx.h new file mode 100644 index 0000000..f9a7c3a --- /dev/null +++ b/include/asm-mips/irq_gt641xx.h @@ -0,0 +1,60 @@ +/* + * Galileo/Marvell GT641xx IRQ definitions. + * + * Copyright (C) 2007 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef _ASM_IRQ_GT641XX_H +#define _ASM_IRQ_GT641XX_H + +#ifndef GT641XX_IRQ_BASE +#define GT641XX_IRQ_BASE 8 +#endif + +#define GT641XX_MEMORY_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 1) +#define GT641XX_DMA_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 2) +#define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 3) +#define GT641XX_DMA0_IRQ (GT641XX_IRQ_BASE + 4) +#define GT641XX_DMA1_IRQ (GT641XX_IRQ_BASE + 5) +#define GT641XX_DMA2_IRQ (GT641XX_IRQ_BASE + 6) +#define GT641XX_DMA3_IRQ (GT641XX_IRQ_BASE + 7) +#define GT641XX_TIMER0_IRQ (GT641XX_IRQ_BASE + 8) +#define GT641XX_TIMER1_IRQ (GT641XX_IRQ_BASE + 9) +#define GT641XX_TIMER2_IRQ (GT641XX_IRQ_BASE + 10) +#define GT641XX_TIMER3_IRQ (GT641XX_IRQ_BASE + 11) +#define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 12) +#define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 13) +#define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 14) +#define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 15) +#define GT641XX_PCI_0_ADDRESS_ERROR_IRQ (GT641XX_IRQ_BASE + 16) +#define GT641XX_MEMORY_ERROR_IRQ (GT641XX_IRQ_BASE + 17) +#define GT641XX_PCI_0_MASTER_ABORT_IRQ (GT641XX_IRQ_BASE + 18) +#define GT641XX_PCI_0_TARGET_ABORT_IRQ (GT641XX_IRQ_BASE + 19) +#define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ (GT641XX_IRQ_BASE + 20) +#define GT641XX_CPU_INT0_IRQ (GT641XX_IRQ_BASE + 21) +#define GT641XX_CPU_INT1_IRQ (GT641XX_IRQ_BASE + 22) +#define GT641XX_CPU_INT2_IRQ (GT641XX_IRQ_BASE + 23) +#define GT641XX_CPU_INT3_IRQ (GT641XX_IRQ_BASE + 24) +#define GT641XX_CPU_INT4_IRQ (GT641XX_IRQ_BASE + 25) +#define GT641XX_PCI_INT0_IRQ (GT641XX_IRQ_BASE + 26) +#define GT641XX_PCI_INT1_IRQ (GT641XX_IRQ_BASE + 27) +#define GT641XX_PCI_INT2_IRQ (GT641XX_IRQ_BASE + 28) +#define GT641XX_PCI_INT3_IRQ (GT641XX_IRQ_BASE + 29) + +extern void gt641xx_irq_dispatch(void); +extern void gt641xx_irq_init(void); + +#endif /* _ASM_IRQ_GT641XX_H */ diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h index 9c9d2b9..408eecc 100644 --- a/include/asm-mips/mach-cobalt/cobalt.h +++ b/include/asm-mips/mach-cobalt/cobalt.h @@ -12,32 +12,6 @@ #ifndef __ASM_COBALT_H #define __ASM_COBALT_H -#include - -/* - * i8259 legacy interrupts used on Cobalt: - * - * 8 - RTC - * 9 - PCI - * 14 - IDE0 - * 15 - IDE1 - */ -#define COBALT_QUBE_SLOT_IRQ 9 - -/* - * CPU IRQs are 16 ... 23 - */ -#define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE - -#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2) -#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3) -#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3) -#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4) -#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4) -#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5) -#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5) -#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */ - /* * PCI configuration space manifest constants. These are wired into * the board layout according to the PCI spec to enable the software diff --git a/include/asm-mips/mach-cobalt/irq.h b/include/asm-mips/mach-cobalt/irq.h new file mode 100644 index 0000000..179d0e8 --- /dev/null +++ b/include/asm-mips/mach-cobalt/irq.h @@ -0,0 +1,58 @@ +/* + * Cobalt IRQ definitions. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1997 Cobalt Microserver + * Copyright (C) 1997, 2003 Ralf Baechle + * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv) + * Copyright (C) 2007 Yoichi Yuasa + */ +#ifndef _ASM_COBALT_IRQ_H +#define _ASM_COBALT_IRQ_H + +/* + * i8259 interrupts used on Cobalt: + * + * 8 - RTC + * 9 - PCI slot + * 14 - IDE0 + * 15 - IDE1(no connector on board) + */ +#define I8259A_IRQ_BASE 0 + +#define PCISLOT_IRQ (I8259A_IRQ_BASE + 9) + +/* + * CPU interrupts used on Cobalt: + * + * 0 - Software interrupt 0 (unused) + * 1 - Software interrupt 0 (unused) + * 2 - cascade GT64111 + * 3 - ethernet or SCSI host controller + * 4 - ethernet + * 5 - 16550 UART + * 6 - cascade i8259 + * 7 - CP0 counter (unused) + */ +#define MIPS_CPU_IRQ_BASE 16 + +#define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2) +#define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3) +#define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3) +#define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4) +#define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4) +#define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5) +#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5) +#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6) + + +#define GT641XX_IRQ_BASE 24 + +#include + +#define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1) + +#endif /* _ASM_COBALT_IRQ_H */ -- cgit v0.10.2 From 0f5c90644240cc17d5940fa3594cc51ad1ae7ba7 Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Sat, 15 Sep 2007 23:35:53 +0200 Subject: [MIPS] Introduce a consistent style for vmlinux.lds. This style will be consitent with all other arch's - soon. In addition: - Moved a few labels inside brackets for the sections they specify to prevent that linker alignmnet made them point before the section start Signed-off-by: Sam Ravnborg Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 087ab99..84f9a4c 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -6,163 +6,202 @@ OUTPUT_ARCH(mips) ENTRY(kernel_entry) jiffies = JIFFIES; + SECTIONS { #ifdef CONFIG_BOOT_ELF64 - /* Read-only sections, merged into text segment: */ - /* . = 0xc000000000000000; */ + /* Read-only sections, merged into text segment: */ + /* . = 0xc000000000000000; */ - /* This is the value for an Origin kernel, taken from an IRIX kernel. */ - /* . = 0xc00000000001c000; */ + /* This is the value for an Origin kernel, taken from an IRIX kernel. */ + /* . = 0xc00000000001c000; */ - /* Set the vaddr for the text segment to a value - >= 0xa800 0000 0001 9000 if no symmon is going to configured - >= 0xa800 0000 0030 0000 otherwise */ + /* Set the vaddr for the text segment to a value + * >= 0xa800 0000 0001 9000 if no symmon is going to configured + * >= 0xa800 0000 0030 0000 otherwise + */ - /* . = 0xa800000000300000; */ - /* . = 0xa800000000300000; */ - . = 0xffffffff80300000; + /* . = 0xa800000000300000; */ + /* . = 0xa800000000300000; */ + . = 0xffffffff80300000; #endif - . = LOADADDR; - /* read-only */ - _text = .; /* Text and read-only data */ - .text : { - TEXT_TEXT - SCHED_TEXT - LOCK_TEXT - *(.fixup) - *(.gnu.warning) - } =0 - - _etext = .; /* End of text section */ - - . = ALIGN(16); /* Exception table */ - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - __start___dbe_table = .; /* Exception table for data bus errors */ - __dbe_table : { *(__dbe_table) } - __stop___dbe_table = .; - - NOTES - - RODATA - - /* writeable */ - .data : { /* Data */ - . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ - /* - * This ALIGN is needed as a workaround for a bug a gcc bug upto 4.1 which - * limits the maximum alignment to at most 32kB and results in the following - * warning: - * - * CC arch/mips/kernel/init_task.o - * arch/mips/kernel/init_task.c:30: warning: alignment of ‘init_thread_union’ - * is greater than maximum object file alignment. Using 32768 - */ - . = ALIGN(_PAGE_SIZE); - *(.data.init_task) - - DATA_DATA - - CONSTRUCTORS - } - _gp = . + 0x8000; - .lit8 : { *(.lit8) } - .lit4 : { *(.lit4) } - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata : { *(.sdata) } - - . = ALIGN(_PAGE_SIZE); - __nosave_begin = .; - .data_nosave : { *(.data.nosave) } - . = ALIGN(_PAGE_SIZE); - __nosave_end = .; - - . = ALIGN(32); - .data.cacheline_aligned : { *(.data.cacheline_aligned) } - - _edata = .; /* End of data section */ - - /* will be freed after init */ - . = ALIGN(_PAGE_SIZE); /* Init code and data */ - __init_begin = .; - .init.text : { - _sinittext = .; - *(.init.text) - _einittext = .; - } - .init.data : { *(.init.data) } - . = ALIGN(16); - __setup_start = .; - .init.setup : { *(.init.setup) } - __setup_end = .; - - __initcall_start = .; - .initcall.init : { - INITCALLS - } - __initcall_end = .; - - __con_initcall_start = .; - .con_initcall.init : { *(.con_initcall.init) } - __con_initcall_end = .; - SECURITY_INIT - /* .exit.text is discarded at runtime, not link time, to deal with - references from .rodata */ - .exit.text : { *(.exit.text) } - .exit.data : { *(.exit.data) } + . = LOADADDR; + /* read-only */ + _text = .; /* Text and read-only data */ + .text : { + TEXT_TEXT + SCHED_TEXT + LOCK_TEXT + *(.fixup) + *(.gnu.warning) + } =0 + _etext = .; /* End of text section */ + + /* Exception table */ + . = ALIGN(16); + __ex_table : { + __start___ex_table = .; + *(__ex_table) + __stop___ex_table = .; + } + + /* Exception table for data bus errors */ + __dbe_table : { + __start___dbe_table = .; + *(__dbe_table) + __stop___dbe_table = .; + } + RODATA + + /* writeable */ + .data : { /* Data */ + . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ + /* + * This ALIGN is needed as a workaround for a bug a gcc bug upto 4.1 which + * limits the maximum alignment to at most 32kB and results in the following + * warning: + * + * CC arch/mips/kernel/init_task.o + * arch/mips/kernel/init_task.c:30: warning: alignment of ‘init_thread_union’ + * is greater than maximum object file alignment. Using 32768 + */ + . = ALIGN(_PAGE_SIZE); + *(.data.init_task) + + DATA_DATA + CONSTRUCTORS + } + _gp = . + 0x8000; + .lit8 : { + *(.lit8) + } + .lit4 : { + *(.lit4) + } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata : { + *(.sdata) + } + + . = ALIGN(_PAGE_SIZE); + .data_nosave : { + __nosave_begin = .; + *(.data.nosave) + } + . = ALIGN(_PAGE_SIZE); + __nosave_end = .; + + . = ALIGN(32); + .data.cacheline_aligned : { + *(.data.cacheline_aligned) + } + _edata = .; /* End of data section */ + + /* will be freed after init */ + . = ALIGN(_PAGE_SIZE); /* Init code and data */ + __init_begin = .; + .init.text : { + _sinittext = .; + *(.init.text) + _einittext = .; + } + .init.data : { + *(.init.data) + } + . = ALIGN(16); + .init.setup : { + __setup_start = .; + *(.init.setup) + __setup_end = .; + } + + .initcall.init : { + __initcall_start = .; + INITCALLS + __initcall_end = .; + } + + .con_initcall.init : { + __con_initcall_start = .; + *(.con_initcall.init) + __con_initcall_end = .; + } + SECURITY_INIT + + /* .exit.text is discarded at runtime, not link time, to deal with + * references from .rodata + */ + .exit.text : { + *(.exit.text) + } + .exit.data : { + *(.exit.data) + } #if defined(CONFIG_BLK_DEV_INITRD) - . = ALIGN(_PAGE_SIZE); - __initramfs_start = .; - .init.ramfs : { *(.init.ramfs) } - __initramfs_end = .; + . = ALIGN(_PAGE_SIZE); + .init.ramfs : { + __initramfs_start = .; + *(.init.ramfs) + __initramfs_end = .; + } #endif - PERCPU(_PAGE_SIZE) - . = ALIGN(_PAGE_SIZE); - __init_end = .; - /* freed after init ends here */ - - __bss_start = .; /* BSS */ - .sbss : { - *(.sbss) - *(.scommon) - } - .bss : { - *(.bss) - *(COMMON) - } - __bss_stop = .; - - _end = . ; - - /* Sections to be discarded */ - /DISCARD/ : { - *(.exitcall.exit) - - /* ABI crap starts here */ - *(.MIPS.options) - *(.options) - *(.pdr) - *(.reginfo) - } - - /* These mark the ABI of the kernel for debuggers. */ - .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) } - .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) } - - /* This is the MIPS specific mdebug section. */ - .mdebug : { *(.mdebug) } - - STABS_DEBUG - - DWARF_DEBUG - - /* These must appear regardless of . */ - .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } - .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } - .note : { *(.note) } + PERCPU(_PAGE_SIZE) + . = ALIGN(_PAGE_SIZE); + __init_end = .; + /* freed after init ends here */ + + __bss_start = .; /* BSS */ + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + __bss_stop = .; + + _end = . ; + + /* Sections to be discarded */ + /DISCARD/ : { + *(.exitcall.exit) + + /* ABI crap starts here */ + *(.MIPS.options) + *(.options) + *(.pdr) + *(.reginfo) + } + + /* These mark the ABI of the kernel for debuggers. */ + .mdebug.abi32 : { + KEEP(*(.mdebug.abi32)) + } + .mdebug.abi64 : { + KEEP(*(.mdebug.abi64)) + } + + /* This is the MIPS specific mdebug section. */ + .mdebug : { + *(.mdebug) + } + + STABS_DEBUG + DWARF_DEBUG + + /* These must appear regardless of . */ + .gptab.sdata : { + *(.gptab.data) + *(.gptab.sdata) + } + .gptab.sbss : { + *(.gptab.bss) + *(.gptab.sbss) + } + .note : { + *(.note) + } } -- cgit v0.10.2 From e5d77754c5e1a54f9eb61c03085d7932a0b6b738 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Tue, 18 Sep 2007 18:49:08 +0100 Subject: [MIPS] R3000 setup for kernel_thread() Match the R4000 semantics for the initial state of interrupt/kernel status register flags for the R3000 in kernel_thread(). Signed-off-by: Maciej W. Rozycki Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index e6ce943..aadd2cd 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -231,8 +231,8 @@ long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) regs.cp0_epc = (unsigned long) kernel_thread_helper; regs.cp0_status = read_c0_status(); #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) - regs.cp0_status &= ~(ST0_KUP | ST0_IEC); - regs.cp0_status |= ST0_IEP; + regs.cp0_status = (regs.cp0_status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) | + ((regs.cp0_status & (ST0_KUC | ST0_IEC)) << 2); #else regs.cp0_status |= ST0_EXL; #endif -- cgit v0.10.2 From 7c4b4773b9b6c440837e5a479204d7bd1b804a43 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:05 +0100 Subject: [MIPS] Sibyte: cleanup static inline forward declarations. In fact there are no foward declarations at all needed when moving things into the right order. Signed-off-by: Ralf Baechle diff --git a/arch/mips/sibyte/bcm1480/setup.c b/arch/mips/sibyte/bcm1480/setup.c index 7e1aa34..05ed92c 100644 --- a/arch/mips/sibyte/bcm1480/setup.c +++ b/arch/mips/sibyte/bcm1480/setup.c @@ -43,16 +43,49 @@ static unsigned int part_type; static char *soc_str; static char *pass_str; -static inline int setup_bcm1x80_bcm1x55(void); +static int __init setup_bcm1x80_bcm1x55(void) +{ + int ret = 0; + + switch (soc_pass) { + case K_SYS_REVISION_BCM1480_S0: + periph_rev = 1; + pass_str = "S0 (pass1)"; + break; + case K_SYS_REVISION_BCM1480_A1: + periph_rev = 1; + pass_str = "A1 (pass1)"; + break; + case K_SYS_REVISION_BCM1480_A2: + periph_rev = 1; + pass_str = "A2 (pass1)"; + break; + case K_SYS_REVISION_BCM1480_A3: + periph_rev = 1; + pass_str = "A3 (pass1)"; + break; + case K_SYS_REVISION_BCM1480_B0: + periph_rev = 1; + pass_str = "B0 (pass2)"; + break; + default: + printk("Unknown %s rev %x\n", soc_str, soc_pass); + periph_rev = 1; + pass_str = "Unknown Revision"; + break; + } + + return ret; +} /* Setup code likely to be common to all SiByte platforms */ -static inline int sys_rev_decode(void) +static int __init sys_rev_decode(void) { int ret = 0; switch (soc_type) { - case K_SYS_SOC_TYPE_BCM1x80: + case K_SYS_SOC_TYPE_BCM1x80: if (part_type == K_SYS_PART_BCM1480) soc_str = "BCM1480"; else if (part_type == K_SYS_PART_BCM1280) @@ -62,7 +95,7 @@ static inline int sys_rev_decode(void) ret = setup_bcm1x80_bcm1x55(); break; - case K_SYS_SOC_TYPE_BCM1x55: + case K_SYS_SOC_TYPE_BCM1x55: if (part_type == K_SYS_PART_BCM1455) soc_str = "BCM1455"; else if (part_type == K_SYS_PART_BCM1255) @@ -72,49 +105,16 @@ static inline int sys_rev_decode(void) ret = setup_bcm1x80_bcm1x55(); break; - default: + default: printk("Unknown part type %x\n", part_type); ret = 1; break; } - return ret; -} -static inline int setup_bcm1x80_bcm1x55(void) -{ - int ret = 0; - - switch (soc_pass) { - case K_SYS_REVISION_BCM1480_S0: - periph_rev = 1; - pass_str = "S0 (pass1)"; - break; - case K_SYS_REVISION_BCM1480_A1: - periph_rev = 1; - pass_str = "A1 (pass1)"; - break; - case K_SYS_REVISION_BCM1480_A2: - periph_rev = 1; - pass_str = "A2 (pass1)"; - break; - case K_SYS_REVISION_BCM1480_A3: - periph_rev = 1; - pass_str = "A3 (pass1)"; - break; - case K_SYS_REVISION_BCM1480_B0: - periph_rev = 1; - pass_str = "B0 (pass2)"; - break; - default: - printk("Unknown %s rev %x\n", soc_str, soc_pass); - periph_rev = 1; - pass_str = "Unknown Revision"; - break; - } return ret; } -void bcm1480_setup(void) +void __init bcm1480_setup(void) { uint64_t sys_rev; int plldiv; diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c index 2d5c6d8b..0444da1 100644 --- a/arch/mips/sibyte/sb1250/setup.c +++ b/arch/mips/sibyte/sb1250/setup.c @@ -40,43 +40,6 @@ static char *soc_str; static char *pass_str; static unsigned int war_pass; /* XXXKW don't overload PASS defines? */ -static inline int setup_bcm1250(void); -static inline int setup_bcm112x(void); - -/* Setup code likely to be common to all SiByte platforms */ - -static int __init sys_rev_decode(void) -{ - int ret = 0; - - war_pass = soc_pass; - switch (soc_type) { - case K_SYS_SOC_TYPE_BCM1250: - case K_SYS_SOC_TYPE_BCM1250_ALT: - case K_SYS_SOC_TYPE_BCM1250_ALT2: - soc_str = "BCM1250"; - ret = setup_bcm1250(); - break; - case K_SYS_SOC_TYPE_BCM1120: - soc_str = "BCM1120"; - ret = setup_bcm112x(); - break; - case K_SYS_SOC_TYPE_BCM1125: - soc_str = "BCM1125"; - ret = setup_bcm112x(); - break; - case K_SYS_SOC_TYPE_BCM1125H: - soc_str = "BCM1125H"; - ret = setup_bcm112x(); - break; - default: - printk("Unknown SOC type %x\n", soc_type); - ret = 1; - break; - } - return ret; -} - static int __init setup_bcm1250(void) { int ret = 0; @@ -120,6 +83,7 @@ static int __init setup_bcm1250(void) } break; } + return ret; } @@ -158,6 +122,42 @@ static int __init setup_bcm112x(void) printk("Unknown %s rev %x\n", soc_str, soc_pass); ret = 1; } + + return ret; +} + +/* Setup code likely to be common to all SiByte platforms */ + +static int __init sys_rev_decode(void) +{ + int ret = 0; + + war_pass = soc_pass; + switch (soc_type) { + case K_SYS_SOC_TYPE_BCM1250: + case K_SYS_SOC_TYPE_BCM1250_ALT: + case K_SYS_SOC_TYPE_BCM1250_ALT2: + soc_str = "BCM1250"; + ret = setup_bcm1250(); + break; + case K_SYS_SOC_TYPE_BCM1120: + soc_str = "BCM1120"; + ret = setup_bcm112x(); + break; + case K_SYS_SOC_TYPE_BCM1125: + soc_str = "BCM1125"; + ret = setup_bcm112x(); + break; + case K_SYS_SOC_TYPE_BCM1125H: + soc_str = "BCM1125H"; + ret = setup_bcm112x(); + break; + default: + printk("Unknown SOC type %x\n", soc_type); + ret = 1; + break; + } + return ret; } -- cgit v0.10.2 From 424b28ba4d25fc41abdb7e6fa90e132f0d9558fb Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:05 +0100 Subject: [MIPS] Alchemy: remove useless prototypes. Signed-off-by: Ralf Baechle diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c index ea6e99f..db2ba0d 100644 --- a/arch/mips/au1000/common/irq.c +++ b/arch/mips/au1000/common/irq.c @@ -65,19 +65,8 @@ #define EXT_INTC1_REQ1 5 /* IP 5 */ #define MIPS_TIMER_IP 7 /* IP 7 */ -extern void set_debug_traps(void); -extern irq_cpustat_t irq_stat [NR_CPUS]; extern void mips_timer_interrupt(void); -static void setup_local_irq(unsigned int irq, int type, int int_req); -static void end_irq(unsigned int irq_nr); -static inline void mask_and_ack_level_irq(unsigned int irq_nr); -static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr); -static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr); -static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr); -inline void local_enable_irq(unsigned int irq_nr); -inline void local_disable_irq(unsigned int irq_nr); - void (*board_init_irq)(void); static DEFINE_SPINLOCK(irq_lock); -- cgit v0.10.2 From 641e97f318870921d048154af6807e46e43c307a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:05 +0100 Subject: [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 97c0386..dde2adf 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -746,14 +746,6 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) { decode_configs(c); - /* - * For historical reasons the SB1 comes with it's own variant of - * cache code which eventually will be folded into c-r4k.c. Until - * then we pretend it's got it's own cache architecture. - */ - c->options &= ~MIPS_CPU_4K_CACHE; - c->options |= MIPS_CPU_SB1_CACHE; - switch (c->processor_id & 0xff00) { case PRID_IMP_SB1: c->cputype = CPU_SB1; diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 3d033e1..d96f821 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1435,6 +1435,9 @@ void __init set_handler (unsigned long offset, void *addr, unsigned long size) flush_icache_range(ebase + offset, ebase + offset + size); } +static char panic_null_cerr[] __initdata = + "Trying to set NULL cache error exception handler"; + /* Install uncached CPU exception handler */ void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size) { @@ -1445,6 +1448,9 @@ void __init set_uncached_handler (unsigned long offset, void *addr, unsigned lon unsigned long uncached_ebase = TO_UNCAC(ebase); #endif + if (!addr) + panic(panic_null_cerr); + memcpy((void *)(uncached_ebase + offset), addr, size); } diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 43e4810..32fd5db 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -22,7 +22,7 @@ obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r8k.o obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o -obj-$(CONFIG_CPU_SB1) += c-sb1.o cerr-sb1.o cex-sb1.o pg-sb1.o \ +obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o pg-sb1.o \ tlb-r4k.o obj-$(CONFIG_CPU_TX39XX) += c-tx39.o pg-r4k.o tlb-r3k.o obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index bad5719..738b898 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -9,6 +9,7 @@ */ #include #include +#include #include #include #include @@ -948,12 +949,16 @@ static void __init probe_pcache(void) switch (c->cputype) { case CPU_20KC: case CPU_25KF: + case CPU_SB1: + case CPU_SB1A: c->dcache.flags |= MIPS_CACHE_PINDEX; + break; + case CPU_R10000: case CPU_R12000: case CPU_R14000: - case CPU_SB1: break; + case CPU_24K: case CPU_34K: case CPU_74K: @@ -1235,11 +1240,20 @@ void __init r4k_cache_init(void) { extern void build_clear_page(void); extern void build_copy_page(void); - extern char except_vec2_generic; + extern char __weak except_vec2_generic; + extern char __weak except_vec2_sb1; struct cpuinfo_mips *c = ¤t_cpu_data; - /* Default cache error handler for R4000 and R5000 family */ - set_uncached_handler (0x100, &except_vec2_generic, 0x80); + switch (c->cputype) { + case CPU_SB1: + case CPU_SB1A: + set_uncached_handler(0x100, &except_vec2_sb1, 0x80); + break; + + default: + set_uncached_handler(0x100, &except_vec2_generic, 0x80); + break; + } probe_pcache(); setup_scache(); diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c deleted file mode 100644 index 85ce284..0000000 --- a/arch/mips/mm/c-sb1.c +++ /dev/null @@ -1,535 +0,0 @@ -/* - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation - * Copyright (C) 2004 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -extern void sb1_dma_init(void); - -/* These are probed at ld_mmu time */ -static unsigned long icache_size; -static unsigned long dcache_size; - -static unsigned short icache_line_size; -static unsigned short dcache_line_size; - -static unsigned int icache_index_mask; -static unsigned int dcache_index_mask; - -static unsigned short icache_assoc; -static unsigned short dcache_assoc; - -static unsigned short icache_sets; -static unsigned short dcache_sets; - -static unsigned int icache_range_cutoff; -static unsigned int dcache_range_cutoff; - -static inline void sb1_on_each_cpu(void (*func) (void *info), void *info, - int retry, int wait) -{ - preempt_disable(); - smp_call_function(func, info, retry, wait); - func(info); - preempt_enable(); -} - -/* - * The dcache is fully coherent to the system, with one - * big caveat: the instruction stream. In other words, - * if we miss in the icache, and have dirty data in the - * L1 dcache, then we'll go out to memory (or the L2) and - * get the not-as-recent data. - * - * So the only time we have to flush the dcache is when - * we're flushing the icache. Since the L2 is fully - * coherent to everything, including I/O, we never have - * to flush it - */ - -#define cache_set_op(op, addr) \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips64\n\t \n" \ - " cache %0, (0<<13)(%1) \n" \ - " cache %0, (1<<13)(%1) \n" \ - " cache %0, (2<<13)(%1) \n" \ - " cache %0, (3<<13)(%1) \n" \ - " .set mips0 \n" \ - " .set reorder" \ - : \ - : "i" (op), "r" (addr)) - -#define sync() \ - __asm__ __volatile( \ - " .set mips64\n\t \n" \ - " sync \n" \ - " .set mips0") - -#define mispredict() \ - __asm__ __volatile__( \ - " bnezl $0, 1f \n" /* Force mispredict */ \ - "1: \n"); - -/* - * Writeback and invalidate the entire dcache - */ -static inline void __sb1_writeback_inv_dcache_all(void) -{ - unsigned long addr = 0; - - while (addr < dcache_line_size * dcache_sets) { - cache_set_op(Index_Writeback_Inv_D, addr); - addr += dcache_line_size; - } -} - -/* - * Writeback and invalidate a range of the dcache. The addresses are - * virtual, and since we're using index ops and bit 12 is part of both - * the virtual frame and physical index, we have to clear both sets - * (bit 12 set and cleared). - */ -static inline void __sb1_writeback_inv_dcache_range(unsigned long start, - unsigned long end) -{ - unsigned long index; - - start &= ~(dcache_line_size - 1); - end = (end + dcache_line_size - 1) & ~(dcache_line_size - 1); - - while (start != end) { - index = start & dcache_index_mask; - cache_set_op(Index_Writeback_Inv_D, index); - cache_set_op(Index_Writeback_Inv_D, index ^ (1<<12)); - start += dcache_line_size; - } - sync(); -} - -/* - * Writeback and invalidate a range of the dcache. With physical - * addresseses, we don't have to worry about possible bit 12 aliasing. - * XXXKW is it worth turning on KX and using hit ops with xkphys? - */ -static inline void __sb1_writeback_inv_dcache_phys_range(unsigned long start, - unsigned long end) -{ - start &= ~(dcache_line_size - 1); - end = (end + dcache_line_size - 1) & ~(dcache_line_size - 1); - - while (start != end) { - cache_set_op(Index_Writeback_Inv_D, start & dcache_index_mask); - start += dcache_line_size; - } - sync(); -} - - -/* - * Invalidate the entire icache - */ -static inline void __sb1_flush_icache_all(void) -{ - unsigned long addr = 0; - - while (addr < icache_line_size * icache_sets) { - cache_set_op(Index_Invalidate_I, addr); - addr += icache_line_size; - } -} - -/* - * Invalidate a range of the icache. The addresses are virtual, and - * the cache is virtually indexed and tagged. However, we don't - * necessarily have the right ASID context, so use index ops instead - * of hit ops. - */ -static inline void __sb1_flush_icache_range(unsigned long start, - unsigned long end) -{ - start &= ~(icache_line_size - 1); - end = (end + icache_line_size - 1) & ~(icache_line_size - 1); - - while (start != end) { - cache_set_op(Index_Invalidate_I, start & icache_index_mask); - start += icache_line_size; - } - mispredict(); - sync(); -} - -/* - * Flush the icache for a given physical page. Need to writeback the - * dcache first, then invalidate the icache. If the page isn't - * executable, nothing is required. - */ -static void local_sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn) -{ - int cpu = smp_processor_id(); - -#ifndef CONFIG_SMP - if (!(vma->vm_flags & VM_EXEC)) - return; -#endif - - __sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE); - - /* - * Bumping the ASID is probably cheaper than the flush ... - */ - if (vma->vm_mm == current->active_mm) { - if (cpu_context(cpu, vma->vm_mm) != 0) - drop_mmu_context(vma->vm_mm, cpu); - } else - __sb1_flush_icache_range(addr, addr + PAGE_SIZE); -} - -#ifdef CONFIG_SMP -struct flush_cache_page_args { - struct vm_area_struct *vma; - unsigned long addr; - unsigned long pfn; -}; - -static void sb1_flush_cache_page_ipi(void *info) -{ - struct flush_cache_page_args *args = info; - - local_sb1_flush_cache_page(args->vma, args->addr, args->pfn); -} - -/* Dirty dcache could be on another CPU, so do the IPIs */ -static void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn) -{ - struct flush_cache_page_args args; - - if (!(vma->vm_flags & VM_EXEC)) - return; - - addr &= PAGE_MASK; - args.vma = vma; - args.addr = addr; - args.pfn = pfn; - sb1_on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1); -} -#else -void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn) - __attribute__((alias("local_sb1_flush_cache_page"))); -#endif - -#ifdef CONFIG_SMP -static void sb1_flush_cache_data_page_ipi(void *info) -{ - unsigned long start = (unsigned long)info; - - __sb1_writeback_inv_dcache_range(start, start + PAGE_SIZE); -} - -static void sb1_flush_cache_data_page(unsigned long addr) -{ - if (in_atomic()) - __sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE); - else - on_each_cpu(sb1_flush_cache_data_page_ipi, (void *) addr, 1, 1); -} -#else - -static void local_sb1_flush_cache_data_page(unsigned long addr) -{ - __sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE); -} - -void sb1_flush_cache_data_page(unsigned long) - __attribute__((alias("local_sb1_flush_cache_data_page"))); -#endif - -/* - * Invalidate all caches on this CPU - */ -static void __used local_sb1___flush_cache_all(void) -{ - __sb1_writeback_inv_dcache_all(); - __sb1_flush_icache_all(); -} - -#ifdef CONFIG_SMP -void sb1___flush_cache_all_ipi(void *ignored) - __attribute__((alias("local_sb1___flush_cache_all"))); - -static void sb1___flush_cache_all(void) -{ - sb1_on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1); -} -#else -void sb1___flush_cache_all(void) - __attribute__((alias("local_sb1___flush_cache_all"))); -#endif - -/* - * When flushing a range in the icache, we have to first writeback - * the dcache for the same range, so new ifetches will see any - * data that was dirty in the dcache. - * - * The start/end arguments are Kseg addresses (possibly mapped Kseg). - */ - -static void local_sb1_flush_icache_range(unsigned long start, - unsigned long end) -{ - /* Just wb-inv the whole dcache if the range is big enough */ - if ((end - start) > dcache_range_cutoff) - __sb1_writeback_inv_dcache_all(); - else - __sb1_writeback_inv_dcache_range(start, end); - - /* Just flush the whole icache if the range is big enough */ - if ((end - start) > icache_range_cutoff) - __sb1_flush_icache_all(); - else - __sb1_flush_icache_range(start, end); -} - -#ifdef CONFIG_SMP -struct flush_icache_range_args { - unsigned long start; - unsigned long end; -}; - -static void sb1_flush_icache_range_ipi(void *info) -{ - struct flush_icache_range_args *args = info; - - local_sb1_flush_icache_range(args->start, args->end); -} - -void sb1_flush_icache_range(unsigned long start, unsigned long end) -{ - struct flush_icache_range_args args; - - args.start = start; - args.end = end; - sb1_on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1); -} -#else -void sb1_flush_icache_range(unsigned long start, unsigned long end) - __attribute__((alias("local_sb1_flush_icache_range"))); -#endif - -/* - * A signal trampoline must fit into a single cacheline. - */ -static void local_sb1_flush_cache_sigtramp(unsigned long addr) -{ - cache_set_op(Index_Writeback_Inv_D, addr & dcache_index_mask); - cache_set_op(Index_Writeback_Inv_D, (addr ^ (1<<12)) & dcache_index_mask); - cache_set_op(Index_Invalidate_I, addr & icache_index_mask); - mispredict(); -} - -#ifdef CONFIG_SMP -static void sb1_flush_cache_sigtramp_ipi(void *info) -{ - unsigned long iaddr = (unsigned long) info; - local_sb1_flush_cache_sigtramp(iaddr); -} - -static void sb1_flush_cache_sigtramp(unsigned long addr) -{ - sb1_on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1); -} -#else -void sb1_flush_cache_sigtramp(unsigned long addr) - __attribute__((alias("local_sb1_flush_cache_sigtramp"))); -#endif - - -/* - * Anything that just flushes dcache state can be ignored, as we're always - * coherent in dcache space. This is just a dummy function that all the - * nop'ed routines point to - */ -static void sb1_nop(void) -{ -} - -/* - * Cache set values (from the mips64 spec) - * 0 - 64 - * 1 - 128 - * 2 - 256 - * 3 - 512 - * 4 - 1024 - * 5 - 2048 - * 6 - 4096 - * 7 - Reserved - */ - -static unsigned int decode_cache_sets(unsigned int config_field) -{ - if (config_field == 7) { - /* JDCXXX - Find a graceful way to abort. */ - return 0; - } - return (1<<(config_field + 6)); -} - -/* - * Cache line size values (from the mips64 spec) - * 0 - No cache present. - * 1 - 4 bytes - * 2 - 8 bytes - * 3 - 16 bytes - * 4 - 32 bytes - * 5 - 64 bytes - * 6 - 128 bytes - * 7 - Reserved - */ - -static unsigned int decode_cache_line_size(unsigned int config_field) -{ - if (config_field == 0) { - return 0; - } else if (config_field == 7) { - /* JDCXXX - Find a graceful way to abort. */ - return 0; - } - return (1<<(config_field + 1)); -} - -/* - * Relevant bits of the config1 register format (from the MIPS32/MIPS64 specs) - * - * 24:22 Icache sets per way - * 21:19 Icache line size - * 18:16 Icache Associativity - * 15:13 Dcache sets per way - * 12:10 Dcache line size - * 9:7 Dcache Associativity - */ - -static char *way_string[] = { - "direct mapped", "2-way", "3-way", "4-way", - "5-way", "6-way", "7-way", "8-way", -}; - -static __init void probe_cache_sizes(void) -{ - u32 config1; - - config1 = read_c0_config1(); - icache_line_size = decode_cache_line_size((config1 >> 19) & 0x7); - dcache_line_size = decode_cache_line_size((config1 >> 10) & 0x7); - icache_sets = decode_cache_sets((config1 >> 22) & 0x7); - dcache_sets = decode_cache_sets((config1 >> 13) & 0x7); - icache_assoc = ((config1 >> 16) & 0x7) + 1; - dcache_assoc = ((config1 >> 7) & 0x7) + 1; - icache_size = icache_line_size * icache_sets * icache_assoc; - dcache_size = dcache_line_size * dcache_sets * dcache_assoc; - /* Need to remove non-index bits for index ops */ - icache_index_mask = (icache_sets - 1) * icache_line_size; - dcache_index_mask = (dcache_sets - 1) * dcache_line_size; - /* - * These are for choosing range (index ops) versus all. - * icache flushes all ways for each set, so drop icache_assoc. - * dcache flushes all ways and each setting of bit 12 for each - * index, so drop dcache_assoc and halve the dcache_sets. - */ - icache_range_cutoff = icache_sets * icache_line_size; - dcache_range_cutoff = (dcache_sets / 2) * icache_line_size; - - printk("Primary instruction cache %ldkB, %s, linesize %d bytes.\n", - icache_size >> 10, way_string[icache_assoc - 1], - icache_line_size); - printk("Primary data cache %ldkB, %s, linesize %d bytes.\n", - dcache_size >> 10, way_string[dcache_assoc - 1], - dcache_line_size); -} - -/* - * This is called from cache.c. We have to set up all the - * memory management function pointers, as well as initialize - * the caches and tlbs - */ -void __init sb1_cache_init(void) -{ - extern char except_vec2_sb1; - - /* Special cache error handler for SB1 */ - set_uncached_handler (0x100, &except_vec2_sb1, 0x80); - - probe_cache_sizes(); - -#ifdef CONFIG_SIBYTE_DMA_PAGEOPS - sb1_dma_init(); -#endif - - /* - * None of these are needed for the SB1 - the Dcache is - * physically indexed and tagged, so no virtual aliasing can - * occur - */ - flush_cache_range = (void *) sb1_nop; - flush_cache_mm = (void (*)(struct mm_struct *))sb1_nop; - flush_cache_all = sb1_nop; - - /* These routines are for Icache coherence with the Dcache */ - flush_icache_range = sb1_flush_icache_range; - flush_icache_all = __sb1_flush_icache_all; /* local only */ - - /* This implies an Icache flush too, so can't be nop'ed */ - flush_cache_page = sb1_flush_cache_page; - - flush_cache_sigtramp = sb1_flush_cache_sigtramp; - local_flush_data_cache_page = (void *) sb1_nop; - flush_data_cache_page = sb1_flush_cache_data_page; - - /* Full flush */ - __flush_cache_all = sb1___flush_cache_all; - - change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); - - /* - * This is the only way to force the update of K0 to complete - * before subsequent instruction fetch. - */ - __asm__ __volatile__( - ".set push \n" - " .set noat \n" - " .set noreorder \n" - " .set mips3 \n" - " " STR(PTR_LA) " $1, 1f \n" - " " STR(MTC0) " $1, $14 \n" - " eret \n" - "1: .set pop" - : - : - : "memory"); - - local_sb1___flush_cache_all(); -} diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 81f925a..43dde87 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -3,13 +3,14 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994 - 2003, 07 by Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 1994 - 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 2007 MIPS Technologies, Inc. */ #include #include #include #include +#include #include #include #include @@ -157,12 +158,6 @@ void __init cpu_cache_init(void) tx39_cache_init(); return; } - if (cpu_has_sb1_cache) { - extern void __weak sb1_cache_init(void); - - sb1_cache_init(); - return; - } panic(cache_panic); } diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c index adb37d0..82f42ac 100644 --- a/arch/mips/mm/pg-sb1.c +++ b/arch/mips/mm/pg-sb1.c @@ -292,3 +292,11 @@ void copy_page(void *to, void *from) EXPORT_SYMBOL(clear_page); EXPORT_SYMBOL(copy_page); + +void __init build_clear_page(void) +{ +} + +void __init build_copy_page(void) +{ +} diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index d95a83e..81f19ae 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -35,9 +35,6 @@ #ifndef cpu_has_tx39_cache #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) #endif -#ifndef cpu_has_sb1_cache -#define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE) -#endif #ifndef cpu_has_fpu #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index d67f43b..107ccbe 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -255,24 +255,23 @@ #define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ #define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ #define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ -#define MIPS_CPU_SB1_CACHE 0x00000020 /* SB1-style caches */ -#define MIPS_CPU_FPU 0x00000040 /* CPU has FPU */ -#define MIPS_CPU_32FPR 0x00000080 /* 32 dbl. prec. FP registers */ -#define MIPS_CPU_COUNTER 0x00000100 /* Cycle count/compare */ -#define MIPS_CPU_WATCH 0x00000200 /* watchpoint registers */ -#define MIPS_CPU_DIVEC 0x00000400 /* dedicated interrupt vector */ -#define MIPS_CPU_VCE 0x00000800 /* virt. coherence conflict possible */ -#define MIPS_CPU_CACHE_CDEX_P 0x00001000 /* Create_Dirty_Exclusive CACHE op */ -#define MIPS_CPU_CACHE_CDEX_S 0x00002000 /* ... same for seconary cache ... */ -#define MIPS_CPU_MCHECK 0x00004000 /* Machine check exception */ -#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */ -#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */ -#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */ -#define MIPS_CPU_INCLUSIVE_CACHES 0x00040000 /* P-cache subset enforced */ -#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ -#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ -#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ -#define MIPS_CPU_ULRI 0x00400000 /* CPU has ULRI feature */ +#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */ +#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */ +#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */ +#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */ +#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ +#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ +#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */ +#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */ +#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */ +#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */ +#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */ +#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ +#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */ +#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ +#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ +#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ +#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ /* * CPU ASE encodings diff --git a/include/asm-mips/linkage.h b/include/asm-mips/linkage.h index b6185d3c..e9a940d 100644 --- a/include/asm-mips/linkage.h +++ b/include/asm-mips/linkage.h @@ -5,4 +5,6 @@ #include #endif +#define __weak __attribute__((weak)) + #endif diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h index d38f069..b3314cf 100644 --- a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h +++ b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h @@ -14,7 +14,6 @@ #define cpu_has_3k_cache 0 #define cpu_has_4k_cache 1 #define cpu_has_tx39_cache 0 -#define cpu_has_sb1_cache 0 #define cpu_has_fpu 1 #define cpu_has_32fpr 1 #define cpu_has_counter 1 -- cgit v0.10.2 From cc6e8e0812cf95aea397c457ff48de2ac069614f Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:05 +0100 Subject: [MIPS] Remove IP27 specific structures from struct cpuinfo_mips Signed-off-by: Ralf Baechle diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c index 74158d3..af08c41 100644 --- a/arch/mips/sgi-ip27/ip27-init.c +++ b/arch/mips/sgi-ip27/ip27-init.c @@ -47,6 +47,9 @@ cnodeid_t cpuid_to_compact_node[MAXCPUS]; EXPORT_SYMBOL(nasid_to_compact_node); +struct cpuinfo_ip27 sn_cpu_info[NR_CPUS]; +EXPORT_SYMBOL_GPL(sn_cpu_info); + extern void pcibr_setup(cnodeid_t); extern void xtalk_probe_node(cnodeid_t nid); diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c index fbb2772..493777e 100644 --- a/arch/mips/sgi-ip27/ip27-smp.c +++ b/arch/mips/sgi-ip27/ip27-smp.c @@ -33,7 +33,7 @@ static void alloc_cpupda(cpuid_t cpu, int cpunum) nasid_t nasid = COMPACT_TO_NASID_NODEID(node); cputonasid(cpunum) = nasid; - cpu_data[cpunum].p_nodeid = node; + sn_cpu_info[cpunum].p_nodeid = node; cputoslice(cpunum) = get_cpu_slice(cpu); } diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h index 22fe845..0468959 100644 --- a/include/asm-mips/cpu-info.h +++ b/include/asm-mips/cpu-info.h @@ -14,10 +14,6 @@ #include -#ifdef CONFIG_SGI_IP27 -#include -#endif - /* * Descriptor for a cache */ @@ -43,20 +39,6 @@ struct cache_desc { struct cpuinfo_mips { unsigned long udelay_val; unsigned long asid_cache; -#if defined(CONFIG_SGI_IP27) -// cpuid_t p_cpuid; /* PROM assigned cpuid */ - cnodeid_t p_nodeid; /* my node ID in compact-id-space */ - nasid_t p_nasid; /* my node ID in numa-as-id-space */ - unsigned char p_slice; /* Physical position on node board */ -#endif -#if 0 - unsigned long loops_per_sec; - unsigned long ipi_count; - unsigned long irq_attempt[NR_IRQS]; - unsigned long smp_local_irq_count; - unsigned long prof_multiplier; - unsigned long prof_counter; -#endif /* * Capability and feature descriptor structure for MIPS CPU diff --git a/include/asm-mips/mach-ip27/topology.h b/include/asm-mips/mach-ip27/topology.h index 61d9be3..372291f 100644 --- a/include/asm-mips/mach-ip27/topology.h +++ b/include/asm-mips/mach-ip27/topology.h @@ -2,9 +2,27 @@ #define _ASM_MACH_TOPOLOGY_H 1 #include +#include #include -#define cpu_to_node(cpu) (cpu_data[(cpu)].p_nodeid) +struct cpuinfo_ip27 { +// cpuid_t p_cpuid; /* PROM assigned cpuid */ + cnodeid_t p_nodeid; /* my node ID in compact-id-space */ + nasid_t p_nasid; /* my node ID in numa-as-id-space */ + unsigned char p_slice; /* Physical position on node board */ +#if 0 + unsigned long loops_per_sec; + unsigned long ipi_count; + unsigned long irq_attempt[NR_IRQS]; + unsigned long smp_local_irq_count; + unsigned long prof_multiplier; + unsigned long prof_counter; +#endif +}; + +extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS]; + +#define cpu_to_node(cpu) (sn_cpu_info[(cpu)].p_nodeid) #define parent_node(node) (node) #define node_to_cpumask(node) (hub_data(node)->h_cpus) #define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node))) diff --git a/include/asm-mips/sn/arch.h b/include/asm-mips/sn/arch.h index da523de..bd75945 100644 --- a/include/asm-mips/sn/arch.h +++ b/include/asm-mips/sn/arch.h @@ -19,8 +19,8 @@ typedef u64 hubreg_t; -#define cputonasid(cpu) (cpu_data[(cpu)].p_nasid) -#define cputoslice(cpu) (cpu_data[(cpu)].p_slice) +#define cputonasid(cpu) (sn_cpu_info[(cpu)].p_nasid) +#define cputoslice(cpu) (sn_cpu_info[(cpu)].p_slice) #define makespnum(_nasid, _slice) \ (((_nasid) << CPUS_PER_NODE_SHFT) | (_slice)) -- cgit v0.10.2 From df78b5c8faa72b3c04f82faab126de93af178348 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Wed, 5 Sep 2007 08:58:26 +0200 Subject: [MIPS] Move CFE code into arch/mips/fw/cfe Move the platform independent part of the CFE code to arch/mips/fw/cfe from arch/mips/sibyte/cfe. Signed-off-by: Aurelien Jarno Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 90b409d..4863494 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -688,6 +688,9 @@ config ARCH_MAY_HAVE_PC_FDC config BOOT_RAW bool +config CFE + bool + config DMA_COHERENT bool diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 7b936ed..a097ae6 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -149,6 +149,7 @@ endif # Firmware support # libs-$(CONFIG_ARC) += arch/mips/arc/ +libs-$(CONFIG_CFE) += arch/mips/fw/cfe/ libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/ # diff --git a/arch/mips/fw/cfe/Makefile b/arch/mips/fw/cfe/Makefile new file mode 100644 index 0000000..8f20044 --- /dev/null +++ b/arch/mips/fw/cfe/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the Broadcom Common Firmware Environment support +# + +lib-y += cfe_api.o diff --git a/arch/mips/fw/cfe/cfe_api.c b/arch/mips/fw/cfe/cfe_api.c new file mode 100644 index 0000000..a9f69e4 --- /dev/null +++ b/arch/mips/fw/cfe/cfe_api.c @@ -0,0 +1,502 @@ +/* + * Copyright (C) 2000, 2001, 2002 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* ********************************************************************* + * + * Broadcom Common Firmware Environment (CFE) + * + * Device Function stubs File: cfe_api.c + * + * This module contains device function stubs (small routines to + * call the standard "iocb" interface entry point to CFE). + * There should be one routine here per iocb function call. + * + * Authors: Mitch Lichtenberg, Chris Demetriou + * + ********************************************************************* */ + +#include +#include "cfe_api_int.h" + +/* Cast from a native pointer to a cfe_xptr_t and back. */ +#define XPTR_FROM_NATIVE(n) ((cfe_xptr_t) (intptr_t) (n)) +#define NATIVE_FROM_XPTR(x) ((void *) (intptr_t) (x)) + +#ifdef CFE_API_IMPL_NAMESPACE +#define cfe_iocb_dispatch(a) __cfe_iocb_dispatch(a) +#endif +int cfe_iocb_dispatch(cfe_xiocb_t * xiocb); + +#if defined(CFE_API_common) || defined(CFE_API_ALL) +/* + * Declare the dispatch function with args of "intptr_t". + * This makes sure whatever model we're compiling in + * puts the pointers in a single register. For example, + * combining -mlong64 and -mips1 or -mips2 would lead to + * trouble, since the handle and IOCB pointer will be + * passed in two registers each, and CFE expects one. + */ + +static int (*cfe_dispfunc) (intptr_t handle, intptr_t xiocb) = 0; +static cfe_xuint_t cfe_handle = 0; + +int cfe_init(cfe_xuint_t handle, cfe_xuint_t ept) +{ + cfe_dispfunc = NATIVE_FROM_XPTR(ept); + cfe_handle = handle; + return 0; +} + +int cfe_iocb_dispatch(cfe_xiocb_t * xiocb) +{ + if (!cfe_dispfunc) + return -1; + return (*cfe_dispfunc) ((intptr_t) cfe_handle, (intptr_t) xiocb); +} +#endif /* CFE_API_common || CFE_API_ALL */ + +#if defined(CFE_API_close) || defined(CFE_API_ALL) +int cfe_close(int handle) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_DEV_CLOSE; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = handle; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = 0; + + cfe_iocb_dispatch(&xiocb); + + return xiocb.xiocb_status; + +} +#endif /* CFE_API_close || CFE_API_ALL */ + +#if defined(CFE_API_cpu_start) || defined(CFE_API_ALL) +int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t); + xiocb.plist.xiocb_cpuctl.cpu_number = cpu; + xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_START; + xiocb.plist.xiocb_cpuctl.gp_val = gp; + xiocb.plist.xiocb_cpuctl.sp_val = sp; + xiocb.plist.xiocb_cpuctl.a1_val = a1; + xiocb.plist.xiocb_cpuctl.start_addr = (long) fn; + + cfe_iocb_dispatch(&xiocb); + + return xiocb.xiocb_status; +} +#endif /* CFE_API_cpu_start || CFE_API_ALL */ + +#if defined(CFE_API_cpu_stop) || defined(CFE_API_ALL) +int cfe_cpu_stop(int cpu) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t); + xiocb.plist.xiocb_cpuctl.cpu_number = cpu; + xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_STOP; + + cfe_iocb_dispatch(&xiocb); + + return xiocb.xiocb_status; +} +#endif /* CFE_API_cpu_stop || CFE_API_ALL */ + +#if defined(CFE_API_enumenv) || defined(CFE_API_ALL) +int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_ENV_SET; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); + xiocb.plist.xiocb_envbuf.enum_idx = idx; + xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); + xiocb.plist.xiocb_envbuf.name_length = namelen; + xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val); + xiocb.plist.xiocb_envbuf.val_length = vallen; + + cfe_iocb_dispatch(&xiocb); + + return xiocb.xiocb_status; +} +#endif /* CFE_API_enumenv || CFE_API_ALL */ + +#if defined(CFE_API_enummem) || defined(CFE_API_ALL) +int +cfe_enummem(int idx, int flags, cfe_xuint_t * start, cfe_xuint_t * length, + cfe_xuint_t * type) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_FW_MEMENUM; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = flags; + xiocb.xiocb_psize = sizeof(xiocb_meminfo_t); + xiocb.plist.xiocb_meminfo.mi_idx = idx; + + cfe_iocb_dispatch(&xiocb); + + if (xiocb.xiocb_status < 0) + return xiocb.xiocb_status; + + *start = xiocb.plist.xiocb_meminfo.mi_addr; + *length = xiocb.plist.xiocb_meminfo.mi_size; + *type = xiocb.plist.xiocb_meminfo.mi_type; + + return 0; +} +#endif /* CFE_API_enummem || CFE_API_ALL */ + +#if defined(CFE_API_exit) || defined(CFE_API_ALL) +int cfe_exit(int warm, int status) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_FW_RESTART; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = warm ? CFE_FLG_WARMSTART : 0; + xiocb.xiocb_psize = sizeof(xiocb_exitstat_t); + xiocb.plist.xiocb_exitstat.status = status; + + cfe_iocb_dispatch(&xiocb); + + return xiocb.xiocb_status; +} +#endif /* CFE_API_exit || CFE_API_ALL */ + +#if defined(CFE_API_flushcache) || defined(CFE_API_ALL) +int cfe_flushcache(int flg) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_FW_FLUSHCACHE; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = flg; + xiocb.xiocb_psize = 0; + + cfe_iocb_dispatch(&xiocb); + + return xiocb.xiocb_status; +} +#endif /* CFE_API_flushcache || CFE_API_ALL */ + +#if defined(CFE_API_getdevinfo) || defined(CFE_API_ALL) +int cfe_getdevinfo(char *name) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_DEV_GETINFO; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_buffer_t); + xiocb.plist.xiocb_buffer.buf_offset = 0; + xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name); + xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name); + + cfe_iocb_dispatch(&xiocb); + + if (xiocb.xiocb_status < 0) + return xiocb.xiocb_status; + return xiocb.plist.xiocb_buffer.buf_devflags; +} +#endif /* CFE_API_getdevinfo || CFE_API_ALL */ + +#if defined(CFE_API_getenv) || defined(CFE_API_ALL) +int cfe_getenv(char *name, char *dest, int destlen) +{ + cfe_xiocb_t xiocb; + + *dest = 0; + + xiocb.xiocb_fcode = CFE_CMD_ENV_GET; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); + xiocb.plist.xiocb_envbuf.enum_idx = 0; + xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); + xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name); + xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(dest); + xiocb.plist.xiocb_envbuf.val_length = destlen; + + cfe_iocb_dispatch(&xiocb); + + return xiocb.xiocb_status; +} +#endif /* CFE_API_getenv || CFE_API_ALL */ + +#if defined(CFE_API_getfwinfo) || defined(CFE_API_ALL) +int cfe_getfwinfo(cfe_fwinfo_t * info) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_FW_GETINFO; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_fwinfo_t); + + cfe_iocb_dispatch(&xiocb); + + if (xiocb.xiocb_status < 0) + return xiocb.xiocb_status; + + info->fwi_version = xiocb.plist.xiocb_fwinfo.fwi_version; + info->fwi_totalmem = xiocb.plist.xiocb_fwinfo.fwi_totalmem; + info->fwi_flags = xiocb.plist.xiocb_fwinfo.fwi_flags; + info->fwi_boardid = xiocb.plist.xiocb_fwinfo.fwi_boardid; + info->fwi_bootarea_va = xiocb.plist.xiocb_fwinfo.fwi_bootarea_va; + info->fwi_bootarea_pa = xiocb.plist.xiocb_fwinfo.fwi_bootarea_pa; + info->fwi_bootarea_size = + xiocb.plist.xiocb_fwinfo.fwi_bootarea_size; +#if 0 + info->fwi_reserved1 = xiocb.plist.xiocb_fwinfo.fwi_reserved1; + info->fwi_reserved2 = xiocb.plist.xiocb_fwinfo.fwi_reserved2; + info->fwi_reserved3 = xiocb.plist.xiocb_fwinfo.fwi_reserved3; +#endif + + return 0; +} +#endif /* CFE_API_getfwinfo || CFE_API_ALL */ + +#if defined(CFE_API_getstdhandle) || defined(CFE_API_ALL) +int cfe_getstdhandle(int flg) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_DEV_GETHANDLE; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = flg; + xiocb.xiocb_psize = 0; + + cfe_iocb_dispatch(&xiocb); + + if (xiocb.xiocb_status < 0) + return xiocb.xiocb_status; + return xiocb.xiocb_handle; +} +#endif /* CFE_API_getstdhandle || CFE_API_ALL */ + +#if defined(CFE_API_getticks) || defined(CFE_API_ALL) +int64_t +#ifdef CFE_API_IMPL_NAMESPACE +__cfe_getticks(void) +#else +cfe_getticks(void) +#endif +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_FW_GETTIME; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_time_t); + xiocb.plist.xiocb_time.ticks = 0; + + cfe_iocb_dispatch(&xiocb); + + return xiocb.plist.xiocb_time.ticks; + +} +#endif /* CFE_API_getticks || CFE_API_ALL */ + +#if defined(CFE_API_inpstat) || defined(CFE_API_ALL) +int cfe_inpstat(int handle) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_DEV_INPSTAT; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = handle; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_inpstat_t); + xiocb.plist.xiocb_inpstat.inp_status = 0; + + cfe_iocb_dispatch(&xiocb); + + if (xiocb.xiocb_status < 0) + return xiocb.xiocb_status; + return xiocb.plist.xiocb_inpstat.inp_status; +} +#endif /* CFE_API_inpstat || CFE_API_ALL */ + +#if defined(CFE_API_ioctl) || defined(CFE_API_ALL) +int +cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer, + int length, int *retlen, cfe_xuint_t offset) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_DEV_IOCTL; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = handle; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_buffer_t); + xiocb.plist.xiocb_buffer.buf_offset = offset; + xiocb.plist.xiocb_buffer.buf_ioctlcmd = ioctlnum; + xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); + xiocb.plist.xiocb_buffer.buf_length = length; + + cfe_iocb_dispatch(&xiocb); + + if (retlen) + *retlen = xiocb.plist.xiocb_buffer.buf_retlen; + return xiocb.xiocb_status; +} +#endif /* CFE_API_ioctl || CFE_API_ALL */ + +#if defined(CFE_API_open) || defined(CFE_API_ALL) +int cfe_open(char *name) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_DEV_OPEN; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_buffer_t); + xiocb.plist.xiocb_buffer.buf_offset = 0; + xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name); + xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name); + + cfe_iocb_dispatch(&xiocb); + + if (xiocb.xiocb_status < 0) + return xiocb.xiocb_status; + return xiocb.xiocb_handle; +} +#endif /* CFE_API_open || CFE_API_ALL */ + +#if defined(CFE_API_read) || defined(CFE_API_ALL) +int cfe_read(int handle, unsigned char *buffer, int length) +{ + return cfe_readblk(handle, 0, buffer, length); +} +#endif /* CFE_API_read || CFE_API_ALL */ + +#if defined(CFE_API_readblk) || defined(CFE_API_ALL) +int +cfe_readblk(int handle, cfe_xint_t offset, unsigned char *buffer, + int length) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_DEV_READ; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = handle; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_buffer_t); + xiocb.plist.xiocb_buffer.buf_offset = offset; + xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); + xiocb.plist.xiocb_buffer.buf_length = length; + + cfe_iocb_dispatch(&xiocb); + + if (xiocb.xiocb_status < 0) + return xiocb.xiocb_status; + return xiocb.plist.xiocb_buffer.buf_retlen; +} +#endif /* CFE_API_readblk || CFE_API_ALL */ + +#if defined(CFE_API_setenv) || defined(CFE_API_ALL) +int cfe_setenv(char *name, char *val) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_ENV_SET; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); + xiocb.plist.xiocb_envbuf.enum_idx = 0; + xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); + xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name); + xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val); + xiocb.plist.xiocb_envbuf.val_length = cfe_strlen(val); + + cfe_iocb_dispatch(&xiocb); + + return xiocb.xiocb_status; +} +#endif /* CFE_API_setenv || CFE_API_ALL */ + +#if (defined(CFE_API_strlen) || defined(CFE_API_ALL)) \ + && !defined(CFE_API_STRLEN_CUSTOM) +int cfe_strlen(char *name) +{ + int count = 0; + + while (*name++) + count++; + + return count; +} +#endif /* CFE_API_strlen || CFE_API_ALL */ + +#if defined(CFE_API_write) || defined(CFE_API_ALL) +int cfe_write(int handle, unsigned char *buffer, int length) +{ + return cfe_writeblk(handle, 0, buffer, length); +} +#endif /* CFE_API_write || CFE_API_ALL */ + +#if defined(CFE_API_writeblk) || defined(CFE_API_ALL) +int +cfe_writeblk(int handle, cfe_xint_t offset, unsigned char *buffer, + int length) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_DEV_WRITE; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = handle; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_buffer_t); + xiocb.plist.xiocb_buffer.buf_offset = offset; + xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); + xiocb.plist.xiocb_buffer.buf_length = length; + + cfe_iocb_dispatch(&xiocb); + + if (xiocb.xiocb_status < 0) + return xiocb.xiocb_status; + return xiocb.plist.xiocb_buffer.buf_retlen; +} +#endif /* CFE_API_writeblk || CFE_API_ALL */ diff --git a/arch/mips/fw/cfe/cfe_api_int.h b/arch/mips/fw/cfe/cfe_api_int.h new file mode 100644 index 0000000..f7e5a64 --- /dev/null +++ b/arch/mips/fw/cfe/cfe_api_int.h @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2000, 2001, 2002 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* ********************************************************************* + * + * Broadcom Common Firmware Environment (CFE) + * + * Device function prototypes File: cfe_api_int.h + * + * This header defines all internal types and macros for the + * library. This is stuff that's not exported to an app + * using the library. + * + * Authors: Mitch Lichtenberg, Chris Demetriou + * + ********************************************************************* */ + +#ifndef CFE_API_INT_H +#define CFE_API_INT_H + +/* ********************************************************************* + * Constants + ********************************************************************* */ + +#define CFE_CMD_FW_GETINFO 0 +#define CFE_CMD_FW_RESTART 1 +#define CFE_CMD_FW_BOOT 2 +#define CFE_CMD_FW_CPUCTL 3 +#define CFE_CMD_FW_GETTIME 4 +#define CFE_CMD_FW_MEMENUM 5 +#define CFE_CMD_FW_FLUSHCACHE 6 + +#define CFE_CMD_DEV_GETHANDLE 9 +#define CFE_CMD_DEV_ENUM 10 +#define CFE_CMD_DEV_OPEN 11 +#define CFE_CMD_DEV_INPSTAT 12 +#define CFE_CMD_DEV_READ 13 +#define CFE_CMD_DEV_WRITE 14 +#define CFE_CMD_DEV_IOCTL 15 +#define CFE_CMD_DEV_CLOSE 16 +#define CFE_CMD_DEV_GETINFO 17 + +#define CFE_CMD_ENV_ENUM 20 +#define CFE_CMD_ENV_GET 22 +#define CFE_CMD_ENV_SET 23 +#define CFE_CMD_ENV_DEL 24 + +#define CFE_CMD_MAX 32 + +#define CFE_CMD_VENDOR_USE 0x8000 /* codes above this are for customer use */ + +/* ********************************************************************* + * Structures + ********************************************************************* */ + +typedef uint64_t cfe_xuint_t; +typedef int64_t cfe_xint_t; +typedef int64_t cfe_xptr_t; + +typedef struct xiocb_buffer_s { + cfe_xuint_t buf_offset; /* offset on device (bytes) */ + cfe_xptr_t buf_ptr; /* pointer to a buffer */ + cfe_xuint_t buf_length; /* length of this buffer */ + cfe_xuint_t buf_retlen; /* returned length (for read ops) */ + cfe_xuint_t buf_ioctlcmd; /* IOCTL command (used only for IOCTLs) */ +} xiocb_buffer_t; + +#define buf_devflags buf_ioctlcmd /* returned device info flags */ + +typedef struct xiocb_inpstat_s { + cfe_xuint_t inp_status; /* 1 means input available */ +} xiocb_inpstat_t; + +typedef struct xiocb_envbuf_s { + cfe_xint_t enum_idx; /* 0-based enumeration index */ + cfe_xptr_t name_ptr; /* name string buffer */ + cfe_xint_t name_length; /* size of name buffer */ + cfe_xptr_t val_ptr; /* value string buffer */ + cfe_xint_t val_length; /* size of value string buffer */ +} xiocb_envbuf_t; + +typedef struct xiocb_cpuctl_s { + cfe_xuint_t cpu_number; /* cpu number to control */ + cfe_xuint_t cpu_command; /* command to issue to CPU */ + cfe_xuint_t start_addr; /* CPU start address */ + cfe_xuint_t gp_val; /* starting GP value */ + cfe_xuint_t sp_val; /* starting SP value */ + cfe_xuint_t a1_val; /* starting A1 value */ +} xiocb_cpuctl_t; + +typedef struct xiocb_time_s { + cfe_xint_t ticks; /* current time in ticks */ +} xiocb_time_t; + +typedef struct xiocb_exitstat_s { + cfe_xint_t status; +} xiocb_exitstat_t; + +typedef struct xiocb_meminfo_s { + cfe_xint_t mi_idx; /* 0-based enumeration index */ + cfe_xint_t mi_type; /* type of memory block */ + cfe_xuint_t mi_addr; /* physical start address */ + cfe_xuint_t mi_size; /* block size */ +} xiocb_meminfo_t; + +typedef struct xiocb_fwinfo_s { + cfe_xint_t fwi_version; /* major, minor, eco version */ + cfe_xint_t fwi_totalmem; /* total installed mem */ + cfe_xint_t fwi_flags; /* various flags */ + cfe_xint_t fwi_boardid; /* board ID */ + cfe_xint_t fwi_bootarea_va; /* VA of boot area */ + cfe_xint_t fwi_bootarea_pa; /* PA of boot area */ + cfe_xint_t fwi_bootarea_size; /* size of boot area */ + cfe_xint_t fwi_reserved1; + cfe_xint_t fwi_reserved2; + cfe_xint_t fwi_reserved3; +} xiocb_fwinfo_t; + +typedef struct cfe_xiocb_s { + cfe_xuint_t xiocb_fcode; /* IOCB function code */ + cfe_xint_t xiocb_status; /* return status */ + cfe_xint_t xiocb_handle; /* file/device handle */ + cfe_xuint_t xiocb_flags; /* flags for this IOCB */ + cfe_xuint_t xiocb_psize; /* size of parameter list */ + union { + xiocb_buffer_t xiocb_buffer; /* buffer parameters */ + xiocb_inpstat_t xiocb_inpstat; /* input status parameters */ + xiocb_envbuf_t xiocb_envbuf; /* environment function parameters */ + xiocb_cpuctl_t xiocb_cpuctl; /* CPU control parameters */ + xiocb_time_t xiocb_time; /* timer parameters */ + xiocb_meminfo_t xiocb_meminfo; /* memory arena info parameters */ + xiocb_fwinfo_t xiocb_fwinfo; /* firmware information */ + xiocb_exitstat_t xiocb_exitstat; /* Exit Status */ + } plist; +} cfe_xiocb_t; + +#endif /* CFE_API_INT_H */ diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig index fdd7bd9..841b301 100644 --- a/arch/mips/sibyte/Kconfig +++ b/arch/mips/sibyte/Kconfig @@ -124,6 +124,7 @@ config SB1_CERR_STALL config SIBYTE_CFE bool "Booting from CFE" depends on SIBYTE_SB1xxx_SOC + select CFE select SYS_HAS_EARLY_PRINTK help Make use of the CFE API for enumerating available memory, diff --git a/arch/mips/sibyte/cfe/Makefile b/arch/mips/sibyte/cfe/Makefile index 059d84a..a121493 100644 --- a/arch/mips/sibyte/cfe/Makefile +++ b/arch/mips/sibyte/cfe/Makefile @@ -1,3 +1,3 @@ -lib-y = cfe_api.o setup.o +lib-y = setup.o lib-$(CONFIG_SMP) += smp.o lib-$(CONFIG_SIBYTE_CFE_CONSOLE) += console.o diff --git a/arch/mips/sibyte/cfe/cfe_api.c b/arch/mips/sibyte/cfe/cfe_api.c deleted file mode 100644 index c021360..0000000 --- a/arch/mips/sibyte/cfe/cfe_api.c +++ /dev/null @@ -1,502 +0,0 @@ -/* - * Copyright (C) 2000, 2001, 2002 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -/* ********************************************************************* - * - * Broadcom Common Firmware Environment (CFE) - * - * Device Function stubs File: cfe_api.c - * - * This module contains device function stubs (small routines to - * call the standard "iocb" interface entry point to CFE). - * There should be one routine here per iocb function call. - * - * Authors: Mitch Lichtenberg, Chris Demetriou - * - ********************************************************************* */ - -#include "cfe_api.h" -#include "cfe_api_int.h" - -/* Cast from a native pointer to a cfe_xptr_t and back. */ -#define XPTR_FROM_NATIVE(n) ((cfe_xptr_t) (intptr_t) (n)) -#define NATIVE_FROM_XPTR(x) ((void *) (intptr_t) (x)) - -#ifdef CFE_API_IMPL_NAMESPACE -#define cfe_iocb_dispatch(a) __cfe_iocb_dispatch(a) -#endif -int cfe_iocb_dispatch(cfe_xiocb_t * xiocb); - -#if defined(CFE_API_common) || defined(CFE_API_ALL) -/* - * Declare the dispatch function with args of "intptr_t". - * This makes sure whatever model we're compiling in - * puts the pointers in a single register. For example, - * combining -mlong64 and -mips1 or -mips2 would lead to - * trouble, since the handle and IOCB pointer will be - * passed in two registers each, and CFE expects one. - */ - -static int (*cfe_dispfunc) (intptr_t handle, intptr_t xiocb) = 0; -static cfe_xuint_t cfe_handle = 0; - -int cfe_init(cfe_xuint_t handle, cfe_xuint_t ept) -{ - cfe_dispfunc = NATIVE_FROM_XPTR(ept); - cfe_handle = handle; - return 0; -} - -int cfe_iocb_dispatch(cfe_xiocb_t * xiocb) -{ - if (!cfe_dispfunc) - return -1; - return (*cfe_dispfunc) ((intptr_t) cfe_handle, (intptr_t) xiocb); -} -#endif /* CFE_API_common || CFE_API_ALL */ - -#if defined(CFE_API_close) || defined(CFE_API_ALL) -int cfe_close(int handle) -{ - cfe_xiocb_t xiocb; - - xiocb.xiocb_fcode = CFE_CMD_DEV_CLOSE; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = handle; - xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = 0; - - cfe_iocb_dispatch(&xiocb); - - return xiocb.xiocb_status; - -} -#endif /* CFE_API_close || CFE_API_ALL */ - -#if defined(CFE_API_cpu_start) || defined(CFE_API_ALL) -int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1) -{ - cfe_xiocb_t xiocb; - - xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = 0; - xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t); - xiocb.plist.xiocb_cpuctl.cpu_number = cpu; - xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_START; - xiocb.plist.xiocb_cpuctl.gp_val = gp; - xiocb.plist.xiocb_cpuctl.sp_val = sp; - xiocb.plist.xiocb_cpuctl.a1_val = a1; - xiocb.plist.xiocb_cpuctl.start_addr = (long) fn; - - cfe_iocb_dispatch(&xiocb); - - return xiocb.xiocb_status; -} -#endif /* CFE_API_cpu_start || CFE_API_ALL */ - -#if defined(CFE_API_cpu_stop) || defined(CFE_API_ALL) -int cfe_cpu_stop(int cpu) -{ - cfe_xiocb_t xiocb; - - xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = 0; - xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t); - xiocb.plist.xiocb_cpuctl.cpu_number = cpu; - xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_STOP; - - cfe_iocb_dispatch(&xiocb); - - return xiocb.xiocb_status; -} -#endif /* CFE_API_cpu_stop || CFE_API_ALL */ - -#if defined(CFE_API_enumenv) || defined(CFE_API_ALL) -int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen) -{ - cfe_xiocb_t xiocb; - - xiocb.xiocb_fcode = CFE_CMD_ENV_SET; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = 0; - xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); - xiocb.plist.xiocb_envbuf.enum_idx = idx; - xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); - xiocb.plist.xiocb_envbuf.name_length = namelen; - xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val); - xiocb.plist.xiocb_envbuf.val_length = vallen; - - cfe_iocb_dispatch(&xiocb); - - return xiocb.xiocb_status; -} -#endif /* CFE_API_enumenv || CFE_API_ALL */ - -#if defined(CFE_API_enummem) || defined(CFE_API_ALL) -int -cfe_enummem(int idx, int flags, cfe_xuint_t * start, cfe_xuint_t * length, - cfe_xuint_t * type) -{ - cfe_xiocb_t xiocb; - - xiocb.xiocb_fcode = CFE_CMD_FW_MEMENUM; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = 0; - xiocb.xiocb_flags = flags; - xiocb.xiocb_psize = sizeof(xiocb_meminfo_t); - xiocb.plist.xiocb_meminfo.mi_idx = idx; - - cfe_iocb_dispatch(&xiocb); - - if (xiocb.xiocb_status < 0) - return xiocb.xiocb_status; - - *start = xiocb.plist.xiocb_meminfo.mi_addr; - *length = xiocb.plist.xiocb_meminfo.mi_size; - *type = xiocb.plist.xiocb_meminfo.mi_type; - - return 0; -} -#endif /* CFE_API_enummem || CFE_API_ALL */ - -#if defined(CFE_API_exit) || defined(CFE_API_ALL) -int cfe_exit(int warm, int status) -{ - cfe_xiocb_t xiocb; - - xiocb.xiocb_fcode = CFE_CMD_FW_RESTART; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = 0; - xiocb.xiocb_flags = warm ? CFE_FLG_WARMSTART : 0; - xiocb.xiocb_psize = sizeof(xiocb_exitstat_t); - xiocb.plist.xiocb_exitstat.status = status; - - cfe_iocb_dispatch(&xiocb); - - return xiocb.xiocb_status; -} -#endif /* CFE_API_exit || CFE_API_ALL */ - -#if defined(CFE_API_flushcache) || defined(CFE_API_ALL) -int cfe_flushcache(int flg) -{ - cfe_xiocb_t xiocb; - - xiocb.xiocb_fcode = CFE_CMD_FW_FLUSHCACHE; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = 0; - xiocb.xiocb_flags = flg; - xiocb.xiocb_psize = 0; - - cfe_iocb_dispatch(&xiocb); - - return xiocb.xiocb_status; -} -#endif /* CFE_API_flushcache || CFE_API_ALL */ - -#if defined(CFE_API_getdevinfo) || defined(CFE_API_ALL) -int cfe_getdevinfo(char *name) -{ - cfe_xiocb_t xiocb; - - xiocb.xiocb_fcode = CFE_CMD_DEV_GETINFO; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = 0; - xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_buffer_t); - xiocb.plist.xiocb_buffer.buf_offset = 0; - xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name); - xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name); - - cfe_iocb_dispatch(&xiocb); - - if (xiocb.xiocb_status < 0) - return xiocb.xiocb_status; - return xiocb.plist.xiocb_buffer.buf_devflags; -} -#endif /* CFE_API_getdevinfo || CFE_API_ALL */ - -#if defined(CFE_API_getenv) || defined(CFE_API_ALL) -int cfe_getenv(char *name, char *dest, int destlen) -{ - cfe_xiocb_t xiocb; - - *dest = 0; - - xiocb.xiocb_fcode = CFE_CMD_ENV_GET; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = 0; - xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); - xiocb.plist.xiocb_envbuf.enum_idx = 0; - xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); - xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name); - xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(dest); - xiocb.plist.xiocb_envbuf.val_length = destlen; - - cfe_iocb_dispatch(&xiocb); - - return xiocb.xiocb_status; -} -#endif /* CFE_API_getenv || CFE_API_ALL */ - -#if defined(CFE_API_getfwinfo) || defined(CFE_API_ALL) -int cfe_getfwinfo(cfe_fwinfo_t * info) -{ - cfe_xiocb_t xiocb; - - xiocb.xiocb_fcode = CFE_CMD_FW_GETINFO; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = 0; - xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_fwinfo_t); - - cfe_iocb_dispatch(&xiocb); - - if (xiocb.xiocb_status < 0) - return xiocb.xiocb_status; - - info->fwi_version = xiocb.plist.xiocb_fwinfo.fwi_version; - info->fwi_totalmem = xiocb.plist.xiocb_fwinfo.fwi_totalmem; - info->fwi_flags = xiocb.plist.xiocb_fwinfo.fwi_flags; - info->fwi_boardid = xiocb.plist.xiocb_fwinfo.fwi_boardid; - info->fwi_bootarea_va = xiocb.plist.xiocb_fwinfo.fwi_bootarea_va; - info->fwi_bootarea_pa = xiocb.plist.xiocb_fwinfo.fwi_bootarea_pa; - info->fwi_bootarea_size = - xiocb.plist.xiocb_fwinfo.fwi_bootarea_size; -#if 0 - info->fwi_reserved1 = xiocb.plist.xiocb_fwinfo.fwi_reserved1; - info->fwi_reserved2 = xiocb.plist.xiocb_fwinfo.fwi_reserved2; - info->fwi_reserved3 = xiocb.plist.xiocb_fwinfo.fwi_reserved3; -#endif - - return 0; -} -#endif /* CFE_API_getfwinfo || CFE_API_ALL */ - -#if defined(CFE_API_getstdhandle) || defined(CFE_API_ALL) -int cfe_getstdhandle(int flg) -{ - cfe_xiocb_t xiocb; - - xiocb.xiocb_fcode = CFE_CMD_DEV_GETHANDLE; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = 0; - xiocb.xiocb_flags = flg; - xiocb.xiocb_psize = 0; - - cfe_iocb_dispatch(&xiocb); - - if (xiocb.xiocb_status < 0) - return xiocb.xiocb_status; - return xiocb.xiocb_handle; -} -#endif /* CFE_API_getstdhandle || CFE_API_ALL */ - -#if defined(CFE_API_getticks) || defined(CFE_API_ALL) -int64_t -#ifdef CFE_API_IMPL_NAMESPACE -__cfe_getticks(void) -#else -cfe_getticks(void) -#endif -{ - cfe_xiocb_t xiocb; - - xiocb.xiocb_fcode = CFE_CMD_FW_GETTIME; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = 0; - xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_time_t); - xiocb.plist.xiocb_time.ticks = 0; - - cfe_iocb_dispatch(&xiocb); - - return xiocb.plist.xiocb_time.ticks; - -} -#endif /* CFE_API_getticks || CFE_API_ALL */ - -#if defined(CFE_API_inpstat) || defined(CFE_API_ALL) -int cfe_inpstat(int handle) -{ - cfe_xiocb_t xiocb; - - xiocb.xiocb_fcode = CFE_CMD_DEV_INPSTAT; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = handle; - xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_inpstat_t); - xiocb.plist.xiocb_inpstat.inp_status = 0; - - cfe_iocb_dispatch(&xiocb); - - if (xiocb.xiocb_status < 0) - return xiocb.xiocb_status; - return xiocb.plist.xiocb_inpstat.inp_status; -} -#endif /* CFE_API_inpstat || CFE_API_ALL */ - -#if defined(CFE_API_ioctl) || defined(CFE_API_ALL) -int -cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer, - int length, int *retlen, cfe_xuint_t offset) -{ - cfe_xiocb_t xiocb; - - xiocb.xiocb_fcode = CFE_CMD_DEV_IOCTL; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = handle; - xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_buffer_t); - xiocb.plist.xiocb_buffer.buf_offset = offset; - xiocb.plist.xiocb_buffer.buf_ioctlcmd = ioctlnum; - xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); - xiocb.plist.xiocb_buffer.buf_length = length; - - cfe_iocb_dispatch(&xiocb); - - if (retlen) - *retlen = xiocb.plist.xiocb_buffer.buf_retlen; - return xiocb.xiocb_status; -} -#endif /* CFE_API_ioctl || CFE_API_ALL */ - -#if defined(CFE_API_open) || defined(CFE_API_ALL) -int cfe_open(char *name) -{ - cfe_xiocb_t xiocb; - - xiocb.xiocb_fcode = CFE_CMD_DEV_OPEN; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = 0; - xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_buffer_t); - xiocb.plist.xiocb_buffer.buf_offset = 0; - xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name); - xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name); - - cfe_iocb_dispatch(&xiocb); - - if (xiocb.xiocb_status < 0) - return xiocb.xiocb_status; - return xiocb.xiocb_handle; -} -#endif /* CFE_API_open || CFE_API_ALL */ - -#if defined(CFE_API_read) || defined(CFE_API_ALL) -int cfe_read(int handle, unsigned char *buffer, int length) -{ - return cfe_readblk(handle, 0, buffer, length); -} -#endif /* CFE_API_read || CFE_API_ALL */ - -#if defined(CFE_API_readblk) || defined(CFE_API_ALL) -int -cfe_readblk(int handle, cfe_xint_t offset, unsigned char *buffer, - int length) -{ - cfe_xiocb_t xiocb; - - xiocb.xiocb_fcode = CFE_CMD_DEV_READ; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = handle; - xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_buffer_t); - xiocb.plist.xiocb_buffer.buf_offset = offset; - xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); - xiocb.plist.xiocb_buffer.buf_length = length; - - cfe_iocb_dispatch(&xiocb); - - if (xiocb.xiocb_status < 0) - return xiocb.xiocb_status; - return xiocb.plist.xiocb_buffer.buf_retlen; -} -#endif /* CFE_API_readblk || CFE_API_ALL */ - -#if defined(CFE_API_setenv) || defined(CFE_API_ALL) -int cfe_setenv(char *name, char *val) -{ - cfe_xiocb_t xiocb; - - xiocb.xiocb_fcode = CFE_CMD_ENV_SET; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = 0; - xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); - xiocb.plist.xiocb_envbuf.enum_idx = 0; - xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); - xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name); - xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val); - xiocb.plist.xiocb_envbuf.val_length = cfe_strlen(val); - - cfe_iocb_dispatch(&xiocb); - - return xiocb.xiocb_status; -} -#endif /* CFE_API_setenv || CFE_API_ALL */ - -#if (defined(CFE_API_strlen) || defined(CFE_API_ALL)) \ - && !defined(CFE_API_STRLEN_CUSTOM) -int cfe_strlen(char *name) -{ - int count = 0; - - while (*name++) - count++; - - return count; -} -#endif /* CFE_API_strlen || CFE_API_ALL */ - -#if defined(CFE_API_write) || defined(CFE_API_ALL) -int cfe_write(int handle, unsigned char *buffer, int length) -{ - return cfe_writeblk(handle, 0, buffer, length); -} -#endif /* CFE_API_write || CFE_API_ALL */ - -#if defined(CFE_API_writeblk) || defined(CFE_API_ALL) -int -cfe_writeblk(int handle, cfe_xint_t offset, unsigned char *buffer, - int length) -{ - cfe_xiocb_t xiocb; - - xiocb.xiocb_fcode = CFE_CMD_DEV_WRITE; - xiocb.xiocb_status = 0; - xiocb.xiocb_handle = handle; - xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_buffer_t); - xiocb.plist.xiocb_buffer.buf_offset = offset; - xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); - xiocb.plist.xiocb_buffer.buf_length = length; - - cfe_iocb_dispatch(&xiocb); - - if (xiocb.xiocb_status < 0) - return xiocb.xiocb_status; - return xiocb.plist.xiocb_buffer.buf_retlen; -} -#endif /* CFE_API_writeblk || CFE_API_ALL */ diff --git a/arch/mips/sibyte/cfe/cfe_api.h b/arch/mips/sibyte/cfe/cfe_api.h deleted file mode 100644 index d8230cc..0000000 --- a/arch/mips/sibyte/cfe/cfe_api.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (C) 2000, 2001, 2002 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -/* ********************************************************************* - * - * Broadcom Common Firmware Environment (CFE) - * - * Device function prototypes File: cfe_api.h - * - * This file contains declarations for doing callbacks to - * cfe from an application. It should be the only header - * needed by the application to use this library - * - * Authors: Mitch Lichtenberg, Chris Demetriou - * - ********************************************************************* */ - -#ifndef CFE_API_H -#define CFE_API_H - -/* - * Apply customizations here for different OSes. These need to: - * * typedef uint64_t, int64_t, intptr_t, uintptr_t. - * * define cfe_strlen() if use of an existing function is desired. - * * define CFE_API_IMPL_NAMESPACE if API functions are to use - * names in the implementation namespace. - * Also, optionally, if the build environment does not do so automatically, - * CFE_API_* can be defined here as desired. - */ -/* Begin customization. */ -#include -#include - -typedef long intptr_t; - -#define cfe_strlen strlen - -#define CFE_API_ALL -#define CFE_API_STRLEN_CUSTOM -/* End customization. */ - - -/* ********************************************************************* - * Constants - ********************************************************************* */ - -/* Seal indicating CFE's presence, passed to user program. */ -#define CFE_EPTSEAL 0x43464531 - -#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */ -#define CFE_MI_AVAILABLE 1 /* memory is available */ - -#define CFE_FLG_WARMSTART 0x00000001 -#define CFE_FLG_FULL_ARENA 0x00000001 -#define CFE_FLG_ENV_PERMANENT 0x00000001 - -#define CFE_CPU_CMD_START 1 -#define CFE_CPU_CMD_STOP 0 - -#define CFE_STDHANDLE_CONSOLE 0 - -#define CFE_DEV_NETWORK 1 -#define CFE_DEV_DISK 2 -#define CFE_DEV_FLASH 3 -#define CFE_DEV_SERIAL 4 -#define CFE_DEV_CPU 5 -#define CFE_DEV_NVRAM 6 -#define CFE_DEV_CLOCK 7 -#define CFE_DEV_OTHER 8 -#define CFE_DEV_MASK 0x0F - -#define CFE_CACHE_FLUSH_D 1 -#define CFE_CACHE_INVAL_I 2 -#define CFE_CACHE_INVAL_D 4 -#define CFE_CACHE_INVAL_L2 8 - -#define CFE_FWI_64BIT 0x00000001 -#define CFE_FWI_32BIT 0x00000002 -#define CFE_FWI_RELOC 0x00000004 -#define CFE_FWI_UNCACHED 0x00000008 -#define CFE_FWI_MULTICPU 0x00000010 -#define CFE_FWI_FUNCSIM 0x00000020 -#define CFE_FWI_RTLSIM 0x00000040 - -typedef struct { - int64_t fwi_version; /* major, minor, eco version */ - int64_t fwi_totalmem; /* total installed mem */ - int64_t fwi_flags; /* various flags */ - int64_t fwi_boardid; /* board ID */ - int64_t fwi_bootarea_va; /* VA of boot area */ - int64_t fwi_bootarea_pa; /* PA of boot area */ - int64_t fwi_bootarea_size; /* size of boot area */ -} cfe_fwinfo_t; - - -/* - * cfe_strlen is handled specially: If already defined, it has been - * overridden in this environment with a standard strlen-like function. - */ -#ifdef cfe_strlen -# define CFE_API_STRLEN_CUSTOM -#else -# ifdef CFE_API_IMPL_NAMESPACE -# define cfe_strlen(a) __cfe_strlen(a) -# endif -int cfe_strlen(char *name); -#endif - -/* - * Defines and prototypes for functions which take no arguments. - */ -#ifdef CFE_API_IMPL_NAMESPACE -int64_t __cfe_getticks(void); -#define cfe_getticks() __cfe_getticks() -#else -int64_t cfe_getticks(void); -#endif - -/* - * Defines and prototypes for the rest of the functions. - */ -#ifdef CFE_API_IMPL_NAMESPACE -#define cfe_close(a) __cfe_close(a) -#define cfe_cpu_start(a,b,c,d,e) __cfe_cpu_start(a,b,c,d,e) -#define cfe_cpu_stop(a) __cfe_cpu_stop(a) -#define cfe_enumenv(a,b,d,e,f) __cfe_enumenv(a,b,d,e,f) -#define cfe_enummem(a,b,c,d,e) __cfe_enummem(a,b,c,d,e) -#define cfe_exit(a,b) __cfe_exit(a,b) -#define cfe_flushcache(a) __cfe_cacheflush(a) -#define cfe_getdevinfo(a) __cfe_getdevinfo(a) -#define cfe_getenv(a,b,c) __cfe_getenv(a,b,c) -#define cfe_getfwinfo(a) __cfe_getfwinfo(a) -#define cfe_getstdhandle(a) __cfe_getstdhandle(a) -#define cfe_init(a,b) __cfe_init(a,b) -#define cfe_inpstat(a) __cfe_inpstat(a) -#define cfe_ioctl(a,b,c,d,e,f) __cfe_ioctl(a,b,c,d,e,f) -#define cfe_open(a) __cfe_open(a) -#define cfe_read(a,b,c) __cfe_read(a,b,c) -#define cfe_readblk(a,b,c,d) __cfe_readblk(a,b,c,d) -#define cfe_setenv(a,b) __cfe_setenv(a,b) -#define cfe_write(a,b,c) __cfe_write(a,b,c) -#define cfe_writeblk(a,b,c,d) __cfe_writeblk(a,b,c,d) -#endif /* CFE_API_IMPL_NAMESPACE */ - -int cfe_close(int handle); -int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1); -int cfe_cpu_stop(int cpu); -int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen); -int cfe_enummem(int idx, int flags, uint64_t * start, uint64_t * length, - uint64_t * type); -int cfe_exit(int warm, int status); -int cfe_flushcache(int flg); -int cfe_getdevinfo(char *name); -int cfe_getenv(char *name, char *dest, int destlen); -int cfe_getfwinfo(cfe_fwinfo_t * info); -int cfe_getstdhandle(int flg); -int cfe_init(uint64_t handle, uint64_t ept); -int cfe_inpstat(int handle); -int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer, - int length, int *retlen, uint64_t offset); -int cfe_open(char *name); -int cfe_read(int handle, unsigned char *buffer, int length); -int cfe_readblk(int handle, int64_t offset, unsigned char *buffer, - int length); -int cfe_setenv(char *name, char *val); -int cfe_write(int handle, unsigned char *buffer, int length); -int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer, - int length); - -#endif /* CFE_API_H */ diff --git a/arch/mips/sibyte/cfe/cfe_api_int.h b/arch/mips/sibyte/cfe/cfe_api_int.h deleted file mode 100644 index f7e5a64..0000000 --- a/arch/mips/sibyte/cfe/cfe_api_int.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (C) 2000, 2001, 2002 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -/* ********************************************************************* - * - * Broadcom Common Firmware Environment (CFE) - * - * Device function prototypes File: cfe_api_int.h - * - * This header defines all internal types and macros for the - * library. This is stuff that's not exported to an app - * using the library. - * - * Authors: Mitch Lichtenberg, Chris Demetriou - * - ********************************************************************* */ - -#ifndef CFE_API_INT_H -#define CFE_API_INT_H - -/* ********************************************************************* - * Constants - ********************************************************************* */ - -#define CFE_CMD_FW_GETINFO 0 -#define CFE_CMD_FW_RESTART 1 -#define CFE_CMD_FW_BOOT 2 -#define CFE_CMD_FW_CPUCTL 3 -#define CFE_CMD_FW_GETTIME 4 -#define CFE_CMD_FW_MEMENUM 5 -#define CFE_CMD_FW_FLUSHCACHE 6 - -#define CFE_CMD_DEV_GETHANDLE 9 -#define CFE_CMD_DEV_ENUM 10 -#define CFE_CMD_DEV_OPEN 11 -#define CFE_CMD_DEV_INPSTAT 12 -#define CFE_CMD_DEV_READ 13 -#define CFE_CMD_DEV_WRITE 14 -#define CFE_CMD_DEV_IOCTL 15 -#define CFE_CMD_DEV_CLOSE 16 -#define CFE_CMD_DEV_GETINFO 17 - -#define CFE_CMD_ENV_ENUM 20 -#define CFE_CMD_ENV_GET 22 -#define CFE_CMD_ENV_SET 23 -#define CFE_CMD_ENV_DEL 24 - -#define CFE_CMD_MAX 32 - -#define CFE_CMD_VENDOR_USE 0x8000 /* codes above this are for customer use */ - -/* ********************************************************************* - * Structures - ********************************************************************* */ - -typedef uint64_t cfe_xuint_t; -typedef int64_t cfe_xint_t; -typedef int64_t cfe_xptr_t; - -typedef struct xiocb_buffer_s { - cfe_xuint_t buf_offset; /* offset on device (bytes) */ - cfe_xptr_t buf_ptr; /* pointer to a buffer */ - cfe_xuint_t buf_length; /* length of this buffer */ - cfe_xuint_t buf_retlen; /* returned length (for read ops) */ - cfe_xuint_t buf_ioctlcmd; /* IOCTL command (used only for IOCTLs) */ -} xiocb_buffer_t; - -#define buf_devflags buf_ioctlcmd /* returned device info flags */ - -typedef struct xiocb_inpstat_s { - cfe_xuint_t inp_status; /* 1 means input available */ -} xiocb_inpstat_t; - -typedef struct xiocb_envbuf_s { - cfe_xint_t enum_idx; /* 0-based enumeration index */ - cfe_xptr_t name_ptr; /* name string buffer */ - cfe_xint_t name_length; /* size of name buffer */ - cfe_xptr_t val_ptr; /* value string buffer */ - cfe_xint_t val_length; /* size of value string buffer */ -} xiocb_envbuf_t; - -typedef struct xiocb_cpuctl_s { - cfe_xuint_t cpu_number; /* cpu number to control */ - cfe_xuint_t cpu_command; /* command to issue to CPU */ - cfe_xuint_t start_addr; /* CPU start address */ - cfe_xuint_t gp_val; /* starting GP value */ - cfe_xuint_t sp_val; /* starting SP value */ - cfe_xuint_t a1_val; /* starting A1 value */ -} xiocb_cpuctl_t; - -typedef struct xiocb_time_s { - cfe_xint_t ticks; /* current time in ticks */ -} xiocb_time_t; - -typedef struct xiocb_exitstat_s { - cfe_xint_t status; -} xiocb_exitstat_t; - -typedef struct xiocb_meminfo_s { - cfe_xint_t mi_idx; /* 0-based enumeration index */ - cfe_xint_t mi_type; /* type of memory block */ - cfe_xuint_t mi_addr; /* physical start address */ - cfe_xuint_t mi_size; /* block size */ -} xiocb_meminfo_t; - -typedef struct xiocb_fwinfo_s { - cfe_xint_t fwi_version; /* major, minor, eco version */ - cfe_xint_t fwi_totalmem; /* total installed mem */ - cfe_xint_t fwi_flags; /* various flags */ - cfe_xint_t fwi_boardid; /* board ID */ - cfe_xint_t fwi_bootarea_va; /* VA of boot area */ - cfe_xint_t fwi_bootarea_pa; /* PA of boot area */ - cfe_xint_t fwi_bootarea_size; /* size of boot area */ - cfe_xint_t fwi_reserved1; - cfe_xint_t fwi_reserved2; - cfe_xint_t fwi_reserved3; -} xiocb_fwinfo_t; - -typedef struct cfe_xiocb_s { - cfe_xuint_t xiocb_fcode; /* IOCB function code */ - cfe_xint_t xiocb_status; /* return status */ - cfe_xint_t xiocb_handle; /* file/device handle */ - cfe_xuint_t xiocb_flags; /* flags for this IOCB */ - cfe_xuint_t xiocb_psize; /* size of parameter list */ - union { - xiocb_buffer_t xiocb_buffer; /* buffer parameters */ - xiocb_inpstat_t xiocb_inpstat; /* input status parameters */ - xiocb_envbuf_t xiocb_envbuf; /* environment function parameters */ - xiocb_cpuctl_t xiocb_cpuctl; /* CPU control parameters */ - xiocb_time_t xiocb_time; /* timer parameters */ - xiocb_meminfo_t xiocb_meminfo; /* memory arena info parameters */ - xiocb_fwinfo_t xiocb_fwinfo; /* firmware information */ - xiocb_exitstat_t xiocb_exitstat; /* Exit Status */ - } plist; -} cfe_xiocb_t; - -#endif /* CFE_API_INT_H */ diff --git a/arch/mips/sibyte/cfe/cfe_error.h b/arch/mips/sibyte/cfe/cfe_error.h deleted file mode 100644 index 975f000..0000000 --- a/arch/mips/sibyte/cfe/cfe_error.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (C) 2000, 2001, 2002 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -/* ********************************************************************* - * - * Broadcom Common Firmware Environment (CFE) - * - * Error codes File: cfe_error.h - * - * CFE's global error code list is here. - * - * Author: Mitch Lichtenberg - * - ********************************************************************* */ - - -#define CFE_OK 0 -#define CFE_ERR -1 /* generic error */ -#define CFE_ERR_INV_COMMAND -2 -#define CFE_ERR_EOF -3 -#define CFE_ERR_IOERR -4 -#define CFE_ERR_NOMEM -5 -#define CFE_ERR_DEVNOTFOUND -6 -#define CFE_ERR_DEVOPEN -7 -#define CFE_ERR_INV_PARAM -8 -#define CFE_ERR_ENVNOTFOUND -9 -#define CFE_ERR_ENVREADONLY -10 - -#define CFE_ERR_NOTELF -11 -#define CFE_ERR_NOT32BIT -12 -#define CFE_ERR_WRONGENDIAN -13 -#define CFE_ERR_BADELFVERS -14 -#define CFE_ERR_NOTMIPS -15 -#define CFE_ERR_BADELFFMT -16 -#define CFE_ERR_BADADDR -17 - -#define CFE_ERR_FILENOTFOUND -18 -#define CFE_ERR_UNSUPPORTED -19 - -#define CFE_ERR_HOSTUNKNOWN -20 - -#define CFE_ERR_TIMEOUT -21 - -#define CFE_ERR_PROTOCOLERR -22 - -#define CFE_ERR_NETDOWN -23 -#define CFE_ERR_NONAMESERVER -24 - -#define CFE_ERR_NOHANDLES -25 -#define CFE_ERR_ALREADYBOUND -26 - -#define CFE_ERR_CANNOTSET -27 -#define CFE_ERR_NOMORE -28 -#define CFE_ERR_BADFILESYS -29 -#define CFE_ERR_FSNOTAVAIL -30 - -#define CFE_ERR_INVBOOTBLOCK -31 -#define CFE_ERR_WRONGDEVTYPE -32 -#define CFE_ERR_BBCHECKSUM -33 -#define CFE_ERR_BOOTPROGCHKSUM -34 - -#define CFE_ERR_LDRNOTAVAIL -35 - -#define CFE_ERR_NOTREADY -36 - -#define CFE_ERR_GETMEM -37 -#define CFE_ERR_SETMEM -38 - -#define CFE_ERR_NOTCONN -39 -#define CFE_ERR_ADDRINUSE -40 diff --git a/arch/mips/sibyte/cfe/console.c b/arch/mips/sibyte/cfe/console.c index 4cec9d7..7a4ecfc 100644 --- a/arch/mips/sibyte/cfe/console.c +++ b/arch/mips/sibyte/cfe/console.c @@ -4,8 +4,8 @@ #include -#include "cfe_api.h" -#include "cfe_error.h" +#include +#include extern int cfe_cons_handle; diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c index 51898dd..d842b98 100644 --- a/arch/mips/sibyte/cfe/setup.c +++ b/arch/mips/sibyte/cfe/setup.c @@ -29,8 +29,8 @@ #include #include -#include "cfe_api.h" -#include "cfe_error.h" +#include +#include /* Max ram addressable in 32-bit segments */ #ifdef CONFIG_64BIT diff --git a/arch/mips/sibyte/cfe/smp.c b/arch/mips/sibyte/cfe/smp.c index 5de4cff..534a629 100644 --- a/arch/mips/sibyte/cfe/smp.c +++ b/arch/mips/sibyte/cfe/smp.c @@ -21,8 +21,8 @@ #include #include -#include "cfe_api.h" -#include "cfe_error.h" +#include +#include /* * Use CFE to find out how many CPUs are available, setting up diff --git a/include/asm-mips/fw/cfe/cfe_api.h b/include/asm-mips/fw/cfe/cfe_api.h new file mode 100644 index 0000000..d8230cc --- /dev/null +++ b/include/asm-mips/fw/cfe/cfe_api.h @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2000, 2001, 2002 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* ********************************************************************* + * + * Broadcom Common Firmware Environment (CFE) + * + * Device function prototypes File: cfe_api.h + * + * This file contains declarations for doing callbacks to + * cfe from an application. It should be the only header + * needed by the application to use this library + * + * Authors: Mitch Lichtenberg, Chris Demetriou + * + ********************************************************************* */ + +#ifndef CFE_API_H +#define CFE_API_H + +/* + * Apply customizations here for different OSes. These need to: + * * typedef uint64_t, int64_t, intptr_t, uintptr_t. + * * define cfe_strlen() if use of an existing function is desired. + * * define CFE_API_IMPL_NAMESPACE if API functions are to use + * names in the implementation namespace. + * Also, optionally, if the build environment does not do so automatically, + * CFE_API_* can be defined here as desired. + */ +/* Begin customization. */ +#include +#include + +typedef long intptr_t; + +#define cfe_strlen strlen + +#define CFE_API_ALL +#define CFE_API_STRLEN_CUSTOM +/* End customization. */ + + +/* ********************************************************************* + * Constants + ********************************************************************* */ + +/* Seal indicating CFE's presence, passed to user program. */ +#define CFE_EPTSEAL 0x43464531 + +#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */ +#define CFE_MI_AVAILABLE 1 /* memory is available */ + +#define CFE_FLG_WARMSTART 0x00000001 +#define CFE_FLG_FULL_ARENA 0x00000001 +#define CFE_FLG_ENV_PERMANENT 0x00000001 + +#define CFE_CPU_CMD_START 1 +#define CFE_CPU_CMD_STOP 0 + +#define CFE_STDHANDLE_CONSOLE 0 + +#define CFE_DEV_NETWORK 1 +#define CFE_DEV_DISK 2 +#define CFE_DEV_FLASH 3 +#define CFE_DEV_SERIAL 4 +#define CFE_DEV_CPU 5 +#define CFE_DEV_NVRAM 6 +#define CFE_DEV_CLOCK 7 +#define CFE_DEV_OTHER 8 +#define CFE_DEV_MASK 0x0F + +#define CFE_CACHE_FLUSH_D 1 +#define CFE_CACHE_INVAL_I 2 +#define CFE_CACHE_INVAL_D 4 +#define CFE_CACHE_INVAL_L2 8 + +#define CFE_FWI_64BIT 0x00000001 +#define CFE_FWI_32BIT 0x00000002 +#define CFE_FWI_RELOC 0x00000004 +#define CFE_FWI_UNCACHED 0x00000008 +#define CFE_FWI_MULTICPU 0x00000010 +#define CFE_FWI_FUNCSIM 0x00000020 +#define CFE_FWI_RTLSIM 0x00000040 + +typedef struct { + int64_t fwi_version; /* major, minor, eco version */ + int64_t fwi_totalmem; /* total installed mem */ + int64_t fwi_flags; /* various flags */ + int64_t fwi_boardid; /* board ID */ + int64_t fwi_bootarea_va; /* VA of boot area */ + int64_t fwi_bootarea_pa; /* PA of boot area */ + int64_t fwi_bootarea_size; /* size of boot area */ +} cfe_fwinfo_t; + + +/* + * cfe_strlen is handled specially: If already defined, it has been + * overridden in this environment with a standard strlen-like function. + */ +#ifdef cfe_strlen +# define CFE_API_STRLEN_CUSTOM +#else +# ifdef CFE_API_IMPL_NAMESPACE +# define cfe_strlen(a) __cfe_strlen(a) +# endif +int cfe_strlen(char *name); +#endif + +/* + * Defines and prototypes for functions which take no arguments. + */ +#ifdef CFE_API_IMPL_NAMESPACE +int64_t __cfe_getticks(void); +#define cfe_getticks() __cfe_getticks() +#else +int64_t cfe_getticks(void); +#endif + +/* + * Defines and prototypes for the rest of the functions. + */ +#ifdef CFE_API_IMPL_NAMESPACE +#define cfe_close(a) __cfe_close(a) +#define cfe_cpu_start(a,b,c,d,e) __cfe_cpu_start(a,b,c,d,e) +#define cfe_cpu_stop(a) __cfe_cpu_stop(a) +#define cfe_enumenv(a,b,d,e,f) __cfe_enumenv(a,b,d,e,f) +#define cfe_enummem(a,b,c,d,e) __cfe_enummem(a,b,c,d,e) +#define cfe_exit(a,b) __cfe_exit(a,b) +#define cfe_flushcache(a) __cfe_cacheflush(a) +#define cfe_getdevinfo(a) __cfe_getdevinfo(a) +#define cfe_getenv(a,b,c) __cfe_getenv(a,b,c) +#define cfe_getfwinfo(a) __cfe_getfwinfo(a) +#define cfe_getstdhandle(a) __cfe_getstdhandle(a) +#define cfe_init(a,b) __cfe_init(a,b) +#define cfe_inpstat(a) __cfe_inpstat(a) +#define cfe_ioctl(a,b,c,d,e,f) __cfe_ioctl(a,b,c,d,e,f) +#define cfe_open(a) __cfe_open(a) +#define cfe_read(a,b,c) __cfe_read(a,b,c) +#define cfe_readblk(a,b,c,d) __cfe_readblk(a,b,c,d) +#define cfe_setenv(a,b) __cfe_setenv(a,b) +#define cfe_write(a,b,c) __cfe_write(a,b,c) +#define cfe_writeblk(a,b,c,d) __cfe_writeblk(a,b,c,d) +#endif /* CFE_API_IMPL_NAMESPACE */ + +int cfe_close(int handle); +int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1); +int cfe_cpu_stop(int cpu); +int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen); +int cfe_enummem(int idx, int flags, uint64_t * start, uint64_t * length, + uint64_t * type); +int cfe_exit(int warm, int status); +int cfe_flushcache(int flg); +int cfe_getdevinfo(char *name); +int cfe_getenv(char *name, char *dest, int destlen); +int cfe_getfwinfo(cfe_fwinfo_t * info); +int cfe_getstdhandle(int flg); +int cfe_init(uint64_t handle, uint64_t ept); +int cfe_inpstat(int handle); +int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer, + int length, int *retlen, uint64_t offset); +int cfe_open(char *name); +int cfe_read(int handle, unsigned char *buffer, int length); +int cfe_readblk(int handle, int64_t offset, unsigned char *buffer, + int length); +int cfe_setenv(char *name, char *val); +int cfe_write(int handle, unsigned char *buffer, int length); +int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer, + int length); + +#endif /* CFE_API_H */ diff --git a/include/asm-mips/fw/cfe/cfe_error.h b/include/asm-mips/fw/cfe/cfe_error.h new file mode 100644 index 0000000..975f000 --- /dev/null +++ b/include/asm-mips/fw/cfe/cfe_error.h @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2000, 2001, 2002 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* ********************************************************************* + * + * Broadcom Common Firmware Environment (CFE) + * + * Error codes File: cfe_error.h + * + * CFE's global error code list is here. + * + * Author: Mitch Lichtenberg + * + ********************************************************************* */ + + +#define CFE_OK 0 +#define CFE_ERR -1 /* generic error */ +#define CFE_ERR_INV_COMMAND -2 +#define CFE_ERR_EOF -3 +#define CFE_ERR_IOERR -4 +#define CFE_ERR_NOMEM -5 +#define CFE_ERR_DEVNOTFOUND -6 +#define CFE_ERR_DEVOPEN -7 +#define CFE_ERR_INV_PARAM -8 +#define CFE_ERR_ENVNOTFOUND -9 +#define CFE_ERR_ENVREADONLY -10 + +#define CFE_ERR_NOTELF -11 +#define CFE_ERR_NOT32BIT -12 +#define CFE_ERR_WRONGENDIAN -13 +#define CFE_ERR_BADELFVERS -14 +#define CFE_ERR_NOTMIPS -15 +#define CFE_ERR_BADELFFMT -16 +#define CFE_ERR_BADADDR -17 + +#define CFE_ERR_FILENOTFOUND -18 +#define CFE_ERR_UNSUPPORTED -19 + +#define CFE_ERR_HOSTUNKNOWN -20 + +#define CFE_ERR_TIMEOUT -21 + +#define CFE_ERR_PROTOCOLERR -22 + +#define CFE_ERR_NETDOWN -23 +#define CFE_ERR_NONAMESERVER -24 + +#define CFE_ERR_NOHANDLES -25 +#define CFE_ERR_ALREADYBOUND -26 + +#define CFE_ERR_CANNOTSET -27 +#define CFE_ERR_NOMORE -28 +#define CFE_ERR_BADFILESYS -29 +#define CFE_ERR_FSNOTAVAIL -30 + +#define CFE_ERR_INVBOOTBLOCK -31 +#define CFE_ERR_WRONGDEVTYPE -32 +#define CFE_ERR_BBCHECKSUM -33 +#define CFE_ERR_BOOTPROGCHKSUM -34 + +#define CFE_ERR_LDRNOTAVAIL -35 + +#define CFE_ERR_NOTREADY -36 + +#define CFE_ERR_GETMEM -37 +#define CFE_ERR_SETMEM -38 + +#define CFE_ERR_NOTCONN -39 +#define CFE_ERR_ADDRINUSE -40 -- cgit v0.10.2 From 2f56cfdd812a17623483d3dfa3370a2e6282b245 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Wed, 5 Sep 2007 08:59:34 +0200 Subject: [MIPS] Move ARC code into arch/mips/fw/arc Move the ARC code to arch/mips/fw/arc from arch/mips/arc. Signed-off-by: Aurelien Jarno Signed-off-by: Ralf Baechle diff --git a/arch/mips/Makefile b/arch/mips/Makefile index a097ae6..b0fac2d 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -148,7 +148,7 @@ endif # # Firmware support # -libs-$(CONFIG_ARC) += arch/mips/arc/ +libs-$(CONFIG_ARC) += arch/mips/fw/arc/ libs-$(CONFIG_CFE) += arch/mips/fw/cfe/ libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/ diff --git a/arch/mips/arc/Makefile b/arch/mips/arc/Makefile deleted file mode 100644 index 4f349ec..0000000 --- a/arch/mips/arc/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# Makefile for the ARC prom monitor library routines under Linux. -# - -lib-y += cmdline.o env.o file.o identify.o init.o \ - misc.o salone.o time.o tree.o - -lib-$(CONFIG_ARC_MEMORY) += memory.o -lib-$(CONFIG_ARC_CONSOLE) += arc_con.o -lib-$(CONFIG_ARC_PROMLIB) += promlib.o diff --git a/arch/mips/arc/arc_con.c b/arch/mips/arc/arc_con.c deleted file mode 100644 index bc32fe6..0000000 --- a/arch/mips/arc/arc_con.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Wrap-around code for a console using the - * ARC io-routines. - * - * Copyright (c) 1998 Harald Koerfgen - * Copyright (c) 2001 Ralf Baechle - * Copyright (c) 2002 Thiemo Seufer - */ -#include -#include -#include -#include -#include -#include - -static void prom_console_write(struct console *co, const char *s, - unsigned count) -{ - /* Do each character */ - while (count--) { - if (*s == '\n') - prom_putchar('\r'); - prom_putchar(*s++); - } -} - -static int prom_console_setup(struct console *co, char *options) -{ - return !(prom_flags & PROM_FLAG_USE_AS_CONSOLE); -} - -static struct console arc_cons = { - .name = "arc", - .write = prom_console_write, - .setup = prom_console_setup, - .flags = CON_PRINTBUFFER, - .index = -1, -}; - -/* - * Register console. - */ - -static int __init arc_console_init(void) -{ - register_console(&arc_cons); - - return 0; -} -console_initcall(arc_console_init); diff --git a/arch/mips/arc/cmdline.c b/arch/mips/arc/cmdline.c deleted file mode 100644 index fd604ef..0000000 --- a/arch/mips/arc/cmdline.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * cmdline.c: Kernel command line creation using ARCS argc/argv. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include -#include -#include - -#include -#include - -#undef DEBUG_CMDLINE - -char * __init prom_getcmdline(void) -{ - return arcs_cmdline; -} - -static char *ignored[] = { - "ConsoleIn=", - "ConsoleOut=", - "SystemPartition=", - "OSLoader=", - "OSLoadPartition=", - "OSLoadFilename=", - "OSLoadOptions=" -}; - -static char *used_arc[][2] = { - { "OSLoadPartition=", "root=" }, - { "OSLoadOptions=", "" } -}; - -static char * __init move_firmware_args(char* cp) -{ - char *s; - int actr, i; - - actr = 1; /* Always ignore argv[0] */ - - while (actr < prom_argc) { - for(i = 0; i < ARRAY_SIZE(used_arc); i++) { - int len = strlen(used_arc[i][0]); - - if (!strncmp(prom_argv(actr), used_arc[i][0], len)) { - /* Ok, we want it. First append the replacement... */ - strcat(cp, used_arc[i][1]); - cp += strlen(used_arc[i][1]); - /* ... and now the argument */ - s = strstr(prom_argv(actr), "="); - if (s) { - s++; - strcpy(cp, s); - cp += strlen(s); - } - *cp++ = ' '; - break; - } - } - actr++; - } - - return cp; -} - -void __init prom_init_cmdline(void) -{ - char *cp; - int actr, i; - - actr = 1; /* Always ignore argv[0] */ - - cp = arcs_cmdline; - /* - * Move ARC variables to the beginning to make sure they can be - * overridden by later arguments. - */ - cp = move_firmware_args(cp); - - while (actr < prom_argc) { - for (i = 0; i < ARRAY_SIZE(ignored); i++) { - int len = strlen(ignored[i]); - - if (!strncmp(prom_argv(actr), ignored[i], len)) - goto pic_cont; - } - /* Ok, we want it. */ - strcpy(cp, prom_argv(actr)); - cp += strlen(prom_argv(actr)); - *cp++ = ' '; - - pic_cont: - actr++; - } - - if (cp != arcs_cmdline) /* get rid of trailing space */ - --cp; - *cp = '\0'; - -#ifdef DEBUG_CMDLINE - printk(KERN_DEBUG "prom cmdline: %s\n", arcs_cmdline); -#endif -} diff --git a/arch/mips/arc/env.c b/arch/mips/arc/env.c deleted file mode 100644 index e521a6e..0000000 --- a/arch/mips/arc/env.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * env.c: ARCS environment variable routines. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include -#include -#include - -#include -#include - -PCHAR __init -ArcGetEnvironmentVariable(CHAR *name) -{ - return (CHAR *) ARC_CALL1(get_evar, name); -} - -LONG __init -ArcSetEnvironmentVariable(PCHAR name, PCHAR value) -{ - return ARC_CALL2(set_evar, name, value); -} diff --git a/arch/mips/arc/file.c b/arch/mips/arc/file.c deleted file mode 100644 index cb0127cf..0000000 --- a/arch/mips/arc/file.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * ARC firmware interface. - * - * Copyright (C) 1994, 1995, 1996, 1999 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#include - -#include -#include - -LONG -ArcGetDirectoryEntry(ULONG FileID, struct linux_vdirent *Buffer, - ULONG N, ULONG *Count) -{ - return ARC_CALL4(get_vdirent, FileID, Buffer, N, Count); -} - -LONG -ArcOpen(CHAR *Path, enum linux_omode OpenMode, ULONG *FileID) -{ - return ARC_CALL3(open, Path, OpenMode, FileID); -} - -LONG -ArcClose(ULONG FileID) -{ - return ARC_CALL1(close, FileID); -} - -LONG -ArcRead(ULONG FileID, VOID *Buffer, ULONG N, ULONG *Count) -{ - return ARC_CALL4(read, FileID, Buffer, N, Count); -} - -LONG -ArcGetReadStatus(ULONG FileID) -{ - return ARC_CALL1(get_rstatus, FileID); -} - -LONG -ArcWrite(ULONG FileID, PVOID Buffer, ULONG N, PULONG Count) -{ - return ARC_CALL4(write, FileID, Buffer, N, Count); -} - -LONG -ArcSeek(ULONG FileID, struct linux_bigint *Position, enum linux_seekmode SeekMode) -{ - return ARC_CALL3(seek, FileID, Position, SeekMode); -} - -LONG -ArcMount(char *name, enum linux_mountops op) -{ - return ARC_CALL2(mount, name, op); -} - -LONG -ArcGetFileInformation(ULONG FileID, struct linux_finfo *Information) -{ - return ARC_CALL2(get_finfo, FileID, Information); -} - -LONG ArcSetFileInformation(ULONG FileID, ULONG AttributeFlags, - ULONG AttributeMask) -{ - return ARC_CALL3(set_finfo, FileID, AttributeFlags, AttributeMask); -} diff --git a/arch/mips/arc/identify.c b/arch/mips/arc/identify.c deleted file mode 100644 index 4b90736..0000000 --- a/arch/mips/arc/identify.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * identify.c: identify machine by looking up system identifier - * - * Copyright (C) 1998 Thomas Bogendoerfer - * - * This code is based on arch/mips/sgi/kernel/system.c, which is - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include -#include -#include -#include - -#include -#include - -struct smatch { - char *arcname; - char *liname; - int group; - int type; - int flags; -}; - -static struct smatch mach_table[] = { - { "SGI-IP22", - "SGI Indy", - MACH_GROUP_SGI, - MACH_SGI_IP22, - PROM_FLAG_ARCS - }, { "SGI-IP27", - "SGI Origin", - MACH_GROUP_SGI, - MACH_SGI_IP27, - PROM_FLAG_ARCS - }, { "SGI-IP28", - "SGI IP28", - MACH_GROUP_SGI, - MACH_SGI_IP28, - PROM_FLAG_ARCS - }, { "SGI-IP30", - "SGI Octane", - MACH_GROUP_SGI, - MACH_SGI_IP30, - PROM_FLAG_ARCS - }, { "SGI-IP32", - "SGI O2", - MACH_GROUP_SGI, - MACH_SGI_IP32, - PROM_FLAG_ARCS - }, { "Microsoft-Jazz", - "Jazz MIPS_Magnum_4000", - MACH_GROUP_JAZZ, - MACH_MIPS_MAGNUM_4000, - 0 - }, { "PICA-61", - "Jazz Acer_PICA_61", - MACH_GROUP_JAZZ, - MACH_ACER_PICA_61, - 0 - }, { "RM200PCI", - "SNI RM200_PCI", - MACH_GROUP_SNI_RM, - MACH_SNI_RM200_PCI, - PROM_FLAG_DONT_FREE_TEMP - } -}; - -int prom_flags; - -static struct smatch * __init string_to_mach(const char *s) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(mach_table); i++) { - if (!strcmp(s, mach_table[i].arcname)) - return &mach_table[i]; - } - - panic("Yeee, could not determine architecture type <%s>", s); -} - -char *system_type; - -const char *get_system_type(void) -{ - return system_type; -} - -void __init prom_identify_arch(void) -{ - pcomponent *p; - struct smatch *mach; - const char *iname; - - /* - * The root component tells us what machine architecture we have here. - */ - p = ArcGetChild(PROM_NULL_COMPONENT); - if (p == NULL) { -#ifdef CONFIG_SGI_IP27 - /* IP27 PROM misbehaves, seems to not implement ARC - GetChild(). So we just assume it's an IP27. */ - iname = "SGI-IP27"; -#else - iname = "Unknown"; -#endif - } else - iname = (char *) (long) p->iname; - - printk("ARCH: %s\n", iname); - mach = string_to_mach(iname); - system_type = mach->liname; - - mips_machgroup = mach->group; - mips_machtype = mach->type; - prom_flags = mach->flags; -} diff --git a/arch/mips/arc/init.c b/arch/mips/arc/init.c deleted file mode 100644 index e2f75b1..0000000 --- a/arch/mips/arc/init.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * PROM library initialisation code. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include -#include - -#include -#include - -#undef DEBUG_PROM_INIT - -/* Master romvec interface. */ -struct linux_romvec *romvec; -int prom_argc; -LONG *_prom_argv, *_prom_envp; - -void __init prom_init(void) -{ - PSYSTEM_PARAMETER_BLOCK pb = PROMBLOCK; - - romvec = ROMVECTOR; - - prom_argc = fw_arg0; - _prom_argv = (LONG *) fw_arg1; - _prom_envp = (LONG *) fw_arg2; - - if (pb->magic != 0x53435241) { - printk(KERN_CRIT "Aieee, bad prom vector magic %08lx\n", - (unsigned long) pb->magic); - while(1) - ; - } - - prom_init_cmdline(); - prom_identify_arch(); - printk(KERN_INFO "PROMLIB: ARC firmware Version %d Revision %d\n", - pb->ver, pb->rev); - prom_meminit(); - -#ifdef DEBUG_PROM_INIT - pr_info("Press a key to reboot\n"); - ArcRead(0, &c, 1, &cnt); - ArcEnterInteractiveMode(); -#endif -} diff --git a/arch/mips/arc/memory.c b/arch/mips/arc/memory.c deleted file mode 100644 index 83d1579..0000000 --- a/arch/mips/arc/memory.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * memory.c: PROM library functions for acquiring/using memory descriptors - * given to us from the ARCS firmware. - * - * Copyright (C) 1996 by David S. Miller - * Copyright (C) 1999, 2000, 2001 by Ralf Baechle - * Copyright (C) 1999, 2000 by Silicon Graphics, Inc. - * - * PROM library functions for acquiring/using memory descriptors given to us - * from the ARCS firmware. This is only used when CONFIG_ARC_MEMORY is set - * because on some machines like SGI IP27 the ARC memory configuration data - * completly bogus and alternate easier to use mechanisms are available. - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#undef DEBUG - -/* - * For ARC firmware memory functions the unit of meassuring memory is always - * a 4k page of memory - */ -#define ARC_PAGE_SHIFT 12 - -struct linux_mdesc * __init ArcGetMemoryDescriptor(struct linux_mdesc *Current) -{ - return (struct linux_mdesc *) ARC_CALL1(get_mdesc, Current); -} - -#ifdef DEBUG /* convenient for debugging */ -static char *arcs_mtypes[8] = { - "Exception Block", - "ARCS Romvec Page", - "Free/Contig RAM", - "Generic Free RAM", - "Bad Memory", - "Standalone Program Pages", - "ARCS Temp Storage Area", - "ARCS Permanent Storage Area" -}; - -static char *arc_mtypes[8] = { - "Exception Block", - "SystemParameterBlock", - "FreeMemory", - "Bad Memory", - "LoadedProgram", - "FirmwareTemporary", - "FirmwarePermanent", - "FreeContiguous" -}; -#define mtypes(a) (prom_flags & PROM_FLAG_ARCS) ? arcs_mtypes[a.arcs] \ - : arc_mtypes[a.arc] -#endif - -static inline int memtype_classify_arcs (union linux_memtypes type) -{ - switch (type.arcs) { - case arcs_fcontig: - case arcs_free: - return BOOT_MEM_RAM; - case arcs_atmp: - return BOOT_MEM_ROM_DATA; - case arcs_eblock: - case arcs_rvpage: - case arcs_bmem: - case arcs_prog: - case arcs_aperm: - return BOOT_MEM_RESERVED; - default: - BUG(); - } - while(1); /* Nuke warning. */ -} - -static inline int memtype_classify_arc (union linux_memtypes type) -{ - switch (type.arc) { - case arc_free: - case arc_fcontig: - return BOOT_MEM_RAM; - case arc_atmp: - return BOOT_MEM_ROM_DATA; - case arc_eblock: - case arc_rvpage: - case arc_bmem: - case arc_prog: - case arc_aperm: - return BOOT_MEM_RESERVED; - default: - BUG(); - } - while(1); /* Nuke warning. */ -} - -static int __init prom_memtype_classify (union linux_memtypes type) -{ - if (prom_flags & PROM_FLAG_ARCS) /* SGI is ``different'' ... */ - return memtype_classify_arcs(type); - - return memtype_classify_arc(type); -} - -void __init prom_meminit(void) -{ - struct linux_mdesc *p; - -#ifdef DEBUG - int i = 0; - - printk("ARCS MEMORY DESCRIPTOR dump:\n"); - p = ArcGetMemoryDescriptor(PROM_NULL_MDESC); - while(p) { - printk("[%d,%p]: base<%08lx> pages<%08lx> type<%s>\n", - i, p, p->base, p->pages, mtypes(p->type)); - p = ArcGetMemoryDescriptor(p); - i++; - } -#endif - - p = PROM_NULL_MDESC; - while ((p = ArcGetMemoryDescriptor(p))) { - unsigned long base, size; - long type; - - base = p->base << ARC_PAGE_SHIFT; - size = p->pages << ARC_PAGE_SHIFT; - type = prom_memtype_classify(p->type); - - add_memory_region(base, size, type); - } -} - -void __init prom_free_prom_memory(void) -{ - unsigned long addr; - int i; - - if (prom_flags & PROM_FLAG_DONT_FREE_TEMP) - return; - - for (i = 0; i < boot_mem_map.nr_map; i++) { - if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) - continue; - - addr = boot_mem_map.map[i].addr; - free_init_pages("prom memory", - addr, addr + boot_mem_map.map[i].size); - } -} diff --git a/arch/mips/arc/misc.c b/arch/mips/arc/misc.c deleted file mode 100644 index b2e10b9..0000000 --- a/arch/mips/arc/misc.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Miscellaneous ARCS PROM routines. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#include -#include - -#include - -#include -#include -#include -#include - -VOID -ArcHalt(VOID) -{ - bc_disable(); - local_irq_disable(); - ARC_CALL0(halt); -never: goto never; -} - -VOID -ArcPowerDown(VOID) -{ - bc_disable(); - local_irq_disable(); - ARC_CALL0(pdown); -never: goto never; -} - -/* XXX is this a soft reset basically? XXX */ -VOID -ArcRestart(VOID) -{ - bc_disable(); - local_irq_disable(); - ARC_CALL0(restart); -never: goto never; -} - -VOID -ArcReboot(VOID) -{ - bc_disable(); - local_irq_disable(); - ARC_CALL0(reboot); -never: goto never; -} - -VOID -ArcEnterInteractiveMode(VOID) -{ - bc_disable(); - local_irq_disable(); - ARC_CALL0(imode); -never: goto never; -} - -LONG -ArcSaveConfiguration(VOID) -{ - return ARC_CALL0(cfg_save); -} - -struct linux_sysid * -ArcGetSystemId(VOID) -{ - return (struct linux_sysid *) ARC_CALL0(get_sysid); -} - -VOID __init -ArcFlushAllCaches(VOID) -{ - ARC_CALL0(cache_flush); -} - -DISPLAY_STATUS * __init ArcGetDisplayStatus(ULONG FileID) -{ - return (DISPLAY_STATUS *) ARC_CALL1(GetDisplayStatus, FileID); -} diff --git a/arch/mips/arc/promlib.c b/arch/mips/arc/promlib.c deleted file mode 100644 index c508c00..0000000 --- a/arch/mips/arc/promlib.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996 David S. Miller (dm@sgi.com) - * Compability with board caches, Ulf Carlsson - */ -#include -#include -#include - -/* - * IP22 boardcache is not compatible with board caches. Thus we disable it - * during romvec action. Since r4xx0.c is always compiled and linked with your - * kernel, this shouldn't cause any harm regardless what MIPS processor you - * have. - * - * The ARC write and read functions seem to interfere with the serial lines - * in some way. You should be careful with them. - */ - -void prom_putchar(char c) -{ - ULONG cnt; - CHAR it = c; - - bc_disable(); - ArcWrite(1, &it, 1, &cnt); - bc_enable(); -} - -char prom_getchar(void) -{ - ULONG cnt; - CHAR c; - - bc_disable(); - ArcRead(0, &c, 1, &cnt); - bc_enable(); - - return c; -} diff --git a/arch/mips/arc/salone.c b/arch/mips/arc/salone.c deleted file mode 100644 index e6afb64..0000000 --- a/arch/mips/arc/salone.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Routines to load into memory and execute stand-along program images using - * ARCS PROM firmware. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include -#include - -LONG __init ArcLoad(CHAR *Path, ULONG TopAddr, ULONG *ExecAddr, ULONG *LowAddr) -{ - return ARC_CALL4(load, Path, TopAddr, ExecAddr, LowAddr); -} - -LONG __init ArcInvoke(ULONG ExecAddr, ULONG StackAddr, ULONG Argc, CHAR *Argv[], - CHAR *Envp[]) -{ - return ARC_CALL5(invoke, ExecAddr, StackAddr, Argc, Argv, Envp); -} - -LONG __init ArcExecute(CHAR *Path, LONG Argc, CHAR *Argv[], CHAR *Envp[]) -{ - return ARC_CALL4(exec, Path, Argc, Argv, Envp); -} diff --git a/arch/mips/arc/time.c b/arch/mips/arc/time.c deleted file mode 100644 index 299ff2c..0000000 --- a/arch/mips/arc/time.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Extracting time information from ARCS prom. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include - -#include -#include - -struct linux_tinfo * __init -ArcGetTime(VOID) -{ - return (struct linux_tinfo *) ARC_CALL0(get_tinfo); -} - -ULONG __init -ArcGetRelativeTime(VOID) -{ - return ARC_CALL0(get_rtime); -} diff --git a/arch/mips/arc/tree.c b/arch/mips/arc/tree.c deleted file mode 100644 index abd1786..0000000 --- a/arch/mips/arc/tree.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * PROM component device tree code. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#include -#include -#include - -#undef DEBUG_PROM_TREE - -pcomponent * __init -ArcGetPeer(pcomponent *Current) -{ - if (Current == PROM_NULL_COMPONENT) - return PROM_NULL_COMPONENT; - - return (pcomponent *) ARC_CALL1(next_component, Current); -} - -pcomponent * __init -ArcGetChild(pcomponent *Current) -{ - return (pcomponent *) ARC_CALL1(child_component, Current); -} - -pcomponent * __init -ArcGetParent(pcomponent *Current) -{ - if (Current == PROM_NULL_COMPONENT) - return PROM_NULL_COMPONENT; - - return (pcomponent *) ARC_CALL1(parent_component, Current); -} - -LONG __init -ArcGetConfigurationData(VOID *Buffer, pcomponent *Current) -{ - return ARC_CALL2(component_data, Buffer, Current); -} - -pcomponent * __init -ArcAddChild(pcomponent *Current, pcomponent *Template, VOID *ConfigurationData) -{ - return (pcomponent *) - ARC_CALL3(child_add, Current, Template, ConfigurationData); -} - -LONG __init -ArcDeleteComponent(pcomponent *ComponentToDelete) -{ - return ARC_CALL1(comp_del, ComponentToDelete); -} - -pcomponent * __init -ArcGetComponent(CHAR *Path) -{ - return (pcomponent *)ARC_CALL1(component_by_path, Path); -} - -#ifdef DEBUG_PROM_TREE - -static char *classes[] = { - "system", "processor", "cache", "adapter", "controller", "peripheral", - "memory" -}; - -static char *types[] = { - "arc", "cpu", "fpu", "picache", "pdcache", "sicache", "sdcache", - "sccache", "memdev", "eisa adapter", "tc adapter", "scsi adapter", - "dti adapter", "multi-func adapter", "disk controller", - "tp controller", "cdrom controller", "worm controller", - "serial controller", "net controller", "display controller", - "parallel controller", "pointer controller", "keyboard controller", - "audio controller", "misc controller", "disk peripheral", - "floppy peripheral", "tp peripheral", "modem peripheral", - "monitor peripheral", "printer peripheral", "pointer peripheral", - "keyboard peripheral", "terminal peripheral", "line peripheral", - "net peripheral", "misc peripheral", "anonymous" -}; - -static char *iflags[] = { - "bogus", "read only", "removable", "console in", "console out", - "input", "output" -}; - -static void __init -dump_component(pcomponent *p) -{ - printk("[%p]:class<%s>type<%s>flags<%s>ver<%d>rev<%d>", - p, classes[p->class], types[p->type], - iflags[p->iflags], p->vers, p->rev); - printk("key<%08lx>\n\tamask<%08lx>cdsize<%d>ilen<%d>iname<%s>\n", - p->key, p->amask, (int)p->cdsize, (int)p->ilen, p->iname); -} - -static void __init -traverse(pcomponent *p, int op) -{ - dump_component(p); - if(ArcGetChild(p)) - traverse(ArcGetChild(p), 1); - if(ArcGetPeer(p) && op) - traverse(ArcGetPeer(p), 1); -} - -void __init -prom_testtree(void) -{ - pcomponent *p; - - p = ArcGetChild(PROM_NULL_COMPONENT); - dump_component(p); - p = ArcGetChild(p); - while(p) { - dump_component(p); - p = ArcGetPeer(p); - } -} - -#endif /* DEBUG_PROM_TREE */ diff --git a/arch/mips/fw/arc/Makefile b/arch/mips/fw/arc/Makefile new file mode 100644 index 0000000..4f349ec --- /dev/null +++ b/arch/mips/fw/arc/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the ARC prom monitor library routines under Linux. +# + +lib-y += cmdline.o env.o file.o identify.o init.o \ + misc.o salone.o time.o tree.o + +lib-$(CONFIG_ARC_MEMORY) += memory.o +lib-$(CONFIG_ARC_CONSOLE) += arc_con.o +lib-$(CONFIG_ARC_PROMLIB) += promlib.o diff --git a/arch/mips/fw/arc/arc_con.c b/arch/mips/fw/arc/arc_con.c new file mode 100644 index 0000000..bc32fe6 --- /dev/null +++ b/arch/mips/fw/arc/arc_con.c @@ -0,0 +1,50 @@ +/* + * Wrap-around code for a console using the + * ARC io-routines. + * + * Copyright (c) 1998 Harald Koerfgen + * Copyright (c) 2001 Ralf Baechle + * Copyright (c) 2002 Thiemo Seufer + */ +#include +#include +#include +#include +#include +#include + +static void prom_console_write(struct console *co, const char *s, + unsigned count) +{ + /* Do each character */ + while (count--) { + if (*s == '\n') + prom_putchar('\r'); + prom_putchar(*s++); + } +} + +static int prom_console_setup(struct console *co, char *options) +{ + return !(prom_flags & PROM_FLAG_USE_AS_CONSOLE); +} + +static struct console arc_cons = { + .name = "arc", + .write = prom_console_write, + .setup = prom_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, +}; + +/* + * Register console. + */ + +static int __init arc_console_init(void) +{ + register_console(&arc_cons); + + return 0; +} +console_initcall(arc_console_init); diff --git a/arch/mips/fw/arc/cmdline.c b/arch/mips/fw/arc/cmdline.c new file mode 100644 index 0000000..fd604ef --- /dev/null +++ b/arch/mips/fw/arc/cmdline.c @@ -0,0 +1,108 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * cmdline.c: Kernel command line creation using ARCS argc/argv. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + */ +#include +#include +#include + +#include +#include + +#undef DEBUG_CMDLINE + +char * __init prom_getcmdline(void) +{ + return arcs_cmdline; +} + +static char *ignored[] = { + "ConsoleIn=", + "ConsoleOut=", + "SystemPartition=", + "OSLoader=", + "OSLoadPartition=", + "OSLoadFilename=", + "OSLoadOptions=" +}; + +static char *used_arc[][2] = { + { "OSLoadPartition=", "root=" }, + { "OSLoadOptions=", "" } +}; + +static char * __init move_firmware_args(char* cp) +{ + char *s; + int actr, i; + + actr = 1; /* Always ignore argv[0] */ + + while (actr < prom_argc) { + for(i = 0; i < ARRAY_SIZE(used_arc); i++) { + int len = strlen(used_arc[i][0]); + + if (!strncmp(prom_argv(actr), used_arc[i][0], len)) { + /* Ok, we want it. First append the replacement... */ + strcat(cp, used_arc[i][1]); + cp += strlen(used_arc[i][1]); + /* ... and now the argument */ + s = strstr(prom_argv(actr), "="); + if (s) { + s++; + strcpy(cp, s); + cp += strlen(s); + } + *cp++ = ' '; + break; + } + } + actr++; + } + + return cp; +} + +void __init prom_init_cmdline(void) +{ + char *cp; + int actr, i; + + actr = 1; /* Always ignore argv[0] */ + + cp = arcs_cmdline; + /* + * Move ARC variables to the beginning to make sure they can be + * overridden by later arguments. + */ + cp = move_firmware_args(cp); + + while (actr < prom_argc) { + for (i = 0; i < ARRAY_SIZE(ignored); i++) { + int len = strlen(ignored[i]); + + if (!strncmp(prom_argv(actr), ignored[i], len)) + goto pic_cont; + } + /* Ok, we want it. */ + strcpy(cp, prom_argv(actr)); + cp += strlen(prom_argv(actr)); + *cp++ = ' '; + + pic_cont: + actr++; + } + + if (cp != arcs_cmdline) /* get rid of trailing space */ + --cp; + *cp = '\0'; + +#ifdef DEBUG_CMDLINE + printk(KERN_DEBUG "prom cmdline: %s\n", arcs_cmdline); +#endif +} diff --git a/arch/mips/fw/arc/env.c b/arch/mips/fw/arc/env.c new file mode 100644 index 0000000..6f5dd42 --- /dev/null +++ b/arch/mips/fw/arc/env.c @@ -0,0 +1,27 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * env.c: ARCS environment variable routines. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + */ +#include +#include +#include + +#include +#include + +PCHAR __init +ArcGetEnvironmentVariable(CHAR *name) +{ + return (CHAR *) ARC_CALL1(get_evar, name); +} + +LONG __init +ArcSetEnvironmentVariable(PCHAR name, PCHAR value) +{ + return ARC_CALL2(set_evar, name, value); +} diff --git a/arch/mips/fw/arc/file.c b/arch/mips/fw/arc/file.c new file mode 100644 index 0000000..3033534 --- /dev/null +++ b/arch/mips/fw/arc/file.c @@ -0,0 +1,75 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * ARC firmware interface. + * + * Copyright (C) 1994, 1995, 1996, 1999 Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + */ +#include + +#include +#include + +LONG +ArcGetDirectoryEntry(ULONG FileID, struct linux_vdirent *Buffer, + ULONG N, ULONG *Count) +{ + return ARC_CALL4(get_vdirent, FileID, Buffer, N, Count); +} + +LONG +ArcOpen(CHAR *Path, enum linux_omode OpenMode, ULONG *FileID) +{ + return ARC_CALL3(open, Path, OpenMode, FileID); +} + +LONG +ArcClose(ULONG FileID) +{ + return ARC_CALL1(close, FileID); +} + +LONG +ArcRead(ULONG FileID, VOID *Buffer, ULONG N, ULONG *Count) +{ + return ARC_CALL4(read, FileID, Buffer, N, Count); +} + +LONG +ArcGetReadStatus(ULONG FileID) +{ + return ARC_CALL1(get_rstatus, FileID); +} + +LONG +ArcWrite(ULONG FileID, PVOID Buffer, ULONG N, PULONG Count) +{ + return ARC_CALL4(write, FileID, Buffer, N, Count); +} + +LONG +ArcSeek(ULONG FileID, struct linux_bigint *Position, enum linux_seekmode SeekMode) +{ + return ARC_CALL3(seek, FileID, Position, SeekMode); +} + +LONG +ArcMount(char *name, enum linux_mountops op) +{ + return ARC_CALL2(mount, name, op); +} + +LONG +ArcGetFileInformation(ULONG FileID, struct linux_finfo *Information) +{ + return ARC_CALL2(get_finfo, FileID, Information); +} + +LONG ArcSetFileInformation(ULONG FileID, ULONG AttributeFlags, + ULONG AttributeMask) +{ + return ARC_CALL3(set_finfo, FileID, AttributeFlags, AttributeMask); +} diff --git a/arch/mips/fw/arc/identify.c b/arch/mips/fw/arc/identify.c new file mode 100644 index 0000000..4b90736 --- /dev/null +++ b/arch/mips/fw/arc/identify.c @@ -0,0 +1,123 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * identify.c: identify machine by looking up system identifier + * + * Copyright (C) 1998 Thomas Bogendoerfer + * + * This code is based on arch/mips/sgi/kernel/system.c, which is + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + */ +#include +#include +#include +#include + +#include +#include + +struct smatch { + char *arcname; + char *liname; + int group; + int type; + int flags; +}; + +static struct smatch mach_table[] = { + { "SGI-IP22", + "SGI Indy", + MACH_GROUP_SGI, + MACH_SGI_IP22, + PROM_FLAG_ARCS + }, { "SGI-IP27", + "SGI Origin", + MACH_GROUP_SGI, + MACH_SGI_IP27, + PROM_FLAG_ARCS + }, { "SGI-IP28", + "SGI IP28", + MACH_GROUP_SGI, + MACH_SGI_IP28, + PROM_FLAG_ARCS + }, { "SGI-IP30", + "SGI Octane", + MACH_GROUP_SGI, + MACH_SGI_IP30, + PROM_FLAG_ARCS + }, { "SGI-IP32", + "SGI O2", + MACH_GROUP_SGI, + MACH_SGI_IP32, + PROM_FLAG_ARCS + }, { "Microsoft-Jazz", + "Jazz MIPS_Magnum_4000", + MACH_GROUP_JAZZ, + MACH_MIPS_MAGNUM_4000, + 0 + }, { "PICA-61", + "Jazz Acer_PICA_61", + MACH_GROUP_JAZZ, + MACH_ACER_PICA_61, + 0 + }, { "RM200PCI", + "SNI RM200_PCI", + MACH_GROUP_SNI_RM, + MACH_SNI_RM200_PCI, + PROM_FLAG_DONT_FREE_TEMP + } +}; + +int prom_flags; + +static struct smatch * __init string_to_mach(const char *s) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mach_table); i++) { + if (!strcmp(s, mach_table[i].arcname)) + return &mach_table[i]; + } + + panic("Yeee, could not determine architecture type <%s>", s); +} + +char *system_type; + +const char *get_system_type(void) +{ + return system_type; +} + +void __init prom_identify_arch(void) +{ + pcomponent *p; + struct smatch *mach; + const char *iname; + + /* + * The root component tells us what machine architecture we have here. + */ + p = ArcGetChild(PROM_NULL_COMPONENT); + if (p == NULL) { +#ifdef CONFIG_SGI_IP27 + /* IP27 PROM misbehaves, seems to not implement ARC + GetChild(). So we just assume it's an IP27. */ + iname = "SGI-IP27"; +#else + iname = "Unknown"; +#endif + } else + iname = (char *) (long) p->iname; + + printk("ARCH: %s\n", iname); + mach = string_to_mach(iname); + system_type = mach->liname; + + mips_machgroup = mach->group; + mips_machtype = mach->type; + prom_flags = mach->flags; +} diff --git a/arch/mips/fw/arc/init.c b/arch/mips/fw/arc/init.c new file mode 100644 index 0000000..e2f75b1 --- /dev/null +++ b/arch/mips/fw/arc/init.c @@ -0,0 +1,51 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * PROM library initialisation code. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + */ +#include +#include + +#include +#include + +#undef DEBUG_PROM_INIT + +/* Master romvec interface. */ +struct linux_romvec *romvec; +int prom_argc; +LONG *_prom_argv, *_prom_envp; + +void __init prom_init(void) +{ + PSYSTEM_PARAMETER_BLOCK pb = PROMBLOCK; + + romvec = ROMVECTOR; + + prom_argc = fw_arg0; + _prom_argv = (LONG *) fw_arg1; + _prom_envp = (LONG *) fw_arg2; + + if (pb->magic != 0x53435241) { + printk(KERN_CRIT "Aieee, bad prom vector magic %08lx\n", + (unsigned long) pb->magic); + while(1) + ; + } + + prom_init_cmdline(); + prom_identify_arch(); + printk(KERN_INFO "PROMLIB: ARC firmware Version %d Revision %d\n", + pb->ver, pb->rev); + prom_meminit(); + +#ifdef DEBUG_PROM_INIT + pr_info("Press a key to reboot\n"); + ArcRead(0, &c, 1, &cnt); + ArcEnterInteractiveMode(); +#endif +} diff --git a/arch/mips/fw/arc/memory.c b/arch/mips/fw/arc/memory.c new file mode 100644 index 0000000..83d1579 --- /dev/null +++ b/arch/mips/fw/arc/memory.c @@ -0,0 +1,160 @@ +/* + * memory.c: PROM library functions for acquiring/using memory descriptors + * given to us from the ARCS firmware. + * + * Copyright (C) 1996 by David S. Miller + * Copyright (C) 1999, 2000, 2001 by Ralf Baechle + * Copyright (C) 1999, 2000 by Silicon Graphics, Inc. + * + * PROM library functions for acquiring/using memory descriptors given to us + * from the ARCS firmware. This is only used when CONFIG_ARC_MEMORY is set + * because on some machines like SGI IP27 the ARC memory configuration data + * completly bogus and alternate easier to use mechanisms are available. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#undef DEBUG + +/* + * For ARC firmware memory functions the unit of meassuring memory is always + * a 4k page of memory + */ +#define ARC_PAGE_SHIFT 12 + +struct linux_mdesc * __init ArcGetMemoryDescriptor(struct linux_mdesc *Current) +{ + return (struct linux_mdesc *) ARC_CALL1(get_mdesc, Current); +} + +#ifdef DEBUG /* convenient for debugging */ +static char *arcs_mtypes[8] = { + "Exception Block", + "ARCS Romvec Page", + "Free/Contig RAM", + "Generic Free RAM", + "Bad Memory", + "Standalone Program Pages", + "ARCS Temp Storage Area", + "ARCS Permanent Storage Area" +}; + +static char *arc_mtypes[8] = { + "Exception Block", + "SystemParameterBlock", + "FreeMemory", + "Bad Memory", + "LoadedProgram", + "FirmwareTemporary", + "FirmwarePermanent", + "FreeContiguous" +}; +#define mtypes(a) (prom_flags & PROM_FLAG_ARCS) ? arcs_mtypes[a.arcs] \ + : arc_mtypes[a.arc] +#endif + +static inline int memtype_classify_arcs (union linux_memtypes type) +{ + switch (type.arcs) { + case arcs_fcontig: + case arcs_free: + return BOOT_MEM_RAM; + case arcs_atmp: + return BOOT_MEM_ROM_DATA; + case arcs_eblock: + case arcs_rvpage: + case arcs_bmem: + case arcs_prog: + case arcs_aperm: + return BOOT_MEM_RESERVED; + default: + BUG(); + } + while(1); /* Nuke warning. */ +} + +static inline int memtype_classify_arc (union linux_memtypes type) +{ + switch (type.arc) { + case arc_free: + case arc_fcontig: + return BOOT_MEM_RAM; + case arc_atmp: + return BOOT_MEM_ROM_DATA; + case arc_eblock: + case arc_rvpage: + case arc_bmem: + case arc_prog: + case arc_aperm: + return BOOT_MEM_RESERVED; + default: + BUG(); + } + while(1); /* Nuke warning. */ +} + +static int __init prom_memtype_classify (union linux_memtypes type) +{ + if (prom_flags & PROM_FLAG_ARCS) /* SGI is ``different'' ... */ + return memtype_classify_arcs(type); + + return memtype_classify_arc(type); +} + +void __init prom_meminit(void) +{ + struct linux_mdesc *p; + +#ifdef DEBUG + int i = 0; + + printk("ARCS MEMORY DESCRIPTOR dump:\n"); + p = ArcGetMemoryDescriptor(PROM_NULL_MDESC); + while(p) { + printk("[%d,%p]: base<%08lx> pages<%08lx> type<%s>\n", + i, p, p->base, p->pages, mtypes(p->type)); + p = ArcGetMemoryDescriptor(p); + i++; + } +#endif + + p = PROM_NULL_MDESC; + while ((p = ArcGetMemoryDescriptor(p))) { + unsigned long base, size; + long type; + + base = p->base << ARC_PAGE_SHIFT; + size = p->pages << ARC_PAGE_SHIFT; + type = prom_memtype_classify(p->type); + + add_memory_region(base, size, type); + } +} + +void __init prom_free_prom_memory(void) +{ + unsigned long addr; + int i; + + if (prom_flags & PROM_FLAG_DONT_FREE_TEMP) + return; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) + continue; + + addr = boot_mem_map.map[i].addr; + free_init_pages("prom memory", + addr, addr + boot_mem_map.map[i].size); + } +} diff --git a/arch/mips/fw/arc/misc.c b/arch/mips/fw/arc/misc.c new file mode 100644 index 0000000..e527c5f --- /dev/null +++ b/arch/mips/fw/arc/misc.c @@ -0,0 +1,89 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Miscellaneous ARCS PROM routines. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999 Silicon Graphics, Inc. + */ +#include +#include + +#include + +#include +#include +#include +#include + +VOID +ArcHalt(VOID) +{ + bc_disable(); + local_irq_disable(); + ARC_CALL0(halt); +never: goto never; +} + +VOID +ArcPowerDown(VOID) +{ + bc_disable(); + local_irq_disable(); + ARC_CALL0(pdown); +never: goto never; +} + +/* XXX is this a soft reset basically? XXX */ +VOID +ArcRestart(VOID) +{ + bc_disable(); + local_irq_disable(); + ARC_CALL0(restart); +never: goto never; +} + +VOID +ArcReboot(VOID) +{ + bc_disable(); + local_irq_disable(); + ARC_CALL0(reboot); +never: goto never; +} + +VOID +ArcEnterInteractiveMode(VOID) +{ + bc_disable(); + local_irq_disable(); + ARC_CALL0(imode); +never: goto never; +} + +LONG +ArcSaveConfiguration(VOID) +{ + return ARC_CALL0(cfg_save); +} + +struct linux_sysid * +ArcGetSystemId(VOID) +{ + return (struct linux_sysid *) ARC_CALL0(get_sysid); +} + +VOID __init +ArcFlushAllCaches(VOID) +{ + ARC_CALL0(cache_flush); +} + +DISPLAY_STATUS * __init ArcGetDisplayStatus(ULONG FileID) +{ + return (DISPLAY_STATUS *) ARC_CALL1(GetDisplayStatus, FileID); +} diff --git a/arch/mips/fw/arc/promlib.c b/arch/mips/fw/arc/promlib.c new file mode 100644 index 0000000..c508c00 --- /dev/null +++ b/arch/mips/fw/arc/promlib.c @@ -0,0 +1,43 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 David S. Miller (dm@sgi.com) + * Compability with board caches, Ulf Carlsson + */ +#include +#include +#include + +/* + * IP22 boardcache is not compatible with board caches. Thus we disable it + * during romvec action. Since r4xx0.c is always compiled and linked with your + * kernel, this shouldn't cause any harm regardless what MIPS processor you + * have. + * + * The ARC write and read functions seem to interfere with the serial lines + * in some way. You should be careful with them. + */ + +void prom_putchar(char c) +{ + ULONG cnt; + CHAR it = c; + + bc_disable(); + ArcWrite(1, &it, 1, &cnt); + bc_enable(); +} + +char prom_getchar(void) +{ + ULONG cnt; + CHAR c; + + bc_disable(); + ArcRead(0, &c, 1, &cnt); + bc_enable(); + + return c; +} diff --git a/arch/mips/fw/arc/salone.c b/arch/mips/fw/arc/salone.c new file mode 100644 index 0000000..e6afb64 --- /dev/null +++ b/arch/mips/fw/arc/salone.c @@ -0,0 +1,24 @@ +/* + * Routines to load into memory and execute stand-along program images using + * ARCS PROM firmware. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + */ +#include +#include + +LONG __init ArcLoad(CHAR *Path, ULONG TopAddr, ULONG *ExecAddr, ULONG *LowAddr) +{ + return ARC_CALL4(load, Path, TopAddr, ExecAddr, LowAddr); +} + +LONG __init ArcInvoke(ULONG ExecAddr, ULONG StackAddr, ULONG Argc, CHAR *Argv[], + CHAR *Envp[]) +{ + return ARC_CALL5(invoke, ExecAddr, StackAddr, Argc, Argv, Envp); +} + +LONG __init ArcExecute(CHAR *Path, LONG Argc, CHAR *Argv[], CHAR *Envp[]) +{ + return ARC_CALL4(exec, Path, Argc, Argv, Envp); +} diff --git a/arch/mips/fw/arc/time.c b/arch/mips/fw/arc/time.c new file mode 100644 index 0000000..42138c8 --- /dev/null +++ b/arch/mips/fw/arc/time.c @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Extracting time information from ARCS prom. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + */ +#include + +#include +#include + +struct linux_tinfo * __init +ArcGetTime(VOID) +{ + return (struct linux_tinfo *) ARC_CALL0(get_tinfo); +} + +ULONG __init +ArcGetRelativeTime(VOID) +{ + return ARC_CALL0(get_rtime); +} diff --git a/arch/mips/fw/arc/tree.c b/arch/mips/fw/arc/tree.c new file mode 100644 index 0000000..d68e5a5 --- /dev/null +++ b/arch/mips/fw/arc/tree.c @@ -0,0 +1,127 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * PROM component device tree code. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999 Silicon Graphics, Inc. + */ +#include +#include +#include + +#undef DEBUG_PROM_TREE + +pcomponent * __init +ArcGetPeer(pcomponent *Current) +{ + if (Current == PROM_NULL_COMPONENT) + return PROM_NULL_COMPONENT; + + return (pcomponent *) ARC_CALL1(next_component, Current); +} + +pcomponent * __init +ArcGetChild(pcomponent *Current) +{ + return (pcomponent *) ARC_CALL1(child_component, Current); +} + +pcomponent * __init +ArcGetParent(pcomponent *Current) +{ + if (Current == PROM_NULL_COMPONENT) + return PROM_NULL_COMPONENT; + + return (pcomponent *) ARC_CALL1(parent_component, Current); +} + +LONG __init +ArcGetConfigurationData(VOID *Buffer, pcomponent *Current) +{ + return ARC_CALL2(component_data, Buffer, Current); +} + +pcomponent * __init +ArcAddChild(pcomponent *Current, pcomponent *Template, VOID *ConfigurationData) +{ + return (pcomponent *) + ARC_CALL3(child_add, Current, Template, ConfigurationData); +} + +LONG __init +ArcDeleteComponent(pcomponent *ComponentToDelete) +{ + return ARC_CALL1(comp_del, ComponentToDelete); +} + +pcomponent * __init +ArcGetComponent(CHAR *Path) +{ + return (pcomponent *)ARC_CALL1(component_by_path, Path); +} + +#ifdef DEBUG_PROM_TREE + +static char *classes[] = { + "system", "processor", "cache", "adapter", "controller", "peripheral", + "memory" +}; + +static char *types[] = { + "arc", "cpu", "fpu", "picache", "pdcache", "sicache", "sdcache", + "sccache", "memdev", "eisa adapter", "tc adapter", "scsi adapter", + "dti adapter", "multi-func adapter", "disk controller", + "tp controller", "cdrom controller", "worm controller", + "serial controller", "net controller", "display controller", + "parallel controller", "pointer controller", "keyboard controller", + "audio controller", "misc controller", "disk peripheral", + "floppy peripheral", "tp peripheral", "modem peripheral", + "monitor peripheral", "printer peripheral", "pointer peripheral", + "keyboard peripheral", "terminal peripheral", "line peripheral", + "net peripheral", "misc peripheral", "anonymous" +}; + +static char *iflags[] = { + "bogus", "read only", "removable", "console in", "console out", + "input", "output" +}; + +static void __init +dump_component(pcomponent *p) +{ + printk("[%p]:class<%s>type<%s>flags<%s>ver<%d>rev<%d>", + p, classes[p->class], types[p->type], + iflags[p->iflags], p->vers, p->rev); + printk("key<%08lx>\n\tamask<%08lx>cdsize<%d>ilen<%d>iname<%s>\n", + p->key, p->amask, (int)p->cdsize, (int)p->ilen, p->iname); +} + +static void __init +traverse(pcomponent *p, int op) +{ + dump_component(p); + if(ArcGetChild(p)) + traverse(ArcGetChild(p), 1); + if(ArcGetPeer(p) && op) + traverse(ArcGetPeer(p), 1); +} + +void __init +prom_testtree(void) +{ + pcomponent *p; + + p = ArcGetChild(PROM_NULL_COMPONENT); + dump_component(p); + p = ArcGetChild(p); + while(p) { + dump_component(p); + p = ArcGetPeer(p); + } +} + +#endif /* DEBUG_PROM_TREE */ diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c index 6edbb30..883e35e 100644 --- a/arch/mips/sni/setup.c +++ b/arch/mips/sni/setup.c @@ -15,7 +15,7 @@ #include #ifdef CONFIG_ARC -#include +#include #include #endif diff --git a/include/asm-mips/arc/hinv.h b/include/asm-mips/arc/hinv.h deleted file mode 100644 index 1862912..0000000 --- a/include/asm-mips/arc/hinv.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * ARCS hardware/memory inventory/configuration and system ID definitions. - */ -#ifndef _ASM_ARC_HINV_H -#define _ASM_ARC_HINV_H - -#include -#include - -/* configuration query defines */ -typedef enum configclass { - SystemClass, - ProcessorClass, - CacheClass, -#ifndef _NT_PROM - MemoryClass, - AdapterClass, - ControllerClass, - PeripheralClass -#else /* _NT_PROM */ - AdapterClass, - ControllerClass, - PeripheralClass, - MemoryClass -#endif /* _NT_PROM */ -} CONFIGCLASS; - -typedef enum configtype { - ARC, - CPU, - FPU, - PrimaryICache, - PrimaryDCache, - SecondaryICache, - SecondaryDCache, - SecondaryCache, -#ifndef _NT_PROM - Memory, -#endif - EISAAdapter, - TCAdapter, - SCSIAdapter, - DTIAdapter, - MultiFunctionAdapter, - DiskController, - TapeController, - CDROMController, - WORMController, - SerialController, - NetworkController, - DisplayController, - ParallelController, - PointerController, - KeyboardController, - AudioController, - OtherController, - DiskPeripheral, - FloppyDiskPeripheral, - TapePeripheral, - ModemPeripheral, - MonitorPeripheral, - PrinterPeripheral, - PointerPeripheral, - KeyboardPeripheral, - TerminalPeripheral, - LinePeripheral, - NetworkPeripheral, -#ifdef _NT_PROM - Memory, -#endif - OtherPeripheral, - - /* new stuff for IP30 */ - /* added without moving anything */ - /* except ANONYMOUS. */ - - XTalkAdapter, - PCIAdapter, - GIOAdapter, - TPUAdapter, - - Anonymous -} CONFIGTYPE; - -typedef enum { - Failed = 1, - ReadOnly = 2, - Removable = 4, - ConsoleIn = 8, - ConsoleOut = 16, - Input = 32, - Output = 64 -} IDENTIFIERFLAG; - -#ifndef NULL /* for GetChild(NULL); */ -#define NULL 0 -#endif - -union key_u { - struct { -#ifdef _MIPSEB - unsigned char c_bsize; /* block size in lines */ - unsigned char c_lsize; /* line size in bytes/tag */ - unsigned short c_size; /* cache size in 4K pages */ -#else /* _MIPSEL */ - unsigned short c_size; /* cache size in 4K pages */ - unsigned char c_lsize; /* line size in bytes/tag */ - unsigned char c_bsize; /* block size in lines */ -#endif /* _MIPSEL */ - } cache; - ULONG FullKey; -}; - -#if _MIPS_SIM == _MIPS_SIM_ABI64 -#define SGI_ARCS_VERS 64 /* sgi 64-bit version */ -#define SGI_ARCS_REV 0 /* rev .00 */ -#else -#define SGI_ARCS_VERS 1 /* first version */ -#define SGI_ARCS_REV 10 /* rev .10, 3/04/92 */ -#endif - -typedef struct component { - CONFIGCLASS Class; - CONFIGTYPE Type; - IDENTIFIERFLAG Flags; - USHORT Version; - USHORT Revision; - ULONG Key; - ULONG AffinityMask; - ULONG ConfigurationDataSize; - ULONG IdentifierLength; - char *Identifier; -} COMPONENT; - -/* internal structure that holds pathname parsing data */ -struct cfgdata { - char *name; /* full name */ - int minlen; /* minimum length to match */ - CONFIGTYPE type; /* type of token */ -}; - -/* System ID */ -typedef struct systemid { - CHAR VendorId[8]; - CHAR ProductId[8]; -} SYSTEMID; - -/* memory query functions */ -typedef enum memorytype { - ExceptionBlock, - SPBPage, /* ARCS == SystemParameterBlock */ -#ifndef _NT_PROM - FreeContiguous, - FreeMemory, - BadMemory, - LoadedProgram, - FirmwareTemporary, - FirmwarePermanent -#else /* _NT_PROM */ - FreeMemory, - BadMemory, - LoadedProgram, - FirmwareTemporary, - FirmwarePermanent, - FreeContiguous -#endif /* _NT_PROM */ -} MEMORYTYPE; - -typedef struct memorydescriptor { - MEMORYTYPE Type; - LONG BasePage; - LONG PageCount; -} MEMORYDESCRIPTOR; - -#endif /* _ASM_ARC_HINV_H */ diff --git a/include/asm-mips/arc/types.h b/include/asm-mips/arc/types.h deleted file mode 100644 index b9adcd6..0000000 --- a/include/asm-mips/arc/types.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright 1999 Ralf Baechle (ralf@gnu.org) - * Copyright 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_ARC_TYPES_H -#define _ASM_ARC_TYPES_H - - -#ifdef CONFIG_ARC32 - -typedef char CHAR; -typedef short SHORT; -typedef long LARGE_INTEGER __attribute__ ((__mode__ (__DI__))); -typedef long LONG __attribute__ ((__mode__ (__SI__))); -typedef unsigned char UCHAR; -typedef unsigned short USHORT; -typedef unsigned long ULONG __attribute__ ((__mode__ (__SI__))); -typedef void VOID; - -/* The pointer types. Note that we're using a 64-bit compiler but all - pointer in the ARC structures are only 32-bit, so we need some disgusting - workarounds. Keep your vomit bag handy. */ -typedef LONG _PCHAR; -typedef LONG _PSHORT; -typedef LONG _PLARGE_INTEGER; -typedef LONG _PLONG; -typedef LONG _PUCHAR; -typedef LONG _PUSHORT; -typedef LONG _PULONG; -typedef LONG _PVOID; - -#endif /* CONFIG_ARC32 */ - -#ifdef CONFIG_ARC64 - -typedef char CHAR; -typedef short SHORT; -typedef long LARGE_INTEGER __attribute__ ((__mode__ (__DI__))); -typedef long LONG __attribute__ ((__mode__ (__DI__))); -typedef unsigned char UCHAR; -typedef unsigned short USHORT; -typedef unsigned long ULONG __attribute__ ((__mode__ (__DI__))); -typedef void VOID; - -/* The pointer types. We're 64-bit and the firmware is also 64-bit, so - live is sane ... */ -typedef CHAR *_PCHAR; -typedef SHORT *_PSHORT; -typedef LARGE_INTEGER *_PLARGE_INTEGER; -typedef LONG *_PLONG; -typedef UCHAR *_PUCHAR; -typedef USHORT *_PUSHORT; -typedef ULONG *_PULONG; -typedef VOID *_PVOID; - -#endif /* CONFIG_ARC64 */ - -typedef CHAR *PCHAR; -typedef SHORT *PSHORT; -typedef LARGE_INTEGER *PLARGE_INTEGER; -typedef LONG *PLONG; -typedef UCHAR *PUCHAR; -typedef USHORT *PUSHORT; -typedef ULONG *PULONG; -typedef VOID *PVOID; - -/* - * Return type of ArcGetDisplayStatus() - */ -typedef struct { - USHORT CursorXPosition; - USHORT CursorYPosition; - USHORT CursorMaxXPosition; - USHORT CursorMaxYPosition; - USHORT ForegroundColor; - USHORT BackgroundColor; - UCHAR HighIntensity; - UCHAR Underscored; - UCHAR ReverseVideo; -} DISPLAY_STATUS; - -#endif /* _ASM_ARC_TYPES_H */ diff --git a/include/asm-mips/fw/arc/hinv.h b/include/asm-mips/fw/arc/hinv.h new file mode 100644 index 0000000..e6ff4ad --- /dev/null +++ b/include/asm-mips/fw/arc/hinv.h @@ -0,0 +1,175 @@ +/* + * ARCS hardware/memory inventory/configuration and system ID definitions. + */ +#ifndef _ASM_ARC_HINV_H +#define _ASM_ARC_HINV_H + +#include +#include + +/* configuration query defines */ +typedef enum configclass { + SystemClass, + ProcessorClass, + CacheClass, +#ifndef _NT_PROM + MemoryClass, + AdapterClass, + ControllerClass, + PeripheralClass +#else /* _NT_PROM */ + AdapterClass, + ControllerClass, + PeripheralClass, + MemoryClass +#endif /* _NT_PROM */ +} CONFIGCLASS; + +typedef enum configtype { + ARC, + CPU, + FPU, + PrimaryICache, + PrimaryDCache, + SecondaryICache, + SecondaryDCache, + SecondaryCache, +#ifndef _NT_PROM + Memory, +#endif + EISAAdapter, + TCAdapter, + SCSIAdapter, + DTIAdapter, + MultiFunctionAdapter, + DiskController, + TapeController, + CDROMController, + WORMController, + SerialController, + NetworkController, + DisplayController, + ParallelController, + PointerController, + KeyboardController, + AudioController, + OtherController, + DiskPeripheral, + FloppyDiskPeripheral, + TapePeripheral, + ModemPeripheral, + MonitorPeripheral, + PrinterPeripheral, + PointerPeripheral, + KeyboardPeripheral, + TerminalPeripheral, + LinePeripheral, + NetworkPeripheral, +#ifdef _NT_PROM + Memory, +#endif + OtherPeripheral, + + /* new stuff for IP30 */ + /* added without moving anything */ + /* except ANONYMOUS. */ + + XTalkAdapter, + PCIAdapter, + GIOAdapter, + TPUAdapter, + + Anonymous +} CONFIGTYPE; + +typedef enum { + Failed = 1, + ReadOnly = 2, + Removable = 4, + ConsoleIn = 8, + ConsoleOut = 16, + Input = 32, + Output = 64 +} IDENTIFIERFLAG; + +#ifndef NULL /* for GetChild(NULL); */ +#define NULL 0 +#endif + +union key_u { + struct { +#ifdef _MIPSEB + unsigned char c_bsize; /* block size in lines */ + unsigned char c_lsize; /* line size in bytes/tag */ + unsigned short c_size; /* cache size in 4K pages */ +#else /* _MIPSEL */ + unsigned short c_size; /* cache size in 4K pages */ + unsigned char c_lsize; /* line size in bytes/tag */ + unsigned char c_bsize; /* block size in lines */ +#endif /* _MIPSEL */ + } cache; + ULONG FullKey; +}; + +#if _MIPS_SIM == _MIPS_SIM_ABI64 +#define SGI_ARCS_VERS 64 /* sgi 64-bit version */ +#define SGI_ARCS_REV 0 /* rev .00 */ +#else +#define SGI_ARCS_VERS 1 /* first version */ +#define SGI_ARCS_REV 10 /* rev .10, 3/04/92 */ +#endif + +typedef struct component { + CONFIGCLASS Class; + CONFIGTYPE Type; + IDENTIFIERFLAG Flags; + USHORT Version; + USHORT Revision; + ULONG Key; + ULONG AffinityMask; + ULONG ConfigurationDataSize; + ULONG IdentifierLength; + char *Identifier; +} COMPONENT; + +/* internal structure that holds pathname parsing data */ +struct cfgdata { + char *name; /* full name */ + int minlen; /* minimum length to match */ + CONFIGTYPE type; /* type of token */ +}; + +/* System ID */ +typedef struct systemid { + CHAR VendorId[8]; + CHAR ProductId[8]; +} SYSTEMID; + +/* memory query functions */ +typedef enum memorytype { + ExceptionBlock, + SPBPage, /* ARCS == SystemParameterBlock */ +#ifndef _NT_PROM + FreeContiguous, + FreeMemory, + BadMemory, + LoadedProgram, + FirmwareTemporary, + FirmwarePermanent +#else /* _NT_PROM */ + FreeMemory, + BadMemory, + LoadedProgram, + FirmwareTemporary, + FirmwarePermanent, + FreeContiguous +#endif /* _NT_PROM */ +} MEMORYTYPE; + +typedef struct memorydescriptor { + MEMORYTYPE Type; + LONG BasePage; + LONG PageCount; +} MEMORYDESCRIPTOR; + +#endif /* _ASM_ARC_HINV_H */ diff --git a/include/asm-mips/fw/arc/types.h b/include/asm-mips/fw/arc/types.h new file mode 100644 index 0000000..b9adcd6 --- /dev/null +++ b/include/asm-mips/fw/arc/types.h @@ -0,0 +1,86 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright 1999 Ralf Baechle (ralf@gnu.org) + * Copyright 1999 Silicon Graphics, Inc. + */ +#ifndef _ASM_ARC_TYPES_H +#define _ASM_ARC_TYPES_H + + +#ifdef CONFIG_ARC32 + +typedef char CHAR; +typedef short SHORT; +typedef long LARGE_INTEGER __attribute__ ((__mode__ (__DI__))); +typedef long LONG __attribute__ ((__mode__ (__SI__))); +typedef unsigned char UCHAR; +typedef unsigned short USHORT; +typedef unsigned long ULONG __attribute__ ((__mode__ (__SI__))); +typedef void VOID; + +/* The pointer types. Note that we're using a 64-bit compiler but all + pointer in the ARC structures are only 32-bit, so we need some disgusting + workarounds. Keep your vomit bag handy. */ +typedef LONG _PCHAR; +typedef LONG _PSHORT; +typedef LONG _PLARGE_INTEGER; +typedef LONG _PLONG; +typedef LONG _PUCHAR; +typedef LONG _PUSHORT; +typedef LONG _PULONG; +typedef LONG _PVOID; + +#endif /* CONFIG_ARC32 */ + +#ifdef CONFIG_ARC64 + +typedef char CHAR; +typedef short SHORT; +typedef long LARGE_INTEGER __attribute__ ((__mode__ (__DI__))); +typedef long LONG __attribute__ ((__mode__ (__DI__))); +typedef unsigned char UCHAR; +typedef unsigned short USHORT; +typedef unsigned long ULONG __attribute__ ((__mode__ (__DI__))); +typedef void VOID; + +/* The pointer types. We're 64-bit and the firmware is also 64-bit, so + live is sane ... */ +typedef CHAR *_PCHAR; +typedef SHORT *_PSHORT; +typedef LARGE_INTEGER *_PLARGE_INTEGER; +typedef LONG *_PLONG; +typedef UCHAR *_PUCHAR; +typedef USHORT *_PUSHORT; +typedef ULONG *_PULONG; +typedef VOID *_PVOID; + +#endif /* CONFIG_ARC64 */ + +typedef CHAR *PCHAR; +typedef SHORT *PSHORT; +typedef LARGE_INTEGER *PLARGE_INTEGER; +typedef LONG *PLONG; +typedef UCHAR *PUCHAR; +typedef USHORT *PUSHORT; +typedef ULONG *PULONG; +typedef VOID *PVOID; + +/* + * Return type of ArcGetDisplayStatus() + */ +typedef struct { + USHORT CursorXPosition; + USHORT CursorYPosition; + USHORT CursorMaxXPosition; + USHORT CursorMaxYPosition; + USHORT ForegroundColor; + USHORT BackgroundColor; + UCHAR HighIntensity; + UCHAR Underscored; + UCHAR ReverseVideo; +} DISPLAY_STATUS; + +#endif /* _ASM_ARC_TYPES_H */ diff --git a/include/asm-mips/sgiarcs.h b/include/asm-mips/sgiarcs.h index 439bce7..6d1eda6 100644 --- a/include/asm-mips/sgiarcs.h +++ b/include/asm-mips/sgiarcs.h @@ -13,7 +13,7 @@ #define _ASM_SGIARCS_H #include -#include +#include /* Various ARCS error codes. */ #define PROM_ESUCCESS 0x00 diff --git a/include/asm-mips/sn/klconfig.h b/include/asm-mips/sn/klconfig.h index 82aeb9e..852213d 100644 --- a/include/asm-mips/sn/klconfig.h +++ b/include/asm-mips/sn/klconfig.h @@ -51,8 +51,8 @@ #if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP35) #include -#include -#include +#include +#include #if defined(CONFIG_SGI_IP35) // The hack file has to be before vector and after sn0_fru.... #include -- cgit v0.10.2 From 25e5fb97419f73d39b37e9f73f9492c394de07b2 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 25 Sep 2007 15:41:24 +0200 Subject: [MIPS] Add CFE support to BCM47XX Add CFE support to the BCM47XX code. That includes querying CFE environment variables as well as using CFE to print messages before the serial port is initialized (early printk). Signed-off-by: Aurelien Jarno Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 4863494..371434d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -55,6 +55,8 @@ config BCM47XX select SSB select SSB_DRIVER_MIPS select GENERIC_GPIO + select SYS_HAS_EARLY_PRINTK + select CFE help Support for BCM47XX based boards diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c index 41ac9dd..079e33d 100644 --- a/arch/mips/bcm47xx/prom.c +++ b/arch/mips/bcm47xx/prom.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2004 Florian Schirmer + * Copyright (C) 2007 Aurelien Jarno * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -23,18 +24,117 @@ */ #include +#include +#include +#include #include +#include +#include + +static int cfe_cons_handle; const char *get_system_type(void) { return "Broadcom BCM47XX"; } -void __init prom_init(void) +void prom_putchar(char c) +{ + while (cfe_write(cfe_cons_handle, &c, 1) == 0) + ; +} + +static __init void prom_init_cfe(void) +{ + uint32_t cfe_ept; + uint32_t cfe_handle; + uint32_t cfe_eptseal; + int argc = fw_arg0; + char **envp = (char **) fw_arg2; + int *prom_vec = (int *) fw_arg3; + + /* + * Check if a loader was used; if NOT, the 4 arguments are + * what CFE gives us (handle, 0, EPT and EPTSEAL) + */ + if (argc < 0) { + cfe_handle = (uint32_t)argc; + cfe_ept = (uint32_t)envp; + cfe_eptseal = (uint32_t)prom_vec; + } else { + if ((int)prom_vec < 0) { + /* + * Old loader; all it gives us is the handle, + * so use the "known" entrypoint and assume + * the seal. + */ + cfe_handle = (uint32_t)prom_vec; + cfe_ept = 0xBFC00500; + cfe_eptseal = CFE_EPTSEAL; + } else { + /* + * Newer loaders bundle the handle/ept/eptseal + * Note: prom_vec is in the loader's useg + * which is still alive in the TLB. + */ + cfe_handle = prom_vec[0]; + cfe_ept = prom_vec[2]; + cfe_eptseal = prom_vec[3]; + } + } + + if (cfe_eptseal != CFE_EPTSEAL) { + /* too early for panic to do any good */ + printk(KERN_ERR "CFE's entrypoint seal doesn't match."); + while (1) ; + } + + cfe_init(cfe_handle, cfe_ept); +} + +static __init void prom_init_console(void) +{ + /* Initialize CFE console */ + cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE); +} + +static __init void prom_init_cmdline(void) +{ + char buf[CL_SIZE]; + + /* Get the kernel command line from CFE */ + if (cfe_getenv("LINUX_CMDLINE", buf, CL_SIZE) >= 0) { + buf[CL_SIZE-1] = 0; + strcpy(arcs_cmdline, buf); + } + + /* Force a console handover by adding a console= argument if needed, + * as CFE is not available anymore later in the boot process. */ + if ((strstr(arcs_cmdline, "console=")) == NULL) { + /* Try to read the default serial port used by CFE */ + if ((cfe_getenv("BOOT_CONSOLE", buf, CL_SIZE) < 0) + || (strncmp("uart", buf, 4))) + /* Default to uart0 */ + strcpy(buf, "uart0"); + + /* Compute the new command line */ + snprintf(arcs_cmdline, CL_SIZE, "%s console=ttyS%c,115200", + arcs_cmdline, buf[4]); + } +} + +static __init void prom_init_mem(void) { unsigned long mem; - /* Figure out memory size by finding aliases */ + /* Figure out memory size by finding aliases. + * + * We should theoretically use the mapping from CFE using cfe_enummem(). + * However as the BCM47XX is mostly used on low-memory systems, we + * want to reuse the memory used by CFE (around 4MB). That means cfe_* + * functions stop to work at some point during the boot, we should only + * call them at the beginning of the boot. + */ for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) { if (*(unsigned long *)((unsigned long)(prom_init) + mem) == *(unsigned long *)(prom_init)) @@ -44,6 +144,15 @@ void __init prom_init(void) add_memory_region(0, mem, BOOT_MEM_RAM); } +void __init prom_init(void) +{ + prom_init_cfe(); + prom_init_console(); + prom_init_cmdline(); + prom_init_mem(); +} + void __init prom_free_prom_memory(void) { } + diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index dfc580a..f48aa5a 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -27,9 +27,11 @@ #include #include +#include #include #include #include +#include struct ssb_bus ssb_bcm47xx; EXPORT_SYMBOL(ssb_bcm47xx); @@ -53,12 +55,55 @@ static void bcm47xx_machine_halt(void) cpu_relax(); } +static void str2eaddr(char *str, char *dest) +{ + int i = 0; + + if (str == NULL) { + memset(dest, 0, 6); + return; + } + + for (;;) { + dest[i++] = (char) simple_strtoul(str, NULL, 16); + str += 2; + if (!*str++ || i == 6) + break; + } +} + static int bcm47xx_get_invariants(struct ssb_bus *bus, struct ssb_init_invariants *iv) { - /* TODO: fill ssb_init_invariants using boardtype/boardrev - * CFE environment variables. - */ + char buf[100]; + + /* Fill boardinfo structure */ + memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo)); + + if (cfe_getenv("boardvendor", buf, sizeof(buf)) >= 0) + iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0); + if (cfe_getenv("boardtype", buf, sizeof(buf)) >= 0) + iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0); + if (cfe_getenv("boardrev", buf, sizeof(buf)) >= 0) + iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0); + + /* Fill sprom structure */ + memset(&(iv->sprom), 0, sizeof(struct ssb_sprom)); + iv->sprom.revision = 3; + + if (cfe_getenv("et0macaddr", buf, sizeof(buf)) >= 0) + str2eaddr(buf, iv->sprom.r1.et0mac); + if (cfe_getenv("et1macaddr", buf, sizeof(buf)) >= 0) + str2eaddr(buf, iv->sprom.r1.et1mac); + if (cfe_getenv("et0phyaddr", buf, sizeof(buf)) >= 0) + iv->sprom.r1.et0phyaddr = simple_strtoul(buf, NULL, 10); + if (cfe_getenv("et1phyaddr", buf, sizeof(buf)) >= 0) + iv->sprom.r1.et1phyaddr = simple_strtoul(buf, NULL, 10); + if (cfe_getenv("et0mdcport", buf, sizeof(buf)) >= 0) + iv->sprom.r1.et0mdcport = simple_strtoul(buf, NULL, 10); + if (cfe_getenv("et1mdcport", buf, sizeof(buf)) >= 0) + iv->sprom.r1.et1mdcport = simple_strtoul(buf, NULL, 10); + return 0; } -- cgit v0.10.2 From 34cc662f8aae0ce1db5c64d55a39a5081f9e3cd8 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 25 Sep 2007 15:42:09 +0200 Subject: [MIPS] Add gpio support to the BCM47XX platform Add GPIO support to the BCM47XX platform. It will be used by a GPIO LED driver. Signed-off-by: Aurelien Jarno Signed-off-by: Ralf Baechle diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile index dc035f9..0afe097 100644 --- a/arch/mips/bcm47xx/Makefile +++ b/arch/mips/bcm47xx/Makefile @@ -3,4 +3,4 @@ # under Linux. # -obj-y := irq.o prom.o serial.o setup.o time.o +obj-y := gpio.o irq.o prom.o serial.o setup.o time.o diff --git a/arch/mips/bcm47xx/gpio.c b/arch/mips/bcm47xx/gpio.c new file mode 100644 index 0000000..f5a53ac --- /dev/null +++ b/arch/mips/bcm47xx/gpio.c @@ -0,0 +1,79 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 Aurelien Jarno + */ + +#include +#include +#include +#include +#include + +int bcm47xx_gpio_to_irq(unsigned gpio) +{ + if (ssb_bcm47xx.chipco.dev) + return ssb_mips_irq(ssb_bcm47xx.chipco.dev) + 2; + else if (ssb_bcm47xx.extif.dev) + return ssb_mips_irq(ssb_bcm47xx.extif.dev) + 2; + else + return -EINVAL; +} +EXPORT_SYMBOL_GPL(bcm47xx_gpio_to_irq); + +int bcm47xx_gpio_get_value(unsigned gpio) +{ + if (ssb_bcm47xx.chipco.dev) + return ssb_chipco_gpio_in(&ssb_bcm47xx.chipco, 1 << gpio); + else if (ssb_bcm47xx.extif.dev) + return ssb_extif_gpio_in(&ssb_bcm47xx.extif, 1 << gpio); + else + return 0; +} +EXPORT_SYMBOL_GPL(bcm47xx_gpio_get_value); + +void bcm47xx_gpio_set_value(unsigned gpio, int value) +{ + if (ssb_bcm47xx.chipco.dev) + ssb_chipco_gpio_out(&ssb_bcm47xx.chipco, + 1 << gpio, + value ? 1 << gpio : 0); + else if (ssb_bcm47xx.extif.dev) + ssb_extif_gpio_out(&ssb_bcm47xx.extif, + 1 << gpio, + value ? 1 << gpio : 0); +} +EXPORT_SYMBOL_GPL(bcm47xx_gpio_set_value); + +int bcm47xx_gpio_direction_input(unsigned gpio) +{ + if (ssb_bcm47xx.chipco.dev && (gpio < BCM47XX_CHIPCO_GPIO_LINES)) + ssb_chipco_gpio_outen(&ssb_bcm47xx.chipco, + 1 << gpio, 0); + else if (ssb_bcm47xx.extif.dev && (gpio < BCM47XX_EXTIF_GPIO_LINES)) + ssb_extif_gpio_outen(&ssb_bcm47xx.extif, + 1 << gpio, 0); + else + return -EINVAL; + return 0; +} +EXPORT_SYMBOL_GPL(bcm47xx_gpio_direction_input); + +int bcm47xx_gpio_direction_output(unsigned gpio, int value) +{ + bcm47xx_gpio_set_value(gpio, value); + + if (ssb_bcm47xx.chipco.dev && (gpio < BCM47XX_CHIPCO_GPIO_LINES)) + ssb_chipco_gpio_outen(&ssb_bcm47xx.chipco, + 1 << gpio, 1 << gpio); + else if (ssb_bcm47xx.extif.dev && (gpio < BCM47XX_EXTIF_GPIO_LINES)) + ssb_extif_gpio_outen(&ssb_bcm47xx.extif, + 1 << gpio, 1 << gpio); + else + return -EINVAL; + return 0; +} +EXPORT_SYMBOL_GPL(bcm47xx_gpio_direction_output); + diff --git a/include/asm-mips/mach-bcm47xx/gpio.h b/include/asm-mips/mach-bcm47xx/gpio.h new file mode 100644 index 0000000..cfc8f4d --- /dev/null +++ b/include/asm-mips/mach-bcm47xx/gpio.h @@ -0,0 +1,59 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 Aurelien Jarno + */ + +#ifndef __BCM47XX_GPIO_H +#define __BCM47XX_GPIO_H + +#define BCM47XX_EXTIF_GPIO_LINES 5 +#define BCM47XX_CHIPCO_GPIO_LINES 16 + +extern int bcm47xx_gpio_to_irq(unsigned gpio); +extern int bcm47xx_gpio_get_value(unsigned gpio); +extern void bcm47xx_gpio_set_value(unsigned gpio, int value); +extern int bcm47xx_gpio_direction_input(unsigned gpio); +extern int bcm47xx_gpio_direction_output(unsigned gpio, int value); + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +static inline void gpio_free(unsigned gpio) +{ +} + +static inline int gpio_to_irq(unsigned gpio) +{ + return bcm47xx_gpio_to_irq(gpio); +} + +static inline int gpio_get_value(unsigned gpio) +{ + return bcm47xx_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + bcm47xx_gpio_set_value(gpio, value); +} + +static inline int gpio_direction_input(unsigned gpio) +{ + return bcm47xx_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + return bcm47xx_gpio_direction_output(gpio, value); +} + + +/* cansleep wrappers */ +#include + +#endif /* __BCM47XX_GPIO_H */ -- cgit v0.10.2 From 21c854dcbd7698bf723676a552968040e2813490 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 25 Sep 2007 15:43:07 +0200 Subject: [MIPS] GPIO LED driver for the WGT634U machine Add LED support to the WGT634U machine. It uses the new gpio-led driver and a platform driver for the pin definitions. Signed-off-by: Aurelien Jarno Signed-off-by: Ralf Baechle diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile index 0afe097..35294b1 100644 --- a/arch/mips/bcm47xx/Makefile +++ b/arch/mips/bcm47xx/Makefile @@ -3,4 +3,4 @@ # under Linux. # -obj-y := gpio.o irq.o prom.o serial.o setup.o time.o +obj-y := gpio.o irq.o prom.o serial.o setup.o time.o wgt634u.o diff --git a/arch/mips/bcm47xx/wgt634u.c b/arch/mips/bcm47xx/wgt634u.c new file mode 100644 index 0000000..5a017ea --- /dev/null +++ b/arch/mips/bcm47xx/wgt634u.c @@ -0,0 +1,64 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 Aurelien Jarno + */ + +#include +#include +#include +#include +#include + +/* GPIO definitions for the WGT634U */ +#define WGT634U_GPIO_LED 3 +#define WGT634U_GPIO_RESET 2 +#define WGT634U_GPIO_TP1 7 +#define WGT634U_GPIO_TP2 6 +#define WGT634U_GPIO_TP3 5 +#define WGT634U_GPIO_TP4 4 +#define WGT634U_GPIO_TP5 1 + +static struct gpio_led wgt634u_leds[] = { + { + .name = "power", + .gpio = WGT634U_GPIO_LED, + .active_low = 1, + .default_trigger = "heartbeat", + }, +}; + +static struct gpio_led_platform_data wgt634u_led_data = { + .num_leds = ARRAY_SIZE(wgt634u_leds), + .leds = wgt634u_leds, +}; + +static struct platform_device wgt634u_gpio_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &wgt634u_led_data, + } +}; + +static int __init wgt634u_init(void) +{ + /* There is no easy way to detect that we are running on a WGT634U + * machine. Use the MAC address as an heuristic. Netgear Inc. has + * been allocated ranges 00:09:5b:xx:xx:xx and 00:0f:b5:xx:xx:xx. + */ + + u8 *et0mac = ssb_bcm47xx.sprom.r1.et0mac; + + if (et0mac[0] == 0x00 && + ((et0mac[1] == 0x09 && et0mac[2] == 0x5b) || + (et0mac[1] == 0x0f && et0mac[2] == 0xb5))) + return platform_device_register(&wgt634u_gpio_leds); + else + return -ENODEV; +} + +module_init(wgt634u_init); + -- cgit v0.10.2 From baf22c1e7aedf264e264b15d2595e5e76564bd4e Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:07 +0100 Subject: [MIPS] Split up war.h It was getting a little big, ugly and a primary source for merge conflicts. Also the old method was a bit too forgiving in that the workaround did default to off, so now there is an explicit #error forcing platform maintainers to think if they should enable a workaround for a particular platform. Signed-off-by: Ralf Baechle diff --git a/include/asm-mips/mach-au1x00/war.h b/include/asm-mips/mach-au1x00/war.h new file mode 100644 index 0000000..dd57d03 --- /dev/null +++ b/include/asm-mips/mach-au1x00/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_AU1X00_WAR_H +#define __ASM_MIPS_MACH_AU1X00_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_AU1X00_WAR_H */ diff --git a/include/asm-mips/mach-bcm47xx/war.h b/include/asm-mips/mach-bcm47xx/war.h new file mode 100644 index 0000000..4a2b798 --- /dev/null +++ b/include/asm-mips/mach-bcm47xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_BCM947XX_WAR_H +#define __ASM_MIPS_MACH_BCM947XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_BCM947XX_WAR_H */ diff --git a/include/asm-mips/mach-cobalt/war.h b/include/asm-mips/mach-cobalt/war.h new file mode 100644 index 0000000..97884fd --- /dev/null +++ b/include/asm-mips/mach-cobalt/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_COBALT_WAR_H +#define __ASM_MIPS_MACH_COBALT_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_COBALT_WAR_H */ diff --git a/include/asm-mips/mach-dec/war.h b/include/asm-mips/mach-dec/war.h new file mode 100644 index 0000000..ca5e2ef --- /dev/null +++ b/include/asm-mips/mach-dec/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_DEC_WAR_H +#define __ASM_MIPS_MACH_DEC_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_DEC_WAR_H */ diff --git a/include/asm-mips/mach-emma2rh/war.h b/include/asm-mips/mach-emma2rh/war.h new file mode 100644 index 0000000..b660a4c --- /dev/null +++ b/include/asm-mips/mach-emma2rh/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_EMMA2RH_WAR_H +#define __ASM_MIPS_MACH_EMMA2RH_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_EMMA2RH_WAR_H */ diff --git a/include/asm-mips/mach-excite/war.h b/include/asm-mips/mach-excite/war.h new file mode 100644 index 0000000..1f82180 --- /dev/null +++ b/include/asm-mips/mach-excite/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H +#define __ASM_MIPS_MACH_EXCITE_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 1 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */ diff --git a/include/asm-mips/mach-ip22/war.h b/include/asm-mips/mach-ip22/war.h new file mode 100644 index 0000000..a44fa96 --- /dev/null +++ b/include/asm-mips/mach-ip22/war.h @@ -0,0 +1,29 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_IP22_WAR_H +#define __ASM_MIPS_MACH_IP22_WAR_H + +/* + * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. + */ + +#define R4600_V1_INDEX_ICACHEOP_WAR 1 +#define R4600_V1_HIT_CACHEOP_WAR 1 +#define R4600_V2_HIT_CACHEOP_WAR 1 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_IP22_WAR_H */ diff --git a/include/asm-mips/mach-ip27/war.h b/include/asm-mips/mach-ip27/war.h new file mode 100644 index 0000000..e2ddcc9 --- /dev/null +++ b/include/asm-mips/mach-ip27/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_IP27_WAR_H +#define __ASM_MIPS_MACH_IP27_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 1 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_IP27_WAR_H */ diff --git a/include/asm-mips/mach-ip32/war.h b/include/asm-mips/mach-ip32/war.h new file mode 100644 index 0000000..d194056 --- /dev/null +++ b/include/asm-mips/mach-ip32/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_IP32_WAR_H +#define __ASM_MIPS_MACH_IP32_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_IP32_WAR_H */ diff --git a/include/asm-mips/mach-jazz/war.h b/include/asm-mips/mach-jazz/war.h new file mode 100644 index 0000000..6158ee8 --- /dev/null +++ b/include/asm-mips/mach-jazz/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_JAZZ_WAR_H +#define __ASM_MIPS_MACH_JAZZ_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_JAZZ_WAR_H */ diff --git a/include/asm-mips/mach-jmr3927/war.h b/include/asm-mips/mach-jmr3927/war.h new file mode 100644 index 0000000..1ff55fb --- /dev/null +++ b/include/asm-mips/mach-jmr3927/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_JMR3927_WAR_H +#define __ASM_MIPS_MACH_JMR3927_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_JMR3927_WAR_H */ diff --git a/include/asm-mips/mach-lasat/war.h b/include/asm-mips/mach-lasat/war.h new file mode 100644 index 0000000..bb1e032 --- /dev/null +++ b/include/asm-mips/mach-lasat/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_LASAT_WAR_H +#define __ASM_MIPS_MACH_LASAT_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_LASAT_WAR_H */ diff --git a/include/asm-mips/mach-lemote/war.h b/include/asm-mips/mach-lemote/war.h new file mode 100644 index 0000000..05f89e0 --- /dev/null +++ b/include/asm-mips/mach-lemote/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_LEMOTE_WAR_H +#define __ASM_MIPS_MACH_LEMOTE_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_LEMOTE_WAR_H */ diff --git a/include/asm-mips/mach-mips/war.h b/include/asm-mips/mach-mips/war.h new file mode 100644 index 0000000..7c6931d --- /dev/null +++ b/include/asm-mips/mach-mips/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H +#define __ASM_MIPS_MACH_MIPS_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 1 +#define MIPS_CACHE_SYNC_WAR 1 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ diff --git a/include/asm-mips/mach-mipssim/war.h b/include/asm-mips/mach-mipssim/war.h new file mode 100644 index 0000000..c8a74a3 --- /dev/null +++ b/include/asm-mips/mach-mipssim/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H +#define __ASM_MIPS_MACH_MIPSSIM_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */ diff --git a/include/asm-mips/mach-pnx8550/war.h b/include/asm-mips/mach-pnx8550/war.h new file mode 100644 index 0000000..d0458dd --- /dev/null +++ b/include/asm-mips/mach-pnx8550/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_PNX8550_WAR_H +#define __ASM_MIPS_MACH_PNX8550_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */ diff --git a/include/asm-mips/mach-qemu/war.h b/include/asm-mips/mach-qemu/war.h new file mode 100644 index 0000000..0eaf0c5 --- /dev/null +++ b/include/asm-mips/mach-qemu/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_QEMU_WAR_H +#define __ASM_MIPS_MACH_QEMU_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_QEMU_WAR_H */ diff --git a/include/asm-mips/mach-rm/war.h b/include/asm-mips/mach-rm/war.h new file mode 100644 index 0000000..948d312 --- /dev/null +++ b/include/asm-mips/mach-rm/war.h @@ -0,0 +1,29 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_RM_WAR_H +#define __ASM_MIPS_MACH_RM_WAR_H + +/* + * The RM200C seems to have been shipped only with V2.0 R4600s + */ + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 1 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_RM_WAR_H */ diff --git a/include/asm-mips/mach-sibyte/war.h b/include/asm-mips/mach-sibyte/war.h new file mode 100644 index 0000000..7950ef4 --- /dev/null +++ b/include/asm-mips/mach-sibyte/war.h @@ -0,0 +1,37 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H +#define __ASM_MIPS_MACH_SIBYTE_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 + +#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \ + defined(CONFIG_SB1_PASS_2_WORKAROUNDS) + +#define BCM1250_M3_WAR 1 +#define SIBYTE_1956_WAR 1 + +#else + +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 + +#endif + +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */ diff --git a/include/asm-mips/mach-tx49xx/war.h b/include/asm-mips/mach-tx49xx/war.h new file mode 100644 index 0000000..39b5d11 --- /dev/null +++ b/include/asm-mips/mach-tx49xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H +#define __ASM_MIPS_MACH_TX49XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 1 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */ diff --git a/include/asm-mips/mach-vr41xx/war.h b/include/asm-mips/mach-vr41xx/war.h new file mode 100644 index 0000000..56a3892 --- /dev/null +++ b/include/asm-mips/mach-vr41xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_VR41XX_WAR_H +#define __ASM_MIPS_MACH_VR41XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_VR41XX_WAR_H */ diff --git a/include/asm-mips/mach-wrppmc/war.h b/include/asm-mips/mach-wrppmc/war.h new file mode 100644 index 0000000..ac48629 --- /dev/null +++ b/include/asm-mips/mach-wrppmc/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H +#define __ASM_MIPS_MACH_WRPPMC_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */ diff --git a/include/asm-mips/mach-yosemite/war.h b/include/asm-mips/mach-yosemite/war.h new file mode 100644 index 0000000..e5c6d53 --- /dev/null +++ b/include/asm-mips/mach-yosemite/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_YOSEMITE_WAR_H +#define __ASM_MIPS_MACH_YOSEMITE_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 1 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_YOSEMITE_WAR_H */ diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index c0715d0..d2808ed 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -3,20 +3,22 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2002, 2004 by Ralf Baechle + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle */ #ifndef _ASM_WAR_H #define _ASM_WAR_H +#include /* * Another R4600 erratum. Due to the lack of errata information the exact * technical details aren't known. I've experimentally found that disabling * interrupts during indexed I-cache flushes seems to be sufficient to deal * with the issue. - * - * #define R4600_V1_INDEX_ICACHEOP_WAR 1 */ +#ifndef R4600_V1_INDEX_ICACHEOP_WAR +#error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform +#endif /* * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: @@ -43,9 +45,10 @@ * nop * nop * cache Hit_Writeback_Invalidate_D - * - * #define R4600_V1_HIT_CACHEOP_WAR 1 */ +#ifndef R4600_V1_HIT_CACHEOP_WAR +#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform +#endif /* @@ -58,32 +61,11 @@ * by a load instruction to an uncached address to empty the response buffer." * (Revision 2.0 device errata from IDT available on http://www.idt.com/ * in .pdf format.) - * - * #define R4600_V2_HIT_CACHEOP_WAR 1 - */ - -/* - * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. - */ -#ifdef CONFIG_SGI_IP22 - -#define R4600_V1_INDEX_ICACHEOP_WAR 1 -#define R4600_V1_HIT_CACHEOP_WAR 1 -#define R4600_V2_HIT_CACHEOP_WAR 1 - -#endif - -/* - * But the RM200C seems to have been shipped only with V2.0 R4600s */ -#ifdef CONFIG_SNI_RM - -#define R4600_V2_HIT_CACHEOP_WAR 1 - +#ifndef R4600_V2_HIT_CACHEOP_WAR +#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform #endif -#ifdef CONFIG_CPU_R5432 - /* * When an interrupt happens on a CP0 register read instruction, CPU may * lock up or read corrupted values of CP0 registers after it enters @@ -93,13 +75,10 @@ * first thing in the exception handler, which breaks one of the * pre-conditions for this problem. */ -#define R5432_CP0_INTERRUPT_WAR 1 - +#ifndef R5432_CP0_INTERRUPT_WAR +#error Check setting of R5432_CP0_INTERRUPT_WAR for your platform #endif -#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \ - defined(CONFIG_SB1_PASS_2_WORKAROUNDS) - /* * Workaround for the Sibyte M3 errata the text of which can be found at * @@ -110,13 +89,15 @@ * will just return and take the exception again if the information was * found to be inconsistent. */ -#define BCM1250_M3_WAR 1 +#ifndef BCM1250_M3_WAR +#error Check setting of BCM1250_M3_WAR for your platform +#endif /* * This is a DUART workaround related to glitches around register accesses */ -#define SIBYTE_1956_WAR 1 - +#ifndef SIBYTE_1956_WAR +#error Check setting of SIBYTE_1956_WAR for your platform #endif /* @@ -131,9 +112,8 @@ * Affects: * MIPS 4K RTL revision <3.0, PRID revision <4 */ -#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \ - defined(CONFIG_MIPS_SEAD) -#define MIPS4K_ICACHE_REFILL_WAR 1 +#ifndef MIPS4K_ICACHE_REFILL_WAR +#error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform #endif /* @@ -151,9 +131,8 @@ * MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8 * MIPS 20Kc RTL revision <4.0, PRID revision Date: Mon, 24 Sep 2007 16:13:34 +0100 Subject: [MIPS] dec/time.c: Remove no longer needed inclusion of . Signed-off-by: Maciej W. Rozycki Signed-off-by: Ralf Baechle diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c index 8b7e0c1..e2973a4 100644 --- a/arch/mips/dec/time.c +++ b/arch/mips/dec/time.c @@ -24,7 +24,6 @@ #include #include -#include #include #include #include -- cgit v0.10.2 From 112b20a1e849aec8077bbf11fc3de338b62f363a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:07 +0100 Subject: [MIPS] ARC: Convert mach_table[] to ISO C initializers. Signed-off-by: Ralf Baechle diff --git a/arch/mips/fw/arc/identify.c b/arch/mips/fw/arc/identify.c index 4b90736..5d28dbe 100644 --- a/arch/mips/fw/arc/identify.c +++ b/arch/mips/fw/arc/identify.c @@ -28,46 +28,54 @@ struct smatch { }; static struct smatch mach_table[] = { - { "SGI-IP22", - "SGI Indy", - MACH_GROUP_SGI, - MACH_SGI_IP22, - PROM_FLAG_ARCS - }, { "SGI-IP27", - "SGI Origin", - MACH_GROUP_SGI, - MACH_SGI_IP27, - PROM_FLAG_ARCS - }, { "SGI-IP28", - "SGI IP28", - MACH_GROUP_SGI, - MACH_SGI_IP28, - PROM_FLAG_ARCS - }, { "SGI-IP30", - "SGI Octane", - MACH_GROUP_SGI, - MACH_SGI_IP30, - PROM_FLAG_ARCS - }, { "SGI-IP32", - "SGI O2", - MACH_GROUP_SGI, - MACH_SGI_IP32, - PROM_FLAG_ARCS - }, { "Microsoft-Jazz", - "Jazz MIPS_Magnum_4000", - MACH_GROUP_JAZZ, - MACH_MIPS_MAGNUM_4000, - 0 - }, { "PICA-61", - "Jazz Acer_PICA_61", - MACH_GROUP_JAZZ, - MACH_ACER_PICA_61, - 0 - }, { "RM200PCI", - "SNI RM200_PCI", - MACH_GROUP_SNI_RM, - MACH_SNI_RM200_PCI, - PROM_FLAG_DONT_FREE_TEMP + { + .arcname = "SGI-IP22", + .liname = "SGI Indy", + .group = MACH_GROUP_SGI, + .type = MACH_SGI_IP22, + .flags = PROM_FLAG_ARCS, + }, { + .arcname = "SGI-IP27", + .liname = "SGI Origin", + .group = MACH_GROUP_SGI, + .type = MACH_SGI_IP27, + .flags = PROM_FLAG_ARCS, + }, { + .arcname = "SGI-IP28", + .liname = "SGI IP28", + .group = MACH_GROUP_SGI, + .type = MACH_SGI_IP28, + .flags = PROM_FLAG_ARCS, + }, { + .arcname = "SGI-IP30", + .liname = "SGI Octane", + .group = MACH_GROUP_SGI, + .type = MACH_SGI_IP30, + .flags = PROM_FLAG_ARCS, + }, { + .arcname = "SGI-IP32", + .liname = "SGI O2", + .group = MACH_GROUP_SGI, + .type = MACH_SGI_IP32, + .flags = PROM_FLAG_ARCS, + }, { + .arcname = "Microsoft-Jazz", + .liname = "Jazz MIPS_Magnum_4000", + .group = MACH_GROUP_JAZZ, + .type = MACH_MIPS_MAGNUM_4000, + .flags = 0, + }, { + .arcname = "PICA-61", + .liname = "Jazz Acer_PICA_61", + .group = MACH_GROUP_JAZZ, + .type = MACH_ACER_PICA_61, + .flags = 0, + }, { + .arcname = "RM200PCI", + .liname = "SNI RM200_PCI", + .group = MACH_GROUP_SNI_RM, + .type = MACH_SNI_RM200_PCI, + .flags = PROM_FLAG_DONT_FREE_TEMP, } }; -- cgit v0.10.2 From 05dc8c02bf40090e9ed23932b1980ead48eb8870 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:08 +0100 Subject: [MIPS] ARC: Get rid of mips_machgroup This has not been any serious user of this ill conceived thing since the original invention in like '95. Signed-off-by: Ralf Baechle diff --git a/arch/mips/au1000/db1x00/init.c b/arch/mips/au1000/db1x00/init.c index 0a3f025..e6bdd07 100644 --- a/arch/mips/au1000/db1x00/init.c +++ b/arch/mips/au1000/db1x00/init.c @@ -59,8 +59,6 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; - mips_machgroup = MACH_GROUP_ALCHEMY; - /* Set the platform # */ #if defined (CONFIG_MIPS_DB1550) mips_machtype = MACH_DB1550; diff --git a/arch/mips/au1000/mtx-1/init.c b/arch/mips/au1000/mtx-1/init.c index 88f2b6d..2aa7b2e 100644 --- a/arch/mips/au1000/mtx-1/init.c +++ b/arch/mips/au1000/mtx-1/init.c @@ -56,7 +56,6 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; - mips_machgroup = MACH_GROUP_ALCHEMY; mips_machtype = MACH_MTX1; /* set the platform # */ prom_init_cmdline(); diff --git a/arch/mips/au1000/pb1000/init.c b/arch/mips/au1000/pb1000/init.c index e9fa1ba..4535f72 100644 --- a/arch/mips/au1000/pb1000/init.c +++ b/arch/mips/au1000/pb1000/init.c @@ -54,7 +54,6 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; - mips_machgroup = MACH_GROUP_ALCHEMY; mips_machtype = MACH_PB1000; prom_init_cmdline(); diff --git a/arch/mips/au1000/pb1100/init.c b/arch/mips/au1000/pb1100/init.c index 6131b56..7ba6852 100644 --- a/arch/mips/au1000/pb1100/init.c +++ b/arch/mips/au1000/pb1100/init.c @@ -55,7 +55,6 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg3; - mips_machgroup = MACH_GROUP_ALCHEMY; mips_machtype = MACH_PB1100; prom_init_cmdline(); diff --git a/arch/mips/au1000/pb1200/init.c b/arch/mips/au1000/pb1200/init.c index 27f09e3..5a70029 100644 --- a/arch/mips/au1000/pb1200/init.c +++ b/arch/mips/au1000/pb1200/init.c @@ -55,7 +55,6 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; - mips_machgroup = MACH_GROUP_ALCHEMY; mips_machtype = MACH_PB1200; prom_init_cmdline(); diff --git a/arch/mips/au1000/pb1500/init.c b/arch/mips/au1000/pb1500/init.c index 733d2e4..e58a9d6 100644 --- a/arch/mips/au1000/pb1500/init.c +++ b/arch/mips/au1000/pb1500/init.c @@ -55,7 +55,6 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; - mips_machgroup = MACH_GROUP_ALCHEMY; mips_machtype = MACH_PB1500; prom_init_cmdline(); diff --git a/arch/mips/au1000/pb1550/init.c b/arch/mips/au1000/pb1550/init.c index 41daa33..fad53bf 100644 --- a/arch/mips/au1000/pb1550/init.c +++ b/arch/mips/au1000/pb1550/init.c @@ -55,7 +55,6 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; - mips_machgroup = MACH_GROUP_ALCHEMY; mips_machtype = MACH_PB1550; prom_init_cmdline(); diff --git a/arch/mips/au1000/xxs1500/init.c b/arch/mips/au1000/xxs1500/init.c index f1c7653..9f839c3 100644 --- a/arch/mips/au1000/xxs1500/init.c +++ b/arch/mips/au1000/xxs1500/init.c @@ -54,7 +54,6 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; - mips_machgroup = MACH_GROUP_ALCHEMY; mips_machtype = MACH_XXS1500; /* set the platform # */ prom_init_cmdline(); diff --git a/arch/mips/basler/excite/excite_prom.c b/arch/mips/basler/excite/excite_prom.c index 6ecd512..2d752c2 100644 --- a/arch/mips/basler/excite/excite_prom.c +++ b/arch/mips/basler/excite/excite_prom.c @@ -136,7 +136,6 @@ void __init prom_init(void) # error 64 bit support not implemented #endif /* CONFIG_64BIT */ - mips_machgroup = MACH_GROUP_TITAN; mips_machtype = MACH_TITAN_EXCITE; } diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c index fc9cbb2..5d2e879 100644 --- a/arch/mips/cobalt/setup.c +++ b/arch/mips/cobalt/setup.c @@ -114,8 +114,6 @@ void __init prom_init(void) unsigned long memsz; char **argv; - mips_machgroup = MACH_GROUP_COBALT; - memsz = fw_arg0 & 0x7fff0000; narg = fw_arg0 & 0x0000ffff; diff --git a/arch/mips/dec/prom/identify.c b/arch/mips/dec/prom/identify.c index cd85924..95e26f4 100644 --- a/arch/mips/dec/prom/identify.c +++ b/arch/mips/dec/prom/identify.c @@ -133,9 +133,6 @@ void __init prom_identify_arch(u32 magic) dec_firmrev = (dec_sysid & 0xff00) >> 8; dec_etc = dec_sysid & 0xff; - /* We're obviously one of the DEC machines */ - mips_machgroup = MACH_GROUP_DEC; - /* * FIXME: This may not be an exhaustive list of DECStations/Servers! * Put all model-specific initialisation calls here. diff --git a/arch/mips/emma2rh/common/prom.c b/arch/mips/emma2rh/common/prom.c index 7433bd8..0f791eb 100644 --- a/arch/mips/emma2rh/common/prom.c +++ b/arch/mips/emma2rh/common/prom.c @@ -62,8 +62,6 @@ void __init prom_init(void) strcat(arcs_cmdline, " "); } - mips_machgroup = MACH_GROUP_NEC_EMMA2RH; - #if defined(CONFIG_MARKEINS) mips_machtype = MACH_NEC_MARKEINS; add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM); diff --git a/arch/mips/fw/arc/identify.c b/arch/mips/fw/arc/identify.c index 5d28dbe..28dfd2e 100644 --- a/arch/mips/fw/arc/identify.c +++ b/arch/mips/fw/arc/identify.c @@ -22,7 +22,6 @@ struct smatch { char *arcname; char *liname; - int group; int type; int flags; }; @@ -31,49 +30,41 @@ static struct smatch mach_table[] = { { .arcname = "SGI-IP22", .liname = "SGI Indy", - .group = MACH_GROUP_SGI, .type = MACH_SGI_IP22, .flags = PROM_FLAG_ARCS, }, { .arcname = "SGI-IP27", .liname = "SGI Origin", - .group = MACH_GROUP_SGI, .type = MACH_SGI_IP27, .flags = PROM_FLAG_ARCS, }, { .arcname = "SGI-IP28", .liname = "SGI IP28", - .group = MACH_GROUP_SGI, .type = MACH_SGI_IP28, .flags = PROM_FLAG_ARCS, }, { .arcname = "SGI-IP30", .liname = "SGI Octane", - .group = MACH_GROUP_SGI, .type = MACH_SGI_IP30, .flags = PROM_FLAG_ARCS, }, { .arcname = "SGI-IP32", .liname = "SGI O2", - .group = MACH_GROUP_SGI, .type = MACH_SGI_IP32, .flags = PROM_FLAG_ARCS, }, { .arcname = "Microsoft-Jazz", .liname = "Jazz MIPS_Magnum_4000", - .group = MACH_GROUP_JAZZ, .type = MACH_MIPS_MAGNUM_4000, .flags = 0, }, { .arcname = "PICA-61", .liname = "Jazz Acer_PICA_61", - .group = MACH_GROUP_JAZZ, .type = MACH_ACER_PICA_61, .flags = 0, }, { .arcname = "RM200PCI", .liname = "SNI RM200_PCI", - .group = MACH_GROUP_SNI_RM, .type = MACH_SNI_RM200_PCI, .flags = PROM_FLAG_DONT_FREE_TEMP, } @@ -125,7 +116,6 @@ void __init prom_identify_arch(void) mach = string_to_mach(iname); system_type = mach->liname; - mips_machgroup = mach->group; mips_machtype = mach->type; prom_flags = mach->flags; } diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/gt64120/wrppmc/setup.c index ed58c13..238b508 100644 --- a/arch/mips/gt64120/wrppmc/setup.c +++ b/arch/mips/gt64120/wrppmc/setup.c @@ -159,7 +159,6 @@ const char *get_system_type(void) */ void __init prom_init(void) { - mips_machgroup = MACH_GROUP_WINDRIVER; mips_machtype = MACH_WRPPMC; add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM); diff --git a/arch/mips/jmr3927/rbhma3100/init.c b/arch/mips/jmr3927/rbhma3100/init.c index 9169fab..b643f75 100644 --- a/arch/mips/jmr3927/rbhma3100/init.c +++ b/arch/mips/jmr3927/rbhma3100/init.c @@ -51,7 +51,6 @@ void __init prom_init(void) if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) puts("Warning: TX3927 TLB off\n"); #endif - mips_machgroup = MACH_GROUP_TOSHIBA; #ifdef CONFIG_TOSHIBA_JMR3927 mips_machtype = MACH_TOSHIBA_JMR3927; diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 316685f..a06a27d 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -51,10 +51,8 @@ EXPORT_SYMBOL(PCI_DMA_BUS_IS_PHYS); * These are initialized so they are in the .data section */ unsigned long mips_machtype __read_mostly = MACH_UNKNOWN; -unsigned long mips_machgroup __read_mostly = MACH_GROUP_UNKNOWN; EXPORT_SYMBOL(mips_machtype); -EXPORT_SYMBOL(mips_machgroup); struct boot_mem_map boot_mem_map; diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c index 4b80fff..209edcc 100644 --- a/arch/mips/lasat/prom.c +++ b/arch/mips/lasat/prom.c @@ -100,8 +100,6 @@ void __init prom_init(void) lasat_init_board_info(); /* Read info from EEPROM */ - mips_machgroup = MACH_GROUP_LASAT; - /* Get the command line */ if (argc > 0) { strncpy(arcs_cmdline, argv[0], CL_SIZE-1); diff --git a/arch/mips/lemote/lm2e/prom.c b/arch/mips/lemote/lm2e/prom.c index 3efb1cf..8243368 100644 --- a/arch/mips/lemote/lm2e/prom.c +++ b/arch/mips/lemote/lm2e/prom.c @@ -57,7 +57,6 @@ void __init prom_init(void) arg = (int *)fw_arg1; env = (int *)fw_arg2; - mips_machgroup = MACH_GROUP_LEMOTE; mips_machtype = MACH_LEMOTE_FULONG; prom_init_cmdline(); diff --git a/arch/mips/philips/pnx8550/jbs/init.c b/arch/mips/philips/pnx8550/jbs/init.c index 85f4491..cfd90fa 100644 --- a/arch/mips/philips/pnx8550/jbs/init.c +++ b/arch/mips/philips/pnx8550/jbs/init.c @@ -48,7 +48,6 @@ void __init prom_init(void) unsigned long memsize; - mips_machgroup = MACH_GROUP_PHILIPS; mips_machtype = MACH_PHILIPS_JBS; //memsize = 0x02800000; /* Trimedia uses memory above */ diff --git a/arch/mips/philips/pnx8550/stb810/prom_init.c b/arch/mips/philips/pnx8550/stb810/prom_init.c index ea5b4e0..fdb33ed 100644 --- a/arch/mips/philips/pnx8550/stb810/prom_init.c +++ b/arch/mips/philips/pnx8550/stb810/prom_init.c @@ -41,7 +41,6 @@ void __init prom_init(void) prom_init_cmdline(); - mips_machgroup = MACH_GROUP_PHILIPS; mips_machtype = MACH_PHILIPS_STB810; memsize = 0x08000000; /* Trimedia uses memory above */ diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c index 8f69b78..e4cc548 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c @@ -176,16 +176,13 @@ void __init prom_init(void) case FAMILY_FPGA: if (FPGA_IS_MSP4200(revision)) { /* Old-style revision ID */ - mips_machgroup = MACH_GROUP_MSP; mips_machtype = MACH_MSP4200_FPGA; } else { - mips_machgroup = MACH_GROUP_MSP; mips_machtype = MACH_MSP_OTHER; } break; case FAMILY_MSP4200: - mips_machgroup = MACH_GROUP_MSP; #if defined(CONFIG_PMC_MSP4200_EVAL) mips_machtype = MACH_MSP4200_EVAL; #elif defined(CONFIG_PMC_MSP4200_GW) @@ -196,12 +193,10 @@ void __init prom_init(void) break; case FAMILY_MSP4200_FPGA: - mips_machgroup = MACH_GROUP_MSP; mips_machtype = MACH_MSP4200_FPGA; break; case FAMILY_MSP7100: - mips_machgroup = MACH_GROUP_MSP; #if defined(CONFIG_PMC_MSP7120_EVAL) mips_machtype = MACH_MSP7120_EVAL; #elif defined(CONFIG_PMC_MSP7120_GW) @@ -212,22 +207,14 @@ void __init prom_init(void) break; case FAMILY_MSP7100_FPGA: - mips_machgroup = MACH_GROUP_MSP; mips_machtype = MACH_MSP7120_FPGA; break; default: /* we don't recognize the machine */ - mips_machgroup = MACH_GROUP_UNKNOWN; mips_machtype = MACH_UNKNOWN; - break; - } - - /* make sure we have the right initialization routine - sanity */ - if (mips_machgroup != MACH_GROUP_MSP) { - ppfinit("Unknown machine group in a " - "MSP initialization routine\n"); panic("***Bogosity factor five***, exiting\n"); + break; } prom_init_cmdline(); diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c index 0cd78f0f..9b9936d 100644 --- a/arch/mips/pmc-sierra/yosemite/prom.c +++ b/arch/mips/pmc-sierra/yosemite/prom.c @@ -126,7 +126,6 @@ void __init prom_init(void) env++; } - mips_machgroup = MACH_GROUP_TITAN; mips_machtype = MACH_TITAN_YOSEMITE; prom_grab_secondary(); diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c index d842b98..147b7fb 100644 --- a/arch/mips/sibyte/cfe/setup.c +++ b/arch/mips/sibyte/cfe/setup.c @@ -339,7 +339,6 @@ void __init prom_init(void) /* Not sure this is needed, but it's the safe way. */ arcs_cmdline[CL_SIZE-1] = 0; - mips_machgroup = MACH_GROUP_SIBYTE; prom_meminit(); } diff --git a/arch/mips/sibyte/sb1250/prom.c b/arch/mips/sibyte/sb1250/prom.c index 257c4e6..f07ad3b 100644 --- a/arch/mips/sibyte/sb1250/prom.c +++ b/arch/mips/sibyte/sb1250/prom.c @@ -83,7 +83,6 @@ void __init prom_init(void) strcpy(arcs_cmdline, "root=/dev/ram0 "); - mips_machgroup = MACH_GROUP_SIBYTE; prom_meminit(); } diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c index 9a3a5ba..f3f8685 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c @@ -66,8 +66,6 @@ void __init prom_init(void) prom_init_cmdline(); - mips_machgroup = MACH_GROUP_TOSHIBA; - if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) { mips_machtype = MACH_TOSHIBA_RBTX4927; toshiba_name = "TX4927"; diff --git a/arch/mips/tx4938/toshiba_rbtx4938/prom.c b/arch/mips/tx4938/toshiba_rbtx4938/prom.c index 7dc6a0a..69f21c1 100644 --- a/arch/mips/tx4938/toshiba_rbtx4938/prom.c +++ b/arch/mips/tx4938/toshiba_rbtx4938/prom.c @@ -47,7 +47,6 @@ void __init prom_init(void) #ifndef CONFIG_TX4938_NAND_BOOT prom_init_cmdline(); #endif - mips_machgroup = MACH_GROUP_TOSHIBA; mips_machtype = MACH_TOSHIBA_RBTX4938; msize = tx4938_get_mem_size(); diff --git a/arch/mips/vr41xx/nec-cmbvr4133/setup.c b/arch/mips/vr41xx/nec-cmbvr4133/setup.c index b20b93b..58e4768 100644 --- a/arch/mips/vr41xx/nec-cmbvr4133/setup.c +++ b/arch/mips/vr41xx/nec-cmbvr4133/setup.c @@ -64,7 +64,6 @@ static void __init nec_cmbvr4133_setup(void) #endif set_io_port_base(KSEG1ADDR(0x16000000)); - mips_machgroup = MACH_GROUP_NEC_VR41XX; mips_machtype = MACH_NEC_CMBVR4133; #ifdef CONFIG_PCI diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index efa8158..b2dd9b3 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -15,21 +15,19 @@ #include /* - * The MACH_GROUP_ IDs are the equivalent to PCI vendor IDs; the remaining - * MACH_ values equivalent to product IDs. As such the numbers do not - * necessarily reflect technical relations or similarities between systems. + * The MACH_ IDs are sort of equivalent to PCI product IDs. As such the + * numbers do not necessarily reflect technical relations or similarities + * between systems. */ /* * Valid machtype values for group unknown */ -#define MACH_GROUP_UNKNOWN 0 /* whatever... */ #define MACH_UNKNOWN 0 /* whatever... */ /* * Valid machtype values for group JAZZ */ -#define MACH_GROUP_JAZZ 1 /* Jazz */ #define MACH_ACER_PICA_61 0 /* Acer PICA-61 (PICA1) */ #define MACH_MIPS_MAGNUM_4000 1 /* Mips Magnum 4000 "RC4030" */ #define MACH_OLIVETTI_M700 2 /* Olivetti M700-10 (-15 ??) */ @@ -37,7 +35,6 @@ /* * Valid machtype for group DEC */ -#define MACH_GROUP_DEC 2 /* Digital Equipment */ #define MACH_DSUNKNOWN 0 #define MACH_DS23100 1 /* DECstation 2100 or 3100 */ #define MACH_DS5100 2 /* DECsystem 5100 */ @@ -53,26 +50,22 @@ /* * Valid machtype for group ARC */ -#define MACH_GROUP_ARC 3 /* Deskstation */ #define MACH_DESKSTATION_RPC44 0 /* Deskstation rPC44 */ #define MACH_DESKSTATION_TYNE 1 /* Deskstation Tyne */ /* * Valid machtype for group SNI_RM */ -#define MACH_GROUP_SNI_RM 4 /* Siemens Nixdorf RM series */ #define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */ /* * Valid machtype for group ACN */ -#define MACH_GROUP_ACN 5 #define MACH_ACN_MIPS_BOARD 0 /* ACN MIPS single board */ /* * Valid machtype for group SGI */ -#define MACH_GROUP_SGI 6 /* Silicon Graphics */ #define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */ #define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */ #define MACH_SGI_IP28 2 /* Indigo2 Impact */ @@ -82,26 +75,22 @@ /* * Valid machtype for group COBALT */ -#define MACH_GROUP_COBALT 7 /* Cobalt servers */ #define MACH_COBALT_27 0 /* Proto "27" hardware */ /* * Valid machtype for group BAGET */ -#define MACH_GROUP_BAGET 9 /* Baget */ #define MACH_BAGET201 0 /* BT23-201 */ #define MACH_BAGET202 1 /* BT23-202 */ /* * Cosine boards. */ -#define MACH_GROUP_COSINE 10 /* CoSine Orion */ #define MACH_COSINE_ORION 0 /* * Valid machtype for group MOMENCO */ -#define MACH_GROUP_MOMENCO 12 /* Momentum Boards */ #define MACH_MOMENCO_OCELOT 0 #define MACH_MOMENCO_OCELOT_G 1 /* no more supported (may 2007) */ #define MACH_MOMENCO_OCELOT_C 2 /* no more supported (jun 2007) */ @@ -111,7 +100,6 @@ /* * Valid machtype for group PHILIPS */ -#define MACH_GROUP_PHILIPS 14 #define MACH_PHILIPS_NINO 0 /* Nino */ #define MACH_PHILIPS_VELO 1 /* Velo */ #define MACH_PHILIPS_JBS 2 /* JBS */ @@ -120,13 +108,11 @@ /* * Valid machtype for group SIBYTE */ -#define MACH_GROUP_SIBYTE 16 /* Sibyte / Broadcom */ #define MACH_SWARM 0 /* * Valid machtypes for group Toshiba */ -#define MACH_GROUP_TOSHIBA 17 /* Toshiba Reference Systems TSBREF */ #define MACH_PALLAS 0 #define MACH_TOPAS 1 #define MACH_JMR 2 @@ -138,7 +124,6 @@ /* * Valid machtype for group Alchemy */ -#define MACH_GROUP_ALCHEMY 18 /* AMD Alchemy */ #define MACH_PB1000 0 /* Au1000-based eval board */ #define MACH_PB1100 1 /* Au1100-based eval board */ #define MACH_PB1500 2 /* Au1500-based eval board */ @@ -160,7 +145,6 @@ * FIXME: MACH_GROUPs should be by _MANUFACTURER_ of * the device, not by * technical properties, so no new additions to this group. */ -#define MACH_GROUP_NEC_VR41XX 19 #define MACH_NEC_OSPREY 0 /* Osprey eval board */ #define MACH_NEC_EAGLE 1 /* NEC Eagle/Hawk board */ #define MACH_ZAO_CAPCELLA 2 /* ZAO Networks Capcella */ @@ -171,39 +155,33 @@ #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */ #define MACH_NEC_CMBVR4133 8 /* CMB VR4133 Board */ -#define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */ #define MACH_HP_LASERJET 1 /* * Valid machtype for group LASAT */ -#define MACH_GROUP_LASAT 21 #define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */ #define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */ /* * Valid machtype for group TITAN */ -#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */ #define MACH_TITAN_EXCITE 2 /* Basler eXcite */ /* * Valid machtype for group NEC EMMA2RH */ -#define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */ #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ /* * Valid machtype for group LEMOTE */ -#define MACH_GROUP_LEMOTE 27 #define MACH_LEMOTE_FULONG 0 /* * Valid machtype for group PMC-MSP */ -#define MACH_GROUP_MSP 26 /* PMC-Sierra MSP boards/CPUs */ #define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */ #define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */ #define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */ @@ -212,7 +190,6 @@ #define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ #define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ -#define MACH_GROUP_WINDRIVER 28 /* Windriver boards */ #define MACH_WRPPMC 1 /* @@ -226,7 +203,6 @@ const char *get_system_type(void); extern unsigned long mips_machtype; -extern unsigned long mips_machgroup; #define BOOT_MEM_MAP_MAX 32 #define BOOT_MEM_RAM 1 -- cgit v0.10.2 From 4680576edecb640f64936bd9b92add0a56027b61 Mon Sep 17 00:00:00 2001 From: "Ahmed S. Darwish" Date: Thu, 27 Sep 2007 01:35:43 +0300 Subject: [MIPS] Replace deprecated SA_* IRQ flags with modern IRQF_ variants. Signed-off-by: Ahmed S. Darwish Signed-off-by: Ralf Baechle diff --git a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c index 6fa8572..ab96a2d 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c @@ -163,7 +163,7 @@ static int msp_hwbutton_register(struct hwbutton_interrupt *hirq) CIC_EXT_SET_ACTIVE_HI(cic_ext, hirq->eirq); *CIC_EXT_CFG_REG = cic_ext; - return request_irq(hirq->irq, hwbutton_handler, SA_INTERRUPT, + return request_irq(hirq->irq, hwbutton_handler, IRQF_DISABLED, hirq->name, (void *)hirq); } -- cgit v0.10.2 From f5ff0a280201c9cbfb6e9eb4bafdb465c2269ed3 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 13 Aug 2007 15:26:12 +0100 Subject: [MIPS] Use generic NTP code for all MIPS platforms Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 371434d..c024113 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -670,6 +670,10 @@ config GENERIC_TIME bool default y +config GENERIC_CMOS_UPDATE + bool + default y + config SCHED_NO_NO_OMIT_FRAME_POINTER bool default y diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 9a5596b..628a8ba 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -67,6 +67,10 @@ unsigned long (*rtc_mips_get_time)(void) = null_rtc_get_time; int (*rtc_mips_set_time)(unsigned long) = null_rtc_set_time; int (*rtc_mips_set_mmss)(unsigned long); +int update_persistent_clock(struct timespec now) +{ + return rtc_mips_set_mmss(now.tv_sec); +} /* how many counter cycles in a jiffy */ static unsigned long cycles_per_jiffy __read_mostly; @@ -125,9 +129,6 @@ static void __init c0_hpt_timer_init(void) int (*mips_timer_state)(void); void (*mips_timer_ack)(void); -/* last time when xtime and rtc are sync'ed up */ -static long last_rtc_update; - /* * local_timer_interrupt() does profiling and process accounting * on a per-CPU basis. @@ -159,23 +160,6 @@ irqreturn_t timer_interrupt(int irq, void *dev_id) */ do_timer(1); - /* - * If we have an externally synchronized Linux clock, then update - * CMOS clock accordingly every ~11 minutes. rtc_mips_set_time() has to be - * called as close as possible to 500 ms before the new second starts. - */ - if (ntp_synced() && - xtime.tv_sec > last_rtc_update + 660 && - (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && - (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { - if (rtc_mips_set_mmss(xtime.tv_sec) == 0) { - last_rtc_update = xtime.tv_sec; - } else { - /* do it again in 60 s */ - last_rtc_update = xtime.tv_sec - 600; - } - } - write_sequnlock(&xtime_lock); /* diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index 8c3c78c..3134616 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -40,7 +40,6 @@ #define TICK_SIZE (tick_nsec / 1000) static unsigned long ct_cur[NR_CPUS]; /* What counter should be at next timer irq */ -static long last_rtc_update; /* Last time the rtc clock got updated */ #if 0 static int set_rtc_mmss(unsigned long nowtime) @@ -113,23 +112,6 @@ again: update_process_times(user_mode(get_irq_regs())); - /* - * If we have an externally synchronized Linux clock, then update - * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be - * called as close as possible to when a second starts. - */ - if (ntp_synced() && - xtime.tv_sec > last_rtc_update + 660 && - (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && - (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { - if (rtc_mips_set_time(xtime.tv_sec) == 0) { - last_rtc_update = xtime.tv_sec; - } else { - last_rtc_update = xtime.tv_sec - 600; - /* do it again in 60 s */ - } - } - write_sequnlock(&xtime_lock); irq_exit(); } -- cgit v0.10.2 From 4b550488f894c899aa54dc935c8fee47bca2b7df Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:08 +0100 Subject: [MIPS] Deforest the function pointer jungle in the time code. Hard to follow who is pointing what to where and why so it's simply getting in the way of the time code renovation. Signed-off-by: Ralf Baechle diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c index a95b377..b212c07 100644 --- a/arch/mips/au1000/common/setup.c +++ b/arch/mips/au1000/common/setup.c @@ -50,7 +50,6 @@ extern void au1000_halt(void); extern void au1000_power_off(void); extern void au1x_time_init(void); extern void au1x_timer_setup(struct irqaction *irq); -extern void au1xxx_time_init(void); extern void set_cpuspec(void); void __init plat_mem_setup(void) @@ -112,7 +111,6 @@ void __init plat_mem_setup(void) _machine_restart = au1000_restart; _machine_halt = au1000_halt; pm_power_off = au1000_power_off; - board_time_init = au1xxx_time_init; /* IO/MEM resources. */ set_io_port_base(0); diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index 8fc2998..fb1fd50 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -329,7 +329,3 @@ void __init plat_timer_setup(struct irqaction *irq) #endif } - -void __init au1xxx_time_init(void) -{ -} diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c index 5600318..68be19d 100644 --- a/arch/mips/basler/excite/excite_setup.c +++ b/arch/mips/basler/excite/excite_setup.c @@ -68,7 +68,7 @@ DEFINE_SPINLOCK(titan_lock); int titan_irqflags; -static void excite_timer_init(void) +void __init plat_time_init(void) { const u32 modebit5 = ocd_readl(0x00e4); unsigned int @@ -261,9 +261,6 @@ void __init plat_mem_setup(void) /* Announce RAM to system */ add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); - /* Set up timer initialization hooks */ - board_time_init = excite_timer_init; - /* Set up the peripheral address map */ *(boot_ocd_base + (LKB9 / sizeof (u32))) = 0; *(boot_ocd_base + (LKB10 / sizeof (u32))) = 0; diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index f48aa5a..1b6b0fa 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -119,6 +119,5 @@ void __init plat_mem_setup(void) _machine_restart = bcm47xx_machine_restart; _machine_halt = bcm47xx_machine_halt; pm_power_off = bcm47xx_machine_halt; - board_time_init = bcm47xx_time_init; } diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c index b27d07f..0ab4676 100644 --- a/arch/mips/bcm47xx/time.c +++ b/arch/mips/bcm47xx/time.c @@ -28,8 +28,7 @@ #include #include -void __init -bcm47xx_time_init(void) +void __init plat_time_init(void) { unsigned long hz; diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c index 3e634f2f..bd5431e 100644 --- a/arch/mips/dec/setup.c +++ b/arch/mips/dec/setup.c @@ -145,13 +145,9 @@ static void __init dec_be_init(void) } } - -extern void dec_time_init(void); - void __init plat_mem_setup(void) { board_be_init = dec_be_init; - board_time_init = dec_time_init; wbflush_setup(); diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c index e2973a4..820e533 100644 --- a/arch/mips/dec/time.c +++ b/arch/mips/dec/time.c @@ -35,7 +35,7 @@ #include #include -static unsigned long dec_rtc_get_time(void) +unsigned long read_persistent_clock(void) { unsigned int year, mon, day, hour, min, sec, real_year; unsigned long flags; @@ -74,13 +74,13 @@ static unsigned long dec_rtc_get_time(void) } /* - * In order to set the CMOS clock precisely, dec_rtc_set_mmss has to + * In order to set the CMOS clock precisely, rtc_mips_set_mmss has to * be called 500 ms after the second nowtime has started, because when * nowtime is written into the registers of the CMOS clock, it will * jump to the next second precisely 500 ms later. Check the Dallas * DS1287 data sheet for details. */ -static int dec_rtc_set_mmss(unsigned long nowtime) +int rtc_mips_set_mmss(unsigned long nowtime) { int retval = 0; int real_seconds, real_minutes, cmos_minutes; @@ -139,7 +139,6 @@ static int dec_rtc_set_mmss(unsigned long nowtime) return retval; } - static int dec_timer_state(void) { return (CMOS_READ(RTC_REG_C) & RTC_PF) != 0; @@ -160,11 +159,8 @@ static cycle_t dec_ioasic_hpt_read(void) } -void __init dec_time_init(void) +void __init plat_time_init(void) { - rtc_mips_get_time = dec_rtc_get_time; - rtc_mips_set_mmss = dec_rtc_set_mmss; - mips_timer_state = dec_timer_state; mips_timer_ack = dec_timer_ack; diff --git a/arch/mips/emma2rh/markeins/setup.c b/arch/mips/emma2rh/markeins/setup.c index 2f060e1..5e1da53 100644 --- a/arch/mips/emma2rh/markeins/setup.c +++ b/arch/mips/emma2rh/markeins/setup.c @@ -88,7 +88,7 @@ static unsigned int __init detect_bus_frequency(unsigned long rtc_base) return clock[reg]; } -static void __init emma2rh_time_init(void) +void __init plat_time_init(void) { u32 reg; if (bus_frequency == 0) @@ -124,8 +124,6 @@ void __init plat_mem_setup(void) set_io_port_base(KSEG1ADDR(EMMA2RH_PCI_IO_BASE)); - board_time_init = emma2rh_time_init; - _machine_restart = markeins_machine_restart; _machine_halt = markeins_machine_halt; pm_power_off = markeins_machine_power_off; diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/gt64120/wrppmc/setup.c index 238b508..f2ccf10 100644 --- a/arch/mips/gt64120/wrppmc/setup.c +++ b/arch/mips/gt64120/wrppmc/setup.c @@ -126,7 +126,6 @@ static void wrppmc_setup_serial(void) void __init plat_mem_setup(void) { - extern void wrppmc_time_init(void); extern void wrppmc_machine_restart(char *command); extern void wrppmc_machine_halt(void); extern void wrppmc_machine_power_off(void); @@ -135,9 +134,6 @@ void __init plat_mem_setup(void) _machine_halt = wrppmc_machine_halt; pm_power_off = wrppmc_machine_power_off; - /* Use MIPS Count/Compare Timer */ - board_time_init = wrppmc_time_init; - /* This makes the operations of 'in/out[bwl]' to the * physical address ( < KSEG0) can work via KSEG1 */ diff --git a/arch/mips/gt64120/wrppmc/time.c b/arch/mips/gt64120/wrppmc/time.c index 5b44085..faf164e 100644 --- a/arch/mips/gt64120/wrppmc/time.c +++ b/arch/mips/gt64120/wrppmc/time.c @@ -38,7 +38,7 @@ void __init plat_timer_setup(struct irqaction *irq) * NOTE: We disable all GT64120 timers, and use MIPS processor internal * timer as the source of kernel clock tick. */ -void __init wrppmc_time_init(void) +void __init plat_time_init(void) { /* Disable GT64120 timers */ GT_WRITE(GT_TC_CONTROL_OFS, 0x00); diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c index fde56e8..7f14f70 100644 --- a/arch/mips/jmr3927/rbhma3100/setup.c +++ b/arch/mips/jmr3927/rbhma3100/setup.c @@ -109,7 +109,7 @@ static void jmr3927_timer_ack(void) jmr3927_tmrptr->tisr = 0; /* ack interrupt */ } -static void __init jmr3927_time_init(void) +void __init plat_time_init(void) { clocksource_mips.read = jmr3927_hpt_read; mips_timer_ack = jmr3927_timer_ack; @@ -141,8 +141,6 @@ void __init plat_mem_setup(void) set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); - board_time_init = jmr3927_time_init; - _machine_restart = jmr3927_machine_restart; _machine_halt = jmr3927_machine_halt; pm_power_off = jmr3927_machine_power_off; diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 628a8ba..9bbbd9b 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -49,24 +49,19 @@ * forward reference */ DEFINE_SPINLOCK(rtc_lock); +EXPORT_SYMBOL(rtc_lock); -/* - * By default we provide the null RTC ops - */ -static unsigned long null_rtc_get_time(void) +int __weak rtc_mips_set_time(unsigned long sec) { - return mktime(2000, 1, 1, 0, 0, 0); + return 0; } +EXPORT_SYMBOL(rtc_mips_set_time); -static int null_rtc_set_time(unsigned long sec) +int __weak rtc_mips_set_mmss(unsigned long nowtime) { - return 0; + return rtc_mips_set_time(nowtime); } -unsigned long (*rtc_mips_get_time)(void) = null_rtc_get_time; -int (*rtc_mips_set_time)(unsigned long) = null_rtc_set_time; -int (*rtc_mips_set_mmss)(unsigned long); - int update_persistent_clock(struct timespec now) { return rtc_mips_set_mmss(now.tv_sec); @@ -247,21 +242,18 @@ asmlinkage void ll_local_timer_interrupt(int irq) /* * time_init() - it does the following things. * - * 1) board_time_init() - + * 1) plat_time_init() - * a) (optional) set up RTC routines, * b) (optional) calibrate and set the mips_hpt_frequency * (only needed if you intended to use cpu counter as timer interrupt * source) - * 2) setup xtime based on rtc_mips_get_time(). - * 3) calculate a couple of cached variables for later usage - * 4) plat_timer_setup() - + * 2) calculate a couple of cached variables for later usage + * 3) plat_timer_setup() - * a) (optional) over-write any choices made above by time_init(). * b) machine specific code should setup the timer irqaction. * c) enable the timer interrupt */ -void (*board_time_init)(void); - unsigned int mips_hpt_frequency; static struct irqaction timer_irqaction = { @@ -341,19 +333,13 @@ static void __init init_mips_clocksource(void) clocksource_register(&clocksource_mips); } -void __init time_init(void) +void __init __weak plat_time_init(void) { - if (board_time_init) - board_time_init(); - - if (!rtc_mips_set_mmss) - rtc_mips_set_mmss = rtc_mips_set_time; - - xtime.tv_sec = rtc_mips_get_time(); - xtime.tv_nsec = 0; +} - set_normalized_timespec(&wall_to_monotonic, - -xtime.tv_sec, -xtime.tv_nsec); +void __init time_init(void) +{ + plat_time_init(); /* Choose appropriate high precision timer routines. */ if (!cpu_has_counter && !clocksource_mips.read) @@ -459,7 +445,4 @@ void to_tm(unsigned long tim, struct rtc_time *tm) tm->tm_wday = (gday + 4) % 7; /* 1970/1/1 was Thursday */ } -EXPORT_SYMBOL(rtc_lock); EXPORT_SYMBOL(to_tm); -EXPORT_SYMBOL(rtc_mips_set_time); -EXPORT_SYMBOL(rtc_mips_get_time); diff --git a/arch/mips/lasat/ds1603.c b/arch/mips/lasat/ds1603.c index 0b315f5..52cb143 100644 --- a/arch/mips/lasat/ds1603.c +++ b/arch/mips/lasat/ds1603.c @@ -135,8 +135,7 @@ static void rtc_end_op(void) lasat_ndelay(1000); } -/* interface */ -unsigned long ds1603_read(void) +unsigned long read_persistent_clock(void) { unsigned long word; unsigned long flags; @@ -147,10 +146,11 @@ unsigned long ds1603_read(void) word = rtc_read_word(); rtc_end_op(); spin_unlock_irqrestore(&rtc_lock, flags); + return word; } -int ds1603_set(unsigned long time) +int rtc_mips_set_mmss(unsigned long time) { unsigned long flags; diff --git a/arch/mips/lasat/ds1603.h b/arch/mips/lasat/ds1603.h index c2e5c76..2da3704 100644 --- a/arch/mips/lasat/ds1603.h +++ b/arch/mips/lasat/ds1603.h @@ -20,8 +20,6 @@ struct ds_defs { extern struct ds_defs *ds1603; -unsigned long ds1603_read(void); -int ds1603_set(unsigned long); void ds1603_set_trimmer(unsigned int); void ds1603_enable(void); void ds1603_disable(void); diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c index 187e378..54827d0 100644 --- a/arch/mips/lasat/setup.c +++ b/arch/mips/lasat/setup.c @@ -117,7 +117,7 @@ static struct notifier_block lasat_panic_block[] = } }; -static void lasat_time_init(void) +void plat_time_init(void) { mips_hpt_frequency = lasat_board_info.li_cpu_hz / 2; } @@ -142,12 +142,8 @@ void __init plat_mem_setup(void) lasat_reboot_setup(); - board_time_init = lasat_time_init; - #ifdef CONFIG_DS1603 ds1603 = &ds_defs[mips_machtype]; - rtc_mips_get_time = ds1603_read; - rtc_mips_set_time = ds1603_set; #endif #ifdef DYNAMIC_SERIAL_INIT diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c index 4575a82..389336c 100644 --- a/arch/mips/lasat/sysctl.c +++ b/arch/mips/lasat/sysctl.c @@ -32,6 +32,8 @@ #include #include +#include + #include "sysctl.h" #include "ds1603.h" @@ -106,7 +108,7 @@ int proc_dolasatrtc(ctl_table *table, int write, struct file *filp, mutex_lock(&lasat_info_mutex); if (!write) { - rtctmp = ds1603_read(); + rtctmp = read_persistent_clock(); /* check for time < 0 and set to 0 */ if (rtctmp < 0) rtctmp = 0; @@ -116,7 +118,7 @@ int proc_dolasatrtc(ctl_table *table, int write, struct file *filp, mutex_unlock(&lasat_info_mutex); return r; } - ds1603_set(rtctmp); + rtc_mips_set_mmss(rtctmp); mutex_unlock(&lasat_info_mutex); return 0; @@ -152,7 +154,7 @@ int sysctl_lasat_rtc(ctl_table *table, int *name, int nlen, int r; mutex_lock(&lasat_info_mutex); - rtctmp = ds1603_read(); + rtctmp = read_persistent_clock(); if (rtctmp < 0) rtctmp = 0; r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen); @@ -161,7 +163,7 @@ int sysctl_lasat_rtc(ctl_table *table, int *name, int nlen, return r; } if (newval && newlen) - ds1603_set(rtctmp); + rtc_mips_set_mmss(rtctmp); mutex_unlock(&lasat_info_mutex); return 1; diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c index f34350a..09314a2 100644 --- a/arch/mips/lemote/lm2e/setup.c +++ b/arch/mips/lemote/lm2e/setup.c @@ -58,13 +58,13 @@ void __init plat_timer_setup(struct irqaction *irq) setup_irq(MIPS_CPU_IRQ_BASE + 7, irq); } -static void __init loongson2e_time_init(void) +void __init plat_time_init(void) { /* setup mips r4k timer */ mips_hpt_frequency = cpu_clock_freq / 2; } -static unsigned long __init mips_rtc_get_time(void) +unsigned long read_persistent_clock(void) { return mc146818_get_cmos_time(); } @@ -89,9 +89,6 @@ void __init plat_mem_setup(void) mips_reboot_setup(); - board_time_init = loongson2e_time_init; - rtc_mips_get_time = mips_rtc_get_time; - __wbflush = wbflush_loongson2e; add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c index c68358a..86bfc05 100644 --- a/arch/mips/mips-boards/atlas/atlas_setup.c +++ b/arch/mips/mips-boards/atlas/atlas_setup.c @@ -35,8 +35,6 @@ #include extern void mips_reboot_setup(void); -extern void mips_time_init(void); -extern unsigned long mips_rtc_get_time(void); #ifdef CONFIG_KGDB extern void kgdb_config(void); @@ -63,9 +61,6 @@ void __init plat_mem_setup(void) kgdb_config(); #endif mips_reboot_setup(); - - board_time_init = mips_time_init; - rtc_mips_get_time = mips_rtc_get_time; } static void __init serial_init(void) diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index d7bff9c..075f9d4 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -224,12 +224,12 @@ static unsigned int __init estimate_cpu_frequency(void) return count; } -unsigned long __init mips_rtc_get_time(void) +unsigned long read_persistent_clock(void) { return mc146818_get_cmos_time(); } -void __init mips_time_init(void) +void __init plat_time_init(void) { unsigned int est_freq; diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c index 8f1b78d..a5a5a43 100644 --- a/arch/mips/mips-boards/malta/malta_setup.c +++ b/arch/mips/mips-boards/malta/malta_setup.c @@ -36,7 +36,6 @@ #endif extern void mips_reboot_setup(void); -extern void mips_time_init(void); extern unsigned long mips_rtc_get_time(void); #ifdef CONFIG_KGDB @@ -185,7 +184,4 @@ void __init plat_mem_setup(void) #endif #endif mips_reboot_setup(); - - board_time_init = mips_time_init; - rtc_mips_get_time = mips_rtc_get_time; } diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c index 5f70eaf..fad5897 100644 --- a/arch/mips/mips-boards/sead/sead_setup.c +++ b/arch/mips/mips-boards/sead/sead_setup.c @@ -35,7 +35,6 @@ #include extern void mips_reboot_setup(void); -extern void mips_time_init(void); static void __init serial_init(void); @@ -52,8 +51,6 @@ void __init plat_mem_setup(void) serial_init (); - board_time_init = mips_time_init; - mips_reboot_setup(); } diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c index d012719..452c129 100644 --- a/arch/mips/mipssim/sim_setup.c +++ b/arch/mips/mipssim/sim_setup.c @@ -36,7 +36,6 @@ #include -extern void sim_time_init(void); static void __init serial_init(void); unsigned int _isbonito = 0; @@ -54,7 +53,6 @@ void __init plat_mem_setup(void) serial_init(); - board_time_init = sim_time_init; pr_info("Linux started...\n"); #ifdef CONFIG_MIPS_MT_SMP diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c index a0f5a5d..9a355e7 100644 --- a/arch/mips/mipssim/sim_time.c +++ b/arch/mips/mipssim/sim_time.c @@ -146,7 +146,7 @@ static unsigned int __init estimate_cpu_frequency(void) return count; } -void __init sim_time_init(void) +void __init plat_time_init(void) { unsigned int est_freq, flags; diff --git a/arch/mips/philips/pnx8550/common/setup.c b/arch/mips/philips/pnx8550/common/setup.c index 5bd7374..2ce298f 100644 --- a/arch/mips/philips/pnx8550/common/setup.c +++ b/arch/mips/philips/pnx8550/common/setup.c @@ -47,7 +47,6 @@ extern void pnx8550_machine_halt(void); extern void pnx8550_machine_power_off(void); extern struct resource ioport_resource; extern struct resource iomem_resource; -extern void pnx8550_time_init(void); extern void rs_kgdb_hook(int tty_no); extern char *prom_getcmdline(void); @@ -104,8 +103,6 @@ void __init plat_mem_setup(void) _machine_halt = pnx8550_machine_halt; pm_power_off = pnx8550_machine_power_off; - board_time_init = pnx8550_time_init; - /* Clear the Global 2 Register, PCI Inta Output Enable Registers Bit 1:Enable DAC Powerdown -> 0:DACs are enabled and are working normally diff --git a/arch/mips/philips/pnx8550/common/time.c b/arch/mips/philips/pnx8550/common/time.c index 68def38..e818fd0 100644 --- a/arch/mips/philips/pnx8550/common/time.c +++ b/arch/mips/philips/pnx8550/common/time.c @@ -1,6 +1,7 @@ /* * Copyright 2001, 2002, 2003 MontaVista Software Inc. * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) * * Common time service routines for MIPS machines. See * Documents/MIPS/README.txt. @@ -46,16 +47,16 @@ static void timer_ack(void) } /* - * pnx8550_time_init() - it does the following things: + * plat_time_init() - it does the following things: * - * 1) board_time_init() - + * 1) plat_time_init() - * a) (optional) set up RTC routines, * b) (optional) calibrate and set the mips_hpt_frequency * (only needed if you intended to use cpu counter as timer interrupt * source) */ -void pnx8550_time_init(void) +__init void plat_time_init(void) { unsigned int n; unsigned int m; diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c index e4cc548..c936756 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c @@ -25,7 +25,6 @@ #define MSP_BOARD_RESET_GPIO 9 #endif -extern void msp_timer_init(void); extern void msp_serial_setup(void); extern void pmctwiled_setup(void); @@ -149,8 +148,6 @@ void __init plat_mem_setup(void) _machine_restart = msp_restart; _machine_halt = msp_halt; pm_power_off = msp_power_off; - - board_time_init = msp_timer_init; } void __init prom_init(void) diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c index 2a2beac5..f221d47 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_time.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c @@ -36,7 +36,7 @@ #include #include -void __init msp_timer_init(void) +void __init plat_time_init(void) { char *endp, *s; unsigned long cpu_rate = 0; @@ -81,7 +81,6 @@ void __init msp_timer_init(void) mips_hpt_frequency = cpu_rate/2; } - void __init plat_timer_setup(struct irqaction *irq) { #ifdef CONFIG_IRQ_MSP_CIC diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c index 58862c8..56bf695 100644 --- a/arch/mips/pmc-sierra/yosemite/setup.c +++ b/arch/mips/pmc-sierra/yosemite/setup.c @@ -70,7 +70,7 @@ void __init bus_error_init(void) } -unsigned long m48t37y_get_time(void) +unsigned long read_persistent_clock(void) { unsigned int year, month, day, hour, min, sec; unsigned long flags; @@ -95,7 +95,7 @@ unsigned long m48t37y_get_time(void) return mktime(year, month, day, hour, min, sec); } -int m48t37y_set_time(unsigned long sec) +int rtc_mips_set_time(unsigned long tim) { struct rtc_time tm; unsigned long flags; @@ -138,7 +138,7 @@ void __init plat_timer_setup(struct irqaction *irq) setup_irq(7, irq); } -void yosemite_time_init(void) +void __init plat_time_init(void) { mips_hpt_frequency = cpu_clock_freq / 2; mips_hpt_frequency = 33000000 * 3 * 5; @@ -198,17 +198,6 @@ static void __init py_rtc_setup(void) m48t37_base = ioremap(YOSEMITE_RTC_BASE, YOSEMITE_RTC_SIZE); if (!m48t37_base) printk(KERN_ERR "Mapping the RTC failed\n"); - - rtc_mips_get_time = m48t37y_get_time; - rtc_mips_set_time = m48t37y_set_time; - - write_seqlock(&xtime_lock); - xtime.tv_sec = m48t37y_get_time(); - xtime.tv_nsec = 0; - - set_normalized_timespec(&wall_to_monotonic, - -xtime.tv_sec, -xtime.tv_nsec); - write_sequnlock(&xtime_lock); } /* Not only time init but that's what the hook it's called through is named */ @@ -221,7 +210,6 @@ static void __init py_late_time_init(void) void __init plat_mem_setup(void) { - board_time_init = yosemite_time_init; late_time_init = py_late_time_init; /* Add memory regions */ diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c index e7ce798..174f09e 100644 --- a/arch/mips/sgi-ip22/ip22-setup.c +++ b/arch/mips/sgi-ip22/ip22-setup.c @@ -51,7 +51,6 @@ void ip22_do_break(void) EXPORT_SYMBOL(ip22_do_break); extern void ip22_be_init(void) __init; -extern void ip22_time_init(void) __init; void __init plat_mem_setup(void) { @@ -59,7 +58,6 @@ void __init plat_mem_setup(void) char *cserial; board_be_init = ip22_be_init; - ip22_time_init(); /* Init the INDY HPC I/O controller. Need to call this before * fucking with the memory controller because it needs to know the diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c index de3d018..0387c38 100644 --- a/arch/mips/sgi-ip22/ip22-time.c +++ b/arch/mips/sgi-ip22/ip22-time.c @@ -32,7 +32,7 @@ * note that mktime uses month from 1 to 12 while to_tm * uses 0 to 11. */ -static unsigned long indy_rtc_get_time(void) +unsigned long read_persistent_clock(void) { unsigned int yrs, mon, day, hrs, min, sec; unsigned int save_control; @@ -60,7 +60,7 @@ static unsigned long indy_rtc_get_time(void) return mktime(yrs + 1900, mon, day, hrs, min, sec); } -static int indy_rtc_set_time(unsigned long tim) +int rtc_mips_set_time(unsigned long tim) { struct rtc_time tm; unsigned int save_control; @@ -128,7 +128,7 @@ static unsigned long dosample(void) /* * Here we need to calibrate the cycle counter to at least be close. */ -static __init void indy_time_init(void) +__init void plat_time_init(void) { unsigned long r4k_ticks[3]; unsigned long r4k_tick; @@ -207,12 +207,3 @@ void __init plat_timer_setup(struct irqaction *irq) /* setup irqaction */ setup_irq(SGI_TIMER_IRQ, irq); } - -void __init ip22_time_init(void) -{ - /* setup hookup functions */ - rtc_mips_get_time = indy_rtc_get_time; - rtc_mips_set_time = indy_rtc_set_time; - - board_time_init = indy_time_init; -} diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c index af08c41..681b593 100644 --- a/arch/mips/sgi-ip27/ip27-init.c +++ b/arch/mips/sgi-ip27/ip27-init.c @@ -194,7 +194,6 @@ static inline void ioc3_eth_init(void) ioc3->eier = 0; } -extern void ip27_time_init(void); extern void ip27_reboot_setup(void); void __init plat_mem_setup(void) @@ -241,6 +240,4 @@ void __init plat_mem_setup(void) per_cpu_init(); set_io_port_base(IO_BASE); - - board_time_init = ip27_time_init; } diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index 3134616..9c1700e 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -123,7 +123,7 @@ again: #include #include -static __init unsigned long get_m48t35_time(void) +unsigned long read_persistent_clock(void) { unsigned int year, month, date, hour, min, sec; struct m48t35_rtc *rtc; @@ -205,12 +205,10 @@ static cycle_t ip27_hpt_read(void) return REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT); } -void __init ip27_time_init(void) +void __init plat_time_init(void) { clocksource_mips.read = ip27_hpt_read; mips_hpt_frequency = CYCLES_PER_SEC; - xtime.tv_sec = get_m48t35_time(); - xtime.tv_nsec = 0; } void __init cpu_time_init(void) diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c index bbba066..4125a5b 100644 --- a/arch/mips/sgi-ip32/ip32-setup.c +++ b/arch/mips/sgi-ip32/ip32-setup.c @@ -62,10 +62,15 @@ static inline void str2eaddr(unsigned char *ea, unsigned char *str) } #endif +unsigned long read_persistent_clock(void) +{ + return mc146818_get_cmos_time(); +} + /* An arbitrary time; this can be decreased if reliability looks good */ #define WAIT_MS 10 -void __init ip32_time_init(void) +void __init plat_time_init(void) { printk(KERN_INFO "Calibrating system timer... "); write_c0_count(0); @@ -85,11 +90,6 @@ void __init plat_mem_setup(void) { board_be_init = ip32_be_init; - rtc_mips_get_time = mc146818_get_cmos_time; - rtc_mips_set_mmss = mc146818_set_rtc_mmss; - - board_time_init = ip32_time_init; - #ifdef CONFIG_SGI_O2MACE_ETH { char *mac = ArcGetEnvironmentVariable("eaddr"); diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 83572d8..8b3ef0e 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -69,7 +69,7 @@ const char *get_system_type(void) return "SiByte " SIBYTE_BOARD_NAME; } -void __init swarm_time_init(void) +void __init plat_time_init(void) { #if defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) /* Setup HPT */ @@ -104,6 +104,44 @@ int swarm_be_handler(struct pt_regs *regs, int is_fixup) return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL); } +enum swarm_rtc_type { + RTC_NONE, + RTC_XICOR, + RTC_M4LT81 +}; + +enum swarm_rtc_type swarm_rtc_type; + +unsigned long read_persistent_clock(void) +{ + switch (swarm_rtc_type) { + case RTC_XICOR: + return xicor_get_time(); + + case RTC_M4LT81: + return m41t81_get_time(); + + case RTC_NONE: + default: + return mktime(2000, 1, 1, 0, 0, 0); + } +} + +int rtc_mips_set_time(unsigned long sec) +{ + switch (swarm_rtc_type) { + case RTC_XICOR: + return xicor_set_time(sec); + + case RTC_M4LT81: + return m41t81_set_time(sec); + + case RTC_NONE: + default: + return -1; + } +} + void __init plat_mem_setup(void) { #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) @@ -116,20 +154,12 @@ void __init plat_mem_setup(void) panic_timeout = 5; /* For debug. */ - board_time_init = swarm_time_init; board_be_handler = swarm_be_handler; - if (xicor_probe()) { - printk("swarm setup: Xicor 1241 RTC detected.\n"); - rtc_mips_get_time = xicor_get_time; - rtc_mips_set_time = xicor_set_time; - } - - if (m41t81_probe()) { - printk("swarm setup: M41T81 RTC detected.\n"); - rtc_mips_get_time = m41t81_get_time; - rtc_mips_set_time = m41t81_set_time; - } + if (xicor_probe()) + swarm_rtc_type = RTC_XICOR; + if (m41t81_probe()) + swarm_rtc_type = RTC_M4LT81; printk("This kernel optimized for " #ifdef CONFIG_SIMULATION diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c index 44b1ae6..25cf646 100644 --- a/arch/mips/sni/pcimt.c +++ b/arch/mips/sni/pcimt.c @@ -313,7 +313,6 @@ void __init sni_pcimt_init(void) { sni_pcimt_detect(); sni_pcimt_sc_init(); - board_time_init = sni_cpu_time_init; ioport_resource.end = sni_io_resource.end; #ifdef CONFIG_PCI PCIBIOS_MIN_IO = 0x9000; diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c index 2480c47..3361bdd 100644 --- a/arch/mips/sni/pcit.c +++ b/arch/mips/sni/pcit.c @@ -263,7 +263,6 @@ void __init sni_pcit_cplus_irq_init(void) void __init sni_pcit_init(void) { - board_time_init = sni_cpu_time_init; ioport_resource.end = sni_io_resource.end; #ifdef CONFIG_PCI PCIBIOS_MIN_IO = 0x9000; diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c index 28a11d8..94f115c 100644 --- a/arch/mips/sni/rm200.c +++ b/arch/mips/sni/rm200.c @@ -194,5 +194,4 @@ void __init sni_rm200_init(void) { set_io_port_base(SNI_PORT_BASE + 0x02000000); ioport_resource.end += 0x02000000; - board_time_init = sni_cpu_time_init; } diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c index 20028fc..92452d6 100644 --- a/arch/mips/sni/time.c +++ b/arch/mips/sni/time.c @@ -4,6 +4,7 @@ #include #include +#include #define SNI_CLOCK_TICK_RATE 3686400 #define SNI_COUNTER2_DIV 64 @@ -71,7 +72,7 @@ static __init unsigned long dosample(void) /* * Here we need to calibrate the cycle counter to at least be close. */ -__init void sni_cpu_time_init(void) +void __init plat_time_init(void) { unsigned long r4k_ticks[3]; unsigned long r4k_tick; @@ -146,3 +147,8 @@ void __init plat_timer_setup(struct irqaction *irq) break; } } + +unsigned long read_persistent_clock(void) +{ + return -1; +} diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c index b18ed58..8ce0989 100644 --- a/arch/mips/tx4927/common/tx4927_setup.c +++ b/arch/mips/tx4927/common/tx4927_setup.c @@ -49,14 +49,11 @@ #undef DEBUG -void __init tx4927_time_init(void); void dump_cp0(char *key); void __init plat_mem_setup(void) { - board_time_init = tx4927_time_init; - #ifdef CONFIG_TOSHIBA_RBTX4927 { extern void toshiba_rbtx4927_setup(void); @@ -65,20 +62,16 @@ void __init plat_mem_setup(void) #endif } -void __init tx4927_time_init(void) +void __init plat_time_init(void) { - #ifdef CONFIG_TOSHIBA_RBTX4927 { extern void toshiba_rbtx4927_time_init(void); toshiba_rbtx4927_time_init(); } #endif - - return; } - void __init plat_timer_setup(struct irqaction *irq) { setup_irq(TX4927_IRQ_CPU_TIMER, irq); diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c index 142abf4..ab40822 100644 --- a/arch/mips/tx4938/common/setup.c +++ b/arch/mips/tx4938/common/setup.c @@ -34,25 +34,16 @@ #include extern void toshiba_rbtx4938_setup(void); -extern void rbtx4938_time_init(void); void __init tx4938_setup(void); -void __init tx4938_time_init(void); void dump_cp0(char *key); void __init plat_mem_setup(void) { - board_time_init = tx4938_time_init; toshiba_rbtx4938_setup(); } -void __init -tx4938_time_init(void) -{ - rbtx4938_time_init(); -} - void __init plat_timer_setup(struct irqaction *irq) { setup_irq(TX4938_IRQ_CPU_TIMER, irq); diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c index f236b1f..304b406 100644 --- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c +++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c @@ -39,7 +39,6 @@ #include #include -extern void rbtx4938_time_init(void) __init; extern char * __init prom_getcmdline(void); static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr); @@ -856,7 +855,7 @@ void tx4938_report_pcic_status(void) /* We use onchip r4k counter or TMR timer as our system wide timer * interrupt running at 100HZ. */ -void __init rbtx4938_time_init(void) +void __init plat_time_init(void) { mips_hpt_frequency = txx9_cpu_clock / 2; } diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c index 4f97e0b..407cec2 100644 --- a/arch/mips/vr41xx/common/init.c +++ b/arch/mips/vr41xx/common/init.c @@ -36,7 +36,7 @@ static void __init iomem_resource_init(void) iomem_resource.end = IO_MEM_RESOURCE_END; } -static void __init setup_timer_frequency(void) +void __init plat_time_init(void) { unsigned long tclock; @@ -53,16 +53,10 @@ void __init plat_timer_setup(struct irqaction *irq) setup_irq(TIMER_IRQ, irq); } -static void __init timer_init(void) -{ - board_time_init = setup_timer_frequency; -} - void __init plat_mem_setup(void) { vr41xx_calculate_clock_frequency(); - timer_init(); iomem_resource_init(); } diff --git a/include/asm-mips/mach-bcm47xx/bcm47xx.h b/include/asm-mips/mach-bcm47xx/bcm47xx.h index a2fb5e8..d008f47 100644 --- a/include/asm-mips/mach-bcm47xx/bcm47xx.h +++ b/include/asm-mips/mach-bcm47xx/bcm47xx.h @@ -22,6 +22,4 @@ /* SSB bus */ extern struct ssb_bus ssb_bcm47xx; -extern void bcm47xx_time_init(void); - #endif /* __ASM_BCM47XX_H */ diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h index a632cef..74ab331 100644 --- a/include/asm-mips/time.h +++ b/include/asm-mips/time.h @@ -26,15 +26,13 @@ extern spinlock_t rtc_lock; /* - * RTC ops. By default, they point to no-RTC functions. - * rtc_mips_get_time - mktime(year, mon, day, hour, min, sec) in seconds. + * RTC ops. By default, they point to weak no-op RTC functions. * rtc_mips_set_time - reverse the above translation and set time to RTC. * rtc_mips_set_mmss - similar to rtc_set_time, but only min and sec need * to be set. Used by RTC sync-up. */ -extern unsigned long (*rtc_mips_get_time)(void); -extern int (*rtc_mips_set_time)(unsigned long); -extern int (*rtc_mips_set_mmss)(unsigned long); +extern int rtc_mips_set_time(unsigned long); +extern int rtc_mips_set_mmss(unsigned long); /* * Timer interrupt functions. @@ -75,11 +73,9 @@ extern asmlinkage void ll_local_timer_interrupt(int irq); /* * board specific routines required by time_init(). - * board_time_init is defaulted to NULL and can remain so. - * plat_timer_setup must be setup properly in machine setup routine. */ struct irqaction; -extern void (*board_time_init)(void); +extern void plat_time_init(void); extern void plat_timer_setup(struct irqaction *irq); /* -- cgit v0.10.2 From 90b02340dcc6ce00bf22c48f4865915f5989e5e4 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:09 +0100 Subject: [MIPS] Switch from to_tm to rtc_time_to_tm This replaces the MIPS-specific to_tm function with the generic rtc_time_to_tm function. The big difference between the two functions is that rtc_time_to_tm uses epoch 70 while to_tm uses 1970, so the result of rtc_time_to_tm needs to be fixed up. Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c024113..0cd0f83 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -3,6 +3,7 @@ config MIPS default y # Horrible source of confusion. Die, die, die ... select EMBEDDED + select RTC_LIB mainmenu "Linux/MIPS Kernel Configuration" diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 9bbbd9b..c48ebd4 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -397,52 +397,3 @@ void __init time_init(void) init_mips_clocksource(); } - -#define FEBRUARY 2 -#define STARTOFTIME 1970 -#define SECDAY 86400L -#define SECYR (SECDAY * 365) -#define leapyear(y) ((!((y) % 4) && ((y) % 100)) || !((y) % 400)) -#define days_in_year(y) (leapyear(y) ? 366 : 365) -#define days_in_month(m) (month_days[(m) - 1]) - -static int month_days[12] = { - 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 -}; - -void to_tm(unsigned long tim, struct rtc_time *tm) -{ - long hms, day, gday; - int i; - - gday = day = tim / SECDAY; - hms = tim % SECDAY; - - /* Hours, minutes, seconds are easy */ - tm->tm_hour = hms / 3600; - tm->tm_min = (hms % 3600) / 60; - tm->tm_sec = (hms % 3600) % 60; - - /* Number of years in days */ - for (i = STARTOFTIME; day >= days_in_year(i); i++) - day -= days_in_year(i); - tm->tm_year = i; - - /* Number of months in days left */ - if (leapyear(tm->tm_year)) - days_in_month(FEBRUARY) = 29; - for (i = 1; day >= days_in_month(i); i++) - day -= days_in_month(i); - days_in_month(FEBRUARY) = 28; - tm->tm_mon = i - 1; /* tm_mon starts from 0 to 11 */ - - /* Days are what is left over (+1) from all that. */ - tm->tm_mday = day + 1; - - /* - * Determine the day of week - */ - tm->tm_wday = (gday + 4) % 7; /* 1970/1/1 was Thursday */ -} - -EXPORT_SYMBOL(to_tm); diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c index 56bf695..015fcc3 100644 --- a/arch/mips/pmc-sierra/yosemite/setup.c +++ b/arch/mips/pmc-sierra/yosemite/setup.c @@ -100,8 +100,12 @@ int rtc_mips_set_time(unsigned long tim) struct rtc_time tm; unsigned long flags; - /* convert to a more useful format -- note months count from 0 */ - to_tm(sec, &tm); + /* + * Convert to a more useful format -- note months count from 0 + * and years from 1900 + */ + rtc_time_to_tm(tim, &tm); + tm.tm_year += 1900; tm.tm_mon += 1; spin_lock_irqsave(&rtc_lock, flags); diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c index 0387c38..c494180 100644 --- a/arch/mips/sgi-ip22/ip22-time.c +++ b/arch/mips/sgi-ip22/ip22-time.c @@ -29,7 +29,7 @@ #include /* - * note that mktime uses month from 1 to 12 while to_tm + * Note that mktime uses month from 1 to 12 while rtc_time_to_tm * uses 0 to 11. */ unsigned long read_persistent_clock(void) @@ -66,10 +66,10 @@ int rtc_mips_set_time(unsigned long tim) unsigned int save_control; unsigned long flags; - to_tm(tim, &tm); + rtc_time_to_tm(tim, &tm); tm.tm_mon += 1; /* tm_mon starts at zero */ - tm.tm_year -= 1940; + tm.tm_year -= 40; if (tm.tm_year >= 100) tm.tm_year -= 100; diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c index c13914b..26fbff4 100644 --- a/arch/mips/sibyte/swarm/rtc_m41t81.c +++ b/arch/mips/sibyte/swarm/rtc_m41t81.c @@ -146,7 +146,8 @@ int m41t81_set_time(unsigned long t) struct rtc_time tm; unsigned long flags; - to_tm(t, &tm); + /* Note we don't care about the century */ + rtc_time_to_tm(t, &tm); /* * Note the write order matters as it ensures the correctness. diff --git a/arch/mips/sibyte/swarm/rtc_xicor1241.c b/arch/mips/sibyte/swarm/rtc_xicor1241.c index f4a1788..ff3e5da 100644 --- a/arch/mips/sibyte/swarm/rtc_xicor1241.c +++ b/arch/mips/sibyte/swarm/rtc_xicor1241.c @@ -115,7 +115,8 @@ int xicor_set_time(unsigned long t) int tmp; unsigned long flags; - to_tm(t, &tm); + rtc_time_to_tm(t, &tm); + tm.tm_year += 1900; spin_lock_irqsave(&rtc_lock, flags); /* unlock writes to the CCR */ diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h index 74ab331..963507d 100644 --- a/include/asm-mips/time.h +++ b/include/asm-mips/time.h @@ -49,13 +49,6 @@ extern void (*mips_timer_ack)(void); extern struct clocksource clocksource_mips; /* - * to_tm() converts system time back to (year, mon, day, hour, min, sec). - * It is intended to help implement rtc_set_time() functions. - * Copied from PPC implementation. - */ -extern void to_tm(unsigned long tim, struct rtc_time *tm); - -/* * high-level timer interrupt routines. */ extern irqreturn_t timer_interrupt(int irq, void *dev_id); -- cgit v0.10.2 From 91a2fcc88634663e9e13dcdfad0e4a860e64aeee Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:09 +0100 Subject: [MIPS] Consolidate all variants of MIPS cp0 timer interrupt handlers. Signed-off-by: Ralf Baechle diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c index db2ba0d..47949d6 100644 --- a/arch/mips/au1000/common/irq.c +++ b/arch/mips/au1000/common/irq.c @@ -65,8 +65,6 @@ #define EXT_INTC1_REQ1 5 /* IP 5 */ #define MIPS_TIMER_IP 7 /* IP 7 */ -extern void mips_timer_interrupt(void); - void (*board_init_irq)(void); static DEFINE_SPINLOCK(irq_lock); @@ -635,7 +633,7 @@ asmlinkage void plat_irq_dispatch(void) unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; if (pending & CAUSEF_IP7) - mips_timer_interrupt(); + ll_timer_interrupt(63); else if (pending & CAUSEF_IP2) intc0_req0_irqdispatch(); else if (pending & CAUSEF_IP3) diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index fb1fd50..726c340 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -64,48 +64,8 @@ static unsigned long last_pc0, last_match20; static DEFINE_SPINLOCK(time_lock); -static inline void ack_r4ktimer(unsigned long newval) -{ - write_c0_compare(newval); -} - -/* - * There are a lot of conceptually broken versions of the MIPS timer interrupt - * handler floating around. This one is rather different, but the algorithm - * is provably more robust. - */ unsigned long wtimer; -void mips_timer_interrupt(void) -{ - int irq = 63; - - irq_enter(); - kstat_this_cpu.irqs[irq]++; - - if (r4k_offset == 0) - goto null; - - do { - kstat_this_cpu.irqs[irq]++; - do_timer(1); -#ifndef CONFIG_SMP - update_process_times(user_mode(get_irq_regs())); -#endif - r4k_cur += r4k_offset; - ack_r4ktimer(r4k_cur); - - } while (((unsigned long)read_c0_count() - - r4k_cur) < 0x7fffffff); - - irq_exit(); - return; - -null: - ack_r4ktimer(0); - irq_exit(); -} - #ifdef CONFIG_PM irqreturn_t counter0_irq(int irq, void *dev_id) { diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 137183b..a7afbf2 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -867,7 +867,7 @@ void ipi_decode(struct smtc_ipi *pipi) #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG clock_hang_reported[dest_copy] = 0; #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ - local_timer_interrupt(0, NULL); + local_timer_interrupt(0); irq_exit(); break; case LINUX_SMP_IPI: diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index c48ebd4..d23e682 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -144,7 +144,7 @@ void local_timer_interrupt(int irq, void *dev_id) * High-level timer interrupt service routines. This function * is set as irqaction->handler and is invoked through do_IRQ. */ -irqreturn_t timer_interrupt(int irq, void *dev_id) +static irqreturn_t timer_interrupt(int irq, void *dev_id) { write_seqlock(&xtime_lock); @@ -174,9 +174,10 @@ int null_perf_irq(void) return 0; } +EXPORT_SYMBOL(null_perf_irq); + int (*perf_irq)(void) = null_perf_irq; -EXPORT_SYMBOL(null_perf_irq); EXPORT_SYMBOL(perf_irq); /* @@ -208,35 +209,79 @@ static inline int handle_perf_irq (int r2) !r2; } -asmlinkage void ll_timer_interrupt(int irq) +void ll_timer_interrupt(int irq, void *dev_id) { - int r2 = cpu_has_mips_r2; + int cpu = smp_processor_id(); - irq_enter(); - kstat_this_cpu.irqs[irq]++; +#ifdef CONFIG_MIPS_MT_SMTC + /* + * In an SMTC system, one Count/Compare set exists per VPE. + * Which TC within a VPE gets the interrupt is essentially + * random - we only know that it shouldn't be one with + * IXMT set. Whichever TC gets the interrupt needs to + * send special interprocessor interrupts to the other + * TCs to make sure that they schedule, etc. + * + * That code is specific to the SMTC kernel, not to + * the a particular platform, so it's invoked from + * the general MIPS timer_interrupt routine. + */ + + /* + * We could be here due to timer interrupt, + * perf counter overflow, or both. + */ + (void) handle_perf_irq(1); + + if (read_c0_cause() & (1 << 30)) { + /* + * There are things we only want to do once per tick + * in an "MP" system. One TC of each VPE will take + * the actual timer interrupt. The others will get + * timer broadcast IPIs. We use whoever it is that takes + * the tick on VPE 0 to run the full timer_interrupt(). + */ + if (cpu_data[cpu].vpe_id == 0) { + timer_interrupt(irq, NULL); + } else { + write_c0_compare(read_c0_count() + + (mips_hpt_frequency/HZ)); + local_timer_interrupt(irq, dev_id); + } + smtc_timer_broadcast(cpu_data[cpu].vpe_id); + } +#else /* CONFIG_MIPS_MT_SMTC */ + int r2 = cpu_has_mips_r2; if (handle_perf_irq(r2)) - goto out; + return; if (r2 && ((read_c0_cause() & (1 << 30)) == 0)) - goto out; - - timer_interrupt(irq, NULL); - -out: - irq_exit(); -} - -asmlinkage void ll_local_timer_interrupt(int irq) -{ - irq_enter(); - if (smp_processor_id() != 0) - kstat_this_cpu.irqs[irq]++; - - /* we keep interrupt disabled all the time */ - local_timer_interrupt(irq, NULL); + return; - irq_exit(); + if (cpu == 0) { + /* + * CPU 0 handles the global timer interrupt job and process + * accounting resets count/compare registers to trigger next + * timer int. + */ + timer_interrupt(irq, NULL); + } else { + /* Everyone else needs to reset the timer int here as + ll_local_timer_interrupt doesn't */ + /* + * FIXME: need to cope with counter underflow. + * More support needs to be added to kernel/time for + * counter/timer interrupts on multiple CPU's + */ + write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ)); + + /* + * Other CPUs should do profiling and process accounting + */ + local_timer_interrupt(irq, dev_id); + } +#endif /* CONFIG_MIPS_MT_SMTC */ } /* diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index 075f9d4..345de88 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -68,108 +68,6 @@ static void mips_perf_dispatch(void) } /* - * Redeclare until I get around mopping the timer code insanity on MIPS. - */ -extern int null_perf_irq(void); - -extern int (*perf_irq)(void); - -/* - * Possibly handle a performance counter interrupt. - * Return true if the timer interrupt should not be checked - */ -static inline int handle_perf_irq (int r2) -{ - /* - * The performance counter overflow interrupt may be shared with the - * timer interrupt (cp0_perfcount_irq < 0). If it is and a - * performance counter has overflowed (perf_irq() == IRQ_HANDLED) - * and we can't reliably determine if a counter interrupt has also - * happened (!r2) then don't check for a timer interrupt. - */ - return (cp0_perfcount_irq < 0) && - perf_irq() == IRQ_HANDLED && - !r2; -} - -irqreturn_t mips_timer_interrupt(int irq, void *dev_id) -{ - int cpu = smp_processor_id(); - -#ifdef CONFIG_MIPS_MT_SMTC - /* - * In an SMTC system, one Count/Compare set exists per VPE. - * Which TC within a VPE gets the interrupt is essentially - * random - we only know that it shouldn't be one with - * IXMT set. Whichever TC gets the interrupt needs to - * send special interprocessor interrupts to the other - * TCs to make sure that they schedule, etc. - * - * That code is specific to the SMTC kernel, not to - * the a particular platform, so it's invoked from - * the general MIPS timer_interrupt routine. - */ - - /* - * We could be here due to timer interrupt, - * perf counter overflow, or both. - */ - (void) handle_perf_irq(1); - - if (read_c0_cause() & (1 << 30)) { - /* - * There are things we only want to do once per tick - * in an "MP" system. One TC of each VPE will take - * the actual timer interrupt. The others will get - * timer broadcast IPIs. We use whoever it is that takes - * the tick on VPE 0 to run the full timer_interrupt(). - */ - if (cpu_data[cpu].vpe_id == 0) { - timer_interrupt(irq, NULL); - } else { - write_c0_compare(read_c0_count() + - (mips_hpt_frequency/HZ)); - local_timer_interrupt(irq, dev_id); - } - smtc_timer_broadcast(); - } -#else /* CONFIG_MIPS_MT_SMTC */ - int r2 = cpu_has_mips_r2; - - if (handle_perf_irq(r2)) - goto out; - - if (r2 && ((read_c0_cause() & (1 << 30)) == 0)) - goto out; - - if (cpu == 0) { - /* - * CPU 0 handles the global timer interrupt job and process - * accounting resets count/compare registers to trigger next - * timer int. - */ - timer_interrupt(irq, NULL); - } else { - /* Everyone else needs to reset the timer int here as - ll_local_timer_interrupt doesn't */ - /* - * FIXME: need to cope with counter underflow. - * More support needs to be added to kernel/time for - * counter/timer interrupts on multiple CPU's - */ - write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ)); - - /* - * Other CPUs should do profiling and process accounting - */ - local_timer_interrupt(irq, dev_id); - } -out: -#endif /* CONFIG_MIPS_MT_SMTC */ - return IRQ_HANDLED; -} - -/* * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect */ static unsigned int __init estimate_cpu_frequency(void) @@ -246,7 +144,7 @@ void __init plat_time_init(void) mips_scroll_message(); } -irqreturn_t mips_perf_interrupt(int irq, void *dev_id) +static irqreturn_t mips_perf_interrupt(int irq, void *dev_id) { return perf_irq(); } @@ -257,8 +155,10 @@ static struct irqaction perf_irqaction = { .name = "performance", }; -void __init plat_perf_setup(struct irqaction *irq) +void __init plat_perf_setup(void) { + struct irqaction *irq = &perf_irqaction; + cp0_perfcount_irq = -1; #ifdef MSC01E_INT_BASE @@ -297,8 +197,6 @@ void __init plat_timer_setup(struct irqaction *irq) mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; } - /* we are using the cpu counter for timer interrupts */ - irq->handler = mips_timer_interrupt; /* we use our own handler */ #ifdef CONFIG_MIPS_MT_SMTC setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq); #else @@ -308,5 +206,5 @@ void __init plat_timer_setup(struct irqaction *irq) set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); #endif - plat_perf_setup(&perf_irqaction); + plat_perf_setup(); } diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c index 9a355e7..3625f7d 100644 --- a/arch/mips/mipssim/sim_time.c +++ b/arch/mips/mipssim/sim_time.c @@ -23,77 +23,6 @@ unsigned long cpu_khz; -irqreturn_t sim_timer_interrupt(int irq, void *dev_id) -{ -#ifdef CONFIG_SMP - int cpu = smp_processor_id(); - - /* - * CPU 0 handles the global timer interrupt job - * resets count/compare registers to trigger next timer int. - */ -#ifndef CONFIG_MIPS_MT_SMTC - if (cpu == 0) { - timer_interrupt(irq, dev_id); - } else { - /* Everyone else needs to reset the timer int here as - ll_local_timer_interrupt doesn't */ - /* - * FIXME: need to cope with counter underflow. - * More support needs to be added to kernel/time for - * counter/timer interrupts on multiple CPU's - */ - write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ)); - } -#else /* SMTC */ - /* - * In SMTC system, one Count/Compare set exists per VPE. - * Which TC within a VPE gets the interrupt is essentially - * random - we only know that it shouldn't be one with - * IXMT set. Whichever TC gets the interrupt needs to - * send special interprocessor interrupts to the other - * TCs to make sure that they schedule, etc. - * - * That code is specific to the SMTC kernel, not to - * the simulation platform, so it's invoked from - * the general MIPS timer_interrupt routine. - * - * We have a problem in that the interrupt vector code - * had to turn off the timer IM bit to avoid redundant - * entries, but we may never get to mips_cpu_irq_end - * to turn it back on again if the scheduler gets - * involved. So we clear the pending timer here, - * and re-enable the mask... - */ - - int vpflags = dvpe(); - write_c0_compare (read_c0_count() - 1); - clear_c0_cause(0x100 << cp0_compare_irq); - set_c0_status(0x100 << cp0_compare_irq); - irq_enable_hazard(); - evpe(vpflags); - - if (cpu_data[cpu].vpe_id == 0) - timer_interrupt(irq, dev_id); - else - write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ)); - smtc_timer_broadcast(cpu_data[cpu].vpe_id); - -#endif /* CONFIG_MIPS_MT_SMTC */ - - /* - * every CPU should do profiling and process accounting - */ - local_timer_interrupt (irq, dev_id); - - return IRQ_HANDLED; -#else - return timer_interrupt (irq, dev_id); -#endif -} - - - /* * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect */ @@ -185,7 +114,6 @@ void __init plat_timer_setup(struct irqaction *irq) } /* we are using the cpu counter for timer interrupts */ - irq->handler = sim_timer_interrupt; setup_irq(mips_cpu_timer_irq, irq); #ifdef CONFIG_SMP diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index 1834832..338c0d7 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c @@ -20,10 +20,10 @@ #include #include #include - #include #include #include +#include /* #define DEBUG_SGINT */ @@ -204,7 +204,6 @@ static struct irqaction map1_cascade = { #define SGI_INTERRUPTS SGINT_LOCAL3 #endif -extern void indy_r4k_timer_interrupt(void); extern void indy_8254timer_irq(void); /* @@ -243,7 +242,7 @@ asmlinkage void plat_irq_dispatch(void) * First we check for r4k counter/timer IRQ. */ if (pending & CAUSEF_IP7) - indy_r4k_timer_interrupt(); + ll_timer_interrupt(SGI_TIMER_IRQ, NULL); else if (pending & CAUSEF_IP2) indy_local0_irqdispatch(); else if (pending & CAUSEF_IP3) diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c index c494180..a1df1f9 100644 --- a/arch/mips/sgi-ip22/ip22-time.c +++ b/arch/mips/sgi-ip22/ip22-time.c @@ -189,16 +189,6 @@ void indy_8254timer_irq(void) irq_exit(); } -void indy_r4k_timer_interrupt(void) -{ - int irq = SGI_TIMER_IRQ; - - irq_enter(); - kstat_this_cpu.irqs[irq]++; - timer_interrupt(irq, NULL); - irq_exit(); -} - void __init plat_timer_setup(struct irqaction *irq) { /* over-write the handler, we use our own way */ diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c index 6f3f71b..8519091 100644 --- a/arch/mips/sibyte/bcm1480/time.c +++ b/arch/mips/sibyte/bcm1480/time.c @@ -103,18 +103,7 @@ void bcm1480_timer_interrupt(void) __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); - if (cpu == 0) { - /* - * CPU 0 handles the global timer interrupt job - */ - ll_timer_interrupt(irq); - } - else { - /* - * other CPUs should just do profiling and process accounting - */ - ll_local_timer_interrupt(irq); - } + ll_timer_interrupt(irq); } static cycle_t bcm1480_hpt_read(void) diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c index 2efffe1..5bb83cd 100644 --- a/arch/mips/sibyte/sb1250/time.c +++ b/arch/mips/sibyte/sb1250/time.c @@ -125,18 +125,7 @@ void sb1250_timer_interrupt(void) ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); - if (cpu == 0) { - /* - * CPU 0 handles the global timer interrupt job - */ - ll_timer_interrupt(irq); - } - else { - /* - * other CPUs should just do profiling and process accounting - */ - ll_local_timer_interrupt(irq); - } + ll_timer_interrupt(irq); } /* diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h index 963507d..3516b32 100644 --- a/include/asm-mips/time.h +++ b/include/asm-mips/time.h @@ -49,20 +49,14 @@ extern void (*mips_timer_ack)(void); extern struct clocksource clocksource_mips; /* - * high-level timer interrupt routines. + * The low-level timer interrupt routine. */ -extern irqreturn_t timer_interrupt(int irq, void *dev_id); - -/* - * the corresponding low-level timer interrupt routine. - */ -extern asmlinkage void ll_timer_interrupt(int irq); +extern void ll_timer_interrupt(int irq, void *dev_id); /* * profiling and process accouting is done separately in local_timer_interrupt */ extern void local_timer_interrupt(int irq, void *dev_id); -extern asmlinkage void ll_local_timer_interrupt(int irq); /* * board specific routines required by time_init(). @@ -78,4 +72,10 @@ extern void plat_timer_setup(struct irqaction *irq); */ extern unsigned int mips_hpt_frequency; +/* + * The performance counter IRQ on MIPS is a close relative to the timer IRQ + * so it lives here. + */ +extern int (*perf_irq)(void); + #endif /* _ASM_TIME_H */ -- cgit v0.10.2 From 7bcf7717b6a047c272410d0cd00213185fe6b99d Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:09 +0100 Subject: [MIPS] Implement clockevents for R4000-style cp0 count/compare interrupt Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 0cd0f83..ecce3aa 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -335,6 +335,7 @@ config QEMU select GENERIC_ISA_DMA select HAVE_STD_PC_SERIAL_PORT select I8259 + select IRQ_CPU select ISA select PCSPEAKER select SWAP_IO_SPACE @@ -667,6 +668,10 @@ config GENERIC_CALIBRATE_DELAY bool default y +config GENERIC_CLOCKEVENTS + bool + default y + config GENERIC_TIME bool default y @@ -901,6 +906,8 @@ config BOOT_ELF64 menu "CPU selection" +source "kernel/time/Kconfig" + choice prompt "CPU type" default CPU_R4X00 diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c index 47949d6..a6640b9 100644 --- a/arch/mips/au1000/common/irq.c +++ b/arch/mips/au1000/common/irq.c @@ -633,7 +633,7 @@ asmlinkage void plat_irq_dispatch(void) unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; if (pending & CAUSEF_IP7) - ll_timer_interrupt(63); + do_IRQ(63); else if (pending & CAUSEF_IP2) intc0_req0_irqdispatch(); else if (pending & CAUSEF_IP3) diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index 700a3a2..30f3e9a 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig @@ -69,7 +69,6 @@ CONFIG_SIBYTE_SB1xxx_SOC=y CONFIG_SIBYTE_CFE=y # CONFIG_SIBYTE_CFE_CONSOLE is not set # CONFIG_SIBYTE_BUS_WATCHER is not set -# CONFIG_SIBYTE_SB1250_PROF is not set # CONFIG_SIBYTE_TBPROF is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig index 93f9e83..3d1b628 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250-swarm_defconfig @@ -70,7 +70,6 @@ CONFIG_SIBYTE_HAS_LDT=y CONFIG_SIBYTE_CFE=y # CONFIG_SIBYTE_CFE_CONSOLE is not set # CONFIG_SIBYTE_BUS_WATCHER is not set -# CONFIG_SIBYTE_SB1250_PROF is not set # CONFIG_SIBYTE_TBPROF is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index aadd2cd..f99bb40 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -52,6 +53,7 @@ void __noreturn cpu_idle(void) { /* endless idle loop with no priority at all */ while (1) { + tick_nohz_stop_sched_tick(); while (!need_resched()) { #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG extern void smtc_idle_loop_hook(void); @@ -61,6 +63,7 @@ void __noreturn cpu_idle(void) if (cpu_wait) (*cpu_wait)(); } + tick_nohz_restart_sched_tick(); preempt_enable_no_resched(); schedule(); preempt_disable(); diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 73b0dab..500a7ec 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -38,6 +38,7 @@ #include #include #include +#include #ifdef CONFIG_MIPS_MT_SMTC #include @@ -70,6 +71,7 @@ asmlinkage __cpuinit void start_secondary(void) cpu_probe(); cpu_report(); per_cpu_trap_init(); + mips_clockevent_init(); prom_init_secondary(); /* diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index a7afbf2..137183b 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -867,7 +867,7 @@ void ipi_decode(struct smtc_ipi *pipi) #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG clock_hang_reported[dest_copy] = 0; #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ - local_timer_interrupt(0); + local_timer_interrupt(0, NULL); irq_exit(); break; case LINUX_SMP_IPI: diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index d23e682..3598884 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -11,6 +11,7 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ +#include #include #include #include @@ -34,6 +35,8 @@ #include #include +#include + /* * The integer part of the number of usecs per jiffy is taken from tick, * but the fractional part is not recorded, so we calculate it using the @@ -70,10 +73,6 @@ int update_persistent_clock(struct timespec now) /* how many counter cycles in a jiffy */ static unsigned long cycles_per_jiffy __read_mostly; -/* expirelo is the count value for next CPU timer interrupt */ -static unsigned int expirelo; - - /* * Null timer ack for systems not needing one (e.g. i8254). */ @@ -92,18 +91,7 @@ static cycle_t null_hpt_read(void) */ static void c0_timer_ack(void) { - unsigned int count; - - /* Ack this timer interrupt and set the next one. */ - expirelo += cycles_per_jiffy; - write_c0_compare(expirelo); - - /* Check to see if we have missed any timer interrupts. */ - while (((count = read_c0_count()) - expirelo) < 0x7fffffff) { - /* missed_timer_count++; */ - expirelo = count + cycles_per_jiffy; - write_c0_compare(expirelo); - } + write_c0_compare(read_c0_compare()); } /* @@ -114,13 +102,6 @@ static cycle_t c0_hpt_read(void) return read_c0_count(); } -/* For use both as a high precision timer and an interrupt source. */ -static void __init c0_hpt_timer_init(void) -{ - expirelo = read_c0_count() + cycles_per_jiffy; - write_c0_compare(expirelo); -} - int (*mips_timer_state)(void); void (*mips_timer_ack)(void); @@ -140,35 +121,6 @@ void local_timer_interrupt(int irq, void *dev_id) update_process_times(user_mode(get_irq_regs())); } -/* - * High-level timer interrupt service routines. This function - * is set as irqaction->handler and is invoked through do_IRQ. - */ -static irqreturn_t timer_interrupt(int irq, void *dev_id) -{ - write_seqlock(&xtime_lock); - - mips_timer_ack(); - - /* - * call the generic timer interrupt handling - */ - do_timer(1); - - write_sequnlock(&xtime_lock); - - /* - * In UP mode, we call local_timer_interrupt() to do profiling - * and process accouting. - * - * In SMP mode, local_timer_interrupt() is invoked by appropriate - * low-level local timer interrupt handler. - */ - local_timer_interrupt(irq, dev_id); - - return IRQ_HANDLED; -} - int null_perf_irq(void) { return 0; @@ -209,81 +161,6 @@ static inline int handle_perf_irq (int r2) !r2; } -void ll_timer_interrupt(int irq, void *dev_id) -{ - int cpu = smp_processor_id(); - -#ifdef CONFIG_MIPS_MT_SMTC - /* - * In an SMTC system, one Count/Compare set exists per VPE. - * Which TC within a VPE gets the interrupt is essentially - * random - we only know that it shouldn't be one with - * IXMT set. Whichever TC gets the interrupt needs to - * send special interprocessor interrupts to the other - * TCs to make sure that they schedule, etc. - * - * That code is specific to the SMTC kernel, not to - * the a particular platform, so it's invoked from - * the general MIPS timer_interrupt routine. - */ - - /* - * We could be here due to timer interrupt, - * perf counter overflow, or both. - */ - (void) handle_perf_irq(1); - - if (read_c0_cause() & (1 << 30)) { - /* - * There are things we only want to do once per tick - * in an "MP" system. One TC of each VPE will take - * the actual timer interrupt. The others will get - * timer broadcast IPIs. We use whoever it is that takes - * the tick on VPE 0 to run the full timer_interrupt(). - */ - if (cpu_data[cpu].vpe_id == 0) { - timer_interrupt(irq, NULL); - } else { - write_c0_compare(read_c0_count() + - (mips_hpt_frequency/HZ)); - local_timer_interrupt(irq, dev_id); - } - smtc_timer_broadcast(cpu_data[cpu].vpe_id); - } -#else /* CONFIG_MIPS_MT_SMTC */ - int r2 = cpu_has_mips_r2; - - if (handle_perf_irq(r2)) - return; - - if (r2 && ((read_c0_cause() & (1 << 30)) == 0)) - return; - - if (cpu == 0) { - /* - * CPU 0 handles the global timer interrupt job and process - * accounting resets count/compare registers to trigger next - * timer int. - */ - timer_interrupt(irq, NULL); - } else { - /* Everyone else needs to reset the timer int here as - ll_local_timer_interrupt doesn't */ - /* - * FIXME: need to cope with counter underflow. - * More support needs to be added to kernel/time for - * counter/timer interrupts on multiple CPU's - */ - write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ)); - - /* - * Other CPUs should do profiling and process accounting - */ - local_timer_interrupt(irq, dev_id); - } -#endif /* CONFIG_MIPS_MT_SMTC */ -} - /* * time_init() - it does the following things. * @@ -301,12 +178,6 @@ void ll_timer_interrupt(int irq, void *dev_id) unsigned int mips_hpt_frequency; -static struct irqaction timer_irqaction = { - .handler = timer_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU, - .name = "timer", -}; - static unsigned int __init calibrate_hpt(void) { cycle_t frequency, hpt_start, hpt_end, hpt_count, hz; @@ -355,6 +226,65 @@ struct clocksource clocksource_mips = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; +static int mips_next_event(unsigned long delta, + struct clock_event_device *evt) +{ + unsigned int cnt; + + cnt = read_c0_count(); + cnt += delta; + write_c0_compare(cnt); + + return ((long)(read_c0_count() - cnt ) > 0) ? -ETIME : 0; +} + +static void mips_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + /* Nothing to do ... */ +} + +struct clock_event_device mips_clockevent; + +static struct clock_event_device *global_cd[NR_CPUS]; +static int cp0_timer_irq_installed; + +static irqreturn_t timer_interrupt(int irq, void *dev_id) +{ + const int r2 = cpu_has_mips_r2; + struct clock_event_device *cd; + int cpu = smp_processor_id(); + + /* + * Suckage alert: + * Before R2 of the architecture there was no way to see if a + * performance counter interrupt was pending, so we have to run + * the performance counter interrupt handler anyway. + */ + if (handle_perf_irq(r2)) + goto out; + + /* + * The same applies to performance counter interrupts. But with the + * above we now know that the reason we got here must be a timer + * interrupt. Being the paranoiacs we are we check anyway. + */ + if (!r2 || (read_c0_cause() & (1 << 30))) { + c0_timer_ack(); + cd = global_cd[cpu]; + cd->event_handler(cd); + } + +out: + return IRQ_HANDLED; +} + +static struct irqaction timer_irqaction = { + .handler = timer_interrupt, + .flags = IRQF_DISABLED | IRQF_PERCPU, + .name = "timer", +}; + static void __init init_mips_clocksource(void) { u64 temp; @@ -382,6 +312,56 @@ void __init __weak plat_time_init(void) { } +void __init __weak plat_timer_setup(struct irqaction *irq) +{ +} + +void __cpuinit mips_clockevent_init(void) +{ + uint64_t mips_freq = mips_hpt_frequency; + unsigned int cpu = smp_processor_id(); + struct clock_event_device *cd; + unsigned int irq = MIPS_CPU_IRQ_BASE + 7; + + if (!cpu_has_counter) + return; + + if (cpu == 0) + cd = &mips_clockevent; + else + cd = kzalloc(sizeof(*cd), GFP_ATOMIC); + if (!cd) + return; /* We're probably roadkill ... */ + + cd->name = "MIPS"; + cd->features = CLOCK_EVT_FEAT_ONESHOT; + + /* Calculate the min / max delta */ + cd->mult = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32); + cd->shift = 32; + cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd); + cd->min_delta_ns = clockevent_delta2ns(0x30, cd); + + cd->rating = 300; + cd->irq = irq; + cd->cpumask = cpumask_of_cpu(cpu); + cd->set_next_event = mips_next_event; + cd->set_mode = mips_set_mode; + + global_cd[cpu] = cd; + clockevents_register_device(cd); + + if (!cp0_timer_irq_installed) { +#ifdef CONFIG_MIPS_MT_SMTC +#define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq) + setup_irq_smtc(irq, &timer_irqaction, CPUCTR_IMASKBIT); +#else + setup_irq(irq, &timer_irqaction); +#endif /* CONFIG_MIPS_MT_SMTC */ + cp0_timer_irq_installed = 1; + } +} + void __init time_init(void) { plat_time_init(); @@ -407,11 +387,6 @@ void __init time_init(void) /* Calculate cache parameters. */ cycles_per_jiffy = (mips_hpt_frequency + HZ / 2) / HZ; - /* - * This sets up the high precision - * timer for the first interrupt. - */ - c0_hpt_timer_init(); } } if (!mips_hpt_frequency) @@ -421,6 +396,10 @@ void __init time_init(void) printk("Using %u.%03u MHz high precision timer.\n", ((mips_hpt_frequency + 500) / 1000) / 1000, ((mips_hpt_frequency + 500) / 1000) % 1000); + +#ifdef CONFIG_IRQ_CPU + setup_irq(MIPS_CPU_IRQ_BASE + 7, &timer_irqaction); +#endif } if (!mips_timer_ack) @@ -441,4 +420,5 @@ void __init time_init(void) plat_timer_setup(&timer_irqaction); init_mips_clocksource(); + mips_clockevent_init(); } diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index 345de88..2c8db3e 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -144,20 +144,20 @@ void __init plat_time_init(void) mips_scroll_message(); } -static irqreturn_t mips_perf_interrupt(int irq, void *dev_id) -{ - return perf_irq(); -} +//static irqreturn_t mips_perf_interrupt(int irq, void *dev_id) +//{ +// return perf_irq(); +//} -static struct irqaction perf_irqaction = { - .handler = mips_perf_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU, - .name = "performance", -}; +//static struct irqaction perf_irqaction = { +// .handler = mips_perf_interrupt, +// .flags = IRQF_DISABLED | IRQF_PERCPU, +// .name = "performance", +//}; void __init plat_perf_setup(void) { - struct irqaction *irq = &perf_irqaction; +// struct irqaction *irq = &perf_irqaction; cp0_perfcount_irq = -1; @@ -170,12 +170,6 @@ void __init plat_perf_setup(void) if (cp0_perfcount_irq >= 0) { if (cpu_has_vint) set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); -#ifdef CONFIG_MIPS_MT_SMTC - setup_irq_smtc(cp0_perfcount_irq, irq, - 0x100 << cp0_perfcount_irq); -#else - setup_irq(cp0_perfcount_irq, irq); -#endif /* CONFIG_MIPS_MT_SMTC */ #ifdef CONFIG_SMP set_irq_handler(cp0_perfcount_irq, handle_percpu_irq); #endif diff --git a/arch/mips/qemu/q-irq.c b/arch/mips/qemu/q-irq.c index 89891e9..4681757 100644 --- a/arch/mips/qemu/q-irq.c +++ b/arch/mips/qemu/q-irq.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -12,7 +13,7 @@ asmlinkage void plat_irq_dispatch(void) unsigned int pending = read_c0_status() & read_c0_cause(); if (pending & 0x8000) { - ll_timer_interrupt(Q_COUNT_COMPARE_IRQ); + do_IRQ(Q_COUNT_COMPARE_IRQ); return; } if (pending & 0x0400) { @@ -29,6 +30,7 @@ void __init arch_init_irq(void) { mips_hpt_frequency = QEMU_C0_COUNTER_CLOCK; /* 100MHz */ + mips_cpu_irq_init(); init_i8259_irqs(); set_c0_status(0x8400); } diff --git a/arch/mips/qemu/q-setup.c b/arch/mips/qemu/q-setup.c index 8413943..89a2076 100644 --- a/arch/mips/qemu/q-setup.c +++ b/arch/mips/qemu/q-setup.c @@ -17,7 +17,6 @@ void __init plat_timer_setup(struct irqaction *irq) outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */ outb_p(LATCH & 0xff , 0x40); /* LSB */ outb(LATCH >> 8 , 0x40); /* MSB */ - setup_irq(0, irq); } void __init plat_mem_setup(void) diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index 338c0d7..f199da7 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c @@ -242,7 +242,7 @@ asmlinkage void plat_irq_dispatch(void) * First we check for r4k counter/timer IRQ. */ if (pending & CAUSEF_IP7) - ll_timer_interrupt(SGI_TIMER_IRQ, NULL); + do_IRQ(SGI_TIMER_IRQ); else if (pending & CAUSEF_IP2) indy_local0_irqdispatch(); else if (pending & CAUSEF_IP3) diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index 5bad1b7..002095b 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c @@ -457,7 +457,7 @@ static void ip32_irq4(void) static void ip32_irq5(void) { - ll_timer_interrupt(IP32_R4K_TIMER_IRQ); + do_IRQ(IP32_R4K_TIMER_IRQ); } asmlinkage void plat_irq_dispatch(void) diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig index 841b301..e8fb880 100644 --- a/arch/mips/sibyte/Kconfig +++ b/arch/mips/sibyte/Kconfig @@ -1,6 +1,7 @@ config SIBYTE_SB1250 bool select HW_HAS_PCI + select IRQ_CPU select SIBYTE_ENABLE_LDT_IF_PCI select SIBYTE_HAS_ZBUS_PROFILING select SIBYTE_SB1xxx_SOC @@ -8,6 +9,7 @@ config SIBYTE_SB1250 config SIBYTE_BCM1120 bool + select IRQ_CPU select SIBYTE_BCM112X select SIBYTE_HAS_ZBUS_PROFILING select SIBYTE_SB1xxx_SOC @@ -15,6 +17,7 @@ config SIBYTE_BCM1120 config SIBYTE_BCM1125 bool select HW_HAS_PCI + select IRQ_CPU select SIBYTE_BCM112X select SIBYTE_HAS_ZBUS_PROFILING select SIBYTE_SB1xxx_SOC @@ -22,6 +25,7 @@ config SIBYTE_BCM1125 config SIBYTE_BCM1125H bool select HW_HAS_PCI + select IRQ_CPU select SIBYTE_BCM112X select SIBYTE_ENABLE_LDT_IF_PCI select SIBYTE_HAS_ZBUS_PROFILING @@ -29,12 +33,14 @@ config SIBYTE_BCM1125H config SIBYTE_BCM112X bool + select IRQ_CPU select SIBYTE_SB1xxx_SOC select SIBYTE_HAS_ZBUS_PROFILING config SIBYTE_BCM1x80 bool select HW_HAS_PCI + select IRQ_CPU select SIBYTE_HAS_ZBUS_PROFILING select SIBYTE_SB1xxx_SOC select SYS_SUPPORTS_SMP @@ -42,6 +48,7 @@ config SIBYTE_BCM1x80 config SIBYTE_BCM1x55 bool select HW_HAS_PCI + select IRQ_CPU select SIBYTE_SB1xxx_SOC select SIBYTE_HAS_ZBUS_PROFILING select SYS_SUPPORTS_SMP @@ -49,6 +56,7 @@ config SIBYTE_BCM1x55 config SIBYTE_SB1xxx_SOC bool select DMA_COHERENT + select IRQ_CPU select SIBYTE_CFE select SWAP_IO_SPACE select SYS_SUPPORTS_32BIT_KERNEL @@ -166,10 +174,6 @@ config SIBYTE_BW_TRACE buffer activity. Raw buffer data is dumped to console, and must be processed off-line. -config SIBYTE_SB1250_PROF - bool "Support for SB1/SOC profiling - SB1/SCD perf counters" - depends on SIBYTE_SB1xxx_SOC - config SIBYTE_TBPROF tristate "Support for ZBbus profiling" depends on SIBYTE_HAS_ZBUS_PROFILING diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c index e729b5f..cf979db 100644 --- a/arch/mips/sibyte/bcm1480/irq.c +++ b/arch/mips/sibyte/bcm1480/irq.c @@ -450,7 +450,6 @@ static void bcm1480_kgdb_interrupt(void) #endif /* CONFIG_KGDB */ -extern void bcm1480_timer_interrupt(void); extern void bcm1480_mailbox_interrupt(void); asmlinkage void plat_irq_dispatch(void) @@ -470,8 +469,16 @@ asmlinkage void plat_irq_dispatch(void) else #endif - if (pending & CAUSEF_IP4) - bcm1480_timer_interrupt(); + if (pending & CAUSEF_IP4) { + int cpu = smp_processor_id(); + int irq = K_BCM1480_INT_TIMER_0 + cpu; + + /* Reset the timer */ + __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, + IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); + + do_IRQ(irq); + } #ifdef CONFIG_SMP else if (pending & CAUSEF_IP3) diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index ad593a6..6a4cc84 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -399,18 +400,45 @@ static void sb1250_kgdb_interrupt(void) #endif /* CONFIG_KGDB */ -extern void sb1250_timer_interrupt(void); +static inline void sb1250_timer_interrupt(void) +{ + int cpu = smp_processor_id(); + int irq = K_INT_TIMER_0 + cpu; + + irq_enter(); + kstat_this_cpu.irqs[irq]++; + + write_seqlock(&xtime_lock); + + /* ACK interrupt */ + ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, + IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); + + /* + * call the generic timer interrupt handling + */ + do_timer(1); + + write_sequnlock(&xtime_lock); + + /* + * In UP mode, we call local_timer_interrupt() to do profiling + * and process accouting. + * + * In SMP mode, local_timer_interrupt() is invoked by appropriate + * low-level local timer interrupt handler. + */ + local_timer_interrupt(irq); + + irq_exit(); +} + extern void sb1250_mailbox_interrupt(void); asmlinkage void plat_irq_dispatch(void) { unsigned int pending; -#ifdef CONFIG_SIBYTE_SB1250_PROF - /* Set compare to count to silence count/compare timer interrupts */ - write_c0_compare(read_c0_count()); -#endif - /* * What a pain. We have to be really careful saving the upper 32 bits * of any * register across function calls if we don't want them @@ -423,13 +451,9 @@ asmlinkage void plat_irq_dispatch(void) pending = read_c0_cause() & read_c0_status() & ST0_IM; -#ifdef CONFIG_SIBYTE_SB1250_PROF - if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */ - sbprof_cpu_intr(); - else -#endif - - if (pending & CAUSEF_IP4) + if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */ + do_IRQ(MIPS_CPU_IRQ_BASE + 7); + else if (pending & CAUSEF_IP4) sb1250_timer_interrupt(); #ifdef CONFIG_SMP diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c index 5bb83cd..eb17707 100644 --- a/arch/mips/sibyte/sb1250/time.c +++ b/arch/mips/sibyte/sb1250/time.c @@ -116,18 +116,6 @@ void sb1250_time_init(void) */ } -void sb1250_timer_interrupt(void) -{ - int cpu = smp_processor_id(); - int irq = K_INT_TIMER_0 + cpu; - - /* ACK interrupt */ - ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, - IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); - - ll_timer_interrupt(irq); -} - /* * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over * again. diff --git a/include/asm-mips/mach-ip27/irq.h b/include/asm-mips/mach-ip27/irq.h index 25f0c3f..cf4384b 100644 --- a/include/asm-mips/mach-ip27/irq.h +++ b/include/asm-mips/mach-ip27/irq.h @@ -17,4 +17,6 @@ */ #define NR_IRQS 256 +#include_next + #endif /* __ASM_MACH_IP27_IRQ_H */ diff --git a/include/asm-mips/qemu.h b/include/asm-mips/qemu.h index 531caf4..487ced4 100644 --- a/include/asm-mips/qemu.h +++ b/include/asm-mips/qemu.h @@ -12,7 +12,7 @@ * Interrupt numbers */ #define Q_PIC_IRQ_BASE 0 -#define Q_COUNT_COMPARE_IRQ 16 +#define Q_COUNT_COMPARE_IRQ 23 /* * Qemu clock rate. Unlike on real MIPS this has no relation to the diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h index 3516b32..35555bd 100644 --- a/include/asm-mips/time.h +++ b/include/asm-mips/time.h @@ -49,11 +49,6 @@ extern void (*mips_timer_ack)(void); extern struct clocksource clocksource_mips; /* - * The low-level timer interrupt routine. - */ -extern void ll_timer_interrupt(int irq, void *dev_id); - -/* * profiling and process accouting is done separately in local_timer_interrupt */ extern void local_timer_interrupt(int irq, void *dev_id); @@ -78,4 +73,9 @@ extern unsigned int mips_hpt_frequency; */ extern int (*perf_irq)(void); +/* + * Initialize the calling CPU's compare interrupt as clockevent device + */ +extern void mips_clockevent_init(void); + #endif /* _ASM_TIME_H */ -- cgit v0.10.2 From ea5804015c0ce67741eb4b156a071fb4f415345f Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:09 +0100 Subject: [MIPS] Dyntick support for SMTC: The kernel currently only supports broadcasting of the timer interrupt from a single timer, not multicasting into two multicast groups of processors. So the implemented mechanism for SMTC works by broadcasting the cp0 compare interrupt on VPE 0 and ignoring it on any additional VPEs. Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ecce3aa..d8c9058 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1368,6 +1368,7 @@ config MIPS_MT_SMTC depends on CPU_MIPS32_R2 #depends on CPU_MIPS64_R2 # once there is hardware ... depends on SYS_SUPPORTS_MULTITHREADING + select GENERIC_CLOCKEVENTS_BROADCAST select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI select CPU_MIPSR2_SRS @@ -1537,6 +1538,9 @@ config CPU_HAS_SYNC depends on !CPU_R3000 default y +config GENERIC_CLOCKEVENTS_BROADCAST + bool + # # Use the generic interrupt handling code in kernel/irq/: # diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 137183b..4d1ac96 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -1,5 +1,6 @@ /* Copyright (C) 2004 Mips Technologies, Inc */ +#include #include #include #include @@ -62,7 +63,7 @@ asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; * Clock interrupt "latch" buffers, per "CPU" */ -unsigned int ipi_timer_latch[NR_CPUS]; +static atomic_t ipi_timer_latch[NR_CPUS]; /* * Number of InterProcessor Interupt (IPI) message buffers to allocate @@ -296,8 +297,10 @@ int __init mipsmt_build_cpu_map(int start_cpu_slot) __cpu_number_map[i] = i; __cpu_logical_map[i] = i; } +#ifdef CONFIG_MIPS_MT_FPAFF /* Initialize map of CPUs with FPUs */ cpus_clear(mt_fpu_cpumask); +#endif /* One of those TC's is the one booting, and not a secondary... */ printk("%i available secondary CPU TC(s)\n", i - 1); @@ -359,7 +362,7 @@ void mipsmt_prepare_cpus(void) IPIQ[i].head = IPIQ[i].tail = NULL; spin_lock_init(&IPIQ[i].lock); IPIQ[i].depth = 0; - ipi_timer_latch[i] = 0; + atomic_set(&ipi_timer_latch[i], 0); } /* cpu_data index starts at zero */ @@ -482,10 +485,12 @@ void mipsmt_prepare_cpus(void) /* Set up coprocessor affinity CPU mask(s) */ +#ifdef CONFIG_MIPS_MT_FPAFF for (tc = 0; tc < ntc; tc++) { if (cpu_data[tc].options & MIPS_CPU_FPU) cpu_set(tc, mt_fpu_cpumask); } +#endif /* set up ipi interrupts... */ @@ -702,7 +707,7 @@ static void smtc_ipi_qdump(void) * be done with the atomic.h primitives). And since this is * MIPS MT, we can assume that we have LL/SC. */ -static __inline__ int atomic_postincrement(unsigned int *pv) +static inline int atomic_postincrement(atomic_t *v) { unsigned long result; @@ -714,8 +719,8 @@ static __inline__ int atomic_postincrement(unsigned int *pv) " sc %1, %2 \n" " beqz %1, 1b \n" __WEAK_LLSC_MB - : "=&r" (result), "=&r" (temp), "=m" (*pv) - : "m" (*pv) + : "=&r" (result), "=&r" (temp), "=m" (v->counter) + : "m" (v->counter) : "memory"); return result; @@ -743,6 +748,8 @@ void smtc_send_ipi(int cpu, int type, unsigned int action) pipi->arg = (void *)action; pipi->dest = cpu; if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { + if (type == SMTC_CLOCK_TICK) + atomic_inc(&ipi_timer_latch[cpu]); /* If not on same VPE, enqueue and send cross-VPE interupt */ smtc_ipi_nq(&IPIQ[cpu], pipi); LOCK_CORE_PRA(); @@ -784,6 +791,8 @@ void smtc_send_ipi(int cpu, int type, unsigned int action) } smtc_ipi_nq(&IPIQ[cpu], pipi); } else { + if (type == SMTC_CLOCK_TICK) + atomic_inc(&ipi_timer_latch[cpu]); post_direct_ipi(cpu, pipi); write_tc_c0_tchalt(0); UNLOCK_CORE_PRA(); @@ -801,6 +810,7 @@ static void post_direct_ipi(int cpu, struct smtc_ipi *pipi) unsigned long tcrestart; extern u32 kernelsp[NR_CPUS]; extern void __smtc_ipi_vector(void); +//printk("%s: on %d for %d\n", __func__, smp_processor_id(), cpu); /* Extract Status, EPC from halted TC */ tcstatus = read_tc_c0_tcstatus(); @@ -851,25 +861,31 @@ static void ipi_call_interrupt(void) smp_call_function_interrupt(); } +DECLARE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device); + void ipi_decode(struct smtc_ipi *pipi) { + unsigned int cpu = smp_processor_id(); + struct clock_event_device *cd; void *arg_copy = pipi->arg; int type_copy = pipi->type; - int dest_copy = pipi->dest; + int ticks; smtc_ipi_nq(&freeIPIq, pipi); switch (type_copy) { case SMTC_CLOCK_TICK: irq_enter(); - kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + cp0_compare_irq]++; - /* Invoke Clock "Interrupt" */ - ipi_timer_latch[dest_copy] = 0; -#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG - clock_hang_reported[dest_copy] = 0; -#endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ - local_timer_interrupt(0, NULL); + kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + 1]++; + cd = &per_cpu(smtc_dummy_clockevent_device, cpu); + ticks = atomic_read(&ipi_timer_latch[cpu]); + atomic_sub(ticks, &ipi_timer_latch[cpu]); + while (ticks) { + cd->event_handler(cd); + ticks--; + } irq_exit(); break; + case LINUX_SMP_IPI: switch ((int)arg_copy) { case SMP_RESCHEDULE_YOURSELF: @@ -921,25 +937,6 @@ void deferred_smtc_ipi(void) } /* - * Send clock tick to all TCs except the one executing the funtion - */ - -void smtc_timer_broadcast(void) -{ - int cpu; - int myTC = cpu_data[smp_processor_id()].tc_id; - int myVPE = cpu_data[smp_processor_id()].vpe_id; - - smtc_cpu_stats[smp_processor_id()].timerints++; - - for_each_online_cpu(cpu) { - if (cpu_data[cpu].vpe_id == myVPE && - cpu_data[cpu].tc_id != myTC) - smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0); - } -} - -/* * Cross-VPE interrupts in the SMTC prototype use "software interrupts" * set via cross-VPE MTTR manipulation of the Cause register. It would be * in some regards preferable to have external logic for "doorbell" hardware @@ -1180,11 +1177,11 @@ void smtc_idle_loop_hook(void) for (tc = 0; tc < NR_CPUS; tc++) { /* Don't check ourself - we'll dequeue IPIs just below */ if ((tc != smp_processor_id()) && - ipi_timer_latch[tc] > timerq_limit) { + atomic_read(&ipi_timer_latch[tc]) > timerq_limit) { if (clock_hang_reported[tc] == 0) { pdb_msg += sprintf(pdb_msg, "TC %d looks hung with timer latch at %d\n", - tc, ipi_timer_latch[tc]); + tc, atomic_read(&ipi_timer_latch[tc])); clock_hang_reported[tc]++; } } @@ -1225,7 +1222,7 @@ void smtc_soft_dump(void) smtc_ipi_qdump(); printk("Timer IPI Backlogs:\n"); for (i=0; i < NR_CPUS; i++) { - printk("%d: %d\n", i, ipi_timer_latch[i]); + printk("%d: %d\n", i, atomic_read(&ipi_timer_latch[i])); } printk("%d Recoveries of \"stolen\" FPU\n", atomic_read(&smtc_fpu_recoveries)); diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 3598884..369a5f9 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -33,6 +34,7 @@ #include #include #include +#include #include #include @@ -230,12 +232,24 @@ static int mips_next_event(unsigned long delta, struct clock_event_device *evt) { unsigned int cnt; + int res; +#ifdef CONFIG_MIPS_MT_SMTC + { + unsigned long flags, vpflags; + local_irq_save(flags); + vpflags = dvpe(); +#endif cnt = read_c0_count(); cnt += delta; write_c0_compare(cnt); - - return ((long)(read_c0_count() - cnt ) > 0) ? -ETIME : 0; + res = ((long)(read_c0_count() - cnt ) > 0) ? -ETIME : 0; +#ifdef CONFIG_MIPS_MT_SMTC + evpe(vpflags); + local_irq_restore(flags); + } +#endif + return res; } static void mips_set_mode(enum clock_event_mode mode, @@ -244,9 +258,7 @@ static void mips_set_mode(enum clock_event_mode mode, /* Nothing to do ... */ } -struct clock_event_device mips_clockevent; - -static struct clock_event_device *global_cd[NR_CPUS]; +static DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device); static int cp0_timer_irq_installed; static irqreturn_t timer_interrupt(int irq, void *dev_id) @@ -271,7 +283,12 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id) */ if (!r2 || (read_c0_cause() & (1 << 30))) { c0_timer_ack(); - cd = global_cd[cpu]; +#ifdef CONFIG_MIPS_MT_SMTC + if (cpu_data[cpu].vpe_id) + goto out; + cpu = 0; +#endif + cd = &per_cpu(mips_clockevent_device, cpu); cd->event_handler(cd); } @@ -281,7 +298,11 @@ out: static struct irqaction timer_irqaction = { .handler = timer_interrupt, +#ifdef CONFIG_MIPS_MT_SMTC + .flags = IRQF_DISABLED, +#else .flags = IRQF_DISABLED | IRQF_PERCPU, +#endif .name = "timer", }; @@ -316,6 +337,60 @@ void __init __weak plat_timer_setup(struct irqaction *irq) { } +#ifdef CONFIG_MIPS_MT_SMTC +DEFINE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device); + +static void smtc_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ +} + +int dummycnt[NR_CPUS]; + +static void mips_broadcast(cpumask_t mask) +{ + unsigned int cpu; + + for_each_cpu_mask(cpu, mask) + smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0); +} + +static void setup_smtc_dummy_clockevent_device(void) +{ + //uint64_t mips_freq = mips_hpt_^frequency; + unsigned int cpu = smp_processor_id(); + struct clock_event_device *cd; + + cd = &per_cpu(smtc_dummy_clockevent_device, cpu); + + cd->name = "SMTC"; + cd->features = CLOCK_EVT_FEAT_DUMMY; + + /* Calculate the min / max delta */ + cd->mult = 0; //div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32); + cd->shift = 0; //32; + cd->max_delta_ns = 0; //clockevent_delta2ns(0x7fffffff, cd); + cd->min_delta_ns = 0; //clockevent_delta2ns(0x30, cd); + + cd->rating = 200; + cd->irq = 17; //-1; +// if (cpu) +// cd->cpumask = CPU_MASK_ALL; // cpumask_of_cpu(cpu); +// else + cd->cpumask = cpumask_of_cpu(cpu); + + cd->set_mode = smtc_set_mode; + + cd->broadcast = mips_broadcast; + + clockevents_register_device(cd); +} +#endif + +static void mips_event_handler(struct clock_event_device *dev) +{ +} + void __cpuinit mips_clockevent_init(void) { uint64_t mips_freq = mips_hpt_frequency; @@ -326,12 +401,18 @@ void __cpuinit mips_clockevent_init(void) if (!cpu_has_counter) return; - if (cpu == 0) - cd = &mips_clockevent; - else - cd = kzalloc(sizeof(*cd), GFP_ATOMIC); - if (!cd) - return; /* We're probably roadkill ... */ +#ifdef CONFIG_MIPS_MT_SMTC + setup_smtc_dummy_clockevent_device(); + + /* + * On SMTC we only register VPE0's compare interrupt as clockevent + * device. + */ + if (cpu) + return; +#endif + + cd = &per_cpu(mips_clockevent_device, cpu); cd->name = "MIPS"; cd->features = CLOCK_EVT_FEAT_ONESHOT; @@ -344,11 +425,15 @@ void __cpuinit mips_clockevent_init(void) cd->rating = 300; cd->irq = irq; +#ifdef CONFIG_MIPS_MT_SMTC + cd->cpumask = CPU_MASK_ALL; +#else cd->cpumask = cpumask_of_cpu(cpu); +#endif cd->set_next_event = mips_next_event; cd->set_mode = mips_set_mode; + cd->event_handler = mips_event_handler; - global_cd[cpu] = cd; clockevents_register_device(cd); if (!cp0_timer_irq_installed) { diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index 2c8db3e..cf55ecd 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -55,7 +55,6 @@ unsigned long cpu_khz; static int mips_cpu_timer_irq; extern int cp0_perfcount_irq; -extern void smtc_timer_broadcast(void); static void mips_timer_dispatch(void) { -- cgit v0.10.2 From 584d98be3b90f00b410288e59eeba871fbf81b86 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:09 +0100 Subject: [MIPS] Jazz clockevent driver Signed-off-by: Ralf Baechle diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index 5623541..835b056 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c @@ -6,6 +6,7 @@ * Copyright (C) 1992 Linus Torvalds * Copyright (C) 1994 - 2001, 2003 Ralf Baechle */ +#include #include #include #include @@ -105,3 +106,50 @@ asmlinkage void plat_irq_dispatch(void) panic("Unimplemented loc_no_irq handler"); } } + +static void r4030_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + /* Nothing to do ... */ +} + +struct clock_event_device r4030_clockevent = { + .name = "r4030", + .features = CLOCK_EVT_FEAT_PERIODIC, + .rating = 100, + .irq = JAZZ_TIMER_IRQ, + .cpumask = CPU_MASK_CPU0, + .set_mode = r4030_set_mode, +}; + +static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id) +{ + r4030_clockevent.event_handler(&r4030_clockevent); + + return IRQ_HANDLED; +} + +static struct irqaction r4030_timer_irqaction = { + .handler = r4030_timer_interrupt, + .flags = IRQF_DISABLED, + .mask = CPU_MASK_CPU0, + .name = "timer", +}; + +void __init plat_timer_setup(struct irqaction *ignored) +{ + struct irqaction *irq = &r4030_timer_irqaction; + + BUG_ON(HZ != 100); + + /* + * Set clock to 100Hz. + * + * The R4030 timer receives an input clock of 1kHz which is divieded by + * a programmable 4-bit divider. This makes it fairly inflexible. + */ + r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9); + setup_irq(JAZZ_TIMER_IRQ, irq); + + clockevents_register_device(&r4030_clockevent); +} diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c index 5c6271a..fa890df 100644 --- a/arch/mips/jazz/setup.c +++ b/arch/mips/jazz/setup.c @@ -39,13 +39,6 @@ extern asmlinkage void jazz_handle_int(void); extern void jazz_machine_restart(char *command); -void __init plat_timer_setup(struct irqaction *irq) -{ - /* set the clock to 100 Hz */ - r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9); - setup_irq(JAZZ_TIMER_IRQ, irq); -} - static struct resource jazz_io_resources[] = { { .start = 0x00, -- cgit v0.10.2 From 87b2335d6ef97e19ca19dbbb523673680a029e3f Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:10 +0100 Subject: [MIPS] IP27: Add clocksource drivers Signed-off-by: Ralf Baechle diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index 9c1700e..b7b3479 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -200,15 +200,23 @@ void __init plat_timer_setup(struct irqaction *irq) setup_irq(irqno, &rt_irqaction); } -static cycle_t ip27_hpt_read(void) +static cycle_t hub_rt_read(void) { return REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT); } +struct clocksource ht_rt_clocksource = { + .name = "HUB", + .rating = 200, + .read = hub_rt_read, + .mask = CLOCKSOURCE_MASK(52), + .shift = 32, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + void __init plat_time_init(void) { - clocksource_mips.read = ip27_hpt_read; - mips_hpt_frequency = CYCLES_PER_SEC; + clocksource_register(&ht_rt_clocksource); } void __init cpu_time_init(void) -- cgit v0.10.2 From d865bea4dace1d42995a6cf552bc4863842623f4 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:10 +0100 Subject: [MIPS] i8253 PIT clocksource and clockevent drivers Derived from the i386 variant with a few x86 complexities chopped off. Signed-off-by: Ralf Baechle diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d8c9058..f943736 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -65,6 +65,7 @@ config MIPS_COBALT bool "Cobalt Server" select DMA_NONCOHERENT select HW_HAS_PCI + select I8253 select I8259 select IRQ_CPU select IRQ_GT641XX @@ -112,6 +113,7 @@ config MACH_JAZZ select ARCH_MAY_HAVE_PC_FDC select GENERIC_ISA_DMA select IRQ_CPU + select I8253 select I8259 select ISA select PCSPEAKER @@ -201,6 +203,7 @@ config MIPS_MALTA select GENERIC_ISA_DMA select IRQ_CPU select HW_HAS_PCI + select I8253 select I8259 select MIPS_BOARDS_GEN select MIPS_BONITO64 @@ -334,6 +337,7 @@ config QEMU select DMA_COHERENT select GENERIC_ISA_DMA select HAVE_STD_PC_SERIAL_PORT + select I8253 select I8259 select IRQ_CPU select ISA @@ -362,6 +366,7 @@ config SGI_IP22 select BOOT_ELF32 select DMA_NONCOHERENT select HW_HAS_EISA + select I8253 select IP22_CPU_SCACHE select IRQ_CPU select GENERIC_ISA_DMA_SUPPORT_BROKEN @@ -534,6 +539,7 @@ config SNI_RM select HW_HAS_EISA select HW_HAS_PCI select IRQ_CPU + select I8253 select I8259 select ISA select PCSPEAKER @@ -1893,6 +1899,9 @@ config MMU bool default y +config I8253 + bool + config PCSPEAKER bool diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c index 5d2e879..345e4ae 100644 --- a/arch/mips/cobalt/setup.c +++ b/arch/mips/cobalt/setup.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -84,6 +85,11 @@ static struct resource cobalt_reserved_resources[] = { }, }; +void __init plat_time_init(void) +{ + setup_pit_timer(); +} + void __init plat_mem_setup(void) { int i; diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c index fa890df..2a7ec08 100644 --- a/arch/mips/jazz/setup.c +++ b/arch/mips/jazz/setup.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include @@ -63,6 +64,11 @@ static struct resource jazz_io_resources[] = { } }; +void __init plat_time_init(void) +{ + setup_pit_timer(); +} + void __init plat_mem_setup(void) { int i; diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 7851b4b..a2689f9 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_PROC_FS) += proc.o obj-$(CONFIG_64BIT) += cpu-bugs64.o +obj-$(CONFIG_I8253) += i8253.o obj-$(CONFIG_PCSPEAKER) += pcspeaker.o obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c new file mode 100644 index 0000000..5d9830d --- /dev/null +++ b/arch/mips/kernel/i8253.c @@ -0,0 +1,213 @@ +/* + * i8253.c 8253/PIT functions + * + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static DEFINE_SPINLOCK(i8253_lock); + +/* + * Initialize the PIT timer. + * + * This is also called after resume to bring the PIT into operation again. + */ +static void init_pit_timer(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + unsigned long flags; + + spin_lock_irqsave(&i8253_lock, flags); + + switch(mode) { + case CLOCK_EVT_MODE_PERIODIC: + /* binary, mode 2, LSB/MSB, ch 0 */ + outb_p(0x34, PIT_MODE); + outb_p(LATCH & 0xff , PIT_CH0); /* LSB */ + outb(LATCH >> 8 , PIT_CH0); /* MSB */ + break; + + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + if (evt->mode == CLOCK_EVT_MODE_PERIODIC || + evt->mode == CLOCK_EVT_MODE_ONESHOT) { + outb_p(0x30, PIT_MODE); + outb_p(0, PIT_CH0); + outb_p(0, PIT_CH0); + } + break; + + case CLOCK_EVT_MODE_ONESHOT: + /* One shot setup */ + outb_p(0x38, PIT_MODE); + break; + + case CLOCK_EVT_MODE_RESUME: + /* Nothing to do here */ + break; + } + spin_unlock_irqrestore(&i8253_lock, flags); +} + +/* + * Program the next event in oneshot mode + * + * Delta is given in PIT ticks + */ +static int pit_next_event(unsigned long delta, struct clock_event_device *evt) +{ + unsigned long flags; + + spin_lock_irqsave(&i8253_lock, flags); + outb_p(delta & 0xff , PIT_CH0); /* LSB */ + outb(delta >> 8 , PIT_CH0); /* MSB */ + spin_unlock_irqrestore(&i8253_lock, flags); + + return 0; +} + +/* + * On UP the PIT can serve all of the possible timer functions. On SMP systems + * it can be solely used for the global tick. + * + * The profiling and update capabilites are switched off once the local apic is + * registered. This mechanism replaces the previous #ifdef LOCAL_APIC - + * !using_apic_timer decisions in do_timer_interrupt_hook() + */ +struct clock_event_device pit_clockevent = { + .name = "pit", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = init_pit_timer, + .set_next_event = pit_next_event, + .shift = 32, + .irq = 0, +}; + +irqreturn_t timer_interrupt(int irq, void *dev_id) +{ + pit_clockevent.event_handler(&pit_clockevent); + + return IRQ_HANDLED; +} + +static struct irqaction irq0 = { + .handler = timer_interrupt, + .flags = IRQF_DISABLED | IRQF_NOBALANCING, + .mask = CPU_MASK_NONE, + .name = "timer" +}; + +/* + * Initialize the conversion factor and the min/max deltas of the clock event + * structure and register the clock event source with the framework. + */ +void __init setup_pit_timer(void) +{ + /* + * Start pit with the boot cpu mask and make it global after the + * IO_APIC has been initialized. + */ + pit_clockevent.cpumask = cpumask_of_cpu(0); + pit_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, 32); + pit_clockevent.max_delta_ns = + clockevent_delta2ns(0x7FFF, &pit_clockevent); + pit_clockevent.min_delta_ns = + clockevent_delta2ns(0xF, &pit_clockevent); + clockevents_register_device(&pit_clockevent); + + irq0.mask = cpumask_of_cpu(0); + setup_irq(0, &irq0); +} + +/* + * Since the PIT overflows every tick, its not very useful + * to just read by itself. So use jiffies to emulate a free + * running counter: + */ +static cycle_t pit_read(void) +{ + unsigned long flags; + int count; + u32 jifs; + static int old_count; + static u32 old_jifs; + + spin_lock_irqsave(&i8253_lock, flags); + /* + * Although our caller may have the read side of xtime_lock, + * this is now a seqlock, and we are cheating in this routine + * by having side effects on state that we cannot undo if + * there is a collision on the seqlock and our caller has to + * retry. (Namely, old_jifs and old_count.) So we must treat + * jiffies as volatile despite the lock. We read jiffies + * before latching the timer count to guarantee that although + * the jiffies value might be older than the count (that is, + * the counter may underflow between the last point where + * jiffies was incremented and the point where we latch the + * count), it cannot be newer. + */ + jifs = jiffies; + outb_p(0x00, PIT_MODE); /* latch the count ASAP */ + count = inb_p(PIT_CH0); /* read the latched count */ + count |= inb_p(PIT_CH0) << 8; + + /* VIA686a test code... reset the latch if count > max + 1 */ + if (count > LATCH) { + outb_p(0x34, PIT_MODE); + outb_p(LATCH & 0xff, PIT_CH0); + outb(LATCH >> 8, PIT_CH0); + count = LATCH - 1; + } + + /* + * It's possible for count to appear to go the wrong way for a + * couple of reasons: + * + * 1. The timer counter underflows, but we haven't handled the + * resulting interrupt and incremented jiffies yet. + * 2. Hardware problem with the timer, not giving us continuous time, + * the counter does small "jumps" upwards on some Pentium systems, + * (see c't 95/10 page 335 for Neptun bug.) + * + * Previous attempts to handle these cases intelligently were + * buggy, so we just do the simple thing now. + */ + if (count > old_count && jifs == old_jifs) { + count = old_count; + } + old_count = count; + old_jifs = jifs; + + spin_unlock_irqrestore(&i8253_lock, flags); + + count = (LATCH - 1) - count; + + return (cycle_t)(jifs * LATCH) + count; +} + +static struct clocksource clocksource_pit = { + .name = "pit", + .rating = 110, + .read = pit_read, + .mask = CLOCKSOURCE_MASK(32), + .mult = 0, + .shift = 20, +}; + +static int __init init_pit_clocksource(void) +{ + if (num_possible_cpus() > 1) /* PIT does not scale! */ + return 0; + + clocksource_pit.mult = clocksource_hz2mult(CLOCK_TICK_RATE, 20); + return clocksource_register(&clocksource_pit); +} +arch_initcall(init_pit_clocksource); diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index cf55ecd..4fab3b2 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -141,6 +142,9 @@ void __init plat_time_init(void) cpu_khz = est_freq / 1000; mips_scroll_message(); +#ifdef CONFIG_I8253 /* Only Malta has a PIT */ + setup_pit_timer(); +#endif } //static irqreturn_t mips_perf_interrupt(int irq, void *dev_id) diff --git a/arch/mips/qemu/q-setup.c b/arch/mips/qemu/q-setup.c index 89a2076..23d34c1 100644 --- a/arch/mips/qemu/q-setup.c +++ b/arch/mips/qemu/q-setup.c @@ -1,4 +1,6 @@ #include + +#include #include #include @@ -11,12 +13,9 @@ const char *get_system_type(void) return "Qemu"; } -void __init plat_timer_setup(struct irqaction *irq) +void __init plat_time_init(void) { - /* set the clock to 100 Hz */ - outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */ - outb_p(LATCH & 0xff , 0x40); /* LSB */ - outb(LATCH >> 8 , 0x40); /* MSB */ + setup_pit_timer(); } void __init plat_mem_setup(void) diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c index a1df1f9..9b9bffd 100644 --- a/arch/mips/sgi-ip22/ip22-time.c +++ b/arch/mips/sgi-ip22/ip22-time.c @@ -20,6 +20,7 @@ #include #include +#include #include #include #include @@ -172,6 +173,9 @@ __init void plat_time_init(void) (int) (r4k_tick % (500000 / HZ))); mips_hpt_frequency = r4k_tick * HZ; + + if (ip22_is_fullhouse()) + setup_pit_timer(); } /* Generic SGI handler for (spurious) 8254 interrupts */ diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c index 92452d6..153f065 100644 --- a/arch/mips/sni/time.c +++ b/arch/mips/sni/time.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -116,6 +117,8 @@ void __init plat_time_init(void) (int) (r4k_tick % (500000 / HZ))); mips_hpt_frequency = r4k_tick * HZ; + + setup_pit_timer(); } /* diff --git a/include/asm-mips/i8253.h b/include/asm-mips/i8253.h new file mode 100644 index 0000000..8f689d7 --- /dev/null +++ b/include/asm-mips/i8253.h @@ -0,0 +1,30 @@ +/* + * Machine specific IO port address definition for generic. + * Written by Osamu Tomita + */ +#ifndef _MACH_IO_PORTS_H +#define _MACH_IO_PORTS_H + +/* i8253A PIT registers */ +#define PIT_MODE 0x43 +#define PIT_CH0 0x40 +#define PIT_CH2 0x42 + +/* i8259A PIC registers */ +#define PIC_MASTER_CMD 0x20 +#define PIC_MASTER_IMR 0x21 +#define PIC_MASTER_ISR PIC_MASTER_CMD +#define PIC_MASTER_POLL PIC_MASTER_ISR +#define PIC_MASTER_OCW3 PIC_MASTER_ISR +#define PIC_SLAVE_CMD 0xa0 +#define PIC_SLAVE_IMR 0xa1 + +/* i8259A PIC related value */ +#define PIC_CASCADE_IR 2 +#define MASTER_ICW4_DEFAULT 0x01 +#define SLAVE_ICW4_DEFAULT 0x01 +#define PIC_ICW4_AEOI 2 + +extern void setup_pit_timer(void); + +#endif /* !_MACH_IO_PORTS_H */ -- cgit v0.10.2 From 9b9ea2202f3396790f635c62f7498ad75f08f62c Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:10 +0100 Subject: [MIPS] Clockevent driver for BCM1250 Signed-off-by: Ralf Baechle diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c index eb17707..38199ad 100644 --- a/arch/mips/sibyte/sb1250/time.c +++ b/arch/mips/sibyte/sb1250/time.c @@ -25,6 +25,7 @@ * code to do general bookkeeping (e.g. update jiffies, run * bottom halves, etc.) */ +#include #include #include #include @@ -71,16 +72,158 @@ void __init sb1250_hpt_setup(void) } } +/* + * The general purpose timer ticks at 1 Mhz independent if + * the rest of the system + */ +static void sibyte_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + unsigned int cpu = smp_processor_id(); + void __iomem *timer_cfg, *timer_init; + + timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); + timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); + + switch(mode) { + case CLOCK_EVT_MODE_PERIODIC: + __raw_writeq(0, timer_cfg); + __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init); + __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, + timer_cfg); + break; + + case CLOCK_EVT_MODE_ONESHOT: + /* Stop the timer until we actually program a shot */ + case CLOCK_EVT_MODE_SHUTDOWN: + __raw_writeq(0, timer_cfg); + break; -void sb1250_time_init(void) + case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ + ; + } +} + +static int +sibyte_next_event(unsigned long delta, struct clock_event_device *evt) { - int cpu = smp_processor_id(); - int irq = K_INT_TIMER_0+cpu; + unsigned int cpu = smp_processor_id(); + void __iomem *timer_cfg, *timer_init; - /* Only have 4 general purpose timers, and we use last one as hpt */ - if (cpu > 2) { - BUG(); + timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); + timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); + + __raw_writeq(0, timer_cfg); + __raw_writeq(delta, timer_init); + __raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg); + + return 0; +} + +struct clock_event_device sibyte_hpt_clockevent = { + .name = "sb1250-counter", + .features = CLOCK_EVT_FEAT_PERIODIC, + .set_mode = sibyte_set_mode, + .set_next_event = sibyte_next_event, + .shift = 32, + .irq = 0, +}; + +static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) +{ + struct clock_event_device *cd = &sibyte_hpt_clockevent; + + cd->event_handler(cd); + + return IRQ_HANDLED; +} + +static struct irqaction sibyte_irqaction = { + .handler = sibyte_counter_handler, + .flags = IRQF_DISABLED | IRQF_PERCPU, + .name = "timer", +}; + +/* + * The general purpose timer ticks at 1 Mhz independent if + * the rest of the system + */ +static void sibyte_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + unsigned int cpu = smp_processor_id(); + void __iomem *timer_cfg, *timer_init; + + timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); + timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + __raw_writeq(0, timer_cfg); + __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init); + __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, + timer_cfg); + break; + + case CLOCK_EVT_MODE_ONESHOT: + /* Stop the timer until we actually program a shot */ + case CLOCK_EVT_MODE_SHUTDOWN: + __raw_writeq(0, timer_cfg); + break; + + case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ + ; } +} + +static int +sibyte_next_event(unsigned long delta, struct clock_event_device *evt) +{ + unsigned int cpu = smp_processor_id(); + void __iomem *timer_cfg, *timer_init; + + timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); + timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); + + __raw_writeq(0, timer_cfg); + __raw_writeq(delta, timer_init); + __raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg); + + return 0; +} + +struct clock_event_device sibyte_hpt_clockevent = { + .name = "sb1250-counter", + .features = CLOCK_EVT_FEAT_PERIODIC, + .set_mode = sibyte_set_mode, + .set_next_event = sibyte_next_event, + .shift = 32, + .irq = 0, +}; + +static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) +{ + struct clock_event_device *cd = &sibyte_hpt_clockevent; + + cd->event_handler(cd); + + return IRQ_HANDLED; +} + +static struct irqaction sibyte_irqaction = { + .handler = sibyte_counter_handler, + .flags = IRQF_DISABLED | IRQF_PERCPU, + .name = "timer", +}; + +static void __init sb1250_clockevent_init(void) +{ + struct clock_event_device *cd = &sibyte_hpt_clockevent; + unsigned int cpu = smp_processor_id(); + int irq = K_INT_TIMER_0 + cpu; + + /* Only have 4 general purpose timers, and we use last one as hpt */ + BUG_ON(cpu > 2); sb1250_mask_irq(cpu, irq); @@ -88,24 +231,11 @@ void sb1250_time_init(void) __raw_writeq(IMR_IP4_VAL, IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + (irq << 3))); - - /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */ - /* Disable the timer and set up the count */ - __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); -#ifdef CONFIG_SIMULATION - __raw_writeq((50000 / HZ) - 1, - IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); -#else - __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, - IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); -#endif - - /* Set the timer running */ - __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, - IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); + cd->cpumask = cpumask_of_cpu(0); sb1250_unmask_irq(cpu, irq); sb1250_steal_irq(irq); + /* * This interrupt is "special" in that it doesn't use the request_irq * way to hook the irq line. The timer interrupt is initialized early @@ -114,6 +244,15 @@ void sb1250_time_init(void) * called directly from irq_handler.S when IP[4] is set during an * interrupt */ + setup_irq(irq, &sibyte_irqaction); + + clockevents_register_device(cd); +} + +void __init plat_time_init(void) +{ + sb1250_clocksource_init(); + sb1250_clockevent_init(); } /* -- cgit v0.10.2 From e9f874b6f761f7f8394157d28641491c9babc1d3 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:10 +0100 Subject: [MIPS] Clockevent driver for BCM1480 Signed-off-by: Ralf Baechle diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c index 8519091..40d7126 100644 --- a/arch/mips/sibyte/bcm1480/time.c +++ b/arch/mips/sibyte/bcm1480/time.c @@ -25,6 +25,7 @@ * code to do general bookkeeping (e.g. update jiffies, run * bottom halves, etc.) */ +#include #include #include #include @@ -55,15 +56,12 @@ extern int bcm1480_steal_irq(int irq); -void bcm1480_time_init(void) +void __init plat_time_init(void) { - int cpu = smp_processor_id(); - int irq = K_BCM1480_INT_TIMER_0+cpu; + unsigned int cpu = smp_processor_id(); + unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu; - /* Only have 4 general purpose timers */ - if (cpu > 3) { - BUG(); - } + BUG_ON(cpu > 3); /* Only have 4 general purpose timers */ bcm1480_mask_irq(cpu, irq); @@ -71,27 +69,83 @@ void bcm1480_time_init(void) __raw_writeq(IMR_IP4_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq<<3))); - /* the general purpose timer ticks at 1 Mhz independent of the rest of the system */ - /* Disable the timer and set up the count */ - __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); - __raw_writeq( - BCM1480_HPT_VALUE/HZ - , IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); + bcm1480_unmask_irq(cpu, irq); + bcm1480_steal_irq(irq); +} - /* Set the timer running */ +/* + * The general purpose timer ticks at 1 Mhz independent if + * the rest of the system + */ +static void sibyte_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + unsigned int cpu = smp_processor_id(); + void __iomem *timer_cfg, *timer_init; + + timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); + timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + __raw_writeq(0, timer_cfg); + __raw_writeq(BCM1480_HPT_VALUE / HZ - 1, timer_init); + __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, + timer_cfg); + break; + + case CLOCK_EVT_MODE_ONESHOT: + /* Stop the timer until we actually program a shot */ + case CLOCK_EVT_MODE_SHUTDOWN: + __raw_writeq(0, timer_cfg); + break; + + case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ + ; + } +} + +struct clock_event_device sibyte_hpt_clockevent = { + .name = "bcm1480-counter", + .features = CLOCK_EVT_FEAT_PERIODIC, + .set_mode = sibyte_set_mode, + .shift = 32, + .irq = 0, +}; + +static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) +{ + struct clock_event_device *cd = &sibyte_hpt_clockevent; + unsigned int cpu = smp_processor_id(); + + /* Reset the timer */ __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, - IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); + IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); + cd->event_handler(cd); - bcm1480_unmask_irq(cpu, irq); - bcm1480_steal_irq(irq); - /* - * This interrupt is "special" in that it doesn't use the request_irq - * way to hook the irq line. The timer interrupt is initialized early - * enough to make this a major pain, and it's also firing enough to - * warrant a bit of special case code. bcm1480_timer_interrupt is - * called directly from irq_handler.S when IP[4] is set during an - * interrupt - */ + return IRQ_HANDLED; +} + +static struct irqaction sibyte_counter_irqaction = { + .handler = sibyte_counter_handler, + .flags = IRQF_DISABLED | IRQF_PERCPU, + .name = "timer", +}; + +/* + * This interrupt is "special" in that it doesn't use the request_irq + * way to hook the irq line. The timer interrupt is initialized early + * enough to make this a major pain, and it's also firing enough to + * warrant a bit of special case code. bcm1480_timer_interrupt is + * called directly from irq_handler.S when IP[4] is set during an + * interrupt + */ +static void __init sb1480_clockevent_init(void) +{ + unsigned int cpu = smp_processor_id(); + unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu; + + setup_irq(irq, &sibyte_counter_irqaction); } void bcm1480_timer_interrupt(void) @@ -118,4 +172,5 @@ void __init bcm1480_hpt_setup(void) { clocksource_mips.read = bcm1480_hpt_read; mips_hpt_frequency = BCM1480_HPT_VALUE; + sb1480_clockevent_init(); } -- cgit v0.10.2 From e58d95abb7b3232333ab35a09f7f5b0cd6a19cdb Mon Sep 17 00:00:00 2001 From: Franck Bui-Huu Date: Thu, 27 Sep 2007 16:26:40 +0200 Subject: [MIPS] Don't abort the build process if '-msym32' isn't supported -msym32 and previously the strategy to tell the compiler to generate 64-bit code but the assembler to put it into 32-bit ELF was initially a hack to get around the lack of proper 64-bit binutils support and later turned into a neat optimization with significant code size savings. But it's really just an optimization so there is nothing wrong with just dropping the option (and whatever else goes along with it, I forgot all the nasty details) on the floor if due to a vintage compiler it can't be suported. Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle diff --git a/arch/mips/Makefile b/arch/mips/Makefile index b0fac2d..ebd5d02 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -602,7 +602,9 @@ ifdef CONFIG_64BIT endif ifeq ($(KBUILD_SYM32), y) - cflags-y += -msym32 -DKBUILD_64BIT_SYM32 + ifeq ($(call cc-option-yn,-msym32), y) + cflags-y += -msym32 -DKBUILD_64BIT_SYM32 + endif endif endif -- cgit v0.10.2 From db813fe5a77d03b29e872da47463d2efbddc3fc2 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 27 Sep 2007 18:26:43 +0100 Subject: [MIPS] Avoid indexed cacheops. On MP configurations it's highly dubious what this code will actually affect since blasting away cachelines may or may not do the right thing wrt. cache coherency. Signed-off-by: Ralf Baechle diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 738b898..cf48371 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -8,6 +8,7 @@ * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ #include +#include #include #include #include @@ -318,23 +319,6 @@ static void __init r4k_blast_scache_setup(void) r4k_blast_scache = blast_scache128; } -/* - * This is former mm's flush_cache_all() which really should be - * flush_cache_vunmap these days ... - */ -static inline void local_r4k_flush_cache_all(void * args) -{ - r4k_blast_dcache(); -} - -static void r4k_flush_cache_all(void) -{ - if (!cpu_has_dc_aliases) - return; - - r4k_on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1); -} - static inline void local_r4k___flush_cache_all(void * args) { #if defined(CONFIG_CPU_LOONGSON2) @@ -423,13 +407,14 @@ static inline void local_r4k_flush_cache_page(void *args) struct flush_cache_page_args *fcp_args = args; struct vm_area_struct *vma = fcp_args->vma; unsigned long addr = fcp_args->addr; - unsigned long paddr = fcp_args->pfn << PAGE_SHIFT; + struct page *page = pfn_to_page(fcp_args->pfn); int exec = vma->vm_flags & VM_EXEC; struct mm_struct *mm = vma->vm_mm; pgd_t *pgdp; pud_t *pudp; pmd_t *pmdp; pte_t *ptep; + void *vaddr; /* * If ownes no valid ASID yet, cannot possibly have gotten @@ -451,43 +436,40 @@ static inline void local_r4k_flush_cache_page(void *args) if (!(pte_val(*ptep) & _PAGE_PRESENT)) return; - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) { - if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { - r4k_blast_dcache_page(addr); - if (exec && !cpu_icache_snoops_remote_store) - r4k_blast_scache_page(addr); - } - if (exec) - r4k_blast_icache_page(addr); - - return; + if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) + vaddr = NULL; + else { + /* + * Use kmap_coherent or kmap_atomic to do flushes for + * another ASID than the current one. + */ + if (cpu_has_dc_aliases) + vaddr = kmap_coherent(page, addr); + else + vaddr = kmap_atomic(page, KM_USER0); + addr = (unsigned long)vaddr; } - /* - * Do indexed flush, too much work to get the (possible) TLB refills - * to work correctly. - */ if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { - r4k_blast_dcache_page_indexed(cpu_has_pindexed_dcache ? - paddr : addr); - if (exec && !cpu_icache_snoops_remote_store) { - r4k_blast_scache_page_indexed(paddr); - } + r4k_blast_dcache_page(addr); + if (exec && !cpu_icache_snoops_remote_store) + r4k_blast_scache_page(addr); } if (exec) { - if (cpu_has_vtag_icache && mm == current->active_mm) { + if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { int cpu = smp_processor_id(); if (cpu_context(cpu, mm) != 0) drop_mmu_context(mm, cpu); } else - r4k_blast_icache_page_indexed(addr); + r4k_blast_icache_page(addr); + } + + if (vaddr) { + if (cpu_has_dc_aliases) + kunmap_coherent(); + else + kunmap_atomic(vaddr, KM_USER0); } } @@ -1279,7 +1261,7 @@ void __init r4k_cache_init(void) PAGE_SIZE - 1); else shm_align_mask = PAGE_SIZE-1; - flush_cache_all = r4k_flush_cache_all; + flush_cache_all = cache_noop; __flush_cache_all = r4k___flush_cache_all; flush_cache_mm = r4k_flush_cache_mm; flush_cache_page = r4k_flush_cache_page; -- cgit v0.10.2 From f4fae8267c152d6c319a7bfaf92ed1c2c9a2c4e8 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:12 +0100 Subject: [MIPS] Optimize __alloc_zeroed_user_highpage implementation. Signed-off-by: Ralf Baechle diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index c90fe56..e3301e5 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -142,7 +142,7 @@ typedef struct { unsigned long pgprot; } pgprot_t; /* * __pa()/__va() should be used only during mem init. */ -#ifdef KBUILD_64BIT_SYM32 +#ifdef CONFIG_64BIT #define __pa(x) \ ({ \ unsigned long __x = (unsigned long)(x); \ -- cgit v0.10.2 From e86169fffedc2f461be6f70817ae5ab201c12fd5 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Mon, 1 Oct 2007 19:45:05 +0900 Subject: [MIPS] Cobalt: Add Cobalt Raq LED platform register and power off trigger Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile index a043f93..6b83f4d 100644 --- a/arch/mips/cobalt/Makefile +++ b/arch/mips/cobalt/Makefile @@ -2,7 +2,7 @@ # Makefile for the Cobalt micro systems family specific parts of the kernel # -obj-y := buttons.o irq.o reset.o rtc.o serial.o setup.o +obj-y := buttons.o irq.o led.o reset.o rtc.o serial.o setup.o obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_EARLY_PRINTK) += console.o diff --git a/arch/mips/cobalt/led.c b/arch/mips/cobalt/led.c new file mode 100644 index 0000000..8150af3 --- /dev/null +++ b/arch/mips/cobalt/led.c @@ -0,0 +1,56 @@ +/* + * Registration of Cobalt LED platform device. + * + * Copyright (C) 2007 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include + +static struct resource cobalt_led_resource __initdata = { + .start = 0x1c000000, + .end = 0x1c000000, + .flags = IORESOURCE_MEM, +}; + +static __init int cobalt_led_add(void) +{ + struct platform_device *pdev; + int retval; + + pdev = platform_device_alloc("cobalt-raq-leds", -1); + + if (!pdev) + return -ENOMEM; + + retval = platform_device_add_resources(pdev, &cobalt_led_resource, 1); + if (retval) + goto err_free_device; + + retval = platform_device_add(pdev); + if (retval) + goto err_free_device; + + return 0; + +err_free_device: + platform_device_put(pdev); + + return retval; +} +device_initcall(cobalt_led_add); diff --git a/arch/mips/cobalt/reset.c b/arch/mips/cobalt/reset.c index 43cca21..f503a0d 100644 --- a/arch/mips/cobalt/reset.c +++ b/arch/mips/cobalt/reset.c @@ -8,31 +8,37 @@ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv) */ +#include #include - -#include -#include +#include #include +DEFINE_LED_TRIGGER(power_off_led_trigger); + +static int __init ledtrig_power_off_init(void) +{ + led_trigger_register_simple("power-off", &power_off_led_trigger); + return 0; +} +device_initcall(ledtrig_power_off_init); + void cobalt_machine_halt(void) { int state, last, diff; unsigned long mark; /* - * turn off bar on Qube, flash power off LED on RaQ (0.5Hz) + * turn on power off LED on RaQ * * restart if ENTER and SELECT are pressed */ last = COBALT_KEY_PORT; - for (state = 0;;) { - - state ^= COBALT_LED_POWER_OFF; - COBALT_LED_PORT = state; + led_trigger_event(power_off_led_trigger, LED_FULL); + for (state = 0;;) { diff = COBALT_KEY_PORT ^ last; last ^= diff; -- cgit v0.10.2 From 9a203755ca392587953be2b5cf235800dcb27d8e Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Mon, 1 Oct 2007 19:46:50 +0900 Subject: [MIPS] Cobalt: Add Qube series front LED support to platform register Add Cobalt Qube series front LED support to platform register. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/arch/mips/cobalt/led.c b/arch/mips/cobalt/led.c index 8150af3..1c6ebd4 100644 --- a/arch/mips/cobalt/led.c +++ b/arch/mips/cobalt/led.c @@ -22,6 +22,8 @@ #include #include +#include + static struct resource cobalt_led_resource __initdata = { .start = 0x1c000000, .end = 0x1c000000, @@ -33,7 +35,11 @@ static __init int cobalt_led_add(void) struct platform_device *pdev; int retval; - pdev = platform_device_alloc("cobalt-raq-leds", -1); + if (cobalt_board_id == COBALT_BRD_ID_QUBE1 || + cobalt_board_id == COBALT_BRD_ID_QUBE2) + pdev = platform_device_alloc("cobalt-qube-leds", -1); + else + pdev = platform_device_alloc("cobalt-raq-leds", -1); if (!pdev) return -ENOMEM; -- cgit v0.10.2 From 414461f9e0e30551a75b015aa2864efbf393de2f Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Mon, 1 Oct 2007 19:48:31 +0900 Subject: [MIPS] Cobalt: Add LED support to cobalt_defconfig Add LED support to cobalt_defconfig. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig index ebcb7ad..36c1303 100644 --- a/arch/mips/configs/cobalt_defconfig +++ b/arch/mips/configs/cobalt_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.23-rc2 -# Tue Aug 7 22:12:54 2007 +# Linux kernel version: 2.6.23-rc5 +# Thu Sep 6 13:14:29 2007 # CONFIG_MIPS=y @@ -55,12 +55,14 @@ CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_EARLY_PRINTK=y CONFIG_SYS_HAS_EARLY_PRINTK=y +# CONFIG_HOTPLUG_CPU is not set CONFIG_I8259=y # CONFIG_NO_IOPORT is not set # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y +CONFIG_IRQ_GT641XX=y CONFIG_PCI_GT64XXX_PCI0=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -235,6 +237,7 @@ CONFIG_TRAD_SIGNALS=y # Power management options # # CONFIG_PM is not set +CONFIG_SUSPEND_UP_POSSIBLE=y # # Networking @@ -844,7 +847,21 @@ CONFIG_USB_MON=y # # CONFIG_USB_GADGET is not set # CONFIG_MMC is not set -# CONFIG_NEW_LEDS is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_COBALT_QUBE=y +CONFIG_LEDS_COBALT_RAQ=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set # CONFIG_INFINIBAND is not set CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y -- cgit v0.10.2 From b1df86d6e148e3be6d1e43e604b19fbb6815b8ba Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 1 Oct 2007 13:52:38 +0200 Subject: [MIPS] MTX1: Add defconfig file Signed-off-by: Florian Fainelli Signed-off-by: Ralf Baechle diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig new file mode 100644 index 0000000..0280ef3 --- /dev/null +++ b/arch/mips/configs/mtx1_defconfig @@ -0,0 +1,3115 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.23-rc8 +# Sun Sep 30 12:56:10 2007 +# +CONFIG_MIPS=y + +# +# Machine selection +# +CONFIG_MACH_ALCHEMY=y +# CONFIG_BASLER_EXCITE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_WR_PPMC is not set +CONFIG_MIPS_MTX1=y +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_XXS1500 is not set +CONFIG_SOC_AU1500=y +CONFIG_SOC_AU1X00=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_TIME=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NO_IOPORT is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_RESOURCES_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +CONFIG_SECCOMP=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +CONFIG_AUDIT=y +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_SYSFS_DEPRECATED=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_KMOD=y +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# +CONFIG_PCCARD=m +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_PCMCIA=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y +CONFIG_CARDBUS=y + +# +# PC-card bridges +# +CONFIG_YENTA=m +CONFIG_YENTA_O2=y +CONFIG_YENTA_RICOH=y +CONFIG_YENTA_TI=y +CONFIG_YENTA_ENE_TUNE=y +CONFIG_YENTA_TOSHIBA=y +CONFIG_PD6729=m +CONFIG_I82092=m +# CONFIG_PCMCIA_AU1X00 is not set +CONFIG_PCCARD_NONSTATIC=m +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_BINFMT_MISC=m +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_LEGACY is not set +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_UP_POSSIBLE=y +CONFIG_SUSPEND=y +# CONFIG_APM_EMULATION is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=m +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IP_VS=m +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_TUNNEL=m +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_NETLABEL is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +# CONFIG_NF_CONNTRACK_ENABLED is not set +# CONFIG_NF_CONNTRACK is not set +CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_IPRANGE=m +CONFIG_IP_NF_MATCH_TOS=m +CONFIG_IP_NF_MATCH_RECENT=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_MATCH_OWNER=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_TOS=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration (EXPERIMENTAL) +# +CONFIG_IP6_NF_QUEUE=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_OWNER=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_AH=m +# CONFIG_IP6_NF_MATCH_MH is not set +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_RAW=m + +# +# DECnet: Netfilter Configuration +# +CONFIG_DECNET_NF_GRABULATOR=m + +# +# Bridge: Netfilter Configuration +# +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_ULOG=m +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m +CONFIG_IP_DCCP_ACKVEC=y + +# +# DCCP CCIDs Configuration (EXPERIMENTAL) +# +CONFIG_IP_DCCP_CCID2=m +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=m +CONFIG_IP_DCCP_TFRC_LIB=m +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_CCID3_RTO=100 +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +CONFIG_TIPC=m +# CONFIG_TIPC_ADVANCED is not set +# CONFIG_TIPC_DEBUG is not set +CONFIG_ATM=y +CONFIG_ATM_CLIP=y +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_DECNET=m +# CONFIG_DECNET_ROUTER is not set +CONFIG_LLC=y +CONFIG_LLC2=m +CONFIG_IPX=m +# CONFIG_IPX_INTERN is not set +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_ECONET=m +CONFIG_ECONET_AUNUDP=y +CONFIG_ECONET_NATIVE=y +CONFIG_WAN_ROUTER=m + +# +# QoS and/or fair queueing +# +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_FIFO=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +# CONFIG_NET_SCH_RR is not set +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_INGRESS=m + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_ROUTE=y +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +CONFIG_NET_CLS_POLICE=y +# CONFIG_NET_CLS_IND is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +CONFIG_AX25=m +# CONFIG_AX25_DAMA_SLAVE is not set +CONFIG_NETROM=m +CONFIG_ROSE=m + +# +# AX.25 network device drivers +# +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_BAYCOM_PAR=m +CONFIG_BAYCOM_EPP=m +CONFIG_YAM=m +CONFIG_IRDA=m + +# +# IrDA protocols +# +CONFIG_IRLAN=m +CONFIG_IRNET=m +CONFIG_IRCOMM=m +CONFIG_IRDA_ULTRA=y + +# +# IrDA options +# +CONFIG_IRDA_CACHE_LAST_LSAP=y +CONFIG_IRDA_FAST_RR=y +CONFIG_IRDA_DEBUG=y + +# +# Infrared-port device drivers +# + +# +# SIR device drivers +# +CONFIG_IRTTY_SIR=m + +# +# Dongle support +# +CONFIG_DONGLE=y +CONFIG_ESI_DONGLE=m +CONFIG_ACTISYS_DONGLE=m +CONFIG_TEKRAM_DONGLE=m +# CONFIG_TOIM3232_DONGLE is not set +CONFIG_LITELINK_DONGLE=m +CONFIG_MA600_DONGLE=m +CONFIG_GIRBIL_DONGLE=m +CONFIG_MCP2120_DONGLE=m +CONFIG_OLD_BELKIN_DONGLE=m +CONFIG_ACT200L_DONGLE=m +# CONFIG_KINGSUN_DONGLE is not set + +# +# Old SIR device drivers +# +# CONFIG_IRPORT_SIR is not set + +# +# Old Serial dongle support +# + +# +# FIR device drivers +# +CONFIG_USB_IRDA=m +CONFIG_SIGMATEL_FIR=m +CONFIG_TOSHIBA_FIR=m +CONFIG_VLSI_FIR=m +CONFIG_MCS_FIR=m +CONFIG_BT=m +CONFIG_BT_L2CAP=m +CONFIG_BT_SCO=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_CMTP=m +CONFIG_BT_HIDP=m + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIUSB=m +CONFIG_BT_HCIUSB_SCO=y +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIDTL1=m +CONFIG_BT_HCIBT3C=m +CONFIG_BT_HCIBLUECARD=m +CONFIG_BT_HCIBTUART=m +CONFIG_BT_HCIVHCI=m +CONFIG_AF_RXRPC=m +# CONFIG_AF_RXRPC_DEBUG is not set +# CONFIG_RXKAD is not set +CONFIG_FIB_RULES=y + +# +# Wireless +# +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m +CONFIG_IEEE80211_SOFTMAC=m +# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=m +CONFIG_MTD=m +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=m +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_REDBOOT_PARTS=m +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=m +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK_RO=m +CONFIG_FTL=m +CONFIG_NFTL=m +CONFIG_NFTL_RW=y +CONFIG_INFTL=m +CONFIG_RFD_FTL=m +CONFIG_SSFDC=m + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_GEN_PROBE=m +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_CFI_UTIL=m +CONFIG_MTD_RAM=m +CONFIG_MTD_ROM=m +CONFIG_MTD_ABSENT=m + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=m +CONFIG_MTD_PHYSMAP_START=0x8000000 +CONFIG_MTD_PHYSMAP_LEN=0x4000000 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_ALCHEMY is not set +# CONFIG_MTD_MTX1 is not set +CONFIG_MTD_PCI=m +CONFIG_MTD_PLATRAM=m + +# +# Self-contained MTD device drivers +# +CONFIG_MTD_PMC551=m +# CONFIG_MTD_PMC551_BUGFIX is not set +# CONFIG_MTD_PMC551_DEBUG is not set +CONFIG_MTD_DATAFLASH=m +CONFIG_MTD_M25P80=m +CONFIG_MTD_SLRAM=m +CONFIG_MTD_PHRAM=m +CONFIG_MTD_MTDRAM=m +CONFIG_MTDRAM_TOTAL_SIZE=4096 +CONFIG_MTDRAM_ERASE_SIZE=128 +CONFIG_MTD_BLOCK2MTD=m + +# +# Disk-On-Chip Device Drivers +# +CONFIG_MTD_DOC2000=m +CONFIG_MTD_DOC2001=m +CONFIG_MTD_DOC2001PLUS=m +CONFIG_MTD_DOCPROBE=m +CONFIG_MTD_DOCECC=m +# CONFIG_MTD_DOCPROBE_ADVANCED is not set +CONFIG_MTD_DOCPROBE_ADDRESS=0 +CONFIG_MTD_NAND=m +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=m +CONFIG_MTD_NAND_DISKONCHIP=m +# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 +# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set +# CONFIG_MTD_NAND_CAFE is not set +CONFIG_MTD_NAND_NANDSIM=m +# CONFIG_MTD_NAND_PLATFORM is not set +CONFIG_MTD_ONENAND=m +CONFIG_MTD_ONENAND_VERIFY_WRITE=y +# CONFIG_MTD_ONENAND_OTP is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +CONFIG_PARPORT=m +CONFIG_PARPORT_PC=m +CONFIG_PARPORT_SERIAL=m +CONFIG_PARPORT_PC_FIFO=y +CONFIG_PARPORT_PC_SUPERIO=y +CONFIG_PARPORT_PC_PCMCIA=m +# CONFIG_PARPORT_GSC is not set +CONFIG_PARPORT_AX88796=m +CONFIG_PARPORT_1284=y +CONFIG_PARPORT_NOT_PC=y +CONFIG_BLK_DEV=y +CONFIG_PARIDE=m + +# +# Parallel IDE high-level drivers +# +CONFIG_PARIDE_PD=m +CONFIG_PARIDE_PCD=m +CONFIG_PARIDE_PF=m +CONFIG_PARIDE_PT=m +CONFIG_PARIDE_PG=m + +# +# Parallel IDE protocol modules +# +CONFIG_PARIDE_ATEN=m +CONFIG_PARIDE_BPCK=m +CONFIG_PARIDE_BPCK6=m +CONFIG_PARIDE_COMM=m +CONFIG_PARIDE_DSTR=m +CONFIG_PARIDE_FIT2=m +CONFIG_PARIDE_FIT3=m +CONFIG_PARIDE_EPAT=m +CONFIG_PARIDE_EPATC8=y +CONFIG_PARIDE_EPIA=m +CONFIG_PARIDE_FRIQ=m +CONFIG_PARIDE_FRPW=m +CONFIG_PARIDE_KBIC=m +CONFIG_PARIDE_KTTI=m +CONFIG_PARIDE_ON20=m +CONFIG_PARIDE_ON26=m +CONFIG_BLK_CPQ_DA=m +CONFIG_BLK_CPQ_CISS_DA=m +CONFIG_CISS_SCSI_TAPE=y +CONFIG_BLK_DEV_DAC960=m +CONFIG_BLK_DEV_UMEM=m +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_SX8=m +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +CONFIG_ATA_OVER_ETH=m +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_SGI_IOC4=m +CONFIG_TIFM_CORE=m +CONFIG_TIFM_7XX1=m +CONFIG_IDE=y +CONFIG_IDE_MAX_HWIFS=4 +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=m +# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_BLK_DEV_IDECS=m +# CONFIG_BLK_DEV_DELKIN is not set +CONFIG_BLK_DEV_IDECD=m +CONFIG_BLK_DEV_IDETAPE=m +CONFIG_BLK_DEV_IDEFLOPPY=m +CONFIG_BLK_DEV_IDESCSI=m +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=m +CONFIG_BLK_DEV_IDEPCI=y +CONFIG_IDEPCI_SHARE_IRQ=y +CONFIG_IDEPCI_PCIBUS_ORDER=y +# CONFIG_BLK_DEV_OFFBOARD is not set +CONFIG_BLK_DEV_GENERIC=m +CONFIG_BLK_DEV_OPTI621=m +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_IDEDMA_FORCED is not set +# CONFIG_IDEDMA_ONLYDISK is not set +CONFIG_BLK_DEV_AEC62XX=m +CONFIG_BLK_DEV_ALI15X3=m +# CONFIG_WDC_ALI15X3 is not set +CONFIG_BLK_DEV_AMD74XX=m +CONFIG_BLK_DEV_CMD64X=m +CONFIG_BLK_DEV_TRIFLEX=m +CONFIG_BLK_DEV_CY82C693=m +# CONFIG_BLK_DEV_CS5520 is not set +CONFIG_BLK_DEV_CS5530=m +CONFIG_BLK_DEV_HPT34X=m +# CONFIG_HPT34X_AUTODMA is not set +CONFIG_BLK_DEV_HPT366=m +# CONFIG_BLK_DEV_JMICRON is not set +CONFIG_BLK_DEV_SC1200=m +CONFIG_BLK_DEV_PIIX=m +# CONFIG_BLK_DEV_IT8213 is not set +CONFIG_BLK_DEV_IT821X=m +CONFIG_BLK_DEV_NS87415=m +CONFIG_BLK_DEV_PDC202XX_OLD=m +CONFIG_PDC202XX_BURST=y +CONFIG_BLK_DEV_PDC202XX_NEW=m +CONFIG_BLK_DEV_SVWKS=m +CONFIG_BLK_DEV_SIIMAGE=m +# CONFIG_BLK_DEV_SLC90E66 is not set +CONFIG_BLK_DEV_TRM290=m +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_TC86C001 is not set +# CONFIG_IDE_ARM is not set +CONFIG_BLK_DEV_IDEDMA=y +# CONFIG_IDEDMA_IVB is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=m +CONFIG_CHR_DEV_SCH=m + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +# CONFIG_SCSI_SAS_ATA is not set +# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_ISCSI_TCP=m +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_ACARD=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_AIC7XXX=m +CONFIG_AIC7XXX_CMDS_PER_DEVICE=8 +CONFIG_AIC7XXX_RESET_DELAY_MS=15000 +CONFIG_AIC7XXX_DEBUG_ENABLE=y +CONFIG_AIC7XXX_DEBUG_MASK=0 +CONFIG_AIC7XXX_REG_PRETTY_PRINT=y +# CONFIG_SCSI_AIC7XXX_OLD is not set +CONFIG_SCSI_AIC79XX=m +CONFIG_AIC79XX_CMDS_PER_DEVICE=32 +CONFIG_AIC79XX_RESET_DELAY_MS=15000 +CONFIG_AIC79XX_DEBUG_ENABLE=y +CONFIG_AIC79XX_DEBUG_MASK=0 +CONFIG_AIC79XX_REG_PRETTY_PRINT=y +CONFIG_SCSI_AIC94XX=m +# CONFIG_AIC94XX_DEBUG is not set +CONFIG_SCSI_DPT_I2O=m +CONFIG_SCSI_ARCMSR=m +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_MAILBOX=m +CONFIG_MEGARAID_LEGACY=m +CONFIG_MEGARAID_SAS=m +CONFIG_SCSI_HPTIOP=m +CONFIG_SCSI_DMX3191D=m +CONFIG_SCSI_FUTURE_DOMAIN=m +CONFIG_SCSI_IPS=m +CONFIG_SCSI_INITIO=m +# CONFIG_SCSI_INIA100 is not set +CONFIG_SCSI_PPA=m +CONFIG_SCSI_IMM=m +# CONFIG_SCSI_IZIP_EPP16 is not set +# CONFIG_SCSI_IZIP_SLOW_CTR is not set +CONFIG_SCSI_STEX=m +CONFIG_SCSI_SYM53C8XX_2=m +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 +CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 +CONFIG_SCSI_SYM53C8XX_MMIO=y +CONFIG_SCSI_IPR=m +# CONFIG_SCSI_IPR_TRACE is not set +# CONFIG_SCSI_IPR_DUMP is not set +CONFIG_SCSI_QLOGIC_1280=m +CONFIG_SCSI_QLA_FC=m +CONFIG_SCSI_QLA_ISCSI=m +CONFIG_SCSI_LPFC=m +CONFIG_SCSI_DC395x=m +CONFIG_SCSI_DC390T=m +CONFIG_SCSI_NSP32=m +CONFIG_SCSI_DEBUG=m +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set +CONFIG_ATA=m +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_SATA_AHCI=m +CONFIG_SATA_SVW=m +CONFIG_ATA_PIIX=m +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_PDC_ADMA=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_PROMISE=m +CONFIG_SATA_SX4=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIL24=m +CONFIG_SATA_SIS=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m +# CONFIG_SATA_INIC162X is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +CONFIG_PATA_CS5520=m +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CYPRESS is not set +CONFIG_PATA_EFAR=m +CONFIG_ATA_GENERIC=m +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_IT8213 is not set +CONFIG_PATA_JMICRON=m +CONFIG_PATA_TRIFLEX=m +# CONFIG_PATA_MARVELL is not set +CONFIG_PATA_MPIIX=m +# CONFIG_PATA_OLDPIIX is not set +CONFIG_PATA_NETCELL=m +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +CONFIG_PATA_PCMCIA=m +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +CONFIG_PATA_RZ1000=m +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SERVERWORKS is not set +CONFIG_PATA_PDC2027X=m +CONFIG_PATA_SIL680=m +CONFIG_PATA_SIS=m +CONFIG_PATA_VIA=m +CONFIG_PATA_WINBOND=m +# CONFIG_PATA_PLATFORM is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +# CONFIG_MD_RAID5_RESHAPE is not set +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_MIRROR=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_EMC=m +# CONFIG_DM_MULTIPATH_RDAC is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +CONFIG_FUSION=y +CONFIG_FUSION_SPI=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_SAS=m +CONFIG_FUSION_MAX_SGE=128 +CONFIG_FUSION_CTL=m +CONFIG_FUSION_LAN=m +# CONFIG_FUSION_LOGGING is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +CONFIG_IEEE1394=m + +# +# Subsystem Options +# +# CONFIG_IEEE1394_VERBOSEDEBUG is not set + +# +# Controllers +# +CONFIG_IEEE1394_PCILYNX=m +CONFIG_IEEE1394_OHCI1394=m + +# +# Protocols +# +CONFIG_IEEE1394_VIDEO1394=m +CONFIG_IEEE1394_SBP2=m +# CONFIG_IEEE1394_SBP2_PHYS_DMA is not set +CONFIG_IEEE1394_ETH1394_ROM_ENTRY=y +CONFIG_IEEE1394_ETH1394=m +CONFIG_IEEE1394_DV1394=m +CONFIG_IEEE1394_RAWIO=m +CONFIG_I2O=m +CONFIG_I2O_LCT_NOTIFY_ON_CHANGES=y +CONFIG_I2O_EXT_ADAPTEC=y +CONFIG_I2O_CONFIG=m +CONFIG_I2O_CONFIG_OLD_IOCTL=y +CONFIG_I2O_BUS=m +CONFIG_I2O_BLOCK=m +CONFIG_I2O_SCSI=m +CONFIG_I2O_PROC=m +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_IFB is not set +CONFIG_DUMMY=m +CONFIG_BONDING=m +# CONFIG_MACVLAN is not set +CONFIG_EQUALIZER=m +CONFIG_TUN=m +CONFIG_ARCNET=m +CONFIG_ARCNET_1201=m +CONFIG_ARCNET_1051=m +CONFIG_ARCNET_RAW=m +CONFIG_ARCNET_CAP=m +CONFIG_ARCNET_COM90xx=m +CONFIG_ARCNET_COM90xxIO=m +CONFIG_ARCNET_RIM_I=m +CONFIG_ARCNET_COM20020=m +CONFIG_ARCNET_COM20020_PCI=m +CONFIG_PHYLIB=m + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m +CONFIG_VITESSE_PHY=m +CONFIG_SMSC_PHY=m +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +CONFIG_FIXED_PHY=m +# CONFIG_FIXED_MII_10_FDX is not set +# CONFIG_FIXED_MII_100_FDX is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=m +# CONFIG_AX88796 is not set +# CONFIG_MIPS_AU1X00_ENET is not set +CONFIG_HAPPYMEAL=m +CONFIG_SUNGEM=m +CONFIG_CASSINI=m +CONFIG_NET_VENDOR_3COM=y +CONFIG_VORTEX=m +CONFIG_TYPHOON=m +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +CONFIG_NET_TULIP=y +CONFIG_DE2104X=m +CONFIG_TULIP=m +# CONFIG_TULIP_MWI is not set +# CONFIG_TULIP_MMIO is not set +# CONFIG_TULIP_NAPI is not set +CONFIG_DE4X5=m +CONFIG_WINBOND_840=m +CONFIG_DM9102=m +CONFIG_ULI526X=m +CONFIG_PCMCIA_XIRCOM=m +# CONFIG_PCMCIA_XIRTULIP is not set +CONFIG_HP100=m +CONFIG_NET_PCI=y +CONFIG_PCNET32=m +# CONFIG_PCNET32_NAPI is not set +CONFIG_AMD8111_ETH=m +# CONFIG_AMD8111E_NAPI is not set +CONFIG_ADAPTEC_STARFIRE=m +# CONFIG_ADAPTEC_STARFIRE_NAPI is not set +CONFIG_B44=m +CONFIG_FORCEDETH=m +# CONFIG_FORCEDETH_NAPI is not set +# CONFIG_TC35815 is not set +CONFIG_DGRS=m +CONFIG_EEPRO100=m +CONFIG_E100=m +CONFIG_FEALNX=m +CONFIG_NATSEMI=m +CONFIG_NE2K_PCI=m +CONFIG_8139CP=m +CONFIG_8139TOO=m +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +CONFIG_8139TOO_8129=y +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_SIS900=m +CONFIG_EPIC100=m +CONFIG_SUNDANCE=m +# CONFIG_SUNDANCE_MMIO is not set +CONFIG_TLAN=m +CONFIG_VIA_RHINE=m +# CONFIG_VIA_RHINE_MMIO is not set +# CONFIG_VIA_RHINE_NAPI is not set +# CONFIG_SC92031 is not set +CONFIG_NET_POCKET=y +CONFIG_DE600=m +CONFIG_DE620=m +CONFIG_NETDEV_1000=y +CONFIG_ACENIC=m +# CONFIG_ACENIC_OMIT_TIGON_I is not set +CONFIG_DL2K=m +CONFIG_E1000=m +# CONFIG_E1000_NAPI is not set +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +CONFIG_NS83820=m +CONFIG_HAMACHI=m +CONFIG_YELLOWFIN=m +CONFIG_R8169=m +# CONFIG_R8169_NAPI is not set +CONFIG_R8169_VLAN=y +CONFIG_SIS190=m +CONFIG_SKGE=m +CONFIG_SKY2=m +CONFIG_SK98LIN=m +CONFIG_VIA_VELOCITY=m +CONFIG_TIGON3=m +CONFIG_BNX2=m +CONFIG_QLA3XXX=m +# CONFIG_ATL1 is not set +CONFIG_NETDEV_10000=y +CONFIG_CHELSIO_T1=m +# CONFIG_CHELSIO_T1_1G is not set +CONFIG_CHELSIO_T1_NAPI=y +# CONFIG_CHELSIO_T3 is not set +CONFIG_IXGB=m +# CONFIG_IXGB_NAPI is not set +CONFIG_S2IO=m +# CONFIG_S2IO_NAPI is not set +CONFIG_MYRI10GE=m +# CONFIG_NETXEN_NIC is not set +# CONFIG_MLX4_CORE is not set +CONFIG_TR=y +CONFIG_IBMOL=m +CONFIG_IBMLS=m +CONFIG_3C359=m +CONFIG_TMS380TR=m +CONFIG_TMSPCI=m +CONFIG_ABYSS=m + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_USBNET_MII=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_CDCETHER=m +# CONFIG_USB_NET_DM9601 is not set +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +# CONFIG_USB_KC2190 is not set +CONFIG_USB_NET_ZAURUS=m +CONFIG_NET_PCMCIA=y +CONFIG_PCMCIA_3C589=m +CONFIG_PCMCIA_3C574=m +CONFIG_PCMCIA_FMVJ18X=m +CONFIG_PCMCIA_PCNET=m +CONFIG_PCMCIA_NMCLAN=m +CONFIG_PCMCIA_SMC91C92=m +CONFIG_PCMCIA_XIRC2PS=m +CONFIG_PCMCIA_AXNET=m +CONFIG_ARCNET_COM20020_CS=m +CONFIG_PCMCIA_IBMTR=m +CONFIG_WAN=y +CONFIG_LANMEDIA=m +CONFIG_HDLC=m +CONFIG_HDLC_RAW=m +CONFIG_HDLC_RAW_ETH=m +CONFIG_HDLC_CISCO=m +CONFIG_HDLC_FR=m +CONFIG_HDLC_PPP=m +CONFIG_HDLC_X25=m +CONFIG_PCI200SYN=m +CONFIG_WANXL=m +CONFIG_PC300=m +CONFIG_PC300_MLPPP=y + +# +# Cyclades-PC300 MLPPP support is disabled. +# + +# +# Refer to the file README.mlppp, provided by PC300 package. +# +# CONFIG_PC300TOO is not set +CONFIG_FARSYNC=m +CONFIG_DSCC4=m +CONFIG_DSCC4_PCISYNC=y +CONFIG_DSCC4_PCI_RST=y +CONFIG_DLCI=m +CONFIG_DLCI_MAX=8 +CONFIG_WAN_ROUTER_DRIVERS=m +CONFIG_CYCLADES_SYNC=m +CONFIG_CYCLOMX_X25=y +CONFIG_LAPBETHER=m +CONFIG_X25_ASY=m +CONFIG_ATM_DRIVERS=y +# CONFIG_ATM_DUMMY is not set +CONFIG_ATM_TCP=m +CONFIG_ATM_LANAI=m +CONFIG_ATM_ENI=m +# CONFIG_ATM_ENI_DEBUG is not set +# CONFIG_ATM_ENI_TUNE_BURST is not set +CONFIG_ATM_FIRESTREAM=m +CONFIG_ATM_ZATM=m +# CONFIG_ATM_ZATM_DEBUG is not set +CONFIG_ATM_NICSTAR=m +# CONFIG_ATM_NICSTAR_USE_SUNI is not set +# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set +CONFIG_ATM_IDT77252=m +# CONFIG_ATM_IDT77252_DEBUG is not set +# CONFIG_ATM_IDT77252_RCV_ALL is not set +CONFIG_ATM_IDT77252_USE_SUNI=y +CONFIG_ATM_AMBASSADOR=m +# CONFIG_ATM_AMBASSADOR_DEBUG is not set +CONFIG_ATM_HORIZON=m +# CONFIG_ATM_HORIZON_DEBUG is not set +CONFIG_ATM_IA=m +# CONFIG_ATM_IA_DEBUG is not set +CONFIG_ATM_FORE200E_MAYBE=m +CONFIG_ATM_FORE200E_PCA=y +CONFIG_ATM_FORE200E_PCA_DEFAULT_FW=y +# CONFIG_ATM_FORE200E_USE_TASKLET is not set +CONFIG_ATM_FORE200E_TX_RETRY=16 +CONFIG_ATM_FORE200E_DEBUG=0 +CONFIG_ATM_FORE200E=m +CONFIG_ATM_HE=m +CONFIG_ATM_HE_USE_SUNI=y +CONFIG_FDDI=y +CONFIG_DEFXX=m +# CONFIG_DEFXX_MMIO is not set +CONFIG_SKFP=m +CONFIG_HIPPI=y +CONFIG_ROADRUNNER=m +# CONFIG_ROADRUNNER_LARGE_RINGS is not set +CONFIG_PLIP=m +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPPOATM=m +# CONFIG_PPPOL2TP is not set +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLHC=m +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +CONFIG_NET_FC=y +CONFIG_SHAPER=m +CONFIG_NETCONSOLE=m +CONFIG_NETPOLL=y +# CONFIG_NETPOLL_TRAP is not set +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_ISDN=m +CONFIG_ISDN_I4L=m +CONFIG_ISDN_PPP=y +CONFIG_ISDN_PPP_VJ=y +CONFIG_ISDN_MPP=y +CONFIG_IPPP_FILTER=y +CONFIG_ISDN_PPP_BSDCOMP=m +CONFIG_ISDN_AUDIO=y +CONFIG_ISDN_TTY_FAX=y +CONFIG_ISDN_X25=y + +# +# ISDN feature submodules +# +# CONFIG_ISDN_DRV_LOOP is not set +CONFIG_ISDN_DIVERSION=m + +# +# ISDN4Linux hardware drivers +# + +# +# Passive cards +# +CONFIG_ISDN_DRV_HISAX=m + +# +# D-channel protocol features +# +CONFIG_HISAX_EURO=y +CONFIG_DE_AOC=y +# CONFIG_HISAX_NO_SENDCOMPLETE is not set +# CONFIG_HISAX_NO_LLC is not set +# CONFIG_HISAX_NO_KEYPAD is not set +CONFIG_HISAX_1TR6=y +CONFIG_HISAX_NI1=y +CONFIG_HISAX_MAX_CARDS=8 + +# +# HiSax supported cards +# +CONFIG_HISAX_16_3=y +CONFIG_HISAX_TELESPCI=y +CONFIG_HISAX_S0BOX=y +CONFIG_HISAX_FRITZPCI=y +CONFIG_HISAX_AVM_A1_PCMCIA=y +CONFIG_HISAX_ELSA=y +CONFIG_HISAX_DIEHLDIVA=y +CONFIG_HISAX_SEDLBAUER=y +CONFIG_HISAX_NETJET=y +CONFIG_HISAX_NETJET_U=y +CONFIG_HISAX_NICCY=y +CONFIG_HISAX_BKM_A4T=y +CONFIG_HISAX_SCT_QUADRO=y +CONFIG_HISAX_GAZEL=y +CONFIG_HISAX_HFC_PCI=y +CONFIG_HISAX_W6692=y +CONFIG_HISAX_HFC_SX=y +CONFIG_HISAX_ENTERNOW_PCI=y +# CONFIG_HISAX_DEBUG is not set + +# +# HiSax PCMCIA card service modules +# +CONFIG_HISAX_SEDLBAUER_CS=m +CONFIG_HISAX_ELSA_CS=m +CONFIG_HISAX_AVM_A1_CS=m +CONFIG_HISAX_TELES_CS=m + +# +# HiSax sub driver modules +# +CONFIG_HISAX_ST5481=m +CONFIG_HISAX_HFCUSB=m +CONFIG_HISAX_HFC4S8S=m +CONFIG_HISAX_FRITZ_PCIPNP=m +CONFIG_HISAX_HDLC=y + +# +# Active cards +# +# CONFIG_HYSDN is not set +CONFIG_ISDN_DRV_GIGASET=m +CONFIG_GIGASET_BASE=m +CONFIG_GIGASET_M105=m +# CONFIG_GIGASET_M101 is not set +# CONFIG_GIGASET_DEBUG is not set +# CONFIG_GIGASET_UNDOCREQ is not set +CONFIG_ISDN_CAPI=m +CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON=y +CONFIG_CAPI_TRACE=y +CONFIG_ISDN_CAPI_MIDDLEWARE=y +CONFIG_ISDN_CAPI_CAPI20=m +CONFIG_ISDN_CAPI_CAPIFS_BOOL=y +CONFIG_ISDN_CAPI_CAPIFS=m +CONFIG_ISDN_CAPI_CAPIDRV=m + +# +# CAPI hardware drivers +# +CONFIG_CAPI_AVM=y +CONFIG_ISDN_DRV_AVMB1_B1PCI=m +CONFIG_ISDN_DRV_AVMB1_B1PCIV4=y +CONFIG_ISDN_DRV_AVMB1_B1PCMCIA=m +CONFIG_ISDN_DRV_AVMB1_AVM_CS=m +CONFIG_ISDN_DRV_AVMB1_T1PCI=m +CONFIG_ISDN_DRV_AVMB1_C4=m +CONFIG_CAPI_EICON=y +CONFIG_ISDN_DIVAS=m +CONFIG_ISDN_DIVAS_BRIPCI=y +CONFIG_ISDN_DIVAS_PRIPCI=y +CONFIG_ISDN_DIVAS_DIVACAPI=m +CONFIG_ISDN_DIVAS_USERIDI=m +CONFIG_ISDN_DIVAS_MAINT=m +CONFIG_PHONE=m +CONFIG_PHONE_IXJ=m +CONFIG_PHONE_IXJ_PCMCIA=m + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_TSDEV=m +CONFIG_INPUT_TSDEV_SCREEN_X=240 +CONFIG_INPUT_TSDEV_SCREEN_Y=320 +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +CONFIG_KEYBOARD_SUNKBD=m +CONFIG_KEYBOARD_LKKBD=m +CONFIG_KEYBOARD_XTKBD=m +CONFIG_KEYBOARD_NEWTON=m +CONFIG_KEYBOARD_STOWAWAY=m +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=m +# CONFIG_MOUSE_APPLETOUCH is not set +CONFIG_MOUSE_VSXXXAA=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=y +CONFIG_JOYSTICK_IFORCE_232=y +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_DB9=m +CONFIG_JOYSTICK_GAMECON=m +CONFIG_JOYSTICK_TURBOGRAFX=m +CONFIG_JOYSTICK_JOYDUMP=m +# CONFIG_JOYSTICK_XPAD is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +# CONFIG_TOUCHSCREEN_FUJITSU is not set +CONFIG_TOUCHSCREEN_GUNZE=m +CONFIG_TOUCHSCREEN_ELO=m +CONFIG_TOUCHSCREEN_MTOUCH=m +CONFIG_TOUCHSCREEN_MK712=m +CONFIG_TOUCHSCREEN_PENMOUNT=m +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m +CONFIG_TOUCHSCREEN_TOUCHWIN=m +# CONFIG_TOUCHSCREEN_UCB1400 is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_PCSPKR=m +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +CONFIG_INPUT_UINPUT=m + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_PARKBD=m +CONFIG_SERIO_PCIPS2=m +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m +CONFIG_GAMEPORT_EMU10K1=m +CONFIG_GAMEPORT_FM801=m + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_COMPUTONE is not set +CONFIG_ROCKETPORT=m +CONFIG_CYCLADES=m +# CONFIG_CYZ_INTR is not set +CONFIG_DIGIEPCA=m +# CONFIG_MOXA_INTELLIO is not set +CONFIG_MOXA_SMARTIO=m +# CONFIG_MOXA_SMARTIO_NEW is not set +# CONFIG_ISI is not set +CONFIG_SYNCLINKMP=m +CONFIG_SYNCLINK_GT=m +CONFIG_N_HDLC=m +# CONFIG_RISCOM8 is not set +CONFIG_SPECIALIX=m +# CONFIG_SPECIALIX_RTSCTS is not set +CONFIG_SX=m +# CONFIG_RIO is not set +CONFIG_STALDRV=y +# CONFIG_STALLION is not set +# CONFIG_ISTALLION is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=m +CONFIG_SERIAL_8250_PCI=m +CONFIG_SERIAL_8250_CS=m +CONFIG_SERIAL_8250_NR_UARTS=48 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_RSA=y +# CONFIG_SERIAL_8250_AU1X00 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=m +CONFIG_SERIAL_JSM=m +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_PRINTER=m +# CONFIG_LP_CONSOLE is not set +CONFIG_PPDEV=m +CONFIG_TIPAR=m +CONFIG_IPMI_HANDLER=m +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +CONFIG_SOFT_WATCHDOG=m +# CONFIG_WDT_MTX1 is not set + +# +# PCI-based Watchdog Cards +# +CONFIG_PCIPCWATCHDOG=m +CONFIG_WDTPCI=m +CONFIG_WDT_501_PCI=y + +# +# USB-based Watchdog Cards +# +CONFIG_USBPCWATCHDOG=m +CONFIG_HW_RANDOM=y +CONFIG_RTC=y +CONFIG_R3964=m +CONFIG_APPLICOM=m +CONFIG_DRM=m +CONFIG_DRM_TDFX=m +CONFIG_DRM_R128=m +CONFIG_DRM_RADEON=m +CONFIG_DRM_MGA=m +CONFIG_DRM_VIA=m +CONFIG_DRM_SAVAGE=m + +# +# PCMCIA character devices +# +CONFIG_SYNCLINK_CS=m +CONFIG_CARDMAN_4000=m +CONFIG_CARDMAN_4040=m +CONFIG_RAW_DRIVER=m +CONFIG_MAX_RAW_DEVS=256 +CONFIG_TCG_TPM=m +CONFIG_TCG_ATMEL=m +CONFIG_DEVPORT=y +CONFIG_I2C=m +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=m + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=m +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# +CONFIG_I2C_ALI1535=m +CONFIG_I2C_ALI1563=m +CONFIG_I2C_ALI15X3=m +CONFIG_I2C_AMD756=m +CONFIG_I2C_AMD756_S4882=m +CONFIG_I2C_AMD8111=m +CONFIG_I2C_I801=m +CONFIG_I2C_I810=m +CONFIG_I2C_PIIX4=m +CONFIG_I2C_NFORCE2=m +CONFIG_I2C_OCORES=m +CONFIG_I2C_PARPORT=m +CONFIG_I2C_PARPORT_LIGHT=m +CONFIG_I2C_PROSAVAGE=m +CONFIG_I2C_SAVAGE4=m +# CONFIG_I2C_SIMTEC is not set +CONFIG_I2C_SIS5595=m +CONFIG_I2C_SIS630=m +CONFIG_I2C_SIS96X=m +# CONFIG_I2C_TAOS_EVM is not set +CONFIG_I2C_STUB=m +# CONFIG_I2C_TINY_USB is not set +CONFIG_I2C_VIA=m +CONFIG_I2C_VIAPRO=m +CONFIG_I2C_VOODOO3=m + +# +# Miscellaneous I2C Chip support +# +CONFIG_SENSORS_DS1337=m +CONFIG_SENSORS_DS1374=m +# CONFIG_DS1682 is not set +CONFIG_SENSORS_EEPROM=m +CONFIG_SENSORS_PCF8574=m +CONFIG_SENSORS_PCA9539=m +CONFIG_SENSORS_PCF8591=m +CONFIG_SENSORS_MAX6875=m +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=m +CONFIG_SPI_BUTTERFLY=m +# CONFIG_SPI_LM70_LLP is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +CONFIG_W1=m +CONFIG_W1_CON=y + +# +# 1-wire Bus Masters +# +CONFIG_W1_MASTER_MATROX=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m + +# +# 1-wire Slaves +# +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2433=m +# CONFIG_W1_SLAVE_DS2433_CRC is not set +# CONFIG_W1_SLAVE_DS2760 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +CONFIG_HWMON_VID=m +CONFIG_SENSORS_ABITUGURU=m +# CONFIG_SENSORS_ABITUGURU3 is not set +# CONFIG_SENSORS_AD7418 is not set +CONFIG_SENSORS_ADM1021=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +# CONFIG_SENSORS_ADM1029 is not set +CONFIG_SENSORS_ADM1031=m +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ASB100=m +CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_FSCHER=m +CONFIG_SENSORS_FSCPOS=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM70=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +# CONFIG_SENSORS_LM93 is not set +CONFIG_SENSORS_MAX1619=m +# CONFIG_SENSORS_MAX6650 is not set +CONFIG_SENSORS_PC87360=m +# CONFIG_SENSORS_PC87427 is not set +CONFIG_SENSORS_SIS5595=m +# CONFIG_SENSORS_DME1737 is not set +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SMSC47B397=m +# CONFIG_SENSORS_THMC50 is not set +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +# CONFIG_SENSORS_W83793 is not set +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83627EHF=m +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_VIDEO_TVAUDIO=m +CONFIG_VIDEO_TDA7432=m +CONFIG_VIDEO_TDA9840=m +CONFIG_VIDEO_TDA9875=m +CONFIG_VIDEO_TEA6415C=m +CONFIG_VIDEO_TEA6420=m +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_WM8775=m +CONFIG_VIDEO_BT819=m +CONFIG_VIDEO_BT856=m +CONFIG_VIDEO_KS0127=m +CONFIG_VIDEO_SAA7110=m +CONFIG_VIDEO_SAA7111=m +CONFIG_VIDEO_SAA7114=m +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_VPX3220=m +CONFIG_VIDEO_CX25840=m +CONFIG_VIDEO_CX2341X=m +CONFIG_VIDEO_SAA7185=m +CONFIG_VIDEO_ADV7170=m +CONFIG_VIDEO_ADV7175=m +CONFIG_VIDEO_VIVI=m +CONFIG_VIDEO_BT848=m +CONFIG_VIDEO_BT848_DVB=y +CONFIG_VIDEO_SAA6588=m +CONFIG_VIDEO_BWQCAM=m +CONFIG_VIDEO_CQCAM=m +CONFIG_VIDEO_W9966=m +CONFIG_VIDEO_CPIA=m +CONFIG_VIDEO_CPIA_PP=m +CONFIG_VIDEO_CPIA_USB=m +CONFIG_VIDEO_CPIA2=m +CONFIG_VIDEO_SAA5246A=m +CONFIG_VIDEO_SAA5249=m +CONFIG_TUNER_3036=m +# CONFIG_TUNER_TEA5761 is not set +CONFIG_VIDEO_STRADIS=m +CONFIG_VIDEO_ZORAN_ZR36060=m +CONFIG_VIDEO_ZORAN=m +CONFIG_VIDEO_ZORAN_BUZ=m +CONFIG_VIDEO_ZORAN_DC10=m +CONFIG_VIDEO_ZORAN_DC30=m +CONFIG_VIDEO_ZORAN_LML33=m +CONFIG_VIDEO_ZORAN_LML33R10=m +CONFIG_VIDEO_ZORAN_AVS6EYES=m +CONFIG_VIDEO_SAA7134=m +CONFIG_VIDEO_SAA7134_ALSA=m +CONFIG_VIDEO_SAA7134_OSS=m +CONFIG_VIDEO_SAA7134_DVB=m +CONFIG_VIDEO_MXB=m +CONFIG_VIDEO_DPC=m +CONFIG_VIDEO_HEXIUM_ORION=m +CONFIG_VIDEO_HEXIUM_GEMINI=m +CONFIG_VIDEO_CX88=m +CONFIG_VIDEO_CX88_ALSA=m +CONFIG_VIDEO_CX88_BLACKBIRD=m +CONFIG_VIDEO_CX88_DVB=m +CONFIG_VIDEO_CX88_VP3054=m +# CONFIG_VIDEO_IVTV is not set +# CONFIG_VIDEO_CAFE_CCIC is not set +CONFIG_V4L_USB_DRIVERS=y +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_29XXX=y +CONFIG_VIDEO_PVRUSB2_24XXX=y +CONFIG_VIDEO_PVRUSB2_SYSFS=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_EM28XX=m +# CONFIG_VIDEO_USBVISION is not set +CONFIG_VIDEO_USBVIDEO=m +CONFIG_USB_VICAM=m +CONFIG_USB_IBMCAM=m +CONFIG_USB_KONICAWC=m +CONFIG_USB_QUICKCAM_MESSENGER=m +CONFIG_USB_ET61X251=m +CONFIG_VIDEO_OVCAMCHIP=m +CONFIG_USB_W9968CF=m +# CONFIG_USB_OV511 is not set +CONFIG_USB_SE401=m +CONFIG_USB_SN9C102=m +CONFIG_USB_STV680=m +CONFIG_USB_ZC0301=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +# CONFIG_USB_ZR364XX is not set +CONFIG_RADIO_ADAPTERS=y +CONFIG_RADIO_GEMTEK_PCI=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_MAESTRO=m +CONFIG_USB_DSBR=m +CONFIG_DVB_CORE=m +CONFIG_DVB_CORE_ATTACH=y +CONFIG_DVB_CAPTURE_DRIVERS=y + +# +# Supported SAA7146 based PCI Adapters +# +CONFIG_DVB_AV7110=m +CONFIG_DVB_AV7110_OSD=y +CONFIG_DVB_BUDGET=m +CONFIG_DVB_BUDGET_CI=m +CONFIG_DVB_BUDGET_AV=m +CONFIG_DVB_BUDGET_PATCH=m + +# +# Supported USB Adapters +# +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_CXUSB=m +# CONFIG_DVB_USB_M920X is not set +# CONFIG_DVB_USB_GL861 is not set +# CONFIG_DVB_USB_AU6610 is not set +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_NOVA_T_USB2=m +# CONFIG_DVB_USB_TTUSB2 is not set +CONFIG_DVB_USB_DTT200U=m +# CONFIG_DVB_USB_OPERA1 is not set +# CONFIG_DVB_USB_AF9005 is not set +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +CONFIG_DVB_CINERGYT2=m +CONFIG_DVB_CINERGYT2_TUNING=y +CONFIG_DVB_CINERGYT2_STREAM_URB_COUNT=32 +CONFIG_DVB_CINERGYT2_STREAM_BUF_SIZE=512 +CONFIG_DVB_CINERGYT2_QUERY_INTERVAL=250 +CONFIG_DVB_CINERGYT2_ENABLE_RC_INPUT_DEVICE=y +CONFIG_DVB_CINERGYT2_RC_QUERY_INTERVAL=100 + +# +# Supported FlexCopII (B2C2) Adapters +# +CONFIG_DVB_B2C2_FLEXCOP=m +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set + +# +# Supported BT878 Adapters +# +CONFIG_DVB_BT8XX=m + +# +# Supported Pluto2 Adapters +# +CONFIG_DVB_PLUTO2=m + +# +# Supported DVB Frontends +# + +# +# Customise DVB Frontends +# +# CONFIG_DVB_FE_CUSTOMISE is not set + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_STV0299=m +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_MT312=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_TDA10086=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_SP8870=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_L64781=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_MT352=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_VES1820=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_STV0297=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_NXT200X=m +CONFIG_DVB_OR51211=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LGDT330X=m + +# +# Tuners/PLL support +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TDA827X=m +# CONFIG_DVB_TUNER_QT1010 is not set +CONFIG_DVB_TUNER_MT2060=m + +# +# Miscellaneous devices +# +CONFIG_DVB_LNBP21=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_TUA6100=m +CONFIG_VIDEO_SAA7146=m +CONFIG_VIDEO_SAA7146_VV=m +CONFIG_VIDEO_TUNER=m +CONFIG_VIDEO_BUF=m +CONFIG_VIDEO_BUF_DVB=m +CONFIG_VIDEO_BTCX=m +CONFIG_VIDEO_IR_I2C=m +CONFIG_VIDEO_IR=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_DAB=y +CONFIG_USB_DABUSB=m + +# +# Graphics support +# +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=m +CONFIG_BACKLIGHT_CLASS_DEVICE=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +CONFIG_VGASTATE=m +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_DDC=m +CONFIG_FB_CFB_FILLRECT=m +CONFIG_FB_CFB_COPYAREA=m +CONFIG_FB_CFB_IMAGEBLIT=m +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +CONFIG_FB_BACKLIGHT=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +CONFIG_FB_CIRRUS=m +CONFIG_FB_PM2=m +CONFIG_FB_PM2_FIFO_DISCONNECT=y +CONFIG_FB_CYBER2000=m +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +CONFIG_FB_S1D13XXX=m +CONFIG_FB_NVIDIA=m +CONFIG_FB_NVIDIA_I2C=y +# CONFIG_FB_NVIDIA_DEBUG is not set +CONFIG_FB_NVIDIA_BACKLIGHT=y +CONFIG_FB_RIVA=m +CONFIG_FB_RIVA_I2C=y +# CONFIG_FB_RIVA_DEBUG is not set +CONFIG_FB_RIVA_BACKLIGHT=y +CONFIG_FB_MATROX=m +CONFIG_FB_MATROX_MILLENIUM=y +CONFIG_FB_MATROX_MYSTIQUE=y +CONFIG_FB_MATROX_G=y +CONFIG_FB_MATROX_I2C=m +CONFIG_FB_MATROX_MAVEN=m +CONFIG_FB_MATROX_MULTIHEAD=y +CONFIG_FB_RADEON=m +CONFIG_FB_RADEON_I2C=y +CONFIG_FB_RADEON_BACKLIGHT=y +# CONFIG_FB_RADEON_DEBUG is not set +CONFIG_FB_ATY128=m +CONFIG_FB_ATY128_BACKLIGHT=y +CONFIG_FB_ATY=m +CONFIG_FB_ATY_CT=y +CONFIG_FB_ATY_GENERIC_LCD=y +CONFIG_FB_ATY_GX=y +CONFIG_FB_ATY_BACKLIGHT=y +# CONFIG_FB_S3 is not set +CONFIG_FB_SAVAGE=m +CONFIG_FB_SAVAGE_I2C=y +CONFIG_FB_SAVAGE_ACCEL=y +CONFIG_FB_SIS=m +CONFIG_FB_SIS_300=y +CONFIG_FB_SIS_315=y +CONFIG_FB_NEOMAGIC=m +CONFIG_FB_KYRO=m +CONFIG_FB_3DFX=m +# CONFIG_FB_3DFX_ACCEL is not set +CONFIG_FB_VOODOO1=m +# CONFIG_FB_VT8623 is not set +CONFIG_FB_TRIDENT=m +# CONFIG_FB_TRIDENT_ACCEL is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +# CONFIG_VGACON_SOFT_SCROLLBACK is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=m +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_LOGO is not set + +# +# Sound +# +CONFIG_SOUND=m + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_HWDEP=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +CONFIG_SND_RTCTIMER=m +CONFIG_SND_SEQ_RTCTIMER_DEFAULT=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +CONFIG_SND_MPU401_UART=m +CONFIG_SND_OPL3_LIB=m +CONFIG_SND_VX_LIB=m +CONFIG_SND_AC97_CODEC=m +CONFIG_SND_DUMMY=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_MTS64=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_MPU401=m +# CONFIG_SND_PORTMAN2X4 is not set + +# +# PCI devices +# +CONFIG_SND_AD1889=m +CONFIG_SND_ALS300=m +CONFIG_SND_ALI5451=m +CONFIG_SND_ATIIXP=m +CONFIG_SND_ATIIXP_MODEM=m +CONFIG_SND_AU8810=m +CONFIG_SND_AU8820=m +CONFIG_SND_AU8830=m +CONFIG_SND_AZT3328=m +CONFIG_SND_BT87X=m +# CONFIG_SND_BT87X_OVERCLOCK is not set +CONFIG_SND_CA0106=m +CONFIG_SND_CMIPCI=m +CONFIG_SND_CS4281=m +CONFIG_SND_CS46XX=m +CONFIG_SND_CS46XX_NEW_DSP=y +CONFIG_SND_DARLA20=m +CONFIG_SND_GINA20=m +CONFIG_SND_LAYLA20=m +CONFIG_SND_DARLA24=m +CONFIG_SND_GINA24=m +CONFIG_SND_LAYLA24=m +CONFIG_SND_MONA=m +CONFIG_SND_MIA=m +CONFIG_SND_ECHO3G=m +CONFIG_SND_INDIGO=m +CONFIG_SND_INDIGOIO=m +CONFIG_SND_INDIGODJ=m +CONFIG_SND_EMU10K1=m +CONFIG_SND_EMU10K1X=m +CONFIG_SND_ENS1370=m +CONFIG_SND_ENS1371=m +CONFIG_SND_ES1938=m +CONFIG_SND_ES1968=m +CONFIG_SND_FM801=m +CONFIG_SND_FM801_TEA575X_BOOL=y +CONFIG_SND_FM801_TEA575X=m +CONFIG_SND_HDA_INTEL=m +CONFIG_SND_HDSP=m +CONFIG_SND_HDSPM=m +CONFIG_SND_ICE1712=m +CONFIG_SND_ICE1724=m +CONFIG_SND_INTEL8X0=m +CONFIG_SND_INTEL8X0M=m +CONFIG_SND_KORG1212=m +CONFIG_SND_KORG1212_FIRMWARE_IN_KERNEL=y +CONFIG_SND_MAESTRO3=m +CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL=y +CONFIG_SND_MIXART=m +CONFIG_SND_NM256=m +CONFIG_SND_PCXHR=m +CONFIG_SND_RIPTIDE=m +CONFIG_SND_RME32=m +CONFIG_SND_RME96=m +CONFIG_SND_RME9652=m +CONFIG_SND_SONICVIBES=m +CONFIG_SND_TRIDENT=m +CONFIG_SND_VIA82XX=m +CONFIG_SND_VIA82XX_MODEM=m +CONFIG_SND_VX222=m +CONFIG_SND_YMFPCI=m +CONFIG_SND_YMFPCI_FIRMWARE_IN_KERNEL=y +# CONFIG_SND_AC97_POWER_SAVE is not set + +# +# ALSA MIPS devices +# +# CONFIG_SND_AU1X00 is not set + +# +# USB devices +# +CONFIG_SND_USB_AUDIO=m +# CONFIG_SND_USB_CAIAQ is not set + +# +# PCMCIA devices +# +CONFIG_SND_VXPOCKET=m +CONFIG_SND_PDAUDIOCF=m + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# SoC Audio support for SuperH +# + +# +# Open Sound System +# +CONFIG_SOUND_PRIME=m +CONFIG_SOUND_TRIDENT=m +# CONFIG_SOUND_MSNDCLAS is not set +# CONFIG_SOUND_MSNDPIN is not set +CONFIG_AC97_BUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=m +CONFIG_USB_HIDINPUT_POWERBOOK=y +# CONFIG_HID_FF is not set +CONFIG_USB_HIDDEV=y + +# +# USB HID Boot Protocol drivers +# +CONFIG_USB_KBD=m +CONFIG_USB_MOUSE=m +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=m +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y +# CONFIG_USB_PERSIST is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=m +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=m +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=m +CONFIG_USB_U132_HCD=m +CONFIG_USB_SL811_HCD=m +CONFIG_USB_SL811_CS=m +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_DPCM=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USB_MON=y + +# +# USB port drivers +# +CONFIG_USB_USS720=m + +# +# USB Serial Converter support +# +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_AIRPRIME=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP2101=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_FUNSOFT=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19QW is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19QI is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA49WLC is not set +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +# CONFIG_USB_SERIAL_OTI6858 is not set +CONFIG_USB_SERIAL_HP4X=m +CONFIG_USB_SERIAL_SAFE=m +# CONFIG_USB_SERIAL_SAFE_PADDED is not set +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +# CONFIG_USB_SERIAL_DEBUG is not set +CONFIG_USB_EZUSB=y + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_AUERSWALD=m +CONFIG_USB_RIO500=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +# CONFIG_USB_BERRY_CHARGE is not set +CONFIG_USB_LED=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_PHIDGET=m +CONFIG_USB_PHIDGETKIT=m +CONFIG_USB_PHIDGETMOTORCONTROL=m +CONFIG_USB_PHIDGETSERVO=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_SISUSBVGA=m +# CONFIG_USB_SISUSBVGA_CON is not set +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +CONFIG_USB_GADGET_NET2280=y +CONFIG_USB_NET2280=m +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_MMC=m +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_BOUNCE=y + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_SDHCI=m +CONFIG_MMC_TIFM_SD=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=m + +# +# LED drivers +# + +# +# LED Triggers +# +# CONFIG_LEDS_TRIGGERS is not set +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_USER_MEM=y +CONFIG_INFINIBAND_ADDR_TRANS=y +CONFIG_INFINIBAND_MTHCA=m +CONFIG_INFINIBAND_MTHCA_DEBUG=y +CONFIG_INFINIBAND_AMSO1100=m +CONFIG_INFINIBAND_AMSO1100_DEBUG=y +# CONFIG_MLX4_INFINIBAND is not set +CONFIG_INFINIBAND_IPOIB=m +# CONFIG_INFINIBAND_IPOIB_CM is not set +CONFIG_INFINIBAND_IPOIB_DEBUG=y +# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_ISER=m +CONFIG_RTC_LIB=m +CONFIG_RTC_CLASS=m + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_TEST=m + +# +# I2C RTC drivers +# +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1672=m +# CONFIG_RTC_DRV_MAX6900 is not set +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +# CONFIG_RTC_DRV_M41T80 is not set + +# +# SPI RTC drivers +# +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_MAX6902=m + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +CONFIG_RTC_DRV_DS1553=m +# CONFIG_RTC_DRV_STK17TA8 is not set +CONFIG_RTC_DRV_DS1742=m +CONFIG_RTC_DRV_M48T86=m +# CONFIG_RTC_DRV_M48T59 is not set +CONFIG_RTC_DRV_V3020=m + +# +# on-CPU RTC drivers +# + +# +# DMA Engine support +# +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +CONFIG_NET_DMA=y + +# +# DMA Devices +# +CONFIG_INTEL_IOATDMA=m +# CONFIG_AUXDISPLAY is not set + +# +# Userspace I/O +# +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=m +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=m +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=m +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=m +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +# CONFIG_JFS_DEBUG is not set +CONFIG_JFS_STATISTICS=y +CONFIG_FS_POSIX_ACL=y +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_SECURITY=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_MINIX_FS=m +CONFIG_ROMFS_FS=m +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y +CONFIG_DNOTIFY=y +CONFIG_AUTOFS_FS=m +CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +CONFIG_CONFIGFS_FS=m + +# +# Miscellaneous filesystems +# +CONFIG_ADFS_FS=m +# CONFIG_ADFS_FS_RW is not set +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +CONFIG_VXFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +CONFIG_NFS_DIRECTIO=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +CONFIG_NFSD_V4=y +CONFIG_NFSD_TCP=y +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +# CONFIG_SUNRPC_BIND34 is not set +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPCSEC_GSS_SPKM3=m +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_XATTR is not set +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_EXPERIMENTAL is not set +CONFIG_NCP_FS=m +CONFIG_NCPFS_PACKET_SIGNING=y +CONFIG_NCPFS_IOCTL_LOCKING=y +CONFIG_NCPFS_STRONG=y +CONFIG_NCPFS_NFS_NS=y +CONFIG_NCPFS_OS2_NS=y +# CONFIG_NCPFS_SMALLDOS is not set +CONFIG_NCPFS_NLS=y +CONFIG_NCPFS_EXTRAS=y +CONFIG_CODA_FS=m +# CONFIG_CODA_FS_OLD_API is not set +CONFIG_AFS_FS=m +# CONFIG_AFS_DEBUG is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +CONFIG_ACORN_PARTITION=y +# CONFIG_ACORN_PARTITION_CUMANA is not set +# CONFIG_ACORN_PARTITION_EESOX is not set +CONFIG_ACORN_PARTITION_ICS=y +# CONFIG_ACORN_PARTITION_ADFS is not set +# CONFIG_ACORN_PARTITION_POWERTEC is not set +CONFIG_ACORN_PARTITION_RISCIX=y +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m + +# +# Distributed Lock Manager +# +CONFIG_DLM=m +# CONFIG_DLM_DEBUG is not set + +# +# Profiling support +# +CONFIG_PROFILING=y +CONFIG_OPROFILE=m + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_CROSSCOMPILE is not set +CONFIG_CMDLINE="" +CONFIG_SYS_SUPPORTS_KGDB=y + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +CONFIG_SECURITY=y +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +CONFIG_SECURITY_CAPABILITIES=m +CONFIG_SECURITY_ROOTPLUG=m +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SELINUX_ENABLE_SECMARK_DEFAULT is not set +# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_REED_SOLOMON=m +CONFIG_REED_SOLOMON_DEC16=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_CHECK_SIGNATURE=y -- cgit v0.10.2 From b4126e86301cfc6863cbc74bc4500a88b7c582df Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Tue, 2 Oct 2007 22:54:41 +0900 Subject: [MIPS] Cobalt: Move PCI definitions to arch/mips/pci/fixup-cobalt.c. These PCI definitions are only used in arch/mips/pci/fixup-cobalt.c. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c index 4eb5410..f7df114 100644 --- a/arch/mips/pci/fixup-cobalt.c +++ b/arch/mips/pci/fixup-cobalt.c @@ -20,6 +20,23 @@ #include #include +/* + * PCI slot numbers + */ +#define COBALT_PCICONF_CPU 0x06 +#define COBALT_PCICONF_ETH0 0x07 +#define COBALT_PCICONF_RAQSCSI 0x08 +#define COBALT_PCICONF_VIA 0x09 +#define COBALT_PCICONF_PCISLOT 0x0A +#define COBALT_PCICONF_ETH1 0x0C + +/* + * The Cobalt board ID information. The boards have an ID number wired + * into the VIA that is available in the high nibble of register 94. + */ +#define VIA_COBALT_BRD_ID_REG 0x94 +#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4) + static void qube_raq_galileo_early_fixup(struct pci_dev *dev) { if (dev->devfn == PCI_DEVFN(0, 0) && diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h index 408eecc..f27fcef 100644 --- a/include/asm-mips/mach-cobalt/cobalt.h +++ b/include/asm-mips/mach-cobalt/cobalt.h @@ -13,37 +13,15 @@ #define __ASM_COBALT_H /* - * PCI configuration space manifest constants. These are wired into - * the board layout according to the PCI spec to enable the software - * to probe the hardware configuration space in a well defined manner. - * - * The PCI_DEVSHFT() macro transforms these values into numbers - * suitable for passing as the dev parameter to the various - * pcibios_read/write_config routines. + * The Cobalt board ID information. */ -#define COBALT_PCICONF_CPU 0x06 -#define COBALT_PCICONF_ETH0 0x07 -#define COBALT_PCICONF_RAQSCSI 0x08 -#define COBALT_PCICONF_VIA 0x09 -#define COBALT_PCICONF_PCISLOT 0x0A -#define COBALT_PCICONF_ETH1 0x0C - +extern int cobalt_board_id; -/* - * The Cobalt board id information. The boards have an ID number wired - * into the VIA that is available in the high nibble of register 94. - * This register is available in the VIA configuration space through the - * interface routines qube_pcibios_read/write_config. See cobalt/pci.c - */ -#define VIA_COBALT_BRD_ID_REG 0x94 -#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char) (reg) >> 4) #define COBALT_BRD_ID_QUBE1 0x3 #define COBALT_BRD_ID_RAQ1 0x4 #define COBALT_BRD_ID_QUBE2 0x5 #define COBALT_BRD_ID_RAQ2 0x6 -extern int cobalt_board_id; - #define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000)) # define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */ # define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */ -- cgit v0.10.2 From 5a860424a1bcf21655d993a7c09b36662e34d2a9 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Tue, 2 Oct 2007 23:13:17 +0900 Subject: [MIPS] Cobalt: Move UART base definition to arch/mips/cobalt/console.c They're only used in arch/mips/cobalt/console.c. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/arch/mips/cobalt/console.c b/arch/mips/cobalt/console.c index 0485d51..db330e8 100644 --- a/arch/mips/cobalt/console.c +++ b/arch/mips/cobalt/console.c @@ -1,16 +1,15 @@ /* * (C) P. Horton 2006 */ +#include #include -#include - -#include +#define UART_BASE ((void __iomem *)CKSEG1ADDR(0x1c800000)) void prom_putchar(char c) { - while(!(COBALT_UART[UART_LSR] & UART_LSR_THRE)) + while (!(readb(UART_BASE + UART_LSR) & UART_LSR_THRE)) ; - COBALT_UART[UART_TX] = c; + writeb(c, UART_BASE + UART_TX); } diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h index f27fcef..4cb5844 100644 --- a/include/asm-mips/mach-cobalt/cobalt.h +++ b/include/asm-mips/mach-cobalt/cobalt.h @@ -39,6 +39,4 @@ extern int cobalt_board_id; # define COBALT_KEY_SELECT (1 << 7) # define COBALT_KEY_MASK 0xfe -#define COBALT_UART ((volatile unsigned char *) CKSEG1ADDR(0x1c800000)) - #endif /* __ASM_COBALT_H */ -- cgit v0.10.2 From 3282bd3cb0c7653e604c0d3666331281ae8f74c4 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Tue, 2 Oct 2007 23:17:38 +0900 Subject: [MIPS] Cobalt: Move reset port definition to arch/mips/cobalt/reset.c It's only used in arch/mips/cobalt/reset.c. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/arch/mips/cobalt/reset.c b/arch/mips/cobalt/reset.c index f503a0d..81628b3 100644 --- a/arch/mips/cobalt/reset.c +++ b/arch/mips/cobalt/reset.c @@ -9,11 +9,15 @@ * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv) */ #include +#include #include #include #include +#define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000)) +#define RESET 0x0f + DEFINE_LED_TRIGGER(power_off_led_trigger); static int __init ledtrig_power_off_init(void) @@ -43,7 +47,7 @@ void cobalt_machine_halt(void) last ^= diff; if((diff & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)) && !(~last & (COBALT_KEY_ENTER | COBALT_KEY_SELECT))) - COBALT_LED_PORT = COBALT_LED_RESET; + writeb(RESET, RESET_PORT); for (mark = jiffies; jiffies - mark < HZ;) ; @@ -52,7 +56,7 @@ void cobalt_machine_halt(void) void cobalt_machine_restart(char *command) { - COBALT_LED_PORT = COBALT_LED_RESET; + writeb(RESET, RESET_PORT); /* we should never get here */ cobalt_machine_halt(); diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h index 4cb5844..a79e7ca 100644 --- a/include/asm-mips/mach-cobalt/cobalt.h +++ b/include/asm-mips/mach-cobalt/cobalt.h @@ -22,13 +22,6 @@ extern int cobalt_board_id; #define COBALT_BRD_ID_QUBE2 0x5 #define COBALT_BRD_ID_RAQ2 0x6 -#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000)) -# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */ -# define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */ -# define COBALT_LED_WEB (1 << 2) /* RaQ */ -# define COBALT_LED_POWER_OFF (1 << 3) /* RaQ */ -# define COBALT_LED_RESET 0x0f - #define COBALT_KEY_PORT ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK) # define COBALT_KEY_CLEAR (1 << 1) # define COBALT_KEY_LEFT (1 << 2) -- cgit v0.10.2 From f13558c2a4a7339192ff7148ee903340affdb790 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Tue, 2 Oct 2007 23:21:36 +0900 Subject: [MIPS] Cobalt: Remove cobalt_machine_power_off() It's same as cobalt_machine_halt(). Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/arch/mips/cobalt/reset.c b/arch/mips/cobalt/reset.c index 81628b3..71eb4cc 100644 --- a/arch/mips/cobalt/reset.c +++ b/arch/mips/cobalt/reset.c @@ -61,12 +61,3 @@ void cobalt_machine_restart(char *command) /* we should never get here */ cobalt_machine_halt(); } - -/* - * This triggers the luser mode device driver for the power switch ;-) - */ -void cobalt_machine_power_off(void) -{ - printk("You can switch the machine off now.\n"); - cobalt_machine_halt(); -} diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c index 345e4ae..d11bb1b 100644 --- a/arch/mips/cobalt/setup.c +++ b/arch/mips/cobalt/setup.c @@ -25,7 +25,6 @@ extern void cobalt_machine_restart(char *command); extern void cobalt_machine_halt(void); -extern void cobalt_machine_power_off(void); const char *get_system_type(void) { @@ -96,7 +95,7 @@ void __init plat_mem_setup(void) _machine_restart = cobalt_machine_restart; _machine_halt = cobalt_machine_halt; - pm_power_off = cobalt_machine_power_off; + pm_power_off = cobalt_machine_halt; set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE)); -- cgit v0.10.2 From 1ac74d528dcfe3dcaa6072289d71fa96569f5e39 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Tue, 2 Oct 2007 14:54:15 +0100 Subject: [MIPS] pg-r4k.c: Dump the generated code Dump the generated code for clear/copy page calls like it is done for TLB fault handlers. Useful for debugging. Signed-off-by: Maciej W. Rozycki Signed-off-by: Ralf Baechle diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c index e47e9e9..c029454 100644 --- a/arch/mips/mm/pg-r4k.c +++ b/arch/mips/mm/pg-r4k.c @@ -347,6 +347,7 @@ void __init build_clear_page(void) { unsigned int loop_start; unsigned long off; + int i; epc = (unsigned int *) &clear_page_array; instruction_pending = 0; @@ -434,12 +435,22 @@ dest = label(); build_jr_ra(); BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array)); + + pr_info("Synthesized clear page handler (%u instructions).\n", + (unsigned int)(epc - clear_page_array)); + + pr_debug("\t.set push\n"); + pr_debug("\t.set noreorder\n"); + for (i = 0; i < (epc - clear_page_array); i++) + pr_debug("\t.word 0x%08x\n", clear_page_array[i]); + pr_debug("\t.set pop\n"); } void __init build_copy_page(void) { unsigned int loop_start; unsigned long off; + int i; epc = (unsigned int *) ©_page_array; store_offset = load_offset = 0; @@ -515,4 +526,13 @@ dest = label(); build_jr_ra(); BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array)); + + pr_info("Synthesized copy page handler (%u instructions).\n", + (unsigned int)(epc - copy_page_array)); + + pr_debug("\t.set push\n"); + pr_debug("\t.set noreorder\n"); + for (i = 0; i < (epc - copy_page_array); i++) + pr_debug("\t.word 0x%08x\n", copy_page_array[i]); + pr_debug("\t.set pop\n"); } -- cgit v0.10.2 From aeffdbbaff133b0c3989e20af5baa091d3d0b409 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:14 +0100 Subject: [MIPS] tlbex: Size optimize code by declaring a few functions inline. Signed-off-by: Ralf Baechle diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index b2c6b9e..7325074 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -35,24 +35,24 @@ #include #include -static __init int __maybe_unused r45k_bvahwbug(void) +static inline int r45k_bvahwbug(void) { /* XXX: We should probe for the presence of this bug, but we don't. */ return 0; } -static __init int __maybe_unused r4k_250MHZhwbug(void) +static inline int r4k_250MHZhwbug(void) { /* XXX: We should probe for the presence of this bug, but we don't. */ return 0; } -static __init int __maybe_unused bcm1250_m3_war(void) +static inline int __maybe_unused bcm1250_m3_war(void) { return BCM1250_M3_WAR; } -static __init int __maybe_unused r10000_llsc_war(void) +static inline int __maybe_unused r10000_llsc_war(void) { return R10000_LLSC_WAR; } -- cgit v0.10.2 From 10cc3529072d5415fb040018a8a99aa7a60190b6 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:15 +0100 Subject: [MIPS] Allow hardwiring of the CPU type to a single type for optimization. This saves a few k on systems which only ever ship with a single CPU type. Signed-off-by: Ralf Baechle diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c index 6d55e8a..6a17c9b 100644 --- a/arch/mips/dec/ecc-berr.c +++ b/arch/mips/dec/ecc-berr.c @@ -263,7 +263,7 @@ static inline void dec_kn03_be_init(void) */ *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) | KN03_MCR_CORRECT; - if (current_cpu_data.cputype == CPU_R4400SC) + if (current_cpu_type() == CPU_R4400SC) *mbcs |= KN4K_MB_CSR_EE; fast_iob(); } diff --git a/arch/mips/dec/kn02xa-berr.c b/arch/mips/dec/kn02xa-berr.c index 7a053aa..5f04545 100644 --- a/arch/mips/dec/kn02xa-berr.c +++ b/arch/mips/dec/kn02xa-berr.c @@ -132,7 +132,7 @@ void __init dec_kn02xa_be_init(void) volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); /* For KN04 we need to make sure EE (?) is enabled in the MB. */ - if (current_cpu_data.cputype == CPU_R4000SC) + if (current_cpu_type() == CPU_R4000SC) *mbcs |= KN4K_MB_CSR_EE; fast_iob(); diff --git a/arch/mips/dec/prom/init.c b/arch/mips/dec/prom/init.c index 808c182..93f1239 100644 --- a/arch/mips/dec/prom/init.c +++ b/arch/mips/dec/prom/init.c @@ -108,8 +108,8 @@ void __init prom_init(void) /* Were we compiled with the right CPU option? */ #if defined(CONFIG_CPU_R3000) - if ((current_cpu_data.cputype == CPU_R4000SC) || - (current_cpu_data.cputype == CPU_R4400SC)) { + if ((current_cpu_type() == CPU_R4000SC) || + (current_cpu_type() == CPU_R4400SC)) { static char r4k_msg[] __initdata = "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n"; printk(cpu_msg); @@ -119,8 +119,8 @@ void __init prom_init(void) #endif #if defined(CONFIG_CPU_R4X00) - if ((current_cpu_data.cputype == CPU_R3000) || - (current_cpu_data.cputype == CPU_R3000A)) { + if ((current_cpu_type() == CPU_R3000) || + (current_cpu_type() == CPU_R3000A)) { static char r3k_msg[] __initdata = "Please recompile with \"CONFIG_CPU_R3000 = y\".\n"; printk(cpu_msg); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index d96f821..ac762d8 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -954,7 +954,7 @@ asmlinkage void do_reserved(struct pt_regs *regs) */ static inline void parity_protection_init(void) { - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_24K: case CPU_34K: case CPU_5KC: @@ -1549,8 +1549,8 @@ void __init trap_init(void) set_except_vector(12, handle_ov); set_except_vector(13, handle_tr); - if (current_cpu_data.cputype == CPU_R6000 || - current_cpu_data.cputype == CPU_R6000A) { + if (current_cpu_type() == CPU_R6000 || + current_cpu_type() == CPU_R6000A) { /* * The R6000 is the only R-series CPU that features a machine * check exception (similar to the R4000 cache error) and diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index cf48371..8b7b7c5 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -328,7 +328,7 @@ static inline void local_r4k___flush_cache_all(void * args) r4k_blast_dcache(); r4k_blast_icache(); - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_R4000SC: case CPU_R4000MC: case CPU_R4400SC: @@ -377,10 +377,10 @@ static inline void local_r4k_flush_cache_mm(void * args) * R4000SC and R4400SC indexed S-cache ops also invalidate primary * caches, so we can bail out early. */ - if (current_cpu_data.cputype == CPU_R4000SC || - current_cpu_data.cputype == CPU_R4000MC || - current_cpu_data.cputype == CPU_R4400SC || - current_cpu_data.cputype == CPU_R4400MC) { + if (current_cpu_type() == CPU_R4000SC || + current_cpu_type() == CPU_R4000MC || + current_cpu_type() == CPU_R4400SC || + current_cpu_type() == CPU_R4400MC) { r4k_blast_scache(); return; } @@ -1197,7 +1197,7 @@ static void __init coherency_setup(void) * this bit and; some wire it to zero, others like Toshiba had the * silly idea of putting something else there ... */ - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_R4000PC: case CPU_R4000SC: case CPU_R4000MC: diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c index 560a6de..9ea121e 100644 --- a/arch/mips/mm/c-tx39.c +++ b/arch/mips/mm/c-tx39.c @@ -69,7 +69,7 @@ static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size) /* TX39H2,TX39H3 */ static inline void tx39_blast_dcache_page(unsigned long addr) { - if (current_cpu_data.cputype != CPU_TX3912) + if (current_cpu_type() != CPU_TX3912) blast_dcache16_page(addr); } @@ -307,7 +307,7 @@ static __init void tx39_probe_cache(void) TX39_CONF_DCS_SHIFT)); current_cpu_data.icache.linesz = 16; - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_TX3912: current_cpu_data.icache.ways = 1; current_cpu_data.dcache.ways = 1; @@ -341,7 +341,7 @@ void __init tx39_cache_init(void) tx39_probe_cache(); - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_TX3912: /* TX39/H core (writethru direct-map cache) */ flush_cache_all = tx39h_flush_icache_all; diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index f60b3dc..98b5e5b 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -35,8 +35,8 @@ static inline unsigned long dma_addr_to_virt(dma_addr_t dma_addr) static inline int cpu_is_noncoherent_r10000(struct device *dev) { return !plat_device_is_coherent(dev) && - (current_cpu_data.cputype == CPU_R10000 || - current_cpu_data.cputype == CPU_R12000); + (current_cpu_type() == CPU_R10000 || + current_cpu_type() == CPU_R12000); } void *dma_alloc_noncoherent(struct device *dev, size_t size, diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c index c029454..4f770ac 100644 --- a/arch/mips/mm/pg-r4k.c +++ b/arch/mips/mm/pg-r4k.c @@ -354,7 +354,7 @@ void __init build_clear_page(void) store_offset = 0; if (cpu_has_prefetch) { - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_TX49XX: /* TX49 supports only Pref_Load */ pref_offset_clear = 0; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 7325074..c3da4fe 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -827,7 +827,7 @@ static __initdata u32 final_handler[64]; */ static __init void __maybe_unused build_tlb_probe_entry(u32 **p) { - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { /* Found by experiment: R4600 v2.0 needs this, too. */ case CPU_R4600: case CPU_R5000: @@ -860,7 +860,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, case tlb_indexed: tlbw = i_tlbwi; break; } - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_R4000PC: case CPU_R4000SC: case CPU_R4000MC: @@ -1158,7 +1158,7 @@ static __init void build_adjust_context(u32 **p, unsigned int ctx) unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_VR41XX: case CPU_VR4111: case CPU_VR4121: @@ -1188,7 +1188,7 @@ static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) * in a different cacheline or a load instruction, probably any * memory reference, is between them. */ - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_NEVADA: i_LW(p, ptr, 0, ptr); GET_CONTEXT(p, tmp); /* get context reg */ @@ -1872,7 +1872,7 @@ void __init build_tlb_refill_handler(void) */ static int run_once = 0; - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_R2000: case CPU_R3000: case CPU_R3000A: diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index 4e0a90b..aa52aa1 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -74,7 +74,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) struct op_mips_model *lmodel = NULL; int res; - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_5KC: case CPU_20KC: case CPU_24K: diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 1ea5c9c..6383000 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -222,7 +222,7 @@ static inline int n_counters(void) { int counters; - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_R10000: counters = 2; break; @@ -274,7 +274,7 @@ static int __init mipsxx_init(void) #endif op_model_mipsxx_ops.num_counters = counters; - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_20KC: op_model_mipsxx_ops.cpu_type = "mips/20K"; break; diff --git a/arch/mips/pci/pci-vr41xx.c b/arch/mips/pci/pci-vr41xx.c index 9885fa4..240df9e 100644 --- a/arch/mips/pci/pci-vr41xx.c +++ b/arch/mips/pci/pci-vr41xx.c @@ -228,7 +228,7 @@ static int __init vr41xx_pciu_init(void) else pciu_write(PCIEXACCREG, 0); - if (current_cpu_data.cputype == CPU_VR4122) + if (current_cpu_type() == CPU_VR4122) pciu_write(PCITRDYVREG, TRDYV(setup->wait_time_limit_from_irdy_to_trdy)); pciu_write(LATTIMEREG, MLTIM(setup->master_latency_timer)); diff --git a/arch/mips/vr41xx/common/bcu.c b/arch/mips/vr41xx/common/bcu.c index ff272b2..d77c330 100644 --- a/arch/mips/vr41xx/common/bcu.c +++ b/arch/mips/vr41xx/common/bcu.c @@ -70,7 +70,7 @@ EXPORT_SYMBOL_GPL(vr41xx_get_tclock_frequency); static inline uint16_t read_clkspeed(void) { - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_VR4111: case CPU_VR4121: return readw(CLKSPEEDREG_TYPE1); case CPU_VR4122: @@ -88,7 +88,7 @@ static inline unsigned long calculate_pclock(uint16_t clkspeed) { unsigned long pclock = 0; - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_VR4111: case CPU_VR4121: pclock = 18432000 * 64; @@ -138,7 +138,7 @@ static inline unsigned long calculate_vtclock(uint16_t clkspeed, unsigned long p { unsigned long vtclock = 0; - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_VR4111: /* The NEC VR4111 doesn't have the VTClock. */ break; @@ -180,7 +180,7 @@ static inline unsigned long calculate_tclock(uint16_t clkspeed, unsigned long pc { unsigned long tclock = 0; - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_VR4111: if (!(clkspeed & DIV2B)) tclock = pclock / 2; diff --git a/arch/mips/vr41xx/common/cmu.c b/arch/mips/vr41xx/common/cmu.c index 657c513..ad0e8e3 100644 --- a/arch/mips/vr41xx/common/cmu.c +++ b/arch/mips/vr41xx/common/cmu.c @@ -95,8 +95,8 @@ void vr41xx_supply_clock(vr41xx_clock_t clock) cmuclkmsk |= MSKFIR | MSKFFIR; break; case DSIU_CLOCK: - if (current_cpu_data.cputype == CPU_VR4111 || - current_cpu_data.cputype == CPU_VR4121) + if (current_cpu_type() == CPU_VR4111 || + current_cpu_type() == CPU_VR4121) cmuclkmsk |= MSKDSIU; else cmuclkmsk |= MSKSIU | MSKDSIU; @@ -146,8 +146,8 @@ void vr41xx_mask_clock(vr41xx_clock_t clock) cmuclkmsk &= ~MSKPIU; break; case SIU_CLOCK: - if (current_cpu_data.cputype == CPU_VR4111 || - current_cpu_data.cputype == CPU_VR4121) { + if (current_cpu_type() == CPU_VR4111 || + current_cpu_type() == CPU_VR4121) { cmuclkmsk &= ~(MSKSIU | MSKSSIU); } else { if (cmuclkmsk & MSKDSIU) @@ -166,8 +166,8 @@ void vr41xx_mask_clock(vr41xx_clock_t clock) cmuclkmsk &= ~(MSKFIR | MSKFFIR); break; case DSIU_CLOCK: - if (current_cpu_data.cputype == CPU_VR4111 || - current_cpu_data.cputype == CPU_VR4121) { + if (current_cpu_type() == CPU_VR4111 || + current_cpu_type() == CPU_VR4121) { cmuclkmsk &= ~MSKDSIU; } else { if (cmuclkmsk & MSKSSIU) @@ -216,7 +216,7 @@ static int __init vr41xx_cmu_init(void) { unsigned long start, size; - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_VR4111: case CPU_VR4121: start = CMU_TYPE1_BASE; @@ -246,7 +246,7 @@ static int __init vr41xx_cmu_init(void) } cmuclkmsk = cmu_read(CMUCLKMSK); - if (current_cpu_data.cputype == CPU_VR4133) + if (current_cpu_type() == CPU_VR4133) cmuclkmsk2 = cmu_read(CMUCLKMSK2); spin_lock_init(&cmu_lock); diff --git a/arch/mips/vr41xx/common/giu.c b/arch/mips/vr41xx/common/giu.c index d21f6f2..2b272f1 100644 --- a/arch/mips/vr41xx/common/giu.c +++ b/arch/mips/vr41xx/common/giu.c @@ -81,7 +81,7 @@ static int __init vr41xx_giu_add(void) if (!pdev) return -ENOMEM; - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_VR4111: case CPU_VR4121: pdev->id = GPIO_50PINS_PULLUPDOWN; diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c index adabc6b..1899601 100644 --- a/arch/mips/vr41xx/common/icu.c +++ b/arch/mips/vr41xx/common/icu.c @@ -157,8 +157,8 @@ void vr41xx_enable_piuint(uint16_t mask) struct irq_desc *desc = irq_desc + PIU_IRQ; unsigned long flags; - if (current_cpu_data.cputype == CPU_VR4111 || - current_cpu_data.cputype == CPU_VR4121) { + if (current_cpu_type() == CPU_VR4111 || + current_cpu_type() == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); icu1_set(MPIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); @@ -172,8 +172,8 @@ void vr41xx_disable_piuint(uint16_t mask) struct irq_desc *desc = irq_desc + PIU_IRQ; unsigned long flags; - if (current_cpu_data.cputype == CPU_VR4111 || - current_cpu_data.cputype == CPU_VR4121) { + if (current_cpu_type() == CPU_VR4111 || + current_cpu_type() == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); icu1_clear(MPIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); @@ -187,8 +187,8 @@ void vr41xx_enable_aiuint(uint16_t mask) struct irq_desc *desc = irq_desc + AIU_IRQ; unsigned long flags; - if (current_cpu_data.cputype == CPU_VR4111 || - current_cpu_data.cputype == CPU_VR4121) { + if (current_cpu_type() == CPU_VR4111 || + current_cpu_type() == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); icu1_set(MAIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); @@ -202,8 +202,8 @@ void vr41xx_disable_aiuint(uint16_t mask) struct irq_desc *desc = irq_desc + AIU_IRQ; unsigned long flags; - if (current_cpu_data.cputype == CPU_VR4111 || - current_cpu_data.cputype == CPU_VR4121) { + if (current_cpu_type() == CPU_VR4111 || + current_cpu_type() == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); icu1_clear(MAIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); @@ -217,8 +217,8 @@ void vr41xx_enable_kiuint(uint16_t mask) struct irq_desc *desc = irq_desc + KIU_IRQ; unsigned long flags; - if (current_cpu_data.cputype == CPU_VR4111 || - current_cpu_data.cputype == CPU_VR4121) { + if (current_cpu_type() == CPU_VR4111 || + current_cpu_type() == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); icu1_set(MKIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); @@ -232,8 +232,8 @@ void vr41xx_disable_kiuint(uint16_t mask) struct irq_desc *desc = irq_desc + KIU_IRQ; unsigned long flags; - if (current_cpu_data.cputype == CPU_VR4111 || - current_cpu_data.cputype == CPU_VR4121) { + if (current_cpu_type() == CPU_VR4111 || + current_cpu_type() == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); icu1_clear(MKIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); @@ -319,9 +319,9 @@ void vr41xx_enable_pciint(void) struct irq_desc *desc = irq_desc + PCI_IRQ; unsigned long flags; - if (current_cpu_data.cputype == CPU_VR4122 || - current_cpu_data.cputype == CPU_VR4131 || - current_cpu_data.cputype == CPU_VR4133) { + if (current_cpu_type() == CPU_VR4122 || + current_cpu_type() == CPU_VR4131 || + current_cpu_type() == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); icu2_write(MPCIINTREG, PCIINT0); spin_unlock_irqrestore(&desc->lock, flags); @@ -335,9 +335,9 @@ void vr41xx_disable_pciint(void) struct irq_desc *desc = irq_desc + PCI_IRQ; unsigned long flags; - if (current_cpu_data.cputype == CPU_VR4122 || - current_cpu_data.cputype == CPU_VR4131 || - current_cpu_data.cputype == CPU_VR4133) { + if (current_cpu_type() == CPU_VR4122 || + current_cpu_type() == CPU_VR4131 || + current_cpu_type() == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); icu2_write(MPCIINTREG, 0); spin_unlock_irqrestore(&desc->lock, flags); @@ -351,9 +351,9 @@ void vr41xx_enable_scuint(void) struct irq_desc *desc = irq_desc + SCU_IRQ; unsigned long flags; - if (current_cpu_data.cputype == CPU_VR4122 || - current_cpu_data.cputype == CPU_VR4131 || - current_cpu_data.cputype == CPU_VR4133) { + if (current_cpu_type() == CPU_VR4122 || + current_cpu_type() == CPU_VR4131 || + current_cpu_type() == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); icu2_write(MSCUINTREG, SCUINT0); spin_unlock_irqrestore(&desc->lock, flags); @@ -367,9 +367,9 @@ void vr41xx_disable_scuint(void) struct irq_desc *desc = irq_desc + SCU_IRQ; unsigned long flags; - if (current_cpu_data.cputype == CPU_VR4122 || - current_cpu_data.cputype == CPU_VR4131 || - current_cpu_data.cputype == CPU_VR4133) { + if (current_cpu_type() == CPU_VR4122 || + current_cpu_type() == CPU_VR4131 || + current_cpu_type() == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); icu2_write(MSCUINTREG, 0); spin_unlock_irqrestore(&desc->lock, flags); @@ -383,9 +383,9 @@ void vr41xx_enable_csiint(uint16_t mask) struct irq_desc *desc = irq_desc + CSI_IRQ; unsigned long flags; - if (current_cpu_data.cputype == CPU_VR4122 || - current_cpu_data.cputype == CPU_VR4131 || - current_cpu_data.cputype == CPU_VR4133) { + if (current_cpu_type() == CPU_VR4122 || + current_cpu_type() == CPU_VR4131 || + current_cpu_type() == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); icu2_set(MCSIINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); @@ -399,9 +399,9 @@ void vr41xx_disable_csiint(uint16_t mask) struct irq_desc *desc = irq_desc + CSI_IRQ; unsigned long flags; - if (current_cpu_data.cputype == CPU_VR4122 || - current_cpu_data.cputype == CPU_VR4131 || - current_cpu_data.cputype == CPU_VR4133) { + if (current_cpu_type() == CPU_VR4122 || + current_cpu_type() == CPU_VR4131 || + current_cpu_type() == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); icu2_clear(MCSIINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); @@ -415,9 +415,9 @@ void vr41xx_enable_bcuint(void) struct irq_desc *desc = irq_desc + BCU_IRQ; unsigned long flags; - if (current_cpu_data.cputype == CPU_VR4122 || - current_cpu_data.cputype == CPU_VR4131 || - current_cpu_data.cputype == CPU_VR4133) { + if (current_cpu_type() == CPU_VR4122 || + current_cpu_type() == CPU_VR4131 || + current_cpu_type() == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); icu2_write(MBCUINTREG, BCUINTR); spin_unlock_irqrestore(&desc->lock, flags); @@ -431,9 +431,9 @@ void vr41xx_disable_bcuint(void) struct irq_desc *desc = irq_desc + BCU_IRQ; unsigned long flags; - if (current_cpu_data.cputype == CPU_VR4122 || - current_cpu_data.cputype == CPU_VR4131 || - current_cpu_data.cputype == CPU_VR4133) { + if (current_cpu_type() == CPU_VR4122 || + current_cpu_type() == CPU_VR4131 || + current_cpu_type() == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); icu2_write(MBCUINTREG, 0); spin_unlock_irqrestore(&desc->lock, flags); @@ -608,7 +608,7 @@ int vr41xx_set_intassign(unsigned int irq, unsigned char intassign) { int retval = -EINVAL; - if (current_cpu_data.cputype != CPU_VR4133) + if (current_cpu_type() != CPU_VR4133) return -EINVAL; if (intassign > INTASSIGN_MAX) @@ -665,7 +665,7 @@ static int __init vr41xx_icu_init(void) unsigned long icu1_start, icu2_start; int i; - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_VR4111: case CPU_VR4121: icu1_start = ICU1_TYPE1_BASE; diff --git a/arch/mips/vr41xx/common/pmu.c b/arch/mips/vr41xx/common/pmu.c index ad5b6db..028aaf7 100644 --- a/arch/mips/vr41xx/common/pmu.c +++ b/arch/mips/vr41xx/common/pmu.c @@ -62,7 +62,7 @@ static inline void software_reset(void) { uint16_t pmucnt2; - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_VR4122: case CPU_VR4131: case CPU_VR4133: @@ -98,7 +98,7 @@ static int __init vr41xx_pmu_init(void) { unsigned long start, size; - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_VR4111: case CPU_VR4121: start = PMU_TYPE1_BASE; diff --git a/arch/mips/vr41xx/common/rtc.c b/arch/mips/vr41xx/common/rtc.c index cce605b..9f26c14 100644 --- a/arch/mips/vr41xx/common/rtc.c +++ b/arch/mips/vr41xx/common/rtc.c @@ -82,7 +82,7 @@ static int __init vr41xx_rtc_add(void) if (!pdev) return -ENOMEM; - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_VR4111: case CPU_VR4121: res = rtc_type1_resource; diff --git a/arch/mips/vr41xx/common/siu.c b/arch/mips/vr41xx/common/siu.c index a1e7741..b735f45 100644 --- a/arch/mips/vr41xx/common/siu.c +++ b/arch/mips/vr41xx/common/siu.c @@ -83,7 +83,7 @@ static int __init vr41xx_siu_add(void) if (!pdev) return -ENOMEM; - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_VR4111: case CPU_VR4121: pdev->dev.platform_data = siu_type1_ports; diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index 81f19ae..f6bd308 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -9,11 +9,14 @@ #ifndef __ASM_CPU_FEATURES_H #define __ASM_CPU_FEATURES_H - #include #include #include +#ifndef current_cpu_type +#define current_cpu_type() current_cpu_data.cputype +#endif + /* * SMP assumption: Options of CPU 0 are a superset of all processors. * This is true for all known MIPS systems. -- cgit v0.10.2 From 49a89efbbbcc178a39555c43bd59a7593c429664 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:15 +0100 Subject: [MIPS] Fix "no space between function name and open parenthesis" warnings. Signed-off-by: Ralf Baechle diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c index 626de44..d15b047 100644 --- a/arch/mips/au1000/common/dbdma.c +++ b/arch/mips/au1000/common/dbdma.c @@ -184,7 +184,7 @@ static dbdev_tab_t dbdev_tab[] = { static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; static dbdev_tab_t * -find_dbdev_id (u32 id) +find_dbdev_id(u32 id) { int i; dbdev_tab_t *p; diff --git a/arch/mips/au1000/common/reset.c b/arch/mips/au1000/common/reset.c index de5447e..b8638d29 100644 --- a/arch/mips/au1000/common/reset.c +++ b/arch/mips/au1000/common/reset.c @@ -42,7 +42,7 @@ extern void (*flush_cache_all)(void); void au1000_restart(char *command) { /* Set all integrated peripherals to disabled states */ - extern void board_reset (void); + extern void board_reset(void); u32 prid = read_c0_prid(); printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n"); diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index 726c340..2556399 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -200,7 +200,7 @@ unsigned long cal_r4koff(void) while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); - au_writel (0, SYS_TOYWRITE); + au_writel(0, SYS_TOYWRITE); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * diff --git a/arch/mips/au1000/db1x00/board_setup.c b/arch/mips/au1000/db1x00/board_setup.c index 8b08edb..99eafea 100644 --- a/arch/mips/au1000/db1x00/board_setup.c +++ b/arch/mips/au1000/db1x00/board_setup.c @@ -46,7 +46,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; -void board_reset (void) +void board_reset(void) { /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ bcsr->swreset = 0x0000; diff --git a/arch/mips/au1000/db1x00/init.c b/arch/mips/au1000/db1x00/init.c index e6bdd07..4d7bcfc 100644 --- a/arch/mips/au1000/db1x00/init.c +++ b/arch/mips/au1000/db1x00/init.c @@ -60,11 +60,11 @@ void __init prom_init(void) prom_envp = (char **) fw_arg2; /* Set the platform # */ -#if defined (CONFIG_MIPS_DB1550) +#if defined(CONFIG_MIPS_DB1550) mips_machtype = MACH_DB1550; -#elif defined (CONFIG_MIPS_DB1500) +#elif defined(CONFIG_MIPS_DB1500) mips_machtype = MACH_DB1500; -#elif defined (CONFIG_MIPS_DB1100) +#elif defined(CONFIG_MIPS_DB1100) mips_machtype = MACH_DB1100; #else mips_machtype = MACH_DB1000; diff --git a/arch/mips/au1000/mtx-1/board_setup.c b/arch/mips/au1000/mtx-1/board_setup.c index 2c460c1..abfc4bc 100644 --- a/arch/mips/au1000/mtx-1/board_setup.c +++ b/arch/mips/au1000/mtx-1/board_setup.c @@ -46,7 +46,7 @@ extern int (*board_pci_idsel)(unsigned int devsel, int assert); int mtx1_pci_idsel(unsigned int devsel, int assert); -void board_reset (void) +void board_reset(void) { /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ au_writel(0x00000000, 0xAE00001C); diff --git a/arch/mips/au1000/pb1000/board_setup.c b/arch/mips/au1000/pb1000/board_setup.c index 0aed891..5198c4f 100644 --- a/arch/mips/au1000/pb1000/board_setup.c +++ b/arch/mips/au1000/pb1000/board_setup.c @@ -39,7 +39,7 @@ #include #include -void board_reset (void) +void board_reset(void) { } diff --git a/arch/mips/au1000/pb1100/board_setup.c b/arch/mips/au1000/pb1100/board_setup.c index 259ca05..42874a6 100644 --- a/arch/mips/au1000/pb1100/board_setup.c +++ b/arch/mips/au1000/pb1100/board_setup.c @@ -39,7 +39,7 @@ #include #include -void board_reset (void) +void board_reset(void) { /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ au_writel(0x00000000, 0xAE00001C); diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/au1000/pb1200/board_setup.c index eea2092..2122515 100644 --- a/arch/mips/au1000/pb1200/board_setup.c +++ b/arch/mips/au1000/pb1200/board_setup.c @@ -57,7 +57,7 @@ extern void _board_init_irq(void); extern void (*board_init_irq)(void); -void board_reset (void) +void board_reset(void) { bcsr->resets = 0; bcsr->system = 0; @@ -148,7 +148,7 @@ void __init board_setup(void) } int -board_au1200fb_panel (void) +board_au1200fb_panel(void) { BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; int p; @@ -160,7 +160,7 @@ board_au1200fb_panel (void) } int -board_au1200fb_panel_init (void) +board_au1200fb_panel_init(void) { /* Apply power */ BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; @@ -170,7 +170,7 @@ board_au1200fb_panel_init (void) } int -board_au1200fb_panel_shutdown (void) +board_au1200fb_panel_shutdown(void) { /* Remove power */ BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; diff --git a/arch/mips/au1000/pb1500/board_setup.c b/arch/mips/au1000/pb1500/board_setup.c index a2d850d..5446836 100644 --- a/arch/mips/au1000/pb1500/board_setup.c +++ b/arch/mips/au1000/pb1500/board_setup.c @@ -39,7 +39,7 @@ #include #include -void board_reset (void) +void board_reset(void) { /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ au_writel(0x00000000, 0xAE00001C); diff --git a/arch/mips/au1000/pb1550/board_setup.c b/arch/mips/au1000/pb1550/board_setup.c index 05fd27d..e3cfb0d 100644 --- a/arch/mips/au1000/pb1550/board_setup.c +++ b/arch/mips/au1000/pb1550/board_setup.c @@ -44,7 +44,7 @@ #include #include -void board_reset (void) +void board_reset(void) { /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ au_writew(au_readw(0xAF00001C) & ~(1<<15), 0xAF00001C); diff --git a/arch/mips/au1000/xxs1500/board_setup.c b/arch/mips/au1000/xxs1500/board_setup.c index ae3d6b1..a9237f4 100644 --- a/arch/mips/au1000/xxs1500/board_setup.c +++ b/arch/mips/au1000/xxs1500/board_setup.c @@ -39,7 +39,7 @@ #include #include -void board_reset (void) +void board_reset(void) { /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ au_writel(0x00000000, 0xAE00001C); diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c index 68be19d..404ca92 100644 --- a/arch/mips/basler/excite/excite_setup.c +++ b/arch/mips/basler/excite/excite_setup.c @@ -216,7 +216,7 @@ static int __init excite_platform_init(void) titan_writel(0x80021dff, GXCFG); /* XDMA reset */ titan_writel(0x00000000, CPXCISRA); titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */ -#if defined (CONFIG_HIGHMEM) +#if defined(CONFIG_HIGHMEM) # error change for HIGHMEM support! #else titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */ @@ -262,12 +262,12 @@ void __init plat_mem_setup(void) add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); /* Set up the peripheral address map */ - *(boot_ocd_base + (LKB9 / sizeof (u32))) = 0; - *(boot_ocd_base + (LKB10 / sizeof (u32))) = 0; - *(boot_ocd_base + (LKB11 / sizeof (u32))) = 0; - *(boot_ocd_base + (LKB12 / sizeof (u32))) = 0; + *(boot_ocd_base + (LKB9 / sizeof(u32))) = 0; + *(boot_ocd_base + (LKB10 / sizeof(u32))) = 0; + *(boot_ocd_base + (LKB11 / sizeof(u32))) = 0; + *(boot_ocd_base + (LKB12 / sizeof(u32))) = 0; wmb(); - *(boot_ocd_base + (LKB0 / sizeof (u32))) = EXCITE_PHYS_OCD >> 4; + *(boot_ocd_base + (LKB0 / sizeof(u32))) = EXCITE_PHYS_OCD >> 4; wmb(); ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5); diff --git a/arch/mips/boot/addinitrd.c b/arch/mips/boot/addinitrd.c index 8b30333..193e4be 100644 --- a/arch/mips/boot/addinitrd.c +++ b/arch/mips/boot/addinitrd.c @@ -32,13 +32,13 @@ #define SWAB(a) (swab ? swab32(a) : (a)) -void die (char *s) +void die(char *s) { - perror (s); - exit (1); + perror(s); + exit(1); } -int main (int argc, char *argv[]) +int main(int argc, char *argv[]) { int fd_vmlinux,fd_initrd,fd_outfile; FILHDR efile; @@ -52,18 +52,18 @@ int main (int argc, char *argv[]) int swab = 0; if (argc != 4) { - printf ("Usage: %s \n",argv[0]); - exit (1); + printf("Usage: %s \n",argv[0]); + exit(1); } if ((fd_vmlinux = open (argv[1],O_RDONLY)) < 0) - die ("open vmlinux"); + die("open vmlinux"); if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile) - die ("read file header"); + die("read file header"); if (read (fd_vmlinux, &eaout, sizeof eaout) != sizeof eaout) - die ("read aout header"); + die("read aout header"); if (read (fd_vmlinux, esecs, sizeof esecs) != sizeof esecs) - die ("read section headers"); + die("read section headers"); /* * check whether the file is good for us */ @@ -82,13 +82,13 @@ int main (int argc, char *argv[]) /* make sure we have an empty data segment for the initrd */ if (eaout.dsize || esecs[1].s_size) { - fprintf (stderr, "Data segment not empty. Giving up!\n"); - exit (1); + fprintf(stderr, "Data segment not empty. Giving up!\n"); + exit(1); } if ((fd_initrd = open (argv[2], O_RDONLY)) < 0) - die ("open initrd"); + die("open initrd"); if (fstat (fd_initrd, &st) < 0) - die ("fstat initrd"); + die("fstat initrd"); loadaddr = ((SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size) + MIPS_PAGE_SIZE-1) & ~MIPS_PAGE_MASK) - 8; if (loadaddr < (SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size))) @@ -99,33 +99,33 @@ int main (int argc, char *argv[]) eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr); if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC,0666)) < 0) - die ("open outfile"); + die("open outfile"); if (write (fd_outfile, &efile, sizeof efile) != sizeof efile) - die ("write file header"); + die("write file header"); if (write (fd_outfile, &eaout, sizeof eaout) != sizeof eaout) - die ("write aout header"); + die("write aout header"); if (write (fd_outfile, esecs, sizeof esecs) != sizeof esecs) - die ("write section headers"); + die("write section headers"); /* skip padding */ if(lseek(fd_vmlinux, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1) - die ("lseek vmlinux"); + die("lseek vmlinux"); if(lseek(fd_outfile, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1) - die ("lseek outfile"); + die("lseek outfile"); /* copy text segment */ cnt = SWAB(eaout.tsize); while (cnt) { if ((i = read (fd_vmlinux, buf, sizeof buf)) <= 0) - die ("read vmlinux"); + die("read vmlinux"); if (write (fd_outfile, buf, i) != i) - die ("write vmlinux"); + die("write vmlinux"); cnt -= i; } if (write (fd_outfile, initrd_header, sizeof initrd_header) != sizeof initrd_header) - die ("write initrd header"); + die("write initrd header"); while ((i = read (fd_initrd, buf, sizeof buf)) > 0) if (write (fd_outfile, buf, i) != i) - die ("write initrd"); - close (fd_vmlinux); - close (fd_initrd); + die("write initrd"); + close(fd_vmlinux); + close(fd_initrd); return 0; } diff --git a/arch/mips/fw/arc/memory.c b/arch/mips/fw/arc/memory.c index 83d1579..8b8eea2 100644 --- a/arch/mips/fw/arc/memory.c +++ b/arch/mips/fw/arc/memory.c @@ -63,7 +63,7 @@ static char *arc_mtypes[8] = { : arc_mtypes[a.arc] #endif -static inline int memtype_classify_arcs (union linux_memtypes type) +static inline int memtype_classify_arcs(union linux_memtypes type) { switch (type.arcs) { case arcs_fcontig: @@ -83,7 +83,7 @@ static inline int memtype_classify_arcs (union linux_memtypes type) while(1); /* Nuke warning. */ } -static inline int memtype_classify_arc (union linux_memtypes type) +static inline int memtype_classify_arc(union linux_memtypes type) { switch (type.arc) { case arc_free: @@ -103,7 +103,7 @@ static inline int memtype_classify_arc (union linux_memtypes type) while(1); /* Nuke warning. */ } -static int __init prom_memtype_classify (union linux_memtypes type) +static int __init prom_memtype_classify(union linux_memtypes type) { if (prom_flags & PROM_FLAG_ARCS) /* SGI is ``different'' ... */ return memtype_classify_arcs(type); diff --git a/arch/mips/jazz/reset.c b/arch/mips/jazz/reset.c index d8ade85..dd889fe 100644 --- a/arch/mips/jazz/reset.c +++ b/arch/mips/jazz/reset.c @@ -49,8 +49,8 @@ void jazz_machine_restart(char *command) { while(1) { kb_wait(); - jazz_write_command (0xd1); + jazz_write_command(0xd1); kb_wait(); - jazz_write_output (0x00); + jazz_write_output(0x00); } } diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c index 2a7ec08..cfc7dce 100644 --- a/arch/mips/jazz/setup.c +++ b/arch/mips/jazz/setup.c @@ -74,11 +74,11 @@ void __init plat_mem_setup(void) int i; /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */ - add_wired_entry (0x02000017, 0x03c00017, 0xe0000000, PM_64K); + add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K); /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */ - add_wired_entry (0x02400017, 0x02440017, 0xe2000000, PM_16M); + add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M); /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */ - add_wired_entry (0x01800017, 0x01000017, 0xe4000000, PM_4M); + add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M); set_io_port_base(JAZZ_PORT_BASE); #ifdef CONFIG_EISA diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c index 6648fde..af78456 100644 --- a/arch/mips/kernel/cpu-bugs64.c +++ b/arch/mips/kernel/cpu-bugs64.c @@ -29,7 +29,7 @@ static inline void align_mod(const int align, const int mod) ".endr\n\t" ".set pop" : - : GCC_IMM_ASM (align), GCC_IMM_ASM (mod)); + : GCC_IMM_ASM(align), GCC_IMM_ASM(mod)); } static inline void mult_sh_align_mod(long *v1, long *v2, long *w, diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c index cb5623a..989d06c 100644 --- a/arch/mips/kernel/gdb-stub.c +++ b/arch/mips/kernel/gdb-stub.c @@ -733,7 +733,7 @@ static int kgdb_smp_call_kgdb_wait(void) * returns 1 if you should skip the instruction at the trap address, 0 * otherwise. */ -void handle_exception (struct gdb_regs *regs) +void handle_exception(struct gdb_regs *regs) { int trap; /* Trap type */ int sigval; @@ -917,7 +917,7 @@ void handle_exception (struct gdb_regs *regs) && hexToInt(&ptr, &length)) { if (mem2hex((char *)addr, output_buffer, length, 1)) break; - strcpy (output_buffer, "E03"); + strcpy(output_buffer, "E03"); } else strcpy(output_buffer,"E01"); break; diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index b6e5bb4..a860b21 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c @@ -329,7 +329,7 @@ static struct resource pic2_io_resource = { * driver compatibility reasons interrupts 0 - 15 to be the i8259 * interrupts even if the hardware uses a different interrupt numbering. */ -void __init init_i8259_irqs (void) +void __init init_i8259_irqs(void) { int i; diff --git a/arch/mips/kernel/irixelf.c b/arch/mips/kernel/irixelf.c index 403d96f..e3b4b54 100644 --- a/arch/mips/kernel/irixelf.c +++ b/arch/mips/kernel/irixelf.c @@ -203,8 +203,8 @@ static unsigned long * create_irix_tables(char * p, int argc, int envc, * Put the ELF interpreter info on the stack */ #define NEW_AUX_ENT(nr, id, val) \ - __put_user ((id), sp+(nr*2)); \ - __put_user ((val), sp+(nr*2+1)); \ + __put_user((id), sp+(nr*2)); \ + __put_user((val), sp+(nr*2+1)); \ sp -= 2; NEW_AUX_ENT(0, AT_NULL, 0); @@ -212,17 +212,17 @@ static unsigned long * create_irix_tables(char * p, int argc, int envc, if (exec) { sp -= 11*2; - NEW_AUX_ENT (0, AT_PHDR, load_addr + exec->e_phoff); - NEW_AUX_ENT (1, AT_PHENT, sizeof (struct elf_phdr)); - NEW_AUX_ENT (2, AT_PHNUM, exec->e_phnum); - NEW_AUX_ENT (3, AT_PAGESZ, ELF_EXEC_PAGESIZE); - NEW_AUX_ENT (4, AT_BASE, interp_load_addr); - NEW_AUX_ENT (5, AT_FLAGS, 0); - NEW_AUX_ENT (6, AT_ENTRY, (elf_addr_t) exec->e_entry); - NEW_AUX_ENT (7, AT_UID, (elf_addr_t) current->uid); - NEW_AUX_ENT (8, AT_EUID, (elf_addr_t) current->euid); - NEW_AUX_ENT (9, AT_GID, (elf_addr_t) current->gid); - NEW_AUX_ENT (10, AT_EGID, (elf_addr_t) current->egid); + NEW_AUX_ENT(0, AT_PHDR, load_addr + exec->e_phoff); + NEW_AUX_ENT(1, AT_PHENT, sizeof(struct elf_phdr)); + NEW_AUX_ENT(2, AT_PHNUM, exec->e_phnum); + NEW_AUX_ENT(3, AT_PAGESZ, ELF_EXEC_PAGESIZE); + NEW_AUX_ENT(4, AT_BASE, interp_load_addr); + NEW_AUX_ENT(5, AT_FLAGS, 0); + NEW_AUX_ENT(6, AT_ENTRY, (elf_addr_t) exec->e_entry); + NEW_AUX_ENT(7, AT_UID, (elf_addr_t) current->uid); + NEW_AUX_ENT(8, AT_EUID, (elf_addr_t) current->euid); + NEW_AUX_ENT(9, AT_GID, (elf_addr_t) current->gid); + NEW_AUX_ENT(10, AT_EGID, (elf_addr_t) current->egid); } #undef NEW_AUX_ENT @@ -581,7 +581,7 @@ static void irix_map_prda_page(void) struct prda *pp; down_write(¤t->mm->mmap_sem); - v = do_brk (PRDA_ADDRESS, PAGE_SIZE); + v = do_brk(PRDA_ADDRESS, PAGE_SIZE); up_write(¤t->mm->mmap_sem); if (v < 0) @@ -815,7 +815,7 @@ out_free_interp: kfree(elf_interpreter); out_free_file: out_free_ph: - kfree (elf_phdata); + kfree(elf_phdata); goto out; } @@ -1232,7 +1232,7 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file) strlcpy(psinfo.pr_fname, current->comm, sizeof(psinfo.pr_fname)); /* Try to dump the FPU. */ - prstatus.pr_fpvalid = dump_fpu (regs, &fpu); + prstatus.pr_fpvalid = dump_fpu(regs, &fpu); if (!prstatus.pr_fpvalid) { numnote--; } else { diff --git a/arch/mips/kernel/irixinv.c b/arch/mips/kernel/irixinv.c index de8584f6..cf2dcd3 100644 --- a/arch/mips/kernel/irixinv.c +++ b/arch/mips/kernel/irixinv.c @@ -14,7 +14,7 @@ int inventory_items = 0; static inventory_t inventory [MAX_INVENTORY]; -void add_to_inventory (int class, int type, int controller, int unit, int state) +void add_to_inventory(int class, int type, int controller, int unit, int state) { inventory_t *ni = &inventory [inventory_items]; @@ -30,7 +30,7 @@ void add_to_inventory (int class, int type, int controller, int unit, int state) inventory_items++; } -int dump_inventory_to_user (void __user *userbuf, int size) +int dump_inventory_to_user(void __user *userbuf, int size) { inventory_t *inv = &inventory [0]; inventory_t __user *user = userbuf; @@ -45,7 +45,7 @@ int dump_inventory_to_user (void __user *userbuf, int size) return -EFAULT; user++; } - return inventory_items * sizeof (inventory_t); + return inventory_items * sizeof(inventory_t); } int __init init_inventory(void) @@ -55,24 +55,24 @@ int __init init_inventory(void) * most likely this will not let just anyone run the X server * until we put the right values all over the place */ - add_to_inventory (10, 3, 0, 0, 16400); - add_to_inventory (1, 1, 150, -1, 12); - add_to_inventory (1, 3, 0, 0, 8976); - add_to_inventory (1, 2, 0, 0, 8976); - add_to_inventory (4, 8, 0, 0, 2); - add_to_inventory (5, 5, 0, 0, 1); - add_to_inventory (3, 3, 0, 0, 32768); - add_to_inventory (3, 4, 0, 0, 32768); - add_to_inventory (3, 8, 0, 0, 524288); - add_to_inventory (3, 9, 0, 0, 64); - add_to_inventory (3, 1, 0, 0, 67108864); - add_to_inventory (12, 3, 0, 0, 16); - add_to_inventory (8, 7, 17, 0, 16777472); - add_to_inventory (8, 0, 0, 0, 1); - add_to_inventory (2, 1, 0, 13, 2); - add_to_inventory (2, 2, 0, 2, 0); - add_to_inventory (2, 2, 0, 1, 0); - add_to_inventory (7, 14, 0, 0, 6); + add_to_inventory(10, 3, 0, 0, 16400); + add_to_inventory(1, 1, 150, -1, 12); + add_to_inventory(1, 3, 0, 0, 8976); + add_to_inventory(1, 2, 0, 0, 8976); + add_to_inventory(4, 8, 0, 0, 2); + add_to_inventory(5, 5, 0, 0, 1); + add_to_inventory(3, 3, 0, 0, 32768); + add_to_inventory(3, 4, 0, 0, 32768); + add_to_inventory(3, 8, 0, 0, 524288); + add_to_inventory(3, 9, 0, 0, 64); + add_to_inventory(3, 1, 0, 0, 67108864); + add_to_inventory(12, 3, 0, 0, 16); + add_to_inventory(8, 7, 17, 0, 16777472); + add_to_inventory(8, 0, 0, 0, 1); + add_to_inventory(2, 1, 0, 13, 2); + add_to_inventory(2, 2, 0, 2, 0); + add_to_inventory(2, 2, 0, 1, 0); + add_to_inventory(7, 14, 0, 0, 6); return 0; } diff --git a/arch/mips/kernel/irixioctl.c b/arch/mips/kernel/irixioctl.c index 30f9eb0..2bde200d 100644 --- a/arch/mips/kernel/irixioctl.c +++ b/arch/mips/kernel/irixioctl.c @@ -238,7 +238,7 @@ asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg) current->comm, current->pid, cmd); do_exit(255); #else - error = sys_ioctl (fd, cmd, arg); + error = sys_ioctl(fd, cmd, arg); #endif } diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index 1ecdd50..4edc7e4 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c @@ -99,7 +99,7 @@ void ll_msc_irq(void) } void -msc_bind_eic_interrupt (unsigned int irq, unsigned int set) +msc_bind_eic_interrupt(unsigned int irq, unsigned int set) { MSCIC_WRITE(MSC01_IC_RAMW, (irq<tv_sec) || - __put_user (t.tv_nsec, &interval->tv_nsec)) + __put_user(t.tv_nsec, &interval->tv_nsec)) return -EFAULT; return ret; } @@ -314,7 +314,7 @@ asmlinkage int sys32_sched_rr_get_interval(compat_pid_t pid, #ifdef CONFIG_SYSVIPC asmlinkage long -sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth) +sys32_ipc(u32 call, int first, int second, int third, u32 ptr, u32 fifth) { int version, err; @@ -373,7 +373,7 @@ sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth) #else asmlinkage long -sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth) +sys32_ipc(u32 call, int first, int second, int third, u32 ptr, u32 fifth) { return -ENOSYS; } @@ -505,7 +505,7 @@ asmlinkage int sys32_ustat(dev_t dev, struct ustat32 __user * ubuf32) set_fs(KERNEL_DS); err = sys_ustat(dev, (struct ustat __user *)&tmp); - set_fs (old_fs); + set_fs(old_fs); if (err) goto out; diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c index 56750b0..3d6b1ec 100644 --- a/arch/mips/kernel/mips-mt.c +++ b/arch/mips/kernel/mips-mt.c @@ -236,7 +236,7 @@ void mips_mt_set_cpuoptions(void) if (oconfig7 != nconfig7) { __asm__ __volatile("sync"); write_c0_config7(nconfig7); - ehb (); + ehb(); printk("Config7: 0x%08x\n", read_c0_config7()); } diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index f99bb40..11cb264 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -202,13 +202,13 @@ void elf_dump_regs(elf_greg_t *gp, struct pt_regs *regs) #endif } -int dump_task_regs (struct task_struct *tsk, elf_gregset_t *regs) +int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs) { elf_dump_regs(*regs, task_pt_regs(tsk)); return 1; } -int dump_task_fpu (struct task_struct *t, elf_fpregset_t *fpr) +int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpr) { memcpy(fpr, &t->thread.fpu, sizeof(current->thread.fpu)); diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index bbd57b2..58aa6fe 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -54,7 +54,7 @@ void ptrace_disable(struct task_struct *child) * for 32-bit kernels and for 32-bit processes on a 64-bit kernel. * Registers are sign extended to fill the available space. */ -int ptrace_getregs (struct task_struct *child, __s64 __user *data) +int ptrace_getregs(struct task_struct *child, __s64 __user *data) { struct pt_regs *regs; int i; @@ -65,13 +65,13 @@ int ptrace_getregs (struct task_struct *child, __s64 __user *data) regs = task_pt_regs(child); for (i = 0; i < 32; i++) - __put_user (regs->regs[i], data + i); - __put_user (regs->lo, data + EF_LO - EF_R0); - __put_user (regs->hi, data + EF_HI - EF_R0); - __put_user (regs->cp0_epc, data + EF_CP0_EPC - EF_R0); - __put_user (regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0); - __put_user (regs->cp0_status, data + EF_CP0_STATUS - EF_R0); - __put_user (regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0); + __put_user(regs->regs[i], data + i); + __put_user(regs->lo, data + EF_LO - EF_R0); + __put_user(regs->hi, data + EF_HI - EF_R0); + __put_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0); + __put_user(regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0); + __put_user(regs->cp0_status, data + EF_CP0_STATUS - EF_R0); + __put_user(regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0); return 0; } @@ -81,7 +81,7 @@ int ptrace_getregs (struct task_struct *child, __s64 __user *data) * the 64-bit format. On a 32-bit kernel only the lower order half * (according to endianness) will be used. */ -int ptrace_setregs (struct task_struct *child, __s64 __user *data) +int ptrace_setregs(struct task_struct *child, __s64 __user *data) { struct pt_regs *regs; int i; @@ -92,17 +92,17 @@ int ptrace_setregs (struct task_struct *child, __s64 __user *data) regs = task_pt_regs(child); for (i = 0; i < 32; i++) - __get_user (regs->regs[i], data + i); - __get_user (regs->lo, data + EF_LO - EF_R0); - __get_user (regs->hi, data + EF_HI - EF_R0); - __get_user (regs->cp0_epc, data + EF_CP0_EPC - EF_R0); + __get_user(regs->regs[i], data + i); + __get_user(regs->lo, data + EF_LO - EF_R0); + __get_user(regs->hi, data + EF_HI - EF_R0); + __get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0); /* badvaddr, status, and cause may not be written. */ return 0; } -int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) +int ptrace_getfpregs(struct task_struct *child, __u32 __user *data) { int i; unsigned int tmp; @@ -113,13 +113,13 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) if (tsk_used_math(child)) { fpureg_t *fregs = get_fpu_regs(child); for (i = 0; i < 32; i++) - __put_user (fregs[i], i + (__u64 __user *) data); + __put_user(fregs[i], i + (__u64 __user *) data); } else { for (i = 0; i < 32; i++) - __put_user ((__u64) -1, i + (__u64 __user *) data); + __put_user((__u64) -1, i + (__u64 __user *) data); } - __put_user (child->thread.fpu.fcr31, data + 64); + __put_user(child->thread.fpu.fcr31, data + 64); preempt_disable(); if (cpu_has_fpu) { @@ -142,12 +142,12 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) tmp = 0; } preempt_enable(); - __put_user (tmp, data + 65); + __put_user(tmp, data + 65); return 0; } -int ptrace_setfpregs (struct task_struct *child, __u32 __user *data) +int ptrace_setfpregs(struct task_struct *child, __u32 __user *data) { fpureg_t *fregs; int i; @@ -158,9 +158,9 @@ int ptrace_setfpregs (struct task_struct *child, __u32 __user *data) fregs = get_fpu_regs(child); for (i = 0; i < 32; i++) - __get_user (fregs[i], i + (__u64 __user *) data); + __get_user(fregs[i], i + (__u64 __user *) data); - __get_user (child->thread.fpu.fcr31, data + 64); + __get_user(child->thread.fpu.fcr31, data + 64); /* FIR may not be written. */ @@ -390,19 +390,19 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) } case PTRACE_GETREGS: - ret = ptrace_getregs (child, (__u64 __user *) data); + ret = ptrace_getregs(child, (__u64 __user *) data); break; case PTRACE_SETREGS: - ret = ptrace_setregs (child, (__u64 __user *) data); + ret = ptrace_setregs(child, (__u64 __user *) data); break; case PTRACE_GETFPREGS: - ret = ptrace_getfpregs (child, (__u32 __user *) data); + ret = ptrace_getfpregs(child, (__u32 __user *) data); break; case PTRACE_SETFPREGS: - ret = ptrace_setfpregs (child, (__u32 __user *) data); + ret = ptrace_setfpregs(child, (__u32 __user *) data); break; case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c index d9a39c1..f2bffed 100644 --- a/arch/mips/kernel/ptrace32.c +++ b/arch/mips/kernel/ptrace32.c @@ -36,11 +36,11 @@ #include #include -int ptrace_getregs (struct task_struct *child, __s64 __user *data); -int ptrace_setregs (struct task_struct *child, __s64 __user *data); +int ptrace_getregs(struct task_struct *child, __s64 __user *data); +int ptrace_setregs(struct task_struct *child, __s64 __user *data); -int ptrace_getfpregs (struct task_struct *child, __u32 __user *data); -int ptrace_setfpregs (struct task_struct *child, __u32 __user *data); +int ptrace_getfpregs(struct task_struct *child, __u32 __user *data); +int ptrace_setfpregs(struct task_struct *child, __u32 __user *data); /* * Tracing a 32-bit process with a 64-bit strace and vice versa will not @@ -346,19 +346,19 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) } case PTRACE_GETREGS: - ret = ptrace_getregs (child, (__u64 __user *) (__u64) data); + ret = ptrace_getregs(child, (__u64 __user *) (__u64) data); break; case PTRACE_SETREGS: - ret = ptrace_setregs (child, (__u64 __user *) (__u64) data); + ret = ptrace_setregs(child, (__u64 __user *) (__u64) data); break; case PTRACE_GETFPREGS: - ret = ptrace_getfpregs (child, (__u32 __user *) (__u64) data); + ret = ptrace_getfpregs(child, (__u32 __user *) (__u64) data); break; case PTRACE_SETFPREGS: - ret = ptrace_setfpregs (child, (__u32 __user *) (__u64) data); + ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data); break; case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 64b612a..572c610 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -261,11 +261,11 @@ static inline int put_sigset(const sigset_t *kbuf, compat_sigset_t __user *ubuf) default: __put_sigset_unknown_nsig(); case 2: - err |= __put_user (kbuf->sig[1] >> 32, &ubuf->sig[3]); - err |= __put_user (kbuf->sig[1] & 0xffffffff, &ubuf->sig[2]); + err |= __put_user(kbuf->sig[1] >> 32, &ubuf->sig[3]); + err |= __put_user(kbuf->sig[1] & 0xffffffff, &ubuf->sig[2]); case 1: - err |= __put_user (kbuf->sig[0] >> 32, &ubuf->sig[1]); - err |= __put_user (kbuf->sig[0] & 0xffffffff, &ubuf->sig[0]); + err |= __put_user(kbuf->sig[0] >> 32, &ubuf->sig[1]); + err |= __put_user(kbuf->sig[0] & 0xffffffff, &ubuf->sig[0]); } return err; @@ -283,12 +283,12 @@ static inline int get_sigset(sigset_t *kbuf, const compat_sigset_t __user *ubuf) default: __get_sigset_unknown_nsig(); case 2: - err |= __get_user (sig[3], &ubuf->sig[3]); - err |= __get_user (sig[2], &ubuf->sig[2]); + err |= __get_user(sig[3], &ubuf->sig[3]); + err |= __get_user(sig[2], &ubuf->sig[2]); kbuf->sig[1] = sig[2] | (sig[3] << 32); case 1: - err |= __get_user (sig[1], &ubuf->sig[1]); - err |= __get_user (sig[0], &ubuf->sig[0]); + err |= __get_user(sig[1], &ubuf->sig[1]); + err |= __get_user(sig[0], &ubuf->sig[0]); kbuf->sig[0] = sig[0] | (sig[1] << 32); } @@ -412,10 +412,10 @@ asmlinkage int sys32_sigaltstack(nabi_no_regargs struct pt_regs regs) return -EFAULT; } - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); ret = do_sigaltstack(uss ? (stack_t __user *)&kss : NULL, uoss ? (stack_t __user *)&koss : NULL, usp); - set_fs (old_fs); + set_fs(old_fs); if (!ret && uoss) { if (!access_ok(VERIFY_WRITE, uoss, sizeof(*uoss))) @@ -559,9 +559,9 @@ asmlinkage void sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs) /* It is more difficult to avoid calling this function than to call it and ignore errors. */ old_fs = get_fs(); - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); do_sigaltstack((stack_t __user *)&st, NULL, regs.regs[29]); - set_fs (old_fs); + set_fs(old_fs); /* * Don't let your children do this ... @@ -746,11 +746,11 @@ asmlinkage int sys32_rt_sigprocmask(int how, compat_sigset_t __user *set, if (set && get_sigset(&new_set, set)) return -EFAULT; - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); ret = sys_rt_sigprocmask(how, set ? (sigset_t __user *)&new_set : NULL, oset ? (sigset_t __user *)&old_set : NULL, sigsetsize); - set_fs (old_fs); + set_fs(old_fs); if (!ret && oset && put_sigset(&old_set, oset)) return -EFAULT; @@ -765,9 +765,9 @@ asmlinkage int sys32_rt_sigpending(compat_sigset_t __user *uset, sigset_t set; mm_segment_t old_fs = get_fs(); - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); ret = sys_rt_sigpending((sigset_t __user *)&set, sigsetsize); - set_fs (old_fs); + set_fs(old_fs); if (!ret && put_sigset(&set, uset)) return -EFAULT; @@ -781,12 +781,12 @@ asmlinkage int sys32_rt_sigqueueinfo(int pid, int sig, compat_siginfo_t __user * int ret; mm_segment_t old_fs = get_fs(); - if (copy_from_user (&info, uinfo, 3*sizeof(int)) || - copy_from_user (info._sifields._pad, uinfo->_sifields._pad, SI_PAD_SIZE)) + if (copy_from_user(&info, uinfo, 3*sizeof(int)) || + copy_from_user(info._sifields._pad, uinfo->_sifields._pad, SI_PAD_SIZE)) return -EFAULT; - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); ret = sys_rt_sigqueueinfo(pid, sig, (siginfo_t __user *)&info); - set_fs (old_fs); + set_fs(old_fs); return ret; } @@ -801,10 +801,10 @@ sys32_waitid(int which, compat_pid_t pid, mm_segment_t old_fs = get_fs(); info.si_signo = 0; - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); ret = sys_waitid(which, pid, (siginfo_t __user *) &info, options, uru ? (struct rusage __user *) &ru : NULL); - set_fs (old_fs); + set_fs(old_fs); if (ret < 0 || info.si_signo == 0) return ret; diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c index eb7e059..bb277e8 100644 --- a/arch/mips/kernel/signal_n32.c +++ b/arch/mips/kernel/signal_n32.c @@ -88,7 +88,7 @@ struct rt_sigframe_n32 { #endif /* !ICACHE_REFILLS_WORKAROUND_WAR */ -extern void sigset_from_compat (sigset_t *set, compat_sigset_t *compat); +extern void sigset_from_compat(sigset_t *set, compat_sigset_t *compat); asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) { @@ -105,7 +105,7 @@ asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) unewset = (compat_sigset_t __user *) regs.regs[4]; if (copy_from_user(&uset, unewset, sizeof(uset))) return -EFAULT; - sigset_from_compat (&newset, &uset); + sigset_from_compat(&newset, &uset); sigdelsetmask(&newset, ~_BLOCKABLE); spin_lock_irq(¤t->sighand->siglock); diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index 05dcce4..94e210c 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -353,7 +353,7 @@ void core_send_ipi(int cpu, unsigned int action) unsigned long flags; int vpflags; - local_irq_save (flags); + local_irq_save(flags); vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */ diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 4d1ac96..7701828 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -372,7 +372,7 @@ void mipsmt_prepare_cpus(void) cpu++; /* Report on boot-time options */ - mips_mt_set_cpuoptions (); + mips_mt_set_cpuoptions(); if (vpelimit > 0) printk("Limit of %d VPEs set\n", vpelimit); if (tclimit > 0) @@ -572,7 +572,7 @@ void smtc_init_secondary(void) if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && ((read_c0_tcbind() & TCBIND_CURVPE) != cpu_data[smp_processor_id() - 1].vpe_id)){ - write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); + write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ); } local_irq_enable(); diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index 7c800ec..ef2c636 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -314,8 +314,8 @@ asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3) * * This is really horribly ugly. */ -asmlinkage int sys_ipc (unsigned int call, int first, int second, - unsigned long third, void __user *ptr, long fifth) +asmlinkage int sys_ipc(unsigned int call, int first, int second, + unsigned long third, void __user *ptr, long fifth) { int version, ret; @@ -324,26 +324,26 @@ asmlinkage int sys_ipc (unsigned int call, int first, int second, switch (call) { case SEMOP: - return sys_semtimedop (first, (struct sembuf __user *)ptr, - second, NULL); + return sys_semtimedop(first, (struct sembuf __user *)ptr, + second, NULL); case SEMTIMEDOP: - return sys_semtimedop (first, (struct sembuf __user *)ptr, - second, - (const struct timespec __user *)fifth); + return sys_semtimedop(first, (struct sembuf __user *)ptr, + second, + (const struct timespec __user *)fifth); case SEMGET: - return sys_semget (first, second, third); + return sys_semget(first, second, third); case SEMCTL: { union semun fourth; if (!ptr) return -EINVAL; if (get_user(fourth.__pad, (void __user *__user *) ptr)) return -EFAULT; - return sys_semctl (first, second, third, fourth); + return sys_semctl(first, second, third, fourth); } case MSGSND: - return sys_msgsnd (first, (struct msgbuf __user *) ptr, - second, third); + return sys_msgsnd(first, (struct msgbuf __user *) ptr, + second, third); case MSGRCV: switch (version) { case 0: { @@ -353,45 +353,45 @@ asmlinkage int sys_ipc (unsigned int call, int first, int second, if (copy_from_user(&tmp, (struct ipc_kludge __user *) ptr, - sizeof (tmp))) + sizeof(tmp))) return -EFAULT; - return sys_msgrcv (first, tmp.msgp, second, - tmp.msgtyp, third); + return sys_msgrcv(first, tmp.msgp, second, + tmp.msgtyp, third); } default: - return sys_msgrcv (first, - (struct msgbuf __user *) ptr, - second, fifth, third); + return sys_msgrcv(first, + (struct msgbuf __user *) ptr, + second, fifth, third); } case MSGGET: - return sys_msgget ((key_t) first, second); + return sys_msgget((key_t) first, second); case MSGCTL: - return sys_msgctl (first, second, - (struct msqid_ds __user *) ptr); + return sys_msgctl(first, second, + (struct msqid_ds __user *) ptr); case SHMAT: switch (version) { default: { unsigned long raddr; - ret = do_shmat (first, (char __user *) ptr, second, - &raddr); + ret = do_shmat(first, (char __user *) ptr, second, + &raddr); if (ret) return ret; - return put_user (raddr, (unsigned long __user *) third); + return put_user(raddr, (unsigned long __user *) third); } case 1: /* iBCS2 emulator entry point */ if (!segment_eq(get_fs(), get_ds())) return -EINVAL; - return do_shmat (first, (char __user *) ptr, second, - (unsigned long *) third); + return do_shmat(first, (char __user *) ptr, second, + (unsigned long *) third); } case SHMDT: - return sys_shmdt ((char __user *)ptr); + return sys_shmdt((char __user *)ptr); case SHMGET: - return sys_shmget (first, second, third); + return sys_shmget(first, second, third); case SHMCTL: - return sys_shmctl (first, second, - (struct shmid_ds __user *) ptr); + return sys_shmctl(first, second, + (struct shmid_ds __user *) ptr); default: return -ENOSYS; } diff --git a/arch/mips/kernel/sysirix.c b/arch/mips/kernel/sysirix.c index 93a1484..b502395 100644 --- a/arch/mips/kernel/sysirix.c +++ b/arch/mips/kernel/sysirix.c @@ -486,10 +486,10 @@ asmlinkage int irix_syssgi(struct pt_regs *regs) switch (arg1) { case SGI_INV_SIZEOF: - retval = sizeof (inventory_t); + retval = sizeof(inventory_t); break; case SGI_INV_READ: - retval = dump_inventory_to_user (buffer, count); + retval = dump_inventory_to_user(buffer, count); break; default: retval = -EINVAL; @@ -1042,9 +1042,9 @@ asmlinkage unsigned long irix_mmap32(unsigned long addr, size_t len, int prot, long max_size = offset + len; if (max_size > file->f_path.dentry->d_inode->i_size) { - old_pos = sys_lseek (fd, max_size - 1, 0); - sys_write (fd, (void __user *) "", 1); - sys_lseek (fd, old_pos, 0); + old_pos = sys_lseek(fd, max_size - 1, 0); + sys_write(fd, (void __user *) "", 1); + sys_lseek(fd, old_pos, 0); } } } @@ -1176,7 +1176,7 @@ static int irix_xstat32_xlate(struct kstat *stat, void __user *ubuf) ub.st_ctime1 = stat->atime.tv_nsec; ub.st_blksize = stat->blksize; ub.st_blocks = stat->blocks; - strcpy (ub.st_fstype, "efs"); + strcpy(ub.st_fstype, "efs"); return copy_to_user(ubuf, &ub, sizeof(ub)) ? -EFAULT : 0; } @@ -1208,7 +1208,7 @@ static int irix_xstat64_xlate(struct kstat *stat, void __user *ubuf) ks.st_nlink = (u32) stat->nlink; ks.st_uid = (s32) stat->uid; ks.st_gid = (s32) stat->gid; - ks.st_rdev = sysv_encode_dev (stat->rdev); + ks.st_rdev = sysv_encode_dev(stat->rdev); ks.st_pad2[0] = ks.st_pad2[1] = 0; ks.st_size = (long long) stat->size; ks.st_pad3 = 0; @@ -1527,9 +1527,9 @@ asmlinkage int irix_mmap64(struct pt_regs *regs) long max_size = off2 + len; if (max_size > file->f_path.dentry->d_inode->i_size) { - old_pos = sys_lseek (fd, max_size - 1, 0); - sys_write (fd, (void __user *) "", 1); - sys_lseek (fd, old_pos, 0); + old_pos = sys_lseek(fd, max_size - 1, 0); + sys_write(fd, (void __user *) "", 1); + sys_lseek(fd, old_pos, 0); } } } diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 369a5f9..5892491 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -149,7 +149,7 @@ EXPORT_SYMBOL_GPL(cp0_perfcount_irq); * Possibly handle a performance counter interrupt. * Return true if the timer interrupt should not be checked */ -static inline int handle_perf_irq (int r2) +static inline int handle_perf_irq(int r2) { /* * The performance counter overflow interrupt may be shared with the diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ac762d8..b3e408b 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -627,7 +627,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) lose_fpu(1); /* Run the emulator */ - sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu, 1); + sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1); /* * We can't allow the emulated instruction to leave any of @@ -1165,11 +1165,11 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) if (cpu_has_veic) { if (board_bind_eic_interrupt) - board_bind_eic_interrupt (n, srs); + board_bind_eic_interrupt(n, srs); } else if (cpu_has_vint) { /* SRSMap is only defined if shadow sets are implemented */ if (mips_srs_max() > 1) - change_c0_srsmap (0xf << n*4, srs << n*4); + change_c0_srsmap(0xf << n*4, srs << n*4); } if (srs == 0) { @@ -1198,10 +1198,10 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) * Sigh... panicing won't help as the console * is probably not configured :( */ - panic ("VECTORSPACING too small"); + panic("VECTORSPACING too small"); } - memcpy (b, &except_vec_vi, handler_len); + memcpy(b, &except_vec_vi, handler_len); #ifdef CONFIG_MIPS_MT_SMTC BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ @@ -1370,9 +1370,9 @@ void __init per_cpu_trap_init(void) #endif /* CONFIG_MIPS_MT_SMTC */ if (cpu_has_veic || cpu_has_vint) { - write_c0_ebase (ebase); + write_c0_ebase(ebase); /* Setting vector spacing enables EI/VI mode */ - change_c0_intctl (0x3e0, VECTORSPACING); + change_c0_intctl(0x3e0, VECTORSPACING); } if (cpu_has_divec) { if (cpu_has_mipsmt) { @@ -1390,8 +1390,8 @@ void __init per_cpu_trap_init(void) * o read IntCtl.IPPCI to determine the performance counter interrupt */ if (cpu_has_mips_r2) { - cp0_compare_irq = (read_c0_intctl () >> 29) & 7; - cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7; + cp0_compare_irq = (read_c0_intctl() >> 29) & 7; + cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; if (cp0_perfcount_irq == cp0_compare_irq) cp0_perfcount_irq = -1; } else { @@ -1429,7 +1429,7 @@ void __init per_cpu_trap_init(void) } /* Install CPU exception handler */ -void __init set_handler (unsigned long offset, void *addr, unsigned long size) +void __init set_handler(unsigned long offset, void *addr, unsigned long size) { memcpy((void *)(ebase + offset), addr, size); flush_icache_range(ebase + offset, ebase + offset + size); @@ -1439,7 +1439,7 @@ static char panic_null_cerr[] __initdata = "Trying to set NULL cache error exception handler"; /* Install uncached CPU exception handler */ -void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size) +void __init set_uncached_handler(unsigned long offset, void *addr, unsigned long size) { #ifdef CONFIG_32BIT unsigned long uncached_ebase = KSEG1ADDR(ebase); @@ -1470,7 +1470,7 @@ void __init trap_init(void) unsigned long i; if (cpu_has_veic || cpu_has_vint) - ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64); + ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); else ebase = CAC_BASE; @@ -1496,7 +1496,7 @@ void __init trap_init(void) * destination. */ if (cpu_has_ejtag && board_ejtag_handler_setup) - board_ejtag_handler_setup (); + board_ejtag_handler_setup(); /* * Only some CPUs have the watch exceptions. diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index d34b1fb..c327b21 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -481,7 +481,7 @@ fault: if (fixup_exception(regs)) return; - die_if_kernel ("Unhandled kernel unaligned access", regs); + die_if_kernel("Unhandled kernel unaligned access", regs); send_sig(SIGSEGV, current, 1); return; diff --git a/arch/mips/lib/ucmpdi2.c b/arch/mips/lib/ucmpdi2.c index e2ff607..b33d856 100644 --- a/arch/mips/lib/ucmpdi2.c +++ b/arch/mips/lib/ucmpdi2.c @@ -2,7 +2,7 @@ #include "libgcc.h" -word_type __ucmpdi2 (unsigned long long a, unsigned long long b) +word_type __ucmpdi2(unsigned long long a, unsigned long long b) { const DWunion au = {.ll = a}; const DWunion bu = {.ll = b}; diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 17419e11..c44e9cc 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -549,16 +549,16 @@ static const unsigned char cmptab[8] = { */ #define DEF3OP(name, p, f1, f2, f3) \ -static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \ +static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \ ieee754##p t) \ { \ struct _ieee754_csr ieee754_csr_save; \ - s = f1 (s, t); \ + s = f1(s, t); \ ieee754_csr_save = ieee754_csr; \ - s = f2 (s, r); \ + s = f2(s, r); \ ieee754_csr_save.cx |= ieee754_csr.cx; \ ieee754_csr_save.sx |= ieee754_csr.sx; \ - s = f3 (s); \ + s = f3(s); \ ieee754_csr.cx |= ieee754_csr_save.cx; \ ieee754_csr.sx |= ieee754_csr_save.sx; \ return s; \ diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c index 3c692ab..6fb29c3 100644 --- a/arch/mips/mips-boards/atlas/atlas_int.c +++ b/arch/mips/mips-boards/atlas/atlas_int.c @@ -112,7 +112,7 @@ static inline void atlas_hw0_irqdispatch(void) static inline int clz(unsigned long x) { - __asm__ ( + __asm__( " .set push \n" " .set mips32 \n" " clz %0, %1 \n" @@ -194,7 +194,7 @@ asmlinkage void plat_irq_dispatch(void) spurious_interrupt(); } -static inline void init_atlas_irqs (int base) +static inline void init_atlas_irqs(int base) { int i; @@ -249,21 +249,21 @@ void __init arch_init_irq(void) case MIPS_REVISION_CORID_CORE_24K: case MIPS_REVISION_CORID_CORE_EMUL_MSC: if (cpu_has_veic) - init_msc_irqs (MSC01E_INT_BASE, MSC01E_INT_BASE, - msc_eicirqmap, msc_nr_eicirqs); + init_msc_irqs(MSC01E_INT_BASE, MSC01E_INT_BASE, + msc_eicirqmap, msc_nr_eicirqs); else - init_msc_irqs (MSC01E_INT_BASE, MSC01C_INT_BASE, - msc_irqmap, msc_nr_irqs); + init_msc_irqs(MSC01E_INT_BASE, MSC01C_INT_BASE, + msc_irqmap, msc_nr_irqs); } if (cpu_has_veic) { - set_vi_handler (MSC01E_INT_ATLAS, atlas_hw0_irqdispatch); - setup_irq (MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq); + set_vi_handler(MSC01E_INT_ATLAS, atlas_hw0_irqdispatch); + setup_irq(MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq); } else if (cpu_has_vint) { - set_vi_handler (MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch); + set_vi_handler(MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch); #ifdef CONFIG_MIPS_MT_SMTC - setup_irq_smtc (MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, - &atlasirq, (0x100 << MIPSCPU_INT_ATLAS)); + setup_irq_smtc(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, + &atlasirq, (0x100 << MIPSCPU_INT_ATLAS)); #else /* Not SMTC */ setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq); #endif /* CONFIG_MIPS_MT_SMTC */ diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c index 86bfc05..e405d11 100644 --- a/arch/mips/mips-boards/atlas/atlas_setup.c +++ b/arch/mips/mips-boards/atlas/atlas_setup.c @@ -55,7 +55,7 @@ void __init plat_mem_setup(void) ioport_resource.end = 0x7fffffff; - serial_init (); + serial_init(); #ifdef CONFIG_KGDB kgdb_config(); diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index e2c7147..30f1f54 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c @@ -166,15 +166,15 @@ static void __init console_config(void) bits = '8'; if (flow == '\0') flow = 'r'; - sprintf (console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); - strcat (prom_getcmdline(), console_string); + sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); + strcat(prom_getcmdline(), console_string); pr_info("Config serial console:%s\n", console_string); } } #endif #ifdef CONFIG_KGDB -void __init kgdb_config (void) +void __init kgdb_config(void) { extern int (*generic_putDebugChar)(char); extern char (*generic_getDebugChar)(void); @@ -218,7 +218,7 @@ void __init kgdb_config (void) { char *s; for (s = "Please connect GDB to this port\r\n"; *s; ) - generic_putDebugChar (*s++); + generic_putDebugChar(*s++); } /* Breakpoint is invoked after interrupts are initialised */ @@ -226,7 +226,7 @@ void __init kgdb_config (void) } #endif -void __init mips_nmi_setup (void) +void __init mips_nmi_setup(void) { void *base; extern char except_vec_nmi; @@ -238,7 +238,7 @@ void __init mips_nmi_setup (void) flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); } -void __init mips_ejtag_setup (void) +void __init mips_ejtag_setup(void) { void *base; extern char except_vec_ejtag_debug; diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c index ae39953..dc272c1 100644 --- a/arch/mips/mips-boards/generic/memory.c +++ b/arch/mips/mips-boards/generic/memory.c @@ -125,7 +125,7 @@ struct prom_pmemblock * __init prom_getmdesc(void) return &mdesc[0]; } -static int __init prom_memtype_classify (unsigned int type) +static int __init prom_memtype_classify(unsigned int type) { switch (type) { case yamon_free: @@ -158,7 +158,7 @@ void __init prom_meminit(void) long type; unsigned long base, size; - type = prom_memtype_classify (p->type); + type = prom_memtype_classify(p->type); base = p->base; size = p->size; diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c index c985220..b974319 100644 --- a/arch/mips/mips-boards/generic/pci.c +++ b/arch/mips/mips-boards/generic/pci.c @@ -239,5 +239,5 @@ void __init mips_pcibios_init(void) iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ ioport_resource.end = controller->io_resource->end; - register_pci_controller (controller); + register_pci_controller(controller); } diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index 4fab3b2..1d00b77 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -134,7 +134,7 @@ void __init plat_time_init(void) /* Set Data mode - binary. */ CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); - est_freq = estimate_cpu_frequency (); + est_freq = estimate_cpu_frequency(); printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, (est_freq%1000000)*100/1000000); @@ -166,7 +166,7 @@ void __init plat_perf_setup(void) #ifdef MSC01E_INT_BASE if (cpu_has_veic) { - set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch); + set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; } else #endif @@ -183,7 +183,7 @@ void __init plat_timer_setup(struct irqaction *irq) { #ifdef MSC01E_INT_BASE if (cpu_has_veic) { - set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); + set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; } else diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c index b73f218..8232392 100644 --- a/arch/mips/mips-boards/malta/malta_int.c +++ b/arch/mips/mips-boards/malta/malta_int.c @@ -178,7 +178,7 @@ static void corehi_irqdispatch(void) static inline int clz(unsigned long x) { - __asm__ ( + __asm__( " .set push \n" " .set mips32 \n" " clz %0, %1 \n" @@ -303,32 +303,32 @@ void __init arch_init_irq(void) case MIPS_REVISION_SCON_SOCIT: case MIPS_REVISION_SCON_ROCIT: if (cpu_has_veic) - init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); + init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); else - init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); + init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); break; case MIPS_REVISION_SCON_SOCITSC: case MIPS_REVISION_SCON_SOCITSCP: if (cpu_has_veic) - init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); + init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); else - init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); + init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); } if (cpu_has_veic) { - set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch); - set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch); - setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); - setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); + set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch); + set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch); + setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); + setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); } else if (cpu_has_vint) { - set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); - set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch); + set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); + set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch); #ifdef CONFIG_MIPS_MT_SMTC - setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq, + setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq, (0x100 << MIPSCPU_INT_I8259A)); - setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, + setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); /* * Temporary hack to ensure that the subsidiary device @@ -343,12 +343,12 @@ void __init arch_init_irq(void) irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A); } #else /* Not SMTC */ - setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); - setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); + setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); + setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); #endif /* CONFIG_MIPS_MT_SMTC */ } else { - setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); - setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); + setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); + setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); } } diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c index a5a5a43..e243d5e 100644 --- a/arch/mips/mips-boards/malta/malta_setup.c +++ b/arch/mips/mips-boards/malta/malta_setup.c @@ -99,7 +99,7 @@ void __init plat_mem_setup(void) enable_dma(4); #ifdef CONFIG_KGDB - kgdb_config (); + kgdb_config(); #endif if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { @@ -108,7 +108,7 @@ void __init plat_mem_setup(void) argptr = prom_getcmdline(); if (strstr(argptr, "debug")) { BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; - printk ("Enabled Bonito debug mode\n"); + printk("Enabled Bonito debug mode\n"); } else BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; @@ -159,14 +159,14 @@ void __init plat_mem_setup(void) if (pciclock != 33 && !strstr (argptr, "idebus=")) { printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock); argptr += strlen(argptr); - sprintf (argptr, " idebus=%d", pciclock); + sprintf(argptr, " idebus=%d", pciclock); if (pciclock < 20 || pciclock > 66) - printk ("WARNING: IDE timing calculations will be incorrect\n"); + printk("WARNING: IDE timing calculations will be incorrect\n"); } } #endif #ifdef CONFIG_BLK_DEV_FD - fd_activate (); + fd_activate(); #endif #ifdef CONFIG_VT #if defined(CONFIG_VGA_CONSOLE) diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c index 9ca0f82..ec6dd19 100644 --- a/arch/mips/mips-boards/sead/sead_int.c +++ b/arch/mips/mips-boards/sead/sead_int.c @@ -31,7 +31,7 @@ static inline int clz(unsigned long x) { - __asm__ ( + __asm__( " .set push \n" " .set mips32 \n" " clz %0, %1 \n" diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c index fad5897..1fb61b8 100644 --- a/arch/mips/mips-boards/sead/sead_setup.c +++ b/arch/mips/mips-boards/sead/sead_setup.c @@ -49,7 +49,7 @@ void __init plat_mem_setup(void) { ioport_resource.end = 0x7fffffff; - serial_init (); + serial_init(); mips_reboot_setup(); } diff --git a/arch/mips/mipssim/sim_int.c b/arch/mips/mipssim/sim_int.c index 5cbc350..46067ad 100644 --- a/arch/mips/mipssim/sim_int.c +++ b/arch/mips/mipssim/sim_int.c @@ -25,7 +25,7 @@ static inline int clz(unsigned long x) { - __asm__ ( + __asm__( " .set push \n" " .set mips32 \n" " clz %0, %1 \n" diff --git a/arch/mips/mipssim/sim_mem.c b/arch/mips/mipssim/sim_mem.c index 2312483..953d836 100644 --- a/arch/mips/mipssim/sim_mem.c +++ b/arch/mips/mipssim/sim_mem.c @@ -69,7 +69,7 @@ struct prom_pmemblock * __init prom_getmdesc(void) return &mdesc[0]; } -static int __init prom_memtype_classify (unsigned int type) +static int __init prom_memtype_classify(unsigned int type) { switch (type) { case simmem_free: @@ -90,7 +90,7 @@ void __init prom_meminit(void) long type; unsigned long base, size; - type = prom_memtype_classify (p->type); + type = prom_memtype_classify(p->type); base = p->base; size = p->size; diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c index 3625f7d..e7fa0d1 100644 --- a/arch/mips/mipssim/sim_time.c +++ b/arch/mips/mipssim/sim_time.c @@ -84,7 +84,7 @@ void __init plat_time_init(void) /* Set Data mode - binary. */ CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); - est_freq = estimate_cpu_frequency (); + est_freq = estimate_cpu_frequency(); printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000, (est_freq % 1000000) * 100 / 1000000); diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c index 59868a1..c55312f 100644 --- a/arch/mips/mm/c-r3k.c +++ b/arch/mips/mm/c-r3k.c @@ -121,7 +121,7 @@ static void r3k_flush_icache_range(unsigned long start, unsigned long end) write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC); for (i = 0; i < size; i += 0x080) { - asm ( "sb\t$0, 0x000(%0)\n\t" + asm( "sb\t$0, 0x000(%0)\n\t" "sb\t$0, 0x004(%0)\n\t" "sb\t$0, 0x008(%0)\n\t" "sb\t$0, 0x00c(%0)\n\t" @@ -178,7 +178,7 @@ static void r3k_flush_dcache_range(unsigned long start, unsigned long end) write_c0_status((ST0_ISC|flags)&~ST0_IEC); for (i = 0; i < size; i += 0x080) { - asm ( "sb\t$0, 0x000(%0)\n\t" + asm( "sb\t$0, 0x000(%0)\n\t" "sb\t$0, 0x004(%0)\n\t" "sb\t$0, 0x008(%0)\n\t" "sb\t$0, 0x00c(%0)\n\t" @@ -217,8 +217,8 @@ static void r3k_flush_dcache_range(unsigned long start, unsigned long end) write_c0_status(flags); } -static inline unsigned long get_phys_page (unsigned long addr, - struct mm_struct *mm) +static inline unsigned long get_phys_page(unsigned long addr, + struct mm_struct *mm) { pgd_t *pgd; pud_t *pud; @@ -281,13 +281,13 @@ static void r3k_flush_cache_sigtramp(unsigned long addr) write_c0_status(flags&~ST0_IEC); /* Fill the TLB to avoid an exception with caches isolated. */ - asm ( "lw\t$0, 0x000(%0)\n\t" + asm( "lw\t$0, 0x000(%0)\n\t" "lw\t$0, 0x004(%0)\n\t" : : "r" (addr) ); write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC); - asm ( "sb\t$0, 0x000(%0)\n\t" + asm( "sb\t$0, 0x000(%0)\n\t" "sb\t$0, 0x004(%0)\n\t" : : "r" (addr) ); diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 42b5096..c13170b 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -102,7 +102,7 @@ static inline int __init mips_sc_probe(void) int __init mips_sc_init(void) { - int found = mips_sc_probe (); + int found = mips_sc_probe(); if (found) { mips_sc_enable(); bcops = &mips_sc_ops; diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index dcd6913..74ae034 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -491,7 +491,7 @@ void __init tlb_init(void) int wired = current_cpu_data.tlbsize - ntlb; write_c0_wired(wired); write_c0_index(wired-1); - printk ("Restricting TLB to %d entries\n", ntlb); + printk("Restricting TLB to %d entries\n", ntlb); } else printk("Ignoring invalid argument ntlb=%d\n", ntlb); } diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 6383000..423bc2c 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -118,7 +118,7 @@ static void mipsxx_reg_setup(struct op_counter_config *ctr) /* Program all of the registers in preparation for enabling profiling. */ -static void mipsxx_cpu_setup (void *args) +static void mipsxx_cpu_setup(void *args) { unsigned int counters = op_model_mipsxx_ops.num_counters; diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c index d29040a..a45d320 100644 --- a/arch/mips/oprofile/op_model_rm9000.c +++ b/arch/mips/oprofile/op_model_rm9000.c @@ -60,7 +60,7 @@ static void rm9000_reg_setup(struct op_counter_config *ctr) /* Program all of the registers in preparation for enabling profiling. */ -static void rm9000_cpu_setup (void *args) +static void rm9000_cpu_setup(void *args) { uint64_t perfcount; diff --git a/arch/mips/pci/fixup-atlas.c b/arch/mips/pci/fixup-atlas.c index 45224fd..506e883 100644 --- a/arch/mips/pci/fixup-atlas.c +++ b/arch/mips/pci/fixup-atlas.c @@ -77,12 +77,12 @@ int pcibios_plat_dev_init(struct pci_dev *dev) * code, but it is better than nothing... */ -static void atlas_saa9730_base_fixup (struct pci_dev *pdev) +static void atlas_saa9730_base_fixup(struct pci_dev *pdev) { extern void *saa9730_base; if (pdev->bus == 0 && PCI_SLOT(pdev->devfn) == 19) - (void) pci_read_config_dword (pdev, 0x14, (u32 *)&saa9730_base); - printk ("saa9730_base = %x\n", saa9730_base); + (void) pci_read_config_dword(pdev, 0x14, (u32 *)&saa9730_base); + printk("saa9730_base = %x\n", saa9730_base); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA9730, diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c index 7932dfe..6b29904 100644 --- a/arch/mips/pci/ops-au1000.c +++ b/arch/mips/pci/ops-au1000.c @@ -112,7 +112,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, first_cfg = 0; pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); if (!pci_cfg_vm) - panic (KERN_ERR "PCI unable to get vm area\n"); + panic(KERN_ERR "PCI unable to get vm area\n"); pci_cfg_wired_entry = read_c0_wired(); add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K); last_entryLo0 = last_entryLo1 = 0xffffffff; diff --git a/arch/mips/pci/ops-sni.c b/arch/mips/pci/ops-sni.c index fa2d2c6..97ed25b 100644 --- a/arch/mips/pci/ops-sni.c +++ b/arch/mips/pci/ops-sni.c @@ -70,13 +70,13 @@ static int pcimt_write(struct pci_bus *bus, unsigned int devfn, int reg, switch (size) { case 1: - outb (val, PCIMT_CONFIG_DATA + (reg & 3)); + outb(val, PCIMT_CONFIG_DATA + (reg & 3)); break; case 2: - outw (val, PCIMT_CONFIG_DATA + (reg & 2)); + outw(val, PCIMT_CONFIG_DATA + (reg & 2)); break; case 4: - outl (val, PCIMT_CONFIG_DATA); + outl(val, PCIMT_CONFIG_DATA); break; } @@ -93,7 +93,7 @@ static int pcit_set_config_address(unsigned int busno, unsigned int devfn, int r if ((devfn > 255) || (reg > 255) || (busno > 255)) return PCIBIOS_BAD_REGISTER_NUMBER; - outl ((1 << 31) | ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc), 0xcf8); + outl((1 << 31) | ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc), 0xcf8); return PCIBIOS_SUCCESSFUL; } @@ -108,12 +108,12 @@ static int pcit_read(struct pci_bus *bus, unsigned int devfn, int reg, * we don't do it, we will get a data bus error */ if (bus->number == 0) { - pcit_set_config_address (0, 0, 0x68); - outl (inl (0xcfc) | 0xc0000000, 0xcfc); + pcit_set_config_address(0, 0, 0x68); + outl(inl(0xcfc) | 0xc0000000, 0xcfc); if ((res = pcit_set_config_address(0, devfn, 0))) return res; - outl (0xffffffff, 0xcfc); - pcit_set_config_address (0, 0, 0x68); + outl(0xffffffff, 0xcfc); + pcit_set_config_address(0, 0, 0x68); if (inl(0xcfc) & 0x100000) return PCIBIOS_DEVICE_NOT_FOUND; } @@ -144,13 +144,13 @@ static int pcit_write(struct pci_bus *bus, unsigned int devfn, int reg, switch (size) { case 1: - outb (val, PCIMT_CONFIG_DATA + (reg & 3)); + outb(val, PCIMT_CONFIG_DATA + (reg & 3)); break; case 2: - outw (val, PCIMT_CONFIG_DATA + (reg & 2)); + outw(val, PCIMT_CONFIG_DATA + (reg & 2)); break; case 4: - outl (val, PCIMT_CONFIG_DATA); + outl(val, PCIMT_CONFIG_DATA); break; } diff --git a/arch/mips/philips/pnx8550/common/proc.c b/arch/mips/philips/pnx8550/common/proc.c index 92311e9..416f834 100644 --- a/arch/mips/philips/pnx8550/common/proc.c +++ b/arch/mips/philips/pnx8550/common/proc.c @@ -27,7 +27,7 @@ #include -static int pnx8550_timers_read (char* page, char** start, off_t offset, int count, int* eof, void* data) +static int pnx8550_timers_read(char* page, char** start, off_t offset, int count, int* eof, void* data) { int len = 0; int configPR = read_c0_config7(); @@ -48,7 +48,7 @@ static int pnx8550_timers_read (char* page, char** start, off_t offset, int coun return len; } -static int pnx8550_registers_read (char* page, char** start, off_t offset, int count, int* eof, void* data) +static int pnx8550_registers_read(char* page, char** start, off_t offset, int count, int* eof, void* data) { int len = 0; diff --git a/arch/mips/pmc-sierra/msp71xx/msp_usb.c b/arch/mips/pmc-sierra/msp71xx/msp_usb.c index 21f9c70..f7ca4f5 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_usb.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_usb.c @@ -58,7 +58,7 @@ static struct platform_device msp_usbhost_device = { .dma_mask = &msp_usbhost_dma_mask, .coherent_dma_mask = DMA_32BIT_MASK, }, - .num_resources = ARRAY_SIZE (msp_usbhost_resources), + .num_resources = ARRAY_SIZE(msp_usbhost_resources), .resource = msp_usbhost_resources, }; #endif /* CONFIG_USB_EHCI_HCD */ @@ -86,7 +86,7 @@ static struct platform_device msp_usbdev_device = { .dma_mask = &msp_usbdev_dma_mask, .coherent_dma_mask = DMA_32BIT_MASK, }, - .num_resources = ARRAY_SIZE (msp_usbdev_resources), + .num_resources = ARRAY_SIZE(msp_usbdev_resources), .resource = msp_usbdev_resources, }; #endif /* CONFIG_USB_GADGET */ @@ -129,7 +129,7 @@ static int __init msp_usb_setup(void) ppfinit("platform add USB HOST done %s.\n", msp_devs[0]->name); - result = platform_add_devices(msp_devs, ARRAY_SIZE (msp_devs)); + result = platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs)); #endif /* CONFIG_USB_EHCI_HCD */ } #if defined(CONFIG_USB_GADGET) @@ -139,7 +139,7 @@ static int __init msp_usb_setup(void) ppfinit("platform add USB DEVICE done %s.\n", msp_devs[0]->name); - result = platform_add_devices(msp_devs, ARRAY_SIZE (msp_devs)); + result = platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs)); } #endif /* CONFIG_USB_GADGET */ #endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */ diff --git a/arch/mips/qemu/q-firmware.c b/arch/mips/qemu/q-firmware.c index fb2a867..c2239b4 100644 --- a/arch/mips/qemu/q-firmware.c +++ b/arch/mips/qemu/q-firmware.c @@ -10,7 +10,7 @@ void __init prom_init(void) cmdline = (int *) (CKSEG0 + (0x10 << 20) - 260); if (*cmdline == 0x12345678) { if (*(char *)(cmdline + 1)) - strcpy (arcs_cmdline, (char *)(cmdline + 1)); + strcpy(arcs_cmdline, (char *)(cmdline + 1)); add_memory_region(0x0<<20, cmdline[-1], BOOT_MEM_RAM); } else { add_memory_region(0x0<<20, 0x10<<20, BOOT_MEM_RAM); diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c index 6b6e97b..26854fb 100644 --- a/arch/mips/sgi-ip22/ip22-eisa.c +++ b/arch/mips/sgi-ip22/ip22-eisa.c @@ -55,7 +55,7 @@ static char __init *decode_eisa_sig(unsigned long addr) int i; for (i = 0; i < 4; i++) { - sig[i] = inb (addr + i); + sig[i] = inb(addr + i); if (!i && (sig[0] & 0x80)) return NULL; diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index f199da7..f6d9bf4 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c @@ -344,6 +344,6 @@ void __init arch_init_irq(void) #ifdef CONFIG_EISA if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */ - ip22_eisa_init (); + ip22_eisa_init(); #endif } diff --git a/arch/mips/sgi-ip32/crime.c b/arch/mips/sgi-ip32/crime.c index bff5087..563c614 100644 --- a/arch/mips/sgi-ip32/crime.c +++ b/arch/mips/sgi-ip32/crime.c @@ -35,8 +35,8 @@ void __init crime_init(void) id = crime->id; rev = id & CRIME_ID_REV; id = (id & CRIME_ID_IDBITS) >> 4; - printk (KERN_INFO "CRIME id %1x rev %d at 0x%0*lx\n", - id, rev, field, (unsigned long) CRIME_BASE); + printk(KERN_INFO "CRIME id %1x rev %d at 0x%0*lx\n", + id, rev, field, (unsigned long) CRIME_BASE); } irqreturn_t crime_memerr_intr(unsigned int irq, void *dev_id) @@ -96,7 +96,7 @@ irqreturn_t crime_cpuerr_intr(unsigned int irq, void *dev_id) unsigned long addr = crime->cpu_error_addr & CRIME_CPU_ERROR_ADDR_MASK; addr <<= 2; - printk ("CRIME CPU error at 0x%09lx status 0x%08lx\n", addr, stat); + printk("CRIME CPU error at 0x%09lx status 0x%08lx\n", addr, stat); crime->cpu_error_stat = 0; return IRQ_HANDLED; diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index 002095b..7f4b793 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c @@ -148,7 +148,7 @@ static void disable_cpu_irq(unsigned int irq) static void end_cpu_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - enable_cpu_irq (irq); + enable_cpu_irq(irq); } static struct irq_chip ip32_cpu_interrupt = { @@ -289,11 +289,11 @@ static struct irq_chip ip32_macepci_interrupt = { static unsigned long maceisa_mask; -static void enable_maceisa_irq (unsigned int irq) +static void enable_maceisa_irq(unsigned int irq) { unsigned int crime_int = 0; - DBG ("maceisa enable: %u\n", irq); + DBG("maceisa enable: %u\n", irq); switch (irq) { case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ: @@ -306,7 +306,7 @@ static void enable_maceisa_irq (unsigned int irq) crime_int = MACE_SUPERIO_INT; break; } - DBG ("crime_int %08x enabled\n", crime_int); + DBG("crime_int %08x enabled\n", crime_int); crime_mask |= crime_int; crime->imask = crime_mask; maceisa_mask |= 1 << (irq - 33); @@ -397,15 +397,15 @@ static struct irq_chip ip32_mace_interrupt = { static void ip32_unknown_interrupt(void) { - printk ("Unknown interrupt occurred!\n"); - printk ("cp0_status: %08x\n", read_c0_status()); - printk ("cp0_cause: %08x\n", read_c0_cause()); - printk ("CRIME intr mask: %016lx\n", crime->imask); - printk ("CRIME intr status: %016lx\n", crime->istat); - printk ("CRIME hardware intr register: %016lx\n", crime->hard_int); - printk ("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask); - printk ("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat); - printk ("MACE PCI control register: %08x\n", mace->pci.control); + printk("Unknown interrupt occurred!\n"); + printk("cp0_status: %08x\n", read_c0_status()); + printk("cp0_cause: %08x\n", read_c0_cause()); + printk("CRIME intr mask: %016lx\n", crime->imask); + printk("CRIME intr status: %016lx\n", crime->istat); + printk("CRIME hardware intr register: %016lx\n", crime->hard_int); + printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask); + printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat); + printk("MACE PCI control register: %08x\n", mace->pci.control); printk("Register dump:\n"); show_regs(get_irq_regs()); diff --git a/arch/mips/sgi-ip32/ip32-memory.c b/arch/mips/sgi-ip32/ip32-memory.c index 849d392..ca93ecf 100644 --- a/arch/mips/sgi-ip32/ip32-memory.c +++ b/arch/mips/sgi-ip32/ip32-memory.c @@ -19,7 +19,7 @@ extern void crime_init(void); -void __init prom_meminit (void) +void __init prom_meminit(void) { u64 base, size; int bank; @@ -38,7 +38,7 @@ void __init prom_meminit (void) printk("CRIME MC: bank %u base 0x%016lx size %luMiB\n", bank, base, size >> 20); - add_memory_region (base, size, BOOT_MEM_RAM); + add_memory_region(base, size, BOOT_MEM_RAM); } } diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c index 4fcdaa8..63b444e 100644 --- a/arch/mips/sibyte/common/sb_tbprof.c +++ b/arch/mips/sibyte/common/sb_tbprof.c @@ -276,8 +276,8 @@ static int sbprof_zbprof_start(struct file *filp) sbp.next_tb_sample = 0; filp->f_pos = 0; - err = request_irq (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, - DEVNAME " trace freeze", &sbp); + err = request_irq(K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, + DEVNAME " trace freeze", &sbp); if (err) return -EBUSY; diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c index acc9ba7..b746075 100644 --- a/arch/mips/sni/a20r.c +++ b/arch/mips/sni/a20r.c @@ -127,7 +127,7 @@ static u32 a20r_ack_hwint(void) { u32 status = read_c0_status(); - write_c0_status (status | 0x00010000); + write_c0_status(status | 0x00010000); asm volatile( " .set push \n" " .set noat \n" @@ -195,7 +195,7 @@ static void a20r_hwint(void) u32 cause, status; int irq; - clear_c0_status (IE_IRQ0); + clear_c0_status(IE_IRQ0); status = a20r_ack_hwint(); cause = read_c0_cause(); @@ -213,7 +213,7 @@ void __init sni_a20r_irq_init(void) set_irq_chip(i, &a20r_irq_type); sni_hwint = a20r_hwint; change_c0_status(ST0_IM, IE_IRQ0); - setup_irq (SNI_A20R_IRQ_BASE + 3, &sni_isa_irq); + setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq); } void sni_a20r_init(void) diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c index 25cf646..39bb15f 100644 --- a/arch/mips/sni/pcimt.c +++ b/arch/mips/sni/pcimt.c @@ -284,9 +284,9 @@ static void sni_pcimt_hwint(void) u32 pending = read_c0_cause() & read_c0_status(); if (pending & C_IRQ5) - do_IRQ (MIPS_CPU_IRQ_BASE + 7); + do_IRQ(MIPS_CPU_IRQ_BASE + 7); else if (pending & C_IRQ4) - do_IRQ (MIPS_CPU_IRQ_BASE + 6); + do_IRQ(MIPS_CPU_IRQ_BASE + 6); else if (pending & C_IRQ3) pcimt_hwint3(); else if (pending & C_IRQ1) diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c index 3361bdd..416f397 100644 --- a/arch/mips/sni/pcit.c +++ b/arch/mips/sni/pcit.c @@ -188,8 +188,8 @@ static void pcit_hwint1(void) irq = ffs((pending >> 16) & 0x7f); if (likely(irq > 0)) - do_IRQ (irq + SNI_PCIT_INT_START - 1); - set_c0_status (IE_IRQ1); + do_IRQ(irq + SNI_PCIT_INT_START - 1); + set_c0_status(IE_IRQ1); } static void pcit_hwint0(void) @@ -201,8 +201,8 @@ static void pcit_hwint0(void) irq = ffs((pending >> 16) & 0x3f); if (likely(irq > 0)) - do_IRQ (irq + SNI_PCIT_INT_START - 1); - set_c0_status (IE_IRQ0); + do_IRQ(irq + SNI_PCIT_INT_START - 1); + set_c0_status(IE_IRQ0); } static void sni_pcit_hwint(void) @@ -212,11 +212,11 @@ static void sni_pcit_hwint(void) if (pending & C_IRQ1) pcit_hwint1(); else if (pending & C_IRQ2) - do_IRQ (MIPS_CPU_IRQ_BASE + 4); + do_IRQ(MIPS_CPU_IRQ_BASE + 4); else if (pending & C_IRQ3) - do_IRQ (MIPS_CPU_IRQ_BASE + 5); + do_IRQ(MIPS_CPU_IRQ_BASE + 5); else if (pending & C_IRQ5) - do_IRQ (MIPS_CPU_IRQ_BASE + 7); + do_IRQ(MIPS_CPU_IRQ_BASE + 7); } static void sni_pcit_hwint_cplus(void) @@ -226,13 +226,13 @@ static void sni_pcit_hwint_cplus(void) if (pending & C_IRQ0) pcit_hwint0(); else if (pending & C_IRQ1) - do_IRQ (MIPS_CPU_IRQ_BASE + 3); + do_IRQ(MIPS_CPU_IRQ_BASE + 3); else if (pending & C_IRQ2) - do_IRQ (MIPS_CPU_IRQ_BASE + 4); + do_IRQ(MIPS_CPU_IRQ_BASE + 4); else if (pending & C_IRQ3) - do_IRQ (MIPS_CPU_IRQ_BASE + 5); + do_IRQ(MIPS_CPU_IRQ_BASE + 5); else if (pending & C_IRQ5) - do_IRQ (MIPS_CPU_IRQ_BASE + 7); + do_IRQ(MIPS_CPU_IRQ_BASE + 7); } void __init sni_pcit_irq_init(void) @@ -245,7 +245,7 @@ void __init sni_pcit_irq_init(void) *(volatile u32 *)SNI_PCIT_INT_REG = 0; sni_hwint = sni_pcit_hwint; change_c0_status(ST0_IM, IE_IRQ1); - setup_irq (SNI_PCIT_INT_START + 6, &sni_isa_irq); + setup_irq(SNI_PCIT_INT_START + 6, &sni_isa_irq); } void __init sni_pcit_cplus_irq_init(void) @@ -258,7 +258,7 @@ void __init sni_pcit_cplus_irq_init(void) *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; sni_hwint = sni_pcit_hwint_cplus; change_c0_status(ST0_IM, IE_IRQ0); - setup_irq (MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq); + setup_irq(MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq); } void __init sni_pcit_init(void) diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c index 94f115c..67b061e 100644 --- a/arch/mips/sni/rm200.c +++ b/arch/mips/sni/rm200.c @@ -162,16 +162,16 @@ static void sni_rm200_hwint(void) int irq; if (pending & C_IRQ5) - do_IRQ (MIPS_CPU_IRQ_BASE + 7); + do_IRQ(MIPS_CPU_IRQ_BASE + 7); else if (pending & C_IRQ0) { - clear_c0_status (IE_IRQ0); + clear_c0_status(IE_IRQ0); mask = *(volatile u8 *)SNI_RM200_INT_ENA_REG ^ 0x1f; stat = *(volatile u8 *)SNI_RM200_INT_STAT_REG ^ 0x14; irq = ffs(stat & mask & 0x1f); if (likely(irq > 0)) - do_IRQ (irq + SNI_RM200_INT_START - 1); - set_c0_status (IE_IRQ0); + do_IRQ(irq + SNI_RM200_INT_START - 1); + set_c0_status(IE_IRQ0); } } @@ -187,7 +187,7 @@ void __init sni_rm200_irq_init(void) set_irq_chip(i, &rm200_irq_type); sni_hwint = sni_rm200_hwint; change_c0_status(ST0_IM, IE_IRQ0); - setup_irq (SNI_RM200_INT_START + 0, &sni_isa_irq); + setup_irq(SNI_RM200_INT_START + 0, &sni_isa_irq); } void __init sni_rm200_init(void) diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c index 883e35e..e8b26bd 100644 --- a/arch/mips/sni/setup.c +++ b/arch/mips/sni/setup.c @@ -106,11 +106,11 @@ static void __devinit quirk_cirrus_ram_size(struct pci_dev *dev) * need to do it here, otherwise we get screen corruption * on older Cirrus chips */ - pci_read_config_word (dev, PCI_COMMAND, &cmd); + pci_read_config_word(dev, PCI_COMMAND, &cmd); if ((cmd & (PCI_COMMAND_IO|PCI_COMMAND_MEMORY)) == (PCI_COMMAND_IO|PCI_COMMAND_MEMORY)) { - vga_wseq (NULL, CL_SEQR6, 0x12); /* unlock all extension registers */ - vga_wseq (NULL, CL_SEQRF, 0x18); + vga_wseq(NULL, CL_SEQR6, 0x12); /* unlock all extension registers */ + vga_wseq(NULL, CL_SEQRF, 0x18); } } diff --git a/arch/mips/sni/sniprom.c b/arch/mips/sni/sniprom.c index db544a6..11eddd4 100644 --- a/arch/mips/sni/sniprom.c +++ b/arch/mips/sni/sniprom.c @@ -45,7 +45,7 @@ void prom_putchar(char c) static char *(*__prom_getenv)(char *) = (char *(*)(char *))PROM_ENTRY(PROM_GETENV); static void (*__prom_get_memconf)(void *) = (void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF); -char *prom_getenv (char *s) +char *prom_getenv(char *s) { return __prom_getenv(s); } @@ -131,9 +131,9 @@ static void __init sni_console_setup(void) int port; static char options[8]; - cdev = prom_getenv ("console_dev"); + cdev = prom_getenv("console_dev"); if (strncmp (cdev, "tty", 3) == 0) { - ctype = prom_getenv ("console"); + ctype = prom_getenv("console"); switch (*ctype) { default: case 'l': diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c index 153f065..b808773 100644 --- a/arch/mips/sni/time.c +++ b/arch/mips/sni/time.c @@ -44,23 +44,23 @@ static __init unsigned long dosample(void) volatile u8 msb, lsb; /* Start the counter. */ - outb_p (0x34, 0x43); + outb_p(0x34, 0x43); outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40); - outb (SNI_8254_TCSAMP_COUNTER >> 8, 0x40); + outb(SNI_8254_TCSAMP_COUNTER >> 8, 0x40); /* Get initial counter invariant */ ct0 = read_c0_count(); /* Latch and spin until top byte of counter0 is zero */ do { - outb (0x00, 0x43); - lsb = inb (0x40); - msb = inb (0x40); + outb(0x00, 0x43); + lsb = inb(0x40); + msb = inb(0x40); ct1 = read_c0_count(); } while (msb); /* Stop the counter. */ - outb (0x38, 0x43); + outb(0x38, 0x43); /* * Return the difference, this is how far the r4k counter increments * for every 1/HZ seconds. We round off the nearest 1 MHz of master @@ -137,7 +137,7 @@ void __init plat_timer_setup(struct irqaction *irq) case SNI_BRD_10NEW: case SNI_BRD_TOWER_OASIC: case SNI_BRD_MINITOWER: - sni_a20r_timer_setup (irq); + sni_a20r_timer_setup(irq); break; case SNI_BRD_PCI_TOWER: @@ -146,7 +146,7 @@ void __init plat_timer_setup(struct irqaction *irq) case SNI_BRD_PCI_DESKTOP: case SNI_BRD_PCI_TOWER_CPLUS: case SNI_BRD_PCI_MTOWER_CPLUS: - sni_cpu_timer_setup (irq); + sni_cpu_timer_setup(irq); break; } } diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h index c5f20df..7a88175 100644 --- a/include/asm-mips/asmmacro.h +++ b/include/asm-mips/asmmacro.h @@ -56,27 +56,27 @@ * Temporary until all gas have MT ASE support */ .macro DMT reg=0 - .word (0x41600bc1 | (\reg << 16)) + .word 0x41600bc1 | (\reg << 16) .endm .macro EMT reg=0 - .word (0x41600be1 | (\reg << 16)) + .word 0x41600be1 | (\reg << 16) .endm .macro DVPE reg=0 - .word (0x41600001 | (\reg << 16)) + .word 0x41600001 | (\reg << 16) .endm .macro EVPE reg=0 - .word (0x41600021 | (\reg << 16)) + .word 0x41600021 | (\reg << 16) .endm .macro MFTR rt=0, rd=0, u=0, sel=0 - .word (0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) + .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) .endm .macro MTTR rt=0, rd=0, u=0, sel=0 - .word (0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) + .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) .endm #endif /* _ASM_ASMMACRO_H */ diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 148bc79..899357a 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -19,14 +19,14 @@ #include #include -#if (_MIPS_SZLONG == 32) +#if _MIPS_SZLONG == 32 #define SZLONG_LOG 5 #define SZLONG_MASK 31UL #define __LL "ll " #define __SC "sc " #define __INS "ins " #define __EXT "ext " -#elif (_MIPS_SZLONG == 64) +#elif _MIPS_SZLONG == 64 #define SZLONG_LOG 6 #define SZLONG_MASK 63UL #define __LL "lld " @@ -461,7 +461,7 @@ static inline int __ilog2(unsigned long x) int lz; if (sizeof(x) == 4) { - __asm__ ( + __asm__( " .set push \n" " .set mips32 \n" " clz %0, %1 \n" @@ -474,7 +474,7 @@ static inline int __ilog2(unsigned long x) BUG_ON(sizeof(x) != 8); - __asm__ ( + __asm__( " .set push \n" " .set mips64 \n" " dclz %0, %1 \n" @@ -508,7 +508,7 @@ static inline unsigned long __ffs(unsigned long word) */ static inline int fls(int word) { - __asm__ ("clz %0, %1" : "=r" (word) : "r" (word)); + __asm__("clz %0, %1" : "=r" (word) : "r" (word)); return 32 - word; } @@ -516,7 +516,7 @@ static inline int fls(int word) #if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64) static inline int fls64(__u64 word) { - __asm__ ("dclz %0, %1" : "=r" (word) : "r" (word)); + __asm__("dclz %0, %1" : "=r" (word) : "r" (word)); return 64 - word; } diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h index eee83cb..fe7dc2d 100644 --- a/include/asm-mips/byteorder.h +++ b/include/asm-mips/byteorder.h @@ -65,9 +65,9 @@ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) #endif /* __GNUC__ */ -#if defined (__MIPSEB__) +#if defined(__MIPSEB__) # include -#elif defined (__MIPSEL__) +#elif defined(__MIPSEL__) # include #else # error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h index e7d95d4..766f91a 100644 --- a/include/asm-mips/elf.h +++ b/include/asm-mips/elf.h @@ -319,7 +319,7 @@ do { \ struct task_struct; extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs); -extern int dump_task_regs (struct task_struct *, elf_gregset_t *); +extern int dump_task_regs(struct task_struct *, elf_gregset_t *); extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); #define ELF_CORE_COPY_REGS(elf_regs, regs) \ diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h index 02c8a13..f27b96c 100644 --- a/include/asm-mips/fixmap.h +++ b/include/asm-mips/fixmap.h @@ -60,8 +60,8 @@ enum fixed_addresses { __end_of_fixed_addresses }; -extern void __set_fixmap (enum fixed_addresses idx, - unsigned long phys, pgprot_t flags); +extern void __set_fixmap(enum fixed_addresses idx, + unsigned long phys, pgprot_t flags); #define set_fixmap(idx, phys) \ __set_fixmap(idx, phys, PAGE_KERNEL) diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h index b623882..3e7e30d 100644 --- a/include/asm-mips/futex.h +++ b/include/asm-mips/futex.h @@ -75,7 +75,7 @@ } static inline int -futex_atomic_op_inuser (int encoded_op, int __user *uaddr) +futex_atomic_op_inuser(int encoded_op, int __user *uaddr) { int op = (encoded_op >> 28) & 7; int cmp = (encoded_op >> 24) & 15; diff --git a/include/asm-mips/inventory.h b/include/asm-mips/inventory.h index 92d90f7..cc88aed 100644 --- a/include/asm-mips/inventory.h +++ b/include/asm-mips/inventory.h @@ -17,8 +17,8 @@ typedef struct inventory_s { extern int inventory_items; -extern void add_to_inventory (int class, int type, int controller, int unit, int state); -extern int dump_inventory_to_user (void __user *userbuf, int size); +extern void add_to_inventory(int class, int type, int controller, int unit, int state); +extern int dump_inventory_to_user(void __user *userbuf, int size); extern int __init init_inventory(void); #endif /* __ASM_INVENTORY_H */ diff --git a/include/asm-mips/irqflags.h b/include/asm-mips/irqflags.h index e459fa0..881e886 100644 --- a/include/asm-mips/irqflags.h +++ b/include/asm-mips/irqflags.h @@ -16,7 +16,7 @@ #include #include -__asm__ ( +__asm__( " .macro raw_local_irq_enable \n" " .set push \n" " .set reorder \n" @@ -65,7 +65,7 @@ static inline void raw_local_irq_enable(void) * * Workaround: mask EXL bit of the result or place a nop before mfc0. */ -__asm__ ( +__asm__( " .macro raw_local_irq_disable\n" " .set push \n" " .set noat \n" @@ -96,7 +96,7 @@ static inline void raw_local_irq_disable(void) : "memory"); } -__asm__ ( +__asm__( " .macro raw_local_save_flags flags \n" " .set push \n" " .set reorder \n" @@ -113,7 +113,7 @@ __asm__ __volatile__( \ "raw_local_save_flags %0" \ : "=r" (x)) -__asm__ ( +__asm__( " .macro raw_local_irq_save result \n" " .set push \n" " .set reorder \n" @@ -145,7 +145,7 @@ __asm__ __volatile__( \ : /* no inputs */ \ : "memory") -__asm__ ( +__asm__( " .macro raw_local_irq_restore flags \n" " .set push \n" " .set noreorder \n" diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 58fca8a..10f613f 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -951,25 +951,25 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* Programmable Counters 0 and 1 */ #define SYS_BASE 0xB1900000 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) - #define SYS_CNTRL_E1S (1<<23) - #define SYS_CNTRL_T1S (1<<20) - #define SYS_CNTRL_M21 (1<<19) - #define SYS_CNTRL_M11 (1<<18) - #define SYS_CNTRL_M01 (1<<17) - #define SYS_CNTRL_C1S (1<<16) - #define SYS_CNTRL_BP (1<<14) - #define SYS_CNTRL_EN1 (1<<13) - #define SYS_CNTRL_BT1 (1<<12) - #define SYS_CNTRL_EN0 (1<<11) - #define SYS_CNTRL_BT0 (1<<10) - #define SYS_CNTRL_E0 (1<<8) - #define SYS_CNTRL_E0S (1<<7) - #define SYS_CNTRL_32S (1<<5) - #define SYS_CNTRL_T0S (1<<4) - #define SYS_CNTRL_M20 (1<<3) - #define SYS_CNTRL_M10 (1<<2) - #define SYS_CNTRL_M00 (1<<1) - #define SYS_CNTRL_C0S (1<<0) +# define SYS_CNTRL_E1S (1<<23) +# define SYS_CNTRL_T1S (1<<20) +# define SYS_CNTRL_M21 (1<<19) +# define SYS_CNTRL_M11 (1<<18) +# define SYS_CNTRL_M01 (1<<17) +# define SYS_CNTRL_C1S (1<<16) +# define SYS_CNTRL_BP (1<<14) +# define SYS_CNTRL_EN1 (1<<13) +# define SYS_CNTRL_BT1 (1<<12) +# define SYS_CNTRL_EN0 (1<<11) +# define SYS_CNTRL_BT0 (1<<10) +# define SYS_CNTRL_E0 (1<<8) +# define SYS_CNTRL_E0S (1<<7) +# define SYS_CNTRL_32S (1<<5) +# define SYS_CNTRL_T0S (1<<4) +# define SYS_CNTRL_M20 (1<<3) +# define SYS_CNTRL_M10 (1<<2) +# define SYS_CNTRL_M00 (1<<1) +# define SYS_CNTRL_C0S (1<<0) /* Programmable Counter 0 Registers */ #define SYS_TOYTRIM (SYS_BASE + 0) @@ -989,34 +989,34 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* I2S Controller */ #define I2S_DATA 0xB1000000 - #define I2S_DATA_MASK (0xffffff) +# define I2S_DATA_MASK (0xffffff) #define I2S_CONFIG 0xB1000004 - #define I2S_CONFIG_XU (1<<25) - #define I2S_CONFIG_XO (1<<24) - #define I2S_CONFIG_RU (1<<23) - #define I2S_CONFIG_RO (1<<22) - #define I2S_CONFIG_TR (1<<21) - #define I2S_CONFIG_TE (1<<20) - #define I2S_CONFIG_TF (1<<19) - #define I2S_CONFIG_RR (1<<18) - #define I2S_CONFIG_RE (1<<17) - #define I2S_CONFIG_RF (1<<16) - #define I2S_CONFIG_PD (1<<11) - #define I2S_CONFIG_LB (1<<10) - #define I2S_CONFIG_IC (1<<9) - #define I2S_CONFIG_FM_BIT 7 - #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) - #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) - #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) - #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) - #define I2S_CONFIG_TN (1<<6) - #define I2S_CONFIG_RN (1<<5) - #define I2S_CONFIG_SZ_BIT 0 - #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) +# define I2S_CONFIG_XU (1<<25) +# define I2S_CONFIG_XO (1<<24) +# define I2S_CONFIG_RU (1<<23) +# define I2S_CONFIG_RO (1<<22) +# define I2S_CONFIG_TR (1<<21) +# define I2S_CONFIG_TE (1<<20) +# define I2S_CONFIG_TF (1<<19) +# define I2S_CONFIG_RR (1<<18) +# define I2S_CONFIG_RE (1<<17) +# define I2S_CONFIG_RF (1<<16) +# define I2S_CONFIG_PD (1<<11) +# define I2S_CONFIG_LB (1<<10) +# define I2S_CONFIG_IC (1<<9) +# define I2S_CONFIG_FM_BIT 7 +# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) +# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) +# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) +# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) +# define I2S_CONFIG_TN (1<<6) +# define I2S_CONFIG_RN (1<<5) +# define I2S_CONFIG_SZ_BIT 0 +# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) #define I2S_CONTROL 0xB1000008 - #define I2S_CONTROL_D (1<<1) - #define I2S_CONTROL_CE (1<<0) +# define I2S_CONTROL_D (1<<1) +# define I2S_CONTROL_CE (1<<0) /* USB Host Controller */ #ifndef USB_OHCI_LEN @@ -1034,38 +1034,38 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define USBD_EP5RD 0xB0200014 #define USBD_INTEN 0xB0200018 #define USBD_INTSTAT 0xB020001C - #define USBDEV_INT_SOF (1<<12) - #define USBDEV_INT_HF_BIT 6 - #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) - #define USBDEV_INT_CMPLT_BIT 0 - #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) +# define USBDEV_INT_SOF (1<<12) +# define USBDEV_INT_HF_BIT 6 +# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) +# define USBDEV_INT_CMPLT_BIT 0 +# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) #define USBD_CONFIG 0xB0200020 #define USBD_EP0CS 0xB0200024 #define USBD_EP2CS 0xB0200028 #define USBD_EP3CS 0xB020002C #define USBD_EP4CS 0xB0200030 #define USBD_EP5CS 0xB0200034 - #define USBDEV_CS_SU (1<<14) - #define USBDEV_CS_NAK (1<<13) - #define USBDEV_CS_ACK (1<<12) - #define USBDEV_CS_BUSY (1<<11) - #define USBDEV_CS_TSIZE_BIT 1 - #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) - #define USBDEV_CS_STALL (1<<0) +# define USBDEV_CS_SU (1<<14) +# define USBDEV_CS_NAK (1<<13) +# define USBDEV_CS_ACK (1<<12) +# define USBDEV_CS_BUSY (1<<11) +# define USBDEV_CS_TSIZE_BIT 1 +# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) +# define USBDEV_CS_STALL (1<<0) #define USBD_EP0RDSTAT 0xB0200040 #define USBD_EP0WRSTAT 0xB0200044 #define USBD_EP2WRSTAT 0xB0200048 #define USBD_EP3WRSTAT 0xB020004C #define USBD_EP4RDSTAT 0xB0200050 #define USBD_EP5RDSTAT 0xB0200054 - #define USBDEV_FSTAT_FLUSH (1<<6) - #define USBDEV_FSTAT_UF (1<<5) - #define USBDEV_FSTAT_OF (1<<4) - #define USBDEV_FSTAT_FCNT_BIT 0 - #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) +# define USBDEV_FSTAT_FLUSH (1<<6) +# define USBDEV_FSTAT_UF (1<<5) +# define USBDEV_FSTAT_OF (1<<4) +# define USBDEV_FSTAT_FCNT_BIT 0 +# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) #define USBD_ENABLE 0xB0200058 - #define USBDEV_ENABLE (1<<1) - #define USBDEV_CE (1<<0) +# define USBDEV_ENABLE (1<<1) +# define USBDEV_CE (1<<0) #endif /* !CONFIG_SOC_AU1200 */ @@ -1073,55 +1073,55 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* 4 byte offsets from AU1000_ETH_BASE */ #define MAC_CONTROL 0x0 - #define MAC_RX_ENABLE (1<<2) - #define MAC_TX_ENABLE (1<<3) - #define MAC_DEF_CHECK (1<<5) - #define MAC_SET_BL(X) (((X)&0x3)<<6) - #define MAC_AUTO_PAD (1<<8) - #define MAC_DISABLE_RETRY (1<<10) - #define MAC_DISABLE_BCAST (1<<11) - #define MAC_LATE_COL (1<<12) - #define MAC_HASH_MODE (1<<13) - #define MAC_HASH_ONLY (1<<15) - #define MAC_PASS_ALL (1<<16) - #define MAC_INVERSE_FILTER (1<<17) - #define MAC_PROMISCUOUS (1<<18) - #define MAC_PASS_ALL_MULTI (1<<19) - #define MAC_FULL_DUPLEX (1<<20) - #define MAC_NORMAL_MODE 0 - #define MAC_INT_LOOPBACK (1<<21) - #define MAC_EXT_LOOPBACK (1<<22) - #define MAC_DISABLE_RX_OWN (1<<23) - #define MAC_BIG_ENDIAN (1<<30) - #define MAC_RX_ALL (1<<31) +# define MAC_RX_ENABLE (1<<2) +# define MAC_TX_ENABLE (1<<3) +# define MAC_DEF_CHECK (1<<5) +# define MAC_SET_BL(X) (((X)&0x3)<<6) +# define MAC_AUTO_PAD (1<<8) +# define MAC_DISABLE_RETRY (1<<10) +# define MAC_DISABLE_BCAST (1<<11) +# define MAC_LATE_COL (1<<12) +# define MAC_HASH_MODE (1<<13) +# define MAC_HASH_ONLY (1<<15) +# define MAC_PASS_ALL (1<<16) +# define MAC_INVERSE_FILTER (1<<17) +# define MAC_PROMISCUOUS (1<<18) +# define MAC_PASS_ALL_MULTI (1<<19) +# define MAC_FULL_DUPLEX (1<<20) +# define MAC_NORMAL_MODE 0 +# define MAC_INT_LOOPBACK (1<<21) +# define MAC_EXT_LOOPBACK (1<<22) +# define MAC_DISABLE_RX_OWN (1<<23) +# define MAC_BIG_ENDIAN (1<<30) +# define MAC_RX_ALL (1<<31) #define MAC_ADDRESS_HIGH 0x4 #define MAC_ADDRESS_LOW 0x8 #define MAC_MCAST_HIGH 0xC #define MAC_MCAST_LOW 0x10 #define MAC_MII_CNTRL 0x14 - #define MAC_MII_BUSY (1<<0) - #define MAC_MII_READ 0 - #define MAC_MII_WRITE (1<<1) - #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) - #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) +# define MAC_MII_BUSY (1<<0) +# define MAC_MII_READ 0 +# define MAC_MII_WRITE (1<<1) +# define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) +# define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) #define MAC_MII_DATA 0x18 #define MAC_FLOW_CNTRL 0x1C - #define MAC_FLOW_CNTRL_BUSY (1<<0) - #define MAC_FLOW_CNTRL_ENABLE (1<<1) - #define MAC_PASS_CONTROL (1<<2) - #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) +# define MAC_FLOW_CNTRL_BUSY (1<<0) +# define MAC_FLOW_CNTRL_ENABLE (1<<1) +# define MAC_PASS_CONTROL (1<<2) +# define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) #define MAC_VLAN1_TAG 0x20 #define MAC_VLAN2_TAG 0x24 /* Ethernet Controller Enable */ - #define MAC_EN_CLOCK_ENABLE (1<<0) - #define MAC_EN_RESET0 (1<<1) - #define MAC_EN_TOSS (0<<2) - #define MAC_EN_CACHEABLE (1<<3) - #define MAC_EN_RESET1 (1<<4) - #define MAC_EN_RESET2 (1<<5) - #define MAC_DMA_RESET (1<<6) +# define MAC_EN_CLOCK_ENABLE (1<<0) +# define MAC_EN_RESET0 (1<<1) +# define MAC_EN_TOSS (0<<2) +# define MAC_EN_CACHEABLE (1<<3) +# define MAC_EN_RESET1 (1<<4) +# define MAC_EN_RESET2 (1<<5) +# define MAC_DMA_RESET (1<<6) /* Ethernet Controller DMA Channels */ @@ -1129,22 +1129,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define MAC1_TX_DMA_ADDR 0xB4004200 /* offsets from MAC_TX_RING_ADDR address */ #define MAC_TX_BUFF0_STATUS 0x0 - #define TX_FRAME_ABORTED (1<<0) - #define TX_JAB_TIMEOUT (1<<1) - #define TX_NO_CARRIER (1<<2) - #define TX_LOSS_CARRIER (1<<3) - #define TX_EXC_DEF (1<<4) - #define TX_LATE_COLL_ABORT (1<<5) - #define TX_EXC_COLL (1<<6) - #define TX_UNDERRUN (1<<7) - #define TX_DEFERRED (1<<8) - #define TX_LATE_COLL (1<<9) - #define TX_COLL_CNT_MASK (0xF<<10) - #define TX_PKT_RETRY (1<<31) +# define TX_FRAME_ABORTED (1<<0) +# define TX_JAB_TIMEOUT (1<<1) +# define TX_NO_CARRIER (1<<2) +# define TX_LOSS_CARRIER (1<<3) +# define TX_EXC_DEF (1<<4) +# define TX_LATE_COLL_ABORT (1<<5) +# define TX_EXC_COLL (1<<6) +# define TX_UNDERRUN (1<<7) +# define TX_DEFERRED (1<<8) +# define TX_LATE_COLL (1<<9) +# define TX_COLL_CNT_MASK (0xF<<10) +# define TX_PKT_RETRY (1<<31) #define MAC_TX_BUFF0_ADDR 0x4 - #define TX_DMA_ENABLE (1<<0) - #define TX_T_DONE (1<<1) - #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) +# define TX_DMA_ENABLE (1<<0) +# define TX_T_DONE (1<<1) +# define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) #define MAC_TX_BUFF0_LEN 0x8 #define MAC_TX_BUFF1_STATUS 0x10 #define MAC_TX_BUFF1_ADDR 0x14 @@ -1160,34 +1160,34 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define MAC1_RX_DMA_ADDR 0xB4004300 /* offsets from MAC_RX_RING_ADDR */ #define MAC_RX_BUFF0_STATUS 0x0 - #define RX_FRAME_LEN_MASK 0x3fff - #define RX_WDOG_TIMER (1<<14) - #define RX_RUNT (1<<15) - #define RX_OVERLEN (1<<16) - #define RX_COLL (1<<17) - #define RX_ETHER (1<<18) - #define RX_MII_ERROR (1<<19) - #define RX_DRIBBLING (1<<20) - #define RX_CRC_ERROR (1<<21) - #define RX_VLAN1 (1<<22) - #define RX_VLAN2 (1<<23) - #define RX_LEN_ERROR (1<<24) - #define RX_CNTRL_FRAME (1<<25) - #define RX_U_CNTRL_FRAME (1<<26) - #define RX_MCAST_FRAME (1<<27) - #define RX_BCAST_FRAME (1<<28) - #define RX_FILTER_FAIL (1<<29) - #define RX_PACKET_FILTER (1<<30) - #define RX_MISSED_FRAME (1<<31) - - #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ +# define RX_FRAME_LEN_MASK 0x3fff +# define RX_WDOG_TIMER (1<<14) +# define RX_RUNT (1<<15) +# define RX_OVERLEN (1<<16) +# define RX_COLL (1<<17) +# define RX_ETHER (1<<18) +# define RX_MII_ERROR (1<<19) +# define RX_DRIBBLING (1<<20) +# define RX_CRC_ERROR (1<<21) +# define RX_VLAN1 (1<<22) +# define RX_VLAN2 (1<<23) +# define RX_LEN_ERROR (1<<24) +# define RX_CNTRL_FRAME (1<<25) +# define RX_U_CNTRL_FRAME (1<<26) +# define RX_MCAST_FRAME (1<<27) +# define RX_BCAST_FRAME (1<<28) +# define RX_FILTER_FAIL (1<<29) +# define RX_PACKET_FILTER (1<<30) +# define RX_MISSED_FRAME (1<<31) + +# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) #define MAC_RX_BUFF0_ADDR 0x4 - #define RX_DMA_ENABLE (1<<0) - #define RX_T_DONE (1<<1) - #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) - #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) +# define RX_DMA_ENABLE (1<<0) +# define RX_T_DONE (1<<1) +# define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) +# define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) #define MAC_RX_BUFF1_STATUS 0x10 #define MAC_RX_BUFF1_ADDR 0x14 #define MAC_RX_BUFF2_STATUS 0x20 @@ -1298,44 +1298,44 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* SSIO */ #define SSI0_STATUS 0xB1600000 - #define SSI_STATUS_BF (1<<4) - #define SSI_STATUS_OF (1<<3) - #define SSI_STATUS_UF (1<<2) - #define SSI_STATUS_D (1<<1) - #define SSI_STATUS_B (1<<0) +# define SSI_STATUS_BF (1<<4) +# define SSI_STATUS_OF (1<<3) +# define SSI_STATUS_UF (1<<2) +# define SSI_STATUS_D (1<<1) +# define SSI_STATUS_B (1<<0) #define SSI0_INT 0xB1600004 - #define SSI_INT_OI (1<<3) - #define SSI_INT_UI (1<<2) - #define SSI_INT_DI (1<<1) +# define SSI_INT_OI (1<<3) +# define SSI_INT_UI (1<<2) +# define SSI_INT_DI (1<<1) #define SSI0_INT_ENABLE 0xB1600008 - #define SSI_INTE_OIE (1<<3) - #define SSI_INTE_UIE (1<<2) - #define SSI_INTE_DIE (1<<1) +# define SSI_INTE_OIE (1<<3) +# define SSI_INTE_UIE (1<<2) +# define SSI_INTE_DIE (1<<1) #define SSI0_CONFIG 0xB1600020 - #define SSI_CONFIG_AO (1<<24) - #define SSI_CONFIG_DO (1<<23) - #define SSI_CONFIG_ALEN_BIT 20 - #define SSI_CONFIG_ALEN_MASK (0x7<<20) - #define SSI_CONFIG_DLEN_BIT 16 - #define SSI_CONFIG_DLEN_MASK (0x7<<16) - #define SSI_CONFIG_DD (1<<11) - #define SSI_CONFIG_AD (1<<10) - #define SSI_CONFIG_BM_BIT 8 - #define SSI_CONFIG_BM_MASK (0x3<<8) - #define SSI_CONFIG_CE (1<<7) - #define SSI_CONFIG_DP (1<<6) - #define SSI_CONFIG_DL (1<<5) - #define SSI_CONFIG_EP (1<<4) +# define SSI_CONFIG_AO (1<<24) +# define SSI_CONFIG_DO (1<<23) +# define SSI_CONFIG_ALEN_BIT 20 +# define SSI_CONFIG_ALEN_MASK (0x7<<20) +# define SSI_CONFIG_DLEN_BIT 16 +# define SSI_CONFIG_DLEN_MASK (0x7<<16) +# define SSI_CONFIG_DD (1<<11) +# define SSI_CONFIG_AD (1<<10) +# define SSI_CONFIG_BM_BIT 8 +# define SSI_CONFIG_BM_MASK (0x3<<8) +# define SSI_CONFIG_CE (1<<7) +# define SSI_CONFIG_DP (1<<6) +# define SSI_CONFIG_DL (1<<5) +# define SSI_CONFIG_EP (1<<4) #define SSI0_ADATA 0xB1600024 - #define SSI_AD_D (1<<24) - #define SSI_AD_ADDR_BIT 16 - #define SSI_AD_ADDR_MASK (0xff<<16) - #define SSI_AD_DATA_BIT 0 - #define SSI_AD_DATA_MASK (0xfff<<0) +# define SSI_AD_D (1<<24) +# define SSI_AD_ADDR_BIT 16 +# define SSI_AD_ADDR_MASK (0xff<<16) +# define SSI_AD_DATA_BIT 0 +# define SSI_AD_DATA_MASK (0xfff<<0) #define SSI0_CLKDIV 0xB1600028 #define SSI0_CONTROL 0xB1600100 - #define SSI_CONTROL_CD (1<<1) - #define SSI_CONTROL_E (1<<0) +# define SSI_CONTROL_CD (1<<1) +# define SSI_CONTROL_E (1<<0) /* SSI1 */ #define SSI1_STATUS 0xB1680000 @@ -1401,75 +1401,75 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) #define IR_INT_CLEAR (IRDA_BASE+0x18) #define IR_CONFIG_1 (IRDA_BASE+0x20) - #define IR_RX_INVERT_LED (1<<0) - #define IR_TX_INVERT_LED (1<<1) - #define IR_ST (1<<2) - #define IR_SF (1<<3) - #define IR_SIR (1<<4) - #define IR_MIR (1<<5) - #define IR_FIR (1<<6) - #define IR_16CRC (1<<7) - #define IR_TD (1<<8) - #define IR_RX_ALL (1<<9) - #define IR_DMA_ENABLE (1<<10) - #define IR_RX_ENABLE (1<<11) - #define IR_TX_ENABLE (1<<12) - #define IR_LOOPBACK (1<<14) - #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ +# define IR_RX_INVERT_LED (1<<0) +# define IR_TX_INVERT_LED (1<<1) +# define IR_ST (1<<2) +# define IR_SF (1<<3) +# define IR_SIR (1<<4) +# define IR_MIR (1<<5) +# define IR_FIR (1<<6) +# define IR_16CRC (1<<7) +# define IR_TD (1<<8) +# define IR_RX_ALL (1<<9) +# define IR_DMA_ENABLE (1<<10) +# define IR_RX_ENABLE (1<<11) +# define IR_TX_ENABLE (1<<12) +# define IR_LOOPBACK (1<<14) +# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) #define IR_SIR_FLAGS (IRDA_BASE+0x24) #define IR_ENABLE (IRDA_BASE+0x28) - #define IR_RX_STATUS (1<<9) - #define IR_TX_STATUS (1<<10) +# define IR_RX_STATUS (1<<9) +# define IR_TX_STATUS (1<<10) #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) #define IR_MAX_PKT_LEN (IRDA_BASE+0x34) #define IR_RX_BYTE_CNT (IRDA_BASE+0x38) #define IR_CONFIG_2 (IRDA_BASE+0x3C) - #define IR_MODE_INV (1<<0) - #define IR_ONE_PIN (1<<1) +# define IR_MODE_INV (1<<0) +# define IR_ONE_PIN (1<<1) #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) /* GPIO */ #define SYS_PINFUNC 0xB190002C - #define SYS_PF_USB (1<<15) /* 2nd USB device/host */ - #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ - #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ - #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ - #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ - #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ - #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ - #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ - #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ - #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ - #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ - #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ - #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ - #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ - #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ - #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ +# define SYS_PF_USB (1<<15) /* 2nd USB device/host */ +# define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ +# define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ +# define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ +# define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ +# define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ +# define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ +# define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ +# define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ +# define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ +# define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ +# define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ +# define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ +# define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ +# define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ +# define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ /* Au1100 Only */ - #define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ - #define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ - #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ - #define SYS_PF_EX0 (1<<9) /* gpio2/clock */ +# define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ +# define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ +# define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ +# define SYS_PF_EX0 (1<<9) /* gpio2/clock */ /* Au1550 Only. Redefines lots of pins */ - #define SYS_PF_PSC2_MASK (7 << 17) - #define SYS_PF_PSC2_AC97 (0) - #define SYS_PF_PSC2_SPI (0) - #define SYS_PF_PSC2_I2S (1 << 17) - #define SYS_PF_PSC2_SMBUS (3 << 17) - #define SYS_PF_PSC2_GPIO (7 << 17) - #define SYS_PF_PSC3_MASK (7 << 20) - #define SYS_PF_PSC3_AC97 (0) - #define SYS_PF_PSC3_SPI (0) - #define SYS_PF_PSC3_I2S (1 << 20) - #define SYS_PF_PSC3_SMBUS (3 << 20) - #define SYS_PF_PSC3_GPIO (7 << 20) - #define SYS_PF_PSC1_S1 (1 << 1) - #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) +# define SYS_PF_PSC2_MASK (7 << 17) +# define SYS_PF_PSC2_AC97 (0) +# define SYS_PF_PSC2_SPI (0) +# define SYS_PF_PSC2_I2S (1 << 17) +# define SYS_PF_PSC2_SMBUS (3 << 17) +# define SYS_PF_PSC2_GPIO (7 << 17) +# define SYS_PF_PSC3_MASK (7 << 20) +# define SYS_PF_PSC3_AC97 (0) +# define SYS_PF_PSC3_SPI (0) +# define SYS_PF_PSC3_I2S (1 << 20) +# define SYS_PF_PSC3_SMBUS (3 << 20) +# define SYS_PF_PSC3_GPIO (7 << 20) +# define SYS_PF_PSC1_S1 (1 << 1) +# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) /* Au1200 Only */ #ifdef CONFIG_SOC_AU1200 @@ -1530,104 +1530,104 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* Clock Controller */ #define SYS_FREQCTRL0 0xB1900020 - #define SYS_FC_FRDIV2_BIT 22 - #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) - #define SYS_FC_FE2 (1<<21) - #define SYS_FC_FS2 (1<<20) - #define SYS_FC_FRDIV1_BIT 12 - #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) - #define SYS_FC_FE1 (1<<11) - #define SYS_FC_FS1 (1<<10) - #define SYS_FC_FRDIV0_BIT 2 - #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) - #define SYS_FC_FE0 (1<<1) - #define SYS_FC_FS0 (1<<0) +# define SYS_FC_FRDIV2_BIT 22 +# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) +# define SYS_FC_FE2 (1<<21) +# define SYS_FC_FS2 (1<<20) +# define SYS_FC_FRDIV1_BIT 12 +# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) +# define SYS_FC_FE1 (1<<11) +# define SYS_FC_FS1 (1<<10) +# define SYS_FC_FRDIV0_BIT 2 +# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) +# define SYS_FC_FE0 (1<<1) +# define SYS_FC_FS0 (1<<0) #define SYS_FREQCTRL1 0xB1900024 - #define SYS_FC_FRDIV5_BIT 22 - #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) - #define SYS_FC_FE5 (1<<21) - #define SYS_FC_FS5 (1<<20) - #define SYS_FC_FRDIV4_BIT 12 - #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) - #define SYS_FC_FE4 (1<<11) - #define SYS_FC_FS4 (1<<10) - #define SYS_FC_FRDIV3_BIT 2 - #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) - #define SYS_FC_FE3 (1<<1) - #define SYS_FC_FS3 (1<<0) +# define SYS_FC_FRDIV5_BIT 22 +# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) +# define SYS_FC_FE5 (1<<21) +# define SYS_FC_FS5 (1<<20) +# define SYS_FC_FRDIV4_BIT 12 +# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) +# define SYS_FC_FE4 (1<<11) +# define SYS_FC_FS4 (1<<10) +# define SYS_FC_FRDIV3_BIT 2 +# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) +# define SYS_FC_FE3 (1<<1) +# define SYS_FC_FS3 (1<<0) #define SYS_CLKSRC 0xB1900028 - #define SYS_CS_ME1_BIT 27 - #define SYS_CS_ME1_MASK (0x7<count, val); init_waitqueue_head(&sem->wait); } -static inline void init_MUTEX (struct semaphore *sem) +static inline void init_MUTEX(struct semaphore *sem) { sema_init(sem, 1); } -static inline void init_MUTEX_LOCKED (struct semaphore *sem) +static inline void init_MUTEX_LOCKED(struct semaphore *sem) { sema_init(sem, 0); } diff --git a/include/asm-mips/sim.h b/include/asm-mips/sim.h index 67c4fe5..0cd719f 100644 --- a/include/asm-mips/sim.h +++ b/include/asm-mips/sim.h @@ -18,7 +18,7 @@ #ifdef CONFIG_32BIT #define save_static_function(symbol) \ -__asm__ ( \ +__asm__( \ ".text\n\t" \ ".globl\t" #symbol "\n\t" \ ".align\t2\n\t" \ @@ -46,7 +46,7 @@ __asm__ ( \ #ifdef CONFIG_64BIT #define save_static_function(symbol) \ -__asm__ ( \ +__asm__( \ ".text\n\t" \ ".globl\t" #symbol "\n\t" \ ".align\t2\n\t" \ diff --git a/include/asm-mips/sn/addrs.h b/include/asm-mips/sn/addrs.h index 8fa0af6..6aa0868 100644 --- a/include/asm-mips/sn/addrs.h +++ b/include/asm-mips/sn/addrs.h @@ -50,7 +50,7 @@ #define TO_NODE_ADDRSPACE(_pa) (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK) #define CHANGE_ADDR_NASID(_pa, _nasid) \ - ((UINT64_CAST (_pa) & ~NASID_MASK) | \ + ((UINT64_CAST(_pa) & ~NASID_MASK) | \ (UINT64_CAST(_nasid) << NASID_SHFT)) @@ -75,7 +75,7 @@ #define RAW_NODE_SWIN_BASE(nasid, widget) \ - (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) + (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS)) #define WIDGETID_GET(addr) ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff)) @@ -192,21 +192,21 @@ #define BDDIR_ENTRY_LO(_pa) ((HSPEC_BASE + \ NODE_ADDRSPACE_SIZE * 3 / 4 + \ 0x200) | \ - UINT64_CAST (_pa) & NASID_MASK | \ - UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ - UINT64_CAST (_pa) >> 3 & 0x1f << 4) + UINT64_CAST(_pa) & NASID_MASK | \ + UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \ + UINT64_CAST(_pa) >> 3 & 0x1f << 4) #define BDDIR_ENTRY_HI(_pa) ((HSPEC_BASE + \ NODE_ADDRSPACE_SIZE * 3 / 4 + \ 0x208) | \ - UINT64_CAST (_pa) & NASID_MASK | \ - UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ - UINT64_CAST (_pa) >> 3 & 0x1f << 4) + UINT64_CAST(_pa) & NASID_MASK | \ + UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \ + UINT64_CAST(_pa) >> 3 & 0x1f << 4) #define BDPRT_ENTRY(_pa, _rgn) ((HSPEC_BASE + \ NODE_ADDRSPACE_SIZE * 3 / 4) | \ - UINT64_CAST (_pa) & NASID_MASK | \ - UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ + UINT64_CAST(_pa) & NASID_MASK | \ + UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \ (_rgn) << 3) #define BDPRT_ENTRY_ADDR(_pa,_rgn) (BDPRT_ENTRY((_pa),(_rgn))) #define BDPRT_ENTRY_S(_pa,_rgn,_val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))=(_val)) @@ -214,9 +214,9 @@ #define BDECC_ENTRY(_pa) ((HSPEC_BASE + \ NODE_ADDRSPACE_SIZE / 2) | \ - UINT64_CAST (_pa) & NASID_MASK | \ - UINT64_CAST (_pa) >> 2 & BDECC_UPPER_MASK | \ - UINT64_CAST (_pa) >> 3 & 3) + UINT64_CAST(_pa) & NASID_MASK | \ + UINT64_CAST(_pa) >> 2 & BDECC_UPPER_MASK | \ + UINT64_CAST(_pa) >> 3 & 3) /* * Macro to convert a back door directory or protection address into the @@ -225,16 +225,16 @@ #define BDADDR_IS_DIR(_ba) ((UINT64_CAST (_ba) & 0x200) != 0) #define BDADDR_IS_PRT(_ba) ((UINT64_CAST (_ba) & 0x200) == 0) -#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ - (UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2 | \ - (UINT64_CAST (_ba) & 0x1f << 4) << 3) +#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ + (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2 | \ + (UINT64_CAST(_ba) & 0x1f << 4) << 3) -#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ - (UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2) +#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ + (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2) -#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ - (UINT64_CAST (_ba) & BDECC_UPPER_MASK)<<2 | \ - (UINT64_CAST (_ba) & 3) << 3) +#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ + (UINT64_CAST(_ba) & BDECC_UPPER_MASK)<<2 | \ + (UINT64_CAST(_ba) & 3) << 3) #endif /* CONFIG_SGI_IP27 */ @@ -282,7 +282,7 @@ * the base of the register space. */ #define HUB_REG_PTR(_base, _off) \ - (HUBREG_CAST ((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) + (HUBREG_CAST((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) #define HUB_REG_PTR_L(_base, _off) \ HUB_L(HUB_REG_PTR((_base), (_off))) diff --git a/include/asm-mips/sn/io.h b/include/asm-mips/sn/io.h index ab2fa8c..24c6775 100644 --- a/include/asm-mips/sn/io.h +++ b/include/asm-mips/sn/io.h @@ -9,7 +9,7 @@ #ifndef _ASM_SN_IO_H #define _ASM_SN_IO_H -#if defined (CONFIG_SGI_IP27) +#if defined(CONFIG_SGI_IP27) #include #endif diff --git a/include/asm-mips/sn/kldir.h b/include/asm-mips/sn/kldir.h index 0573cbf..1327e12 100644 --- a/include/asm-mips/sn/kldir.h +++ b/include/asm-mips/sn/kldir.h @@ -140,7 +140,7 @@ */ #define SYMMON_STACK_SIZE 0x8000 -#if defined (PROM) +#if defined(PROM) /* * These defines are prom version dependent. No code other than the IP27 diff --git a/include/asm-mips/sn/sn0/addrs.h b/include/asm-mips/sn/sn0/addrs.h index 9e8cc52..b061900 100644 --- a/include/asm-mips/sn/sn0/addrs.h +++ b/include/asm-mips/sn/sn0/addrs.h @@ -91,7 +91,7 @@ : RAW_NODE_SWIN_BASE(nasid, widget)) #else /* __ASSEMBLY__ */ #define NODE_SWIN_BASE(nasid, widget) \ - (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) + (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS)) #endif /* __ASSEMBLY__ */ /* @@ -106,7 +106,7 @@ #define BWIN_WIDGET_MASK 0x7 #define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) #define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ - (UINT64_CAST (bigwin) << BWIN_SIZE_BITS)) + (UINT64_CAST(bigwin) << BWIN_SIZE_BITS)) #define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) #define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) @@ -259,7 +259,7 @@ * CACHE_ERR_SP_PTR could either contain an address to the stack, or * the stack could start at CACHE_ERR_SP_PTR */ -#if defined (HUB_ERR_STS_WAR) +#if defined(HUB_ERR_STS_WAR) #define CACHE_ERR_EFRAME 0x480 #else /* HUB_ERR_STS_WAR */ #define CACHE_ERR_EFRAME 0x400 @@ -275,7 +275,7 @@ #define _ARCSPROM -#if defined (HUB_ERR_STS_WAR) +#if defined(HUB_ERR_STS_WAR) #define ERR_STS_WAR_REGISTER IIO_IIBUSERR #define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR) diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h index ddaf36a..4d43dbb 100644 --- a/include/asm-mips/sni.h +++ b/include/asm-mips/sni.h @@ -194,17 +194,17 @@ extern unsigned int sni_brd_type; #define PCIMT_INT_ACKNOWLEDGE 0xba000000 /* board specific init functions */ -extern void sni_a20r_init (void); -extern void sni_pcit_init (void); -extern void sni_rm200_init (void); -extern void sni_pcimt_init (void); +extern void sni_a20r_init(void); +extern void sni_pcit_init(void); +extern void sni_rm200_init(void); +extern void sni_pcimt_init(void); /* board specific irq init functions */ -extern void sni_a20r_irq_init (void); -extern void sni_pcit_irq_init (void); -extern void sni_pcit_cplus_irq_init (void); -extern void sni_rm200_irq_init (void); -extern void sni_pcimt_irq_init (void); +extern void sni_a20r_irq_init(void); +extern void sni_pcit_irq_init(void); +extern void sni_pcit_cplus_irq_init(void); +extern void sni_rm200_irq_init(void); +extern void sni_pcimt_irq_init(void); /* timer inits */ extern void sni_cpu_time_init(void); diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 480b574..862f161 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -195,11 +195,11 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) -extern void set_handler (unsigned long offset, void *addr, unsigned long len); -extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len); +extern void set_handler(unsigned long offset, void *addr, unsigned long len); +extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len); typedef void (*vi_handler_t)(void); -extern void *set_vi_handler (int n, vi_handler_t addr); +extern void *set_vi_handler(int n, vi_handler_t addr); extern void *set_except_vector(int n, void *addr); extern unsigned long ebase; diff --git a/include/asm-mips/timex.h b/include/asm-mips/timex.h index b80de8e..87c68ae 100644 --- a/include/asm-mips/timex.h +++ b/include/asm-mips/timex.h @@ -48,7 +48,7 @@ typedef unsigned int cycles_t; -static inline cycles_t get_cycles (void) +static inline cycles_t get_cycles(void) { return read_c0_count(); } diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h index b255117..017dfb0 100644 --- a/include/asm-mips/uaccess.h +++ b/include/asm-mips/uaccess.h @@ -391,9 +391,9 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); #define __invoke_copy_to_user(to,from,n) \ ({ \ - register void __user *__cu_to_r __asm__ ("$4"); \ - register const void *__cu_from_r __asm__ ("$5"); \ - register long __cu_len_r __asm__ ("$6"); \ + register void __user *__cu_to_r __asm__("$4"); \ + register const void *__cu_from_r __asm__("$5"); \ + register long __cu_len_r __asm__("$6"); \ \ __cu_to_r = (to); \ __cu_from_r = (from); \ @@ -495,9 +495,9 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); #define __invoke_copy_from_user(to,from,n) \ ({ \ - register void *__cu_to_r __asm__ ("$4"); \ - register const void __user *__cu_from_r __asm__ ("$5"); \ - register long __cu_len_r __asm__ ("$6"); \ + register void *__cu_to_r __asm__("$4"); \ + register const void __user *__cu_from_r __asm__("$5"); \ + register long __cu_len_r __asm__("$6"); \ \ __cu_to_r = (to); \ __cu_from_r = (from); \ @@ -518,9 +518,9 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); #define __invoke_copy_from_user_inatomic(to,from,n) \ ({ \ - register void *__cu_to_r __asm__ ("$4"); \ - register const void __user *__cu_from_r __asm__ ("$5"); \ - register long __cu_len_r __asm__ ("$6"); \ + register void *__cu_to_r __asm__("$4"); \ + register const void __user *__cu_from_r __asm__("$5"); \ + register long __cu_len_r __asm__("$6"); \ \ __cu_to_r = (to); \ __cu_from_r = (from); \ -- cgit v0.10.2 From 21a151d8ca3aa74ee79f9791a9d4dc370d3e0636 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:15 +0100 Subject: [MIPS] checkfiles: Fix "need space after that ','" errors. Signed-off-by: Ralf Baechle diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c index d15b047..461cf01 100644 --- a/arch/mips/au1000/common/dbdma.c +++ b/arch/mips/au1000/common/dbdma.c @@ -213,7 +213,7 @@ au1xxx_ddma_add_device(dbdev_tab_t *dev) if ( NULL != p ) { memcpy(p, dev, sizeof(dbdev_tab_t)); - p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id); + p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id); ret = p->dev_id; new_id++; #if 0 @@ -671,7 +671,7 @@ _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags) * parts. If it is fixedin the future, these dma_cache_inv will just * be nothing more than empty macros. See io.h. * */ - dma_cache_inv((unsigned long)buf,nbytes); + dma_cache_inv((unsigned long)buf, nbytes); dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ au_sync(); dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); diff --git a/arch/mips/au1000/common/dbg_io.c b/arch/mips/au1000/common/dbg_io.c index 0a50af7..79e0b0a 100644 --- a/arch/mips/au1000/common/dbg_io.c +++ b/arch/mips/au1000/common/dbg_io.c @@ -53,7 +53,7 @@ typedef unsigned int uint32; /* memory-mapped read/write of the port */ #define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff) -#define UART16550_WRITE(y,z) (au_writel(z&0xff, DEBUG_BASE + y)) +#define UART16550_WRITE(y, z) (au_writel(z&0xff, DEBUG_BASE + y)) extern unsigned long get_au1x00_uart_baud_base(void); extern unsigned long cal_r4koff(void); diff --git a/arch/mips/au1000/common/power.c b/arch/mips/au1000/common/power.c index 3901e8e..6f57f72 100644 --- a/arch/mips/au1000/common/power.c +++ b/arch/mips/au1000/common/power.c @@ -211,7 +211,7 @@ int au_sleep(void) unsigned long wakeup, flags; extern void save_and_sleep(void); - spin_lock_irqsave(&pm_lock,flags); + spin_lock_irqsave(&pm_lock, flags); save_core_regs(); diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c index b73b2d1..7c708db 100644 --- a/arch/mips/au1000/pb1200/irqmap.c +++ b/arch/mips/au1000/pb1200/irqmap.c @@ -132,7 +132,7 @@ static void pb1200_shutdown_irq( unsigned int irq_nr ) pb1200_disable_irq(irq_nr); if (--pb1200_cascade_en == 0) { - free_irq(AU1000_GPIO_7,&pb1200_cascade_handler ); + free_irq(AU1000_GPIO_7, &pb1200_cascade_handler ); } return; } diff --git a/arch/mips/boot/addinitrd.c b/arch/mips/boot/addinitrd.c index 193e4be..b5b3feb 100644 --- a/arch/mips/boot/addinitrd.c +++ b/arch/mips/boot/addinitrd.c @@ -40,7 +40,7 @@ void die(char *s) int main(int argc, char *argv[]) { - int fd_vmlinux,fd_initrd,fd_outfile; + int fd_vmlinux, fd_initrd, fd_outfile; FILHDR efile; AOUTHDR eaout; SCNHDR esecs[3]; @@ -48,15 +48,15 @@ int main(int argc, char *argv[]) char buf[1024]; unsigned long loadaddr; unsigned long initrd_header[2]; - int i,cnt; + int i, cnt; int swab = 0; if (argc != 4) { - printf("Usage: %s \n",argv[0]); + printf("Usage: %s \n", argv[0]); exit(1); } - if ((fd_vmlinux = open (argv[1],O_RDONLY)) < 0) + if ((fd_vmlinux = open (argv[1], O_RDONLY)) < 0) die("open vmlinux"); if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile) die("read file header"); @@ -98,7 +98,7 @@ int main(int argc, char *argv[]) eaout.dsize = esecs[1].s_size = initrd_header[1] = SWAB(st.st_size+8); eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr); - if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC,0666)) < 0) + if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC, 0666)) < 0) die("open outfile"); if (write (fd_outfile, &efile, sizeof efile) != sizeof efile) die("write file header"); diff --git a/arch/mips/boot/elf2ecoff.c b/arch/mips/boot/elf2ecoff.c index c3543d9..c5a7f30 100644 --- a/arch/mips/boot/elf2ecoff.c +++ b/arch/mips/boot/elf2ecoff.c @@ -467,7 +467,7 @@ int main(int argc, char *argv[]) esecs[0].s_scnptr = N_TXTOFF(efh, eah); esecs[1].s_scnptr = N_DATOFF(efh, eah); #define ECOFF_SEGMENT_ALIGNMENT(a) 0x10 -#define ECOFF_ROUND(s,a) (((s)+(a)-1)&~((a)-1)) +#define ECOFF_ROUND(s, a) (((s)+(a)-1)&~((a)-1)) esecs[2].s_scnptr = esecs[1].s_scnptr + ECOFF_ROUND(esecs[1].s_size, ECOFF_SEGMENT_ALIGNMENT(&eah)); if (addflag) { diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c index 993f7ec..da41eac 100644 --- a/arch/mips/kernel/binfmt_elfo32.c +++ b/arch/mips/kernel/binfmt_elfo32.c @@ -110,7 +110,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value) } #undef ELF_CORE_COPY_REGS -#define ELF_CORE_COPY_REGS(_dest,_regs) elf32_core_copy_regs(_dest,_regs); +#define ELF_CORE_COPY_REGS(_dest, _regs) elf32_core_copy_regs(_dest, _regs); void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs) { diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c index 989d06c..c33f6f2 100644 --- a/arch/mips/kernel/gdb-stub.c +++ b/arch/mips/kernel/gdb-stub.c @@ -902,7 +902,7 @@ void handle_exception(struct gdb_regs *regs) hex2mem(ptr, (char *)®s->frame_ptr, 2*sizeof(long), 0, 0); ptr += 2*(2*sizeof(long)); hex2mem(ptr, (char *)®s->cp0_index, 16*sizeof(long), 0, 0); - strcpy(output_buffer,"OK"); + strcpy(output_buffer, "OK"); } break; @@ -919,7 +919,7 @@ void handle_exception(struct gdb_regs *regs) break; strcpy(output_buffer, "E03"); } else - strcpy(output_buffer,"E01"); + strcpy(output_buffer, "E01"); break; /* @@ -996,7 +996,7 @@ void handle_exception(struct gdb_regs *regs) ptr = &input_buffer[1]; if (!hexToInt(&ptr, &baudrate)) { - strcpy(output_buffer,"B01"); + strcpy(output_buffer, "B01"); break; } @@ -1015,7 +1015,7 @@ void handle_exception(struct gdb_regs *regs) break; default: baudrate = 0; - strcpy(output_buffer,"B02"); + strcpy(output_buffer, "B02"); goto x1; } diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index a860b21..4710135 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c @@ -127,14 +127,14 @@ static inline int i8259A_irq_real(unsigned int irq) int irqmask = 1 << irq; if (irq < 8) { - outb(0x0B,PIC_MASTER_CMD); /* ISR register */ + outb(0x0B, PIC_MASTER_CMD); /* ISR register */ value = inb(PIC_MASTER_CMD) & irqmask; - outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */ + outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */ return value; } - outb(0x0B,PIC_SLAVE_CMD); /* ISR register */ + outb(0x0B, PIC_SLAVE_CMD); /* ISR register */ value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); - outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */ + outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */ return value; } @@ -175,12 +175,12 @@ handle_real_irq: if (irq & 8) { inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */ outb(cached_slave_mask, PIC_SLAVE_IMR); - outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */ - outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */ + outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */ + outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */ } else { inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */ outb(cached_master_mask, PIC_MASTER_IMR); - outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */ + outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */ } smtc_im_ack_irq(irq); spin_unlock_irqrestore(&i8259A_lock, flags); diff --git a/arch/mips/kernel/irixelf.c b/arch/mips/kernel/irixelf.c index e3b4b54..8ef5cf4 100644 --- a/arch/mips/kernel/irixelf.c +++ b/arch/mips/kernel/irixelf.c @@ -231,16 +231,16 @@ static unsigned long * create_irix_tables(char * p, int argc, int envc, sp -= argc+1; argv = sp; - __put_user((elf_addr_t)argc,--sp); + __put_user((elf_addr_t)argc, --sp); current->mm->arg_start = (unsigned long) p; while (argc-->0) { - __put_user((unsigned long)p,argv++); + __put_user((unsigned long)p, argv++); p += strlen_user(p); } __put_user((unsigned long) NULL, argv); current->mm->arg_end = current->mm->env_start = (unsigned long) p; while (envc-->0) { - __put_user((unsigned long)p,envp++); + __put_user((unsigned long)p, envp++); p += strlen_user(p); } __put_user((unsigned long) NULL, envp); @@ -831,7 +831,7 @@ static int load_irix_library(struct file *file) int retval; unsigned int bss; int error; - int i,j, k; + int i, j, k; error = kernel_read(file, 0, (char *) &elf_ex, sizeof(elf_ex)); if (error != sizeof(elf_ex)) diff --git a/arch/mips/kernel/irixsig.c b/arch/mips/kernel/irixsig.c index 28b2a8f..85c2e38 100644 --- a/arch/mips/kernel/irixsig.c +++ b/arch/mips/kernel/irixsig.c @@ -163,9 +163,9 @@ static inline int handle_signal(unsigned long sig, siginfo_t *info, ret = setup_irix_frame(ka, regs, sig, oldset); spin_lock_irq(¤t->sighand->siglock); - sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); + sigorsets(¤t->blocked, ¤t->blocked, &ka->sa.sa_mask); if (!(ka->sa.sa_flags & SA_NODEFER)) - sigaddset(¤t->blocked,sig); + sigaddset(¤t->blocked, sig); recalc_sigpending(); spin_unlock_irq(¤t->sighand->siglock); @@ -605,8 +605,8 @@ repeat: current->state = TASK_INTERRUPTIBLE; read_lock(&tasklist_lock); tsk = current; - list_for_each(_p,&tsk->children) { - p = list_entry(_p,struct task_struct,sibling); + list_for_each(_p, &tsk->children) { + p = list_entry(_p, struct task_struct, sibling); if ((type == IRIX_P_PID) && p->pid != pid) continue; if ((type == IRIX_P_PGID) && process_group(p) != pid) diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index a990aad..d06e9c9 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -93,7 +93,7 @@ int show_interrupts(struct seq_file *p, void *v) if (i == 0) { seq_printf(p, " "); for_each_online_cpu(j) - seq_printf(p, "CPU%d ",j); + seq_printf(p, "CPU%d ", j); seq_putc(p, '\n'); } @@ -102,7 +102,7 @@ int show_interrupts(struct seq_file *p, void *v) action = irq_desc[i].action; if (!action) goto skip; - seq_printf(p, "%3d: ",i); + seq_printf(p, "%3d: ", i); #ifndef CONFIG_SMP seq_printf(p, "%10u ", kstat_irqs(i)); #else diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c index 1ed1766..d2c2e00 100644 --- a/arch/mips/kernel/kspd.c +++ b/arch/mips/kernel/kspd.c @@ -239,7 +239,7 @@ void sp_work_handle_request(void) case MTSP_SYSCALL_GETTOD: memset(&tz, 0, sizeof(tz)); if ((ret.retval = sp_syscall(__NR_gettimeofday, (int)&tv, - (int)&tz, 0,0)) == 0) + (int)&tz, 0, 0)) == 0) ret.retval = tv.tv_sec; break; diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index a6de170..d6e0121 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c @@ -58,10 +58,10 @@ #define AA(__x) ((unsigned long)((int)__x)) #ifdef __MIPSEB__ -#define merge_64(r1,r2) ((((r1) & 0xffffffffUL) << 32) + ((r2) & 0xffffffffUL)) +#define merge_64(r1, r2) ((((r1) & 0xffffffffUL) << 32) + ((r2) & 0xffffffffUL)) #endif #ifdef __MIPSEL__ -#define merge_64(r1,r2) ((((r2) & 0xffffffffUL) << 32) + ((r1) & 0xffffffffUL)) +#define merge_64(r1, r2) ((((r2) & 0xffffffffUL) << 32) + ((r1) & 0xffffffffUL)) #endif /* @@ -96,7 +96,7 @@ int cp_compat_stat(struct kstat *stat, struct compat_stat __user *statbuf) #endif tmp.st_blocks = stat->blocks; tmp.st_blksize = stat->blksize; - return copy_to_user(statbuf,&tmp,sizeof(tmp)) ? -EFAULT : 0; + return copy_to_user(statbuf, &tmp, sizeof(tmp)) ? -EFAULT : 0; } asmlinkage unsigned long @@ -510,11 +510,11 @@ asmlinkage int sys32_ustat(dev_t dev, struct ustat32 __user * ubuf32) if (err) goto out; - memset(&tmp32,0,sizeof(struct ustat32)); + memset(&tmp32, 0, sizeof(struct ustat32)); tmp32.f_tfree = tmp.f_tfree; tmp32.f_tinode = tmp.f_tinode; - err = copy_to_user(ubuf32,&tmp32,sizeof(struct ustat32)) ? -EFAULT : 0; + err = copy_to_user(ubuf32, &tmp32, sizeof(struct ustat32)) ? -EFAULT : 0; out: return err; diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index 2a08ce4..a4e106c 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -613,9 +613,9 @@ static int handle_signal(unsigned long sig, siginfo_t *info, ret = current->thread.abi->setup_frame(ka, regs, sig, oldset); spin_lock_irq(¤t->sighand->siglock); - sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); + sigorsets(¤t->blocked, ¤t->blocked, &ka->sa.sa_mask); if (!(ka->sa.sa_flags & SA_NODEFER)) - sigaddset(¤t->blocked,sig); + sigaddset(¤t->blocked, sig); recalc_sigpending(); spin_unlock_irq(¤t->sighand->siglock); diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 7701828..4d91e2f 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -180,7 +180,7 @@ void __init sanitize_tlb_entries(void) static void smtc_configure_tlb(void) { - int i,tlbsiz,vpes; + int i, tlbsiz, vpes; unsigned long mvpconf0; unsigned long config1val; @@ -423,7 +423,7 @@ void mipsmt_prepare_cpus(void) * code. Leave it alone! */ if (tc != 0) { - smtc_tc_setup(vpe,tc, cpu); + smtc_tc_setup(vpe, tc, cpu); cpu++; } printk(" %d", tc); @@ -431,7 +431,7 @@ void mipsmt_prepare_cpus(void) } if (slop) { if (tc != 0) { - smtc_tc_setup(vpe,tc, cpu); + smtc_tc_setup(vpe, tc, cpu); cpu++; } printk(" %d", tc); diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index ef2c636..17c4374 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -245,7 +245,7 @@ asmlinkage int sys_olduname(struct oldold_utsname __user * name) if (!name) return -EFAULT; - if (!access_ok(VERIFY_WRITE,name,sizeof(struct oldold_utsname))) + if (!access_ok(VERIFY_WRITE, name, sizeof(struct oldold_utsname))) return -EFAULT; error = __copy_to_user(&name->sysname, &utsname()->sysname, diff --git a/arch/mips/kernel/sysirix.c b/arch/mips/kernel/sysirix.c index b502395..ee7790d 100644 --- a/arch/mips/kernel/sysirix.c +++ b/arch/mips/kernel/sysirix.c @@ -778,7 +778,7 @@ asmlinkage int irix_times(struct tms __user *tbuf) int err = 0; if (tbuf) { - if (!access_ok(VERIFY_WRITE,tbuf,sizeof *tbuf)) + if (!access_ok(VERIFY_WRITE, tbuf, sizeof *tbuf)) return -EFAULT; err = __put_user(current->utime, &tbuf->tms_utime); diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index 3c09b97..45077c4 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -1044,7 +1044,7 @@ static int getcwd(char *buff, int size) old_fs = get_fs(); set_fs(KERNEL_DS); - ret = sys_getcwd(buff,size); + ret = sys_getcwd(buff, size); set_fs(old_fs); diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index c44e9cc..b08fc65 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -178,24 +178,24 @@ static int isBranchInstr(mips_instruction * i) #define FR_BIT 0 #endif -#define SIFROMREG(si,x) ((si) = \ +#define SIFROMREG(si, x) ((si) = \ (xcp->cp0_status & FR_BIT) || !(x & 1) ? \ (int)ctx->fpr[x] : \ (int)(ctx->fpr[x & ~1] >> 32 )) -#define SITOREG(si,x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] = \ +#define SITOREG(si, x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] = \ (xcp->cp0_status & FR_BIT) || !(x & 1) ? \ ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \ ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32) -#define DIFROMREG(di,x) ((di) = \ +#define DIFROMREG(di, x) ((di) = \ ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)]) -#define DITOREG(di,x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] \ +#define DITOREG(di, x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] \ = (di)) -#define SPFROMREG(sp,x) SIFROMREG((sp).bits,x) -#define SPTOREG(sp,x) SITOREG((sp).bits,x) -#define DPFROMREG(dp,x) DIFROMREG((dp).bits,x) -#define DPTOREG(dp,x) DITOREG((dp).bits,x) +#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) +#define SPTOREG(sp, x) SITOREG((sp).bits, x) +#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) +#define DPTOREG(dp, x) DITOREG((dp).bits, x) /* * Emulate the single floating point instruction pointed at by EPC. @@ -584,12 +584,12 @@ static ieee754sp fpemu_sp_rsqrt(ieee754sp s) return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); } -DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add,); -DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub,); +DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); +DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); -DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add,); -DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub,); +DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); +DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); diff --git a/arch/mips/math-emu/dp_mul.c b/arch/mips/math-emu/dp_mul.c index f237390..48908a8 100644 --- a/arch/mips/math-emu/dp_mul.c +++ b/arch/mips/math-emu/dp_mul.c @@ -121,7 +121,7 @@ ieee754dp ieee754dp_mul(ieee754dp x, ieee754dp y) */ /* 32 * 32 => 64 */ -#define DPXMULT(x,y) ((u64)(x) * (u64)y) +#define DPXMULT(x, y) ((u64)(x) * (u64)y) { unsigned lxm = xm; diff --git a/arch/mips/math-emu/ieee754.c b/arch/mips/math-emu/ieee754.c index a93c45d..946aee3 100644 --- a/arch/mips/math-emu/ieee754.c +++ b/arch/mips/math-emu/ieee754.c @@ -47,13 +47,13 @@ #if (defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN) || defined(__MIPSEL__) -#define SPSTR(s,b,m) {m,b,s} -#define DPSTR(s,b,mh,ml) {ml,mh,b,s} +#define SPSTR(s, b, m) {m, b, s} +#define DPSTR(s, b, mh, ml) {ml, mh, b, s} #endif #ifdef __MIPSEB__ -#define SPSTR(s,b,m) {s,b,m} -#define DPSTR(s,b,mh,ml) {s,b,mh,ml} +#define SPSTR(s, b, m) {s, b, m} +#define DPSTR(s, b, mh, ml) {s, b, mh, ml} #endif const struct ieee754dp_konst __ieee754dp_spcvals[] = { @@ -65,7 +65,7 @@ const struct ieee754dp_konst __ieee754dp_spcvals[] = { DPSTR(1, 3 + DP_EBIAS, 0x40000, 0), /* - 10.0 */ DPSTR(0, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* + infinity */ DPSTR(1, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* - infinity */ - DPSTR(0,DP_EMAX+1+DP_EBIAS,0x7FFFF,0xFFFFFFFF), /* + indef quiet Nan */ + DPSTR(0, DP_EMAX+1+DP_EBIAS, 0x7FFFF, 0xFFFFFFFF), /* + indef quiet Nan */ DPSTR(0, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* + max */ DPSTR(1, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* - max */ DPSTR(0, DP_EMIN + DP_EBIAS, 0, 0), /* + min normal */ @@ -85,7 +85,7 @@ const struct ieee754sp_konst __ieee754sp_spcvals[] = { SPSTR(1, 3 + SP_EBIAS, 0x200000), /* - 10.0 */ SPSTR(0, SP_EMAX + 1 + SP_EBIAS, 0), /* + infinity */ SPSTR(1, SP_EMAX + 1 + SP_EBIAS, 0), /* - infinity */ - SPSTR(0,SP_EMAX+1+SP_EBIAS,0x3FFFFF), /* + indef quiet Nan */ + SPSTR(0, SP_EMAX+1+SP_EBIAS, 0x3FFFFF), /* + indef quiet Nan */ SPSTR(0, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* + max normal */ SPSTR(1, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* - max normal */ SPSTR(0, SP_EMIN + SP_EBIAS, 0), /* + min normal */ diff --git a/arch/mips/math-emu/ieee754dp.h b/arch/mips/math-emu/ieee754dp.h index a37370d..8977eb5 100644 --- a/arch/mips/math-emu/ieee754dp.h +++ b/arch/mips/math-emu/ieee754dp.h @@ -43,8 +43,8 @@ /* convert denormal to normalized with extended exponent */ #define DPDNORMx(m,e) \ while( (m >> DP_MBITS) == 0) { m <<= 1; e--; } -#define DPDNORMX DPDNORMx(xm,xe) -#define DPDNORMY DPDNORMx(ym,ye) +#define DPDNORMX DPDNORMx(xm, xe) +#define DPDNORMY DPDNORMx(ym, ye) static __inline ieee754dp builddp(int s, int bx, u64 m) { @@ -71,13 +71,13 @@ extern ieee754dp ieee754dp_bestnan(ieee754dp, ieee754dp); extern ieee754dp ieee754dp_format(int, int, u64); -#define DPNORMRET2(s,e,m,name,a0,a1) \ +#define DPNORMRET2(s, e, m, name, a0, a1) \ { \ - ieee754dp V = ieee754dp_format(s,e,m); \ + ieee754dp V = ieee754dp_format(s, e, m); \ if(TSTX()) \ - return ieee754dp_xcpt(V,name,a0,a1); \ + return ieee754dp_xcpt(V, name, a0, a1); \ else \ return V; \ } -#define DPNORMRET1(s,e,m,name,a0) DPNORMRET2(s,e,m,name,a0,a0) +#define DPNORMRET1(s, e, m, name, a0) DPNORMRET2(s, e, m, name, a0, a0) diff --git a/arch/mips/math-emu/ieee754int.h b/arch/mips/math-emu/ieee754int.h index 4a5a81d..1a846c5 100644 --- a/arch/mips/math-emu/ieee754int.h +++ b/arch/mips/math-emu/ieee754int.h @@ -55,16 +55,16 @@ #define DPBEXP(dp) (dp.parts.bexp) #define DPMANT(dp) (dp.parts.mant) -#define CLPAIR(x,y) ((x)*6+(y)) +#define CLPAIR(x, y) ((x)*6+(y)) #define CLEARCX \ (ieee754_csr.cx = 0) #define SETCX(x) \ - (ieee754_csr.cx |= (x),ieee754_csr.sx |= (x)) + (ieee754_csr.cx |= (x), ieee754_csr.sx |= (x)) #define SETANDTESTCX(x) \ - (SETCX(x),ieee754_csr.mx & (x)) + (SETCX(x), ieee754_csr.mx & (x)) #define TSTX() \ (ieee754_csr.cx & ieee754_csr.mx) @@ -76,7 +76,7 @@ #define COMPYSP \ unsigned ym; int ye; int ys; int yc -#define EXPLODESP(v,vc,vs,ve,vm) \ +#define EXPLODESP(v, vc, vs, ve, vm) \ {\ vs = SPSIGN(v);\ ve = SPBEXP(v);\ @@ -100,8 +100,8 @@ vc = IEEE754_CLASS_NORM;\ }\ } -#define EXPLODEXSP EXPLODESP(x,xc,xs,xe,xm) -#define EXPLODEYSP EXPLODESP(y,yc,ys,ye,ym) +#define EXPLODEXSP EXPLODESP(x, xc, xs, xe, xm) +#define EXPLODEYSP EXPLODESP(y, yc, ys, ye, ym) #define COMPXDP \ @@ -110,7 +110,7 @@ u64 xm; int xe; int xs; int xc #define COMPYDP \ u64 ym; int ye; int ys; int yc -#define EXPLODEDP(v,vc,vs,ve,vm) \ +#define EXPLODEDP(v, vc, vs, ve, vm) \ {\ vm = DPMANT(v);\ vs = DPSIGN(v);\ @@ -134,10 +134,10 @@ u64 ym; int ye; int ys; int yc vc = IEEE754_CLASS_NORM;\ }\ } -#define EXPLODEXDP EXPLODEDP(x,xc,xs,xe,xm) -#define EXPLODEYDP EXPLODEDP(y,yc,ys,ye,ym) +#define EXPLODEXDP EXPLODEDP(x, xc, xs, xe, xm) +#define EXPLODEYDP EXPLODEDP(y, yc, ys, ye, ym) -#define FLUSHDP(v,vc,vs,ve,vm) \ +#define FLUSHDP(v, vc, vs, ve, vm) \ if(vc==IEEE754_CLASS_DNORM) {\ if(ieee754_csr.nod) {\ SETCX(IEEE754_INEXACT);\ @@ -148,7 +148,7 @@ u64 ym; int ye; int ys; int yc }\ } -#define FLUSHSP(v,vc,vs,ve,vm) \ +#define FLUSHSP(v, vc, vs, ve, vm) \ if(vc==IEEE754_CLASS_DNORM) {\ if(ieee754_csr.nod) {\ SETCX(IEEE754_INEXACT);\ @@ -159,7 +159,7 @@ u64 ym; int ye; int ys; int yc }\ } -#define FLUSHXDP FLUSHDP(x,xc,xs,xe,xm) -#define FLUSHYDP FLUSHDP(y,yc,ys,ye,ym) -#define FLUSHXSP FLUSHSP(x,xc,xs,xe,xm) -#define FLUSHYSP FLUSHSP(y,yc,ys,ye,ym) +#define FLUSHXDP FLUSHDP(x, xc, xs, xe, xm) +#define FLUSHYDP FLUSHDP(y, yc, ys, ye, ym) +#define FLUSHXSP FLUSHSP(x, xc, xs, xe, xm) +#define FLUSHYSP FLUSHSP(y, yc, ys, ye, ym) diff --git a/arch/mips/math-emu/ieee754sp.h b/arch/mips/math-emu/ieee754sp.h index ae82f51..9917c1e 100644 --- a/arch/mips/math-emu/ieee754sp.h +++ b/arch/mips/math-emu/ieee754sp.h @@ -48,8 +48,8 @@ /* convert denormal to normalized with extended exponent */ #define SPDNORMx(m,e) \ while( (m >> SP_MBITS) == 0) { m <<= 1; e--; } -#define SPDNORMX SPDNORMx(xm,xe) -#define SPDNORMY SPDNORMx(ym,ye) +#define SPDNORMX SPDNORMx(xm, xe) +#define SPDNORMY SPDNORMx(ym, ye) static __inline ieee754sp buildsp(int s, int bx, unsigned m) { @@ -77,13 +77,13 @@ extern ieee754sp ieee754sp_bestnan(ieee754sp, ieee754sp); extern ieee754sp ieee754sp_format(int, int, unsigned); -#define SPNORMRET2(s,e,m,name,a0,a1) \ +#define SPNORMRET2(s, e, m, name, a0, a1) \ { \ - ieee754sp V = ieee754sp_format(s,e,m); \ + ieee754sp V = ieee754sp_format(s, e, m); \ if(TSTX()) \ - return ieee754sp_xcpt(V,name,a0,a1); \ + return ieee754sp_xcpt(V, name, a0, a1); \ else \ return V; \ } -#define SPNORMRET1(s,e,m,name,a0) SPNORMRET2(s,e,m,name,a0,a0) +#define SPNORMRET1(s, e, m, name, a0) SPNORMRET2(s, e, m, name, a0, a0) diff --git a/arch/mips/mips-boards/atlas/atlas_gdb.c b/arch/mips/mips-boards/atlas/atlas_gdb.c index fb65280..00c98cf 100644 --- a/arch/mips/mips-boards/atlas/atlas_gdb.c +++ b/arch/mips/mips-boards/atlas/atlas_gdb.c @@ -22,7 +22,7 @@ #include #define INB(a) inb((unsigned long)a) -#define OUTB(x,a) outb(x,(unsigned long)a) +#define OUTB(x, a) outb(x, (unsigned long)a) /* * This is the interface to the remote debugger stub diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c index 8232392..f010261 100644 --- a/arch/mips/mips-boards/malta/malta_int.c +++ b/arch/mips/mips-boards/malta/malta_int.c @@ -124,7 +124,7 @@ static void corehi_irqdispatch(void) { unsigned int intedge, intsteer, pcicmd, pcibadaddr; unsigned int pcimstat, intisr, inten, intpol; - unsigned int intrcause,datalo,datahi; + unsigned int intrcause, datalo, datahi; struct pt_regs *regs = get_irq_regs(); printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n"); diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c index e243d5e..9a2636e 100644 --- a/arch/mips/mips-boards/malta/malta_setup.c +++ b/arch/mips/mips-boards/malta/malta_setup.c @@ -176,7 +176,7 @@ void __init plat_mem_setup(void) 0, /* orig-video-page */ 0, /* orig-video-mode */ 80, /* orig-video-cols */ - 0,0,0, /* ega_ax, ega_bx, ega_cx */ + 0, 0, 0, /* ega_ax, ega_bx, ega_cx */ 25, /* orig-video-lines */ VIDEO_TYPE_VGAC, /* orig-video-isVGA */ 16 /* orig-video-points */ diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 8b7b7c5..971f6c0 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -164,12 +164,12 @@ static inline void tx49_blast_icache32(void) /* I'm in even chunk. blast odd chunks */ for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start + 0x400; addr < end; addr += 0x400 * 2) - cache32_unroll32(addr|ws,Index_Invalidate_I); + cache32_unroll32(addr|ws, Index_Invalidate_I); CACHE32_UNROLL32_ALIGN; /* I'm in odd chunk. blast even chunks */ for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x400 * 2) - cache32_unroll32(addr|ws,Index_Invalidate_I); + cache32_unroll32(addr|ws, Index_Invalidate_I); } static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) @@ -195,12 +195,12 @@ static inline void tx49_blast_icache32_page_indexed(unsigned long page) /* I'm in even chunk. blast odd chunks */ for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start + 0x400; addr < end; addr += 0x400 * 2) - cache32_unroll32(addr|ws,Index_Invalidate_I); + cache32_unroll32(addr|ws, Index_Invalidate_I); CACHE32_UNROLL32_ALIGN; /* I'm in odd chunk. blast even chunks */ for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x400 * 2) - cache32_unroll32(addr|ws,Index_Invalidate_I); + cache32_unroll32(addr|ws, Index_Invalidate_I); } static void (* r4k_blast_icache_page)(unsigned long addr); diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c index 4c72e65..e7f539e3 100644 --- a/arch/mips/mm/cerr-sb1.c +++ b/arch/mips/mm/cerr-sb1.c @@ -271,14 +271,22 @@ asmlinkage void sb1_cache_error(void) /* Parity lookup table. */ static const uint8_t parity[256] = { - 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, - 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, - 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, - 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, - 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, - 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, - 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, - 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0 + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0 }; /* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */ diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c index 82f42ac..a3e98c2 100644 --- a/arch/mips/mm/pg-sb1.c +++ b/arch/mips/mm/pg-sb1.c @@ -188,9 +188,9 @@ static inline void copy_page_cpu(void *to, void *from) : "+r" (src), "+r" (dst) : "r" (end) #ifdef CONFIG_64BIT - : "$8","$9","$10","$11","memory"); + : "$8", "$9", "$10", "$11", "memory"); #else - : "$2","$3","$6","$7","$8","$9","$10","$11","memory"); + : "$2", "$3", "$6", "$7", "$8", "$9", "$10", "$11", "memory"); #endif } diff --git a/arch/mips/mm/pgtable.c b/arch/mips/mm/pgtable.c index c93aa6c..57df1c3 100644 --- a/arch/mips/mm/pgtable.c +++ b/arch/mips/mm/pgtable.c @@ -29,9 +29,9 @@ void show_mem(void) shared += page_count(page) - 1; } printk("%d pages of RAM\n", total); - printk("%d pages of HIGHMEM\n",highmem); - printk("%d reserved pages\n",reserved); - printk("%d pages shared\n",shared); - printk("%d pages swap cached\n",cached); + printk("%d pages of HIGHMEM\n", highmem); + printk("%d reserved pages\n", reserved); + printk("%d pages shared\n", shared); + printk("%d pages swap cached\n", cached); #endif } diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c index 266a47d..bd8409d 100644 --- a/arch/mips/mm/tlb-r8k.c +++ b/arch/mips/mm/tlb-r8k.c @@ -56,7 +56,7 @@ void local_flush_tlb_mm(struct mm_struct *mm) int cpu = smp_processor_id(); if (cpu_context(cpu, mm) != 0) - drop_mmu_context(mm,cpu); + drop_mmu_context(mm, cpu); } void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index c3da4fe..a61246d 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -141,53 +141,53 @@ struct insn { | (f) << FUNC_SH) static __initdata struct insn insn_table[] = { - { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM }, - { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD }, - { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD }, - { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM }, - { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM }, - { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM }, - { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM }, - { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM }, - { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM }, - { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM }, - { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM }, - { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM }, - { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD }, - { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD | SET}, - { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD | SET}, - { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE }, - { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE }, - { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE }, - { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE }, - { insn_dsrl32, M(spec_op,0,0,0,0,dsrl32_op), RT | RD | RE }, - { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD }, - { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 }, - { insn_j, M(j_op,0,0,0,0,0), JIMM }, - { insn_jal, M(jal_op,0,0,0,0,0), JIMM }, - { insn_jr, M(spec_op,0,0,0,0,jr_op), RS }, - { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM }, - { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM }, - { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM }, - { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM }, - { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM }, - { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD | SET}, - { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD | SET}, - { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM }, - { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 }, - { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM }, - { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM }, - { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM }, - { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE }, - { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE }, - { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE }, - { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD }, - { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM }, - { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 }, - { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 }, - { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 }, - { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD }, - { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM }, + { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, + { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, + { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, + { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM }, + { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM }, + { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM }, + { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM }, + { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, + { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, + { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, + { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE }, + { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE }, + { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE }, + { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, + { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE }, + { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, + { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, + { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, + { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, + { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, + { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM }, + { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, + { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, + { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, + { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, + { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, + { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, + { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, + { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, + { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, + { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, + { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, + { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, + { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, { insn_invalid, 0, 0 } }; diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c index 2b4e30c..5443ea3 100644 --- a/arch/mips/pci/pci-bcm1480.c +++ b/arch/mips/pci/pci-bcm1480.c @@ -49,8 +49,8 @@ * Macros for calculating offsets into config space given a device * structure or dev/fun/reg */ -#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where)) -#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where) +#define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where)) +#define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where) static void *cfg_space; @@ -255,7 +255,7 @@ static int __init bcm1480_pcibios_init(void) register_pci_controller(&bcm1480_controller); #ifdef CONFIG_VGA_CONSOLE - take_over_console(&vga_con,0,MAX_NR_CONSOLES-1,1); + take_over_console(&vga_con, 0, MAX_NR_CONSOLES-1, 1); #endif return 0; } diff --git a/arch/mips/pci/pci-bcm1480ht.c b/arch/mips/pci/pci-bcm1480ht.c index ba2e34b..a63e3bd 100644 --- a/arch/mips/pci/pci-bcm1480ht.c +++ b/arch/mips/pci/pci-bcm1480ht.c @@ -48,8 +48,8 @@ * Macros for calculating offsets into config space given a device * structure or dev/fun/reg */ -#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where)) -#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where) +#define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where)) +#define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where) static void *ht_cfg_space; diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c index c1ac649..42e4d2c 100644 --- a/arch/mips/pci/pci-sb1250.c +++ b/arch/mips/pci/pci-sb1250.c @@ -49,8 +49,8 @@ * Macros for calculating offsets into config space given a device * structure or dev/fun/reg */ -#define CFGOFFSET(bus,devfn,where) (((bus)<<16) + ((devfn)<<8) + (where)) -#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where) +#define CFGOFFSET(bus, devfn, where) (((bus)<<16) + ((devfn)<<8) + (where)) +#define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where) static void *cfg_space; diff --git a/arch/mips/philips/pnx8550/common/proc.c b/arch/mips/philips/pnx8550/common/proc.c index 416f834..18b125e 100644 --- a/arch/mips/philips/pnx8550/common/proc.c +++ b/arch/mips/philips/pnx8550/common/proc.c @@ -33,14 +33,14 @@ static int pnx8550_timers_read(char* page, char** start, off_t offset, int count int configPR = read_c0_config7(); if (offset==0) { - len += sprintf(&page[len],"Timer: count, compare, tc, status\n"); - len += sprintf(&page[len]," 1: %11i, %8i, %1i, %s\n", + len += sprintf(&page[len], "Timer: count, compare, tc, status\n"); + len += sprintf(&page[len], " 1: %11i, %8i, %1i, %s\n", read_c0_count(), read_c0_compare(), (configPR>>6)&0x1, ((configPR>>3)&0x1)? "off":"on"); - len += sprintf(&page[len]," 2: %11i, %8i, %1i, %s\n", + len += sprintf(&page[len], " 2: %11i, %8i, %1i, %s\n", read_c0_count2(), read_c0_compare2(), (configPR>>7)&0x1, ((configPR>>4)&0x1)? "off":"on"); - len += sprintf(&page[len]," 3: %11i, %8i, %1i, %s\n", + len += sprintf(&page[len], " 3: %11i, %8i, %1i, %s\n", read_c0_count3(), read_c0_compare3(), (configPR>>8)&0x1, ((configPR>>5)&0x1)? "off":"on"); } @@ -53,18 +53,18 @@ static int pnx8550_registers_read(char* page, char** start, off_t offset, int co int len = 0; if (offset==0) { - len += sprintf(&page[len],"config1: %#10.8x\n",read_c0_config1()); - len += sprintf(&page[len],"config2: %#10.8x\n",read_c0_config2()); - len += sprintf(&page[len],"config3: %#10.8x\n",read_c0_config3()); - len += sprintf(&page[len],"configPR: %#10.8x\n",read_c0_config7()); - len += sprintf(&page[len],"status: %#10.8x\n",read_c0_status()); - len += sprintf(&page[len],"cause: %#10.8x\n",read_c0_cause()); - len += sprintf(&page[len],"count: %#10.8x\n",read_c0_count()); - len += sprintf(&page[len],"count_2: %#10.8x\n",read_c0_count2()); - len += sprintf(&page[len],"count_3: %#10.8x\n",read_c0_count3()); - len += sprintf(&page[len],"compare: %#10.8x\n",read_c0_compare()); - len += sprintf(&page[len],"compare_2: %#10.8x\n",read_c0_compare2()); - len += sprintf(&page[len],"compare_3: %#10.8x\n",read_c0_compare3()); + len += sprintf(&page[len], "config1: %#10.8x\n", read_c0_config1()); + len += sprintf(&page[len], "config2: %#10.8x\n", read_c0_config2()); + len += sprintf(&page[len], "config3: %#10.8x\n", read_c0_config3()); + len += sprintf(&page[len], "configPR: %#10.8x\n", read_c0_config7()); + len += sprintf(&page[len], "status: %#10.8x\n", read_c0_status()); + len += sprintf(&page[len], "cause: %#10.8x\n", read_c0_cause()); + len += sprintf(&page[len], "count: %#10.8x\n", read_c0_count()); + len += sprintf(&page[len], "count_2: %#10.8x\n", read_c0_count2()); + len += sprintf(&page[len], "count_3: %#10.8x\n", read_c0_count3()); + len += sprintf(&page[len], "compare: %#10.8x\n", read_c0_compare()); + len += sprintf(&page[len], "compare_2: %#10.8x\n", read_c0_compare2()); + len += sprintf(&page[len], "compare_3: %#10.8x\n", read_c0_compare3()); } return len; diff --git a/arch/mips/pmc-sierra/msp71xx/msp_serial.c b/arch/mips/pmc-sierra/msp71xx/msp_serial.c index e25bac5..15e7b80 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_serial.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_serial.c @@ -117,7 +117,7 @@ void __init msp_serial_setup(void) /* Initialize first serial port */ up.mapbase = MSP_UART0_BASE; - up.membase = ioremap_nocache(up.mapbase,MSP_UART_REG_LEN); + up.membase = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN); up.irq = MSP_INT_UART0; up.uartclk = uartclk; up.regshift = 2; @@ -145,9 +145,9 @@ void __init msp_serial_setup(void) if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) { if( mips_machtype == MACH_MSP4200_FPGA || mips_machtype == MACH_MSP7120_FPGA ) - initDebugPort(uartclk,19200); + initDebugPort(uartclk, 19200); else - initDebugPort(uartclk,57600); + initDebugPort(uartclk, 57600); } #endif break; @@ -157,7 +157,7 @@ void __init msp_serial_setup(void) } up.mapbase = MSP_UART1_BASE; - up.membase = ioremap_nocache(up.mapbase,MSP_UART_REG_LEN); + up.membase = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN); up.irq = MSP_INT_UART1; up.line = 1; up.private_data = (void*)UART1_STATUS_REG; diff --git a/arch/mips/pmc-sierra/yosemite/ht.c b/arch/mips/pmc-sierra/yosemite/ht.c index 1f7c999..6380662 100644 --- a/arch/mips/pmc-sierra/yosemite/ht.c +++ b/arch/mips/pmc-sierra/yosemite/ht.c @@ -115,7 +115,7 @@ static int titan_ht_config_read_word(struct pci_dev *device, u32 longswap(unsigned long l) { - unsigned char b1,b2,b3,b4; + unsigned char b1, b2, b3, b4; b1 = l&255; b2 = (l>>8)&255; diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c index 493777e..a70656d 100644 --- a/arch/mips/sgi-ip27/ip27-smp.c +++ b/arch/mips/sgi-ip27/ip27-smp.c @@ -176,7 +176,7 @@ void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) unsigned long gp = (unsigned long)task_thread_info(idle); unsigned long sp = __KSTK_TOS(idle); - LAUNCH_SLAVE(cputonasid(cpu),cputoslice(cpu), + LAUNCH_SLAVE(cputonasid(cpu), cputoslice(cpu), (launch_proc_t)MAPPED_KERN_RW_TO_K0(smp_bootstrap), 0, (void *) sp, (void *) gp); } diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c index cf979db..7aa79bf 100644 --- a/arch/mips/sibyte/bcm1480/irq.c +++ b/arch/mips/sibyte/bcm1480/irq.c @@ -289,7 +289,7 @@ int bcm1480_steal_irq(int irq) if (irq >= BCM1480_NR_IRQS) return -EINVAL; - spin_lock_irqsave(&desc->lock,flags); + spin_lock_irqsave(&desc->lock, flags); /* Don't allow sharing at all for these */ if (desc->action != NULL) retval = -EBUSY; @@ -297,7 +297,7 @@ int bcm1480_steal_irq(int irq) desc->action = &bcm1480_dummy_action; desc->depth = 0; } - spin_unlock_irqrestore(&desc->lock,flags); + spin_unlock_irqrestore(&desc->lock, flags); return 0; } @@ -431,8 +431,8 @@ void __init arch_init_irq(void) #include -#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) -#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) +#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg))) +#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg))) static void bcm1480_kgdb_interrupt(void) { diff --git a/arch/mips/sibyte/cfe/console.c b/arch/mips/sibyte/cfe/console.c index 7a4ecfc..81e3d54 100644 --- a/arch/mips/sibyte/cfe/console.c +++ b/arch/mips/sibyte/cfe/console.c @@ -14,7 +14,7 @@ static void cfe_console_write(struct console *cons, const char *str, { int i, last, written; - for (i=0,last=0; i= SB1250_NR_IRQS) return -EINVAL; - spin_lock_irqsave(&desc->lock,flags); + spin_lock_irqsave(&desc->lock, flags); /* Don't allow sharing at all for these */ if (desc->action != NULL) retval = -EBUSY; @@ -267,7 +267,7 @@ int sb1250_steal_irq(int irq) desc->action = &sb1250_dummy_action; desc->depth = 0; } - spin_unlock_irqrestore(&desc->lock,flags); + spin_unlock_irqrestore(&desc->lock, flags); return 0; } @@ -381,8 +381,8 @@ void __init arch_init_irq(void) #include -#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) -#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) +#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg))) +#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg))) static void sb1250_kgdb_interrupt(void) { diff --git a/arch/mips/sibyte/sb1250/prom.c b/arch/mips/sibyte/sb1250/prom.c index f07ad3b..cf8f6b3 100644 --- a/arch/mips/sibyte/sb1250/prom.c +++ b/arch/mips/sibyte/sb1250/prom.c @@ -66,7 +66,7 @@ static void prom_linux_exit(void) { #ifdef CONFIG_SMP if (smp_processor_id()) { - smp_call_function(prom_cpu0_exit,NULL,1,1); + smp_call_function(prom_cpu0_exit, NULL, 1, 1); } #endif while(1); diff --git a/arch/mips/sibyte/swarm/dbg_io.c b/arch/mips/sibyte/swarm/dbg_io.c index 75ce14c..b97ae30 100644 --- a/arch/mips/sibyte/swarm/dbg_io.c +++ b/arch/mips/sibyte/swarm/dbg_io.c @@ -37,8 +37,8 @@ static int duart_initialized = 0; /* 0: need to be init'ed by kgdb */ /* -------------------- END OF CONFIG --------------------- */ extern int kgdb_port; -#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) -#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) +#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg))) +#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg))) void putDebugChar(unsigned char c); unsigned char getDebugChar(void); diff --git a/arch/mips/sni/reset.c b/arch/mips/sni/reset.c index 38b6a97..79f8d70 100644 --- a/arch/mips/sni/reset.c +++ b/arch/mips/sni/reset.c @@ -35,7 +35,7 @@ void sni_machine_restart(char *command) kb_wait(); for (j = 0; j < 100000 ; j++) /* nothing */; - outb_p(0xfe,0x64); /* pulse reset low */ + outb_p(0xfe, 0x64); /* pulse reset low */ } } } diff --git a/arch/mips/sni/sniprom.c b/arch/mips/sni/sniprom.c index 11eddd4..eff4b89 100644 --- a/arch/mips/sni/sniprom.c +++ b/arch/mips/sni/sniprom.c @@ -233,7 +233,7 @@ void __init prom_init(void) systype = "RM300-Exx"; break; } - pr_debug("Found SNI brdtype %02x name %s\n", sni_brd_type,systype); + pr_debug("Found SNI brdtype %02x name %s\n", sni_brd_type, systype); #ifdef DEBUG sni_idprom_dump(); diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c index 305eb12..3f808b6 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c @@ -176,7 +176,7 @@ static const u32 toshiba_rbtx4927_irq_debug_flag = printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \ } #else -#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) +#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag, str...) #endif diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c index 4f30206..acaf613 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c @@ -122,7 +122,7 @@ static const u32 toshiba_rbtx4927_setup_debug_flag = printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \ } #else -#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) +#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag, str...) #endif /* These functions are used for rebooting or halting the machine*/ @@ -497,7 +497,7 @@ void __init tx4927_pci_setup(void) "Internal"); called = 1; } - printk("%s PCIC --%s PCICLK:",toshiba_name, + printk("%s PCIC --%s PCICLK:", toshiba_name, (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : ""); if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) { int pciclk = 0; diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c index 304b406..ceecaf4 100644 --- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c +++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c @@ -457,9 +457,9 @@ extern struct pci_controller tx4938_pci_controller[]; static int __init tx4938_pcibios_init(void) { unsigned long mem_base[2]; - unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0,TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */ + unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */ unsigned long io_base[2]; - unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0,TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */ + unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */ /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */ int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB); diff --git a/arch/mips/vr41xx/nec-cmbvr4133/init.c b/arch/mips/vr41xx/nec-cmbvr4133/init.c index ae1af6b..7c5e18e 100644 --- a/arch/mips/vr41xx/nec-cmbvr4133/init.c +++ b/arch/mips/vr41xx/nec-cmbvr4133/init.c @@ -36,7 +36,7 @@ void disable_pcnet(void) */ writel((2 << 16) | - (PCI_DEVFN(1,0) << 8) | + (PCI_DEVFN(1, 0) << 8) | (0 & 0xfc) | 1UL, PCICONFAREG); @@ -44,7 +44,7 @@ void disable_pcnet(void) data = readl(PCICONFDREG); writel((2 << 16) | - (PCI_DEVFN(1,0) << 8) | + (PCI_DEVFN(1, 0) << 8) | (4 & 0xfc) | 1UL, PCICONFAREG); @@ -52,7 +52,7 @@ void disable_pcnet(void) data = readl(PCICONFDREG); writel((2 << 16) | - (PCI_DEVFN(1,0) << 8) | + (PCI_DEVFN(1, 0) << 8) | (4 & 0xfc) | 1UL, PCICONFAREG); diff --git a/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c b/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c index f45cacc..1341f32 100644 --- a/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c +++ b/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c @@ -38,7 +38,7 @@ outb_p((dev_no), DATA_PORT(port)); \ } while(0) -#define WRITE_CONFIG_DATA(port,index,data) \ +#define WRITE_CONFIG_DATA(port, index, data) \ do { \ outb_p((index), INDEX_PORT(port)); \ outb_p((data), DATA_PORT(port)); \ @@ -206,8 +206,8 @@ static inline u16 ali_config_readw(u8 reg, int devfn) int vr4133_rockhopper = 0; void __init ali_m5229_preinit(void) { - if (ali_config_readw(PCI_VENDOR_ID,16) == PCI_VENDOR_ID_AL && - ali_config_readw(PCI_DEVICE_ID,16) == PCI_DEVICE_ID_AL_M1533) { + if (ali_config_readw(PCI_VENDOR_ID, 16) == PCI_VENDOR_ID_AL && + ali_config_readw(PCI_DEVICE_ID, 16) == PCI_DEVICE_ID_AL_M1533) { printk(KERN_INFO "Found an NEC Rockhopper \n"); vr4133_rockhopper = 1; /* diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index 0b3ff9c..0bb7a93 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -123,10 +123,10 @@ /* * 64-bit address conversions */ -#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p)) -#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p)) +#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) +#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) #define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) -#define PHYS_TO_XKPHYS(cm,a) (_CONST64_(0x8000000000000000) | \ +#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ ((cm)<<59) | (a)) /* diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h index 838eb31..12e1758 100644 --- a/include/asm-mips/asm.h +++ b/include/asm-mips/asm.h @@ -21,11 +21,11 @@ #ifndef CAT #ifdef __STDC__ -#define __CAT(str1,str2) str1##str2 +#define __CAT(str1, str2) str1##str2 #else -#define __CAT(str1,str2) str1/**/str2 +#define __CAT(str1, str2) str1/**/str2 #endif -#define CAT(str1,str2) __CAT(str1,str2) +#define CAT(str1, str2) __CAT(str1, str2) #endif /* @@ -51,9 +51,9 @@ #define LEAF(symbol) \ .globl symbol; \ .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ -symbol: .frame sp,0,ra + .type symbol, @function; \ + .ent symbol, 0; \ +symbol: .frame sp, 0, ra /* * NESTED - declare nested routine entry point @@ -61,8 +61,8 @@ symbol: .frame sp,0,ra #define NESTED(symbol, framesize, rpc) \ .globl symbol; \ .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ + .type symbol, @function; \ + .ent symbol, 0; \ symbol: .frame sp, framesize, rpc /* @@ -70,7 +70,7 @@ symbol: .frame sp, framesize, rpc */ #define END(function) \ .end function; \ - .size function,.-function + .size function, .-function /* * EXPORT - export definition of symbol @@ -84,7 +84,7 @@ symbol: */ #define FEXPORT(symbol) \ .globl symbol; \ - .type symbol,@function; \ + .type symbol, @function; \ symbol: /* @@ -97,7 +97,7 @@ symbol = value #define PANIC(msg) \ .set push; \ .set reorder; \ - PTR_LA a0,8f; \ + PTR_LA a0, 8f; \ jal panic; \ 9: b 9b; \ .set pop; \ @@ -110,7 +110,7 @@ symbol = value #define PRINT(string) \ .set push; \ .set reorder; \ - PTR_LA a0,8f; \ + PTR_LA a0, 8f; \ jal printk; \ .set pop; \ TEXT(string) @@ -146,19 +146,19 @@ symbol = value #define PREF(hint,addr) \ .set push; \ .set mips4; \ - pref hint,addr; \ + pref hint, addr; \ .set pop #define PREFX(hint,addr) \ .set push; \ .set mips4; \ - prefx hint,addr; \ + prefx hint, addr; \ .set pop #else /* !CONFIG_CPU_HAS_PREFETCH */ -#define PREF(hint,addr) -#define PREFX(hint,addr) +#define PREF(hint, addr) +#define PREFX(hint, addr) #endif /* !CONFIG_CPU_HAS_PREFETCH */ @@ -166,43 +166,43 @@ symbol = value * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. */ #if (_MIPS_ISA == _MIPS_ISA_MIPS1) -#define MOVN(rd,rs,rt) \ +#define MOVN(rd, rs, rt) \ .set push; \ .set reorder; \ - beqz rt,9f; \ - move rd,rs; \ + beqz rt, 9f; \ + move rd, rs; \ .set pop; \ 9: -#define MOVZ(rd,rs,rt) \ +#define MOVZ(rd, rs, rt) \ .set push; \ .set reorder; \ - bnez rt,9f; \ - move rd,rs; \ + bnez rt, 9f; \ + move rd, rs; \ .set pop; \ 9: #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) -#define MOVN(rd,rs,rt) \ +#define MOVN(rd, rs, rt) \ .set push; \ .set noreorder; \ - bnezl rt,9f; \ - move rd,rs; \ + bnezl rt, 9f; \ + move rd, rs; \ .set pop; \ 9: -#define MOVZ(rd,rs,rt) \ +#define MOVZ(rd, rs, rt) \ .set push; \ .set noreorder; \ - beqzl rt,9f; \ - move rd,rs; \ + beqzl rt, 9f; \ + move rd, rs; \ .set pop; \ 9: #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) -#define MOVN(rd,rs,rt) \ - movn rd,rs,rt -#define MOVZ(rd,rs,rt) \ - movz rd,rs,rt +#define MOVN(rd, rs, rt) \ + movn rd, rs, rt +#define MOVZ(rd, rs, rt) \ + movz rd, rs, rt #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ /* @@ -396,6 +396,6 @@ symbol = value #define MTC0 dmtc0 #endif -#define SSNOP sll zero,zero,1 +#define SSNOP sll zero, zero, 1 #endif /* __ASM_ASM_H */ diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h index 7d80037..a798d62 100644 --- a/include/asm-mips/atomic.h +++ b/include/asm-mips/atomic.h @@ -39,7 +39,7 @@ typedef struct { volatile int counter; } atomic_t; * * Atomically sets the value of @v to @i. */ -#define atomic_set(v,i) ((v)->counter = (i)) +#define atomic_set(v, i) ((v)->counter = (i)) /* * atomic_add - add integer to atomic variable @@ -335,8 +335,8 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) -#define atomic_dec_return(v) atomic_sub_return(1,(v)) -#define atomic_inc_return(v) atomic_add_return(1,(v)) +#define atomic_dec_return(v) atomic_sub_return(1, (v)) +#define atomic_inc_return(v) atomic_add_return(1, (v)) /* * atomic_sub_and_test - subtract value from variable and test result @@ -347,7 +347,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) * true if the result is zero, or false for all * other cases. */ -#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0) +#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0) /* * atomic_inc_and_test - increment and test @@ -381,7 +381,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) * * Atomically increments @v by 1. */ -#define atomic_inc(v) atomic_add(1,(v)) +#define atomic_inc(v) atomic_add(1, (v)) /* * atomic_dec - decrement and test @@ -389,7 +389,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) * * Atomically decrements @v by 1. */ -#define atomic_dec(v) atomic_sub(1,(v)) +#define atomic_dec(v) atomic_sub(1, (v)) /* * atomic_add_negative - add and test if negative @@ -400,7 +400,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) * if the result is negative, or false when * result is greater than or equal to zero. */ -#define atomic_add_negative(i,v) (atomic_add_return(i, (v)) < 0) +#define atomic_add_negative(i, v) (atomic_add_return(i, (v)) < 0) #ifdef CONFIG_64BIT @@ -420,7 +420,7 @@ typedef struct { volatile long counter; } atomic64_t; * @v: pointer of type atomic64_t * @i: required value */ -#define atomic64_set(v,i) ((v)->counter = (i)) +#define atomic64_set(v, i) ((v)->counter = (i)) /* * atomic64_add - add integer to atomic variable @@ -718,8 +718,8 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) -#define atomic64_dec_return(v) atomic64_sub_return(1,(v)) -#define atomic64_inc_return(v) atomic64_add_return(1,(v)) +#define atomic64_dec_return(v) atomic64_sub_return(1, (v)) +#define atomic64_inc_return(v) atomic64_add_return(1, (v)) /* * atomic64_sub_and_test - subtract value from variable and test result @@ -730,7 +730,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) * true if the result is zero, or false for all * other cases. */ -#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0) +#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0) /* * atomic64_inc_and_test - increment and test @@ -764,7 +764,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) * * Atomically increments @v by 1. */ -#define atomic64_inc(v) atomic64_add(1,(v)) +#define atomic64_inc(v) atomic64_add(1, (v)) /* * atomic64_dec - decrement and test @@ -772,7 +772,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) * * Atomically decrements @v by 1. */ -#define atomic64_dec(v) atomic64_sub(1,(v)) +#define atomic64_dec(v) atomic64_sub(1, (v)) /* * atomic64_add_negative - add and test if negative @@ -783,7 +783,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) * if the result is negative, or false when * result is greater than or equal to zero. */ -#define atomic64_add_negative(i,v) (atomic64_add_return(i, (v)) < 0) +#define atomic64_add_negative(i, v) (atomic64_add_return(i, (v)) < 0) #endif /* CONFIG_64BIT */ diff --git a/include/asm-mips/cmpxchg.h b/include/asm-mips/cmpxchg.h index c5b4708..a5ec0e5 100644 --- a/include/asm-mips/cmpxchg.h +++ b/include/asm-mips/cmpxchg.h @@ -72,7 +72,7 @@ */ extern void __cmpxchg_called_with_bad_pointer(void); -#define __cmpxchg(ptr,old,new,barrier) \ +#define __cmpxchg(ptr, old, new, barrier) \ ({ \ __typeof__(ptr) __ptr = (ptr); \ __typeof__(*(ptr)) __old = (old); \ @@ -102,6 +102,6 @@ extern void __cmpxchg_called_with_bad_pointer(void); }) #define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb()) -#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new,) +#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, ) #endif /* __ASM_CMPXCHG_H */ diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h index 223d156..fab3213 100644 --- a/include/asm-mips/delay.h +++ b/include/asm-mips/delay.h @@ -81,7 +81,7 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj) #define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val -#define udelay(usecs) __udelay((usecs),__udelay_val) +#define udelay(usecs) __udelay((usecs), __udelay_val) /* make sure "usecs *= ..." in udelay do not overflow. */ #if HZ >= 1000 diff --git a/include/asm-mips/floppy.h b/include/asm-mips/floppy.h index dcadd85..a62d099 100644 --- a/include/asm-mips/floppy.h +++ b/include/asm-mips/floppy.h @@ -49,7 +49,7 @@ static inline void fd_cacheflush(char * addr, long size) * Actually this needs to be a bit more complicated since the so much different * hardware available with MIPS CPUs ... */ -#define CROSS_64KB(a,s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64) +#define CROSS_64KB(a, s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64) #define EXTRA_FLOPPY_PARAMS diff --git a/include/asm-mips/fw/cfe/cfe_api.h b/include/asm-mips/fw/cfe/cfe_api.h index d8230cc..41cf050 100644 --- a/include/asm-mips/fw/cfe/cfe_api.h +++ b/include/asm-mips/fw/cfe/cfe_api.h @@ -136,25 +136,25 @@ int64_t cfe_getticks(void); */ #ifdef CFE_API_IMPL_NAMESPACE #define cfe_close(a) __cfe_close(a) -#define cfe_cpu_start(a,b,c,d,e) __cfe_cpu_start(a,b,c,d,e) +#define cfe_cpu_start(a, b, c, d, e) __cfe_cpu_start(a, b, c, d, e) #define cfe_cpu_stop(a) __cfe_cpu_stop(a) -#define cfe_enumenv(a,b,d,e,f) __cfe_enumenv(a,b,d,e,f) -#define cfe_enummem(a,b,c,d,e) __cfe_enummem(a,b,c,d,e) -#define cfe_exit(a,b) __cfe_exit(a,b) +#define cfe_enumenv(a, b, d, e, f) __cfe_enumenv(a, b, d, e, f) +#define cfe_enummem(a, b, c, d, e) __cfe_enummem(a, b, c, d, e) +#define cfe_exit(a, b) __cfe_exit(a, b) #define cfe_flushcache(a) __cfe_cacheflush(a) #define cfe_getdevinfo(a) __cfe_getdevinfo(a) -#define cfe_getenv(a,b,c) __cfe_getenv(a,b,c) +#define cfe_getenv(a, b, c) __cfe_getenv(a, b, c) #define cfe_getfwinfo(a) __cfe_getfwinfo(a) #define cfe_getstdhandle(a) __cfe_getstdhandle(a) -#define cfe_init(a,b) __cfe_init(a,b) +#define cfe_init(a, b) __cfe_init(a, b) #define cfe_inpstat(a) __cfe_inpstat(a) -#define cfe_ioctl(a,b,c,d,e,f) __cfe_ioctl(a,b,c,d,e,f) +#define cfe_ioctl(a, b, c, d, e, f) __cfe_ioctl(a, b, c, d, e, f) #define cfe_open(a) __cfe_open(a) -#define cfe_read(a,b,c) __cfe_read(a,b,c) -#define cfe_readblk(a,b,c,d) __cfe_readblk(a,b,c,d) -#define cfe_setenv(a,b) __cfe_setenv(a,b) -#define cfe_write(a,b,c) __cfe_write(a,b,c) -#define cfe_writeblk(a,b,c,d) __cfe_writeblk(a,b,c,d) +#define cfe_read(a, b, c) __cfe_read(a, b, c) +#define cfe_readblk(a, b, c, d) __cfe_readblk(a, b, c, d) +#define cfe_setenv(a, b) __cfe_setenv(a, b) +#define cfe_write(a, b, c) __cfe_write(a, b, c) +#define cfe_writeblk(a, b, c, d __cfe_writeblk(a, b, c, d) #endif /* CFE_API_IMPL_NAMESPACE */ int cfe_close(int handle); diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index 6a5fa32..7e843b5 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -193,7 +193,7 @@ ASMMACRO(enable_fpu_hazard, .set mips64; .set noreorder; _ssnop; - bnezl $0,.+4; + bnezl $0, .+4; _ssnop; .set pop ) diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 7ba9289..2cd8323 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -40,11 +40,11 @@ * hardware. An example use would be for flash memory that's used for * execute in place. */ -# define __raw_ioswabb(a,x) (x) -# define __raw_ioswabw(a,x) (x) -# define __raw_ioswabl(a,x) (x) -# define __raw_ioswabq(a,x) (x) -# define ____raw_ioswabq(a,x) (x) +# define __raw_ioswabb(a, x) (x) +# define __raw_ioswabw(a, x) (x) +# define __raw_ioswabl(a, x) (x) +# define __raw_ioswabq(a, x) (x) +# define ____raw_ioswabq(a, x) (x) /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ @@ -561,9 +561,9 @@ extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); -#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start,size) -#define dma_cache_wback(start, size) _dma_cache_wback(start,size) -#define dma_cache_inv(start, size) _dma_cache_inv(start,size) +#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size) +#define dma_cache_wback(start, size) _dma_cache_wback(start, size) +#define dma_cache_inv(start, size) _dma_cache_inv(start, size) #else /* Sane hardware */ @@ -587,7 +587,7 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); #define __CSR_32_ADJUST 0 #endif -#define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) +#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) /* diff --git a/include/asm-mips/ioctl.h b/include/asm-mips/ioctl.h index 2036fcb..85067e2 100644 --- a/include/asm-mips/ioctl.h +++ b/include/asm-mips/ioctl.h @@ -54,7 +54,7 @@ #define _IOC_IN 0x80000000 #define _IOC_INOUT (IOC_IN|IOC_OUT) -#define _IOC(dir,type,nr,size) \ +#define _IOC(dir, type, nr, size) \ (((dir) << _IOC_DIRSHIFT) | \ ((type) << _IOC_TYPESHIFT) | \ ((nr) << _IOC_NRSHIFT) | \ @@ -68,13 +68,13 @@ extern unsigned int __invalid_size_argument_for_IOC; sizeof(t) : __invalid_size_argument_for_IOC) /* used to create numbers */ -#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) -#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) -#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) -#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) +#define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0) +#define _IOR(type, nr, size) _IOC(_IOC_READ, (type), (nr), (_IOC_TYPECHECK(size))) +#define _IOW(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size))) +#define _IOWR(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size))) +#define _IOR_BAD(type, nr, size) _IOC(_IOC_READ, (type), (nr), sizeof(size)) +#define _IOW_BAD(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), sizeof(size)) +#define _IOWR_BAD(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), sizeof(size)) /* used to decode them.. */ diff --git a/include/asm-mips/ioctls.h b/include/asm-mips/ioctls.h index 5097cbf..3f04a99 100644 --- a/include/asm-mips/ioctls.h +++ b/include/asm-mips/ioctls.h @@ -77,12 +77,12 @@ #define TIOCSBRK 0x5427 /* BSD compatibility */ #define TIOCCBRK 0x5428 /* BSD compatibility */ #define TIOCGSID 0x7416 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T',0x2A, struct termios2) -#define TCSETS2 _IOW('T',0x2B, struct termios2) -#define TCSETSW2 _IOW('T',0x2C, struct termios2) -#define TCSETSF2 _IOW('T',0x2D, struct termios2) -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ +#define TCGETS2 _IOR('T', 0x2A, struct termios2) +#define TCSETS2 _IOW('T', 0x2B, struct termios2) +#define TCSETSW2 _IOW('T', 0x2C, struct termios2) +#define TCSETSF2 _IOW('T', 0x2D, struct termios2) +#define TIOCGPTN _IOR('T', 0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ +#define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */ /* I hope the range from 0x5480 on is free ... */ #define TIOCSCTTY 0x5480 /* become controlling tty */ diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h index 4be2f25..211bcf4 100644 --- a/include/asm-mips/jmr3927/tx3927.h +++ b/include/asm-mips/jmr3927/tx3927.h @@ -53,23 +53,23 @@ struct tx3927_dma_reg { #include #ifdef __BIG_ENDIAN -#define endian_def_s2(e1,e2) \ - volatile unsigned short e1,e2 -#define endian_def_sb2(e1,e2,e3) \ - volatile unsigned short e1;volatile unsigned char e2,e3 -#define endian_def_b2s(e1,e2,e3) \ - volatile unsigned char e1,e2;volatile unsigned short e3 -#define endian_def_b4(e1,e2,e3,e4) \ - volatile unsigned char e1,e2,e3,e4 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e1, e2 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned short e1;volatile unsigned char e2, e3 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned char e1, e2;volatile unsigned short e3 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e1, e2, e3, e4 #else -#define endian_def_s2(e1,e2) \ - volatile unsigned short e2,e1 -#define endian_def_sb2(e1,e2,e3) \ - volatile unsigned char e3,e2;volatile unsigned short e1 -#define endian_def_b2s(e1,e2,e3) \ - volatile unsigned short e3;volatile unsigned char e2,e1 -#define endian_def_b4(e1,e2,e3,e4) \ - volatile unsigned char e4,e3,e2,e1 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e2, e1 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned char e3, e2;volatile unsigned short e1 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned short e3;volatile unsigned char e2, e1 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e4, e3, e2, e1 #endif struct tx3927_pcic_reg { diff --git a/include/asm-mips/local.h b/include/asm-mips/local.h index f9a5ce5..f96fd59 100644 --- a/include/asm-mips/local.h +++ b/include/asm-mips/local.h @@ -15,10 +15,10 @@ typedef struct #define LOCAL_INIT(i) { ATOMIC_LONG_INIT(i) } #define local_read(l) atomic_long_read(&(l)->a) -#define local_set(l,i) atomic_long_set(&(l)->a, (i)) +#define local_set(l, i) atomic_long_set(&(l)->a, (i)) -#define local_add(i,l) atomic_long_add((i),(&(l)->a)) -#define local_sub(i,l) atomic_long_sub((i),(&(l)->a)) +#define local_add(i, l) atomic_long_add((i), (&(l)->a)) +#define local_sub(i, l) atomic_long_sub((i), (&(l)->a)) #define local_inc(l) atomic_long_inc(&(l)->a) #define local_dec(l) atomic_long_dec(&(l)->a) @@ -117,7 +117,7 @@ static __inline__ long local_sub_return(long i, local_t * l) #define local_cmpxchg(l, o, n) \ ((long)cmpxchg_local(&((l)->a.counter), (o), (n))) -#define local_xchg(l, n) (xchg_local(&((l)->a.counter),(n))) +#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n))) /** * local_add_unless - add unless the number is a given value @@ -138,8 +138,8 @@ static __inline__ long local_sub_return(long i, local_t * l) }) #define local_inc_not_zero(l) local_add_unless((l), 1, 0) -#define local_dec_return(l) local_sub_return(1,(l)) -#define local_inc_return(l) local_add_return(1,(l)) +#define local_dec_return(l) local_sub_return(1, (l)) +#define local_inc_return(l) local_add_return(1, (l)) /* * local_sub_and_test - subtract value from variable and test result @@ -150,7 +150,7 @@ static __inline__ long local_sub_return(long i, local_t * l) * true if the result is zero, or false for all * other cases. */ -#define local_sub_and_test(i,l) (local_sub_return((i), (l)) == 0) +#define local_sub_and_test(i, l) (local_sub_return((i), (l)) == 0) /* * local_inc_and_test - increment and test @@ -181,7 +181,7 @@ static __inline__ long local_sub_return(long i, local_t * l) * if the result is negative, or false when * result is greater than or equal to zero. */ -#define local_add_negative(i,l) (local_add_return(i, (l)) < 0) +#define local_add_negative(i, l) (local_add_return(i, (l)) < 0) /* Use these for per-cpu local_t variables: on some archs they are * much more efficient than these naive implementations. Note they take @@ -190,8 +190,8 @@ static __inline__ long local_sub_return(long i, local_t * l) #define __local_inc(l) ((l)->a.counter++) #define __local_dec(l) ((l)->a.counter++) -#define __local_add(i,l) ((l)->a.counter+=(i)) -#define __local_sub(i,l) ((l)->a.counter-=(i)) +#define __local_add(i, l) ((l)->a.counter+=(i)) +#define __local_sub(i, l) ((l)->a.counter-=(i)) /* Need to disable preemption for the cpu local counters otherwise we could still access a variable of a previous CPU in a non atomic way. */ diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h index eeb0c31..93d507c 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h +++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h @@ -199,7 +199,7 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_CMD0_ALWAYS 31 #define DSCR_NDEV_IDS 32 /* THis macro is used to find/create custom device types */ -#define DSCR_DEV2CUSTOM_ID(x,d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF)) +#define DSCR_DEV2CUSTOM_ID(x, d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF)) #define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF) @@ -373,14 +373,14 @@ void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); Some compatibilty macros -- Needed to make changes to API without breaking existing drivers */ -#define au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE) -#define au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags) -#define put_source_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) +#define au1xxx_dbdma_put_source(chanid, buf, nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE) +#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags) +#define put_source_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) -#define au1xxx_dbdma_put_dest(chanid,buf,nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE) -#define au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags) -#define put_dest_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) +#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE) +#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags) +#define put_dest_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) /* * Flags for the put_source/put_dest functions. diff --git a/include/asm-mips/mach-generic/mangle-port.h b/include/asm-mips/mach-generic/mangle-port.h index 6e1b0c0..f49dc99 100644 --- a/include/asm-mips/mach-generic/mangle-port.h +++ b/include/asm-mips/mach-generic/mangle-port.h @@ -27,25 +27,25 @@ */ #if defined(CONFIG_SWAP_IO_SPACE) -# define ioswabb(a,x) (x) -# define __mem_ioswabb(a,x) (x) -# define ioswabw(a,x) le16_to_cpu(x) -# define __mem_ioswabw(a,x) (x) -# define ioswabl(a,x) le32_to_cpu(x) -# define __mem_ioswabl(a,x) (x) -# define ioswabq(a,x) le64_to_cpu(x) -# define __mem_ioswabq(a,x) (x) +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) le16_to_cpu(x) +# define __mem_ioswabw(a, x) (x) +# define ioswabl(a, x) le32_to_cpu(x) +# define __mem_ioswabl(a, x) (x) +# define ioswabq(a, x) le64_to_cpu(x) +# define __mem_ioswabq(a, x) (x) #else -# define ioswabb(a,x) (x) -# define __mem_ioswabb(a,x) (x) -# define ioswabw(a,x) (x) -# define __mem_ioswabw(a,x) cpu_to_le16(x) -# define ioswabl(a,x) (x) -# define __mem_ioswabl(a,x) cpu_to_le32(x) -# define ioswabq(a,x) (x) -# define __mem_ioswabq(a,x) cpu_to_le32(x) +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) (x) +# define __mem_ioswabw(a, x) cpu_to_le16(x) +# define ioswabl(a, x) (x) +# define __mem_ioswabl(a, x) cpu_to_le32(x) +# define ioswabq(a, x) (x) +# define __mem_ioswabq(a, x) cpu_to_le32(x) #endif diff --git a/include/asm-mips/mach-ip27/mangle-port.h b/include/asm-mips/mach-ip27/mangle-port.h index d615312..f6e4912 100644 --- a/include/asm-mips/mach-ip27/mangle-port.h +++ b/include/asm-mips/mach-ip27/mangle-port.h @@ -13,13 +13,13 @@ #define __swizzle_addr_l(port) (port) #define __swizzle_addr_q(port) (port) -# define ioswabb(a,x) (x) -# define __mem_ioswabb(a,x) (x) -# define ioswabw(a,x) (x) -# define __mem_ioswabw(a,x) cpu_to_le16(x) -# define ioswabl(a,x) (x) -# define __mem_ioswabl(a,x) cpu_to_le32(x) -# define ioswabq(a,x) (x) -# define __mem_ioswabq(a,x) cpu_to_le32(x) +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) (x) +# define __mem_ioswabw(a, x) cpu_to_le16(x) +# define ioswabl(a, x) (x) +# define __mem_ioswabl(a, x) cpu_to_le32(x) +# define ioswabq(a, x) (x) +# define __mem_ioswabq(a, x) cpu_to_le32(x) #endif /* __ASM_MACH_IP27_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-ip32/mangle-port.h b/include/asm-mips/mach-ip32/mangle-port.h index 81320eb..f1d0f17 100644 --- a/include/asm-mips/mach-ip32/mangle-port.h +++ b/include/asm-mips/mach-ip32/mangle-port.h @@ -14,13 +14,13 @@ #define __swizzle_addr_l(port) (port) #define __swizzle_addr_q(port) (port) -# define ioswabb(a,x) (x) -# define __mem_ioswabb(a,x) (x) -# define ioswabw(a,x) (x) -# define __mem_ioswabw(a,x) cpu_to_le16(x) -# define ioswabl(a,x) (x) -# define __mem_ioswabl(a,x) cpu_to_le32(x) -# define ioswabq(a,x) (x) -# define __mem_ioswabq(a,x) cpu_to_le32(x) +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) (x) +# define __mem_ioswabw(a, x) cpu_to_le16(x) +# define ioswabl(a, x) (x) +# define __mem_ioswabl(a, x) cpu_to_le32(x) +# define ioswabq(a, x) (x) +# define __mem_ioswabq(a, x) cpu_to_le32(x) #endif /* __ASM_MACH_IP32_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-jmr3927/mangle-port.h b/include/asm-mips/mach-jmr3927/mangle-port.h index 501a202..11bffcd 100644 --- a/include/asm-mips/mach-jmr3927/mangle-port.h +++ b/include/asm-mips/mach-jmr3927/mangle-port.h @@ -6,13 +6,13 @@ extern unsigned long __swizzle_addr_b(unsigned long port); #define __swizzle_addr_l(port) (port) #define __swizzle_addr_q(port) (port) -#define ioswabb(a,x) (x) -#define __mem_ioswabb(a,x) (x) -#define ioswabw(a,x) le16_to_cpu(x) -#define __mem_ioswabw(a,x) (x) -#define ioswabl(a,x) le32_to_cpu(x) -#define __mem_ioswabl(a,x) (x) -#define ioswabq(a,x) le64_to_cpu(x) -#define __mem_ioswabq(a,x) (x) +#define ioswabb(a, x) (x) +#define __mem_ioswabb(a, x) (x) +#define ioswabw(a, x) le16_to_cpu(x) +#define __mem_ioswabw(a, x) (x) +#define ioswabl(a, x) le32_to_cpu(x) +#define __mem_ioswabl(a, x) (x) +#define ioswabq(a, x) le64_to_cpu(x) +#define __mem_ioswabq(a, x) (x) #endif /* __ASM_MACH_JMR3927_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-pnx8550/kernel-entry-init.h b/include/asm-mips/mach-pnx8550/kernel-entry-init.h index 982079f..bdde00c 100644 --- a/include/asm-mips/mach-pnx8550/kernel-entry-init.h +++ b/include/asm-mips/mach-pnx8550/kernel-entry-init.h @@ -44,7 +44,7 @@ cache_begin: li t0, (1<<28) mfc0 t0, CP0_CONFIG, 7 HAZARD_CP0 - and t0,~((1<<19) | (1<<20)) /* TLB/MAP cleared */ + and t0, ~((1<<19) | (1<<20)) /* TLB/MAP cleared */ mtc0 t0, CP0_CONFIG, 7 HAZARD_CP0 diff --git a/include/asm-mips/mach-pnx8550/uart.h b/include/asm-mips/mach-pnx8550/uart.h index 814a7a1..ad7608d 100644 --- a/include/asm-mips/mach-pnx8550/uart.h +++ b/include/asm-mips/mach-pnx8550/uart.h @@ -15,7 +15,7 @@ /* early macros needed for prom/kgdb */ -#define ip3106_lcr(base,port) *(volatile u32 *)(base+(port*0x1000) + 0x000) +#define ip3106_lcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x000) #define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004) #define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008) #define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C) diff --git a/include/asm-mips/mc146818-time.h b/include/asm-mips/mc146818-time.h index 41ac8d3..cdc379a 100644 --- a/include/asm-mips/mc146818-time.h +++ b/include/asm-mips/mc146818-time.h @@ -63,8 +63,8 @@ static inline int mc146818_set_rtc_mmss(unsigned long nowtime) BIN_TO_BCD(real_seconds); BIN_TO_BCD(real_minutes); } - CMOS_WRITE(real_seconds,RTC_SECONDS); - CMOS_WRITE(real_minutes,RTC_MINUTES); + CMOS_WRITE(real_seconds, RTC_SECONDS); + CMOS_WRITE(real_minutes, RTC_MINUTES); } else { printk(KERN_WARNING "set_rtc_mmss: can't update from %d to %d\n", diff --git a/include/asm-mips/mips-boards/bonito64.h b/include/asm-mips/mips-boards/bonito64.h index dc3fc32..a0f04bb 100644 --- a/include/asm-mips/mips-boards/bonito64.h +++ b/include/asm-mips/mips-boards/bonito64.h @@ -387,7 +387,7 @@ extern unsigned long _pcictrl_bonito_pcicfg; #define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000 #define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12 #define BONITO_PCIMAP_PCIMAP_2 0x00040000 -#define BONITO_PCIMAP_WIN(WIN,ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) +#define BONITO_PCIMAP_WIN(WIN, ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) #define BONITO_PCIMAP_WINSIZE (1<<26) #define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1)) @@ -412,19 +412,19 @@ extern unsigned long _pcictrl_bonito_pcicfg; #define BONITO_PCIMEMBASECFG_ASHIFT 23 #define BONITO_PCIMEMBASECFG_AMASK 0x007fffff -#define BONITO_PCIMEMBASECFGSIZE(WIN,SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) -#define BONITO_PCIMEMBASECFGBASE(WIN,BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) +#define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) +#define BONITO_PCIMEMBASECFGBASE(WIN, BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) -#define BONITO_PCIMEMBASECFG_SIZE(WIN,CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) +#define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) -#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) -#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) -#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) +#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) +#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) +#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) -#define BONITO_PCITOPHYS(WIN,ADDR,CFG) ( \ - (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)))) | \ - (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG)) \ +#define BONITO_PCITOPHYS(WIN, ADDR, CFG) ( \ + (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \ + (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \ ) /* PCICmd */ diff --git a/include/asm-mips/mips-boards/malta.h b/include/asm-mips/mips-boards/malta.h index eec9100..93bf4e5 100644 --- a/include/asm-mips/mips-boards/malta.h +++ b/include/asm-mips/mips-boards/malta.h @@ -72,7 +72,7 @@ static inline unsigned long get_msc_port_base(unsigned long reg) #define SMSC_CONFIG_ACTIVATE_ENABLE 1 -#define SMSC_WRITE(x,a) outb(x,a) +#define SMSC_WRITE(x, a) outb(x, a) #define MALTA_JMPRS_REG 0x1f000210 diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h index 294bca1..5a2f8a3 100644 --- a/include/asm-mips/mipsmtregs.h +++ b/include/asm-mips/mipsmtregs.h @@ -41,27 +41,27 @@ * Macros for use in assembly language code */ -#define CP0_MVPCONTROL $0,1 -#define CP0_MVPCONF0 $0,2 -#define CP0_MVPCONF1 $0,3 -#define CP0_VPECONTROL $1,1 -#define CP0_VPECONF0 $1,2 -#define CP0_VPECONF1 $1,3 -#define CP0_YQMASK $1,4 -#define CP0_VPESCHEDULE $1,5 -#define CP0_VPESCHEFBK $1,6 -#define CP0_TCSTATUS $2,1 -#define CP0_TCBIND $2,2 -#define CP0_TCRESTART $2,3 -#define CP0_TCHALT $2,4 -#define CP0_TCCONTEXT $2,5 -#define CP0_TCSCHEDULE $2,6 -#define CP0_TCSCHEFBK $2,7 -#define CP0_SRSCONF0 $6,1 -#define CP0_SRSCONF1 $6,2 -#define CP0_SRSCONF2 $6,3 -#define CP0_SRSCONF3 $6,4 -#define CP0_SRSCONF4 $6,5 +#define CP0_MVPCONTROL $0, 1 +#define CP0_MVPCONF0 $0, 2 +#define CP0_MVPCONF1 $0, 3 +#define CP0_VPECONTROL $1, 1 +#define CP0_VPECONF0 $1, 2 +#define CP0_VPECONF1 $1, 3 +#define CP0_YQMASK $1, 4 +#define CP0_VPESCHEDULE $1, 5 +#define CP0_VPESCHEFBK $1, 6 +#define CP0_TCSTATUS $2, 1 +#define CP0_TCBIND $2, 2 +#define CP0_TCRESTART $2, 3 +#define CP0_TCHALT $2, 4 +#define CP0_TCCONTEXT $2, 5 +#define CP0_TCSCHEDULE $2, 6 +#define CP0_TCSCHEFBK $2, 7 +#define CP0_SRSCONF0 $6, 1 +#define CP0_SRSCONF1 $6, 2 +#define CP0_SRSCONF2 $6, 3 +#define CP0_SRSCONF3 $6, 4 +#define CP0_SRSCONF4 $6, 5 #endif @@ -291,7 +291,7 @@ static inline void ehb(void) __res; \ }) -#define mftr(rt,u,sel) \ +#define mftr(rt, u, sel) \ ({ \ unsigned long __res; \ \ @@ -315,7 +315,7 @@ do { \ : : "r" (v)); \ } while (0) -#define mttc0(rd,sel,v) \ +#define mttc0(rd, sel, v) \ ({ \ __asm__ __volatile__( \ " .set push \n" \ @@ -330,7 +330,7 @@ do { \ }) -#define mttr(rd,u,sel,v) \ +#define mttr(rd, u, sel, v) \ ({ \ __asm__ __volatile__( \ "mttr %0," #rd ", " #u ", " #sel \ @@ -362,7 +362,7 @@ do { \ #define write_vpe_c0_config1(val) mttc0(16, 1, val) #define read_vpe_c0_config7() mftc0(16, 7) #define write_vpe_c0_config7(val) mttc0(16, 7, val) -#define read_vpe_c0_ebase() mftc0(15,1) +#define read_vpe_c0_ebase() mftc0(15, 1) #define write_vpe_c0_ebase(val) mttc0(15, 1, val) #define write_vpe_c0_compare(val) mttc0(11, 0, val) #define read_vpe_c0_badvaddr() mftc0(8, 0) @@ -372,15 +372,15 @@ do { \ /* TC */ #define read_tc_c0_tcstatus() mftc0(2, 1) -#define write_tc_c0_tcstatus(val) mttc0(2,1,val) +#define write_tc_c0_tcstatus(val) mttc0(2, 1, val) #define read_tc_c0_tcbind() mftc0(2, 2) -#define write_tc_c0_tcbind(val) mttc0(2,2,val) +#define write_tc_c0_tcbind(val) mttc0(2, 2, val) #define read_tc_c0_tcrestart() mftc0(2, 3) -#define write_tc_c0_tcrestart(val) mttc0(2,3,val) +#define write_tc_c0_tcrestart(val) mttc0(2, 3, val) #define read_tc_c0_tchalt() mftc0(2, 4) -#define write_tc_c0_tchalt(val) mttc0(2,4,val) +#define write_tc_c0_tchalt(val) mttc0(2, 4, val) #define read_tc_c0_tccontext() mftc0(2, 5) -#define write_tc_c0_tccontext(val) mttc0(2,5,val) +#define write_tc_c0_tccontext(val) mttc0(2, 5, val) /* GPR */ #define read_tc_gpr_sp() mftgpr(29) diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 18f47f1..aa17f65 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -981,7 +981,7 @@ do { \ #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) /* MIPSR2 */ -#define read_c0_hwrena() __read_32bit_c0_register($7,0) +#define read_c0_hwrena() __read_32bit_c0_register($7, 0) #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) #define read_c0_intctl() __read_32bit_c0_register($12, 1) @@ -993,7 +993,7 @@ do { \ #define read_c0_srsmap() __read_32bit_c0_register($12, 3) #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) -#define read_c0_ebase() __read_32bit_c0_register($15,1) +#define read_c0_ebase() __read_32bit_c0_register($15, 1) #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) /* diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h index 65024ff..b3b7a68 100644 --- a/include/asm-mips/mmu_context.h +++ b/include/asm-mips/mmu_context.h @@ -107,7 +107,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) #else /* CONFIG_MIPS_MT_SMTC */ -#define get_new_mmu_context(mm,cpu) smtc_get_new_mmu_context((mm),(cpu)) +#define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu)) #endif /* CONFIG_MIPS_MT_SMTC */ @@ -191,7 +191,7 @@ static inline void destroy_context(struct mm_struct *mm) { } -#define deactivate_mm(tsk,mm) do { } while (0) +#define deactivate_mm(tsk, mm) do { } while (0) /* * After we have set current->mm to a new value, this activates diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h index 8c08fa9..c2394f8 100644 --- a/include/asm-mips/paccess.h +++ b/include/asm-mips/paccess.h @@ -25,13 +25,13 @@ extern asmlinkage void handle_ibe(void); extern asmlinkage void handle_dbe(void); -#define put_dbe(x,ptr) __put_dbe((x),(ptr),sizeof(*(ptr))) -#define get_dbe(x,ptr) __get_dbe((x),(ptr),sizeof(*(ptr))) +#define put_dbe(x, ptr) __put_dbe((x), (ptr), sizeof(*(ptr))) +#define get_dbe(x, ptr) __get_dbe((x), (ptr), sizeof(*(ptr))) struct __large_pstruct { unsigned long buf[100]; }; #define __mp(x) (*(struct __large_pstruct *)(x)) -#define __get_dbe(x,ptr,size) \ +#define __get_dbe(x, ptr, size) \ ({ \ long __gu_err; \ __typeof__(*(ptr)) __gu_val; \ @@ -70,7 +70,7 @@ struct __large_pstruct { unsigned long buf[100]; }; extern void __get_dbe_unknown(void); -#define __put_dbe(x,ptr,size) \ +#define __put_dbe(x, ptr, size) \ ({ \ long __pu_err; \ __typeof__(*(ptr)) __pu_val; \ diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index e3301e5..d2ea983 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -153,7 +153,7 @@ typedef struct { unsigned long pgprot; } pgprot_t; ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET) #endif #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) -#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0)) +#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x), 0)) #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) diff --git a/include/asm-mips/pci/bridge.h b/include/asm-mips/pci/bridge.h index 0c45e75..b84feeb 100644 --- a/include/asm-mips/pci/bridge.h +++ b/include/asm-mips/pci/bridge.h @@ -360,7 +360,7 @@ typedef struct bridge_err_cmdword_s { #define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 /* Type 0 Cfg Func Offset (1..7) */ #define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+\ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF) -#define BRIDGE_TYPE0_CFG_DEVF(s,f) (BRIDGE_TYPE0_CFG_DEV0+\ +#define BRIDGE_TYPE0_CFG_DEVF(s, f) (BRIDGE_TYPE0_CFG_DEV0+\ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\ (f)*BRIDGE_TYPE0_CFG_FUNC_OFF) diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h index 9fb57c0..81b7212 100644 --- a/include/asm-mips/pgalloc.h +++ b/include/asm-mips/pgalloc.h @@ -95,7 +95,7 @@ static inline void pte_free(struct page *pte) __free_pages(pte, PTE_ORDER); } -#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) +#define __pte_free_tlb(tlb, pte) tlb_remove_page((tlb), (pte)) #ifdef CONFIG_32BIT @@ -104,7 +104,7 @@ static inline void pte_free(struct page *pte) * inside the pgd, so has no extra memory associated with it. */ #define pmd_free(x) do { } while (0) -#define __pmd_free_tlb(tlb,x) do { } while (0) +#define __pmd_free_tlb(tlb, x) do { } while (0) #endif @@ -125,7 +125,7 @@ static inline void pmd_free(pmd_t *pmd) free_pages((unsigned long)pmd, PMD_ORDER); } -#define __pmd_free_tlb(tlb,x) pmd_free(x) +#define __pmd_free_tlb(tlb, x) pmd_free(x) #endif diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h index 59c865d..a094709 100644 --- a/include/asm-mips/pgtable-32.h +++ b/include/asm-mips/pgtable-32.h @@ -140,7 +140,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) /* to find an entry in a page-table-directory */ -#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) +#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) /* Find an entry in the third-level page table.. */ #define __pte_offset(address) \ diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h index a8aed9c..943515f 100644 --- a/include/asm-mips/pgtable-64.h +++ b/include/asm-mips/pgtable-64.h @@ -193,7 +193,7 @@ static inline void pud_clear(pud_t *pudp) #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) /* to find an entry in a page-table-directory */ -#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) +#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) static inline unsigned long pud_page_vaddr(pud_t pud) { @@ -237,7 +237,7 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) #define __swp_type(x) (((x).val >> 32) & 0xff) #define __swp_offset(x) ((x).val >> 40) -#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) +#define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) }) #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index d2ee281..17a7703 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -103,7 +103,7 @@ static inline void set_pte(pte_t *ptep, pte_t pte) } } } -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) +#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { @@ -140,7 +140,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval) } #endif } -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) +#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h index 3c8e3c8..2b8466f 100644 --- a/include/asm-mips/r4kcache.h +++ b/include/asm-mips/r4kcache.h @@ -354,7 +354,7 @@ static inline void blast_##pfx##cache##lsize(void) \ \ for (ws = 0; ws < ws_end; ws += ws_inc) \ for (addr = start; addr < end; addr += lsize * 32) \ - cache##lsize##_unroll32(addr|ws,indexop); \ + cache##lsize##_unroll32(addr|ws, indexop); \ \ __##pfx##flush_epilogue \ } \ @@ -367,7 +367,7 @@ static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \ __##pfx##flush_prologue \ \ do { \ - cache##lsize##_unroll32(start,hitop); \ + cache##lsize##_unroll32(start, hitop); \ start += lsize * 32; \ } while (start < end); \ \ @@ -388,7 +388,7 @@ static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ for (ws = 0; ws < ws_end; ws += ws_inc) \ for (addr = start; addr < end; addr += lsize * 32) \ - cache##lsize##_unroll32(addr|ws,indexop); \ + cache##lsize##_unroll32(addr|ws, indexop); \ \ __##pfx##flush_epilogue \ } diff --git a/include/asm-mips/semaphore.h b/include/asm-mips/semaphore.h index ea2413c..080daa7 100644 --- a/include/asm-mips/semaphore.h +++ b/include/asm-mips/semaphore.h @@ -46,7 +46,7 @@ struct semaphore { } #define __DECLARE_SEMAPHORE_GENERIC(name, count) \ - struct semaphore name = __SEMAPHORE_INITIALIZER(name,count) + struct semaphore name = __SEMAPHORE_INITIALIZER(name, count) #define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1) #define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0) diff --git a/include/asm-mips/sgiarcs.h b/include/asm-mips/sgiarcs.h index 6d1eda6..721327f 100644 --- a/include/asm-mips/sgiarcs.h +++ b/include/asm-mips/sgiarcs.h @@ -369,8 +369,8 @@ struct linux_smonblock { #if defined(CONFIG_64BIT) && defined(CONFIG_ARC32) #define __arc_clobbers \ - "$2","$3" /* ... */, "$8","$9","$10","$11", \ - "$12","$13","$14","$15","$16","$24","$25","$31" + "$2", "$3" /* ... */, "$8", "$9", "$10", "$11", \ + "$12", "$13", "$14", "$15", "$16", "$24", "$25", "$31" #define ARC_CALL0(dest) \ ({ long __res; \ @@ -382,11 +382,11 @@ struct linux_smonblock { "move\t%0, $2" \ : "=r" (__res), "=r" (__vec) \ : "1" (__vec) \ - : __arc_clobbers, "$4","$5","$6","$7"); \ + : __arc_clobbers, "$4", "$5", "$6", "$7"); \ (unsigned long) __res; \ }) -#define ARC_CALL1(dest,a1) \ +#define ARC_CALL1(dest, a1) \ ({ long __res; \ register signed int __a1 __asm__("$4") = (int) (long) (a1); \ long __vec = (long) romvec->dest; \ @@ -397,11 +397,11 @@ struct linux_smonblock { "move\t%0, $2" \ : "=r" (__res), "=r" (__vec) \ : "1" (__vec), "r" (__a1) \ - : __arc_clobbers, "$5","$6","$7"); \ + : __arc_clobbers, "$5", "$6", "$7"); \ (unsigned long) __res; \ }) -#define ARC_CALL2(dest,a1,a2) \ +#define ARC_CALL2(dest, a1, a2) \ ({ long __res; \ register signed int __a1 __asm__("$4") = (int) (long) (a1); \ register signed int __a2 __asm__("$5") = (int) (long) (a2); \ @@ -413,11 +413,11 @@ struct linux_smonblock { "move\t%0, $2" \ : "=r" (__res), "=r" (__vec) \ : "1" (__vec), "r" (__a1), "r" (__a2) \ - : __arc_clobbers, "$6","$7"); \ + : __arc_clobbers, "$6", "$7"); \ __res; \ }) -#define ARC_CALL3(dest,a1,a2,a3) \ +#define ARC_CALL3(dest, a1, a2, a3) \ ({ long __res; \ register signed int __a1 __asm__("$4") = (int) (long) (a1); \ register signed int __a2 __asm__("$5") = (int) (long) (a2); \ @@ -434,7 +434,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL4(dest,a1,a2,a3,a4) \ +#define ARC_CALL4(dest, a1, a2, a3, a4) \ ({ long __res; \ register signed int __a1 __asm__("$4") = (int) (long) (a1); \ register signed int __a2 __asm__("$5") = (int) (long) (a2); \ @@ -453,7 +453,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL5(dest,a1,a2,a3,a4,a5) \ +#define ARC_CALL5(dest, a1, a2, a3, a4, a5) \ ({ long __res; \ register signed int __a1 __asm__("$4") = (int) (long) (a1); \ register signed int __a2 __asm__("$5") = (int) (long) (a2); \ @@ -468,8 +468,8 @@ struct linux_smonblock { "daddu\t$29, 32\n\t" \ "move\t%0, $2" \ : "=r" (__res), "=r" (__vec) \ - : "1" (__vec), \ - "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4), \ + : "1" (__vec), \ + "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4), \ "r" (__a5) \ : __arc_clobbers); \ __res; \ @@ -488,7 +488,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL1(dest,a1) \ +#define ARC_CALL1(dest, a1) \ ({ long __res; \ long __a1 = (long) (a1); \ long (*__vec)(long) = (void *) romvec->dest; \ @@ -497,7 +497,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL2(dest,a1,a2) \ +#define ARC_CALL2(dest, a1, a2) \ ({ long __res; \ long __a1 = (long) (a1); \ long __a2 = (long) (a2); \ @@ -507,7 +507,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL3(dest,a1,a2,a3) \ +#define ARC_CALL3(dest, a1, a2, a3) \ ({ long __res; \ long __a1 = (long) (a1); \ long __a2 = (long) (a2); \ @@ -518,7 +518,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL4(dest,a1,a2,a3,a4) \ +#define ARC_CALL4(dest, a1, a2, a3, a4) \ ({ long __res; \ long __a1 = (long) (a1); \ long __a2 = (long) (a2); \ @@ -530,7 +530,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL5(dest,a1,a2,a3,a4,a5) \ +#define ARC_CALL5(dest, a1, a2, a3, a4, a5) \ ({ long __res; \ long __a1 = (long) (a1); \ long __a2 = (long) (a2); \ diff --git a/include/asm-mips/sibyte/bcm1480_int.h b/include/asm-mips/sibyte/bcm1480_int.h index c0d5206..6109557 100644 --- a/include/asm-mips/sibyte/bcm1480_int.h +++ b/include/asm-mips/sibyte/bcm1480_int.h @@ -157,7 +157,7 @@ * Mask values for each interrupt */ -#define _BCM1480_INT_MASK(w,n) _SB_MAKEMASK(w,((n) & 0x3F)) +#define _BCM1480_INT_MASK(w, n) _SB_MAKEMASK(w, ((n) & 0x3F)) #define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F)) #define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6) @@ -196,7 +196,7 @@ #define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH) #define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW) #define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH) -#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8,K_BCM1480_INT_MBOX_0_0) +#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0) #define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0) #define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1) #define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2) @@ -269,9 +269,9 @@ */ #define S_BCM1480_INT_HT_INTMSG 0 -#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3,S_BCM1480_INT_HT_INTMSG) -#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTMSG) -#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTMSG,M_BCM1480_INT_HT_INTMSG) +#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG) +#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG) +#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG) #define K_BCM1480_INT_HT_INTMSG_FIXED 0 #define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1 @@ -291,14 +291,14 @@ #define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE #define S_BCM1480_INT_HT_INTDEST 5 -#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8,S_BCM1480_INT_HT_INTDEST) -#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTDEST) -#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTDEST,M_BCM1480_INT_HT_INTDEST) +#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST) +#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST) +#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST) #define S_BCM1480_INT_HT_VECTOR 13 -#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8,S_BCM1480_INT_HT_VECTOR) -#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_VECTOR) -#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_VECTOR,M_BCM1480_INT_HT_VECTOR) +#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR) +#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR) +#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR) /* * Vector prefix (Table 4-7) diff --git a/include/asm-mips/sibyte/bcm1480_l2c.h b/include/asm-mips/sibyte/bcm1480_l2c.h index 886b099..fd75817 100644 --- a/include/asm-mips/sibyte/bcm1480_l2c.h +++ b/include/asm-mips/sibyte/bcm1480_l2c.h @@ -40,22 +40,22 @@ */ #define S_BCM1480_L2C_MGMT_INDEX 5 -#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_BCM1480_L2C_MGMT_INDEX) -#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_INDEX) -#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_INDEX,M_BCM1480_L2C_MGMT_INDEX) +#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_MGMT_INDEX) +#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_INDEX) +#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_INDEX, M_BCM1480_L2C_MGMT_INDEX) #define S_BCM1480_L2C_MGMT_WAY 17 -#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3,S_BCM1480_L2C_MGMT_WAY) -#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_WAY) -#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_WAY,M_BCM1480_L2C_MGMT_WAY) +#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_MGMT_WAY) +#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_WAY) +#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_WAY, M_BCM1480_L2C_MGMT_WAY) #define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20) #define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21) #define S_BCM1480_L2C_MGMT_ECC_DIAG 22 -#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2,S_BCM1480_L2C_MGMT_ECC_DIAG) -#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG) -#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG,M_BCM1480_L2C_MGMT_ECC_DIAG) +#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_BCM1480_L2C_MGMT_ECC_DIAG) +#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG) +#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG, M_BCM1480_L2C_MGMT_ECC_DIAG) #define A_BCM1480_L2C_MGMT_TAG_BASE 0x00D0000000 @@ -68,36 +68,36 @@ */ #define S_BCM1480_L2C_TAG_MBZ 0 -#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5,S_BCM1480_L2C_TAG_MBZ) +#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5, S_BCM1480_L2C_TAG_MBZ) #define S_BCM1480_L2C_TAG_INDEX 5 -#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12,S_BCM1480_L2C_TAG_INDEX) -#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_INDEX) -#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_INDEX,M_BCM1480_L2C_TAG_INDEX) +#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_TAG_INDEX) +#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_INDEX) +#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_INDEX, M_BCM1480_L2C_TAG_INDEX) /* Note that index bit 16 is also tag bit 40 */ #define S_BCM1480_L2C_TAG_TAG 17 -#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23,S_BCM1480_L2C_TAG_TAG) -#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_TAG) -#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_TAG,M_BCM1480_L2C_TAG_TAG) +#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23, S_BCM1480_L2C_TAG_TAG) +#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_TAG) +#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_TAG, M_BCM1480_L2C_TAG_TAG) #define S_BCM1480_L2C_TAG_ECC 40 -#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6,S_BCM1480_L2C_TAG_ECC) -#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_ECC) -#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_ECC,M_BCM1480_L2C_TAG_ECC) +#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6, S_BCM1480_L2C_TAG_ECC) +#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_ECC) +#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_ECC, M_BCM1480_L2C_TAG_ECC) #define S_BCM1480_L2C_TAG_WAY 46 -#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3,S_BCM1480_L2C_TAG_WAY) -#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_WAY) -#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_WAY,M_BCM1480_L2C_TAG_WAY) +#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_TAG_WAY) +#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_WAY) +#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_WAY, M_BCM1480_L2C_TAG_WAY) #define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49) #define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50) #define S_BCM1480_L2C_DATA_ECC 51 -#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10,S_BCM1480_L2C_DATA_ECC) -#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_DATA_ECC) -#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x,S_BCM1480_L2C_DATA_ECC,M_BCM1480_L2C_DATA_ECC) +#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10, S_BCM1480_L2C_DATA_ECC) +#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_DATA_ECC) +#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_DATA_ECC, M_BCM1480_L2C_DATA_ECC) /* @@ -105,24 +105,24 @@ */ #define S_BCM1480_L2C_MISC0_WAY_REMOTE 0 -#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_REMOTE) -#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_REMOTE,M_BCM1480_L2C_MISC0_WAY_REMOTE) +#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_REMOTE) +#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_REMOTE, M_BCM1480_L2C_MISC0_WAY_REMOTE) #define S_BCM1480_L2C_MISC0_WAY_LOCAL 8 -#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_LOCAL) -#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_LOCAL,M_BCM1480_L2C_MISC0_WAY_LOCAL) +#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_LOCAL) +#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_LOCAL, M_BCM1480_L2C_MISC0_WAY_LOCAL) #define S_BCM1480_L2C_MISC0_WAY_ENABLE 16 -#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_ENABLE) -#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_ENABLE,M_BCM1480_L2C_MISC0_WAY_ENABLE) +#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_ENABLE) +#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_ENABLE, M_BCM1480_L2C_MISC0_WAY_ENABLE) #define S_BCM1480_L2C_MISC0_CACHE_DISABLE 24 -#define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_DISABLE) -#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_DISABLE,M_BCM1480_L2C_MISC0_CACHE_DISABLE) +#define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_DISABLE) +#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_DISABLE, M_BCM1480_L2C_MISC0_CACHE_DISABLE) #define S_BCM1480_L2C_MISC0_CACHE_QUAD 26 -#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_QUAD) -#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_QUAD,M_BCM1480_L2C_MISC0_CACHE_QUAD) +#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_QUAD) +#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_QUAD, M_BCM1480_L2C_MISC0_CACHE_QUAD) #define S_BCM1480_L2C_MISC0_MC_PRIORITY 30 #define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY) @@ -136,24 +136,24 @@ */ #define S_BCM1480_L2C_MISC1_WAY_AGENT_0 0 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_0) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_0,M_BCM1480_L2C_MISC1_WAY_AGENT_0) +#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_0) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_0, M_BCM1480_L2C_MISC1_WAY_AGENT_0) #define S_BCM1480_L2C_MISC1_WAY_AGENT_1 8 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_1) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_1,M_BCM1480_L2C_MISC1_WAY_AGENT_1) +#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_1) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_1, M_BCM1480_L2C_MISC1_WAY_AGENT_1) #define S_BCM1480_L2C_MISC1_WAY_AGENT_2 16 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_2) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_2,M_BCM1480_L2C_MISC1_WAY_AGENT_2) +#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_2) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_2, M_BCM1480_L2C_MISC1_WAY_AGENT_2) #define S_BCM1480_L2C_MISC1_WAY_AGENT_3 24 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_3) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_3,M_BCM1480_L2C_MISC1_WAY_AGENT_3) +#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_3) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_3, M_BCM1480_L2C_MISC1_WAY_AGENT_3) #define S_BCM1480_L2C_MISC1_WAY_AGENT_4 32 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_4) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_4,M_BCM1480_L2C_MISC1_WAY_AGENT_4) +#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_4) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_4, M_BCM1480_L2C_MISC1_WAY_AGENT_4) /* @@ -161,16 +161,16 @@ */ #define S_BCM1480_L2C_MISC2_WAY_AGENT_8 0 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_8) -#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_8,M_BCM1480_L2C_MISC2_WAY_AGENT_8) +#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_8) +#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_8, M_BCM1480_L2C_MISC2_WAY_AGENT_8) #define S_BCM1480_L2C_MISC2_WAY_AGENT_9 8 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_9) -#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_9,M_BCM1480_L2C_MISC2_WAY_AGENT_9) +#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_9) +#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_9, M_BCM1480_L2C_MISC2_WAY_AGENT_9) #define S_BCM1480_L2C_MISC2_WAY_AGENT_A 16 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_A) -#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_A,M_BCM1480_L2C_MISC2_WAY_AGENT_A) +#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_A) +#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_A, M_BCM1480_L2C_MISC2_WAY_AGENT_A) #endif /* _BCM1480_L2C_H */ diff --git a/include/asm-mips/sibyte/bcm1480_mc.h b/include/asm-mips/sibyte/bcm1480_mc.h index a6a4374..f26a41a 100644 --- a/include/asm-mips/sibyte/bcm1480_mc.h +++ b/include/asm-mips/sibyte/bcm1480_mc.h @@ -40,27 +40,27 @@ */ #define S_BCM1480_MC_INTLV0 0 -#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) -#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) -#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) +#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0) +#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) +#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) #define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0) #define S_BCM1480_MC_INTLV1 8 -#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) -#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) -#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) +#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1) +#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) +#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) #define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0) #define S_BCM1480_MC_INTLV2 16 -#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV2) -#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV2) -#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV2,M_BCM1480_MC_INTLV2) +#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV2) +#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2) +#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2) #define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0) #define S_BCM1480_MC_CS_MODE 32 -#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8,S_BCM1480_MC_CS_MODE) -#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS_MODE) -#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_CS_MODE,M_BCM1480_MC_CS_MODE) +#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8, S_BCM1480_MC_CS_MODE) +#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE) +#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE) #define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0) #define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \ @@ -81,131 +81,131 @@ */ #define S_BCM1480_MC_CS0_START 0 -#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12,S_BCM1480_MC_CS0_START) -#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_START) -#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_START,M_BCM1480_MC_CS0_START) +#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12, S_BCM1480_MC_CS0_START) +#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START) +#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_START) #define S_BCM1480_MC_CS1_START 16 -#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12,S_BCM1480_MC_CS1_START) -#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_START) -#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_START,M_BCM1480_MC_CS1_START) +#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12, S_BCM1480_MC_CS1_START) +#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_START) +#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_START, M_BCM1480_MC_CS1_START) #define S_BCM1480_MC_CS2_START 32 -#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12,S_BCM1480_MC_CS2_START) -#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_START) -#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_START,M_BCM1480_MC_CS2_START) +#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12, S_BCM1480_MC_CS2_START) +#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_START) +#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_START, M_BCM1480_MC_CS2_START) #define S_BCM1480_MC_CS3_START 48 -#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12,S_BCM1480_MC_CS3_START) -#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_START) -#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_START,M_BCM1480_MC_CS3_START) +#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12, S_BCM1480_MC_CS3_START) +#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_START) +#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_START, M_BCM1480_MC_CS3_START) /* * Chip Select End Address Register (Table 83) */ #define S_BCM1480_MC_CS0_END 0 -#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12,S_BCM1480_MC_CS0_END) -#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_END) -#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_END,M_BCM1480_MC_CS0_END) +#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12, S_BCM1480_MC_CS0_END) +#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_END) +#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_END, M_BCM1480_MC_CS0_END) #define S_BCM1480_MC_CS1_END 16 -#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12,S_BCM1480_MC_CS1_END) -#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_END) -#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_END,M_BCM1480_MC_CS1_END) +#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12, S_BCM1480_MC_CS1_END) +#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_END) +#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_END, M_BCM1480_MC_CS1_END) #define S_BCM1480_MC_CS2_END 32 -#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12,S_BCM1480_MC_CS2_END) -#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_END) -#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_END,M_BCM1480_MC_CS2_END) +#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12, S_BCM1480_MC_CS2_END) +#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_END) +#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_END, M_BCM1480_MC_CS2_END) #define S_BCM1480_MC_CS3_END 48 -#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12,S_BCM1480_MC_CS3_END) -#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_END) -#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_END,M_BCM1480_MC_CS3_END) +#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12, S_BCM1480_MC_CS3_END) +#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_END) +#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_END, M_BCM1480_MC_CS3_END) /* * Row Address Bit Select Register 0 (Table 84) */ #define S_BCM1480_MC_ROW00 0 -#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6,S_BCM1480_MC_ROW00) -#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW00) -#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW00,M_BCM1480_MC_ROW00) +#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6, S_BCM1480_MC_ROW00) +#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00) +#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW00, M_BCM1480_MC_ROW00) #define S_BCM1480_MC_ROW01 8 -#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6,S_BCM1480_MC_ROW01) -#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW01) -#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW01,M_BCM1480_MC_ROW01) +#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6, S_BCM1480_MC_ROW01) +#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01) +#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW01, M_BCM1480_MC_ROW01) #define S_BCM1480_MC_ROW02 16 -#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6,S_BCM1480_MC_ROW02) -#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW02) -#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW02,M_BCM1480_MC_ROW02) +#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6, S_BCM1480_MC_ROW02) +#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02) +#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW02, M_BCM1480_MC_ROW02) #define S_BCM1480_MC_ROW03 24 -#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6,S_BCM1480_MC_ROW03) -#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW03) -#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW03,M_BCM1480_MC_ROW03) +#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6, S_BCM1480_MC_ROW03) +#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW03) +#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW03, M_BCM1480_MC_ROW03) #define S_BCM1480_MC_ROW04 32 -#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6,S_BCM1480_MC_ROW04) -#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW04) -#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW04,M_BCM1480_MC_ROW04) +#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6, S_BCM1480_MC_ROW04) +#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW04) +#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW04, M_BCM1480_MC_ROW04) #define S_BCM1480_MC_ROW05 40 -#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6,S_BCM1480_MC_ROW05) -#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW05) -#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW05,M_BCM1480_MC_ROW05) +#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6, S_BCM1480_MC_ROW05) +#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW05) +#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW05, M_BCM1480_MC_ROW05) #define S_BCM1480_MC_ROW06 48 -#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6,S_BCM1480_MC_ROW06) -#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW06) -#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW06,M_BCM1480_MC_ROW06) +#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6, S_BCM1480_MC_ROW06) +#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW06) +#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW06, M_BCM1480_MC_ROW06) #define S_BCM1480_MC_ROW07 56 -#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6,S_BCM1480_MC_ROW07) -#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW07) -#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW07,M_BCM1480_MC_ROW07) +#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6, S_BCM1480_MC_ROW07) +#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW07) +#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW07, M_BCM1480_MC_ROW07) /* * Row Address Bit Select Register 1 (Table 85) */ #define S_BCM1480_MC_ROW08 0 -#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6,S_BCM1480_MC_ROW08) -#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW08) -#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW08,M_BCM1480_MC_ROW08) +#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6, S_BCM1480_MC_ROW08) +#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW08) +#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW08, M_BCM1480_MC_ROW08) #define S_BCM1480_MC_ROW09 8 -#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6,S_BCM1480_MC_ROW09) -#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW09) -#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW09,M_BCM1480_MC_ROW09) +#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6, S_BCM1480_MC_ROW09) +#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW09) +#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW09, M_BCM1480_MC_ROW09) #define S_BCM1480_MC_ROW10 16 -#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6,S_BCM1480_MC_ROW10) -#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW10) -#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW10,M_BCM1480_MC_ROW10) +#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6, S_BCM1480_MC_ROW10) +#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW10) +#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW10, M_BCM1480_MC_ROW10) #define S_BCM1480_MC_ROW11 24 -#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6,S_BCM1480_MC_ROW11) -#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW11) -#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW11,M_BCM1480_MC_ROW11) +#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6, S_BCM1480_MC_ROW11) +#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW11) +#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW11, M_BCM1480_MC_ROW11) #define S_BCM1480_MC_ROW12 32 -#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6,S_BCM1480_MC_ROW12) -#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW12) -#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW12,M_BCM1480_MC_ROW12) +#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6, S_BCM1480_MC_ROW12) +#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW12) +#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW12, M_BCM1480_MC_ROW12) #define S_BCM1480_MC_ROW13 40 -#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6,S_BCM1480_MC_ROW13) -#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW13) -#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW13,M_BCM1480_MC_ROW13) +#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6, S_BCM1480_MC_ROW13) +#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW13) +#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW13, M_BCM1480_MC_ROW13) #define S_BCM1480_MC_ROW14 48 -#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6,S_BCM1480_MC_ROW14) -#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW14) -#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW14,M_BCM1480_MC_ROW14) +#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6, S_BCM1480_MC_ROW14) +#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW14) +#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW14, M_BCM1480_MC_ROW14) #define K_BCM1480_MC_ROWX_BIT_SPACING 8 @@ -214,80 +214,80 @@ */ #define S_BCM1480_MC_COL00 0 -#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6,S_BCM1480_MC_COL00) -#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL00) -#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x,S_BCM1480_MC_COL00,M_BCM1480_MC_COL00) +#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6, S_BCM1480_MC_COL00) +#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL00) +#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x, S_BCM1480_MC_COL00, M_BCM1480_MC_COL00) #define S_BCM1480_MC_COL01 8 -#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6,S_BCM1480_MC_COL01) -#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL01) -#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x,S_BCM1480_MC_COL01,M_BCM1480_MC_COL01) +#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6, S_BCM1480_MC_COL01) +#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL01) +#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x, S_BCM1480_MC_COL01, M_BCM1480_MC_COL01) #define S_BCM1480_MC_COL02 16 -#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6,S_BCM1480_MC_COL02) -#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL02) -#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x,S_BCM1480_MC_COL02,M_BCM1480_MC_COL02) +#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6, S_BCM1480_MC_COL02) +#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL02) +#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x, S_BCM1480_MC_COL02, M_BCM1480_MC_COL02) #define S_BCM1480_MC_COL03 24 -#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6,S_BCM1480_MC_COL03) -#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL03) -#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x,S_BCM1480_MC_COL03,M_BCM1480_MC_COL03) +#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6, S_BCM1480_MC_COL03) +#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL03) +#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x, S_BCM1480_MC_COL03, M_BCM1480_MC_COL03) #define S_BCM1480_MC_COL04 32 -#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6,S_BCM1480_MC_COL04) -#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL04) -#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x,S_BCM1480_MC_COL04,M_BCM1480_MC_COL04) +#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6, S_BCM1480_MC_COL04) +#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL04) +#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x, S_BCM1480_MC_COL04, M_BCM1480_MC_COL04) #define S_BCM1480_MC_COL05 40 -#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6,S_BCM1480_MC_COL05) -#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL05) -#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x,S_BCM1480_MC_COL05,M_BCM1480_MC_COL05) +#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6, S_BCM1480_MC_COL05) +#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL05) +#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x, S_BCM1480_MC_COL05, M_BCM1480_MC_COL05) #define S_BCM1480_MC_COL06 48 -#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6,S_BCM1480_MC_COL06) -#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL06) -#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x,S_BCM1480_MC_COL06,M_BCM1480_MC_COL06) +#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6, S_BCM1480_MC_COL06) +#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL06) +#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x, S_BCM1480_MC_COL06, M_BCM1480_MC_COL06) #define S_BCM1480_MC_COL07 56 -#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6,S_BCM1480_MC_COL07) -#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL07) -#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x,S_BCM1480_MC_COL07,M_BCM1480_MC_COL07) +#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6, S_BCM1480_MC_COL07) +#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL07) +#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x, S_BCM1480_MC_COL07, M_BCM1480_MC_COL07) /* * Column Address Bit Select Register 1 (Table 87) */ #define S_BCM1480_MC_COL08 0 -#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6,S_BCM1480_MC_COL08) -#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL08) -#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x,S_BCM1480_MC_COL08,M_BCM1480_MC_COL08) +#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6, S_BCM1480_MC_COL08) +#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL08) +#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x, S_BCM1480_MC_COL08, M_BCM1480_MC_COL08) #define S_BCM1480_MC_COL09 8 -#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6,S_BCM1480_MC_COL09) -#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL09) -#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x,S_BCM1480_MC_COL09,M_BCM1480_MC_COL09) +#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6, S_BCM1480_MC_COL09) +#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL09) +#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x, S_BCM1480_MC_COL09, M_BCM1480_MC_COL09) #define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */ #define S_BCM1480_MC_COL11 24 -#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6,S_BCM1480_MC_COL11) -#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL11) -#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x,S_BCM1480_MC_COL11,M_BCM1480_MC_COL11) +#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6, S_BCM1480_MC_COL11) +#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL11) +#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x, S_BCM1480_MC_COL11, M_BCM1480_MC_COL11) #define S_BCM1480_MC_COL12 32 -#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6,S_BCM1480_MC_COL12) -#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL12) -#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x,S_BCM1480_MC_COL12,M_BCM1480_MC_COL12) +#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6, S_BCM1480_MC_COL12) +#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL12) +#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x, S_BCM1480_MC_COL12, M_BCM1480_MC_COL12) #define S_BCM1480_MC_COL13 40 -#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6,S_BCM1480_MC_COL13) -#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL13) -#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x,S_BCM1480_MC_COL13,M_BCM1480_MC_COL13) +#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6, S_BCM1480_MC_COL13) +#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL13) +#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x, S_BCM1480_MC_COL13, M_BCM1480_MC_COL13) #define S_BCM1480_MC_COL14 48 -#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6,S_BCM1480_MC_COL14) -#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL14) -#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x,S_BCM1480_MC_COL14,M_BCM1480_MC_COL14) +#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6, S_BCM1480_MC_COL14) +#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL14) +#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x, S_BCM1480_MC_COL14, M_BCM1480_MC_COL14) #define K_BCM1480_MC_COLX_BIT_SPACING 8 @@ -296,38 +296,38 @@ */ #define S_BCM1480_MC_CS01_BANK0 0 -#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK0) -#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK0) -#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK0,M_BCM1480_MC_CS01_BANK0) +#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK0) +#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK0) +#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK0, M_BCM1480_MC_CS01_BANK0) #define S_BCM1480_MC_CS01_BANK1 8 -#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK1) -#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK1) -#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK1,M_BCM1480_MC_CS01_BANK1) +#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK1) +#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK1) +#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK1, M_BCM1480_MC_CS01_BANK1) #define S_BCM1480_MC_CS01_BANK2 16 -#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK2) -#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK2) -#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK2,M_BCM1480_MC_CS01_BANK2) +#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK2) +#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK2) +#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK2, M_BCM1480_MC_CS01_BANK2) /* * CS2 and CS3 Bank Address Bit Select Register (Table 89) */ #define S_BCM1480_MC_CS23_BANK0 0 -#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK0) -#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK0) -#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK0,M_BCM1480_MC_CS23_BANK0) +#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK0) +#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK0) +#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK0, M_BCM1480_MC_CS23_BANK0) #define S_BCM1480_MC_CS23_BANK1 8 -#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK1) -#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK1) -#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK1,M_BCM1480_MC_CS23_BANK1) +#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK1) +#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK1) +#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK1, M_BCM1480_MC_CS23_BANK1) #define S_BCM1480_MC_CS23_BANK2 16 -#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK2) -#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK2) -#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK2,M_BCM1480_MC_CS23_BANK2) +#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK2) +#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK2) +#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK2, M_BCM1480_MC_CS23_BANK2) #define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8 @@ -336,9 +336,9 @@ */ #define S_BCM1480_MC_COMMAND 0 -#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4,S_BCM1480_MC_COMMAND) -#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COMMAND) -#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x,S_BCM1480_MC_COMMAND,M_BCM1480_MC_COMMAND) +#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4, S_BCM1480_MC_COMMAND) +#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COMMAND) +#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x, S_BCM1480_MC_COMMAND, M_BCM1480_MC_COMMAND) #define K_BCM1480_MC_COMMAND_EMRS 0 #define K_BCM1480_MC_COMMAND_MRS 1 @@ -382,9 +382,9 @@ #define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) #define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) -#define M_BCM1480_MC_CS _SB_MAKEMASK(8,S_BCM1480_MC_CS0) -#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0) -#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0,M_BCM1480_MC_CS0) +#define M_BCM1480_MC_CS _SB_MAKEMASK(8, S_BCM1480_MC_CS0) +#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0) +#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0, M_BCM1480_MC_CS0) #define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) @@ -393,21 +393,21 @@ */ #define S_BCM1480_MC_EMODE 0 -#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15,S_BCM1480_MC_EMODE) -#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_EMODE) -#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x,S_BCM1480_MC_EMODE,M_BCM1480_MC_EMODE) +#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15, S_BCM1480_MC_EMODE) +#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_EMODE) +#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x, S_BCM1480_MC_EMODE, M_BCM1480_MC_EMODE) #define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0) #define S_BCM1480_MC_MODE 16 -#define M_BCM1480_MC_MODE _SB_MAKEMASK(15,S_BCM1480_MC_MODE) -#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MODE) -#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_MODE,M_BCM1480_MC_MODE) +#define M_BCM1480_MC_MODE _SB_MAKEMASK(15, S_BCM1480_MC_MODE) +#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MODE) +#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_MODE, M_BCM1480_MC_MODE) #define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0) #define S_BCM1480_MC_DRAM_TYPE 32 -#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4,S_BCM1480_MC_DRAM_TYPE) -#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DRAM_TYPE) -#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_BCM1480_MC_DRAM_TYPE,M_BCM1480_MC_DRAM_TYPE) +#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4, S_BCM1480_MC_DRAM_TYPE) +#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DRAM_TYPE) +#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_BCM1480_MC_DRAM_TYPE, M_BCM1480_MC_DRAM_TYPE) #define K_BCM1480_MC_DRAM_TYPE_JEDEC 0 #define K_BCM1480_MC_DRAM_TYPE_FCRAM 1 @@ -431,9 +431,9 @@ #define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39) #define S_BCM1480_MC_PG_POLICY 40 -#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2,S_BCM1480_MC_PG_POLICY) -#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PG_POLICY) -#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x,S_BCM1480_MC_PG_POLICY,M_BCM1480_MC_PG_POLICY) +#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2, S_BCM1480_MC_PG_POLICY) +#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PG_POLICY) +#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x, S_BCM1480_MC_PG_POLICY, M_BCM1480_MC_PG_POLICY) #define K_BCM1480_MC_PG_POLICY_CLOSED 0 #define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1 @@ -454,16 +454,16 @@ */ #define S_BCM1480_MC_CLK_RATIO 0 -#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6,S_BCM1480_MC_CLK_RATIO) -#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CLK_RATIO) -#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_BCM1480_MC_CLK_RATIO,M_BCM1480_MC_CLK_RATIO) +#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6, S_BCM1480_MC_CLK_RATIO) +#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CLK_RATIO) +#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_BCM1480_MC_CLK_RATIO, M_BCM1480_MC_CLK_RATIO) #define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10) #define S_BCM1480_MC_REF_RATE 8 -#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8,S_BCM1480_MC_REF_RATE) -#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_REF_RATE) -#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x,S_BCM1480_MC_REF_RATE,M_BCM1480_MC_REF_RATE) +#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8, S_BCM1480_MC_REF_RATE) +#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_REF_RATE) +#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x, S_BCM1480_MC_REF_RATE, M_BCM1480_MC_REF_RATE) #define K_BCM1480_MC_REF_RATE_100MHz 0x31 #define K_BCM1480_MC_REF_RATE_200MHz 0x62 @@ -519,20 +519,20 @@ #define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32) #define S_BCM1480_MC_ODT0 0 -#define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8,S_BCM1480_MC_ODT0) -#define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT0) +#define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8, S_BCM1480_MC_ODT0) +#define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT0) #define S_BCM1480_MC_ODT2 8 -#define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8,S_BCM1480_MC_ODT2) -#define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT2) +#define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8, S_BCM1480_MC_ODT2) +#define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT2) #define S_BCM1480_MC_ODT4 16 -#define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8,S_BCM1480_MC_ODT4) -#define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT4) +#define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8, S_BCM1480_MC_ODT4) +#define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT4) #define S_BCM1480_MC_ODT6 24 -#define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8,S_BCM1480_MC_ODT6) -#define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT6) +#define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8, S_BCM1480_MC_ODT6) +#define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT6) #endif /* @@ -540,70 +540,70 @@ */ #define S_BCM1480_MC_ADDR_COARSE_ADJ 0 -#define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_ADDR_COARSE_ADJ) -#define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ) -#define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ,M_BCM1480_MC_ADDR_COARSE_ADJ) +#define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_ADDR_COARSE_ADJ) +#define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ) +#define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ, M_BCM1480_MC_ADDR_COARSE_ADJ) #define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_ADDR_FREQ_RANGE 8 -#define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FREQ_RANGE) -#define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE) -#define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE,M_BCM1480_MC_ADDR_FREQ_RANGE) +#define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FREQ_RANGE) +#define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE) +#define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE, M_BCM1480_MC_ADDR_FREQ_RANGE) #define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4) #endif #define S_BCM1480_MC_ADDR_FINE_ADJ 8 -#define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FINE_ADJ) -#define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ) -#define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ,M_BCM1480_MC_ADDR_FINE_ADJ) +#define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FINE_ADJ) +#define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ) +#define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ, M_BCM1480_MC_ADDR_FINE_ADJ) #define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8) #define S_BCM1480_MC_DQI_COARSE_ADJ 16 -#define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQI_COARSE_ADJ) -#define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ) -#define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ,M_BCM1480_MC_DQI_COARSE_ADJ) +#define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQI_COARSE_ADJ) +#define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ) +#define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ, M_BCM1480_MC_DQI_COARSE_ADJ) #define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DQI_FREQ_RANGE 24 -#define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FREQ_RANGE) -#define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE) -#define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE,M_BCM1480_MC_DQI_FREQ_RANGE) +#define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FREQ_RANGE) +#define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE) +#define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE, M_BCM1480_MC_DQI_FREQ_RANGE) #define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4) #endif #define S_BCM1480_MC_DQI_FINE_ADJ 24 -#define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FINE_ADJ) -#define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ) -#define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ,M_BCM1480_MC_DQI_FINE_ADJ) +#define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FINE_ADJ) +#define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ) +#define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ, M_BCM1480_MC_DQI_FINE_ADJ) #define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8) #define S_BCM1480_MC_DQO_COARSE_ADJ 32 -#define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQO_COARSE_ADJ) -#define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ) -#define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ,M_BCM1480_MC_DQO_COARSE_ADJ) +#define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQO_COARSE_ADJ) +#define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ) +#define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ, M_BCM1480_MC_DQO_COARSE_ADJ) #define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DQO_FREQ_RANGE 40 -#define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FREQ_RANGE) -#define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE) -#define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE,M_BCM1480_MC_DQO_FREQ_RANGE) +#define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FREQ_RANGE) +#define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE) +#define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE, M_BCM1480_MC_DQO_FREQ_RANGE) #define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4) #endif #define S_BCM1480_MC_DQO_FINE_ADJ 40 -#define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FINE_ADJ) -#define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ) -#define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ,M_BCM1480_MC_DQO_FINE_ADJ) +#define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FINE_ADJ) +#define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ) +#define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ, M_BCM1480_MC_DQO_FINE_ADJ) #define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DLL_PDSEL 44 -#define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_PDSEL) -#define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_PDSEL) -#define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_PDSEL,M_BCM1480_MC_DLL_PDSEL) +#define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_PDSEL) +#define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_PDSEL) +#define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_PDSEL, M_BCM1480_MC_DLL_PDSEL) #define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0) #define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46) @@ -611,38 +611,38 @@ #endif #define S_BCM1480_MC_DLL_DEFAULT 48 -#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT) -#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT) -#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT) +#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6, S_BCM1480_MC_DLL_DEFAULT) +#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_DEFAULT) +#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_DEFAULT, M_BCM1480_MC_DLL_DEFAULT) #define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DLL_REGCTRL 54 -#define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_REGCTRL) -#define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_REGCTRL) -#define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_REGCTRL,M_BCM1480_MC_DLL_REGCTRL) +#define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_REGCTRL) +#define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_REGCTRL) +#define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_REGCTRL, M_BCM1480_MC_DLL_REGCTRL) #define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0) #endif #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DLL_FREQ_RANGE 56 -#define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_FREQ_RANGE) -#define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE) -#define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE,M_BCM1480_MC_DLL_FREQ_RANGE) +#define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_FREQ_RANGE) +#define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE) +#define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE, M_BCM1480_MC_DLL_FREQ_RANGE) #define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4) #endif #define S_BCM1480_MC_DLL_STEP_SIZE 56 -#define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_STEP_SIZE) -#define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE) -#define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE,M_BCM1480_MC_DLL_STEP_SIZE) +#define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_STEP_SIZE) +#define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE) +#define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE, M_BCM1480_MC_DLL_STEP_SIZE) #define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DLL_BGCTRL 60 -#define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_BGCTRL) -#define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_BGCTRL) -#define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_BGCTRL,M_BCM1480_MC_DLL_BGCTRL) +#define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_BGCTRL) +#define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_BGCTRL) +#define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_BGCTRL, M_BCM1480_MC_DLL_BGCTRL) #define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0) #endif @@ -653,37 +653,37 @@ */ #define S_BCM1480_MC_RTT_BYP_PULLDOWN 0 -#define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLDOWN) -#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN) -#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN,M_BCM1480_MC_RTT_BYP_PULLDOWN) +#define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLDOWN) +#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN) +#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN, M_BCM1480_MC_RTT_BYP_PULLDOWN) #define S_BCM1480_MC_RTT_BYP_PULLUP 6 -#define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLUP) -#define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP) -#define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP,M_BCM1480_MC_RTT_BYP_PULLUP) +#define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLUP) +#define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP) +#define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP, M_BCM1480_MC_RTT_BYP_PULLUP) #define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8) #define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9) #define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10 -#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) -#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) -#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN,M_BCM1480_MC_PVT_BYP_C1_PULLDOWN) +#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) +#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) +#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN, M_BCM1480_MC_PVT_BYP_C1_PULLDOWN) #define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15 -#define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLUP) -#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP) -#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP,M_BCM1480_MC_PVT_BYP_C1_PULLUP) +#define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLUP) +#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP) +#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP, M_BCM1480_MC_PVT_BYP_C1_PULLUP) #define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN 20 -#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) -#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) -#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN,M_BCM1480_MC_PVT_BYP_C2_PULLDOWN) +#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) +#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) +#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN, M_BCM1480_MC_PVT_BYP_C2_PULLDOWN) #define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25 -#define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLUP) -#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP) -#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP,M_BCM1480_MC_PVT_BYP_C2_PULLUP) +#define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLUP) +#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP) +#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP, M_BCM1480_MC_PVT_BYP_C2_PULLUP) #define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30) #define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31) @@ -703,111 +703,111 @@ */ #define S_BCM1480_MC_DATA_INVERT 0 -#define M_DATA_ECC_INVERT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_INVERT) +#define M_DATA_ECC_INVERT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_INVERT) /* * ECC Test ECC Register (Table 96) */ #define S_BCM1480_MC_ECC_INVERT 0 -#define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8,S_BCM1480_MC_ECC_INVERT) +#define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8, S_BCM1480_MC_ECC_INVERT) /* * SDRAM Timing Register (Table 97) */ #define S_BCM1480_MC_tRCD 0 -#define M_BCM1480_MC_tRCD _SB_MAKEMASK(4,S_BCM1480_MC_tRCD) -#define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCD) -#define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCD,M_BCM1480_MC_tRCD) +#define M_BCM1480_MC_tRCD _SB_MAKEMASK(4, S_BCM1480_MC_tRCD) +#define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCD) +#define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCD, M_BCM1480_MC_tRCD) #define K_BCM1480_MC_tRCD_DEFAULT 3 #define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT) #define S_BCM1480_MC_tCL 4 -#define M_BCM1480_MC_tCL _SB_MAKEMASK(4,S_BCM1480_MC_tCL) -#define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCL) -#define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x,S_BCM1480_MC_tCL,M_BCM1480_MC_tCL) +#define M_BCM1480_MC_tCL _SB_MAKEMASK(4, S_BCM1480_MC_tCL) +#define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCL) +#define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x, S_BCM1480_MC_tCL, M_BCM1480_MC_tCL) #define K_BCM1480_MC_tCL_DEFAULT 2 #define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT) #define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8) #define S_BCM1480_MC_tWR 9 -#define M_BCM1480_MC_tWR _SB_MAKEMASK(3,S_BCM1480_MC_tWR) -#define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tWR) -#define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x,S_BCM1480_MC_tWR,M_BCM1480_MC_tWR) +#define M_BCM1480_MC_tWR _SB_MAKEMASK(3, S_BCM1480_MC_tWR) +#define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tWR) +#define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x, S_BCM1480_MC_tWR, M_BCM1480_MC_tWR) #define K_BCM1480_MC_tWR_DEFAULT 2 #define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT) #define S_BCM1480_MC_tCwD 12 -#define M_BCM1480_MC_tCwD _SB_MAKEMASK(4,S_BCM1480_MC_tCwD) -#define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCwD) -#define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x,S_BCM1480_MC_tCwD,M_BCM1480_MC_tCwD) +#define M_BCM1480_MC_tCwD _SB_MAKEMASK(4, S_BCM1480_MC_tCwD) +#define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCwD) +#define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x, S_BCM1480_MC_tCwD, M_BCM1480_MC_tCwD) #define K_BCM1480_MC_tCwD_DEFAULT 1 #define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT) #define S_BCM1480_MC_tRP 16 -#define M_BCM1480_MC_tRP _SB_MAKEMASK(4,S_BCM1480_MC_tRP) -#define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRP) -#define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRP,M_BCM1480_MC_tRP) +#define M_BCM1480_MC_tRP _SB_MAKEMASK(4, S_BCM1480_MC_tRP) +#define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRP) +#define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRP, M_BCM1480_MC_tRP) #define K_BCM1480_MC_tRP_DEFAULT 4 #define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT) #define S_BCM1480_MC_tRRD 20 -#define M_BCM1480_MC_tRRD _SB_MAKEMASK(4,S_BCM1480_MC_tRRD) -#define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRRD) -#define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRRD,M_BCM1480_MC_tRRD) +#define M_BCM1480_MC_tRRD _SB_MAKEMASK(4, S_BCM1480_MC_tRRD) +#define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRRD) +#define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRRD, M_BCM1480_MC_tRRD) #define K_BCM1480_MC_tRRD_DEFAULT 2 #define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT) #define S_BCM1480_MC_tRCw 24 -#define M_BCM1480_MC_tRCw _SB_MAKEMASK(5,S_BCM1480_MC_tRCw) -#define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCw) -#define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCw,M_BCM1480_MC_tRCw) +#define M_BCM1480_MC_tRCw _SB_MAKEMASK(5, S_BCM1480_MC_tRCw) +#define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCw) +#define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCw, M_BCM1480_MC_tRCw) #define K_BCM1480_MC_tRCw_DEFAULT 10 #define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT) #define S_BCM1480_MC_tRCr 32 -#define M_BCM1480_MC_tRCr _SB_MAKEMASK(5,S_BCM1480_MC_tRCr) -#define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCr) -#define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCr,M_BCM1480_MC_tRCr) +#define M_BCM1480_MC_tRCr _SB_MAKEMASK(5, S_BCM1480_MC_tRCr) +#define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCr) +#define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCr, M_BCM1480_MC_tRCr) #define K_BCM1480_MC_tRCr_DEFAULT 9 #define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_tFAW 40 -#define M_BCM1480_MC_tFAW _SB_MAKEMASK(6,S_BCM1480_MC_tFAW) -#define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFAW) -#define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x,S_BCM1480_MC_tFAW,M_BCM1480_MC_tFAW) +#define M_BCM1480_MC_tFAW _SB_MAKEMASK(6, S_BCM1480_MC_tFAW) +#define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFAW) +#define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x, S_BCM1480_MC_tFAW, M_BCM1480_MC_tFAW) #define K_BCM1480_MC_tFAW_DEFAULT 0 #define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT) #endif #define S_BCM1480_MC_tRFC 48 -#define M_BCM1480_MC_tRFC _SB_MAKEMASK(7,S_BCM1480_MC_tRFC) -#define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRFC) -#define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x,S_BCM1480_MC_tRFC,M_BCM1480_MC_tRFC) +#define M_BCM1480_MC_tRFC _SB_MAKEMASK(7, S_BCM1480_MC_tRFC) +#define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRFC) +#define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x, S_BCM1480_MC_tRFC, M_BCM1480_MC_tRFC) #define K_BCM1480_MC_tRFC_DEFAULT 12 #define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT) #define S_BCM1480_MC_tFIFO 56 -#define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2,S_BCM1480_MC_tFIFO) -#define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFIFO) -#define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x,S_BCM1480_MC_tFIFO,M_BCM1480_MC_tFIFO) +#define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2, S_BCM1480_MC_tFIFO) +#define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFIFO) +#define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x, S_BCM1480_MC_tFIFO, M_BCM1480_MC_tFIFO) #define K_BCM1480_MC_tFIFO_DEFAULT 0 #define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT) #define S_BCM1480_MC_tW2R 58 -#define M_BCM1480_MC_tW2R _SB_MAKEMASK(2,S_BCM1480_MC_tW2R) -#define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2R) -#define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2R,M_BCM1480_MC_tW2R) +#define M_BCM1480_MC_tW2R _SB_MAKEMASK(2, S_BCM1480_MC_tW2R) +#define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2R) +#define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2R, M_BCM1480_MC_tW2R) #define K_BCM1480_MC_tW2R_DEFAULT 1 #define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT) #define S_BCM1480_MC_tR2W 60 -#define M_BCM1480_MC_tR2W _SB_MAKEMASK(2,S_BCM1480_MC_tR2W) -#define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tR2W) -#define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tR2W,M_BCM1480_MC_tR2W) +#define M_BCM1480_MC_tR2W _SB_MAKEMASK(2, S_BCM1480_MC_tR2W) +#define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tR2W) +#define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tR2W, M_BCM1480_MC_tR2W) #define K_BCM1480_MC_tR2W_DEFAULT 0 #define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT) @@ -835,30 +835,30 @@ #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_tAL 0 -#define M_BCM1480_MC_tAL _SB_MAKEMASK(4,S_BCM1480_MC_tAL) -#define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tAL) -#define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x,S_BCM1480_MC_tAL,M_BCM1480_MC_tAL) +#define M_BCM1480_MC_tAL _SB_MAKEMASK(4, S_BCM1480_MC_tAL) +#define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tAL) +#define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x, S_BCM1480_MC_tAL, M_BCM1480_MC_tAL) #define K_BCM1480_MC_tAL_DEFAULT 0 #define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT) #define S_BCM1480_MC_tRTP 4 -#define M_BCM1480_MC_tRTP _SB_MAKEMASK(3,S_BCM1480_MC_tRTP) -#define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRTP) -#define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRTP,M_BCM1480_MC_tRTP) +#define M_BCM1480_MC_tRTP _SB_MAKEMASK(3, S_BCM1480_MC_tRTP) +#define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRTP) +#define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRTP, M_BCM1480_MC_tRTP) #define K_BCM1480_MC_tRTP_DEFAULT 2 #define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT) #define S_BCM1480_MC_tW2W 8 -#define M_BCM1480_MC_tW2W _SB_MAKEMASK(2,S_BCM1480_MC_tW2W) -#define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2W) -#define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2W,M_BCM1480_MC_tW2W) +#define M_BCM1480_MC_tW2W _SB_MAKEMASK(2, S_BCM1480_MC_tW2W) +#define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2W) +#define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2W, M_BCM1480_MC_tW2W) #define K_BCM1480_MC_tW2W_DEFAULT 0 #define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT) #define S_BCM1480_MC_tRAP 12 -#define M_BCM1480_MC_tRAP _SB_MAKEMASK(4,S_BCM1480_MC_tRAP) -#define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRAP) -#define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRAP,M_BCM1480_MC_tRAP) +#define M_BCM1480_MC_tRAP _SB_MAKEMASK(4, S_BCM1480_MC_tRAP) +#define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRAP) +#define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRAP, M_BCM1480_MC_tRAP) #define K_BCM1480_MC_tRAP_DEFAULT 0 #define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT) @@ -875,30 +875,30 @@ */ #define S_BCM1480_MC_BLK_SET_MARK 8 -#define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_SET_MARK) -#define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_SET_MARK) -#define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_SET_MARK,M_BCM1480_MC_BLK_SET_MARK) +#define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_SET_MARK) +#define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_SET_MARK) +#define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_SET_MARK, M_BCM1480_MC_BLK_SET_MARK) #define S_BCM1480_MC_BLK_CLR_MARK 12 -#define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_CLR_MARK) -#define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_CLR_MARK) -#define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_CLR_MARK,M_BCM1480_MC_BLK_CLR_MARK) +#define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_CLR_MARK) +#define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_CLR_MARK) +#define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_CLR_MARK, M_BCM1480_MC_BLK_CLR_MARK) #define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16) #define S_BCM1480_MC_MAX_AGE 20 -#define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4,S_BCM1480_MC_MAX_AGE) -#define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MAX_AGE) -#define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x,S_BCM1480_MC_MAX_AGE,M_BCM1480_MC_MAX_AGE) +#define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4, S_BCM1480_MC_MAX_AGE) +#define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MAX_AGE) +#define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x, S_BCM1480_MC_MAX_AGE, M_BCM1480_MC_MAX_AGE) #define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29) #define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30) #define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32) #define S_BCM1480_MC_SLEW 33 -#define M_BCM1480_MC_SLEW _SB_MAKEMASK(2,S_BCM1480_MC_SLEW) -#define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_SLEW) -#define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x,S_BCM1480_MC_SLEW,M_BCM1480_MC_SLEW) +#define M_BCM1480_MC_SLEW _SB_MAKEMASK(2, S_BCM1480_MC_SLEW) +#define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_SLEW) +#define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x, S_BCM1480_MC_SLEW, M_BCM1480_MC_SLEW) #define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35) @@ -907,19 +907,19 @@ */ #define S_BCM1480_MC_INTLV0 0 -#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) -#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) -#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) +#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0) +#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) +#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) #define S_BCM1480_MC_INTLV1 8 -#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) -#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) -#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) +#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1) +#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) +#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) #define S_BCM1480_MC_INTLV_MODE 16 -#define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3,S_BCM1480_MC_INTLV_MODE) -#define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV_MODE) -#define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV_MODE,M_BCM1480_MC_INTLV_MODE) +#define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3, S_BCM1480_MC_INTLV_MODE) +#define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV_MODE) +#define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV_MODE, M_BCM1480_MC_INTLV_MODE) #define K_BCM1480_MC_INTLV_MODE_NONE 0x0 #define K_BCM1480_MC_INTLV_MODE_01 0x1 @@ -938,9 +938,9 @@ */ #define S_BCM1480_MC_ECC_ERR_ADDR 0 -#define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_ERR_ADDR) -#define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR) -#define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR,M_BCM1480_MC_ECC_ERR_ADDR) +#define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_ERR_ADDR) +#define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR) +#define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR, M_BCM1480_MC_ECC_ERR_ADDR) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60) @@ -955,27 +955,27 @@ */ #define S_BCM1480_MC_ECC_CORR_ADDR 0 -#define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_CORR_ADDR) -#define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR) -#define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR,M_BCM1480_MC_ECC_CORR_ADDR) +#define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_CORR_ADDR) +#define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR) +#define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR, M_BCM1480_MC_ECC_CORR_ADDR) /* * Global ECC Correction Register (Table 103) */ #define S_BCM1480_MC_ECC_CORRECT 0 -#define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_CORRECT) -#define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORRECT) -#define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORRECT,M_BCM1480_MC_ECC_CORRECT) +#define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_CORRECT) +#define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORRECT) +#define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORRECT, M_BCM1480_MC_ECC_CORRECT) /* * Global ECC Performance Counters Control Register (Table 104) */ #define S_BCM1480_MC_CHANNEL_SELECT 0 -#define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4,S_BCM1480_MC_CHANNEL_SELECT) -#define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CHANNEL_SELECT) -#define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x,S_BCM1480_MC_CHANNEL_SELECT,M_BCM1480_MC_CHANNEL_SELECT) +#define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4, S_BCM1480_MC_CHANNEL_SELECT) +#define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CHANNEL_SELECT) +#define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x, S_BCM1480_MC_CHANNEL_SELECT, M_BCM1480_MC_CHANNEL_SELECT) #define K_BCM1480_MC_CHANNEL_SELECT_0 0x1 #define K_BCM1480_MC_CHANNEL_SELECT_1 0x2 #define K_BCM1480_MC_CHANNEL_SELECT_2 0x4 diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h index c34d36b..b4077bb 100644 --- a/include/asm-mips/sibyte/bcm1480_regs.h +++ b/include/asm-mips/sibyte/bcm1480_regs.h @@ -87,7 +87,7 @@ #define BCM1480_MC_REGISTER_SPACING 0x1000 #define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING) -#define A_BCM1480_MC_REGISTER(ctlid,reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) +#define A_BCM1480_MC_REGISTER(ctlid, reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) #define R_BCM1480_MC_CONFIG 0x0000000100 #define R_BCM1480_MC_CS_START 0x0000000120 @@ -327,7 +327,7 @@ #define BCM1480_SCD_NUM_WDOGS 4 #define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100) -#define A_BCM1480_SCD_WDOG_REGISTER(w,r) (A_BCM1480_SCD_WDOG_BASE(w) + (r)) +#define A_BCM1480_SCD_WDOG_REGISTER(w, r) (A_BCM1480_SCD_WDOG_BASE(w) + (r)) #define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050 #define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058 @@ -372,7 +372,7 @@ #define BCM1480_IMR_REGISTER_SPACING_SHIFT 13 #define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING) -#define A_BCM1480_IMR_REGISTER(cpu,reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) +#define A_BCM1480_IMR_REGISTER(cpu, reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) /* Most IMR registers are 128 bits, implemented as non-contiguous 64-bit registers high (_H) and low (_L) */ @@ -413,7 +413,7 @@ #define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \ (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING) -#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu,reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) +#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu, reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) #define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ #define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ @@ -427,7 +427,7 @@ #define R_BCM1480_IMR_MAILBOX_SET 0x08 #define R_BCM1480_IMR_MAILBOX_CLR 0x10 #define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20 -#define A_BCM1480_MAILBOX_REGISTER(num,reg,cpu) \ +#define A_BCM1480_MAILBOX_REGISTER(num, reg, cpu) \ (A_BCM1480_IMR_CPU0_BASE + \ (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \ (cpu * BCM1480_IMR_REGISTER_SPACING) + \ @@ -550,7 +550,7 @@ #define BCM1480_HR_REGISTER_SPACING 0x80000 #define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING)) -#define A_BCM1480_HR_REGISTER(idx,reg) (A_BCM1480_HR_BASE(idx) + (reg)) +#define A_BCM1480_HR_REGISTER(idx, reg) (A_BCM1480_HR_BASE(idx) + (reg)) #define R_BCM1480_HR_CFG 0x0000000000 @@ -599,9 +599,9 @@ #define BCM1480_PM_NUM_CHANNELS 32 #define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) -#define A_BCM1480_PMI_LCL_REGISTER(idx,reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) +#define A_BCM1480_PMI_LCL_REGISTER(idx, reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) #define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) -#define A_BCM1480_PMO_LCL_REGISTER(idx,reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) +#define A_BCM1480_PMO_LCL_REGISTER(idx, reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) #define BCM1480_PM_INT_PACKING 8 #define BCM1480_PM_INT_FUNCTION_SPACING 0x40 @@ -721,7 +721,7 @@ #define BCM1480_HSP_REGISTER_SPACING 0x80000 #define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING)) -#define A_BCM1480_HSP_REGISTER(idx,reg) (A_BCM1480_HSP_BASE(idx) + (reg)) +#define A_BCM1480_HSP_REGISTER(idx, reg) (A_BCM1480_HSP_BASE(idx) + (reg)) #define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000 #define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008 diff --git a/include/asm-mips/sibyte/bcm1480_scd.h b/include/asm-mips/sibyte/bcm1480_scd.h index 6111d6d..25ef24c 100644 --- a/include/asm-mips/sibyte/bcm1480_scd.h +++ b/include/asm-mips/sibyte/bcm1480_scd.h @@ -99,22 +99,22 @@ #define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) #define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) -#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_PLL_DIV) -#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_PLL_DIV) -#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_PLL_DIV,M_BCM1480_SYS_PLL_DIV) +#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV) +#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV) +#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV) #define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) -#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_SW_DIV) -#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_SW_DIV) -#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_SW_DIV,M_BCM1480_SYS_SW_DIV) +#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV) +#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV) +#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV) #define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) #define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) #define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) -#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2,S_BCM1480_SYS_BOOT_MODE) -#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_BOOT_MODE) -#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_BCM1480_SYS_BOOT_MODE,M_BCM1480_SYS_BOOT_MODE) +#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE) +#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE) +#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE) #define K_BCM1480_SYS_BOOT_MODE_ROM32 0 #define K_BCM1480_SYS_BOOT_MODE_ROM8 1 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2 @@ -129,16 +129,16 @@ #define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) #define S_BCM1480_SYS_CONFIG 26 -#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6,S_BCM1480_SYS_CONFIG) -#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_CONFIG) -#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x,S_BCM1480_SYS_CONFIG,M_BCM1480_SYS_CONFIG) +#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG) +#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG) +#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG) -#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32,15) +#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15) #define S_BCM1480_SYS_NODEID 47 -#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4,S_BCM1480_SYS_NODEID) -#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_NODEID) -#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x,S_BCM1480_SYS_NODEID,M_BCM1480_SYS_NODEID) +#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID) +#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID) +#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID) #define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) #define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) @@ -196,9 +196,9 @@ #define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) #define S_BCM1480_SCD_WDOG_RESET_TYPE 2 -#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5,S_BCM1480_SCD_WDOG_RESET_TYPE) -#define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE) -#define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE,M_BCM1480_SCD_WDOG_RESET_TYPE) +#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE) +#define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE) +#define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE) #define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ #define K_BCM1480_SCD_WDOG_RESET_SOFT 1 @@ -244,24 +244,24 @@ */ #define S_SPC_CFG_SRC4 32 -#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8,S_SPC_CFG_SRC4) -#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC4) -#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x,S_SPC_CFG_SRC4,M_SPC_CFG_SRC4) +#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4) +#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4) +#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4) #define S_SPC_CFG_SRC5 40 -#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8,S_SPC_CFG_SRC5) -#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC5) -#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x,S_SPC_CFG_SRC5,M_SPC_CFG_SRC5) +#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5) +#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5) +#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5) #define S_SPC_CFG_SRC6 48 -#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8,S_SPC_CFG_SRC6) -#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC6) -#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x,S_SPC_CFG_SRC6,M_SPC_CFG_SRC6) +#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6) +#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6) +#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6) #define S_SPC_CFG_SRC7 56 -#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8,S_SPC_CFG_SRC7) -#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC7) -#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x,S_SPC_CFG_SRC7,M_SPC_CFG_SRC7) +#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7) +#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7) +#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7) /* * System Performance Counter Control Register (Table 32) @@ -281,9 +281,9 @@ */ #define S_BCM1480_SPC_CNT_COUNT 0 -#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40,S_BCM1480_SPC_CNT_COUNT) -#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CNT_COUNT) -#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x,S_BCM1480_SPC_CNT_COUNT,M_BCM1480_SPC_CNT_COUNT) +#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT) +#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT) +#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT) #define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) @@ -322,13 +322,13 @@ * slightly different. */ -#define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4,0) -#define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40,0) +#define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4, 0) +#define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) #define S_BCM1480_ATRAP_CFG_CNT 0 -#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_BCM1480_ATRAP_CFG_CNT) -#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CNT) -#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CNT,M_BCM1480_ATRAP_CFG_CNT) +#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT) +#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT) +#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT) #define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) #define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) @@ -337,9 +337,9 @@ #define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) #define S_BCM1480_ATRAP_CFG_AGENTID 8 -#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_BCM1480_ATRAP_CFG_AGENTID) -#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID) -#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID,M_BCM1480_ATRAP_CFG_AGENTID) +#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID) +#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID) +#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID) #define K_BCM1480_BUS_AGENT_CPU0 0 @@ -354,9 +354,9 @@ #define K_BCM1480_BUS_AGENT_PM 10 #define S_BCM1480_ATRAP_CFG_CATTR 12 -#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2,S_BCM1480_ATRAP_CFG_CATTR) -#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CATTR) -#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CATTR,M_BCM1480_ATRAP_CFG_CATTR) +#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR) +#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR) +#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR) #define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0 #define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 @@ -382,9 +382,9 @@ #define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25) #define S_BCM1480_SCD_TRSEQ_SWFUNC 26 -#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2,S_BCM1480_SCD_TRSEQ_SWFUNC) -#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC) -#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC,M_BCM1480_SCD_TRSEQ_SWFUNC) +#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC) +#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC) +#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC) /* * Trace Control Register (Table 49) @@ -395,9 +395,9 @@ */ #define S_BCM1480_SCD_TRACE_CFG_MODE 16 -#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE) -#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE) -#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE,M_BCM1480_SCD_TRACE_CFG_MODE) +#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE) +#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE) +#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE) #define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0 #define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h index 73bce90..da198a1 100644 --- a/include/asm-mips/sibyte/board.h +++ b/include/asm-mips/sibyte/board.h @@ -41,7 +41,7 @@ #ifdef __ASSEMBLY__ #ifdef LEDS_PHYS -#define setleds(t0,t1,c0,c1,c2,c3) \ +#define setleds(t0, t1, c0, c1, c2, c3) \ li t0, (LEDS_PHYS|0xa0000000); \ li t1, c0; \ sb t1, 0x18(t0); \ @@ -52,7 +52,7 @@ li t1, c3; \ sb t1, 0x00(t0) #else -#define setleds(t0,t1,c0,c1,c2,c3) +#define setleds(t0, t1, c0, c1, c2, c3) #endif /* LEDS_PHYS */ #else diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h index a885491..09365f9 100644 --- a/include/asm-mips/sibyte/sb1250_defs.h +++ b/include/asm-mips/sibyte/sb1250_defs.h @@ -232,18 +232,18 @@ * Make a mask for 'v' bits at position 'n' */ -#define _SB_MAKEMASK(v,n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n)) -#define _SB_MAKEMASK_32(v,n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n)) +#define _SB_MAKEMASK(v, n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n)) +#define _SB_MAKEMASK_32(v, n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n)) /* * Make a value at 'v' at bit position 'n' */ -#define _SB_MAKEVALUE(v,n) (_SB_MAKE64(v) << _SB_MAKE64(n)) -#define _SB_MAKEVALUE_32(v,n) (_SB_MAKE32(v) << _SB_MAKE32(n)) +#define _SB_MAKEVALUE(v, n) (_SB_MAKE64(v) << _SB_MAKE64(n)) +#define _SB_MAKEVALUE_32(v, n) (_SB_MAKE32(v) << _SB_MAKE32(n)) -#define _SB_GETVALUE(v,n,m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n)) -#define _SB_GETVALUE_32(v,n,m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n)) +#define _SB_GETVALUE(v, n, m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n)) +#define _SB_GETVALUE_32(v, n, m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n)) /* * Macros to read/write on-chip registers @@ -252,7 +252,7 @@ #if defined(__mips64) && !defined(__ASSEMBLY__) -#define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) +#define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) #define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr))) #endif /* __ASSEMBLY__ */ diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h index e6145f5..bad5617 100644 --- a/include/asm-mips/sibyte/sb1250_dma.h +++ b/include/asm-mips/sibyte/sb1250_dma.h @@ -57,9 +57,9 @@ #define M_DMA_RESERVED1 _SB_MAKEMASK1(2) #define S_DMA_DESC_TYPE _SB_MAKE64(1) -#define M_DMA_DESC_TYPE _SB_MAKEMASK(2,S_DMA_DESC_TYPE) -#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE) -#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE) +#define M_DMA_DESC_TYPE _SB_MAKEMASK(2, S_DMA_DESC_TYPE) +#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x, S_DMA_DESC_TYPE) +#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x, S_DMA_DESC_TYPE, M_DMA_DESC_TYPE) #define K_DMA_DESC_TYPE_RING_AL 0 #define K_DMA_DESC_TYPE_CHAIN_AL 1 @@ -76,24 +76,24 @@ #define M_DMA_TDX_EN _SB_MAKEMASK1(7) #define S_DMA_INT_PKTCNT _SB_MAKE64(8) -#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8,S_DMA_INT_PKTCNT) -#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x,S_DMA_INT_PKTCNT) -#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x,S_DMA_INT_PKTCNT,M_DMA_INT_PKTCNT) +#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8, S_DMA_INT_PKTCNT) +#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x, S_DMA_INT_PKTCNT) +#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x, S_DMA_INT_PKTCNT, M_DMA_INT_PKTCNT) #define S_DMA_RINGSZ _SB_MAKE64(16) -#define M_DMA_RINGSZ _SB_MAKEMASK(16,S_DMA_RINGSZ) -#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x,S_DMA_RINGSZ) -#define G_DMA_RINGSZ(x) _SB_GETVALUE(x,S_DMA_RINGSZ,M_DMA_RINGSZ) +#define M_DMA_RINGSZ _SB_MAKEMASK(16, S_DMA_RINGSZ) +#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x, S_DMA_RINGSZ) +#define G_DMA_RINGSZ(x) _SB_GETVALUE(x, S_DMA_RINGSZ, M_DMA_RINGSZ) #define S_DMA_HIGH_WATERMARK _SB_MAKE64(32) -#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16,S_DMA_HIGH_WATERMARK) -#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_HIGH_WATERMARK) -#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x,S_DMA_HIGH_WATERMARK,M_DMA_HIGH_WATERMARK) +#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16, S_DMA_HIGH_WATERMARK) +#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_HIGH_WATERMARK) +#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x, S_DMA_HIGH_WATERMARK, M_DMA_HIGH_WATERMARK) #define S_DMA_LOW_WATERMARK _SB_MAKE64(48) -#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16,S_DMA_LOW_WATERMARK) -#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_LOW_WATERMARK) -#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x,S_DMA_LOW_WATERMARK,M_DMA_LOW_WATERMARK) +#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16, S_DMA_LOW_WATERMARK) +#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_LOW_WATERMARK) +#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x, S_DMA_LOW_WATERMARK, M_DMA_LOW_WATERMARK) /* * Ethernet and Serial DMA Configuration Register 1 (Table 7-5) @@ -116,37 +116,37 @@ #define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define M_DMA_MBZ1 _SB_MAKEMASK(6,15) +#define M_DMA_MBZ1 _SB_MAKEMASK(6, 15) #define S_DMA_HDR_SIZE _SB_MAKE64(21) -#define M_DMA_HDR_SIZE _SB_MAKEMASK(9,S_DMA_HDR_SIZE) -#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_HDR_SIZE) -#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x,S_DMA_HDR_SIZE,M_DMA_HDR_SIZE) +#define M_DMA_HDR_SIZE _SB_MAKEMASK(9, S_DMA_HDR_SIZE) +#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_HDR_SIZE) +#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x, S_DMA_HDR_SIZE, M_DMA_HDR_SIZE) -#define M_DMA_MBZ2 _SB_MAKEMASK(5,32) +#define M_DMA_MBZ2 _SB_MAKEMASK(5, 32) #define S_DMA_ASICXFR_SIZE _SB_MAKE64(37) -#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9,S_DMA_ASICXFR_SIZE) -#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_ASICXFR_SIZE) -#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x,S_DMA_ASICXFR_SIZE,M_DMA_ASICXFR_SIZE) +#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9, S_DMA_ASICXFR_SIZE) +#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_ASICXFR_SIZE) +#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x, S_DMA_ASICXFR_SIZE, M_DMA_ASICXFR_SIZE) #define S_DMA_INT_TIMEOUT _SB_MAKE64(48) -#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16,S_DMA_INT_TIMEOUT) -#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x,S_DMA_INT_TIMEOUT) -#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x,S_DMA_INT_TIMEOUT,M_DMA_INT_TIMEOUT) +#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16, S_DMA_INT_TIMEOUT) +#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x, S_DMA_INT_TIMEOUT) +#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x, S_DMA_INT_TIMEOUT, M_DMA_INT_TIMEOUT) /* * Ethernet and Serial DMA Descriptor base address (Table 7-6) */ -#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4,0) +#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4, 0) /* * ASIC Mode Base Address (Table 7-7) */ -#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20,0) +#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20, 0) /* * DMA Descriptor Count Registers (Table 7-8) @@ -160,9 +160,9 @@ */ #define S_DMA_CURDSCR_ADDR _SB_MAKE64(0) -#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40,S_DMA_CURDSCR_ADDR) +#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40, S_DMA_CURDSCR_ADDR) #define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) -#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT) +#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16, S_DMA_CURDSCR_COUNT) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56) @@ -173,12 +173,12 @@ */ #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_OODLOST_RX _SB_MAKE64(0) -#define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX) -#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX) +#define M_DMA_OODLOST_RX _SB_MAKEMASK(16, S_DMA_OODLOST_RX) +#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x, S_DMA_OODLOST_RX, M_DMA_OODLOST_RX) #define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) -#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX) -#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX) +#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8, S_DMA_EOP_COUNT_RX) +#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x, S_DMA_EOP_COUNT_RX, M_DMA_EOP_COUNT_RX) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ /* ********************************************************************* @@ -190,39 +190,39 @@ */ #define S_DMA_DSCRA_OFFSET _SB_MAKE64(0) -#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5,S_DMA_DSCRA_OFFSET) -#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_OFFSET) -#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x,S_DMA_DSCRA_OFFSET,M_DMA_DSCRA_OFFSET) +#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5, S_DMA_DSCRA_OFFSET) +#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_OFFSET) +#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x, S_DMA_DSCRA_OFFSET, M_DMA_DSCRA_OFFSET) /* Note: Don't shift the address over, just mask it with the mask below */ #define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5) -#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35,S_DMA_DSCRA_A_ADDR) +#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35, S_DMA_DSCRA_A_ADDR) #define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) -#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA) +#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40, S_DMA_DSCRA_A_ADDR_UA) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) -#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE) -#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE) -#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE) +#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9, S_DMA_DSCRA_A_SIZE) +#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_A_SIZE) +#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRA_A_SIZE, M_DMA_DSCRA_A_SIZE) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) -#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT) -#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT) +#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8, S_DMA_DSCRA_DSCR_CNT) +#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x, S_DMA_DSCRA_DSCR_CNT, M_DMA_DSCRA_DSCR_CNT) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) #define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50) #define S_DMA_DSCRA_STATUS _SB_MAKE64(51) -#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13,S_DMA_DSCRA_STATUS) -#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_STATUS) -#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRA_STATUS,M_DMA_DSCRA_STATUS) +#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13, S_DMA_DSCRA_STATUS) +#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_STATUS) +#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRA_STATUS, M_DMA_DSCRA_STATUS) /* * Descriptor doubleword "B" (Table 7-13) @@ -230,49 +230,49 @@ #define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0) -#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4,S_DMA_DSCRB_OPTIONS) -#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS) -#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS) +#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4, S_DMA_DSCRB_OPTIONS) +#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_OPTIONS) +#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x, S_DMA_DSCRB_OPTIONS, M_DMA_DSCRB_OPTIONS) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) -#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE) -#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE) -#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE) +#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_A_SIZE) +#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_A_SIZE) +#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_A_SIZE, M_DMA_DSCRB_A_SIZE) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) /* Note: Don't shift the address over, just mask it with the mask below */ #define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5) -#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35,S_DMA_DSCRB_B_ADDR) +#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35, S_DMA_DSCRB_B_ADDR) #define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40) -#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9,S_DMA_DSCRB_B_SIZE) -#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_B_SIZE) -#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_B_SIZE,M_DMA_DSCRB_B_SIZE) +#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9, S_DMA_DSCRB_B_SIZE) +#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_B_SIZE) +#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_B_SIZE, M_DMA_DSCRB_B_SIZE) #define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) -#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB) -#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB) -#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB) +#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2, S_DMA_DSCRB_PKT_SIZE_MSB) +#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB) +#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB, M_DMA_DSCRB_PKT_SIZE_MSB) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) -#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE) -#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE) -#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE,M_DMA_DSCRB_PKT_SIZE) +#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_PKT_SIZE) +#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE) +#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE, M_DMA_DSCRB_PKT_SIZE) /* * from pass2 some bits in dscr_b are also used for rx status */ #define S_DMA_DSCRB_STATUS _SB_MAKE64(0) -#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1,S_DMA_DSCRB_STATUS) -#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS) -#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS) +#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1, S_DMA_DSCRB_STATUS) +#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_STATUS) +#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRB_STATUS, M_DMA_DSCRB_STATUS) /* * Ethernet Descriptor Status Bits (Table 7-15) @@ -293,14 +293,14 @@ #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_DMA_ETHRX_RXCH 53 -#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH) -#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_RXCH) -#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x,S_DMA_ETHRX_RXCH,M_DMA_ETHRX_RXCH) +#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2, S_DMA_ETHRX_RXCH) +#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_RXCH) +#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x, S_DMA_ETHRX_RXCH, M_DMA_ETHRX_RXCH) #define S_DMA_ETHRX_PKTTYPE 55 -#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3,S_DMA_ETHRX_PKTTYPE) -#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_PKTTYPE) -#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x,S_DMA_ETHRX_PKTTYPE,M_DMA_ETHRX_PKTTYPE) +#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3, S_DMA_ETHRX_PKTTYPE) +#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_PKTTYPE) +#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x, S_DMA_ETHRX_PKTTYPE, M_DMA_ETHRX_PKTTYPE) #define K_DMA_ETHRX_PKTTYPE_IPV4 0 #define K_DMA_ETHRX_PKTTYPE_ARPV4 1 @@ -385,21 +385,21 @@ * Register: DM_DSCR_BASE_3 */ -#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4,0) +#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4, 0) /* Note: Just mask the base address and then OR it in. */ #define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4) -#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36,S_DM_DSCR_BASE_ADDR) +#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36, S_DM_DSCR_BASE_ADDR) #define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40) -#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16,S_DM_DSCR_BASE_RINGSZ) -#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_RINGSZ) -#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_RINGSZ,M_DM_DSCR_BASE_RINGSZ) +#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16, S_DM_DSCR_BASE_RINGSZ) +#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_RINGSZ) +#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_RINGSZ, M_DM_DSCR_BASE_RINGSZ) #define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56) -#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3,S_DM_DSCR_BASE_PRIORITY) -#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_PRIORITY) -#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_PRIORITY,M_DM_DSCR_BASE_PRIORITY) +#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3, S_DM_DSCR_BASE_PRIORITY) +#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_PRIORITY) +#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_PRIORITY, M_DM_DSCR_BASE_PRIORITY) #define K_DM_DSCR_BASE_PRIORITY_1 0 #define K_DM_DSCR_BASE_PRIORITY_2 1 @@ -429,12 +429,12 @@ */ #define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0) -#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40,S_DM_CUR_DSCR_DSCR_ADDR) +#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40, S_DM_CUR_DSCR_DSCR_ADDR) #define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48) -#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16,S_DM_CUR_DSCR_DSCR_COUNT) -#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT) -#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT,\ +#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16, S_DM_CUR_DSCR_DSCR_COUNT) +#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT) +#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT,\ M_DM_CUR_DSCR_DSCR_COUNT) @@ -447,15 +447,15 @@ * Register: DM_PARTIAL_3 */ #define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0) -#define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32,S_DM_PARTIAL_CRC_PARTIAL) -#define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_CRC_PARTIAL) -#define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_CRC_PARTIAL,\ +#define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32, S_DM_PARTIAL_CRC_PARTIAL) +#define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_CRC_PARTIAL) +#define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_CRC_PARTIAL,\ M_DM_PARTIAL_CRC_PARTIAL) #define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32) -#define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16,S_DM_PARTIAL_TCPCS_PARTIAL) -#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL) -#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL,\ +#define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16, S_DM_PARTIAL_TCPCS_PARTIAL) +#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL) +#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL,\ M_DM_PARTIAL_TCPCS_PARTIAL) #define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) @@ -469,15 +469,15 @@ * Register: CRC_DEF_1 */ #define S_CRC_DEF_CRC_INIT _SB_MAKE64(0) -#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32,S_CRC_DEF_CRC_INIT) -#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_INIT) -#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_INIT,\ +#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32, S_CRC_DEF_CRC_INIT) +#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_INIT) +#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_INIT,\ M_CRC_DEF_CRC_INIT) #define S_CRC_DEF_CRC_POLY _SB_MAKE64(32) -#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32,S_CRC_DEF_CRC_POLY) -#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY) -#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\ +#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32, S_CRC_DEF_CRC_POLY) +#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_POLY) +#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_POLY,\ M_CRC_DEF_CRC_POLY) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ @@ -489,21 +489,21 @@ * Register: CTCP_DEF_1 */ #define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0) -#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32,S_CTCP_DEF_CRC_TXOR) -#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_TXOR) -#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_TXOR,\ +#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32, S_CTCP_DEF_CRC_TXOR) +#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_TXOR) +#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_TXOR,\ M_CTCP_DEF_CRC_TXOR) #define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32) -#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16,S_CTCP_DEF_TCPCS_INIT) -#define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r,S_CTCP_DEF_TCPCS_INIT) -#define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r,S_CTCP_DEF_TCPCS_INIT,\ +#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16, S_CTCP_DEF_TCPCS_INIT) +#define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r, S_CTCP_DEF_TCPCS_INIT) +#define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r, S_CTCP_DEF_TCPCS_INIT,\ M_CTCP_DEF_TCPCS_INIT) #define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48) -#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2,S_CTCP_DEF_CRC_WIDTH) -#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_WIDTH) -#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_WIDTH,\ +#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2, S_CTCP_DEF_CRC_WIDTH) +#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_WIDTH) +#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_WIDTH,\ M_CTCP_DEF_CRC_WIDTH) #define K_CTCP_DEF_CRC_WIDTH_4 0 @@ -519,7 +519,7 @@ */ #define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0) -#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40,S_DM_DSCRA_DST_ADDR) +#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40, S_DM_DSCRA_DST_ADDR) #define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40) #define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41) @@ -529,30 +529,30 @@ #endif /* up to 1250 PASS1 */ #define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44) -#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2,S_DM_DSCRA_DIR_DEST) -#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_DEST) -#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_DEST,M_DM_DSCRA_DIR_DEST) +#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2, S_DM_DSCRA_DIR_DEST) +#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_DEST) +#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_DEST, M_DM_DSCRA_DIR_DEST) #define K_DM_DSCRA_DIR_DEST_INCR 0 #define K_DM_DSCRA_DIR_DEST_DECR 1 #define K_DM_DSCRA_DIR_DEST_CONST 2 -#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR,S_DM_DSCRA_DIR_DEST) -#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR,S_DM_DSCRA_DIR_DEST) -#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST,S_DM_DSCRA_DIR_DEST) +#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR, S_DM_DSCRA_DIR_DEST) +#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR, S_DM_DSCRA_DIR_DEST) +#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST, S_DM_DSCRA_DIR_DEST) #define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46) -#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2,S_DM_DSCRA_DIR_SRC) -#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_SRC) -#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_SRC,M_DM_DSCRA_DIR_SRC) +#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2, S_DM_DSCRA_DIR_SRC) +#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_SRC) +#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_SRC, M_DM_DSCRA_DIR_SRC) #define K_DM_DSCRA_DIR_SRC_INCR 0 #define K_DM_DSCRA_DIR_SRC_DECR 1 #define K_DM_DSCRA_DIR_SRC_CONST 2 -#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR,S_DM_DSCRA_DIR_SRC) -#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR,S_DM_DSCRA_DIR_SRC) -#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST,S_DM_DSCRA_DIR_SRC) +#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR, S_DM_DSCRA_DIR_SRC) +#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR, S_DM_DSCRA_DIR_SRC) +#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST, S_DM_DSCRA_DIR_SRC) #define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48) @@ -576,19 +576,19 @@ #define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61) +#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3, 61) /* * Data Mover Descriptor Doubleword "B" (Table 7-25) */ #define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0) -#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40,S_DM_DSCRB_SRC_ADDR) +#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40, S_DM_DSCRB_SRC_ADDR) #define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40) -#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20,S_DM_DSCRB_SRC_LENGTH) -#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x,S_DM_DSCRB_SRC_LENGTH) -#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x,S_DM_DSCRB_SRC_LENGTH,M_DM_DSCRB_SRC_LENGTH) +#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20, S_DM_DSCRB_SRC_LENGTH) +#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x, S_DM_DSCRB_SRC_LENGTH) +#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x, S_DM_DSCRB_SRC_LENGTH, M_DM_DSCRB_SRC_LENGTH) #endif diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h index 1b5cbc5..94e9c7c 100644 --- a/include/asm-mips/sibyte/sb1250_genbus.h +++ b/include/asm-mips/sibyte/sb1250_genbus.h @@ -11,7 +11,7 @@ * ********************************************************************* * - * Copyright 2000,2001,2002,2003 + * Copyright 2000, 2001, 2002, 2003 * Broadcom Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or @@ -47,7 +47,7 @@ #define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) #define S_IO_WIDTH_SEL 2 -#define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL) +#define M_IO_WIDTH_SEL _SB_MAKEMASK(2, S_IO_WIDTH_SEL) #define K_IO_WIDTH_SEL_1 0 #define K_IO_WIDTH_SEL_2 1 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ @@ -55,8 +55,8 @@ #define K_IO_WIDTH_SEL_1L 2 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define K_IO_WIDTH_SEL_4 3 -#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL) -#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL) +#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x, S_IO_WIDTH_SEL) +#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL) #define S_IO_PARITY_ENA 4 #define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) @@ -71,18 +71,18 @@ #define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX) #define S_IO_TIMEOUT 8 -#define M_IO_TIMEOUT _SB_MAKEMASK(8,S_IO_TIMEOUT) -#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x,S_IO_TIMEOUT) -#define G_IO_TIMEOUT(x) _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT) +#define M_IO_TIMEOUT _SB_MAKEMASK(8, S_IO_TIMEOUT) +#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x, S_IO_TIMEOUT) +#define G_IO_TIMEOUT(x) _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT) /* * Generic Bus Region Size register (Table 11-5) */ #define S_IO_MULT_SIZE 0 -#define M_IO_MULT_SIZE _SB_MAKEMASK(12,S_IO_MULT_SIZE) -#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x,S_IO_MULT_SIZE) -#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE) +#define M_IO_MULT_SIZE _SB_MAKEMASK(12, S_IO_MULT_SIZE) +#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x, S_IO_MULT_SIZE) +#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x, S_IO_MULT_SIZE, M_IO_MULT_SIZE) #define S_IO_REGSIZE 16 /* # bits to shift size for this reg */ @@ -91,9 +91,9 @@ */ #define S_IO_START_ADDR 0 -#define M_IO_START_ADDR _SB_MAKEMASK(14,S_IO_START_ADDR) -#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x,S_IO_START_ADDR) -#define G_IO_START_ADDR(x) _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR) +#define M_IO_START_ADDR _SB_MAKEMASK(14, S_IO_START_ADDR) +#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x, S_IO_START_ADDR) +#define G_IO_START_ADDR(x) _SB_GETVALUE(x, S_IO_START_ADDR, M_IO_START_ADDR) #define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ @@ -105,9 +105,9 @@ */ #define S_IO_ALE_WIDTH 0 -#define M_IO_ALE_WIDTH _SB_MAKEMASK(3,S_IO_ALE_WIDTH) -#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH) -#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH) +#define M_IO_ALE_WIDTH _SB_MAKEMASK(3, S_IO_ALE_WIDTH) +#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_ALE_WIDTH) +#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x, S_IO_ALE_WIDTH, M_IO_ALE_WIDTH) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ || SIBYTE_HDR_FEATURE_CHIP(1480) @@ -115,27 +115,27 @@ #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_IO_ALE_TO_CS 4 -#define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS) -#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS) -#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS) +#define M_IO_ALE_TO_CS _SB_MAKEMASK(2, S_IO_ALE_TO_CS) +#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_CS) +#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x, S_IO_ALE_TO_CS, M_IO_ALE_TO_CS) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_IO_BURST_WIDTH _SB_MAKE64(6) -#define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH) -#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH) -#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH) +#define M_IO_BURST_WIDTH _SB_MAKEMASK(2, S_IO_BURST_WIDTH) +#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x, S_IO_BURST_WIDTH) +#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_IO_CS_WIDTH 8 -#define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH) -#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x,S_IO_CS_WIDTH) -#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH) +#define M_IO_CS_WIDTH _SB_MAKEMASK(5, S_IO_CS_WIDTH) +#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x, S_IO_CS_WIDTH) +#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x, S_IO_CS_WIDTH, M_IO_CS_WIDTH) #define S_IO_RDY_SMPLE 13 -#define M_IO_RDY_SMPLE _SB_MAKEMASK(3,S_IO_RDY_SMPLE) -#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x,S_IO_RDY_SMPLE) -#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE) +#define M_IO_RDY_SMPLE _SB_MAKEMASK(3, S_IO_RDY_SMPLE) +#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x, S_IO_RDY_SMPLE) +#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x, S_IO_RDY_SMPLE, M_IO_RDY_SMPLE) /* @@ -143,9 +143,9 @@ */ #define S_IO_ALE_TO_WRITE 0 -#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE) -#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE) -#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE) +#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3, S_IO_ALE_TO_WRITE) +#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_WRITE) +#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x, S_IO_ALE_TO_WRITE, M_IO_ALE_TO_WRITE) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ || SIBYTE_HDR_FEATURE_CHIP(1480) @@ -153,30 +153,30 @@ #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_IO_WRITE_WIDTH 4 -#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH) -#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH) -#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH) +#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4, S_IO_WRITE_WIDTH) +#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_WRITE_WIDTH) +#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x, S_IO_WRITE_WIDTH, M_IO_WRITE_WIDTH) #define S_IO_IDLE_CYCLE 8 -#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4,S_IO_IDLE_CYCLE) -#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE) -#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE) +#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4, S_IO_IDLE_CYCLE) +#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x, S_IO_IDLE_CYCLE) +#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x, S_IO_IDLE_CYCLE, M_IO_IDLE_CYCLE) #define S_IO_OE_TO_CS 12 -#define M_IO_OE_TO_CS _SB_MAKEMASK(2,S_IO_OE_TO_CS) -#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_OE_TO_CS) -#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS) +#define M_IO_OE_TO_CS _SB_MAKEMASK(2, S_IO_OE_TO_CS) +#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_OE_TO_CS) +#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x, S_IO_OE_TO_CS, M_IO_OE_TO_CS) #define S_IO_CS_TO_OE 14 -#define M_IO_CS_TO_OE _SB_MAKEMASK(2,S_IO_CS_TO_OE) -#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x,S_IO_CS_TO_OE) -#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE) +#define M_IO_CS_TO_OE _SB_MAKEMASK(2, S_IO_CS_TO_OE) +#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x, S_IO_CS_TO_OE) +#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x, S_IO_CS_TO_OE, M_IO_CS_TO_OE) /* * Generic Bus Interrupt Status Register (Table 11-9) */ -#define M_IO_CS_ERR_INT _SB_MAKEMASK(0,8) +#define M_IO_CS_ERR_INT _SB_MAKEMASK(0, 8) #define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0) #define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1) #define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2) @@ -200,116 +200,116 @@ */ #define S_IO_SLEW0 0 -#define M_IO_SLEW0 _SB_MAKEMASK(2,S_IO_SLEW0) -#define V_IO_SLEW0(x) _SB_MAKEVALUE(x,S_IO_SLEW0) -#define G_IO_SLEW0(x) _SB_GETVALUE(x,S_IO_SLEW0,M_IO_SLEW0) +#define M_IO_SLEW0 _SB_MAKEMASK(2, S_IO_SLEW0) +#define V_IO_SLEW0(x) _SB_MAKEVALUE(x, S_IO_SLEW0) +#define G_IO_SLEW0(x) _SB_GETVALUE(x, S_IO_SLEW0, M_IO_SLEW0) #define S_IO_DRV_A 2 -#define M_IO_DRV_A _SB_MAKEMASK(2,S_IO_DRV_A) -#define V_IO_DRV_A(x) _SB_MAKEVALUE(x,S_IO_DRV_A) -#define G_IO_DRV_A(x) _SB_GETVALUE(x,S_IO_DRV_A,M_IO_DRV_A) +#define M_IO_DRV_A _SB_MAKEMASK(2, S_IO_DRV_A) +#define V_IO_DRV_A(x) _SB_MAKEVALUE(x, S_IO_DRV_A) +#define G_IO_DRV_A(x) _SB_GETVALUE(x, S_IO_DRV_A, M_IO_DRV_A) #define S_IO_DRV_B 6 -#define M_IO_DRV_B _SB_MAKEMASK(2,S_IO_DRV_B) -#define V_IO_DRV_B(x) _SB_MAKEVALUE(x,S_IO_DRV_B) -#define G_IO_DRV_B(x) _SB_GETVALUE(x,S_IO_DRV_B,M_IO_DRV_B) +#define M_IO_DRV_B _SB_MAKEMASK(2, S_IO_DRV_B) +#define V_IO_DRV_B(x) _SB_MAKEVALUE(x, S_IO_DRV_B) +#define G_IO_DRV_B(x) _SB_GETVALUE(x, S_IO_DRV_B, M_IO_DRV_B) #define S_IO_DRV_C 10 -#define M_IO_DRV_C _SB_MAKEMASK(2,S_IO_DRV_C) -#define V_IO_DRV_C(x) _SB_MAKEVALUE(x,S_IO_DRV_C) -#define G_IO_DRV_C(x) _SB_GETVALUE(x,S_IO_DRV_C,M_IO_DRV_C) +#define M_IO_DRV_C _SB_MAKEMASK(2, S_IO_DRV_C) +#define V_IO_DRV_C(x) _SB_MAKEVALUE(x, S_IO_DRV_C) +#define G_IO_DRV_C(x) _SB_GETVALUE(x, S_IO_DRV_C, M_IO_DRV_C) #define S_IO_DRV_D 14 -#define M_IO_DRV_D _SB_MAKEMASK(2,S_IO_DRV_D) -#define V_IO_DRV_D(x) _SB_MAKEVALUE(x,S_IO_DRV_D) -#define G_IO_DRV_D(x) _SB_GETVALUE(x,S_IO_DRV_D,M_IO_DRV_D) +#define M_IO_DRV_D _SB_MAKEMASK(2, S_IO_DRV_D) +#define V_IO_DRV_D(x) _SB_MAKEVALUE(x, S_IO_DRV_D) +#define G_IO_DRV_D(x) _SB_GETVALUE(x, S_IO_DRV_D, M_IO_DRV_D) /* * Generic Bus Output Drive Control Register 1 (Table 14-19) */ #define S_IO_DRV_E 2 -#define M_IO_DRV_E _SB_MAKEMASK(2,S_IO_DRV_E) -#define V_IO_DRV_E(x) _SB_MAKEVALUE(x,S_IO_DRV_E) -#define G_IO_DRV_E(x) _SB_GETVALUE(x,S_IO_DRV_E,M_IO_DRV_E) +#define M_IO_DRV_E _SB_MAKEMASK(2, S_IO_DRV_E) +#define V_IO_DRV_E(x) _SB_MAKEVALUE(x, S_IO_DRV_E) +#define G_IO_DRV_E(x) _SB_GETVALUE(x, S_IO_DRV_E, M_IO_DRV_E) #define S_IO_DRV_F 6 -#define M_IO_DRV_F _SB_MAKEMASK(2,S_IO_DRV_F) -#define V_IO_DRV_F(x) _SB_MAKEVALUE(x,S_IO_DRV_F) -#define G_IO_DRV_F(x) _SB_GETVALUE(x,S_IO_DRV_F,M_IO_DRV_F) +#define M_IO_DRV_F _SB_MAKEMASK(2, S_IO_DRV_F) +#define V_IO_DRV_F(x) _SB_MAKEVALUE(x, S_IO_DRV_F) +#define G_IO_DRV_F(x) _SB_GETVALUE(x, S_IO_DRV_F, M_IO_DRV_F) #define S_IO_SLEW1 8 -#define M_IO_SLEW1 _SB_MAKEMASK(2,S_IO_SLEW1) -#define V_IO_SLEW1(x) _SB_MAKEVALUE(x,S_IO_SLEW1) -#define G_IO_SLEW1(x) _SB_GETVALUE(x,S_IO_SLEW1,M_IO_SLEW1) +#define M_IO_SLEW1 _SB_MAKEMASK(2, S_IO_SLEW1) +#define V_IO_SLEW1(x) _SB_MAKEVALUE(x, S_IO_SLEW1) +#define G_IO_SLEW1(x) _SB_GETVALUE(x, S_IO_SLEW1, M_IO_SLEW1) #define S_IO_DRV_G 10 -#define M_IO_DRV_G _SB_MAKEMASK(2,S_IO_DRV_G) -#define V_IO_DRV_G(x) _SB_MAKEVALUE(x,S_IO_DRV_G) -#define G_IO_DRV_G(x) _SB_GETVALUE(x,S_IO_DRV_G,M_IO_DRV_G) +#define M_IO_DRV_G _SB_MAKEMASK(2, S_IO_DRV_G) +#define V_IO_DRV_G(x) _SB_MAKEVALUE(x, S_IO_DRV_G) +#define G_IO_DRV_G(x) _SB_GETVALUE(x, S_IO_DRV_G, M_IO_DRV_G) #define S_IO_SLEW2 12 -#define M_IO_SLEW2 _SB_MAKEMASK(2,S_IO_SLEW2) -#define V_IO_SLEW2(x) _SB_MAKEVALUE(x,S_IO_SLEW2) -#define G_IO_SLEW2(x) _SB_GETVALUE(x,S_IO_SLEW2,M_IO_SLEW2) +#define M_IO_SLEW2 _SB_MAKEMASK(2, S_IO_SLEW2) +#define V_IO_SLEW2(x) _SB_MAKEVALUE(x, S_IO_SLEW2) +#define G_IO_SLEW2(x) _SB_GETVALUE(x, S_IO_SLEW2, M_IO_SLEW2) #define S_IO_DRV_H 14 -#define M_IO_DRV_H _SB_MAKEMASK(2,S_IO_DRV_H) -#define V_IO_DRV_H(x) _SB_MAKEVALUE(x,S_IO_DRV_H) -#define G_IO_DRV_H(x) _SB_GETVALUE(x,S_IO_DRV_H,M_IO_DRV_H) +#define M_IO_DRV_H _SB_MAKEMASK(2, S_IO_DRV_H) +#define V_IO_DRV_H(x) _SB_MAKEVALUE(x, S_IO_DRV_H) +#define G_IO_DRV_H(x) _SB_GETVALUE(x, S_IO_DRV_H, M_IO_DRV_H) /* * Generic Bus Output Drive Control Register 2 (Table 14-20) */ #define S_IO_DRV_J 2 -#define M_IO_DRV_J _SB_MAKEMASK(2,S_IO_DRV_J) -#define V_IO_DRV_J(x) _SB_MAKEVALUE(x,S_IO_DRV_J) -#define G_IO_DRV_J(x) _SB_GETVALUE(x,S_IO_DRV_J,M_IO_DRV_J) +#define M_IO_DRV_J _SB_MAKEMASK(2, S_IO_DRV_J) +#define V_IO_DRV_J(x) _SB_MAKEVALUE(x, S_IO_DRV_J) +#define G_IO_DRV_J(x) _SB_GETVALUE(x, S_IO_DRV_J, M_IO_DRV_J) #define S_IO_DRV_K 6 -#define M_IO_DRV_K _SB_MAKEMASK(2,S_IO_DRV_K) -#define V_IO_DRV_K(x) _SB_MAKEVALUE(x,S_IO_DRV_K) -#define G_IO_DRV_K(x) _SB_GETVALUE(x,S_IO_DRV_K,M_IO_DRV_K) +#define M_IO_DRV_K _SB_MAKEMASK(2, S_IO_DRV_K) +#define V_IO_DRV_K(x) _SB_MAKEVALUE(x, S_IO_DRV_K) +#define G_IO_DRV_K(x) _SB_GETVALUE(x, S_IO_DRV_K, M_IO_DRV_K) #define S_IO_DRV_L 10 -#define M_IO_DRV_L _SB_MAKEMASK(2,S_IO_DRV_L) -#define V_IO_DRV_L(x) _SB_MAKEVALUE(x,S_IO_DRV_L) -#define G_IO_DRV_L(x) _SB_GETVALUE(x,S_IO_DRV_L,M_IO_DRV_L) +#define M_IO_DRV_L _SB_MAKEMASK(2, S_IO_DRV_L) +#define V_IO_DRV_L(x) _SB_MAKEVALUE(x, S_IO_DRV_L) +#define G_IO_DRV_L(x) _SB_GETVALUE(x, S_IO_DRV_L, M_IO_DRV_L) #define S_IO_DRV_M 14 -#define M_IO_DRV_M _SB_MAKEMASK(2,S_IO_DRV_M) -#define V_IO_DRV_M(x) _SB_MAKEVALUE(x,S_IO_DRV_M) -#define G_IO_DRV_M(x) _SB_GETVALUE(x,S_IO_DRV_M,M_IO_DRV_M) +#define M_IO_DRV_M _SB_MAKEMASK(2, S_IO_DRV_M) +#define V_IO_DRV_M(x) _SB_MAKEVALUE(x, S_IO_DRV_M) +#define G_IO_DRV_M(x) _SB_GETVALUE(x, S_IO_DRV_M, M_IO_DRV_M) /* * Generic Bus Output Drive Control Register 3 (Table 14-21) */ #define S_IO_SLEW3 0 -#define M_IO_SLEW3 _SB_MAKEMASK(2,S_IO_SLEW3) -#define V_IO_SLEW3(x) _SB_MAKEVALUE(x,S_IO_SLEW3) -#define G_IO_SLEW3(x) _SB_GETVALUE(x,S_IO_SLEW3,M_IO_SLEW3) +#define M_IO_SLEW3 _SB_MAKEMASK(2, S_IO_SLEW3) +#define V_IO_SLEW3(x) _SB_MAKEVALUE(x, S_IO_SLEW3) +#define G_IO_SLEW3(x) _SB_GETVALUE(x, S_IO_SLEW3, M_IO_SLEW3) #define S_IO_DRV_N 2 -#define M_IO_DRV_N _SB_MAKEMASK(2,S_IO_DRV_N) -#define V_IO_DRV_N(x) _SB_MAKEVALUE(x,S_IO_DRV_N) -#define G_IO_DRV_N(x) _SB_GETVALUE(x,S_IO_DRV_N,M_IO_DRV_N) +#define M_IO_DRV_N _SB_MAKEMASK(2, S_IO_DRV_N) +#define V_IO_DRV_N(x) _SB_MAKEVALUE(x, S_IO_DRV_N) +#define G_IO_DRV_N(x) _SB_GETVALUE(x, S_IO_DRV_N, M_IO_DRV_N) #define S_IO_DRV_P 6 -#define M_IO_DRV_P _SB_MAKEMASK(2,S_IO_DRV_P) -#define V_IO_DRV_P(x) _SB_MAKEVALUE(x,S_IO_DRV_P) -#define G_IO_DRV_P(x) _SB_GETVALUE(x,S_IO_DRV_P,M_IO_DRV_P) +#define M_IO_DRV_P _SB_MAKEMASK(2, S_IO_DRV_P) +#define V_IO_DRV_P(x) _SB_MAKEVALUE(x, S_IO_DRV_P) +#define G_IO_DRV_P(x) _SB_GETVALUE(x, S_IO_DRV_P, M_IO_DRV_P) #define S_IO_DRV_Q 10 -#define M_IO_DRV_Q _SB_MAKEMASK(2,S_IO_DRV_Q) -#define V_IO_DRV_Q(x) _SB_MAKEVALUE(x,S_IO_DRV_Q) -#define G_IO_DRV_Q(x) _SB_GETVALUE(x,S_IO_DRV_Q,M_IO_DRV_Q) +#define M_IO_DRV_Q _SB_MAKEMASK(2, S_IO_DRV_Q) +#define V_IO_DRV_Q(x) _SB_MAKEVALUE(x, S_IO_DRV_Q) +#define G_IO_DRV_Q(x) _SB_GETVALUE(x, S_IO_DRV_Q, M_IO_DRV_Q) #define S_IO_DRV_R 14 -#define M_IO_DRV_R _SB_MAKEMASK(2,S_IO_DRV_R) -#define V_IO_DRV_R(x) _SB_MAKEVALUE(x,S_IO_DRV_R) -#define G_IO_DRV_R(x) _SB_GETVALUE(x,S_IO_DRV_R,M_IO_DRV_R) +#define M_IO_DRV_R _SB_MAKEMASK(2, S_IO_DRV_R) +#define V_IO_DRV_R(x) _SB_MAKEVALUE(x, S_IO_DRV_R) +#define G_IO_DRV_R(x) _SB_GETVALUE(x, S_IO_DRV_R, M_IO_DRV_R) /* @@ -329,9 +329,9 @@ #if SIBYTE_HDR_FEATURE_CHIP(1480) #define S_PCMCIA_MODE 16 -#define M_PCMCIA_MODE _SB_MAKEMASK(3,S_PCMCIA_MODE) -#define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x,S_PCMCIA_MODE) -#define G_PCMCIA_MODE(x) _SB_GETVALUE(x,S_PCMCIA_MODE,M_PCMCIA_MODE) +#define M_PCMCIA_MODE _SB_MAKEMASK(3, S_PCMCIA_MODE) +#define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x, S_PCMCIA_MODE) +#define G_PCMCIA_MODE(x) _SB_GETVALUE(x, S_PCMCIA_MODE, M_PCMCIA_MODE) #define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */ #define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */ @@ -369,49 +369,49 @@ #define K_GPIO_INTR_SPLIT 3 #define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) -#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n)) -#define V_GPIO_INTR_TYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n)) -#define G_GPIO_INTR_TYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n)) +#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n)) +#define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n)) +#define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n)) #define S_GPIO_INTR_TYPE0 0 -#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0) -#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0) -#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0) +#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0) +#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE0) +#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE0, M_GPIO_INTR_TYPE0) #define S_GPIO_INTR_TYPE2 2 -#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2) -#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2) -#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2) +#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE2) +#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE2) +#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE2, M_GPIO_INTR_TYPE2) #define S_GPIO_INTR_TYPE4 4 -#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4) -#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4) -#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4) +#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE4) +#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE4) +#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE4, M_GPIO_INTR_TYPE4) #define S_GPIO_INTR_TYPE6 6 -#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6) -#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6) -#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6) +#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE6) +#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE6) +#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE6, M_GPIO_INTR_TYPE6) #define S_GPIO_INTR_TYPE8 8 -#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8) -#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8) -#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8) +#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE8) +#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE8) +#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE8, M_GPIO_INTR_TYPE8) #define S_GPIO_INTR_TYPE10 10 -#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10) -#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10) -#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10) +#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE10) +#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE10) +#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE10, M_GPIO_INTR_TYPE10) #define S_GPIO_INTR_TYPE12 12 -#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12) -#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12) -#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12) +#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE12) +#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE12) +#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE12, M_GPIO_INTR_TYPE12) #define S_GPIO_INTR_TYPE14 14 -#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14) -#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14) -#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14) +#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE14) +#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE14) +#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE14, M_GPIO_INTR_TYPE14) #if SIBYTE_HDR_FEATURE_CHIP(1480) @@ -425,49 +425,49 @@ #define K_GPIO_INTR_UNPRED2 3 #define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2) -#define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_ATYPEX(n)) -#define V_GPIO_INTR_ATYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPEX(n)) -#define G_GPIO_INTR_ATYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPEX(n),M_GPIO_INTR_ATYPEX(n)) +#define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_ATYPEX(n)) +#define V_GPIO_INTR_ATYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPEX(n)) +#define G_GPIO_INTR_ATYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPEX(n), M_GPIO_INTR_ATYPEX(n)) #define S_GPIO_INTR_ATYPE0 0 -#define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE0) -#define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE0) -#define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE0,M_GPIO_INTR_ATYPE0) +#define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE0) +#define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE0) +#define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE0, M_GPIO_INTR_ATYPE0) #define S_GPIO_INTR_ATYPE2 2 -#define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE2) -#define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE2) -#define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE2,M_GPIO_INTR_ATYPE2) +#define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE2) +#define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE2) +#define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE2, M_GPIO_INTR_ATYPE2) #define S_GPIO_INTR_ATYPE4 4 -#define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE4) -#define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE4) -#define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE4,M_GPIO_INTR_ATYPE4) +#define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE4) +#define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE4) +#define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE4, M_GPIO_INTR_ATYPE4) #define S_GPIO_INTR_ATYPE6 6 -#define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE6) -#define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE6) -#define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE6,M_GPIO_INTR_ATYPE6) +#define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE6) +#define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE6) +#define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE6, M_GPIO_INTR_ATYPE6) #define S_GPIO_INTR_ATYPE8 8 -#define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE8) -#define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE8) -#define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE8,M_GPIO_INTR_ATYPE8) +#define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE8) +#define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE8) +#define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE8, M_GPIO_INTR_ATYPE8) #define S_GPIO_INTR_ATYPE10 10 -#define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE10) -#define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE10) -#define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE10,M_GPIO_INTR_ATYPE10) +#define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE10) +#define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE10) +#define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE10, M_GPIO_INTR_ATYPE10) #define S_GPIO_INTR_ATYPE12 12 -#define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE12) -#define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE12) -#define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE12,M_GPIO_INTR_ATYPE12) +#define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE12) +#define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE12) +#define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE12, M_GPIO_INTR_ATYPE12) #define S_GPIO_INTR_ATYPE14 14 -#define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE14) -#define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE14) -#define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE14,M_GPIO_INTR_ATYPE14) +#define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE14) +#define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE14) +#define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE14, M_GPIO_INTR_ATYPE14) #endif diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h index 94e8299..f2850b4 100644 --- a/include/asm-mips/sibyte/sb1250_int.h +++ b/include/asm-mips/sibyte/sb1250_int.h @@ -10,7 +10,7 @@ * ********************************************************************* * - * Copyright 2000,2001,2002,2003 + * Copyright 2000, 2001, 2002, 2003 * Broadcom Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or @@ -150,7 +150,7 @@ #define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1) #define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2) #define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3) -#define M_INT_MBOX_ALL _SB_MAKEMASK(4,K_INT_MBOX_0) +#define M_INT_MBOX_ALL _SB_MAKEMASK(4, K_INT_MBOX_0) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) #define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT) #define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT) @@ -208,9 +208,9 @@ */ #define S_INT_LDT_INTMSG 0 -#define M_INT_LDT_INTMSG _SB_MAKEMASK(3,S_INT_LDT_INTMSG) -#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x,S_INT_LDT_INTMSG) -#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x,S_INT_LDT_INTMSG,M_INT_LDT_INTMSG) +#define M_INT_LDT_INTMSG _SB_MAKEMASK(3, S_INT_LDT_INTMSG) +#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x, S_INT_LDT_INTMSG) +#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG) #define K_INT_LDT_INTMSG_FIXED 0 #define K_INT_LDT_INTMSG_ARBITRATED 1 @@ -228,14 +228,14 @@ #define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4) #define S_INT_LDT_INTDEST 5 -#define M_INT_LDT_INTDEST _SB_MAKEMASK(10,S_INT_LDT_INTDEST) -#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x,S_INT_LDT_INTDEST) -#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x,S_INT_LDT_INTDEST,M_INT_LDT_INTDEST) +#define M_INT_LDT_INTDEST _SB_MAKEMASK(10, S_INT_LDT_INTDEST) +#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x, S_INT_LDT_INTDEST) +#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST) #define S_INT_LDT_VECTOR 13 -#define M_INT_LDT_VECTOR _SB_MAKEMASK(8,S_INT_LDT_VECTOR) -#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x,S_INT_LDT_VECTOR) -#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x,S_INT_LDT_VECTOR,M_INT_LDT_VECTOR) +#define M_INT_LDT_VECTOR _SB_MAKEMASK(8, S_INT_LDT_VECTOR) +#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x, S_INT_LDT_VECTOR) +#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR) /* * Vector format (Table 4-6) diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h index 842f205..6554dcf 100644 --- a/include/asm-mips/sibyte/sb1250_l2c.h +++ b/include/asm-mips/sibyte/sb1250_l2c.h @@ -40,27 +40,27 @@ */ #define S_L2C_TAG_MBZ 0 -#define M_L2C_TAG_MBZ _SB_MAKEMASK(5,S_L2C_TAG_MBZ) +#define M_L2C_TAG_MBZ _SB_MAKEMASK(5, S_L2C_TAG_MBZ) #define S_L2C_TAG_INDEX 5 -#define M_L2C_TAG_INDEX _SB_MAKEMASK(12,S_L2C_TAG_INDEX) -#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_L2C_TAG_INDEX) -#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_L2C_TAG_INDEX,M_L2C_TAG_INDEX) +#define M_L2C_TAG_INDEX _SB_MAKEMASK(12, S_L2C_TAG_INDEX) +#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_L2C_TAG_INDEX) +#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_L2C_TAG_INDEX, M_L2C_TAG_INDEX) #define S_L2C_TAG_TAG 17 -#define M_L2C_TAG_TAG _SB_MAKEMASK(23,S_L2C_TAG_TAG) -#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_L2C_TAG_TAG) -#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_L2C_TAG_TAG,M_L2C_TAG_TAG) +#define M_L2C_TAG_TAG _SB_MAKEMASK(23, S_L2C_TAG_TAG) +#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_L2C_TAG_TAG) +#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_L2C_TAG_TAG, M_L2C_TAG_TAG) #define S_L2C_TAG_ECC 40 -#define M_L2C_TAG_ECC _SB_MAKEMASK(6,S_L2C_TAG_ECC) -#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_L2C_TAG_ECC) -#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_L2C_TAG_ECC,M_L2C_TAG_ECC) +#define M_L2C_TAG_ECC _SB_MAKEMASK(6, S_L2C_TAG_ECC) +#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_L2C_TAG_ECC) +#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_L2C_TAG_ECC, M_L2C_TAG_ECC) #define S_L2C_TAG_WAY 46 -#define M_L2C_TAG_WAY _SB_MAKEMASK(2,S_L2C_TAG_WAY) -#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_L2C_TAG_WAY) -#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_L2C_TAG_WAY,M_L2C_TAG_WAY) +#define M_L2C_TAG_WAY _SB_MAKEMASK(2, S_L2C_TAG_WAY) +#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_L2C_TAG_WAY) +#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_L2C_TAG_WAY, M_L2C_TAG_WAY) #define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48) #define M_L2C_TAG_VALID _SB_MAKEMASK1(49) @@ -70,32 +70,32 @@ */ #define S_L2C_MGMT_INDEX 5 -#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_L2C_MGMT_INDEX) -#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_L2C_MGMT_INDEX) -#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_L2C_MGMT_INDEX,M_L2C_MGMT_INDEX) +#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_L2C_MGMT_INDEX) +#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_L2C_MGMT_INDEX) +#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_L2C_MGMT_INDEX, M_L2C_MGMT_INDEX) #define S_L2C_MGMT_QUADRANT 15 -#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2,S_L2C_MGMT_QUADRANT) -#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x,S_L2C_MGMT_QUADRANT) -#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x,S_L2C_MGMT_QUADRANT,M_L2C_MGMT_QUADRANT) +#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2, S_L2C_MGMT_QUADRANT) +#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x, S_L2C_MGMT_QUADRANT) +#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x, S_L2C_MGMT_QUADRANT, M_L2C_MGMT_QUADRANT) #define S_L2C_MGMT_HALF 16 -#define M_L2C_MGMT_HALF _SB_MAKEMASK(1,S_L2C_MGMT_HALF) +#define M_L2C_MGMT_HALF _SB_MAKEMASK(1, S_L2C_MGMT_HALF) #define S_L2C_MGMT_WAY 17 -#define M_L2C_MGMT_WAY _SB_MAKEMASK(2,S_L2C_MGMT_WAY) -#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_L2C_MGMT_WAY) -#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY) +#define M_L2C_MGMT_WAY _SB_MAKEMASK(2, S_L2C_MGMT_WAY) +#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_L2C_MGMT_WAY) +#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_L2C_MGMT_WAY, M_L2C_MGMT_WAY) #define S_L2C_MGMT_ECC_DIAG 21 -#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2,S_L2C_MGMT_ECC_DIAG) -#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_ECC_DIAG) -#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x,S_L2C_MGMT_ECC_DIAG,M_L2C_MGMT_ECC_DIAG) +#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_L2C_MGMT_ECC_DIAG) +#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_ECC_DIAG) +#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_L2C_MGMT_ECC_DIAG, M_L2C_MGMT_ECC_DIAG) #define S_L2C_MGMT_TAG 23 -#define M_L2C_MGMT_TAG _SB_MAKEMASK(4,S_L2C_MGMT_TAG) -#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_TAG) -#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG) +#define M_L2C_MGMT_TAG _SB_MAKEMASK(4, S_L2C_MGMT_TAG) +#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_TAG) +#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x, S_L2C_MGMT_TAG, M_L2C_MGMT_TAG) #define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19) #define M_L2C_MGMT_VALID _SB_MAKEMASK1(20) @@ -111,9 +111,9 @@ * L2 Read Misc. register (A_L2_READ_MISC) */ #define S_L2C_MISC_NO_WAY 10 -#define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4,S_L2C_MISC_NO_WAY) -#define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x,S_L2C_MISC_NO_WAY) -#define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x,S_L2C_MISC_NO_WAY,M_L2C_MISC_NO_WAY) +#define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4, S_L2C_MISC_NO_WAY) +#define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x, S_L2C_MISC_NO_WAY) +#define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x, S_L2C_MISC_NO_WAY, M_L2C_MISC_NO_WAY) #define M_L2C_MISC_ECC_CLEANUP_DIS _SB_MAKEMASK1(9) #define M_L2C_MISC_MC_PRIO_LOW _SB_MAKEMASK1(8) diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h index 7092535..081e8b1 100644 --- a/include/asm-mips/sibyte/sb1250_ldt.h +++ b/include/asm-mips/sibyte/sb1250_ldt.h @@ -10,7 +10,7 @@ * ********************************************************************* * - * Copyright 2000,2001,2002,2003 + * Copyright 2000, 2001, 2002, 2003 * Broadcom Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or @@ -81,14 +81,14 @@ */ #define S_LDT_DEVICEID_VENDOR 0 -#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16,S_LDT_DEVICEID_VENDOR) -#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_VENDOR) -#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_VENDOR,M_LDT_DEVICEID_VENDOR) +#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16, S_LDT_DEVICEID_VENDOR) +#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_VENDOR) +#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_VENDOR, M_LDT_DEVICEID_VENDOR) #define S_LDT_DEVICEID_DEVICEID 16 -#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16,S_LDT_DEVICEID_DEVICEID) -#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_DEVICEID) -#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_DEVICEID,M_LDT_DEVICEID_DEVICEID) +#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16, S_LDT_DEVICEID_DEVICEID) +#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_DEVICEID) +#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_DEVICEID, M_LDT_DEVICEID_DEVICEID) /* @@ -111,14 +111,14 @@ */ #define S_LDT_CLASSREV_REV 0 -#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8,S_LDT_CLASSREV_REV) -#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_REV) -#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_REV,M_LDT_CLASSREV_REV) +#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8, S_LDT_CLASSREV_REV) +#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_REV) +#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_REV, M_LDT_CLASSREV_REV) #define S_LDT_CLASSREV_CLASS 8 -#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24,S_LDT_CLASSREV_CLASS) -#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_CLASS) -#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_CLASS,M_LDT_CLASSREV_CLASS) +#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24, S_LDT_CLASSREV_CLASS) +#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_CLASS) +#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_CLASS, M_LDT_CLASSREV_CLASS) #define K_LDT_REV 0x01 #define K_LDT_CLASS 0x060000 @@ -128,26 +128,26 @@ */ #define S_LDT_DEVHDR_CLINESZ 0 -#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8,S_LDT_DEVHDR_CLINESZ) -#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_CLINESZ) -#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_CLINESZ,M_LDT_DEVHDR_CLINESZ) +#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8, S_LDT_DEVHDR_CLINESZ) +#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_CLINESZ) +#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_CLINESZ, M_LDT_DEVHDR_CLINESZ) #define S_LDT_DEVHDR_LATTMR 8 -#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8,S_LDT_DEVHDR_LATTMR) -#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_LATTMR) -#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_LATTMR,M_LDT_DEVHDR_LATTMR) +#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8, S_LDT_DEVHDR_LATTMR) +#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_LATTMR) +#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_LATTMR, M_LDT_DEVHDR_LATTMR) #define S_LDT_DEVHDR_HDRTYPE 16 -#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8,S_LDT_DEVHDR_HDRTYPE) -#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_HDRTYPE) -#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_HDRTYPE,M_LDT_DEVHDR_HDRTYPE) +#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8, S_LDT_DEVHDR_HDRTYPE) +#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_HDRTYPE) +#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_HDRTYPE, M_LDT_DEVHDR_HDRTYPE) #define K_LDT_DEVHDR_HDRTYPE_TYPE1 1 #define S_LDT_DEVHDR_BIST 24 -#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8,S_LDT_DEVHDR_BIST) -#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_BIST) -#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_BIST,M_LDT_DEVHDR_BIST) +#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8, S_LDT_DEVHDR_BIST) +#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_BIST) +#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_BIST, M_LDT_DEVHDR_BIST) @@ -170,9 +170,9 @@ #define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24) #define S_LDT_STATUS_DEVSELTIMING 25 -#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2,S_LDT_STATUS_DEVSELTIMING) -#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x,S_LDT_STATUS_DEVSELTIMING) -#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x,S_LDT_STATUS_DEVSELTIMING,M_LDT_STATUS_DEVSELTIMING) +#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2, S_LDT_STATUS_DEVSELTIMING) +#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x, S_LDT_STATUS_DEVSELTIMING) +#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x, S_LDT_STATUS_DEVSELTIMING, M_LDT_STATUS_DEVSELTIMING) #define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27) #define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28) @@ -208,9 +208,9 @@ #define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17) #define S_LDT_CMD_CAPTYPE 29 -#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3,S_LDT_CMD_CAPTYPE) -#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_CMD_CAPTYPE) -#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x,S_LDT_CMD_CAPTYPE,M_LDT_CMD_CAPTYPE) +#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3, S_LDT_CMD_CAPTYPE) +#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_CMD_CAPTYPE) +#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x, S_LDT_CMD_CAPTYPE, M_LDT_CMD_CAPTYPE) /* * LDT link control register (Table 8-18), and (Table 8-19) @@ -225,35 +225,35 @@ #define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7) #define S_LDT_LINKCTRL_CRCERR 8 -#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4,S_LDT_LINKCTRL_CRCERR) -#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_CRCERR) -#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_CRCERR,M_LDT_LINKCTRL_CRCERR) +#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4, S_LDT_LINKCTRL_CRCERR) +#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_CRCERR) +#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_CRCERR, M_LDT_LINKCTRL_CRCERR) #define S_LDT_LINKCTRL_MAXIN 16 -#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXIN) -#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXIN) -#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXIN,M_LDT_LINKCTRL_MAXIN) +#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXIN) +#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXIN) +#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXIN, M_LDT_LINKCTRL_MAXIN) #define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19) #define S_LDT_LINKCTRL_MAXOUT 20 -#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXOUT) -#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXOUT) -#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXOUT,M_LDT_LINKCTRL_MAXOUT) +#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXOUT) +#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXOUT) +#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXOUT, M_LDT_LINKCTRL_MAXOUT) #define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23) #define S_LDT_LINKCTRL_WIDTHIN 24 -#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHIN) -#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN) -#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN,M_LDT_LINKCTRL_WIDTHIN) +#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHIN) +#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN) +#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN, M_LDT_LINKCTRL_WIDTHIN) #define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27) #define S_LDT_LINKCTRL_WIDTHOUT 28 -#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHOUT) -#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT) -#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT,M_LDT_LINKCTRL_WIDTHOUT) +#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHOUT) +#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT) +#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT, M_LDT_LINKCTRL_WIDTHOUT) #define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31) @@ -262,9 +262,9 @@ */ #define S_LDT_LINKFREQ_FREQ 8 -#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4,S_LDT_LINKFREQ_FREQ) -#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x,S_LDT_LINKFREQ_FREQ) -#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x,S_LDT_LINKFREQ_FREQ,M_LDT_LINKFREQ_FREQ) +#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4, S_LDT_LINKFREQ_FREQ) +#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x, S_LDT_LINKFREQ_FREQ) +#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x, S_LDT_LINKFREQ_FREQ, M_LDT_LINKFREQ_FREQ) #define K_LDT_LINKFREQ_200MHZ 0 #define K_LDT_LINKFREQ_300MHZ 1 @@ -293,16 +293,16 @@ #define S_LDT_SRICMD_RXMARGIN 20 -#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5,S_LDT_SRICMD_RXMARGIN) -#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_RXMARGIN) -#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_RXMARGIN,M_LDT_SRICMD_RXMARGIN) +#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5, S_LDT_SRICMD_RXMARGIN) +#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_RXMARGIN) +#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_RXMARGIN, M_LDT_SRICMD_RXMARGIN) #define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25) #define S_LDT_SRICMD_TXINITIALOFFSET 28 -#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3,S_LDT_SRICMD_TXINITIALOFFSET) -#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET) -#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET,M_LDT_SRICMD_TXINITIALOFFSET) +#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET) +#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET) +#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET) #define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31) @@ -340,73 +340,73 @@ */ #define S_LDT_SRICTRL_NEEDRESP 0 -#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDRESP) -#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDRESP) -#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDRESP,M_LDT_SRICTRL_NEEDRESP) +#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDRESP) +#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDRESP) +#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDRESP, M_LDT_SRICTRL_NEEDRESP) #define S_LDT_SRICTRL_NEEDNPREQ 2 -#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDNPREQ) -#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ) -#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ,M_LDT_SRICTRL_NEEDNPREQ) +#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDNPREQ) +#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ) +#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ, M_LDT_SRICTRL_NEEDNPREQ) #define S_LDT_SRICTRL_NEEDPREQ 4 -#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDPREQ) -#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ) -#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ,M_LDT_SRICTRL_NEEDPREQ) +#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDPREQ) +#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ) +#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ, M_LDT_SRICTRL_NEEDPREQ) #define S_LDT_SRICTRL_WANTRESP 8 -#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTRESP) -#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTRESP) -#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTRESP,M_LDT_SRICTRL_WANTRESP) +#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTRESP) +#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTRESP) +#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTRESP, M_LDT_SRICTRL_WANTRESP) #define S_LDT_SRICTRL_WANTNPREQ 10 -#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTNPREQ) -#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ) -#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ,M_LDT_SRICTRL_WANTNPREQ) +#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTNPREQ) +#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ) +#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ, M_LDT_SRICTRL_WANTNPREQ) #define S_LDT_SRICTRL_WANTPREQ 12 -#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTPREQ) -#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTPREQ) -#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTPREQ,M_LDT_SRICTRL_WANTPREQ) +#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTPREQ) +#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTPREQ) +#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTPREQ, M_LDT_SRICTRL_WANTPREQ) #define S_LDT_SRICTRL_BUFRELSPACE 16 -#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4,S_LDT_SRICTRL_BUFRELSPACE) -#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE) -#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE,M_LDT_SRICTRL_BUFRELSPACE) +#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4, S_LDT_SRICTRL_BUFRELSPACE) +#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE) +#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE, M_LDT_SRICTRL_BUFRELSPACE) /* * LDT SRI Transmit Buffer Count register (Table 8-26) */ #define S_LDT_TXBUFCNT_PCMD 0 -#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PCMD) -#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PCMD) -#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PCMD,M_LDT_TXBUFCNT_PCMD) +#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PCMD) +#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PCMD) +#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PCMD, M_LDT_TXBUFCNT_PCMD) #define S_LDT_TXBUFCNT_PDATA 4 -#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PDATA) -#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PDATA) -#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PDATA,M_LDT_TXBUFCNT_PDATA) +#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PDATA) +#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PDATA) +#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PDATA, M_LDT_TXBUFCNT_PDATA) #define S_LDT_TXBUFCNT_NPCMD 8 -#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPCMD) -#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPCMD) -#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPCMD,M_LDT_TXBUFCNT_NPCMD) +#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPCMD) +#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPCMD) +#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPCMD, M_LDT_TXBUFCNT_NPCMD) #define S_LDT_TXBUFCNT_NPDATA 12 -#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPDATA) -#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPDATA) -#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPDATA,M_LDT_TXBUFCNT_NPDATA) +#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPDATA) +#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPDATA) +#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPDATA, M_LDT_TXBUFCNT_NPDATA) #define S_LDT_TXBUFCNT_RCMD 16 -#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RCMD) -#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RCMD) -#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RCMD,M_LDT_TXBUFCNT_RCMD) +#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RCMD) +#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RCMD) +#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RCMD, M_LDT_TXBUFCNT_RCMD) #define S_LDT_TXBUFCNT_RDATA 20 -#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RDATA) -#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RDATA) -#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RDATA,M_LDT_TXBUFCNT_RDATA) +#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RDATA) +#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RDATA) +#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RDATA, M_LDT_TXBUFCNT_RDATA) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) /* @@ -414,9 +414,9 @@ */ #define S_LDT_ADDSTATUS_TGTDONE 0 -#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8,S_LDT_ADDSTATUS_TGTDONE) -#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE) -#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE,M_LDT_ADDSTATUS_TGTDONE) +#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8, S_LDT_ADDSTATUS_TGTDONE) +#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE) +#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE, M_LDT_ADDSTATUS_TGTDONE) #endif /* 1250 PASS2 || 112x PASS1 */ #endif diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h index 833c8b5..b6faf08 100644 --- a/include/asm-mips/sibyte/sb1250_mac.h +++ b/include/asm-mips/sibyte/sb1250_mac.h @@ -55,8 +55,8 @@ #define M_MAC_BURST_EN _SB_MAKEMASK1(5) #define S_MAC_TX_PAUSE _SB_MAKE64(6) -#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3,S_MAC_TX_PAUSE) -#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x,S_MAC_TX_PAUSE) +#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3, S_MAC_TX_PAUSE) +#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x, S_MAC_TX_PAUSE) #define K_MAC_TX_PAUSE_CNT_512 0 #define K_MAC_TX_PAUSE_CNT_1K 1 @@ -76,7 +76,7 @@ #define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) #define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) -#define M_MAC_RESERVED1 _SB_MAKEMASK(8,9) +#define M_MAC_RESERVED1 _SB_MAKEMASK(8, 9) #define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) @@ -91,15 +91,15 @@ #define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) #define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) -#define M_MAC_RESERVED3 _SB_MAKEMASK(6,26) +#define M_MAC_RESERVED3 _SB_MAKEMASK(6, 26) #define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) #define M_MAC_HDX_EN _SB_MAKEMASK1(33) #define S_MAC_SPEED_SEL _SB_MAKE64(34) -#define M_MAC_SPEED_SEL _SB_MAKEMASK(2,S_MAC_SPEED_SEL) -#define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x,S_MAC_SPEED_SEL) -#define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x,S_MAC_SPEED_SEL,M_MAC_SPEED_SEL) +#define M_MAC_SPEED_SEL _SB_MAKEMASK(2, S_MAC_SPEED_SEL) +#define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x, S_MAC_SPEED_SEL) +#define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x, S_MAC_SPEED_SEL, M_MAC_SPEED_SEL) #define K_MAC_SPEED_SEL_10MBPS 0 #define K_MAC_SPEED_SEL_100MBPS 1 @@ -117,9 +117,9 @@ #define M_MAC_SS_EN _SB_MAKEMASK1(39) #define S_MAC_BYPASS_CFG _SB_MAKE64(40) -#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2,S_MAC_BYPASS_CFG) -#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_CFG) -#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_CFG,M_MAC_BYPASS_CFG) +#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2, S_MAC_BYPASS_CFG) +#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_CFG) +#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_CFG, M_MAC_BYPASS_CFG) #define K_MAC_BYPASS_GMII 0 #define K_MAC_BYPASS_ENCODED 1 @@ -138,9 +138,9 @@ #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_MAC_BYPASS_IFG _SB_MAKE64(46) -#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG) -#define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_IFG) -#define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_IFG,M_MAC_BYPASS_IFG) +#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8, S_MAC_BYPASS_IFG) +#define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_IFG) +#define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_IFG, M_MAC_BYPASS_IFG) #define K_MAC_FC_CMD_DISABLED 0 #define K_MAC_FC_CMD_ENABLED 1 @@ -153,14 +153,14 @@ #define M_MAC_FC_SEL _SB_MAKEMASK1(54) #define S_MAC_FC_CMD _SB_MAKE64(55) -#define M_MAC_FC_CMD _SB_MAKEMASK(2,S_MAC_FC_CMD) -#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x,S_MAC_FC_CMD) -#define G_MAC_FC_CMD(x) _SB_GETVALUE(x,S_MAC_FC_CMD,M_MAC_FC_CMD) +#define M_MAC_FC_CMD _SB_MAKEMASK(2, S_MAC_FC_CMD) +#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x, S_MAC_FC_CMD) +#define G_MAC_FC_CMD(x) _SB_GETVALUE(x, S_MAC_FC_CMD, M_MAC_FC_CMD) #define S_MAC_RX_CH_SEL _SB_MAKE64(57) -#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7,S_MAC_RX_CH_SEL) -#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_SEL) -#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_SEL,M_MAC_RX_CH_SEL) +#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7, S_MAC_RX_CH_SEL) +#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_SEL) +#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_SEL, M_MAC_RX_CH_SEL) /* @@ -202,14 +202,14 @@ */ #define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) -#define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT0) -#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT0) -#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT0,M_MAC_TXD_WEIGHT0) +#define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT0) +#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT0) +#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT0, M_MAC_TXD_WEIGHT0) #define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) -#define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT1) -#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT1) -#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT1,M_MAC_TXD_WEIGHT1) +#define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT1) +#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT1) +#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1) /* * MAC Fifo Threshhold registers (Table 9-14) @@ -221,50 +221,50 @@ #define S_MAC_TX_WR_THRSH _SB_MAKE64(0) #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) /* XXX: Can't enable, as it has the same name as a pass2+ define below. */ -/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */ +/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6, S_MAC_TX_WR_THRSH) */ #endif /* up to 1250 PASS1 */ #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH) +#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7, S_MAC_TX_WR_THRSH) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH) -#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH) +#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_WR_THRSH) +#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_WR_THRSH, M_MAC_TX_WR_THRSH) #define S_MAC_TX_RD_THRSH _SB_MAKE64(8) #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) /* XXX: Can't enable, as it has the same name as a pass2+ define below. */ -/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */ +/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6, S_MAC_TX_RD_THRSH) */ #endif /* up to 1250 PASS1 */ #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH) +#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7, S_MAC_TX_RD_THRSH) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH) -#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH) +#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RD_THRSH) +#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RD_THRSH, M_MAC_TX_RD_THRSH) #define S_MAC_TX_RL_THRSH _SB_MAKE64(16) -#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4,S_MAC_TX_RL_THRSH) -#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RL_THRSH) -#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RL_THRSH,M_MAC_TX_RL_THRSH) +#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4, S_MAC_TX_RL_THRSH) +#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RL_THRSH) +#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RL_THRSH, M_MAC_TX_RL_THRSH) #define S_MAC_RX_PL_THRSH _SB_MAKE64(24) -#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6,S_MAC_RX_PL_THRSH) -#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_PL_THRSH) -#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_PL_THRSH,M_MAC_RX_PL_THRSH) +#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6, S_MAC_RX_PL_THRSH) +#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_PL_THRSH) +#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_PL_THRSH, M_MAC_RX_PL_THRSH) #define S_MAC_RX_RD_THRSH _SB_MAKE64(32) -#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6,S_MAC_RX_RD_THRSH) -#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RD_THRSH) -#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RD_THRSH,M_MAC_RX_RD_THRSH) +#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6, S_MAC_RX_RD_THRSH) +#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RD_THRSH) +#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RD_THRSH, M_MAC_RX_RD_THRSH) #define S_MAC_RX_RL_THRSH _SB_MAKE64(40) -#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6,S_MAC_RX_RL_THRSH) -#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH) -#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH) +#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6, S_MAC_RX_RL_THRSH) +#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RL_THRSH) +#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RL_THRSH, M_MAC_RX_RL_THRSH) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) -#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH) -#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH) -#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH) +#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6, S_MAC_ENC_FC_THRSH) +#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x, S_MAC_ENC_FC_THRSH) +#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x, S_MAC_ENC_FC_THRSH, M_MAC_ENC_FC_THRSH) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ /* @@ -276,51 +276,51 @@ /* XXXCGD: ??? Unused in pass2? */ #define S_MAC_IFG_RX _SB_MAKE64(0) -#define M_MAC_IFG_RX _SB_MAKEMASK(6,S_MAC_IFG_RX) -#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX) -#define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX) +#define M_MAC_IFG_RX _SB_MAKEMASK(6, S_MAC_IFG_RX) +#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x, S_MAC_IFG_RX) +#define G_MAC_IFG_RX(x) _SB_GETVALUE(x, S_MAC_IFG_RX, M_MAC_IFG_RX) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_MAC_PRE_LEN _SB_MAKE64(0) -#define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN) -#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN) -#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN) +#define M_MAC_PRE_LEN _SB_MAKEMASK(6, S_MAC_PRE_LEN) +#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x, S_MAC_PRE_LEN) +#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x, S_MAC_PRE_LEN, M_MAC_PRE_LEN) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_MAC_IFG_TX _SB_MAKE64(6) -#define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX) -#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x,S_MAC_IFG_TX) -#define G_MAC_IFG_TX(x) _SB_GETVALUE(x,S_MAC_IFG_TX,M_MAC_IFG_TX) +#define M_MAC_IFG_TX _SB_MAKEMASK(6, S_MAC_IFG_TX) +#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x, S_MAC_IFG_TX) +#define G_MAC_IFG_TX(x) _SB_GETVALUE(x, S_MAC_IFG_TX, M_MAC_IFG_TX) #define S_MAC_IFG_THRSH _SB_MAKE64(12) -#define M_MAC_IFG_THRSH _SB_MAKEMASK(6,S_MAC_IFG_THRSH) -#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x,S_MAC_IFG_THRSH) -#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x,S_MAC_IFG_THRSH,M_MAC_IFG_THRSH) +#define M_MAC_IFG_THRSH _SB_MAKEMASK(6, S_MAC_IFG_THRSH) +#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x, S_MAC_IFG_THRSH) +#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x, S_MAC_IFG_THRSH, M_MAC_IFG_THRSH) #define S_MAC_BACKOFF_SEL _SB_MAKE64(18) -#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4,S_MAC_BACKOFF_SEL) -#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x,S_MAC_BACKOFF_SEL) -#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x,S_MAC_BACKOFF_SEL,M_MAC_BACKOFF_SEL) +#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4, S_MAC_BACKOFF_SEL) +#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x, S_MAC_BACKOFF_SEL) +#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x, S_MAC_BACKOFF_SEL, M_MAC_BACKOFF_SEL) #define S_MAC_LFSR_SEED _SB_MAKE64(22) -#define M_MAC_LFSR_SEED _SB_MAKEMASK(8,S_MAC_LFSR_SEED) -#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x,S_MAC_LFSR_SEED) -#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x,S_MAC_LFSR_SEED,M_MAC_LFSR_SEED) +#define M_MAC_LFSR_SEED _SB_MAKEMASK(8, S_MAC_LFSR_SEED) +#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x, S_MAC_LFSR_SEED) +#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x, S_MAC_LFSR_SEED, M_MAC_LFSR_SEED) #define S_MAC_SLOT_SIZE _SB_MAKE64(30) -#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10,S_MAC_SLOT_SIZE) -#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x,S_MAC_SLOT_SIZE) -#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x,S_MAC_SLOT_SIZE,M_MAC_SLOT_SIZE) +#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10, S_MAC_SLOT_SIZE) +#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x, S_MAC_SLOT_SIZE) +#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x, S_MAC_SLOT_SIZE, M_MAC_SLOT_SIZE) #define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) -#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8,S_MAC_MIN_FRAMESZ) -#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MIN_FRAMESZ) -#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MIN_FRAMESZ,M_MAC_MIN_FRAMESZ) +#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8, S_MAC_MIN_FRAMESZ) +#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MIN_FRAMESZ) +#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MIN_FRAMESZ, M_MAC_MIN_FRAMESZ) #define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) -#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16,S_MAC_MAX_FRAMESZ) -#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MAX_FRAMESZ) -#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MAX_FRAMESZ,M_MAC_MAX_FRAMESZ) +#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16, S_MAC_MAX_FRAMESZ) +#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MAX_FRAMESZ) +#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MAX_FRAMESZ, M_MAC_MAX_FRAMESZ) /* * These constants are used to configure the fields within the Frame @@ -377,20 +377,20 @@ */ #define S_MAC_VLAN_TAG _SB_MAKE64(0) -#define M_MAC_VLAN_TAG _SB_MAKEMASK(32,S_MAC_VLAN_TAG) -#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x,S_MAC_VLAN_TAG) -#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x,S_MAC_VLAN_TAG,M_MAC_VLAN_TAG) +#define M_MAC_VLAN_TAG _SB_MAKEMASK(32, S_MAC_VLAN_TAG) +#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x, S_MAC_VLAN_TAG) +#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x, S_MAC_VLAN_TAG, M_MAC_VLAN_TAG) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) #define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) -#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_TX_PKT_OFFSET) -#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_PKT_OFFSET) -#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_PKT_OFFSET,M_MAC_TX_PKT_OFFSET) +#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_TX_PKT_OFFSET) +#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_PKT_OFFSET) +#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_PKT_OFFSET, M_MAC_TX_PKT_OFFSET) #define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) -#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_TX_CRC_OFFSET) -#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_CRC_OFFSET) -#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_CRC_OFFSET,M_MAC_TX_CRC_OFFSET) +#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_TX_CRC_OFFSET) +#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_CRC_OFFSET) +#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_CRC_OFFSET, M_MAC_TX_CRC_OFFSET) #define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48) #endif /* 1250 PASS3 || 112x PASS1 */ @@ -425,7 +425,7 @@ * is that you'll use one of the "S_" things above * and pass just the six bits to a DMA-channel-specific ISR */ -#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8,0) +#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8, 0) #define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) #define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) #define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) @@ -440,19 +440,19 @@ * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see * also DMA_TX/DMA_RX in sb_regs.h). */ -#define S_MAC_STATUS_CH_OFFSET(ch,txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) +#define S_MAC_STATUS_CH_OFFSET(ch, txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) -#define M_MAC_STATUS_CHANNEL(ch,txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8,0),S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_EOP_COUNT(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_EOP_TIMER(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_EOP_SEEN(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_HWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_HWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_LWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_LWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_DSCR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_ERR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_ERR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_DZERO(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_DROP(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DROP,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7,0),40) +#define M_MAC_STATUS_CHANNEL(ch, txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8, 0), S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_EOP_COUNT(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_EOP_TIMER(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_EOP_SEEN(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_HWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_HWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_LWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_LWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_DSCR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_ERR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_ERR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_DZERO(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_DROP(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DROP, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7, 0), 40) #define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) @@ -467,9 +467,9 @@ #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_MAC_COUNTER_ADDR _SB_MAKE64(47) -#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR) -#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR) -#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR) +#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5, S_MAC_COUNTER_ADDR) +#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x, S_MAC_COUNTER_ADDR) +#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x, S_MAC_COUNTER_ADDR, M_MAC_COUNTER_ADDR) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) @@ -483,24 +483,24 @@ */ #define S_MAC_TX_WRPTR _SB_MAKE64(0) -#define M_MAC_TX_WRPTR _SB_MAKEMASK(6,S_MAC_TX_WRPTR) -#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_WRPTR) -#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x,S_MAC_TX_WRPTR,M_MAC_TX_WRPTR) +#define M_MAC_TX_WRPTR _SB_MAKEMASK(6, S_MAC_TX_WRPTR) +#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_WRPTR) +#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x, S_MAC_TX_WRPTR, M_MAC_TX_WRPTR) #define S_MAC_TX_RDPTR _SB_MAKE64(8) -#define M_MAC_TX_RDPTR _SB_MAKEMASK(6,S_MAC_TX_RDPTR) -#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_RDPTR) -#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x,S_MAC_TX_RDPTR,M_MAC_TX_RDPTR) +#define M_MAC_TX_RDPTR _SB_MAKEMASK(6, S_MAC_TX_RDPTR) +#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_RDPTR) +#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x, S_MAC_TX_RDPTR, M_MAC_TX_RDPTR) #define S_MAC_RX_WRPTR _SB_MAKE64(16) -#define M_MAC_RX_WRPTR _SB_MAKEMASK(6,S_MAC_RX_WRPTR) -#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_WRPTR) -#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x,S_MAC_RX_WRPTR,M_MAC_TX_WRPTR) +#define M_MAC_RX_WRPTR _SB_MAKEMASK(6, S_MAC_RX_WRPTR) +#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_WRPTR) +#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x, S_MAC_RX_WRPTR, M_MAC_TX_WRPTR) #define S_MAC_RX_RDPTR _SB_MAKE64(24) -#define M_MAC_RX_RDPTR _SB_MAKEMASK(6,S_MAC_RX_RDPTR) -#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_RDPTR) -#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x,S_MAC_RX_RDPTR,M_MAC_TX_RDPTR) +#define M_MAC_RX_RDPTR _SB_MAKEMASK(6, S_MAC_RX_RDPTR) +#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_RDPTR) +#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x, S_MAC_RX_RDPTR, M_MAC_TX_RDPTR) /* * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] @@ -510,14 +510,14 @@ */ #define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) -#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_TX_EOP_COUNTER) -#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_TX_EOP_COUNTER) -#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_TX_EOP_COUNTER,M_MAC_TX_EOP_COUNTER) +#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_TX_EOP_COUNTER) +#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_TX_EOP_COUNTER) +#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_TX_EOP_COUNTER, M_MAC_TX_EOP_COUNTER) #define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) -#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_RX_EOP_COUNTER) -#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_RX_EOP_COUNTER) -#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_RX_EOP_COUNTER,M_MAC_RX_EOP_COUNTER) +#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_RX_EOP_COUNTER) +#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_RX_EOP_COUNTER) +#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER) /* * MAC Recieve Address Filter Exact Match Registers (Table 9-21) @@ -565,24 +565,24 @@ #define S_TYPECFG_TYPESIZE _SB_MAKE64(16) #define S_TYPECFG_TYPE0 _SB_MAKE64(0) -#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16,S_TYPECFG_TYPE0) -#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE0) -#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x,S_TYPECFG_TYPE0,M_TYPECFG_TYPE0) +#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16, S_TYPECFG_TYPE0) +#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE0) +#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x, S_TYPECFG_TYPE0, M_TYPECFG_TYPE0) #define S_TYPECFG_TYPE1 _SB_MAKE64(0) -#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16,S_TYPECFG_TYPE1) -#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE1) -#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x,S_TYPECFG_TYPE1,M_TYPECFG_TYPE1) +#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16, S_TYPECFG_TYPE1) +#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE1) +#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x, S_TYPECFG_TYPE1, M_TYPECFG_TYPE1) #define S_TYPECFG_TYPE2 _SB_MAKE64(0) -#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16,S_TYPECFG_TYPE2) -#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE2) -#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x,S_TYPECFG_TYPE2,M_TYPECFG_TYPE2) +#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16, S_TYPECFG_TYPE2) +#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE2) +#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x, S_TYPECFG_TYPE2, M_TYPECFG_TYPE2) #define S_TYPECFG_TYPE3 _SB_MAKE64(0) -#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16,S_TYPECFG_TYPE3) -#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE3) -#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x,S_TYPECFG_TYPE3,M_TYPECFG_TYPE3) +#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16, S_TYPECFG_TYPE3) +#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE3) +#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x, S_TYPECFG_TYPE3, M_TYPECFG_TYPE3) /* * MAC Receive Address Filter Control Registers (Table 9-24) @@ -603,28 +603,28 @@ #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) -#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET) -#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET) -#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET) +#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8, S_MAC_IPHDR_OFFSET) +#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_IPHDR_OFFSET) +#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x, S_MAC_IPHDR_OFFSET, M_MAC_IPHDR_OFFSET) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) -#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET) -#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET) -#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_CRC_OFFSET,M_MAC_RX_CRC_OFFSET) +#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_RX_CRC_OFFSET) +#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_CRC_OFFSET) +#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_CRC_OFFSET, M_MAC_RX_CRC_OFFSET) #define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) -#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_RX_PKT_OFFSET) -#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_PKT_OFFSET) -#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_PKT_OFFSET,M_MAC_RX_PKT_OFFSET) +#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_RX_PKT_OFFSET) +#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_PKT_OFFSET) +#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_PKT_OFFSET, M_MAC_RX_PKT_OFFSET) #define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32) #define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33) #define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) -#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL) -#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL) -#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL) +#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8, S_MAC_RX_CH_MSN_SEL) +#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_MSN_SEL) +#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_MSN_SEL, M_MAC_RX_CH_MSN_SEL) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ /* diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h index 4fe848f..1eb1b5a 100644 --- a/include/asm-mips/sibyte/sb1250_mc.h +++ b/include/asm-mips/sibyte/sb1250_mc.h @@ -10,7 +10,7 @@ * ********************************************************************* * - * Copyright 2000,2001,2002,2003 + * Copyright 2000, 2001, 2002, 2003 * Broadcom Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or @@ -40,73 +40,73 @@ */ #define S_MC_RESERVED0 0 -#define M_MC_RESERVED0 _SB_MAKEMASK(8,S_MC_RESERVED0) +#define M_MC_RESERVED0 _SB_MAKEMASK(8, S_MC_RESERVED0) #define S_MC_CHANNEL_SEL 8 -#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8,S_MC_CHANNEL_SEL) -#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x,S_MC_CHANNEL_SEL) -#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x,S_MC_CHANNEL_SEL,M_MC_CHANNEL_SEL) +#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8, S_MC_CHANNEL_SEL) +#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL) +#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL) #define S_MC_BANK0_MAP 16 -#define M_MC_BANK0_MAP _SB_MAKEMASK(4,S_MC_BANK0_MAP) -#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK0_MAP) -#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x,S_MC_BANK0_MAP,M_MC_BANK0_MAP) +#define M_MC_BANK0_MAP _SB_MAKEMASK(4, S_MC_BANK0_MAP) +#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK0_MAP) +#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP) #define K_MC_BANK0_MAP_DEFAULT 0x00 #define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT) #define S_MC_BANK1_MAP 20 -#define M_MC_BANK1_MAP _SB_MAKEMASK(4,S_MC_BANK1_MAP) -#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK1_MAP) -#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x,S_MC_BANK1_MAP,M_MC_BANK1_MAP) +#define M_MC_BANK1_MAP _SB_MAKEMASK(4, S_MC_BANK1_MAP) +#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK1_MAP) +#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP) #define K_MC_BANK1_MAP_DEFAULT 0x08 #define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT) #define S_MC_BANK2_MAP 24 -#define M_MC_BANK2_MAP _SB_MAKEMASK(4,S_MC_BANK2_MAP) -#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK2_MAP) -#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x,S_MC_BANK2_MAP,M_MC_BANK2_MAP) +#define M_MC_BANK2_MAP _SB_MAKEMASK(4, S_MC_BANK2_MAP) +#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK2_MAP) +#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP) #define K_MC_BANK2_MAP_DEFAULT 0x09 #define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT) #define S_MC_BANK3_MAP 28 -#define M_MC_BANK3_MAP _SB_MAKEMASK(4,S_MC_BANK3_MAP) -#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK3_MAP) -#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x,S_MC_BANK3_MAP,M_MC_BANK3_MAP) +#define M_MC_BANK3_MAP _SB_MAKEMASK(4, S_MC_BANK3_MAP) +#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK3_MAP) +#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP) #define K_MC_BANK3_MAP_DEFAULT 0x0C #define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT) -#define M_MC_RESERVED1 _SB_MAKEMASK(8,32) +#define M_MC_RESERVED1 _SB_MAKEMASK(8, 32) #define S_MC_QUEUE_SIZE 40 -#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4,S_MC_QUEUE_SIZE) -#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x,S_MC_QUEUE_SIZE) -#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x,S_MC_QUEUE_SIZE,M_MC_QUEUE_SIZE) +#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4, S_MC_QUEUE_SIZE) +#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE) +#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE) #define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A) #define S_MC_AGE_LIMIT 44 -#define M_MC_AGE_LIMIT _SB_MAKEMASK(4,S_MC_AGE_LIMIT) -#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x,S_MC_AGE_LIMIT) -#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x,S_MC_AGE_LIMIT,M_MC_AGE_LIMIT) +#define M_MC_AGE_LIMIT _SB_MAKEMASK(4, S_MC_AGE_LIMIT) +#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x, S_MC_AGE_LIMIT) +#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT) #define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8) #define S_MC_WR_LIMIT 48 -#define M_MC_WR_LIMIT _SB_MAKEMASK(4,S_MC_WR_LIMIT) -#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x,S_MC_WR_LIMIT) -#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x,S_MC_WR_LIMIT,M_MC_WR_LIMIT) +#define M_MC_WR_LIMIT _SB_MAKEMASK(4, S_MC_WR_LIMIT) +#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x, S_MC_WR_LIMIT) +#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT) #define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5) #define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52) -#define M_MC_RESERVED2 _SB_MAKEMASK(3,53) +#define M_MC_RESERVED2 _SB_MAKEMASK(3, 53) #define S_MC_CS_MODE 56 -#define M_MC_CS_MODE _SB_MAKEMASK(4,S_MC_CS_MODE) -#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_MC_CS_MODE) -#define G_MC_CS_MODE(x) _SB_GETVALUE(x,S_MC_CS_MODE,M_MC_CS_MODE) +#define M_MC_CS_MODE _SB_MAKEMASK(4, S_MC_CS_MODE) +#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_MC_CS_MODE) +#define G_MC_CS_MODE(x) _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE) #define K_MC_CS_MODE_MSB_CS 0 #define K_MC_CS_MODE_INTLV_CS 15 @@ -138,9 +138,9 @@ */ #define S_MC_CLK_RATIO 0 -#define M_MC_CLK_RATIO _SB_MAKEMASK(4,S_MC_CLK_RATIO) -#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_MC_CLK_RATIO) -#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_MC_CLK_RATIO,M_MC_CLK_RATIO) +#define M_MC_CLK_RATIO _SB_MAKEMASK(4, S_MC_CLK_RATIO) +#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_MC_CLK_RATIO) +#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO) #define K_MC_CLK_RATIO_2X 4 #define K_MC_CLK_RATIO_25X 5 @@ -158,9 +158,9 @@ #define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X #define S_MC_REF_RATE 8 -#define M_MC_REF_RATE _SB_MAKEMASK(8,S_MC_REF_RATE) -#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_MC_REF_RATE) -#define G_MC_REF_RATE(x) _SB_GETVALUE(x,S_MC_REF_RATE,M_MC_REF_RATE) +#define M_MC_REF_RATE _SB_MAKEMASK(8, S_MC_REF_RATE) +#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_MC_REF_RATE) +#define G_MC_REF_RATE(x) _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE) #define K_MC_REF_RATE_100MHz 0x62 #define K_MC_REF_RATE_133MHz 0x81 @@ -172,21 +172,21 @@ #define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz #define S_MC_CLOCK_DRIVE 16 -#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4,S_MC_CLOCK_DRIVE) -#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x,S_MC_CLOCK_DRIVE) -#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x,S_MC_CLOCK_DRIVE,M_MC_CLOCK_DRIVE) +#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE) +#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE) +#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE) #define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF) #define S_MC_DATA_DRIVE 20 -#define M_MC_DATA_DRIVE _SB_MAKEMASK(4,S_MC_DATA_DRIVE) -#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x,S_MC_DATA_DRIVE) -#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x,S_MC_DATA_DRIVE,M_MC_DATA_DRIVE) +#define M_MC_DATA_DRIVE _SB_MAKEMASK(4, S_MC_DATA_DRIVE) +#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x, S_MC_DATA_DRIVE) +#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE) #define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0) #define S_MC_ADDR_DRIVE 24 -#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4,S_MC_ADDR_DRIVE) -#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x,S_MC_ADDR_DRIVE) -#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE) +#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4, S_MC_ADDR_DRIVE) +#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE) +#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE) #define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) @@ -196,27 +196,27 @@ #define M_MC_DLL_BYPASS _SB_MAKEMASK1(31) #define S_MC_DQI_SKEW 32 -#define M_MC_DQI_SKEW _SB_MAKEMASK(8,S_MC_DQI_SKEW) -#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQI_SKEW) -#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x,S_MC_DQI_SKEW,M_MC_DQI_SKEW) +#define M_MC_DQI_SKEW _SB_MAKEMASK(8, S_MC_DQI_SKEW) +#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQI_SKEW) +#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW) #define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0) #define S_MC_DQO_SKEW 40 -#define M_MC_DQO_SKEW _SB_MAKEMASK(8,S_MC_DQO_SKEW) -#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQO_SKEW) -#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x,S_MC_DQO_SKEW,M_MC_DQO_SKEW) +#define M_MC_DQO_SKEW _SB_MAKEMASK(8, S_MC_DQO_SKEW) +#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQO_SKEW) +#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW) #define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0) #define S_MC_ADDR_SKEW 48 -#define M_MC_ADDR_SKEW _SB_MAKEMASK(8,S_MC_ADDR_SKEW) -#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x,S_MC_ADDR_SKEW) -#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x,S_MC_ADDR_SKEW,M_MC_ADDR_SKEW) +#define M_MC_ADDR_SKEW _SB_MAKEMASK(8, S_MC_ADDR_SKEW) +#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x, S_MC_ADDR_SKEW) +#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW) #define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F) #define S_MC_DLL_DEFAULT 56 -#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8,S_MC_DLL_DEFAULT) -#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_MC_DLL_DEFAULT) -#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_MC_DLL_DEFAULT,M_MC_DLL_DEFAULT) +#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8, S_MC_DLL_DEFAULT) +#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT) +#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT) #define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10) #define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \ @@ -235,9 +235,9 @@ */ #define S_MC_COMMAND 0 -#define M_MC_COMMAND _SB_MAKEMASK(4,S_MC_COMMAND) -#define V_MC_COMMAND(x) _SB_MAKEVALUE(x,S_MC_COMMAND) -#define G_MC_COMMAND(x) _SB_GETVALUE(x,S_MC_COMMAND,M_MC_COMMAND) +#define M_MC_COMMAND _SB_MAKEMASK(4, S_MC_COMMAND) +#define V_MC_COMMAND(x) _SB_MAKEVALUE(x, S_MC_COMMAND) +#define G_MC_COMMAND(x) _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND) #define K_MC_COMMAND_EMRS 0 #define K_MC_COMMAND_MRS 1 @@ -267,21 +267,21 @@ */ #define S_MC_EMODE 0 -#define M_MC_EMODE _SB_MAKEMASK(15,S_MC_EMODE) -#define V_MC_EMODE(x) _SB_MAKEVALUE(x,S_MC_EMODE) -#define G_MC_EMODE(x) _SB_GETVALUE(x,S_MC_EMODE,M_MC_EMODE) +#define M_MC_EMODE _SB_MAKEMASK(15, S_MC_EMODE) +#define V_MC_EMODE(x) _SB_MAKEVALUE(x, S_MC_EMODE) +#define G_MC_EMODE(x) _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE) #define V_MC_EMODE_DEFAULT V_MC_EMODE(0) #define S_MC_MODE 16 -#define M_MC_MODE _SB_MAKEMASK(15,S_MC_MODE) -#define V_MC_MODE(x) _SB_MAKEVALUE(x,S_MC_MODE) -#define G_MC_MODE(x) _SB_GETVALUE(x,S_MC_MODE,M_MC_MODE) +#define M_MC_MODE _SB_MAKEMASK(15, S_MC_MODE) +#define V_MC_MODE(x) _SB_MAKEVALUE(x, S_MC_MODE) +#define G_MC_MODE(x) _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE) #define V_MC_MODE_DEFAULT V_MC_MODE(0x22) #define S_MC_DRAM_TYPE 32 -#define M_MC_DRAM_TYPE _SB_MAKEMASK(3,S_MC_DRAM_TYPE) -#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_MC_DRAM_TYPE) -#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_MC_DRAM_TYPE,M_MC_DRAM_TYPE) +#define M_MC_DRAM_TYPE _SB_MAKEMASK(3, S_MC_DRAM_TYPE) +#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_MC_DRAM_TYPE) +#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE) #define K_MC_DRAM_TYPE_JEDEC 0 #define K_MC_DRAM_TYPE_FCRAM 1 @@ -309,16 +309,16 @@ #define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62) #define S_MC_tFIFO 56 -#define M_MC_tFIFO _SB_MAKEMASK(4,S_MC_tFIFO) -#define V_MC_tFIFO(x) _SB_MAKEVALUE(x,S_MC_tFIFO) -#define G_MC_tFIFO(x) _SB_GETVALUE(x,S_MC_tFIFO,M_MC_tFIFO) +#define M_MC_tFIFO _SB_MAKEMASK(4, S_MC_tFIFO) +#define V_MC_tFIFO(x) _SB_MAKEVALUE(x, S_MC_tFIFO) +#define G_MC_tFIFO(x) _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO) #define K_MC_tFIFO_DEFAULT 1 #define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) #define S_MC_tRFC 52 -#define M_MC_tRFC _SB_MAKEMASK(4,S_MC_tRFC) -#define V_MC_tRFC(x) _SB_MAKEVALUE(x,S_MC_tRFC) -#define G_MC_tRFC(x) _SB_GETVALUE(x,S_MC_tRFC,M_MC_tRFC) +#define M_MC_tRFC _SB_MAKEMASK(4, S_MC_tRFC) +#define V_MC_tRFC(x) _SB_MAKEVALUE(x, S_MC_tRFC) +#define G_MC_tRFC(x) _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC) #define K_MC_tRFC_DEFAULT 12 #define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) @@ -327,44 +327,44 @@ #endif #define S_MC_tCwCr 40 -#define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr) -#define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr) -#define G_MC_tCwCr(x) _SB_GETVALUE(x,S_MC_tCwCr,M_MC_tCwCr) +#define M_MC_tCwCr _SB_MAKEMASK(4, S_MC_tCwCr) +#define V_MC_tCwCr(x) _SB_MAKEVALUE(x, S_MC_tCwCr) +#define G_MC_tCwCr(x) _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr) #define K_MC_tCwCr_DEFAULT 4 #define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT) #define S_MC_tRCr 28 -#define M_MC_tRCr _SB_MAKEMASK(4,S_MC_tRCr) -#define V_MC_tRCr(x) _SB_MAKEVALUE(x,S_MC_tRCr) -#define G_MC_tRCr(x) _SB_GETVALUE(x,S_MC_tRCr,M_MC_tRCr) +#define M_MC_tRCr _SB_MAKEMASK(4, S_MC_tRCr) +#define V_MC_tRCr(x) _SB_MAKEVALUE(x, S_MC_tRCr) +#define G_MC_tRCr(x) _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr) #define K_MC_tRCr_DEFAULT 9 #define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT) #define S_MC_tRCw 24 -#define M_MC_tRCw _SB_MAKEMASK(4,S_MC_tRCw) -#define V_MC_tRCw(x) _SB_MAKEVALUE(x,S_MC_tRCw) -#define G_MC_tRCw(x) _SB_GETVALUE(x,S_MC_tRCw,M_MC_tRCw) +#define M_MC_tRCw _SB_MAKEMASK(4, S_MC_tRCw) +#define V_MC_tRCw(x) _SB_MAKEVALUE(x, S_MC_tRCw) +#define G_MC_tRCw(x) _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw) #define K_MC_tRCw_DEFAULT 10 #define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT) #define S_MC_tRRD 20 -#define M_MC_tRRD _SB_MAKEMASK(4,S_MC_tRRD) -#define V_MC_tRRD(x) _SB_MAKEVALUE(x,S_MC_tRRD) -#define G_MC_tRRD(x) _SB_GETVALUE(x,S_MC_tRRD,M_MC_tRRD) +#define M_MC_tRRD _SB_MAKEMASK(4, S_MC_tRRD) +#define V_MC_tRRD(x) _SB_MAKEVALUE(x, S_MC_tRRD) +#define G_MC_tRRD(x) _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD) #define K_MC_tRRD_DEFAULT 2 #define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT) #define S_MC_tRP 16 -#define M_MC_tRP _SB_MAKEMASK(4,S_MC_tRP) -#define V_MC_tRP(x) _SB_MAKEVALUE(x,S_MC_tRP) -#define G_MC_tRP(x) _SB_GETVALUE(x,S_MC_tRP,M_MC_tRP) +#define M_MC_tRP _SB_MAKEMASK(4, S_MC_tRP) +#define V_MC_tRP(x) _SB_MAKEVALUE(x, S_MC_tRP) +#define G_MC_tRP(x) _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP) #define K_MC_tRP_DEFAULT 4 #define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT) #define S_MC_tCwD 8 -#define M_MC_tCwD _SB_MAKEMASK(4,S_MC_tCwD) -#define V_MC_tCwD(x) _SB_MAKEVALUE(x,S_MC_tCwD) -#define G_MC_tCwD(x) _SB_GETVALUE(x,S_MC_tCwD,M_MC_tCwD) +#define M_MC_tCwD _SB_MAKEMASK(4, S_MC_tCwD) +#define V_MC_tCwD(x) _SB_MAKEVALUE(x, S_MC_tCwD) +#define G_MC_tCwD(x) _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD) #define K_MC_tCwD_DEFAULT 1 #define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT) @@ -372,16 +372,16 @@ #define M_MC_tCrDh M_tCrDh #define S_MC_tCrD 4 -#define M_MC_tCrD _SB_MAKEMASK(3,S_MC_tCrD) -#define V_MC_tCrD(x) _SB_MAKEVALUE(x,S_MC_tCrD) -#define G_MC_tCrD(x) _SB_GETVALUE(x,S_MC_tCrD,M_MC_tCrD) +#define M_MC_tCrD _SB_MAKEMASK(3, S_MC_tCrD) +#define V_MC_tCrD(x) _SB_MAKEVALUE(x, S_MC_tCrD) +#define G_MC_tCrD(x) _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD) #define K_MC_tCrD_DEFAULT 2 #define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT) #define S_MC_tRCD 0 -#define M_MC_tRCD _SB_MAKEMASK(4,S_MC_tRCD) -#define V_MC_tRCD(x) _SB_MAKEVALUE(x,S_MC_tRCD) -#define G_MC_tRCD(x) _SB_GETVALUE(x,S_MC_tRCD,M_MC_tRCD) +#define M_MC_tRCD _SB_MAKEMASK(4, S_MC_tRCD) +#define V_MC_tRCD(x) _SB_MAKEVALUE(x, S_MC_tRCD) +#define G_MC_tRCD(x) _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD) #define K_MC_tRCD_DEFAULT 3 #define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT) @@ -409,76 +409,76 @@ */ #define S_MC_CS0_START 0 -#define M_MC_CS0_START _SB_MAKEMASK(16,S_MC_CS0_START) -#define V_MC_CS0_START(x) _SB_MAKEVALUE(x,S_MC_CS0_START) -#define G_MC_CS0_START(x) _SB_GETVALUE(x,S_MC_CS0_START,M_MC_CS0_START) +#define M_MC_CS0_START _SB_MAKEMASK(16, S_MC_CS0_START) +#define V_MC_CS0_START(x) _SB_MAKEVALUE(x, S_MC_CS0_START) +#define G_MC_CS0_START(x) _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START) #define S_MC_CS1_START 16 -#define M_MC_CS1_START _SB_MAKEMASK(16,S_MC_CS1_START) -#define V_MC_CS1_START(x) _SB_MAKEVALUE(x,S_MC_CS1_START) -#define G_MC_CS1_START(x) _SB_GETVALUE(x,S_MC_CS1_START,M_MC_CS1_START) +#define M_MC_CS1_START _SB_MAKEMASK(16, S_MC_CS1_START) +#define V_MC_CS1_START(x) _SB_MAKEVALUE(x, S_MC_CS1_START) +#define G_MC_CS1_START(x) _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START) #define S_MC_CS2_START 32 -#define M_MC_CS2_START _SB_MAKEMASK(16,S_MC_CS2_START) -#define V_MC_CS2_START(x) _SB_MAKEVALUE(x,S_MC_CS2_START) -#define G_MC_CS2_START(x) _SB_GETVALUE(x,S_MC_CS2_START,M_MC_CS2_START) +#define M_MC_CS2_START _SB_MAKEMASK(16, S_MC_CS2_START) +#define V_MC_CS2_START(x) _SB_MAKEVALUE(x, S_MC_CS2_START) +#define G_MC_CS2_START(x) _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START) #define S_MC_CS3_START 48 -#define M_MC_CS3_START _SB_MAKEMASK(16,S_MC_CS3_START) -#define V_MC_CS3_START(x) _SB_MAKEVALUE(x,S_MC_CS3_START) -#define G_MC_CS3_START(x) _SB_GETVALUE(x,S_MC_CS3_START,M_MC_CS3_START) +#define M_MC_CS3_START _SB_MAKEMASK(16, S_MC_CS3_START) +#define V_MC_CS3_START(x) _SB_MAKEVALUE(x, S_MC_CS3_START) +#define G_MC_CS3_START(x) _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START) /* * Chip Select End Address Register (Table 6-18) */ #define S_MC_CS0_END 0 -#define M_MC_CS0_END _SB_MAKEMASK(16,S_MC_CS0_END) -#define V_MC_CS0_END(x) _SB_MAKEVALUE(x,S_MC_CS0_END) -#define G_MC_CS0_END(x) _SB_GETVALUE(x,S_MC_CS0_END,M_MC_CS0_END) +#define M_MC_CS0_END _SB_MAKEMASK(16, S_MC_CS0_END) +#define V_MC_CS0_END(x) _SB_MAKEVALUE(x, S_MC_CS0_END) +#define G_MC_CS0_END(x) _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END) #define S_MC_CS1_END 16 -#define M_MC_CS1_END _SB_MAKEMASK(16,S_MC_CS1_END) -#define V_MC_CS1_END(x) _SB_MAKEVALUE(x,S_MC_CS1_END) -#define G_MC_CS1_END(x) _SB_GETVALUE(x,S_MC_CS1_END,M_MC_CS1_END) +#define M_MC_CS1_END _SB_MAKEMASK(16, S_MC_CS1_END) +#define V_MC_CS1_END(x) _SB_MAKEVALUE(x, S_MC_CS1_END) +#define G_MC_CS1_END(x) _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END) #define S_MC_CS2_END 32 -#define M_MC_CS2_END _SB_MAKEMASK(16,S_MC_CS2_END) -#define V_MC_CS2_END(x) _SB_MAKEVALUE(x,S_MC_CS2_END) -#define G_MC_CS2_END(x) _SB_GETVALUE(x,S_MC_CS2_END,M_MC_CS2_END) +#define M_MC_CS2_END _SB_MAKEMASK(16, S_MC_CS2_END) +#define V_MC_CS2_END(x) _SB_MAKEVALUE(x, S_MC_CS2_END) +#define G_MC_CS2_END(x) _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END) #define S_MC_CS3_END 48 -#define M_MC_CS3_END _SB_MAKEMASK(16,S_MC_CS3_END) -#define V_MC_CS3_END(x) _SB_MAKEVALUE(x,S_MC_CS3_END) -#define G_MC_CS3_END(x) _SB_GETVALUE(x,S_MC_CS3_END,M_MC_CS3_END) +#define M_MC_CS3_END _SB_MAKEMASK(16, S_MC_CS3_END) +#define V_MC_CS3_END(x) _SB_MAKEVALUE(x, S_MC_CS3_END) +#define G_MC_CS3_END(x) _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END) /* * Chip Select Interleave Register (Table 6-19) */ #define S_MC_INTLV_RESERVED 0 -#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5,S_MC_INTLV_RESERVED) +#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5, S_MC_INTLV_RESERVED) #define S_MC_INTERLEAVE 7 -#define M_MC_INTERLEAVE _SB_MAKEMASK(18,S_MC_INTERLEAVE) -#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x,S_MC_INTERLEAVE) +#define M_MC_INTERLEAVE _SB_MAKEMASK(18, S_MC_INTERLEAVE) +#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x, S_MC_INTERLEAVE) #define S_MC_INTLV_MBZ 25 -#define M_MC_INTLV_MBZ _SB_MAKEMASK(39,S_MC_INTLV_MBZ) +#define M_MC_INTLV_MBZ _SB_MAKEMASK(39, S_MC_INTLV_MBZ) /* * Row Address Bits Register (Table 6-20) */ #define S_MC_RAS_RESERVED 0 -#define M_MC_RAS_RESERVED _SB_MAKEMASK(5,S_MC_RAS_RESERVED) +#define M_MC_RAS_RESERVED _SB_MAKEMASK(5, S_MC_RAS_RESERVED) #define S_MC_RAS_SELECT 12 -#define M_MC_RAS_SELECT _SB_MAKEMASK(25,S_MC_RAS_SELECT) -#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_RAS_SELECT) +#define M_MC_RAS_SELECT _SB_MAKEMASK(25, S_MC_RAS_SELECT) +#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_RAS_SELECT) #define S_MC_RAS_MBZ 37 -#define M_MC_RAS_MBZ _SB_MAKEMASK(27,S_MC_RAS_MBZ) +#define M_MC_RAS_MBZ _SB_MAKEMASK(27, S_MC_RAS_MBZ) /* @@ -486,14 +486,14 @@ */ #define S_MC_CAS_RESERVED 0 -#define M_MC_CAS_RESERVED _SB_MAKEMASK(5,S_MC_CAS_RESERVED) +#define M_MC_CAS_RESERVED _SB_MAKEMASK(5, S_MC_CAS_RESERVED) #define S_MC_CAS_SELECT 5 -#define M_MC_CAS_SELECT _SB_MAKEMASK(18,S_MC_CAS_SELECT) -#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_CAS_SELECT) +#define M_MC_CAS_SELECT _SB_MAKEMASK(18, S_MC_CAS_SELECT) +#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_CAS_SELECT) #define S_MC_CAS_MBZ 23 -#define M_MC_CAS_MBZ _SB_MAKEMASK(41,S_MC_CAS_MBZ) +#define M_MC_CAS_MBZ _SB_MAKEMASK(41, S_MC_CAS_MBZ) /* @@ -501,14 +501,14 @@ */ #define S_MC_BA_RESERVED 0 -#define M_MC_BA_RESERVED _SB_MAKEMASK(5,S_MC_BA_RESERVED) +#define M_MC_BA_RESERVED _SB_MAKEMASK(5, S_MC_BA_RESERVED) #define S_MC_BA_SELECT 5 -#define M_MC_BA_SELECT _SB_MAKEMASK(20,S_MC_BA_SELECT) -#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x,S_MC_BA_SELECT) +#define M_MC_BA_SELECT _SB_MAKEMASK(20, S_MC_BA_SELECT) +#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x, S_MC_BA_SELECT) #define S_MC_BA_MBZ 25 -#define M_MC_BA_MBZ _SB_MAKEMASK(39,S_MC_BA_MBZ) +#define M_MC_BA_MBZ _SB_MAKEMASK(39, S_MC_BA_MBZ) /* * Chip Select Attribute Register (Table 6-23) @@ -520,31 +520,31 @@ #define K_MC_CS_ATTR_OPEN 3 #define S_MC_CS0_PAGE 0 -#define M_MC_CS0_PAGE _SB_MAKEMASK(2,S_MC_CS0_PAGE) -#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS0_PAGE) -#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x,S_MC_CS0_PAGE,M_MC_CS0_PAGE) +#define M_MC_CS0_PAGE _SB_MAKEMASK(2, S_MC_CS0_PAGE) +#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS0_PAGE) +#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE) #define S_MC_CS1_PAGE 16 -#define M_MC_CS1_PAGE _SB_MAKEMASK(2,S_MC_CS1_PAGE) -#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS1_PAGE) -#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x,S_MC_CS1_PAGE,M_MC_CS1_PAGE) +#define M_MC_CS1_PAGE _SB_MAKEMASK(2, S_MC_CS1_PAGE) +#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS1_PAGE) +#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE) #define S_MC_CS2_PAGE 32 -#define M_MC_CS2_PAGE _SB_MAKEMASK(2,S_MC_CS2_PAGE) -#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS2_PAGE) -#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x,S_MC_CS2_PAGE,M_MC_CS2_PAGE) +#define M_MC_CS2_PAGE _SB_MAKEMASK(2, S_MC_CS2_PAGE) +#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS2_PAGE) +#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE) #define S_MC_CS3_PAGE 48 -#define M_MC_CS3_PAGE _SB_MAKEMASK(2,S_MC_CS3_PAGE) -#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS3_PAGE) -#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x,S_MC_CS3_PAGE,M_MC_CS3_PAGE) +#define M_MC_CS3_PAGE _SB_MAKEMASK(2, S_MC_CS3_PAGE) +#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS3_PAGE) +#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE) /* * ECC Test ECC Register (Table 6-25) */ #define S_MC_ECC_INVERT 0 -#define M_MC_ECC_INVERT _SB_MAKEMASK(8,S_MC_ECC_INVERT) +#define M_MC_ECC_INVERT _SB_MAKEMASK(8, S_MC_ECC_INVERT) #endif diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h index 220b7e9..8f53ec8 100644 --- a/include/asm-mips/sibyte/sb1250_regs.h +++ b/include/asm-mips/sibyte/sb1250_regs.h @@ -66,7 +66,7 @@ #define MC_REGISTER_SPACING 0x1000 #define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) -#define A_MC_REGISTER(ctlid,reg) (A_MC_BASE(ctlid)+(reg)) +#define A_MC_REGISTER(ctlid, reg) (A_MC_BASE(ctlid)+(reg)) #define R_MC_CONFIG 0x0000000100 #define R_MC_DRAMCMD 0x0000000120 @@ -173,23 +173,23 @@ #define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ -#define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) \ +#define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) \ ((A_MAC_CHANNEL_BASE(macnum)) + \ R_MAC_DMA_CHANNELS + \ (MAC_DMA_TXRX_SPACING*(txrx)) + \ (MAC_DMA_CHANNEL_SPACING*(chan))) -#define R_MAC_DMA_CHANNEL_BASE(txrx,chan) \ +#define R_MAC_DMA_CHANNEL_BASE(txrx, chan) \ (R_MAC_DMA_CHANNELS + \ (MAC_DMA_TXRX_SPACING*(txrx)) + \ (MAC_DMA_CHANNEL_SPACING*(chan))) -#define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg) \ - (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) + \ +#define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg) \ + (A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) + \ (reg)) -#define R_MAC_DMA_REGISTER(txrx,chan,reg) \ - (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ +#define R_MAC_DMA_REGISTER(txrx, chan, reg) \ + (R_MAC_DMA_CHANNEL_BASE(txrx, chan) + \ (reg)) /* @@ -415,8 +415,8 @@ R_SER_DMA_CHANNELS + \ (SER_DMA_TXRX_SPACING*(txrx))) -#define A_SER_DMA_REGISTER(sernum,txrx,reg) \ - (A_SER_DMA_CHANNEL_BASE(sernum,txrx) + \ +#define A_SER_DMA_REGISTER(sernum, txrx, reg) \ + (A_SER_DMA_CHANNEL_BASE(sernum, txrx) + \ (reg)) @@ -499,7 +499,7 @@ #define IO_EXT_REGISTER_SPACING 8 #define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) -#define R_IO_EXT_REG(reg,cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) +#define R_IO_EXT_REG(reg, cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) #define R_IO_EXT_CFG 0x0000 #define R_IO_EXT_MULT_SIZE 0x0100 @@ -587,7 +587,7 @@ #define A_SMB_1 0x0010060008 #define SMB_REGISTER_SPACING 0x8 #define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) -#define A_SMB_REGISTER(idx,reg) (A_SMB_BASE(idx)+(reg)) +#define A_SMB_REGISTER(idx, reg) (A_SMB_BASE(idx)+(reg)) #define R_SMB_XTRA 0x0000000000 #define R_SMB_FREQ 0x0000000010 @@ -611,7 +611,7 @@ #define SCD_WDOG_SPACING 0x100 #define SCD_NUM_WDOGS 2 #define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) -#define A_SCD_WDOG_REGISTER(w,r) (A_SCD_WDOG_BASE(w) + (r)) +#define A_SCD_WDOG_REGISTER(w, r) (A_SCD_WDOG_BASE(w) + (r)) #define R_SCD_WDOG_INIT 0x0000000000 #define R_SCD_WDOG_CNT 0x0000000008 @@ -635,7 +635,7 @@ #define A_SCD_TIMER_3 0x0010020178 #define SCD_NUM_TIMERS 4 #define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) -#define A_SCD_TIMER_REGISTER(w,r) (A_SCD_TIMER_BASE(w) + (r)) +#define A_SCD_TIMER_REGISTER(w, r) (A_SCD_TIMER_BASE(w) + (r)) #define R_SCD_TIMER_INIT 0x0000000000 #define R_SCD_TIMER_CNT 0x0000000010 @@ -714,7 +714,7 @@ #define IMR_REGISTER_SPACING_SHIFT 13 #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) -#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg)) +#define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg)) #define R_IMR_INTERRUPT_DIAG 0x0010 #define R_IMR_INTERRUPT_LDT 0x0018 @@ -821,7 +821,7 @@ #define DM_REGISTER_SPACING 0x20 #define DM_NUM_CHANNELS 4 #define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) -#define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg)) +#define A_DM_REGISTER(idx, reg) (A_DM_BASE(idx) + (reg)) #define R_DM_DSCR_BASE 0x0000000000 #define R_DM_DSCR_COUNT 0x0000000008 @@ -843,7 +843,7 @@ #define DM_CRC_REGISTER_SPACING 0x10 #define DM_CRC_NUM_CHANNELS 2 #define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING)) -#define A_DM_CRC_REGISTER(idx,reg) (A_DM_CRC_BASE(idx) + (reg)) +#define A_DM_CRC_REGISTER(idx, reg) (A_DM_CRC_BASE(idx) + (reg)) #define R_CRC_DEF_0 0x00 #define R_CTCP_DEF_0 0x08 diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h index 9ea3da3..e49c3e8 100644 --- a/include/asm-mips/sibyte/sb1250_scd.h +++ b/include/asm-mips/sibyte/sb1250_scd.h @@ -42,12 +42,12 @@ * System Revision Register (Table 4-1) */ -#define M_SYS_RESERVED _SB_MAKEMASK(8,0) +#define M_SYS_RESERVED _SB_MAKEMASK(8, 0) #define S_SYS_REVISION _SB_MAKE64(8) -#define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION) -#define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) -#define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) +#define M_SYS_REVISION _SB_MAKEMASK(8, S_SYS_REVISION) +#define V_SYS_REVISION(x) _SB_MAKEVALUE(x, S_SYS_REVISION) +#define G_SYS_REVISION(x) _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION) #define K_SYS_REVISION_BCM1250_PASS1 0x01 @@ -94,9 +94,9 @@ /*Cache size - 23:20 of revision register*/ #define S_SYS_L2C_SIZE _SB_MAKE64(20) -#define M_SYS_L2C_SIZE _SB_MAKEMASK(4,S_SYS_L2C_SIZE) -#define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x,S_SYS_L2C_SIZE) -#define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x,S_SYS_L2C_SIZE,M_SYS_L2C_SIZE) +#define M_SYS_L2C_SIZE _SB_MAKEMASK(4, S_SYS_L2C_SIZE) +#define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x, S_SYS_L2C_SIZE) +#define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE) #define K_SYS_L2C_SIZE_1MB 0 #define K_SYS_L2C_SIZE_512KB 5 @@ -110,16 +110,16 @@ /* Number of CPU cores, bits 27:24 of revision register*/ #define S_SYS_NUM_CPUS _SB_MAKE64(24) -#define M_SYS_NUM_CPUS _SB_MAKEMASK(4,S_SYS_NUM_CPUS) -#define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x,S_SYS_NUM_CPUS) -#define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x,S_SYS_NUM_CPUS,M_SYS_NUM_CPUS) +#define M_SYS_NUM_CPUS _SB_MAKEMASK(4, S_SYS_NUM_CPUS) +#define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x, S_SYS_NUM_CPUS) +#define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS) /* XXX: discourage people from using these constants. */ #define S_SYS_PART _SB_MAKE64(16) -#define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART) -#define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART) -#define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART) +#define M_SYS_PART _SB_MAKEMASK(16, S_SYS_PART) +#define V_SYS_PART(x) _SB_MAKEVALUE(x, S_SYS_PART) +#define G_SYS_PART(x) _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART) /* XXX: discourage people from using these constants. */ #define K_SYS_PART_SB1250 0x1250 @@ -131,9 +131,9 @@ /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ #define S_SYS_SOC_TYPE _SB_MAKE64(16) -#define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE) -#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE) -#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE) +#define M_SYS_SOC_TYPE _SB_MAKEMASK(4, S_SYS_SOC_TYPE) +#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x, S_SYS_SOC_TYPE) +#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE) #define K_SYS_SOC_TYPE_BCM1250 0x0 #define K_SYS_SOC_TYPE_BCM1120 0x1 @@ -170,9 +170,9 @@ #endif #define S_SYS_WID _SB_MAKE64(32) -#define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID) -#define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) -#define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) +#define M_SYS_WID _SB_MAKEMASK(32, S_SYS_WID) +#define V_SYS_WID(x) _SB_MAKEVALUE(x, S_SYS_WID) +#define G_SYS_WID(x) _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID) /* * System Manufacturing Register @@ -182,36 +182,36 @@ #if SIBYTE_HDR_FEATURE_1250_112x /* Wafer ID: bits 31:0 */ #define S_SYS_WAFERID1_200 _SB_MAKE64(0) -#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) -#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200) -#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) +#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32, S_SYS_WAFERID1_200) +#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID1_200) +#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200) #define S_SYS_BIN _SB_MAKE64(32) -#define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) -#define V_SYS_BIN(x) _SB_MAKEVALUE(x,S_SYS_BIN) -#define G_SYS_BIN(x) _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) +#define M_SYS_BIN _SB_MAKEMASK(4, S_SYS_BIN) +#define V_SYS_BIN(x) _SB_MAKEVALUE(x, S_SYS_BIN) +#define G_SYS_BIN(x) _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN) /* Wafer ID: bits 39:36 */ #define S_SYS_WAFERID2_200 _SB_MAKE64(36) -#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200) -#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200) -#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) +#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4, S_SYS_WAFERID2_200) +#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID2_200) +#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200) /* Wafer ID: bits 39:0 */ #define S_SYS_WAFERID_300 _SB_MAKE64(0) -#define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300) -#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300) -#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) +#define M_SYS_WAFERID_300 _SB_MAKEMASK(40, S_SYS_WAFERID_300) +#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x, S_SYS_WAFERID_300) +#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300) #define S_SYS_XPOS _SB_MAKE64(40) -#define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS) -#define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS) -#define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) +#define M_SYS_XPOS _SB_MAKEMASK(6, S_SYS_XPOS) +#define V_SYS_XPOS(x) _SB_MAKEVALUE(x, S_SYS_XPOS) +#define G_SYS_XPOS(x) _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS) #define S_SYS_YPOS _SB_MAKE64(46) -#define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) -#define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) -#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) +#define M_SYS_YPOS _SB_MAKEMASK(6, S_SYS_YPOS) +#define V_SYS_YPOS(x) _SB_MAKEVALUE(x, S_SYS_YPOS) +#define G_SYS_YPOS(x) _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS) #endif @@ -227,9 +227,9 @@ #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) #define S_SYS_PLL_DIV _SB_MAKE64(7) -#define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV) -#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV) -#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV) +#define M_SYS_PLL_DIV _SB_MAKEMASK(5, S_SYS_PLL_DIV) +#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_SYS_PLL_DIV) +#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV) #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) @@ -238,9 +238,9 @@ #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) #define S_SYS_BOOT_MODE _SB_MAKE64(17) -#define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE) -#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE) -#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE) +#define M_SYS_BOOT_MODE _SB_MAKEMASK(2, S_SYS_BOOT_MODE) +#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_SYS_BOOT_MODE) +#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE) #define K_SYS_BOOT_MODE_ROM32 0 #define K_SYS_BOOT_MODE_ROM8 1 #define K_SYS_BOOT_MODE_SMBUS_SMALL 2 @@ -255,9 +255,9 @@ #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) #define S_SYS_CONFIG 26 -#define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG) -#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG) -#define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG) +#define M_SYS_CONFIG _SB_MAKEMASK(6, S_SYS_CONFIG) +#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_SYS_CONFIG) +#define G_SYS_CONFIG(x) _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG) /* The following bits are writeable by JTAG only. */ @@ -265,20 +265,20 @@ #define M_SYS_CLKSTEP _SB_MAKEMASK1(33) #define S_SYS_CLKCOUNT 34 -#define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT) -#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT) -#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT) +#define M_SYS_CLKCOUNT _SB_MAKEMASK(8, S_SYS_CLKCOUNT) +#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x, S_SYS_CLKCOUNT) +#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT) #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) #define S_SYS_PLL_IREF 43 -#define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF) +#define M_SYS_PLL_IREF _SB_MAKEMASK(2, S_SYS_PLL_IREF) #define S_SYS_PLL_VCO 45 -#define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO) +#define M_SYS_PLL_VCO _SB_MAKEMASK(2, S_SYS_PLL_VCO) #define S_SYS_PLL_VREG 47 -#define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG) +#define M_SYS_PLL_VREG _SB_MAKEMASK(2, S_SYS_PLL_VREG) #define M_SYS_MEM_RESET _SB_MAKEMASK1(49) #define M_SYS_L2C_RESET _SB_MAKEMASK1(50) @@ -314,13 +314,13 @@ */ #define S_MBOX_INT_3 0 -#define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3) +#define M_MBOX_INT_3 _SB_MAKEMASK(16, S_MBOX_INT_3) #define S_MBOX_INT_2 16 -#define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2) +#define M_MBOX_INT_2 _SB_MAKEMASK(16, S_MBOX_INT_2) #define S_MBOX_INT_1 32 -#define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1) +#define M_MBOX_INT_1 _SB_MAKEMASK(16, S_MBOX_INT_1) #define S_MBOX_INT_0 48 -#define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0) +#define M_MBOX_INT_0 _SB_MAKEMASK(16, S_MBOX_INT_0) /* * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) @@ -330,18 +330,18 @@ #define V_SCD_WDOG_FREQ 1000000 #define S_SCD_WDOG_INIT 0 -#define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT) +#define M_SCD_WDOG_INIT _SB_MAKEMASK(23, S_SCD_WDOG_INIT) #define S_SCD_WDOG_CNT 0 -#define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT) +#define M_SCD_WDOG_CNT _SB_MAKEMASK(23, S_SCD_WDOG_CNT) #define S_SCD_WDOG_ENABLE 0 #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE) #define S_SCD_WDOG_RESET_TYPE 2 -#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3,S_SCD_WDOG_RESET_TYPE) -#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_SCD_WDOG_RESET_TYPE) -#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_SCD_WDOG_RESET_TYPE,M_SCD_WDOG_RESET_TYPE) +#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE) +#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE) +#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE) #define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ #define K_SCD_WDOG_RESET_SOFT 1 @@ -363,15 +363,15 @@ #define V_SCD_TIMER_FREQ 1000000 #define S_SCD_TIMER_INIT 0 -#define M_SCD_TIMER_INIT _SB_MAKEMASK(23,S_SCD_TIMER_INIT) -#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) -#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) +#define M_SCD_TIMER_INIT _SB_MAKEMASK(23, S_SCD_TIMER_INIT) +#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_INIT) +#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT) #define V_SCD_TIMER_WIDTH 23 #define S_SCD_TIMER_CNT 0 -#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT) -#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) -#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) +#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT) +#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_CNT) +#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT) #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) @@ -382,24 +382,24 @@ */ #define S_SPC_CFG_SRC0 0 -#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) -#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) -#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0) +#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8, S_SPC_CFG_SRC0) +#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC0) +#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0) #define S_SPC_CFG_SRC1 8 -#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1) -#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1) -#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1) +#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8, S_SPC_CFG_SRC1) +#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC1) +#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1) #define S_SPC_CFG_SRC2 16 -#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2) -#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2) -#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2) +#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8, S_SPC_CFG_SRC2) +#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC2) +#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2) #define S_SPC_CFG_SRC3 24 -#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3) -#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) -#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) +#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8, S_SPC_CFG_SRC3) +#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC3) +#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3) #if SIBYTE_HDR_FEATURE_1250_112x #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) @@ -412,57 +412,57 @@ */ #define S_SCD_BERR_TID 8 -#define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID) -#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID) -#define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID) +#define M_SCD_BERR_TID _SB_MAKEMASK(10, S_SCD_BERR_TID) +#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x, S_SCD_BERR_TID) +#define G_SCD_BERR_TID(x) _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID) #define S_SCD_BERR_RID 18 -#define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID) -#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID) -#define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID) +#define M_SCD_BERR_RID _SB_MAKEMASK(4, S_SCD_BERR_RID) +#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x, S_SCD_BERR_RID) +#define G_SCD_BERR_RID(x) _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID) #define S_SCD_BERR_DCODE 22 -#define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE) -#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE) -#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE) +#define M_SCD_BERR_DCODE _SB_MAKEMASK(3, S_SCD_BERR_DCODE) +#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x, S_SCD_BERR_DCODE) +#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE) #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) #define S_SCD_L2ECC_CORR_D 0 -#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D) -#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D) -#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D) +#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D) +#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D) +#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D) #define S_SCD_L2ECC_BAD_D 8 -#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D) -#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D) -#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D) +#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D) +#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D) +#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D) #define S_SCD_L2ECC_CORR_T 16 -#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T) -#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T) -#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T) +#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T) +#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T) +#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T) #define S_SCD_L2ECC_BAD_T 24 -#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T) -#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T) -#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T) +#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T) +#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T) +#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T) #define S_SCD_MEM_ECC_CORR 0 -#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR) -#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR) -#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR) +#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR) +#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR) +#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR) #define S_SCD_MEM_ECC_BAD 8 -#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD) -#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD) -#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD) +#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD) +#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD) +#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD) #define S_SCD_MEM_BUSERR 16 -#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR) -#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR) -#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR) +#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8, S_SCD_MEM_BUSERR) +#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR) +#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR) /* @@ -470,13 +470,13 @@ */ #if SIBYTE_HDR_FEATURE_1250_112x -#define M_ATRAP_INDEX _SB_MAKEMASK(4,0) -#define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) +#define M_ATRAP_INDEX _SB_MAKEMASK(4, 0) +#define M_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) #define S_ATRAP_CFG_CNT 0 -#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT) -#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT) -#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT) +#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_ATRAP_CFG_CNT) +#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT) +#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT) #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) @@ -485,9 +485,9 @@ #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) #define S_ATRAP_CFG_AGENTID 8 -#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID) -#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID) -#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID) +#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID) +#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID) +#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID) #define K_BUS_AGENT_CPU0 0 #define K_BUS_AGENT_CPU1 1 @@ -498,9 +498,9 @@ #define K_BUS_AGENT_MC 7 #define S_ATRAP_CFG_CATTR 12 -#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR) -#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR) -#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR) +#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3, S_ATRAP_CFG_CATTR) +#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CATTR) +#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_ATRAP_CFG_CATTR, M_ATRAP_CFG_CATTR) #define K_ATRAP_CFG_CATTR_IGNORE 0 #define K_ATRAP_CFG_CATTR_UNC 1 @@ -541,18 +541,18 @@ #endif /* 1480 */ #endif /* 1250/112x */ -#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) -#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) -#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) +#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR) +#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR) +#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR) /* * Trace Event registers */ #define S_SCD_TREVT_ADDR_MATCH 0 -#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH) -#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH) -#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH) +#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH) +#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH) +#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH) #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) @@ -563,48 +563,48 @@ #define M_SCD_TREVT_READ _SB_MAKEMASK1(11) #define S_SCD_TREVT_REQID 12 -#define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID) -#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID) -#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID) +#define M_SCD_TREVT_REQID _SB_MAKEMASK(4, S_SCD_TREVT_REQID) +#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_REQID) +#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID) #define S_SCD_TREVT_RESPID 16 -#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID) -#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID) -#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID) +#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4, S_SCD_TREVT_RESPID) +#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_RESPID) +#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID) #define S_SCD_TREVT_DATAID 20 -#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID) -#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID) -#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID) +#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4, S_SCD_TREVT_DATAID) +#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_DATAID) +#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID) #define S_SCD_TREVT_COUNT 24 -#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT) -#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT) -#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT) +#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8, S_SCD_TREVT_COUNT) +#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x, S_SCD_TREVT_COUNT) +#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT) /* * Trace Sequence registers */ #define S_SCD_TRSEQ_EVENT4 0 -#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4) -#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4) -#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4) +#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4) +#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4) +#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4) #define S_SCD_TRSEQ_EVENT3 4 -#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3) -#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3) -#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3) +#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3) +#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3) +#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3) #define S_SCD_TRSEQ_EVENT2 8 -#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2) -#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2) -#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2) +#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2) +#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2) +#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2) #define S_SCD_TRSEQ_EVENT1 12 -#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1) -#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1) -#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1) +#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1) +#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1) +#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1) #define K_SCD_TRSEQ_E0 0 #define K_SCD_TRSEQ_E1 1 @@ -629,9 +629,9 @@ V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) #define S_SCD_TRSEQ_FUNCTION 16 -#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION) -#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION) -#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION) +#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION) +#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION) +#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION) #define K_SCD_TRSEQ_FUNC_NOP 0 #define K_SCD_TRSEQ_FUNC_START 1 diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h index 279a912..0476992 100644 --- a/include/asm-mips/sibyte/sb1250_smbus.h +++ b/include/asm-mips/sibyte/sb1250_smbus.h @@ -41,16 +41,16 @@ */ #define S_SMB_FREQ_DIV 0 -#define M_SMB_FREQ_DIV _SB_MAKEMASK(13,S_SMB_FREQ_DIV) -#define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x,S_SMB_FREQ_DIV) +#define M_SMB_FREQ_DIV _SB_MAKEMASK(13, S_SMB_FREQ_DIV) +#define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x, S_SMB_FREQ_DIV) #define K_SMB_FREQ_400KHZ 0x1F #define K_SMB_FREQ_100KHZ 0x7D #define K_SMB_FREQ_10KHZ 1250 #define S_SMB_CMD 0 -#define M_SMB_CMD _SB_MAKEMASK(8,S_SMB_CMD) -#define V_SMB_CMD(x) _SB_MAKEVALUE(x,S_SMB_CMD) +#define M_SMB_CMD _SB_MAKEMASK(8, S_SMB_CMD) +#define V_SMB_CMD(x) _SB_MAKEVALUE(x, S_SMB_CMD) /* * SMBus control register (Table 14-4) @@ -61,7 +61,7 @@ #define S_SMB_DATA_OUT 4 #define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT) -#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x,S_SMB_DATA_OUT) +#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x, S_SMB_DATA_OUT) #define M_SMB_DATA_DIR _SB_MAKEMASK1(5) #define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR @@ -79,35 +79,35 @@ #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_SMB_SCL_IN 5 #define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN) -#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x,S_SMB_SCL_IN) -#define G_SMB_SCL_IN(x) _SB_GETVALUE(x,S_SMB_SCL_IN,M_SMB_SCL_IN) +#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x, S_SMB_SCL_IN) +#define G_SMB_SCL_IN(x) _SB_GETVALUE(x, S_SMB_SCL_IN, M_SMB_SCL_IN) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_SMB_REF 6 #define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF) -#define V_SMB_REF(x) _SB_MAKEVALUE(x,S_SMB_REF) -#define G_SMB_REF(x) _SB_GETVALUE(x,S_SMB_REF,M_SMB_REF) +#define V_SMB_REF(x) _SB_MAKEVALUE(x, S_SMB_REF) +#define G_SMB_REF(x) _SB_GETVALUE(x, S_SMB_REF, M_SMB_REF) #define S_SMB_DATA_IN 7 #define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN) -#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x,S_SMB_DATA_IN) -#define G_SMB_DATA_IN(x) _SB_GETVALUE(x,S_SMB_DATA_IN,M_SMB_DATA_IN) +#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x, S_SMB_DATA_IN) +#define G_SMB_DATA_IN(x) _SB_GETVALUE(x, S_SMB_DATA_IN, M_SMB_DATA_IN) /* * SMBus Start/Command registers (Table 14-9) */ #define S_SMB_ADDR 0 -#define M_SMB_ADDR _SB_MAKEMASK(7,S_SMB_ADDR) -#define V_SMB_ADDR(x) _SB_MAKEVALUE(x,S_SMB_ADDR) -#define G_SMB_ADDR(x) _SB_GETVALUE(x,S_SMB_ADDR,M_SMB_ADDR) +#define M_SMB_ADDR _SB_MAKEMASK(7, S_SMB_ADDR) +#define V_SMB_ADDR(x) _SB_MAKEVALUE(x, S_SMB_ADDR) +#define G_SMB_ADDR(x) _SB_GETVALUE(x, S_SMB_ADDR, M_SMB_ADDR) #define M_SMB_QDATA _SB_MAKEMASK1(7) #define S_SMB_TT 8 -#define M_SMB_TT _SB_MAKEMASK(3,S_SMB_TT) -#define V_SMB_TT(x) _SB_MAKEVALUE(x,S_SMB_TT) -#define G_SMB_TT(x) _SB_GETVALUE(x,S_SMB_TT,M_SMB_TT) +#define M_SMB_TT _SB_MAKEMASK(3, S_SMB_TT) +#define V_SMB_TT(x) _SB_MAKEVALUE(x, S_SMB_TT) +#define G_SMB_TT(x) _SB_GETVALUE(x, S_SMB_TT, M_SMB_TT) #define K_SMB_TT_WR1BYTE 0 #define K_SMB_TT_WR2BYTE 1 @@ -134,12 +134,12 @@ */ #define S_SMB_LB 0 -#define M_SMB_LB _SB_MAKEMASK(8,S_SMB_LB) -#define V_SMB_LB(x) _SB_MAKEVALUE(x,S_SMB_LB) +#define M_SMB_LB _SB_MAKEMASK(8, S_SMB_LB) +#define V_SMB_LB(x) _SB_MAKEVALUE(x, S_SMB_LB) #define S_SMB_MB 8 -#define M_SMB_MB _SB_MAKEMASK(8,S_SMB_MB) -#define V_SMB_MB(x) _SB_MAKEVALUE(x,S_SMB_MB) +#define M_SMB_MB _SB_MAKEMASK(8, S_SMB_MB) +#define V_SMB_MB(x) _SB_MAKEVALUE(x, S_SMB_MB) /* @@ -147,22 +147,22 @@ */ #define S_SPEC_PEC 0 -#define M_SPEC_PEC _SB_MAKEMASK(8,S_SPEC_PEC) -#define V_SPEC_MB(x) _SB_MAKEVALUE(x,S_SPEC_PEC) +#define M_SPEC_PEC _SB_MAKEMASK(8, S_SPEC_PEC) +#define V_SPEC_MB(x) _SB_MAKEVALUE(x, S_SPEC_PEC) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_SMB_CMDH 8 -#define M_SMB_CMDH _SB_MAKEMASK(8,S_SMB_CMDH) -#define V_SMB_CMDH(x) _SB_MAKEVALUE(x,S_SMB_CMDH) +#define M_SMB_CMDH _SB_MAKEMASK(8, S_SMB_CMDH) +#define V_SMB_CMDH(x) _SB_MAKEVALUE(x, S_SMB_CMDH) #define M_SMB_EXTEND _SB_MAKEMASK1(14) #define S_SMB_DFMT 8 -#define M_SMB_DFMT _SB_MAKEMASK(3,S_SMB_DFMT) -#define V_SMB_DFMT(x) _SB_MAKEVALUE(x,S_SMB_DFMT) -#define G_SMB_DFMT(x) _SB_GETVALUE(x,S_SMB_DFMT,M_SMB_DFMT) +#define M_SMB_DFMT _SB_MAKEMASK(3, S_SMB_DFMT) +#define V_SMB_DFMT(x) _SB_MAKEVALUE(x, S_SMB_DFMT) +#define G_SMB_DFMT(x) _SB_GETVALUE(x, S_SMB_DFMT, M_SMB_DFMT) #define K_SMB_DFMT_1BYTE 0 #define K_SMB_DFMT_2BYTE 1 @@ -183,9 +183,9 @@ #define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED) #define S_SMB_AFMT 11 -#define M_SMB_AFMT _SB_MAKEMASK(2,S_SMB_AFMT) -#define V_SMB_AFMT(x) _SB_MAKEVALUE(x,S_SMB_AFMT) -#define G_SMB_AFMT(x) _SB_GETVALUE(x,S_SMB_AFMT,M_SMB_AFMT) +#define M_SMB_AFMT _SB_MAKEMASK(2, S_SMB_AFMT) +#define V_SMB_AFMT(x) _SB_MAKEVALUE(x, S_SMB_AFMT) +#define G_SMB_AFMT(x) _SB_GETVALUE(x, S_SMB_AFMT, M_SMB_AFMT) #define K_SMB_AFMT_NONE 0 #define K_SMB_AFMT_ADDR 1 diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h index dd154ac..d4b8558 100644 --- a/include/asm-mips/sibyte/sb1250_syncser.h +++ b/include/asm-mips/sibyte/sb1250_syncser.h @@ -43,8 +43,8 @@ #define M_SYNCSER_MSB_FIRST _SB_MAKEMASK1(1) #define S_SYNCSER_FLAG_NUM 2 -#define M_SYNCSER_FLAG_NUM _SB_MAKEMASK(4,S_SYNCSER_FLAG_NUM) -#define V_SYNCSER_FLAG_NUM _SB_MAKEVALUE(x,S_SYNCSER_FLAG_NUM) +#define M_SYNCSER_FLAG_NUM _SB_MAKEMASK(4, S_SYNCSER_FLAG_NUM) +#define V_SYNCSER_FLAG_NUM _SB_MAKEVALUE(x, S_SYNCSER_FLAG_NUM) #define M_SYNCSER_FLAG_EN _SB_MAKEMASK1(6) #define M_SYNCSER_HDLC_EN _SB_MAKEMASK1(7) @@ -59,8 +59,8 @@ #define M_SYNCSER_RXCLK_EXT _SB_MAKEMASK1(1) #define S_SYNCSER_RXSYNC_DLY 2 -#define M_SYNCSER_RXSYNC_DLY _SB_MAKEMASK(2,S_SYNCSER_RXSYNC_DLY) -#define V_SYNCSER_RXSYNC_DLY(x) _SB_MAKEVALUE(x,S_SYNCSER_RXSYNC_DLY) +#define M_SYNCSER_RXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_RXSYNC_DLY) +#define V_SYNCSER_RXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_RXSYNC_DLY) #define M_SYNCSER_RXSYNC_LOW _SB_MAKEMASK1(4) #define M_SYNCSER_RXSTRB_LOW _SB_MAKEMASK1(5) @@ -72,8 +72,8 @@ #define M_SYNCSER_TXCLK_EXT _SB_MAKEMASK1(9) #define S_SYNCSER_TXSYNC_DLY 10 -#define M_SYNCSER_TXSYNC_DLY _SB_MAKEMASK(2,S_SYNCSER_TXSYNC_DLY) -#define V_SYNCSER_TXSYNC_DLY(x) _SB_MAKEVALUE(x,S_SYNCSER_TXSYNC_DLY) +#define M_SYNCSER_TXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_TXSYNC_DLY) +#define V_SYNCSER_TXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_TXSYNC_DLY) #define M_SYNCSER_TXSYNC_LOW _SB_MAKEMASK1(12) #define M_SYNCSER_TXSTRB_LOW _SB_MAKEMASK1(13) @@ -137,8 +137,8 @@ #define M_SYNCSER_SEQ_BYTE _SB_MAKEMASK1(1) #define S_SYNCSER_SEQ_COUNT 2 -#define M_SYNCSER_SEQ_COUNT _SB_MAKEMASK(4,S_SYNCSER_SEQ_COUNT) -#define V_SYNCSER_SEQ_COUNT(x) _SB_MAKEVALUE(x,S_SYNCSER_SEQ_COUNT) +#define M_SYNCSER_SEQ_COUNT _SB_MAKEMASK(4, S_SYNCSER_SEQ_COUNT) +#define V_SYNCSER_SEQ_COUNT(x) _SB_MAKEVALUE(x, S_SYNCSER_SEQ_COUNT) #define M_SYNCSER_SEQ_ENABLE _SB_MAKEMASK1(6) #define M_SYNCSER_SEQ_STROBE _SB_MAKEMASK1(7) diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h index cf74fed..d835bf2 100644 --- a/include/asm-mips/sibyte/sb1250_uart.h +++ b/include/asm-mips/sibyte/sb1250_uart.h @@ -46,8 +46,8 @@ */ #define S_DUART_BITS_PER_CHAR 0 -#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2,S_DUART_BITS_PER_CHAR) -#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x,S_DUART_BITS_PER_CHAR) +#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR) +#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR) #define K_DUART_BITS_PER_CHAR_RSV0 0 #define K_DUART_BITS_PER_CHAR_RSV1 1 @@ -64,8 +64,8 @@ #define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) #define S_DUART_PARITY_MODE 3 -#define M_DUART_PARITY_MODE _SB_MAKEMASK(2,S_DUART_PARITY_MODE) -#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x,S_DUART_PARITY_MODE) +#define M_DUART_PARITY_MODE _SB_MAKEMASK(2, S_DUART_PARITY_MODE) +#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x, S_DUART_PARITY_MODE) #define K_DUART_PARITY_MODE_ADD 0 #define K_DUART_PARITY_MODE_ADD_FIXED 1 @@ -89,7 +89,7 @@ * Register: DUART_MODE_REG_2_B */ -#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3,0) /* ignored */ +#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3, 0) /* ignored */ #define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) #define M_DUART_STOP_BIT_LEN_1 0 @@ -100,8 +100,8 @@ #define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ #define S_DUART_CHAN_MODE 6 -#define M_DUART_CHAN_MODE _SB_MAKEMASK(2,S_DUART_CHAN_MODE) -#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x,S_DUART_CHAN_MODE) +#define M_DUART_CHAN_MODE _SB_MAKEMASK(2, S_DUART_CHAN_MODE) +#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x, S_DUART_CHAN_MODE) #define K_DUART_CHAN_MODE_NORMAL 0 #define K_DUART_CHAN_MODE_LCL_LOOP 2 @@ -123,8 +123,8 @@ #define M_DUART_TX_DIS _SB_MAKEMASK1(3) #define S_DUART_MISC_CMD 4 -#define M_DUART_MISC_CMD _SB_MAKEMASK(3,S_DUART_MISC_CMD) -#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x,S_DUART_MISC_CMD) +#define M_DUART_MISC_CMD _SB_MAKEMASK(3, S_DUART_MISC_CMD) +#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x, S_DUART_MISC_CMD) #define K_DUART_MISC_CMD_NOACTION0 0 #define K_DUART_MISC_CMD_NOACTION1 1 @@ -168,7 +168,7 @@ * Register: DUART_CLK_SEL_B */ -#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12,0) +#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12, 0) #define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) /* @@ -179,8 +179,8 @@ * Register: DUART_TX_HOLD_B */ -#define M_DUART_RX_DATA _SB_MAKEMASK(8,0) -#define M_DUART_TX_DATA _SB_MAKEMASK(8,0) +#define M_DUART_RX_DATA _SB_MAKEMASK(8, 0) +#define M_DUART_TX_DATA _SB_MAKEMASK(8, 0) /* * DUART Input Port Register (Table 10-10) @@ -202,10 +202,10 @@ */ #define S_DUART_IN_PIN_VAL 0 -#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4,S_DUART_IN_PIN_VAL) +#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL) #define S_DUART_IN_PIN_CHNG 4 -#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4,S_DUART_IN_PIN_CHNG) +#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG) /* @@ -217,7 +217,7 @@ #define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) #define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ #define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) -#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4,4) /* must be zero */ +#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4, 4) /* must be zero */ /* * DUART Aux Control Register (Table 10-15) @@ -228,7 +228,7 @@ #define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) #define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) #define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) -#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4, 4) #define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) #define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) @@ -242,18 +242,18 @@ #define S_DUART_ISR_RX_A 1 #define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A) -#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x,S_DUART_ISR_RX_A) -#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x,S_DUART_ISR_RX_A,M_DUART_ISR_RX_A) +#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x, S_DUART_ISR_RX_A) +#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A) #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) -#define M_DUART_ISR_ALL_A _SB_MAKEMASK(4,0) +#define M_DUART_ISR_ALL_A _SB_MAKEMASK(4, 0) #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) #define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) #define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) #define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) -#define M_DUART_ISR_ALL_B _SB_MAKEMASK(4,4) +#define M_DUART_ISR_ALL_B _SB_MAKEMASK(4, 4) /* * DUART Channel A Interrupt Status Register (Table 10-17) @@ -266,8 +266,8 @@ #define M_DUART_ISR_RX _SB_MAKEMASK1(1) #define M_DUART_ISR_BRK _SB_MAKEMASK1(2) #define M_DUART_ISR_IN _SB_MAKEMASK1(3) -#define M_DUART_ISR_ALL _SB_MAKEMASK(4,0) -#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_ISR_ALL _SB_MAKEMASK(4, 0) +#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4, 4) /* * DUART Interrupt Mask Register (Table 10-19) @@ -278,13 +278,13 @@ #define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) #define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) #define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) -#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4,0) +#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4, 0) #define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) #define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) #define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) #define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) -#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4,4) +#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4, 4) /* * DUART Channel A Interrupt Mask Register (Table 10-20) @@ -297,8 +297,8 @@ #define M_DUART_IMR_RX _SB_MAKEMASK1(1) #define M_DUART_IMR_BRK _SB_MAKEMASK1(2) #define M_DUART_IMR_IN _SB_MAKEMASK1(3) -#define M_DUART_IMR_ALL _SB_MAKEMASK(4,0) -#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_IMR_ALL _SB_MAKEMASK(4, 0) +#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4, 4) /* @@ -310,7 +310,7 @@ #define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) #define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) #define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) -#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4, 4) /* * DUART Output Port Clear Register (Table 10-23) @@ -321,7 +321,7 @@ #define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) #define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) #define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) -#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4, 4) /* * DUART Output Port RTS Register (Table 10-24) @@ -332,7 +332,7 @@ #define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) #define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) #define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) -#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4, 4) #define M_DUART_OUT_PIN_SET(chan) \ (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) @@ -345,14 +345,14 @@ */ #define S_DUART_SIG_FULL _SB_MAKE64(0) -#define M_DUART_SIG_FULL _SB_MAKEMASK(4,S_DUART_SIG_FULL) -#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x,S_DUART_SIG_FULL) -#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x,S_DUART_SIG_FULL,M_DUART_SIG_FULL) +#define M_DUART_SIG_FULL _SB_MAKEMASK(4, S_DUART_SIG_FULL) +#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x, S_DUART_SIG_FULL) +#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL) #define S_DUART_INT_TIME _SB_MAKE64(4) -#define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME) -#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME) -#define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME) +#define M_DUART_INT_TIME _SB_MAKEMASK(4, S_DUART_INT_TIME) +#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x, S_DUART_INT_TIME) +#define G_DUART_INT_TIME(x) _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h index 2e32949..96e28f1 100644 --- a/include/asm-mips/siginfo.h +++ b/include/asm-mips/siginfo.h @@ -106,8 +106,8 @@ typedef struct siginfo { #undef SI_TIMER #undef SI_MESGQ #define SI_ASYNCIO -2 /* sent by AIO completion */ -#define SI_TIMER __SI_CODE(__SI_TIMER,-3) /* sent by timer expiration */ -#define SI_MESGQ __SI_CODE(__SI_MESGQ,-4) /* sent by real time mesq state change */ +#define SI_TIMER __SI_CODE(__SI_TIMER, -3) /* sent by timer expiration */ +#define SI_MESGQ __SI_CODE(__SI_MESGQ, -4) /* sent by real time mesq state change */ #ifdef __KERNEL__ diff --git a/include/asm-mips/sn/addrs.h b/include/asm-mips/sn/addrs.h index 6aa0868..fec9bdd 100644 --- a/include/asm-mips/sn/addrs.h +++ b/include/asm-mips/sn/addrs.h @@ -208,9 +208,9 @@ UINT64_CAST(_pa) & NASID_MASK | \ UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \ (_rgn) << 3) -#define BDPRT_ENTRY_ADDR(_pa,_rgn) (BDPRT_ENTRY((_pa),(_rgn))) -#define BDPRT_ENTRY_S(_pa,_rgn,_val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))=(_val)) -#define BDPRT_ENTRY_L(_pa,_rgn) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))) +#define BDPRT_ENTRY_ADDR(_pa, _rgn) (BDPRT_ENTRY((_pa), (_rgn))) +#define BDPRT_ENTRY_S(_pa, _rgn, _val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn))=(_val)) +#define BDPRT_ENTRY_L(_pa, _rgn) (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn))) #define BDECC_ENTRY(_pa) ((HSPEC_BASE + \ NODE_ADDRSPACE_SIZE / 2) | \ diff --git a/include/asm-mips/sn/klconfig.h b/include/asm-mips/sn/klconfig.h index 852213d..96cfd2a 100644 --- a/include/asm-mips/sn/klconfig.h +++ b/include/asm-mips/sn/klconfig.h @@ -405,7 +405,7 @@ typedef struct kl_config_hdr { #define KLTYPE(_x) ((_x) & KLTYPE_MASK) #define IS_MIO_PRESENT(l) ((l->brd_type == KLTYPE_BASEIO) && \ (l->brd_flags & SECOND_NIC_PRESENT)) -#define IS_MIO_IOC3(l,n) (IS_MIO_PRESENT(l) && (n > 2)) +#define IS_MIO_IOC3(l, n) (IS_MIO_PRESENT(l) && (n > 2)) /* * board structures diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index 59334f5..fb41a8d 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h @@ -393,11 +393,11 @@ * and disable interrupts only for the * current TC, using the TCStatus register. */ - mfc0 t0,CP0_TCSTATUS + mfc0 t0, CP0_TCSTATUS /* Fortunately CU 0 is in the same place in both registers */ /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */ li t1, ST0_CU0 | 0x08001c00 - or t0,t1 + or t0, t1 /* Clear TKSU, leave IXMT */ xori t0, 0x00001800 mtc0 t0, CP0_TCSTATUS @@ -429,11 +429,11 @@ * current TC, using the TCStatus register. */ _ehb - mfc0 t0,CP0_TCSTATUS + mfc0 t0, CP0_TCSTATUS /* Fortunately CU 0 is in the same place in both registers */ /* Set TCU0, TKSU (for later inversion) and IXMT */ li t1, ST0_CU0 | 0x08001c00 - or t0,t1 + or t0, t1 /* Clear TKSU *and* IXMT */ xori t0, 0x00001c00 mtc0 t0, CP0_TCSTATUS diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 862f161..90e4b40 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -62,7 +62,7 @@ do { \ #define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0) #endif -#define switch_to(prev,next,last) \ +#define switch_to(prev, next, last) \ do { \ __mips_mt_fpaff_switch_to(prev); \ if (cpu_has_dsp) \ @@ -193,7 +193,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz return x; } -#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) +#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))) extern void set_handler(unsigned long offset, void *addr, unsigned long len); extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len); diff --git a/include/asm-mips/tlbflush.h b/include/asm-mips/tlbflush.h index 276be77..730e841 100644 --- a/include/asm-mips/tlbflush.h +++ b/include/asm-mips/tlbflush.h @@ -37,10 +37,10 @@ extern void flush_tlb_one(unsigned long vaddr); #define flush_tlb_all() local_flush_tlb_all() #define flush_tlb_mm(mm) local_flush_tlb_mm(mm) -#define flush_tlb_range(vma,vmaddr,end) local_flush_tlb_range(vma, vmaddr, end) +#define flush_tlb_range(vma, vmaddr, end) local_flush_tlb_range(vma, vmaddr, end) #define flush_tlb_kernel_range(vmaddr,end) \ local_flush_tlb_kernel_range(vmaddr, end) -#define flush_tlb_page(vma,page) local_flush_tlb_page(vma, page) +#define flush_tlb_page(vma, page) local_flush_tlb_page(vma, page) #define flush_tlb_one(vaddr) local_flush_tlb_one(vaddr) #endif /* CONFIG_SMP */ diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h index b14acb5..b180488 100644 --- a/include/asm-mips/tx4938/rbtx4938.h +++ b/include/asm-mips/tx4938/rbtx4938.h @@ -153,7 +153,7 @@ #define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) #define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) #define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) -#define RBTX4938_IRQ_IRC_DMA(ch,n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch,n)) +#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n)) #define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO) #define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC) #define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC) diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h index afdb198..650b010 100644 --- a/include/asm-mips/tx4938/tx4938.h +++ b/include/asm-mips/tx4938/tx4938.h @@ -16,7 +16,7 @@ #include #define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) -#define tx4938_write_nfmc(b,addr) (*(volatile unsigned int *)(addr)) = (b) +#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) #define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG @@ -84,27 +84,27 @@ #include #ifdef __BIG_ENDIAN -#define endian_def_l2(e1,e2) \ - volatile unsigned long e1,e2 -#define endian_def_s2(e1,e2) \ - volatile unsigned short e1,e2 -#define endian_def_sb2(e1,e2,e3) \ - volatile unsigned short e1;volatile unsigned char e2,e3 -#define endian_def_b2s(e1,e2,e3) \ - volatile unsigned char e1,e2;volatile unsigned short e3 -#define endian_def_b4(e1,e2,e3,e4) \ - volatile unsigned char e1,e2,e3,e4 +#define endian_def_l2(e1, e2) \ + volatile unsigned long e1, e2 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e1, e2 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned short e1;volatile unsigned char e2, e3 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned char e1, e2;volatile unsigned short e3 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e1, e2, e3, e4 #else -#define endian_def_l2(e1,e2) \ - volatile unsigned long e2,e1 -#define endian_def_s2(e1,e2) \ - volatile unsigned short e2,e1 -#define endian_def_sb2(e1,e2,e3) \ - volatile unsigned char e3,e2;volatile unsigned short e1 -#define endian_def_b2s(e1,e2,e3) \ - volatile unsigned short e3;volatile unsigned char e2,e1 -#define endian_def_b4(e1,e2,e3,e4) \ - volatile unsigned char e4,e3,e2,e1 +#define endian_def_l2(e1, e2) \ + volatile unsigned long e2, e1 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e2, e1 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned char e3, e2;volatile unsigned short e1 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned short e3;volatile unsigned char e2, e1 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e4, e3, e2, e1 #endif @@ -354,7 +354,7 @@ struct tx4938_ccfg_reg { #define TX4938_NUM_IR_SIO 2 #define TX4938_IR_SIO(n) (8 + (n)) #define TX4938_NUM_IR_DMA 4 -#define TX4938_IR_DMA(ch,n) ((ch ? 27 : 10) + (n)) /* 10-13,27-30 */ +#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */ #define TX4938_IR_PIO 14 #define TX4938_IR_PDMAC 15 #define TX4938_IR_PCIC 16 diff --git a/include/asm-mips/tx4938/tx4938_mips.h b/include/asm-mips/tx4938/tx4938_mips.h index 5f8498f..f346ff5 100644 --- a/include/asm-mips/tx4938/tx4938_mips.h +++ b/include/asm-mips/tx4938/tx4938_mips.h @@ -19,10 +19,10 @@ #define reg_rd32(r) ((u32)(*((vu32*)(r)))) #define reg_rd64(r) ((u64)(*((vu64*)(r)))) -#define reg_wr08(r,v) ((*((vu8 *)(r)))=((u8 )(v))) -#define reg_wr16(r,v) ((*((vu16*)(r)))=((u16)(v))) -#define reg_wr32(r,v) ((*((vu32*)(r)))=((u32)(v))) -#define reg_wr64(r,v) ((*((vu64*)(r)))=((u64)(v))) +#define reg_wr08(r, v) ((*((vu8 *)(r)))=((u8 )(v))) +#define reg_wr16(r, v) ((*((vu16*)(r)))=((u16)(v))) +#define reg_wr32(r, v) ((*((vu32*)(r)))=((u32)(v))) +#define reg_wr64(r, v) ((*((vu64*)(r)))=((u64)(v))) typedef volatile __signed char vs8; typedef volatile unsigned char vu8; diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h index 017dfb0..c30c718 100644 --- a/include/asm-mips/uaccess.h +++ b/include/asm-mips/uaccess.h @@ -63,7 +63,7 @@ #define get_fs() (current_thread_info()->addr_limit) #define set_fs(x) (current_thread_info()->addr_limit = (x)) -#define segment_eq(a,b) ((a).seg == (b).seg) +#define segment_eq(a, b) ((a).seg == (b).seg) /* @@ -108,7 +108,7 @@ (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0) #define access_ok(type, addr, size) \ - likely(__access_ok((unsigned long)(addr), (size),__access_mask)) + likely(__access_ok((unsigned long)(addr), (size), __access_mask)) /* * put_user: - Write a simple value into user space. @@ -127,7 +127,7 @@ * Returns zero on success, or -EFAULT on error. */ #define put_user(x,ptr) \ - __put_user_check((x),(ptr),sizeof(*(ptr))) + __put_user_check((x), (ptr), sizeof(*(ptr))) /* * get_user: - Get a simple variable from user space. @@ -147,7 +147,7 @@ * On error, the variable @x is set to zero. */ #define get_user(x,ptr) \ - __get_user_check((x),(ptr),sizeof(*(ptr))) + __get_user_check((x), (ptr), sizeof(*(ptr))) /* * __put_user: - Write a simple value into user space, with less checking. @@ -169,7 +169,7 @@ * Returns zero on success, or -EFAULT on error. */ #define __put_user(x,ptr) \ - __put_user_nocheck((x),(ptr),sizeof(*(ptr))) + __put_user_nocheck((x), (ptr), sizeof(*(ptr))) /* * __get_user: - Get a simple variable from user space, with less checking. @@ -192,7 +192,7 @@ * On error, the variable @x is set to zero. */ #define __get_user(x,ptr) \ - __get_user_nocheck((x),(ptr),sizeof(*(ptr))) + __get_user_nocheck((x), (ptr), sizeof(*(ptr))) struct __large_struct { unsigned long buf[100]; }; #define __m(x) (*(struct __large_struct __user *)(x)) @@ -221,7 +221,7 @@ do { \ } \ } while (0) -#define __get_user_nocheck(x,ptr,size) \ +#define __get_user_nocheck(x, ptr, size) \ ({ \ long __gu_err; \ \ @@ -229,7 +229,7 @@ do { \ __gu_err; \ }) -#define __get_user_check(x,ptr,size) \ +#define __get_user_check(x, ptr, size) \ ({ \ long __gu_err = -EFAULT; \ const __typeof__(*(ptr)) __user * __gu_ptr = (ptr); \ @@ -300,7 +300,7 @@ do { \ #define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr) #endif -#define __put_user_nocheck(x,ptr,size) \ +#define __put_user_nocheck(x, ptr, size) \ ({ \ __typeof__(*(ptr)) __pu_val; \ long __pu_err = 0; \ @@ -316,7 +316,7 @@ do { \ __pu_err; \ }) -#define __put_user_check(x,ptr,size) \ +#define __put_user_check(x, ptr, size) \ ({ \ __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ __typeof__(*(ptr)) __pu_val = (x); \ @@ -389,7 +389,7 @@ extern void __put_user_unknown(void); extern size_t __copy_user(void *__to, const void *__from, size_t __n); -#define __invoke_copy_to_user(to,from,n) \ +#define __invoke_copy_to_user(to, from, n) \ ({ \ register void __user *__cu_to_r __asm__("$4"); \ register const void *__cu_from_r __asm__("$5"); \ @@ -421,7 +421,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); * Returns number of bytes that could not be copied. * On success, this will be zero. */ -#define __copy_to_user(to,from,n) \ +#define __copy_to_user(to, from, n) \ ({ \ void __user *__cu_to; \ const void *__cu_from; \ @@ -437,7 +437,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); -#define __copy_to_user_inatomic(to,from,n) \ +#define __copy_to_user_inatomic(to, from, n) \ ({ \ void __user *__cu_to; \ const void *__cu_from; \ @@ -450,7 +450,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_len; \ }) -#define __copy_from_user_inatomic(to,from,n) \ +#define __copy_from_user_inatomic(to, from, n) \ ({ \ void *__cu_to; \ const void __user *__cu_from; \ @@ -477,7 +477,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); * Returns number of bytes that could not be copied. * On success, this will be zero. */ -#define copy_to_user(to,from,n) \ +#define copy_to_user(to, from, n) \ ({ \ void __user *__cu_to; \ const void *__cu_from; \ @@ -493,7 +493,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_len; \ }) -#define __invoke_copy_from_user(to,from,n) \ +#define __invoke_copy_from_user(to, from, n) \ ({ \ register void *__cu_to_r __asm__("$4"); \ register const void __user *__cu_from_r __asm__("$5"); \ @@ -516,7 +516,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_len_r; \ }) -#define __invoke_copy_from_user_inatomic(to,from,n) \ +#define __invoke_copy_from_user_inatomic(to, from, n) \ ({ \ register void *__cu_to_r __asm__("$4"); \ register const void __user *__cu_from_r __asm__("$5"); \ @@ -556,7 +556,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); * If some data could not be copied, this function will pad the copied * data to the requested size using zero bytes. */ -#define __copy_from_user(to,from,n) \ +#define __copy_from_user(to, from, n) \ ({ \ void *__cu_to; \ const void __user *__cu_from; \ @@ -587,7 +587,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); * If some data could not be copied, this function will pad the copied * data to the requested size using zero bytes. */ -#define copy_from_user(to,from,n) \ +#define copy_from_user(to, from, n) \ ({ \ void *__cu_to; \ const void __user *__cu_from; \ @@ -605,7 +605,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); #define __copy_in_user(to, from, n) __copy_from_user(to, from, n) -#define copy_in_user(to,from,n) \ +#define copy_in_user(to, from, n) \ ({ \ void __user *__cu_to; \ const void __user *__cu_from; \ diff --git a/include/asm-mips/vga.h b/include/asm-mips/vga.h index c1dd0b1..f4cff7e 100644 --- a/include/asm-mips/vga.h +++ b/include/asm-mips/vga.h @@ -13,10 +13,10 @@ * access the videoram directly without any black magic. */ -#define VGA_MAP_MEM(x,s) (0xb0000000L + (unsigned long)(x)) +#define VGA_MAP_MEM(x, s) (0xb0000000L + (unsigned long)(x)) #define vga_readb(x) (*(x)) -#define vga_writeb(x,y) (*(y) = (x)) +#define vga_writeb(x, y) (*(y) = (x)) #define VT_BUF_HAVE_RW /* diff --git a/include/asm-mips/xtalk/xtalk.h b/include/asm-mips/xtalk/xtalk.h index 4a60f27..79bac88 100644 --- a/include/asm-mips/xtalk/xtalk.h +++ b/include/asm-mips/xtalk/xtalk.h @@ -45,7 +45,7 @@ typedef struct xtalk_piomap_s *xtalk_piomap_t; #define XIO_PACKED(x) (((x)&XIO_PORT_BITS) != 0) #define XIO_ADDR(x) ((x)&XIO_ADDR_BITS) #define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT)) -#define XIO_PACK(p,o) ((((uint64_t)(p))< Date: Wed, 14 Feb 2007 21:16:14 +0000 Subject: [MIPS] Optimize get_unaligned / put_unaligned implementations. Signed-off-by: Ralf Baechle diff --git a/include/asm-mips/unaligned.h b/include/asm-mips/unaligned.h index a004256..3249049 100644 --- a/include/asm-mips/unaligned.h +++ b/include/asm-mips/unaligned.h @@ -3,12 +3,27 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 1999, 2000, 2001, 2003 by Ralf Baechle - * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. + * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) */ -#ifndef _ASM_UNALIGNED_H -#define _ASM_UNALIGNED_H +#ifndef __ASM_GENERIC_UNALIGNED_H +#define __ASM_GENERIC_UNALIGNED_H -#include +#include -#endif /* _ASM_UNALIGNED_H */ +#define get_unaligned(ptr) \ +({ \ + struct __packed { \ + typeof(*(ptr)) __v; \ + } *__p = (void *) (ptr); \ + __p->__v; \ +}) + +#define put_unaligned(val, ptr) \ +do { \ + struct __packed { \ + typeof(*(ptr)) __v; \ + } *__p = (void *) (ptr); \ + __p->__v = (val); \ +} while(0) + +#endif /* __ASM_GENERIC_UNALIGNED_H */ -- cgit v0.10.2 From 36cfbaad815908f54872a7b471e9a7a09b4084a4 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:16 +0100 Subject: [MIPS] Convert list of CPU types from #define to enum. Signed-off-by: Ralf Baechle diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 107ccbe..54fc18a 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -157,76 +157,55 @@ #define FPIR_IMP_NONE 0x0000 -#define CPU_UNKNOWN 0 -#define CPU_R2000 1 -#define CPU_R3000 2 -#define CPU_R3000A 3 -#define CPU_R3041 4 -#define CPU_R3051 5 -#define CPU_R3052 6 -#define CPU_R3081 7 -#define CPU_R3081E 8 -#define CPU_R4000PC 9 -#define CPU_R4000SC 10 -#define CPU_R4000MC 11 -#define CPU_R4200 12 -#define CPU_R4400PC 13 -#define CPU_R4400SC 14 -#define CPU_R4400MC 15 -#define CPU_R4600 16 -#define CPU_R6000 17 -#define CPU_R6000A 18 -#define CPU_R8000 19 -#define CPU_R10000 20 -#define CPU_R12000 21 -#define CPU_R4300 22 -#define CPU_R4650 23 -#define CPU_R4700 24 -#define CPU_R5000 25 -#define CPU_R5000A 26 -#define CPU_R4640 27 -#define CPU_NEVADA 28 -#define CPU_RM7000 29 -#define CPU_R5432 30 -#define CPU_4KC 31 -#define CPU_5KC 32 -#define CPU_R4310 33 -#define CPU_SB1 34 -#define CPU_TX3912 35 -#define CPU_TX3922 36 -#define CPU_TX3927 37 -#define CPU_AU1000 38 -#define CPU_4KEC 39 -#define CPU_4KSC 40 -#define CPU_VR41XX 41 -#define CPU_R5500 42 -#define CPU_TX49XX 43 -#define CPU_AU1500 44 -#define CPU_20KC 45 -#define CPU_VR4111 46 -#define CPU_VR4121 47 -#define CPU_VR4122 48 -#define CPU_VR4131 49 -#define CPU_VR4181 50 -#define CPU_VR4181A 51 -#define CPU_AU1100 52 -#define CPU_SR71000 53 -#define CPU_RM9000 54 -#define CPU_25KF 55 -#define CPU_VR4133 56 -#define CPU_AU1550 57 -#define CPU_24K 58 -#define CPU_AU1200 59 -#define CPU_34K 60 -#define CPU_PR4450 61 -#define CPU_SB1A 62 -#define CPU_74K 63 -#define CPU_R14000 64 -#define CPU_LOONGSON1 65 -#define CPU_LOONGSON2 66 -#define CPU_BCM3302 67 -#define CPU_BCM4710 68 -#define CPU_LAST 68 +enum cpu_type_enum { + CPU_UNKNOWN, + + /* + * R2000 class processors + */ + CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, + CPU_R3081, CPU_R3081E, + + /* + * R6000 class processors + */ + CPU_R6000, CPU_R6000A, + + /* + * R4000 class processors + */ + CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, + CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, + CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432, + CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, + CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, + CPU_SR71000, CPU_RM9000, CPU_TX49XX, + + /* + * R8000 class processors + */ + CPU_R8000, + + /* + * TX3900 class processors + */ + CPU_TX3912, CPU_TX3922, CPU_TX3927, + + /* + * MIPS32 class processors + */ + CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000, + CPU_AU1100, CPU_AU1200, CPU_AU1500, CPU_AU1550, CPU_PR4450, + CPU_BCM3302, CPU_BCM4710, + + /* + * MIPS64 class processors + */ + CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, + + CPU_LAST +}; + /* * ISA Level encodings -- cgit v0.10.2 From 9966db25defba4e1dce263246db25237bc24479f Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:17 +0100 Subject: [MIPS] Make facility to convert CPU types to strings generally available. So far /proc/cpuinfo has been the only user but human readable processor name are more useful than that for proc. Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index dde2adf..234c7f5 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -802,9 +802,95 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c) } } +const char *__cpu_name[NR_CPUS]; + +/* + * Name a CPU + */ +static __init const char *cpu_to_name(struct cpuinfo_mips *c) +{ + const char *name = NULL; + + switch (c->cputype) { + case CPU_UNKNOWN: name = "unknown"; break; + case CPU_R2000: name = "R2000"; break; + case CPU_R3000: name = "R3000"; break; + case CPU_R3000A: name = "R3000A"; break; + case CPU_R3041: name = "R3041"; break; + case CPU_R3051: name = "R3051"; break; + case CPU_R3052: name = "R3052"; break; + case CPU_R3081: name = "R3081"; break; + case CPU_R3081E: name = "R3081E"; break; + case CPU_R4000PC: name = "R4000PC"; break; + case CPU_R4000SC: name = "R4000SC"; break; + case CPU_R4000MC: name = "R4000MC"; break; + case CPU_R4200: name = "R4200"; break; + case CPU_R4400PC: name = "R4400PC"; break; + case CPU_R4400SC: name = "R4400SC"; break; + case CPU_R4400MC: name = "R4400MC"; break; + case CPU_R4600: name = "R4600"; break; + case CPU_R6000: name = "R6000"; break; + case CPU_R6000A: name = "R6000A"; break; + case CPU_R8000: name = "R8000"; break; + case CPU_R10000: name = "R10000"; break; + case CPU_R12000: name = "R12000"; break; + case CPU_R14000: name = "R14000"; break; + case CPU_R4300: name = "R4300"; break; + case CPU_R4650: name = "R4650"; break; + case CPU_R4700: name = "R4700"; break; + case CPU_R5000: name = "R5000"; break; + case CPU_R5000A: name = "R5000A"; break; + case CPU_R4640: name = "R4640"; break; + case CPU_NEVADA: name = "Nevada"; break; + case CPU_RM7000: name = "RM7000"; break; + case CPU_RM9000: name = "RM9000"; break; + case CPU_R5432: name = "R5432"; break; + case CPU_4KC: name = "MIPS 4Kc"; break; + case CPU_5KC: name = "MIPS 5Kc"; break; + case CPU_R4310: name = "R4310"; break; + case CPU_SB1: name = "SiByte SB1"; break; + case CPU_SB1A: name = "SiByte SB1A"; break; + case CPU_TX3912: name = "TX3912"; break; + case CPU_TX3922: name = "TX3922"; break; + case CPU_TX3927: name = "TX3927"; break; + case CPU_AU1000: name = "Au1000"; break; + case CPU_AU1500: name = "Au1500"; break; + case CPU_AU1100: name = "Au1100"; break; + case CPU_AU1550: name = "Au1550"; break; + case CPU_AU1200: name = "Au1200"; break; + case CPU_4KEC: name = "MIPS 4KEc"; break; + case CPU_4KSC: name = "MIPS 4KSc"; break; + case CPU_VR41XX: name = "NEC Vr41xx"; break; + case CPU_R5500: name = "R5500"; break; + case CPU_TX49XX: name = "TX49xx"; break; + case CPU_20KC: name = "MIPS 20Kc"; break; + case CPU_24K: name = "MIPS 24K"; break; + case CPU_25KF: name = "MIPS 25Kf"; break; + case CPU_34K: name = "MIPS 34K"; break; + case CPU_74K: name = "MIPS 74K"; break; + case CPU_VR4111: name = "NEC VR4111"; break; + case CPU_VR4121: name = "NEC VR4121"; break; + case CPU_VR4122: name = "NEC VR4122"; break; + case CPU_VR4131: name = "NEC VR4131"; break; + case CPU_VR4133: name = "NEC VR4133"; break; + case CPU_VR4181: name = "NEC VR4181"; break; + case CPU_VR4181A: name = "NEC VR4181A"; break; + case CPU_SR71000: name = "Sandcraft SR71000"; break; + case CPU_BCM3302: name = "Broadcom BCM3302"; break; + case CPU_BCM4710: name = "Broadcom BCM4710"; break; + case CPU_PR4450: name = "Philips PR4450"; break; + case CPU_LOONGSON2: name = "ICT Loongson-2"; break; + default: + BUG(); + } + + return name; +} + __init void cpu_probe(void) { struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int cpu = smp_processor_id(); c->processor_id = PRID_IMP_UNKNOWN; c->fpu_id = FPIR_IMP_NONE; @@ -847,13 +933,16 @@ __init void cpu_probe(void) c->ases |= MIPS_ASE_MIPS3D; } } + + __cpu_name[cpu] = cpu_to_name(c); } __init void cpu_report(void) { struct cpuinfo_mips *c = ¤t_cpu_data; - printk("CPU revision is: %08x\n", c->processor_id); + printk(KERN_INFO "CPU revision is: %08x (%s)\n", + c->processor_id, cpu_name_string()); if (c->options & MIPS_CPU_FPU) - printk("FPU revision is: %08x\n", c->fpu_id); + printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); } diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index accd520..efd2d13 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -17,78 +17,6 @@ unsigned int vced_count, vcei_count; -static const char *cpu_name[] = { - [CPU_UNKNOWN] = "unknown", - [CPU_R2000] = "R2000", - [CPU_R3000] = "R3000", - [CPU_R3000A] = "R3000A", - [CPU_R3041] = "R3041", - [CPU_R3051] = "R3051", - [CPU_R3052] = "R3052", - [CPU_R3081] = "R3081", - [CPU_R3081E] = "R3081E", - [CPU_R4000PC] = "R4000PC", - [CPU_R4000SC] = "R4000SC", - [CPU_R4000MC] = "R4000MC", - [CPU_R4200] = "R4200", - [CPU_R4400PC] = "R4400PC", - [CPU_R4400SC] = "R4400SC", - [CPU_R4400MC] = "R4400MC", - [CPU_R4600] = "R4600", - [CPU_R6000] = "R6000", - [CPU_R6000A] = "R6000A", - [CPU_R8000] = "R8000", - [CPU_R10000] = "R10000", - [CPU_R12000] = "R12000", - [CPU_R14000] = "R14000", - [CPU_R4300] = "R4300", - [CPU_R4650] = "R4650", - [CPU_R4700] = "R4700", - [CPU_R5000] = "R5000", - [CPU_R5000A] = "R5000A", - [CPU_R4640] = "R4640", - [CPU_NEVADA] = "Nevada", - [CPU_RM7000] = "RM7000", - [CPU_RM9000] = "RM9000", - [CPU_R5432] = "R5432", - [CPU_4KC] = "MIPS 4Kc", - [CPU_5KC] = "MIPS 5Kc", - [CPU_R4310] = "R4310", - [CPU_SB1] = "SiByte SB1", - [CPU_SB1A] = "SiByte SB1A", - [CPU_TX3912] = "TX3912", - [CPU_TX3922] = "TX3922", - [CPU_TX3927] = "TX3927", - [CPU_AU1000] = "Au1000", - [CPU_AU1500] = "Au1500", - [CPU_AU1100] = "Au1100", - [CPU_AU1550] = "Au1550", - [CPU_AU1200] = "Au1200", - [CPU_4KEC] = "MIPS 4KEc", - [CPU_4KSC] = "MIPS 4KSc", - [CPU_VR41XX] = "NEC Vr41xx", - [CPU_R5500] = "R5500", - [CPU_TX49XX] = "TX49xx", - [CPU_20KC] = "MIPS 20Kc", - [CPU_24K] = "MIPS 24K", - [CPU_25KF] = "MIPS 25Kf", - [CPU_34K] = "MIPS 34K", - [CPU_74K] = "MIPS 74K", - [CPU_VR4111] = "NEC VR4111", - [CPU_VR4121] = "NEC VR4121", - [CPU_VR4122] = "NEC VR4122", - [CPU_VR4131] = "NEC VR4131", - [CPU_VR4133] = "NEC VR4133", - [CPU_VR4181] = "NEC VR4181", - [CPU_VR4181A] = "NEC VR4181A", - [CPU_SR71000] = "Sandcraft SR71000", - [CPU_BCM3302] = "Broadcom BCM3302", - [CPU_BCM4710] = "Broadcom BCM4710", - [CPU_PR4450] = "Philips PR4450", - [CPU_LOONGSON2] = "ICT Loongson-2", -}; - - static int show_cpuinfo(struct seq_file *m, void *v) { unsigned long n = (unsigned long) v - 1; @@ -110,8 +38,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "processor\t\t: %ld\n", n); sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); - seq_printf(m, fmt, cpu_name[cpu_data[n].cputype <= CPU_LAST ? - cpu_data[n].cputype : CPU_UNKNOWN], + seq_printf(m, fmt, __cpu_name[smp_processor_id()], (version >> 4) & 0x0f, version & 0x0f, (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n", diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index b3e408b..632bce1 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -295,7 +295,8 @@ void show_regs(struct pt_regs *regs) if (1 <= cause && cause <= 5) printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); - printk("PrId : %08x\n", read_c0_prid()); + printk("PrId : %08x (%s)\n", read_c0_prid(), + cpu_name_string()); } void show_registers(struct pt_regs *regs) diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h index 0468959..94f1c81 100644 --- a/include/asm-mips/cpu-info.h +++ b/include/asm-mips/cpu-info.h @@ -74,4 +74,7 @@ extern struct cpuinfo_mips cpu_data[]; extern void cpu_probe(void); extern void cpu_report(void); +extern const char *__cpu_name[]; +#define cpu_name_string() __cpu_name[smp_processor_id()] + #endif /* __ASM_CPU_INFO_H */ -- cgit v0.10.2 From bd6aeeffcc0be716e4d2d1f27fb132741e345cc0 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 3 Oct 2007 01:24:16 +0100 Subject: [MIPS] SMP: Implement smp_call_function_mask(). Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c index c33f6f2..bd128fa 100644 --- a/arch/mips/kernel/gdb-stub.c +++ b/arch/mips/kernel/gdb-stub.c @@ -676,15 +676,18 @@ static void kgdb_wait(void *arg) static int kgdb_smp_call_kgdb_wait(void) { #ifdef CONFIG_SMP + cpumask_t mask = cpu_online_map; struct call_data_struct data; - int i, cpus = num_online_cpus() - 1; int cpu = smp_processor_id(); + int cpus; /* * Can die spectacularly if this CPU isn't yet marked online */ BUG_ON(!cpu_online(cpu)); + cpu_clear(cpu, mask); + cpus = cpus_weight(mask); if (!cpus) return 0; @@ -711,10 +714,7 @@ static int kgdb_smp_call_kgdb_wait(void) call_data = &data; mb(); - /* Send a message to all other CPUs and wait for them to respond */ - for (i = 0; i < NR_CPUS; i++) - if (cpu_online(i) && i != cpu) - core_send_ipi(i, SMP_CALL_FUNCTION); + core_send_ipi_mask(mask, SMP_CALL_FUNCTION); /* Wait for response */ /* FIXME: lock-up detection, backtrace on lock-up */ diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 500a7ec..481ba53 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -97,6 +97,8 @@ struct call_data_struct *call_data; /* * Run a function on all other CPUs. + * + * cpuset_t of all processors to run the function on. * The function to run. This must be fast and non-blocking. * An arbitrary pointer to pass to the function. * If true, keep retrying until ready. @@ -121,18 +123,20 @@ struct call_data_struct *call_data; * Spin waiting for call_lock * Deadlock Deadlock */ -int smp_call_function (void (*func) (void *info), void *info, int retry, - int wait) +int smp_call_function_mask(cpumask_t mask, void (*func) (void *info), + void *info, int retry, int wait) { struct call_data_struct data; - int i, cpus = num_online_cpus() - 1; int cpu = smp_processor_id(); + int cpus; /* * Can die spectacularly if this CPU isn't yet marked online */ BUG_ON(!cpu_online(cpu)); + cpu_clear(cpu, mask); + cpus = cpus_weight(mask); if (!cpus) return 0; @@ -151,9 +155,7 @@ int smp_call_function (void (*func) (void *info), void *info, int retry, smp_mb(); /* Send a message to all other CPUs and wait for them to respond */ - for_each_online_cpu(i) - if (i != cpu) - core_send_ipi(i, SMP_CALL_FUNCTION); + core_send_ipi_mask(mask, SMP_CALL_FUNCTION); /* Wait for response */ /* FIXME: lock-up detection, backtrace on lock-up */ @@ -169,6 +171,11 @@ int smp_call_function (void (*func) (void *info), void *info, int retry, return 0; } +int smp_call_function(void (*func) (void *info), void *info, int retry, + int wait) +{ + return smp_call_function_mask(cpu_online_map, func, info, retry, wait); +} void smp_call_function_interrupt(void) { @@ -199,8 +206,7 @@ void smp_call_function_interrupt(void) int smp_call_function_single(int cpu, void (*func) (void *info), void *info, int retry, int wait) { - struct call_data_struct data; - int me; + int ret, me; /* * Can die spectacularly if this CPU isn't yet marked online @@ -219,33 +225,8 @@ int smp_call_function_single(int cpu, void (*func) (void *info), void *info, return 0; } - /* Can deadlock when called with interrupts disabled */ - WARN_ON(irqs_disabled()); - - data.func = func; - data.info = info; - atomic_set(&data.started, 0); - data.wait = wait; - if (wait) - atomic_set(&data.finished, 0); - - spin_lock(&smp_call_lock); - call_data = &data; - smp_mb(); - - /* Send a message to the other CPU */ - core_send_ipi(cpu, SMP_CALL_FUNCTION); - - /* Wait for response */ - /* FIXME: lock-up detection, backtrace on lock-up */ - while (atomic_read(&data.started) != 1) - barrier(); - - if (wait) - while (atomic_read(&data.finished) != 1) - barrier(); - call_data = NULL; - spin_unlock(&smp_call_lock); + ret = smp_call_function_mask(cpumask_of_cpu(cpu), func, info, retry, + wait); put_cpu(); return 0; diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h index 13aef6a..dc77002 100644 --- a/include/asm-mips/smp.h +++ b/include/asm-mips/smp.h @@ -60,6 +60,15 @@ extern cpumask_t phys_cpu_present_map; */ extern void core_send_ipi(int cpu, unsigned int action); +static inline void core_send_ipi_mask(cpumask_t mask, unsigned int action) +{ + unsigned int i; + + for_each_cpu_mask(i, mask) + core_send_ipi(i, action); +} + + /* * Firmware CPU startup hook */ -- cgit v0.10.2 From b5eb551145395382ddf302548991a5fbaabc5341 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 3 Oct 2007 19:16:57 +0100 Subject: [MIPS] Kill num_online_cpus() loops. Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c index bd128fa..3191afa 100644 --- a/arch/mips/kernel/gdb-stub.c +++ b/arch/mips/kernel/gdb-stub.c @@ -769,7 +769,7 @@ void handle_exception(struct gdb_regs *regs) /* * acquire the CPU spinlocks */ - for (i = num_online_cpus()-1; i >= 0; i--) + for_each_online_cpu(i) if (__raw_spin_trylock(&kgdb_cpulock[i]) == 0) panic("kgdb: couldn't get cpulock %d\n", i); @@ -1044,7 +1044,7 @@ finish_kgdb: exit_kgdb_exception: /* release locks so other CPUs can go */ - for (i = num_online_cpus()-1; i >= 0; i--) + for_each_online_cpu(i) __raw_spin_unlock(&kgdb_cpulock[i]); spin_unlock(&kgdb_lock); diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 481ba53..5ca3809 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -375,10 +375,13 @@ void flush_tlb_mm(struct mm_struct *mm) if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { smp_on_other_tlbs(flush_tlb_mm_ipi, (void *)mm); } else { - int i; - for (i = 0; i < num_online_cpus(); i++) - if (smp_processor_id() != i) - cpu_context(i, mm) = 0; + cpumask_t mask = cpu_online_map; + unsigned int cpu; + + cpu_clear(smp_processor_id(), mask); + for_each_online_cpu(cpu) + if (cpu_context(cpu, mm)) + cpu_context(cpu, mm) = 0; } local_flush_tlb_mm(mm); @@ -411,10 +414,13 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned l fd.addr2 = end; smp_on_other_tlbs(flush_tlb_range_ipi, (void *)&fd); } else { - int i; - for (i = 0; i < num_online_cpus(); i++) - if (smp_processor_id() != i) - cpu_context(i, mm) = 0; + cpumask_t mask = cpu_online_map; + unsigned int cpu; + + cpu_clear(smp_processor_id(), mask); + for_each_online_cpu(cpu) + if (cpu_context(cpu, mm)) + cpu_context(cpu, mm) = 0; } local_flush_tlb_range(vma, start, end); preempt_enable(); @@ -453,10 +459,13 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) fd.addr1 = page; smp_on_other_tlbs(flush_tlb_page_ipi, (void *)&fd); } else { - int i; - for (i = 0; i < num_online_cpus(); i++) - if (smp_processor_id() != i) - cpu_context(i, vma->vm_mm) = 0; + cpumask_t mask = cpu_online_map; + unsigned int cpu; + + cpu_clear(smp_processor_id(), mask); + for_each_online_cpu(cpu) + if (cpu_context(cpu, vma->vm_mm)) + cpu_context(cpu, vma->vm_mm) = 0; } local_flush_tlb_page(vma, page); preempt_enable(); diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 4d91e2f..a8c1a69 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -1264,7 +1264,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) if (cpu_has_vtag_icache) flush_icache_all(); /* Traverse all online CPUs (hack requires contigous range) */ - for (i = 0; i < num_online_cpus(); i++) { + for_each_online_cpu(i) { /* * We don't need to worry about our own CPU, nor those of * CPUs who don't share our TLB. @@ -1293,7 +1293,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) /* * SMTC shares the TLB within VPEs and possibly across all VPEs. */ - for (i = 0; i < num_online_cpus(); i++) { + for_each_online_cpu(i) { if ((smtc_status & SMTC_TLB_SHARED) || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) cpu_context(i, mm) = asid_cache(i) = asid; diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h index b3b7a68..0c4f245 100644 --- a/include/asm-mips/mmu_context.h +++ b/include/asm-mips/mmu_context.h @@ -120,7 +120,7 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm) { int i; - for (i = 0; i < num_online_cpus(); i++) + for_each_online_cpu(i) cpu_context(i, mm) = 0; return 0; @@ -284,7 +284,7 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu) int i; /* SMTC shares the TLB (and ASIDs) across VPEs */ - for (i = 0; i < num_online_cpus(); i++) { + for_each_online_cpu(i) { if((smtc_status & SMTC_TLB_SHARED) || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) cpu_context(i, mm) = 0; -- cgit v0.10.2 From c50cade95b075e1116fc4fae6a9c63829720efb9 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 4 Oct 2007 16:57:08 +0100 Subject: [MIPS] SMP: Kill useless casts. Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 5ca3809..54464fd 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -373,7 +373,7 @@ void flush_tlb_mm(struct mm_struct *mm) preempt_disable(); if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { - smp_on_other_tlbs(flush_tlb_mm_ipi, (void *)mm); + smp_on_other_tlbs(flush_tlb_mm_ipi, mm); } else { cpumask_t mask = cpu_online_map; unsigned int cpu; @@ -396,7 +396,7 @@ struct flush_tlb_data { static void flush_tlb_range_ipi(void *info) { - struct flush_tlb_data *fd = (struct flush_tlb_data *)info; + struct flush_tlb_data *fd = info; local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); } @@ -412,7 +412,7 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned l fd.vma = vma; fd.addr1 = start; fd.addr2 = end; - smp_on_other_tlbs(flush_tlb_range_ipi, (void *)&fd); + smp_on_other_tlbs(flush_tlb_range_ipi, &fd); } else { cpumask_t mask = cpu_online_map; unsigned int cpu; @@ -428,7 +428,7 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned l static void flush_tlb_kernel_range_ipi(void *info) { - struct flush_tlb_data *fd = (struct flush_tlb_data *)info; + struct flush_tlb_data *fd = info; local_flush_tlb_kernel_range(fd->addr1, fd->addr2); } @@ -439,12 +439,12 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end) fd.addr1 = start; fd.addr2 = end; - on_each_cpu(flush_tlb_kernel_range_ipi, (void *)&fd, 1, 1); + on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1, 1); } static void flush_tlb_page_ipi(void *info) { - struct flush_tlb_data *fd = (struct flush_tlb_data *)info; + struct flush_tlb_data *fd = info; local_flush_tlb_page(fd->vma, fd->addr1); } @@ -457,7 +457,7 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) fd.vma = vma; fd.addr1 = page; - smp_on_other_tlbs(flush_tlb_page_ipi, (void *)&fd); + smp_on_other_tlbs(flush_tlb_page_ipi, &fd); } else { cpumask_t mask = cpu_online_map; unsigned int cpu; -- cgit v0.10.2 From 89a8a5a6c965d3dd2571a263ef59e7b23a036d5e Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 4 Oct 2007 18:18:52 +0100 Subject: [MIPS] SMP: Use ISO C struct initializer for local structs. Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 54464fd..432f2e3 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -407,11 +407,12 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned l preempt_disable(); if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { - struct flush_tlb_data fd; + struct flush_tlb_data fd = { + .vma = vma, + .addr1 = start, + .addr2 = end, + }; - fd.vma = vma; - fd.addr1 = start; - fd.addr2 = end; smp_on_other_tlbs(flush_tlb_range_ipi, &fd); } else { cpumask_t mask = cpu_online_map; @@ -435,10 +436,11 @@ static void flush_tlb_kernel_range_ipi(void *info) void flush_tlb_kernel_range(unsigned long start, unsigned long end) { - struct flush_tlb_data fd; + struct flush_tlb_data fd = { + .addr1 = start, + .addr2 = end, + }; - fd.addr1 = start; - fd.addr2 = end; on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1, 1); } @@ -453,10 +455,11 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) { preempt_disable(); if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { - struct flush_tlb_data fd; + struct flush_tlb_data fd = { + .vma = vma, + .addr1 = page, + }; - fd.vma = vma; - fd.addr1 = page; smp_on_other_tlbs(flush_tlb_page_ipi, &fd); } else { cpumask_t mask = cpu_online_map; -- cgit v0.10.2 From dec8b1ca990055f3a8954ac3bc98fdb785af52e4 Mon Sep 17 00:00:00 2001 From: Franck Bui-Huu Date: Mon, 8 Oct 2007 16:11:51 +0200 Subject: [MIPS] Add BUG_ON assertion for attempt to run kernel on the wrong CPU type. Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 234c7f5..c8c47a2 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -922,6 +922,14 @@ __init void cpu_probe(void) default: c->cputype = CPU_UNKNOWN; } + + /* + * Platform code can force the cpu type to optimize code + * generation. In that case be sure the cpu type is correctly + * manually setup otherwise it could trigger some nasty bugs. + */ + BUG_ON(current_cpu_type() != c->cputype); + if (c->options & MIPS_CPU_FPU) { c->fpu_id = cpu_get_fpu_id(); -- cgit v0.10.2 From 4b92fe2309c762d9ba9201a16f20d6d167e641b3 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Wed, 10 Oct 2007 00:28:26 +0900 Subject: [MIPS] cleanup WRPPMC include files Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c index 06177bf..c6e7062 100644 --- a/arch/mips/gt64120/wrppmc/irq.c +++ b/arch/mips/gt64120/wrppmc/irq.c @@ -9,26 +9,13 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ -#include +#include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include + #include +#include +#include asmlinkage void plat_irq_dispatch(void) { diff --git a/arch/mips/gt64120/wrppmc/pci.c b/arch/mips/gt64120/wrppmc/pci.c index 0d5289b..d06192f 100644 --- a/arch/mips/gt64120/wrppmc/pci.c +++ b/arch/mips/gt64120/wrppmc/pci.c @@ -8,9 +8,10 @@ * for more details. */ #include +#include #include #include -#include + #include extern struct pci_ops gt64xxx_pci0_ops; diff --git a/arch/mips/gt64120/wrppmc/reset.c b/arch/mips/gt64120/wrppmc/reset.c index b97039c..c355cff 100644 --- a/arch/mips/gt64120/wrppmc/reset.c +++ b/arch/mips/gt64120/wrppmc/reset.c @@ -5,14 +5,10 @@ * * Copyright (C) 1997 Ralf Baechle */ -#include -#include -#include -#include -#include -#include -#include +#include + #include +#include void wrppmc_machine_restart(char *command) { diff --git a/arch/mips/gt64120/wrppmc/time.c b/arch/mips/gt64120/wrppmc/time.c index faf164e..b207e7f 100644 --- a/arch/mips/gt64120/wrppmc/time.c +++ b/arch/mips/gt64120/wrppmc/time.c @@ -11,18 +11,11 @@ * Copyright (C) 2006, Wind River System Inc. */ #include -#include -#include -#include /* for HZ */ -#include -#include #include +#include -#include -#include -#include -#include #include +#include #define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */ -- cgit v0.10.2 From bdf5d42c6e4d7aa56251b8899f60f55a88c0aaa7 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 10 Oct 2007 13:33:03 +0100 Subject: [MIPS] VPE: reimplement ELF loader. Loading ELF binaries based on the section table is totally wrong. This still leaves the other fat bug of referencing symbols in an executable unfixed, so people better don't run strip on their binaries ... As added bonus the new loader is also 23 lines shorter. Signed-off-by: Ralf Baechle diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index 45077c4..61b729f 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -936,8 +936,18 @@ static int vpe_elfload(struct vpe * v) } } else { - for (i = 0; i < hdr->e_shnum; i++) { + struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff); + for (i = 0; i < hdr->e_phnum; i++) { + if (phdr->p_type != PT_LOAD) + continue; + + memcpy((void *)phdr->p_vaddr, (char *)hdr + phdr->p_offset, phdr->p_filesz); + memset((void *)phdr->p_vaddr + phdr->p_filesz, 0, phdr->p_memsz - phdr->p_filesz); + phdr++; + } + + for (i = 0; i < hdr->e_shnum; i++) { /* Internal symbols and strings. */ if (sechdrs[i].sh_type == SHT_SYMTAB) { symindex = i; @@ -948,39 +958,6 @@ static int vpe_elfload(struct vpe * v) magic symbols */ sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset; } - - /* filter sections we dont want in the final image */ - if (!(sechdrs[i].sh_flags & SHF_ALLOC) || - (sechdrs[i].sh_type == SHT_MIPS_REGINFO)) { - printk( KERN_DEBUG " ignoring section, " - "name %s type %x address 0x%x \n", - secstrings + sechdrs[i].sh_name, - sechdrs[i].sh_type, sechdrs[i].sh_addr); - continue; - } - - if (sechdrs[i].sh_addr < (unsigned int)v->load_addr) { - printk( KERN_WARNING "VPE loader: " - "fully linked image has invalid section, " - "name %s type %x address 0x%x, before load " - "address of 0x%x\n", - secstrings + sechdrs[i].sh_name, - sechdrs[i].sh_type, sechdrs[i].sh_addr, - (unsigned int)v->load_addr); - return -ENOEXEC; - } - - printk(KERN_DEBUG " copying section sh_name %s, sh_addr 0x%x " - "size 0x%x0 from x%p\n", - secstrings + sechdrs[i].sh_name, sechdrs[i].sh_addr, - sechdrs[i].sh_size, hdr + sechdrs[i].sh_offset); - - if (sechdrs[i].sh_type != SHT_NOBITS) - memcpy((void *)sechdrs[i].sh_addr, - (char *)hdr + sechdrs[i].sh_offset, - sechdrs[i].sh_size); - else - memset((void *)sechdrs[i].sh_addr, 0, sechdrs[i].sh_size); } } -- cgit v0.10.2 From 572afc248c33c902760f6f24a72c180f0e4f1719 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Fri, 21 Sep 2007 13:05:44 +0100 Subject: [MIPS] R1: Fix hazard barriers to make kernels work on R2 also. Tested with Malta; inflates malta_defconfig by 3932 bytes. Ideally there should be additional configuration to allow getting rid of this overhead but that would be too much complexity at this stage of the release cycle. Signed-off-by: Ralf Baechle diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index 7e843b5..2de638f 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -10,11 +10,12 @@ #ifndef _ASM_HAZARDS_H #define _ASM_HAZARDS_H - #ifdef __ASSEMBLY__ #define ASMMACRO(name, code...) .macro name; code; .endm #else +#include + #define ASMMACRO(name, code...) \ __asm__(".macro " #name "; " #code "; .endm"); \ \ @@ -86,6 +87,57 @@ do { \ : "=r" (tmp)); \ } while (0) +#elif defined(CONFIG_CPU_MIPSR1) + +/* + * These are slightly complicated by the fact that we guarantee R1 kernels to + * run fine on R2 processors. + */ +ASMMACRO(mtc0_tlbw_hazard, + _ssnop; _ssnop; _ehb + ) +ASMMACRO(tlbw_use_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +ASMMACRO(tlb_probe_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +ASMMACRO(irq_enable_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +ASMMACRO(irq_disable_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +ASMMACRO(back_to_back_c0_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +/* + * gcc has a tradition of misscompiling the previous construct using the + * address of a label as argument to inline assembler. Gas otoh has the + * annoying difference between la and dla which are only usable for 32-bit + * rsp. 64-bit code, so can't be used without conditional compilation. + * The alterantive is switching the assembler to 64-bit code which happens + * to work right even for 32-bit code ... + */ +#define __instruction_hazard() \ +do { \ + unsigned long tmp; \ + \ + __asm__ __volatile__( \ + " .set mips64r2 \n" \ + " dla %0, 1f \n" \ + " jr.hb %0 \n" \ + " .set mips0 \n" \ + "1: \n" \ + : "=r" (tmp)); \ +} while (0) + +#define instruction_hazard() \ +do { \ + if (cpu_has_mips_r2) \ + __instruction_hazard(); \ +} while (0) + #elif defined(CONFIG_CPU_R10000) /* -- cgit v0.10.2 From 2c4d13570d8e512cca65d159502622e1666ad4bd Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Thu, 11 Oct 2007 22:54:13 +0900 Subject: [MIPS] WRPPMC serial support move to platform device Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/arch/mips/gt64120/wrppmc/Makefile b/arch/mips/gt64120/wrppmc/Makefile index bef15c9..b49d282 100644 --- a/arch/mips/gt64120/wrppmc/Makefile +++ b/arch/mips/gt64120/wrppmc/Makefile @@ -9,6 +9,6 @@ # Makefile for the Wind River MIPS 4KC PPMC Eval Board # -obj-y += irq.o reset.o setup.o time.o pci.o +obj-y += irq.o pci.o reset.o serial.o setup.o time.o EXTRA_CFLAGS += -Werror diff --git a/arch/mips/gt64120/wrppmc/serial.c b/arch/mips/gt64120/wrppmc/serial.c new file mode 100644 index 0000000..5ec1c2f --- /dev/null +++ b/arch/mips/gt64120/wrppmc/serial.c @@ -0,0 +1,80 @@ +/* + * Registration of WRPPMC UART platform device. + * + * Copyright (C) 2007 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include + +#include + +static struct resource wrppmc_uart_resource[] __initdata = { + { + .start = WRPPMC_UART16550_BASE, + .end = WRPPMC_UART16550_BASE + 7, + .flags = IORESOURCE_MEM, + }, + { + .start = WRPPMC_UART16550_IRQ, + .end = WRPPMC_UART16550_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct plat_serial8250_port wrppmc_serial8250_port[] = { + { + .irq = WRPPMC_UART16550_IRQ, + .uartclk = WRPPMC_UART16550_CLOCK, + .iotype = UPIO_MEM, + .flags = UPF_IOREMAP | UPF_SKIP_TEST, + .mapbase = WRPPMC_UART16550_BASE, + }, + {}, +}; + +static __init int wrppmc_uart_add(void) +{ + struct platform_device *pdev; + int retval; + + pdev = platform_device_alloc("serial8250", -1); + if (!pdev) + return -ENOMEM; + + pdev->id = PLAT8250_DEV_PLATFORM; + pdev->dev.platform_data = wrppmc_serial8250_port; + + retval = platform_device_add_resources(pdev, wrppmc_uart_resource, + ARRAY_SIZE(wrppmc_uart_resource)); + if (retval) + goto err_free_device; + + retval = platform_device_add(pdev); + if (retval) + goto err_free_device; + + return 0; + +err_free_device: + platform_device_put(pdev); + + return retval; +} +device_initcall(wrppmc_uart_add); diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/gt64120/wrppmc/setup.c index f2ccf10..51f6b78 100644 --- a/arch/mips/gt64120/wrppmc/setup.c +++ b/arch/mips/gt64120/wrppmc/setup.c @@ -11,10 +11,6 @@ #include #include #include -#include -#include -#include -#include #include #include @@ -98,32 +94,6 @@ void __init prom_free_prom_memory(void) { } -#ifdef CONFIG_SERIAL_8250 -static void wrppmc_setup_serial(void) -{ - struct uart_port up; - - memset(&up, 0x00, sizeof(struct uart_port)); - - /* - * A note about mapbase/membase - * -) mapbase is the physical address of the IO port. - * -) membase is an 'ioremapped' cookie. - */ - up.line = 0; - up.type = PORT_16550; - up.iotype = UPIO_MEM; - up.mapbase = WRPPMC_UART16550_BASE; - up.membase = ioremap(up.mapbase, 8); - up.irq = WRPPMC_UART16550_IRQ; - up.uartclk = WRPPMC_UART16550_CLOCK; - up.flags = UPF_SKIP_TEST/* | UPF_BOOT_AUTOCONF */; - up.regshift = 0; - - early_serial_setup(&up); -} -#endif - void __init plat_mem_setup(void) { extern void wrppmc_machine_restart(char *command); @@ -138,10 +108,6 @@ void __init plat_mem_setup(void) * physical address ( < KSEG0) can work via KSEG1 */ set_io_port_base(KSEG1); - -#ifdef CONFIG_SERIAL_8250 - wrppmc_setup_serial(); -#endif } const char *get_system_type(void) -- cgit v0.10.2 From aaf76a3245c02faba51c96b9a340c14d6bb0dcc0 Mon Sep 17 00:00:00 2001 From: Franck Bui-Huu Date: Tue, 9 Oct 2007 22:34:26 +0200 Subject: [MIPS] tlbex.c: Cleanup __init usage. Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index a61246d..01b0961 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -66,7 +66,7 @@ static inline int __maybe_unused r10000_llsc_war(void) * why; it's not an issue caused by the core RTL. * */ -static __init int __attribute__((unused)) m4kc_tlbp_war(void) +static int __init m4kc_tlbp_war(void) { return (current_cpu_data.processor_id & 0xffff00) == (PRID_COMP_MIPS | PRID_IMP_4KC); @@ -140,7 +140,7 @@ struct insn { | (e) << RE_SH \ | (f) << FUNC_SH) -static __initdata struct insn insn_table[] = { +static struct insn insn_table[] __initdata = { { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, @@ -193,7 +193,7 @@ static __initdata struct insn insn_table[] = { #undef M -static __init u32 build_rs(u32 arg) +static u32 __init build_rs(u32 arg) { if (arg & ~RS_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -201,7 +201,7 @@ static __init u32 build_rs(u32 arg) return (arg & RS_MASK) << RS_SH; } -static __init u32 build_rt(u32 arg) +static u32 __init build_rt(u32 arg) { if (arg & ~RT_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -209,7 +209,7 @@ static __init u32 build_rt(u32 arg) return (arg & RT_MASK) << RT_SH; } -static __init u32 build_rd(u32 arg) +static u32 __init build_rd(u32 arg) { if (arg & ~RD_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -217,7 +217,7 @@ static __init u32 build_rd(u32 arg) return (arg & RD_MASK) << RD_SH; } -static __init u32 build_re(u32 arg) +static u32 __init build_re(u32 arg) { if (arg & ~RE_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -225,7 +225,7 @@ static __init u32 build_re(u32 arg) return (arg & RE_MASK) << RE_SH; } -static __init u32 build_simm(s32 arg) +static u32 __init build_simm(s32 arg) { if (arg > 0x7fff || arg < -0x8000) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -233,7 +233,7 @@ static __init u32 build_simm(s32 arg) return arg & 0xffff; } -static __init u32 build_uimm(u32 arg) +static u32 __init build_uimm(u32 arg) { if (arg & ~IMM_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -241,7 +241,7 @@ static __init u32 build_uimm(u32 arg) return arg & IMM_MASK; } -static __init u32 build_bimm(s32 arg) +static u32 __init build_bimm(s32 arg) { if (arg > 0x1ffff || arg < -0x20000) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -252,7 +252,7 @@ static __init u32 build_bimm(s32 arg) return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); } -static __init u32 build_jimm(u32 arg) +static u32 __init build_jimm(u32 arg) { if (arg & ~((JIMM_MASK) << 2)) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -260,7 +260,7 @@ static __init u32 build_jimm(u32 arg) return (arg >> 2) & JIMM_MASK; } -static __init u32 build_func(u32 arg) +static u32 __init build_func(u32 arg) { if (arg & ~FUNC_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -268,7 +268,7 @@ static __init u32 build_func(u32 arg) return arg & FUNC_MASK; } -static __init u32 build_set(u32 arg) +static u32 __init build_set(u32 arg) { if (arg & ~SET_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -315,69 +315,69 @@ static void __init build_insn(u32 **buf, enum opcode opc, ...) } #define I_u1u2u3(op) \ - static inline void __init i##op(u32 **buf, unsigned int a, \ + static inline void i##op(u32 **buf, unsigned int a, \ unsigned int b, unsigned int c) \ { \ build_insn(buf, insn##op, a, b, c); \ } #define I_u2u1u3(op) \ - static inline void __init i##op(u32 **buf, unsigned int a, \ + static inline void i##op(u32 **buf, unsigned int a, \ unsigned int b, unsigned int c) \ { \ build_insn(buf, insn##op, b, a, c); \ } #define I_u3u1u2(op) \ - static inline void __init i##op(u32 **buf, unsigned int a, \ + static inline void i##op(u32 **buf, unsigned int a, \ unsigned int b, unsigned int c) \ { \ build_insn(buf, insn##op, b, c, a); \ } #define I_u1u2s3(op) \ - static inline void __init i##op(u32 **buf, unsigned int a, \ + static inline void i##op(u32 **buf, unsigned int a, \ unsigned int b, signed int c) \ { \ build_insn(buf, insn##op, a, b, c); \ } #define I_u2s3u1(op) \ - static inline void __init i##op(u32 **buf, unsigned int a, \ + static inline void i##op(u32 **buf, unsigned int a, \ signed int b, unsigned int c) \ { \ build_insn(buf, insn##op, c, a, b); \ } #define I_u2u1s3(op) \ - static inline void __init i##op(u32 **buf, unsigned int a, \ + static inline void i##op(u32 **buf, unsigned int a, \ unsigned int b, signed int c) \ { \ build_insn(buf, insn##op, b, a, c); \ } #define I_u1u2(op) \ - static inline void __init i##op(u32 **buf, unsigned int a, \ + static inline void i##op(u32 **buf, unsigned int a, \ unsigned int b) \ { \ build_insn(buf, insn##op, a, b); \ } #define I_u1s2(op) \ - static inline void __init i##op(u32 **buf, unsigned int a, \ + static inline void i##op(u32 **buf, unsigned int a, \ signed int b) \ { \ build_insn(buf, insn##op, a, b); \ } #define I_u1(op) \ - static inline void __init i##op(u32 **buf, unsigned int a) \ + static inline void i##op(u32 **buf, unsigned int a) \ { \ build_insn(buf, insn##op, a); \ } #define I_0(op) \ - static inline void __init i##op(u32 **buf) \ + static inline void i##op(u32 **buf) \ { \ build_insn(buf, insn##op); \ } @@ -457,7 +457,7 @@ struct label { enum label_id lab; }; -static __init void build_label(struct label **lab, u32 *addr, +static void __init build_label(struct label **lab, u32 *addr, enum label_id l) { (*lab)->addr = addr; @@ -526,34 +526,34 @@ L_LA(_r3000_write_probe_fail) #define i_ehb(buf) i_sll(buf, 0, 0, 3) #ifdef CONFIG_64BIT -static __init int __maybe_unused in_compat_space_p(long addr) +static int __init __maybe_unused in_compat_space_p(long addr) { /* Is this address in 32bit compat space? */ return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); } -static __init int __maybe_unused rel_highest(long val) +static int __init __maybe_unused rel_highest(long val) { return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; } -static __init int __maybe_unused rel_higher(long val) +static int __init __maybe_unused rel_higher(long val) { return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; } #endif -static __init int rel_hi(long val) +static int __init rel_hi(long val) { return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; } -static __init int rel_lo(long val) +static int __init rel_lo(long val) { return ((val & 0xffff) ^ 0x8000) - 0x8000; } -static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) +static void __init i_LA_mostly(u32 **buf, unsigned int rs, long addr) { #ifdef CONFIG_64BIT if (!in_compat_space_p(addr)) { @@ -571,7 +571,7 @@ static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) i_lui(buf, rs, rel_hi(addr)); } -static __init void __maybe_unused i_LA(u32 **buf, unsigned int rs, +static void __init __maybe_unused i_LA(u32 **buf, unsigned int rs, long addr) { i_LA_mostly(buf, rs, addr); @@ -589,7 +589,7 @@ struct reloc { enum label_id lab; }; -static __init void r_mips_pc16(struct reloc **rel, u32 *addr, +static void __init r_mips_pc16(struct reloc **rel, u32 *addr, enum label_id l) { (*rel)->addr = addr; @@ -614,7 +614,7 @@ static inline void __resolve_relocs(struct reloc *rel, struct label *lab) } } -static __init void resolve_relocs(struct reloc *rel, struct label *lab) +static void __init resolve_relocs(struct reloc *rel, struct label *lab) { struct label *l; @@ -624,7 +624,7 @@ static __init void resolve_relocs(struct reloc *rel, struct label *lab) __resolve_relocs(rel, l); } -static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end, +static void __init move_relocs(struct reloc *rel, u32 *first, u32 *end, long off) { for (; rel->lab != label_invalid; rel++) @@ -632,7 +632,7 @@ static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end, rel->addr += off; } -static __init void move_labels(struct label *lab, u32 *first, u32 *end, +static void __init move_labels(struct label *lab, u32 *first, u32 *end, long off) { for (; lab->lab != label_invalid; lab++) @@ -640,7 +640,7 @@ static __init void move_labels(struct label *lab, u32 *first, u32 *end, lab->addr += off; } -static __init void copy_handler(struct reloc *rel, struct label *lab, +static void __init copy_handler(struct reloc *rel, struct label *lab, u32 *first, u32 *end, u32 *target) { long off = (long)(target - first); @@ -651,7 +651,7 @@ static __init void copy_handler(struct reloc *rel, struct label *lab, move_labels(lab, first, end, off); } -static __init int __maybe_unused insn_has_bdelay(struct reloc *rel, +static int __init __maybe_unused insn_has_bdelay(struct reloc *rel, u32 *addr) { for (; rel->lab != label_invalid; rel++) { @@ -743,11 +743,11 @@ il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) * We deliberately chose a buffer size of 128, so we won't scribble * over anything important on overflow before we panic. */ -static __initdata u32 tlb_handler[128]; +static u32 tlb_handler[128] __initdata; /* simply assume worst case size for labels and relocs */ -static __initdata struct label labels[128]; -static __initdata struct reloc relocs[128]; +static struct label labels[128] __initdata; +static struct reloc relocs[128] __initdata; /* * The R3000 TLB handler is simple. @@ -801,7 +801,7 @@ static void __init build_r3000_tlb_refill_handler(void) * other one.To keep things simple, we first assume linear space, * then we relocate it to the final handler layout as needed. */ -static __initdata u32 final_handler[64]; +static u32 final_handler[64] __initdata; /* * Hazards @@ -825,7 +825,7 @@ static __initdata u32 final_handler[64]; * * As if we MIPS hackers wouldn't know how to nop pipelines happy ... */ -static __init void __maybe_unused build_tlb_probe_entry(u32 **p) +static void __init __maybe_unused build_tlb_probe_entry(u32 **p) { switch (current_cpu_type()) { /* Found by experiment: R4600 v2.0 needs this, too. */ @@ -849,7 +849,7 @@ static __init void __maybe_unused build_tlb_probe_entry(u32 **p) */ enum tlb_write_entry { tlb_random, tlb_indexed }; -static __init void build_tlb_write_entry(u32 **p, struct label **l, +static void __init build_tlb_write_entry(u32 **p, struct label **l, struct reloc **r, enum tlb_write_entry wmode) { @@ -993,7 +993,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, * TMP and PTR are scratch. * TMP will be clobbered, PTR will hold the pmd entry. */ -static __init void +static void __init build_get_pmde64(u32 **p, struct label **l, struct reloc **r, unsigned int tmp, unsigned int ptr) { @@ -1054,7 +1054,7 @@ build_get_pmde64(u32 **p, struct label **l, struct reloc **r, * BVADDR is the faulting address, PTR is scratch. * PTR will hold the pgd for vmalloc. */ -static __init void +static void __init build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, unsigned int bvaddr, unsigned int ptr) { @@ -1118,7 +1118,7 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, * TMP and PTR are scratch. * TMP will be clobbered, PTR will hold the pgd entry. */ -static __init void __maybe_unused +static void __init __maybe_unused build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) { long pgdc = (long)pgd_current; @@ -1153,7 +1153,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) #endif /* !CONFIG_64BIT */ -static __init void build_adjust_context(u32 **p, unsigned int ctx) +static void __init build_adjust_context(u32 **p, unsigned int ctx) { unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); @@ -1179,7 +1179,7 @@ static __init void build_adjust_context(u32 **p, unsigned int ctx) i_andi(p, ctx, ctx, mask); } -static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) +static void __init build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) { /* * Bug workaround for the Nevada. It seems as if under certain @@ -1204,7 +1204,7 @@ static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) i_ADDU(p, ptr, ptr, tmp); /* add in offset */ } -static __init void build_update_entries(u32 **p, unsigned int tmp, +static void __init build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) { /* -- cgit v0.10.2