From 45f784412aae66d9254685374721a3cad4a106b6 Mon Sep 17 00:00:00 2001 From: Chenhui Zhao Date: Mon, 9 Mar 2015 10:48:28 +0800 Subject: arm: ls1021a: enable WoL by enabling error interrupts of eTSEC1 In deep sleep case, when enabling Wake-on-LAN feature, receiving a magic packet will trigger an error interrupt on eTSEC1. Therefore, enable these interrupts in setting PMC interrupt registers for deep sleep. Signed-off-by: Chenhui Zhao Change-Id: I3a2ca3e98e261d1c5c2f422203943959b871d7bd Reviewed-on: http://git.am.freescale.net:8181/32216 Tested-by: Review Code-CDREVIEW Reviewed-by: Yuantian Tang Reviewed-by: Zhengxiong Jin diff --git a/arch/arm/mach-imx/pm-ls1.c b/arch/arm/mach-imx/pm-ls1.c index f239b67..b8bfdb5 100644 --- a/arch/arm/mach-imx/pm-ls1.c +++ b/arch/arm/mach-imx/pm-ls1.c @@ -42,6 +42,8 @@ #define CCSR_SCFG_PMCINTECR_IRQ1 0x04000000 #define CCSR_SCFG_PMCINTECR_ETSECRXG0 0x00800000 #define CCSR_SCFG_PMCINTECR_ETSECRXG1 0x00400000 +#define CCSR_SCFG_PMCINTECR_ETSECERRG0 0x00080000 +#define CCSR_SCFG_PMCINTECR_ETSECERRG1 0x00040000 #define CCSR_SCFG_PMCINTLECR 0x164 #define CCSR_SCFG_PMCINTSR 0x168 #define CCSR_SCFG_SPARECR2 0x504 @@ -155,7 +157,9 @@ static void ls1_setup_pmc_int(void) pmcintecr = 0; if (ippdexpcr0 & CCSR_RCPM_IPPDEXPCR0_ETSEC) pmcintecr |= CCSR_SCFG_PMCINTECR_ETSECRXG0 | - CCSR_SCFG_PMCINTECR_ETSECRXG1; + CCSR_SCFG_PMCINTECR_ETSECRXG1 | + CCSR_SCFG_PMCINTECR_ETSECERRG0 | + CCSR_SCFG_PMCINTECR_ETSECERRG1; if (ippdexpcr0 & CCSR_RCPM_IPPDEXPCR0_GPIO) pmcintecr |= CCSR_SCFG_PMCINTECR_GPIO; -- cgit v0.10.2