From 2848b94e74a3da59911d41ee727ef5c2cead96c0 Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Tue, 31 Dec 2013 15:33:21 +0800 Subject: ASoC: fsl_sai: Fix one bug for hardware limitation. This is maybe one bug or a limitation of the hardware that the {T,R}CR2's Synchronous Mode bits must be set as late as possible, or the SAI device maybe hanged up, and there has not any explaination about this limitation in the SAI Data Sheet. And the {T,R}CR2's Synchronous Mode bits must be set at the same time whether for Tx or Rx stream. Signed-off-by: Xiubo Li Signed-off-by: Mark Brown --- This patch is pulled back from upstream: commit 496a39d9ec238569fac6daceac8f5420c5edc2f1 Change-Id: Ib09d153b20251254277f3efacdc5d5b5d8f8425b Reviewed-on: http://git.am.freescale.net:8181/19748 Tested-by: Review Code-CDREVIEW Reviewed-by: Zhengxiong Jin diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index ba4d9c8..ecd0104 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -145,7 +145,6 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_I2S: val_cr4 |= FSL_SAI_CR4_FSE; - val_cr4 |= FSL_SAI_CR4_FSP; break; default: return -EINVAL; @@ -185,9 +184,6 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, return -EINVAL; } - if (fsl_dir == FSL_FMT_RECEIVER) - val_cr2 |= FSL_SAI_CR2_SYNC; - sai_writel(sai, val_cr2, sai->base + reg_cr2); sai_writel(sai, val_cr4, sai->base + reg_cr4); @@ -253,6 +249,7 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, val_cr5 |= FSL_SAI_CR5_WNW(word_width); val_cr5 |= FSL_SAI_CR5_W0W(word_width); + val_cr5 &= ~FSL_SAI_CR5_FBT_MASK; if (sai->big_endian_data) val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); else @@ -272,7 +269,15 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *cpu_dai) { struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); - u32 tcsr, rcsr, val_cr3, reg_cr3; + u32 tcsr, rcsr, val_cr2, val_cr3, reg_cr3; + + val_cr2 = sai_readl(sai, sai->base + FSL_SAI_TCR2); + val_cr2 &= ~FSL_SAI_CR2_SYNC; + sai_writel(sai, val_cr2, sai->base + FSL_SAI_TCR2); + + val_cr2 = sai_readl(sai, sai->base + FSL_SAI_RCR2); + val_cr2 |= FSL_SAI_CR2_SYNC; + sai_writel(sai, val_cr2, sai->base + FSL_SAI_RCR2); tcsr = sai_readl(sai, sai->base + FSL_SAI_TCSR); rcsr = sai_readl(sai, sai->base + FSL_SAI_RCSR); -- cgit v0.10.2