/*
 * Copyright 2013-2015 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

/dts-v1/;
#include "ls1021a.dtsi"

/ {
	model = "LS1021A TWR Board";

	aliases {
		enet2_rgmii_phy = &rgmii_phy1;
		enet0_sgmii_phy = &sgmii_phy2;
		enet1_sgmii_phy = &sgmii_phy0;
	};

	clocks {
		sys_mclk: clock {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24576000>;
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_3p3v: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "3P3V";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};
	};

	sound {
		compatible = "fsl,vf610-sgtl5000";
		simple-audio-card,name = "FSL-VF610-TWR-BOARD";
		simple-audio-card,routing =
			"MIC_IN", "Microphone Jack",
			"Microphone Jack", "Mic Bias",
			"LINE_IN", "Line In Jack",
			"Headphone Jack", "HP_OUT",
			"Speaker Ext", "LINE_OUT";

		simple-audio-card,cpu = <&sai1>;

		simple-audio-card,codec = <&codec>;
	};
};

&dcu0 {
	display = <&display>;
	status = "okay";

	display: display@0 {
		bits-per-pixel = <24>;

		display-timings {
			native-mode = <&timing0>;
			timing0: nl4827hc19 {
				clock-frequency = <10870000>;
				hactive = <480>;
				vactive = <272>;
				hback-porch = <2>;
				hfront-porch = <2>;
				vback-porch = <2>;
				vfront-porch = <2>;
				hsync-len = <41>;
				vsync-len = <4>;
				hsync-active = <1>;
				vsync-active = <1>;
			};
		};
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&enet0 {
	tbi-handle = <&tbi1>;
	phy-handle = <&sgmii_phy2>;
	phy-connection-type = "sgmii";
	status = "okay";
};

&enet1 {
	tbi-handle = <&tbi1>;
	phy-handle = <&sgmii_phy0>;
	phy-connection-type = "sgmii";
	status = "okay";
};

&enet2 {
	phy-handle = <&rgmii_phy1>;
	phy-connection-type = "rgmii-id";
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&i2c1 {
	status = "okay";
	codec: sgtl5000@a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		VDDA-supply = <&reg_3p3v>;
		VDDIO-supply = <&reg_3p3v>;
		clocks = <&sys_mclk 1>;
	};

	hdmi: sii9022a@39 {
	      compatible = "fsl,sii902x";
	      reg = <0x39>;
	      interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
	};
};

&i2c2 {
	status = "okay";
	monitor: ltc2945@67 {
		reg = <0x67>;
	};
};

&ifc {
	status = "okay";
	#address-cells = <2>;
	#size-cells = <1>;
	/* NOR, and CPLD on board */
	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
		0x2 0x0 0x0 0x7fb00000 0x00000100>;

		nor@0,0 {
			compatible = "cfi-flash";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x0 0x0 0x8000000>;
			bank-width = <2>;
			device-width = <1>;

			partition@0 {
				/* 128KB for rcw */
				reg = <0x00000000 0x0020000>;
				label = "NOR bank0 RCW Image";
			};

			partition@20000 {
				/* 896KB for DTB */
				reg = <0x00020000 0x000e0000>;
				label = "NOR DTB Image";
			};

			partition@100000 {
				/* 1MB for bank0 u-boot Image */
				reg = <0x00100000 0x00100000>;
				label = "NOR bank0 u-boot Image";
			};

			partition@200000 {
				/* 8 MB for Linux Kernel Image */
				reg = <0x00200000 0x00800000>;
				label = "NOR Linux Kernel Image";
			};

			partition@a00000 {
				/* 54MB for Ramdisk Root File System */
				reg = <0x00a00000 0x03600000>;
				label = "NOR Ramdisk Root File System Image";
			};

			partition@4000000 {
				/* 128KB for bank4 RCW Image */
				reg = <0x04000000 0x00020000>;
				label = "NOR bank4 RCW Image";
			};

			partition@4100000 {
				/* 1MB for bank4 u-boot Image */
				reg = <0x04100000 0x00100000>;
				label = "NOR bank0 u-boot Image";
			};

			partition@4200000 {
				/* 62MB JFFS2 ROOT File System Image */
				reg = <0x04200000 0x03e00000>;
				label = "NOR JFFS2 ROOT File System Image";
			};
		};
};

&lpuart0 {
	status = "okay";
};

&mdio0 {
	sgmii_phy0: ethernet-phy@0 {
		reg = <0x0>;
	};
	rgmii_phy1: ethernet-phy@1 {
		reg = <0x1>;
	};
	sgmii_phy2: ethernet-phy@2 {
		reg = <0x2>;
	};
	tbi1: tbi-phy@1f {
		reg = <0x1f>;
		device_type = "tbi-phy";
	};
};

&uqe {
	tdma: ucc@2000 {
		compatible = "fsl,ucc-tdm";
		rx-clock-name = "clk8";
		tx-clock-name = "clk9";
		fsl,rx-sync-clock = "rsync_pin";
		fsl,tx-sync-clock = "tsync_pin";
		fsl,tx-timeslot = <0xfffffffe>;
		fsl,rx-timeslot = <0xfffffffe>;
		fsl,tdm-framer-type = "e1";
		fsl,tdm-mode = "normal";
		fsl,tdm-id = <0>;
		fsl,siram-entry-id = <0>;
	};

	serial: ucc@2200 {
		device_type = "serial";
		compatible = "ucc_uart";
		port-number = <1>;
		rx-clock-name = "brg2";
		tx-clock-name = "brg2";
	};
};

&pwm6 {
	status = "okay";
};

&pwm7 {
	status = "okay";
};

&qspi {
	num-cs = <2>;
	status = "okay";

	qflash0: n25q128a13@0 {
		compatible = "micron,n25q128a13";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <20000000>;
		reg = <0>;
	};
};

&sai1 {
	status = "okay";
};