/*
 * Copyright 2013-2014 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include "skeleton64.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "fsl,ls1021a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &lpuart0;
		serial1 = &lpuart1;
		serial2 = &lpuart2;
		serial3 = &lpuart3;
		serial4 = &lpuart4;
		serial5 = &lpuart5;
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		sysclk = &sysclk;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x20000000>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@f00 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0xf00>;
		};

		cpu@f01 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0xf01>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = 	<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		interrupt-parent = <&gic>;
		ranges;

		gic: interrupt-controller@1400000 {
			compatible = "arm,cortex-a15-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x0 0x1401000 0x0 0x1000>,
				<0x0 0x1402000 0x0 0x1000>,
				<0x0 0x1404000 0x0 0x2000>,
				<0x0 0x1406000 0x0 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;

		};

		ifc: ifc@1530000 {
			compatible = "fsl,ifc", "simple-bus";
			reg = <0x0 0x1530000 0x0 0x10000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
		};

		dcfg: dcfg@1ee0000 {
			compatible = "fsl,ls1021a-dcfg";
			reg = <0x0 0x1ee0000 0x0 0x10000>;
		};

		qspi: quadspi@1550000 {
			compatible = "fsl,vf610-qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x1550000 0x0 0x10000>;
			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "qspi_en", "qspi";
			clocks = <&platform_clk 1>, <&platform_clk 1>;
			big-endian;
			amba-base = <0x40000000>;
			status = "disabled";
		};

		esdhc: esdhc@1560000 {
			compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
			reg = <0x0 0x1560000 0x0 0x10000>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <0>;
			voltage-ranges = <1800 1800 3300 3300>;
			sdhci,auto-cmd12;
			big-endian;
			bus-width = <4>;
			status = "disabled";
		};

		scfg: scfg@1570000 {
			compatible = "fsl,ls1021a-scfg", "syscon";
			reg = <0x0 0x1570000 0x0 0x10000>;
			big-endian;
		};

		crypto: crypto@1700000 {
			compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
			fsl,sec-era = <4>;
			#address-cells = <1>;
			#size-cells = <1>;
			reg		 = <0x0 0x1700000 0x0 0x100000>;
			ranges		 = <0x0 0x0 0x1700000 0x100000>;
			interrupts	 = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;

			sec_jr0: jr@10000 {
				compatible = "fsl,sec-v5.3-job-ring",
				     "fsl,sec-v5.0-job-ring",
				     "fsl,sec-v4.0-job-ring";
				reg = <0x10000 0x10000>;
				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr1: jr@20000 {
				compatible = "fsl,sec-v5.3-job-ring",
				     "fsl,sec-v5.0-job-ring",
				     "fsl,sec-v4.0-job-ring";
				reg = <0x20000 0x10000>;
				interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr2: jr@30000 {
				compatible = "fsl,sec-v5.3-job-ring",
				     "fsl,sec-v5.0-job-ring",
				     "fsl,sec-v4.0-job-ring";
				reg = <0x30000 0x10000>;
				interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr3: jr@40000 {
				compatible = "fsl,sec-v5.3-job-ring",
				     "fsl,sec-v5.0-job-ring",
				     "fsl,sec-v4.0-job-ring";
				reg = <0x40000 0x10000>;
				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			};

		};

		clockgen: clocking@1ee1000 {
			compatible = "fsl,ls1021a-clockgen";
			reg = <0x0 0x1ee1000 0x0 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			sysclk: sysclk {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <100000000>;
				clock-output-names = "sysclk";
			};

			cga_pll1: pll1@800 {
				compatible = "fsl,core-pll-clock";
				#clock-cells = <1>;
				reg = <0x800>;
				clocks = <&sysclk>;
				clock-output-names = "cga-pll1", "cga-pll1-div2",
						"cga-pll1-div3", "cga-pll1-div4";
			};

			cga_pll2: pll2@820 {
				compatible = "fsl,core-pll-clock";
				#clock-cells = <1>;
				reg = <0x820>;
				clocks = <&sysclk>;
				clock-output-names = "cga-pll2", "cga-pll2-div2",
						"cga-pll2-div3", "cga-pll2-div4";
			};

			platform_clk: pll@c00 {
				compatible = "fsl,core-pll-clock";
				#clock-cells = <1>;
				reg = <0xc00>;
				clocks = <&sysclk>;
				clock-output-names = "platform-clk", "platform-clk-div2";
			};


			cluster1_clk: clk0c0@0 {
				compatible = "fsl,core-mux-clock";
				#clock-cells = <1>;
				reg = <0x0>;
				clock-names = "pll1cga", "pll1cga-div2";
				clocks = <&cga_pll1 0>, <&cga_pll1 2>;
				clock-output-names = "cluster1-clk";

			};

		};

		dspi0: dspi@2100000 {
			compatible = "fsl,vf610-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2100000 0x0 0x10000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "dspi";
			clocks = <&platform_clk 1>;
			spi-num-chipselects = <5>;
			big-endian;
			status = "disabled";
		};

		dspi1: dspi@2110000 {
			compatible = "fsl,vf610-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2110000 0x0 0x10000>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "dspi";
			clocks = <&platform_clk 1>;
			spi-num-chipselects = <5>;
			big-endian;
			status = "disabled";
		};

		i2c0: i2c@2180000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2180000 0x0 0x10000>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "i2c";
			clocks = <&platform_clk 1>;
			status = "disabled";
		};

		i2c1: i2c@2190000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2190000 0x0 0x10000>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "i2c";
			clocks = <&platform_clk 1>;
			status = "disabled";
		};

		i2c2: i2c@21a0000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21a0000 0x0 0x10000>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "i2c";
			clocks = <&platform_clk 1>;
			status = "disabled";
		};

		duart0: serial@21c0500 {
			compatible = "fsl,16550-FIFO64";
			reg = <0x0 0x21c0500 0x0 0x100>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <0>;
			fifo-size = <63>;
			status = "disabled";
		};

		duart1: serial@21c0600 {
			compatible = "fsl,16550-FIFO64";
			reg = <0x0 0x21c0600 0x0 0x100>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <0>;
			fifo-size = <63>;
			status = "disabled";
		};

		duart2: serial@21d0500 {
			compatible = "fsl,16550-FIFO64";
			reg = <0x0 0x21d0500 0x0 0x100>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <0>;
			fifo-size = <63>;
			status = "disabled";
		};

		duart3: serial@21d0600 {
			compatible = "fsl,16550-FIFO64";
			reg = <0x0 0x21d0600 0x0 0x100>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <0>;
			fifo-size = <63>;
			status = "disabled";
		};

		uqe: uqe@2400000 {
			#address-cells = <1>;
			#size-cells = <1>;
			device_type = "qe";
			compatible = "fsl,qe", "simple-bus";
			ranges = <0x0 0x0 0x2400000 0x40000>;
			reg = <0x0 0x2400000 0x0 0x480>;
			brg-frequency = <100000000>;
			bus-frequency = <200000000>;

			fsl,qe-num-riscs = <1>;
			fsl,qe-num-snums = <28>;

			qeic: qeic@80 {
				compatible = "fsl,qe-ic";
				reg = <0x80 0x80>;
				#address-cells = <0>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupts = <0 109 0x04 0 109 0x04>;
			};

			si1: si@700 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,qe-si";
				reg = <0x700 0x80>;
			};

			siram1: siram@1000 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "fsl,qe-siram";
				reg = <0x1000 0x800>;
			};

			ucc@2000 {
				cell-index = <1>;
				reg = <0x2000 0x200>;
				interrupts = <32>;
				interrupt-parent = <&qeic>;
			};

			ucc@2200 {
				cell-index = <3>;
				reg = <0x2200 0x200>;
				interrupts = <34>;
				interrupt-parent = <&qeic>;
			};

			muram@10000 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "fsl,qe-muram", "fsl,cpm-muram";
				ranges = <0x0 0x10000 0x6000>;

				data-only@0 {
					compatible = "fsl,qe-muram-data",
					"fsl,cpm-muram-data";
					reg = <0x0 0x6000>;
				};
			};
		};

		lpuart0: serial@2950000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2950000 0x0 0x1000>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysclk>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart1: serial@2960000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2960000 0x0 0x1000>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&platform_clk 1>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart2: serial@2970000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2970000 0x0 0x1000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&platform_clk 1>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart3: serial@2980000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2980000 0x0 0x1000>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&platform_clk 1>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart4: serial@2990000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2990000 0x0 0x1000>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&platform_clk 1>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart5: serial@29a0000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x29a0000 0x0 0x1000>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&platform_clk 1>;
			clock-names = "ipg";
			status = "disabled";
		};

		ftm0: ftm0@29d0000 {
			compatible = "fsl,ftm-alarm";
			reg = <0x0 0x29d0000 0x0 0x10000>;
			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
			status = "disabled";
		};

		pwm3: ftm@2a00000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x2a00000 0x0 0x10000>;
			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "ftm_sys", "ftm_ext",
				"ftm_fix", "ftm_cnt_clk_en";
			clocks = <&platform_clk 1>, <&platform_clk 1>,
				<&platform_clk 1>, <&platform_clk 1>;
			big-endian;
			status = "disabled";
		};

		pwm6: ftm@2a30000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x2a30000 0x0 0x10000>;
			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "ftm_sys", "ftm_ext",
				"ftm_fix", "ftm_cnt_clk_en";
			clocks = <&platform_clk 1>, <&platform_clk 1>,
				<&platform_clk 1>, <&platform_clk 1>;
			big-endian;
			status = "disabled";
		};

		pwm7: ftm@2a40000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x2a40000 0x0 0x10000>;
			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "ftm_sys", "ftm_ext",
				"ftm_fix", "ftm_cnt_clk_en";
			clocks = <&platform_clk 1>, <&platform_clk 1>,
				<&platform_clk 1>, <&platform_clk 1>;
			big-endian;
			status = "disabled";
		};

		wdog0: wdog@2ad0000 {
			compatible = "fsl,imx21-wdt";
			reg = <0x0 0x2ad0000 0x0 0x10000>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&platform_clk 1>;
			clock-names = "wdog";
			big-endian;
		};

		sai2: sai@2b60000 {
			compatible = "fsl,vf610-sai";
			reg = <0x0 0x2b60000 0x0 0x10000>;
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&platform_clk 1>;
			clock-names = "sai";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 45>,
				<&edma0 1 44>;
			big-endian-regs;
			status = "disabled";
		};

		edma0: edma@2c00000 {
			#dma-cells = <2>;
			compatible = "fsl,vf610-edma";
			reg = <0x0 0x2c00000 0x0 0x10000>,
				<0x0 0x2c10000 0x0 0x10000>,
				<0x0 0x2c20000 0x0 0x10000>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "edma-tx", "edma-err";
			dma-channels = <32>;
			big-endian;
			clock-names = "dmamux0", "dmamux1";
			clocks = <&platform_clk 1>,
				<&platform_clk 1>;
		};

		dcu0: dcu@2ce0000 {
			compatible = "fsl,ls1021a-dcu";
			reg = <0x0 0x2ce0000 0x0 0x10000>;
			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&platform_clk 0>;
			clock-names = "dcu";
			scfg-controller = <&scfg>;
			big-endian;
			status = "disabled";
		};

		mdio0: mdio@2d24000 {
			compatible = "gianfar";
			device_type = "mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2d24000 0x0 0x4000>;
		};

		enet0: ethernet@2d10000 {
			compatible = "fsl,etsec2";
			device_type = "network";
			#address-cells = <2>;
			#size-cells = <2>;
			interrupt-parent = <&gic>;
			model = "eTSEC";
			fsl,dma-endian-le;
			fsl,num_rx_queues = <0x1>;
			fsl,num_tx_queues = <0x1>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			ranges;

			queue-group@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x0 0x2d10000 0x0 0x8000>;
				fsl,rx-bit-map = <0xff>;
				fsl,tx-bit-map = <0xff>;
				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
			};

		};

		enet1: ethernet@2d50000 {
			compatible = "fsl,etsec2";
			device_type = "network";
			#address-cells = <2>;
			#size-cells = <2>;
			interrupt-parent = <&gic>;
			model = "eTSEC";
			fsl,dma-endian-le;
			fsl,num_rx_queues = <0x1>;
			fsl,num_tx_queues = <0x1>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			ranges;

			queue-group@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x0 0x2d50000 0x0 0x8000>;
				fsl,rx-bit-map = <0xff>;
				fsl,tx-bit-map = <0xff>;
				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
			};

		};

		enet2: ethernet@2d90000 {
			compatible = "fsl,etsec2";
			device_type = "network";
			#address-cells = <2>;
			#size-cells = <2>;
			interrupt-parent = <&gic>;
			model = "eTSEC";
			fsl,dma-endian-le;
			fsl,num_rx_queues = <0x1>;
			fsl,num_tx_queues = <0x1>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			ranges;

			queue-group@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x0 0x2d90000 0x0 0x8000>;
				fsl,rx-bit-map = <0xff>;
				fsl,tx-bit-map = <0xff>;
				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		usb@8600000 {
			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
			reg = <0x0 0x8600000 0x0 0x1000>;
			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "host";
			phy_type = "ulpi";
		};

		usb3@3100000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x3100000 0x0 0x10000>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "host";
		};

		pcie@3400000 {
			compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
			reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, /* MSI interrupt */
				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
			interrupt-names = "intr", "msi", "pme";
			fsl,pcie-scfg = <&scfg 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-lanes = <4>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
		};

		pcie@3500000 {
			compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
			reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "intr", "msi", "pme";
			fsl,pcie-scfg = <&scfg 1>;
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-lanes = <2>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	dcsr {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,dcsr", "simple-bus";

		ranges = <0x0 0x0 0x20000000 0x1000000>;

		dcsr-epu@0 {
			compatible = "fsl,ls1021a-dcsr-epu";
			reg = <0x0 0x10000>;
		};

		dcsr-gdi@100000 {
			compatible = "fsl,ls1021a-dcsr-gdi";
			reg = <0x100000 0x10000>;
		};

		dcsr-dddi@120000 {
			compatible = "fsl,ls1021a-dcsr-dddi";
			reg = <0x120000 0x10000>;
		};

		dcsr-dcfg@220000 {
			compatible = "fsl,ls1021a-dcsr-dcfg";
			reg = <0x220000 0x1000>;
		};

		dcsr-clock@221000 {
			compatible = "fsl,ls1021a-dcsr-clock";
			reg = <0x221000 0x1000>;
		};

		dcsr-rcpm@222000 {
			compatible = "fsl,ls1021a-dcsr-rcpm";
			reg = <0x222000 0x1000 0x223000 0x1000>;
		};

		dcsr-ccp@225000 {
			compatible = "fsl,ls1021a-dcsr-ccp";
			reg = <0x225000 0x1000>;
		};

		dcsr-fusectrl@226000 {
			compatible = "fsl,ls1021a-dcsr-fusectrl";
			reg = <0x226000 0x1000>;
		};

		dcsr-dap@300000 {
			compatible = "fsl,ls1021a-dcsr-dap";
			reg = <0x300000 0x10000>;
		};

		dcsr-cstf@350000 {
			compatible = "fsl,ls1021a-dcsr-cstf";
			reg = <0x350000 0x1000 0x3a7000 0x1000>;
		};

		dcsr-a7rom@360000 {
			compatible = "fsl,ls1021a-dcsr-a7rom";
			reg = <0x360000 0x10000>;
		};

		dcsr-a7cpu@370000 {
			compatible = "fsl,ls1021a-dcsr-a7cpu";
			reg = <0x370000 0x8000>;
		};

		dcsr-a7cti@378000 {
			compatible = "fsl,ls1021a-dcsr-a7cti";
			reg = <0x378000 0x4000>;
		};

		dcsr-etm@37c000 {
			compatible = "fsl,ls1021a-dcsr-etm";
			reg = <0x37c000 0x1000 0x37d000 0x3000>;
		};

		dcsr-hugorom@3a0000 {
			compatible = "fsl,ls1021a-dcsr-hugorom";
			reg = <0x3a0000 0x1000>;
		};

		dcsr-etf@3a1000 {
			compatible = "fsl,ls1021a-dcsr-etf";
			reg = <0x3a1000 0x1000 0x3a2000 0x1000>;
		};

		dcsr-etr@3a3000 {
			compatible = "fsl,ls1021a-dcsr-etr";
			reg = <0x3a3000 0x1000>;
		};

		dcsr-cti@3a4000 {
			compatible = "fsl,ls1021a-dcsr-cti";
			reg = <0x3a4000 0x1000 0x3a5000 0x1000 0x3a6000 0x1000>;
		};

		dcsr-atbrepl@3a8000 {
			compatible = "fsl,ls1021a-dcsr-atbrepl";
			reg = <0x3a8000 0x1000>;
		};

		dcsr-tsgen-ctrl@3a9000 {
			compatible = "fsl,ls1021a-dcsr-tsgen-ctrl";
			reg = <0x3a9000 0x1000>;
		};

		dcsr-tsgen-read@3aa000 {
			compatible = "fsl,ls1021a-dcsr-tsgen-read";
			reg = <0x3aa000 0x1000>;
		};
	};
};