/*
 * P5040DS Device Tree Source
 *
 * Copyright 2012 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *	 notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *	 notice, this list of conditions and the following disclaimer in the
 *	 documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *	 names of its contributors may be used to endorse or promote products
 *	 derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * This software is provided by Freescale Semiconductor "as is" and any
 * express or implied warranties, including, but not limited to, the implied
 * warranties of merchantability and fitness for a particular purpose are
 * disclaimed. In no event shall Freescale Semiconductor be liable for any
 * direct, indirect, incidental, special, exemplary, or consequential damages
 * (including, but not limited to, procurement of substitute goods or services;
 * loss of use, data, or profits; or business interruption) however caused and
 * on any theory of liability, whether in contract, strict liability, or tort
 * (including negligence or otherwise) arising in any way out of the use of this
 * software, even if advised of the possibility of such damage.
 */

/include/ "fsl/p5040si-pre.dtsi"

/ {
	model = "fsl,P5040DS";
	compatible = "fsl,P5040DS";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&mpic>;

	aliases {
		ethernet0 = &fm1dtsec1;
		ethernet1 = &fm1dtsec2;
		ethernet2 = &fm1dtsec3;
		ethernet3 = &fm1dtsec4;
		ethernet4 = &fm1dtsec5;
		ethernet5 = &fm1tgec;
		ethernet6 = &fm2dtsec1;
		ethernet7 = &fm2dtsec2;
		ethernet8 = &fm2dtsec3;
		ethernet9 = &fm2dtsec4;
		ethernet10 = &fm2dtsec5;
		ethernet11 = &fm2tgec;

		phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c;
		phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d;
		phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e;
		phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f;

		phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c;
		phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d;
		phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e;
		phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f;

		phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c;
		phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d;
		phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e;
		phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f;

		phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c;
		phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d;
		phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e;
		phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f;

		hydra_rg = &hydra_rg;
		hydra_sg_slot2 = &hydra_sg_slot2;
		hydra_sg_slot3 = &hydra_sg_slot3;
		hydra_sg_slot5 = &hydra_sg_slot5;
		hydra_sg_slot6 = &hydra_sg_slot6;
		hydra_xg_slot1 = &hydra_xg_slot1;
		hydra_xg_slot2 = &hydra_xg_slot2;
	};

	memory {
		device_type = "memory";
	};

	dcsr: dcsr@f00000000 {
		ranges = <0x00000000 0xf 0x00000000 0x01008000>;
	};

	bportals: bman-portals@ff4000000 {
		ranges = <0x0 0xf 0xf4000000 0x200000>;
	};

	qportals: qman-portals@ff4200000 {
		ranges = <0x0 0xf 0xf4200000 0x200000>;
	};

	soc: soc@ffe000000 {
		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
		reg = <0xf 0xfe000000 0 0x00001000>;
		spi@110000 {
			flash@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "spansion,s25sl12801";
				reg = <0>;
				spi-max-frequency = <40000000>; /* input clock */
				partition@u-boot {
					label = "u-boot";
					reg = <0x00000000 0x00100000>;
					read-only;
				};
				partition@kernel {
					label = "kernel";
					reg = <0x00100000 0x00500000>;
					read-only;
				};
				partition@dtb {
					label = "dtb";
					reg = <0x00600000 0x00100000>;
					read-only;
				};
				partition@fs {
					label = "file system";
					reg = <0x00700000 0x00900000>;
				};
			};
		};

		i2c@118100 {
			eeprom@51 {
				compatible = "at24,24c256";
				reg = <0x51>;
			};
			eeprom@52 {
				compatible = "at24,24c256";
				reg = <0x52>;
			};
		};

		i2c@119100 {
			rtc@68 {
				compatible = "dallas,ds3232";
				reg = <0x68>;
				interrupts = <0x1 0x1 0 0>;
			};
			adt7461@4c {
				compatible = "adi,adt7461";
				reg = <0x4c>;
			};
		};

		fman0: fman@400000 {
			fm1dtsec1: ethernet@e0000 {
				tbi-handle = <&tbi0>;
				phy-connection-type = "sgmii";
			};

			mdio0: mdio@e1120 {
				tbi0: tbi-phy@8 {
					reg = <0x8>;
					device_type = "tbi-phy";
				};
			};

			fm1dtsec2: ethernet@e2000 {
				tbi-handle = <&tbi1>;
				phy-connection-type = "sgmii";
			};

			mdio@e3120 {
				tbi1: tbi-phy@8 {
					reg = <8>;
					device_type = "tbi-phy";
				};
			};

			fm1dtsec3: ethernet@e4000 {
				tbi-handle = <&tbi2>;
				phy-connection-type = "sgmii";
			};

			mdio@e5120 {
				tbi2: tbi-phy@8 {
					reg = <8>;
					device_type = "tbi-phy";
				};
			};

			fm1dtsec4: ethernet@e6000 {
				tbi-handle = <&tbi3>;
				phy-connection-type = "sgmii";
			};

			mdio@e7120 {
				#address-cells = <1>;
				#size-cells = <0>;
				tbi3: tbi-phy@8 {
					reg = <8>;
					device_type = "tbi-phy";
				};
			};

			fm1dtsec5: ethernet@e8000 {
				tbi-handle = <&tbi4>;
				phy-handle = <&phy_rgmii_0>;
				phy-connection-type = "rgmii";
			};

			mdio@e9120 {
				tbi4: tbi-phy@8 {
					reg = <8>;
					device_type = "tbi-phy";
				};
			};

			fm1tgec: ethernet@f0000 {
				phy-handle = <&phy_xgmii_slot_2>;
				phy-connection-type = "xgmii";
			};

			xmdio0: mdio@f1000 {
			};

		};

		fman1: fman@500000 {
			fm2dtsec1: ethernet@e0000 {
				tbi-handle = <&tbi5>;
				phy-connection-type = "sgmii";
			};

			mdio@e1120 {
				tbi5: tbi-phy@8 {
					reg = <8>;
					device_type = "tbi-phy";
				};
			};

			fm2dtsec2: ethernet@e2000 {
				tbi-handle = <&tbi6>;
				phy-connection-type = "sgmii";
			};

			mdio@e3120 {
				tbi6: tbi-phy@8 {
					reg = <8>;
					device_type = "tbi-phy";
				};
			};

			fm2dtsec3: ethernet@e4000 {
				tbi-handle = <&tbi7>;
				phy-connection-type = "sgmii";
			};

			mdio@e5120 {
				tbi7: tbi-phy@8 {
					reg = <8>;
					device_type = "tbi-phy";
				};
			};

			fm2dtsec4: ethernet@e6000 {
				tbi-handle = <&tbi8>;
				phy-connection-type = "sgmii";
			};

			mdio@e7120 {
				tbi8: tbi-phy@8 {
					reg = <8>;
					device_type = "tbi-phy";
				};
			};

			fm2dtsec5: ethernet@e8000 {
				tbi-handle = <&tbi9>;
				phy-handle = <&phy_rgmii_1>;
				phy-connection-type = "rgmii";
			};

			mdio@e9120 {
				tbi9: tbi-phy@8 {
					reg = <8>;
					device_type = "tbi-phy";
				};
			};

			fm2tgec: ethernet@f0000 {
				phy-handle = <&phy_xgmii_slot_1>;
				phy-connection-type = "xgmii";
			};
		};
	};

	lbc: localbus@ffe124000 {
		reg = <0xf 0xfe124000 0 0x1000>;
		ranges = <0 0 0xf 0xe8000000 0x08000000
			  2 0 0xf 0xffa00000 0x00040000
			  3 0 0xf 0xffdf0000 0x00008000>;

		flash@0,0 {
			compatible = "cfi-flash";
			reg = <0 0 0x08000000>;
			bank-width = <2>;
			device-width = <2>;
		};

		nand@2,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,elbc-fcm-nand";
			reg = <0x2 0x0 0x40000>;

			partition@0 {
				label = "NAND U-Boot Image";
				reg = <0x0 0x02000000>;
				read-only;
			};

			partition@2000000 {
				label = "NAND Root File System";
				reg = <0x02000000 0x10000000>;
			};

			partition@12000000 {
				label = "NAND Compressed RFS Image";
				reg = <0x12000000 0x08000000>;
			};

			partition@1a000000 {
				label = "NAND Linux Kernel Image";
				reg = <0x1a000000 0x04000000>;
			};

			partition@1e000000 {
				label = "NAND DTB Image";
				reg = <0x1e000000 0x01000000>;
			};

			partition@1f000000 {
				label = "NAND Writable User area";
				reg = <0x1f000000 0x01000000>;
			};
		};

		board-control@3,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
			reg = <3 0 0x30>;
			ranges = <0 3 0 0x30>;

			mdio-mux-emi1 {
				compatible = "mdio-mux-mmioreg", "mdio-mux";
				mdio-parent-bus = <&mdio0>;
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <9 1>; // BRDCFG1
				mux-mask = <0x78>; // EMI1

				/*
				 * Virtual MDIO for the two on-board RGMII
				 * ports.  The reg property is already correct.
				 */
				hydra_rg: rgmii-mdio@8 {
					status = "disabled";
					reg = <8>; /* EMI1_EN | 0 */
					#address-cells = <1>;
					#size-cells = <0>;

					phy_rgmii_0: ethernet-phy@0 {
						reg = <0x0>;
					};
					phy_rgmii_1: ethernet-phy@1 {
						reg = <0x1>;
					};
				};
				/*
				 * Virtual MDIO for the four-port SGMII cards.
				 */
				hydra_sg_slot2: sgmii-mdio@28 {
					reg = <0x28>; /* EMI1_EN | 0x20 */
					#address-cells = <1>;
					#size-cells = <0>;
					status = "disabled";

					phy_sgmii_slot2_1c: ethernet-phy@1c {
						reg = <0x1c>;
					};
					phy_sgmii_slot2_1d: ethernet-phy@1d {
						reg = <0x1d>;
					};
					phy_sgmii_slot2_1e: ethernet-phy@1e {
						reg = <0x1e>;
					};
					phy_sgmii_slot2_1f: ethernet-phy@1f {
						reg = <0x1f>;
					};
				};
				hydra_sg_slot3: sgmii-mdio@68 {
					reg = <0x68>; /* EMI1_EN | 0x60 */
					#address-cells = <1>;
					#size-cells = <0>;
					status = "disabled";

					phy_sgmii_slot3_1c: ethernet-phy@1c {
						reg = <0x1c>;
					};
					phy_sgmii_slot3_1d: ethernet-phy@1d {
						reg = <0x1d>;
					};
					phy_sgmii_slot3_1e: ethernet-phy@1e {
						reg = <0x1e>;
					};
					phy_sgmii_slot3_1f: ethernet-phy@1f {
						reg = <0x1f>;
					};
				};
				hydra_sg_slot5: sgmii-mdio@38 {
					reg = <0x38>; /* EMI1_EN | 0x30 */
					#address-cells = <1>;
					#size-cells = <0>;
					status = "disabled";

					phy_sgmii_slot5_1c: ethernet-phy@1c {
						reg = <0x1c>;
					};
					phy_sgmii_slot5_1d: ethernet-phy@1d {
						reg = <0x1d>;
					};
					phy_sgmii_slot5_1e: ethernet-phy@1e {
						reg = <0x1e>;
					};
					phy_sgmii_slot5_1f: ethernet-phy@1f {
						reg = <0x1f>;
					};
				};
				hydra_sg_slot6: sgmii-mdio@48 {
					reg = <0x48>; /* EMI1_EN | 0x40 */
					#address-cells = <1>;
					#size-cells = <0>;
					status = "disabled";

					phy_sgmii_slot6_1c: ethernet-phy@1c {
						reg = <0x1c>;
					};
					phy_sgmii_slot6_1d: ethernet-phy@1d {
						reg = <0x1d>;
					};
					phy_sgmii_slot6_1e: ethernet-phy@1e {
						reg = <0x1e>;
					};
					phy_sgmii_slot6_1f: ethernet-phy@1f {
						reg = <0x1f>;
					};
				};
			};
			mdio-mux-emi2 {
				compatible = "mdio-mux-mmioreg", "mdio-mux";
				mdio-parent-bus = <&xmdio0>;
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <9 1>; // BRDCFG1
				mux-mask = <0x06>; // EMI2

				/* FM2 10GEC1 is always on slot 1 */
				hydra_xg_slot1: hydra-xg-slot1@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;
					status = "disabled";

					phy_xgmii_slot_1: ethernet-phy@0 {
						reg = <4>;
					};
				};

				/* FM1 10GEC1 is always on slot 2 */
				hydra_xg_slot2: hydra-xg-slot2@2 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <2>;

					phy_xgmii_slot_2: ethernet-phy@4 {
						reg = <0>;
					};
				};
			};
		};
	};

	pci0: pcie@ffe200000 {
		reg = <0xf 0xfe200000 0 0x1000>;
		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x20000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};

	pci1: pcie@ffe201000 {
		reg = <0xf 0xfe201000 0 0x1000>;
		ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x20000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};

	pci2: pcie@ffe202000 {
		reg = <0xf 0xfe202000 0 0x1000>;
		ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x20000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};

	fsl,dpaa {
		compatible = "fsl,p5040-dpaa", "fsl,dpaa";

		ethernet@0 {
			compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet";
			fsl,fman-mac = <&fm1dtsec1>;
			status = "disabled";
		};
		ethernet@1 {
			compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet";
			fsl,fman-mac = <&fm1dtsec2>;
		};
		ethernet@2 {
			compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet";
			fsl,fman-mac = <&fm1dtsec3>;
		};
		ethernet@3 {
			compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet";
			fsl,fman-mac = <&fm1dtsec4>;
		};
		ethernet@4 {
			compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet";
			fsl,fman-mac = <&fm1dtsec5>;
		};
		ethernet@5 {
			compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet";
			fsl,fman-mac = <&fm1tgec>;
		};
		ethernet@6 {
			compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet";
			fsl,fman-mac = <&fm2dtsec1>;
			status = "disabled";
		};
		ethernet@7 {
			compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet";
			fsl,fman-mac = <&fm2dtsec2>;
		};
		ethernet@8 {
			compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet";
			fsl,fman-mac = <&fm2dtsec3>;
		};
		ethernet@9 {
			compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet";
			fsl,fman-mac = <&fm2dtsec4>;
		};
		ethernet@10 {
			compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet";
			fsl,fman-mac = <&fm2dtsec5>;
		};
		ethernet@11 {
			compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet";
			fsl,fman-mac = <&fm2tgec>;
		};
	};
};

/include/ "fsl/p5040si-post.dtsi"
/include/ "fsl/qoriq-dpaa-res1.dtsi"