/* * T1040RDB Device Tree Source * * Copyright 2014 Freescale Semiconductor Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /include/ "fsl/t104xsi-pre.dtsi" / { model = "fsl,T1040RDB"; compatible = "fsl,T1040RDB"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; aliases { phy_rgmii_0 = &phy_rgmii_0; phy_rgmii_1 = &phy_rgmii_1; phy_sgmii_2 = &phy_sgmii_2; }; ifc: localbus@ffe124000 { reg = <0xf 0xfe124000 0 0x2000>; ranges = <0 0 0xf 0xe8000000 0x08000000 2 0 0xf 0xff800000 0x00010000 3 0 0xf 0xffdf0000 0x00008000>; nor@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; reg = <0x0 0x0 0x8000000>; bank-width = <2>; device-width = <1>; }; nand@2,0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,ifc-nand"; reg = <0x2 0x0 0x10000>; partition@0 { /* This location must not be altered */ /* 1MB for u-boot Bootloader Image */ reg = <0x0 0x00100000>; label = "NAND U-Boot Image"; read-only; }; partition@100000 { /* 1MB for DTB Image */ reg = <0x00100000 0x00100000>; label = "NAND DTB Image"; }; partition@200000 { /* 10MB for Linux Kernel Image */ reg = <0x00200000 0x00A00000>; label = "NAND Linux Kernel Image"; }; partition@C00000 { /* 500MB for Root file System Image */ reg = <0x00c00000 0x1F400000>; label = "NAND RFS Image"; }; }; cpld@3,0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,t104xrdb-cpld", "fsl,deepsleep-cpld"; reg = <3 0 0x20>; ranges = <0 3 0 0x20>; bank-width = <1>; device-width = <1>; }; }; memory { device_type = "memory"; }; dcsr: dcsr@f00000000 { ranges = <0x00000000 0xf 0x00000000 0x01072000>; }; bportals: bman-portals@ff4000000 { ranges = <0x0 0xf 0xf4000000 0x2000000>; }; qportals: qman-portals@ff6000000 { ranges = <0x0 0xf 0xf6000000 0x2000000>; }; soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; i2c@118000 { adt7461@4c { compatible = "adi,adt7461"; reg = <0x4c>; }; }; i2c@118100 { pca9546@77 { compatible = "philips,pca9546"; reg = <0x77>; #address-cells = <1>; #size-cells = <0>; }; }; spi@110000 { flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q512ax3"; reg = <0>; spi-max-frequency = <10000000>; /* input clock */ }; slic@0 { compatible = "zarlink,le88266"; reg = <1>; spi-max-frequency = <8000000>; }; slic@1 { compatible = "zarlink,le88266"; reg = <2>; spi-max-frequency = <8000000>; }; slic@3 { compatible = "maxim,ds26522"; reg = <3>; spi-max-frequency = <2000000>; /* input clock */ }; }; fman0: fman@400000 { sleep = <&rcpm 0x00000008>; enet0: ethernet@e0000 { fixed-link = <0 1 1000 0 0>; phy-connection-type = "sgmii"; sleep = <&rcpm 0x80000000>; }; enet1: ethernet@e2000 { fixed-link = <1 1 1000 0 0>; phy-connection-type = "sgmii"; sleep = <&rcpm 0x40000000>; }; enet2: ethernet@e4000 { phy-handle = <&phy_sgmii_2>; phy-connection-type = "sgmii"; sleep = <&rcpm 0x20000000>; }; enet3: ethernet@e6000 { phy-handle = <&phy_rgmii_0>; phy-connection-type = "rgmii"; sleep = <&rcpm 0x10000000>; }; enet4: ethernet@e8000 { phy-handle = <&phy_rgmii_1>; phy-connection-type = "rgmii"; sleep = <&rcpm 0x08000000>; }; mdio0: mdio@fc000 { phy_sgmii_2: ethernet-phy@03 { reg = <0x03>; }; phy_rgmii_0: ethernet-phy@01 { reg = <0x01>; }; phy_rgmii_1: ethernet-phy@02 { reg = <0x02>; }; phy_qsgmii_0: ethernet-phy@04 { reg = <0x04>; interrupts = <0 1 0 0>; }; phy_qsgmii_1: ethernet-phy@05 { reg = <0x05>; interrupts = <0 1 0 0>; }; phy_qsgmii_2: ethernet-phy@06 { reg = <0x06>; interrupts = <0 1 0 0>; }; phy_qsgmii_3: ethernet-phy@07 { reg = <0x07>; interrupts = <0 1 0 0>; }; phy_qsgmii_4: ethernet-phy@08 { reg = <0x08>; interrupts = <0 1 0 0>; }; phy_qsgmii_5: ethernet-phy@09 { reg = <0x09>; interrupts = <0 1 0 0>; }; phy_qsgmii_6: ethernet-phy@0a { reg = <0x0a>; interrupts = <0 1 0 0>; }; phy_qsgmii_7: ethernet-phy@0b { reg = <0x0b>; interrupts = <0 1 0 0>; }; }; }; l2switch: l2switch@800000 { port@100000 { phy-connection-type = "qsgmii"; phy-handle = <&phy_qsgmii_0>; }; port@110000 { phy-connection-type = "qsgmii"; phy-handle = <&phy_qsgmii_1>; }; port@120000 { phy-connection-type = "qsgmii"; phy-handle = <&phy_qsgmii_2>; }; port@130000 { phy-connection-type = "qsgmii"; phy-handle = <&phy_qsgmii_3>; }; port@140000 { phy-connection-type = "qsgmii"; phy-handle = <&phy_qsgmii_4>; }; port@150000 { phy-connection-type = "qsgmii"; phy-handle = <&phy_qsgmii_5>; }; port@160000 { phy-connection-type = "qsgmii"; phy-handle = <&phy_qsgmii_6>; }; port@170000 { phy-connection-type = "qsgmii"; phy-handle = <&phy_qsgmii_7>; }; }; }; pci0: pcie@ffe240000 { reg = <0xf 0xfe240000 0 0x10000>; ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 0 0x10000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00010000>; }; }; pci1: pcie@ffe250000 { reg = <0xf 0xfe250000 0 0x10000>; ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 0 0x10000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00010000>; }; }; pci2: pcie@ffe260000 { reg = <0xf 0xfe260000 0 0x10000>; ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 0 0x10000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00010000>; }; }; pci3: pcie@ffe270000 { reg = <0xf 0xfe270000 0 0x10000>; ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 0 0x10000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00010000>; }; }; fsl,dpaa { compatible = "fsl,t1040-dpaa", "fsl,dpaa"; ethernet@0 { compatible = "fsl,t1040-dpa-ethernet", "fsl,dpa-ethernet"; fsl,fman-mac = <&enet0>; }; ethernet@1 { compatible = "fsl,t1040-dpa-ethernet", "fsl,dpa-ethernet"; fsl,fman-mac = <&enet1>; }; ethernet@2 { compatible = "fsl,t1040-dpa-ethernet", "fsl,dpa-ethernet"; fsl,fman-mac = <&enet2>; }; ethernet@3 { compatible = "fsl,t1040-dpa-ethernet", "fsl,dpa-ethernet"; fsl,fman-mac = <&enet3>; }; ethernet@4 { compatible = "fsl,t1040-dpa-ethernet", "fsl,dpa-ethernet"; fsl,fman-mac = <&enet4>; }; }; qe: qe@ffe139999 { ranges = <0x0 0xf 0xfe140000 0x40000>; reg = <0xf 0xfe140000 0 0x480>; brg-frequency = <0>; bus-frequency = <0>; si1: si@700 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,qe-si"; reg = <0x700 0x80>; }; siram1: siram@1000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,qe-siram"; reg = <0x1000 0x800>; }; tdma: ucc@2000 { compatible = "fsl,ucc-tdm"; rx-clock-name = "clk8"; tx-clock-name = "clk9"; fsl,rx-sync-clock = "rsync_pin"; fsl,tx-sync-clock = "tsync_pin"; fsl,tx-timeslot = <0xfffffffe>; fsl,rx-timeslot = <0xfffffffe>; fsl,tdm-framer-type = "e1"; fsl,tdm-mode = "normal"; fsl,tdm-id = <0>; fsl,siram-entry-id = <0>; }; ucc@2200 { compatible = "fsl,ucc_hdlc"; rx-clock-name = "clk10"; tx-clock-name = "clk11"; fsl,rx-sync-clock = "rsync_pin"; fsl,tx-sync-clock = "tsync_pin"; fsl,tx-timeslot = <0xfffffffe>; fsl,rx-timeslot = <0xfffffffe>; fsl,tdm-framer-type = "e1"; fsl,tdm-mode = "normal"; fsl,tdm-id = <1>; fsl,siram-entry-id = <2>; fsl,tdm-interface; }; }; }; /include/ "fsl/t1040si-post.dtsi" /include/ "fsl/qoriq-dpaa-res3.dtsi"