/* * PCIe host controller driver for Freescale Layerscape SoCs * * Copyright (C) 2014 Freescale Semiconductor. * * Author: Minghuan Lian * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "pcie-designware.h" /* PEX1/2 Misc Ports Status Register */ #define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4) #define LTSSM_STATE_SHIFT 20 #define LTSSM_STATE_MASK 0x3f #define LTSSM_PCIE_L0 0x11 /* L0 state */ /* SCFG MSI register */ #define SCFG_SPIMSICR 0x40 #define SCFG_SPIMSICLRCR 0x90 #define LS1021A_MSIIR_ADDR(idx) (0x1570e00 + (idx) * 8) #define LS1021A_MSIR_OFF(idx) (0x0e04 + (idx) * 8) /* Symbol Timer Register and Filter Mask Register 1 */ #define PCIE_STRFMR1 0x71c struct ls_pcie { struct list_head node; struct device *dev; struct pci_bus *bus; void __iomem *dbi; struct regmap *scfg; struct pcie_port pp; int index; int msi_irq; }; #define to_ls_pcie(x) container_of(x, struct ls_pcie, pp) static int ls_pcie_link_up(struct pcie_port *pp) { u32 state; struct ls_pcie *pcie = to_ls_pcie(pp); regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state); state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK; if (state < LTSSM_PCIE_L0) return 0; return 1; } static u32 ls_pcie_get_msi_addr(struct pcie_port *pp) { struct ls_pcie *pcie = to_ls_pcie(pp); return LS1021A_MSIIR_ADDR(pcie->index); } static u32 ls_pcie_get_msi_data(struct pcie_port *pp, int pos) { return pos * 8; } static irqreturn_t ls_pcie_msi_irq_handler(int irq, void *data) { struct pcie_port *pp = data; struct ls_pcie *pcie = to_ls_pcie(pp); unsigned long val; int msi_irq, ret, pos; regmap_read(pcie->scfg, LS1021A_MSIR_OFF(pcie->index), (u32 *) &val); if (val) { ret = IRQ_HANDLED; pos = 0; while ((pos = find_next_bit(&val, 32, pos)) != 32) { msi_irq = irq_find_mapping(pp->irq_domain, 31 - pos); if (!msi_irq) { /* * that's weird who triggered this? * just clear it */ dev_err(pcie->dev, "unexpected MSI\n"); ret = IRQ_NONE; continue; } #if defined(CONFIG_PREEMPT_RT_FULL) || defined(CONFIG_PREEMPT_RTB) local_irq_disable(); #endif generic_handle_irq(msi_irq); #if defined(CONFIG_PREEMPT_RT_FULL) || defined(CONFIG_PREEMPT_RTB) local_irq_enable(); #endif ret = IRQ_HANDLED; pos++; } } return ret; } static void ls_pcie_msi_clear_irq(struct pcie_port *pp, int irq) { } static void ls_pcie_msi_set_irq(struct pcie_port *pp, int irq) { } static void ls_pcie_host_init(struct pcie_port *pp) { struct ls_pcie *pcie = to_ls_pcie(pp); int count = 0; u32 val; dw_pcie_setup_rc(pp); if (of_device_is_compatible(pcie->dev->of_node, "fsl,ls1021a-pcie")) { /* * LS1021A Workaround for internal TKT228622 * to fix the INTx hang issue */ val = ioread32(pcie->dbi + PCIE_STRFMR1); val &= 0xffff; iowrite32(val, pcie->dbi + PCIE_STRFMR1); } } static struct pcie_host_ops ls_pcie_host_ops = { .link_up = ls_pcie_link_up, .host_init = ls_pcie_host_init, .msi_set_irq = ls_pcie_msi_set_irq, .msi_clear_irq = ls_pcie_msi_clear_irq, .get_msi_addr = ls_pcie_get_msi_addr, .get_msi_data = ls_pcie_get_msi_data, }; static int ls_add_pcie_port(struct ls_pcie *pcie) { struct pcie_port *pp; int ret; if (!pcie) return -EINVAL; pp = &pcie->pp; pp->dev = pcie->dev; pp->dbi_base = pcie->dbi; pp->msi_irq = pcie->msi_irq; if (IS_ENABLED(CONFIG_PCI_MSI)) { ret = devm_request_irq(pp->dev, pp->msi_irq, ls_pcie_msi_irq_handler, IRQF_SHARED, "ls-pcie-msi", pp); if (ret) { dev_err(pp->dev, "failed to request msi irq\n"); return ret; } } pp->root_bus_nr = -1; pp->ops = &ls_pcie_host_ops; ret = dw_pcie_host_init(pp); if (ret) { dev_err(pp->dev, "failed to initialize host\n"); return ret; } return 0; } static int __init ls_pcie_probe(struct platform_device *pdev) { struct ls_pcie *pcie; struct resource *dbi_base; u32 index[2]; int ret; pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) return -ENOMEM; pcie->dev = &pdev->dev; dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); if (!dbi_base) { dev_err(&pdev->dev, "missing *regs* space\n"); return -ENODEV; } pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base); if (IS_ERR(pcie->dbi)) return PTR_ERR(pcie->dbi); pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "fsl,pcie-scfg"); if (IS_ERR(pcie->scfg)) { dev_err(&pdev->dev, "No syscfg phandle specified\n"); return PTR_ERR(pcie->scfg); } ret = of_property_read_u32_array(pdev->dev.of_node, "fsl,pcie-scfg", index, 2); if (ret) return ret; pcie->index = index[1]; pcie->msi_irq = platform_get_irq_byname(pdev, "msi"); if (pcie->msi_irq < 0) { dev_err(&pdev->dev, "failed to get MSI IRQ: %d\n", pcie->msi_irq); return pcie->msi_irq; } ret = ls_add_pcie_port(pcie); if (ret < 0) return ret; platform_set_drvdata(pdev, pcie); return 0; } #ifdef CONFIG_PM_SLEEP static int ls_pcie_pm_suspend(struct device *dev) { return 0; } static int ls_pcie_pm_resume(struct device *dev) { struct ls_pcie *pcie = dev_get_drvdata(dev); ls_pcie_host_init(&pcie->pp); return 0; }; #endif /* CONFIG_PM_SLEEP */ static const struct of_device_id ls_pcie_of_match[] = { { .compatible = "fsl,ls1021a-pcie" }, { }, }; MODULE_DEVICE_TABLE(of, ls_pcie_of_match); static const struct dev_pm_ops ls_pcie_pm = { SET_SYSTEM_SLEEP_PM_OPS(ls_pcie_pm_suspend, ls_pcie_pm_resume) }; static struct platform_driver ls_pcie_driver = { .driver = { .name = "layerscape-pcie", .owner = THIS_MODULE, .of_match_table = ls_pcie_of_match, .pm = &ls_pcie_pm, }, }; module_platform_driver_probe(ls_pcie_driver, ls_pcie_probe); MODULE_AUTHOR("Minghuan Lian "); MODULE_DESCRIPTION("Freescale Layerscape PCIe host controller driver"); MODULE_LICENSE("GPL v2");