summaryrefslogtreecommitdiff
path: root/drivers/edac/mce_amd.c
blob: 44e6cdaff663d2fb83852342333290202752679b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
#include <linux/module.h>
#include <linux/slab.h>

#include "mce_amd.h"

static struct amd_decoder_ops *fam_ops;

static u8 xec_mask	 = 0xf;
static u8 nb_err_cpumask = 0xf;

static bool report_gart_errors;
static void (*nb_bus_decoder)(int node_id, struct mce *m, u32 nbcfg);

void amd_report_gart_errors(bool v)
{
	report_gart_errors = v;
}
EXPORT_SYMBOL_GPL(amd_report_gart_errors);

void amd_register_ecc_decoder(void (*f)(int, struct mce *, u32))
{
	nb_bus_decoder = f;
}
EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);

void amd_unregister_ecc_decoder(void (*f)(int, struct mce *, u32))
{
	if (nb_bus_decoder) {
		WARN_ON(nb_bus_decoder != f);

		nb_bus_decoder = NULL;
	}
}
EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);

/*
 * string representation for the different MCA reported error types, see F3x48
 * or MSR0000_0411.
 */

/* transaction type */
const char *tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
EXPORT_SYMBOL_GPL(tt_msgs);

/* cache level */
const char *ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
EXPORT_SYMBOL_GPL(ll_msgs);

/* memory transaction type */
const char *rrrr_msgs[] = {
       "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
};
EXPORT_SYMBOL_GPL(rrrr_msgs);

/* participating processor */
const char *pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
EXPORT_SYMBOL_GPL(pp_msgs);

/* request timeout */
const char *to_msgs[] = { "no timeout",	"timed out" };
EXPORT_SYMBOL_GPL(to_msgs);

/* memory or i/o */
const char *ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
EXPORT_SYMBOL_GPL(ii_msgs);

static const char *f10h_nb_mce_desc[] = {
	"HT link data error",
	"Protocol error (link, L3, probe filter, etc.)",
	"Parity error in NB-internal arrays",
	"Link Retry due to IO link transmission error",
	"L3 ECC data cache error",
	"ECC error in L3 cache tag",
	"L3 LRU parity bits error",
	"ECC Error in the Probe Filter directory"
};

static const char * const f15h_ic_mce_desc[] = {
	"UC during a demand linefill from L2",
	"Parity error during data load from IC",
	"Parity error for IC valid bit",
	"Main tag parity error",
	"Parity error in prediction queue",
	"PFB data/address parity error",
	"Parity error in the branch status reg",
	"PFB promotion address error",
	"Tag error during probe/victimization",
	"Parity error for IC probe tag valid bit",
	"PFB non-cacheable bit parity error",
	"PFB valid bit parity error",			/* xec = 0xd */
	"patch RAM",					/* xec = 010 */
	"uop queue",
	"insn buffer",
	"predecode buffer",
	"fetch address FIFO"
};

static const char * const f15h_cu_mce_desc[] = {
	"Fill ECC error on data fills",			/* xec = 0x4 */
	"Fill parity error on insn fills",
	"Prefetcher request FIFO parity error",
	"PRQ address parity error",
	"PRQ data parity error",
	"WCC Tag ECC error",
	"WCC Data ECC error",
	"WCB Data parity error",
	"VB Data/ECC error",
	"L2 Tag ECC error",				/* xec = 0x10 */
	"Hard L2 Tag ECC error",
	"Multiple hits on L2 tag",
	"XAB parity error",
	"PRB address parity error"
};

static bool f12h_dc_mce(u16 ec, u8 xec)
{
	bool ret = false;

	if (MEM_ERROR(ec)) {
		u8 ll = ec & 0x3;
		ret = true;

		if (ll == LL_L2)
			pr_cont("during L1 linefill from L2.\n");
		else if (ll == LL_L1)
			pr_cont("Data/Tag %s error.\n", RRRR_MSG(ec));
		else
			ret = false;
	}
	return ret;
}

static bool f10h_dc_mce(u16 ec, u8 xec)
{
	u8 r4  = (ec >> 4) & 0xf;
	u8 ll  = ec & 0x3;

	if (r4 == R4_GEN && ll == LL_L1) {
		pr_cont("during data scrub.\n");
		return true;
	}
	return f12h_dc_mce(ec, xec);
}

static bool k8_dc_mce(u16 ec, u8 xec)
{
	if (BUS_ERROR(ec)) {
		pr_cont("during system linefill.\n");
		return true;
	}

	return f10h_dc_mce(ec, xec);
}

static bool f14h_dc_mce(u16 ec, u8 xec)
{
	u8 r4	 = (ec >> 4) & 0xf;
	u8 ll	 = ec & 0x3;
	u8 tt	 = (ec >> 2) & 0x3;
	u8 ii	 = tt;
	bool ret = true;

	if (MEM_ERROR(ec)) {

		if (tt != TT_DATA || ll != LL_L1)
			return false;

		switch (r4) {
		case R4_DRD:
		case R4_DWR:
			pr_cont("Data/Tag parity error due to %s.\n",
				(r4 == R4_DRD ? "load/hw prf" : "store"));
			break;
		case R4_EVICT:
			pr_cont("Copyback parity error on a tag miss.\n");
			break;
		case R4_SNOOP:
			pr_cont("Tag parity error during snoop.\n");
			break;
		default:
			ret = false;
		}
	} else if (BUS_ERROR(ec)) {

		if ((ii != II_MEM && ii != II_IO) || ll != LL_LG)
			return false;

		pr_cont("System read data error on a ");

		switch (r4) {
		case R4_RD:
			pr_cont("TLB reload.\n");
			break;
		case R4_DWR:
			pr_cont("store.\n");
			break;
		case R4_DRD:
			pr_cont("load.\n");
			break;
		default:
			ret = false;
		}
	} else {
		ret = false;
	}

	return ret;
}

static bool f15h_dc_mce(u16 ec, u8 xec)
{
	bool ret = true;

	if (MEM_ERROR(ec)) {

		switch (xec) {
		case 0x0:
			pr_cont("Data Array access error.\n");
			break;

		case 0x1:
			pr_cont("UC error during a linefill from L2/NB.\n");
			break;

		case 0x2:
		case 0x11:
			pr_cont("STQ access error.\n");
			break;

		case 0x3:
			pr_cont("SCB access error.\n");
			break;

		case 0x10:
			pr_cont("Tag error.\n");
			break;

		case 0x12:
			pr_cont("LDQ access error.\n");
			break;

		default:
			ret = false;
		}
	} else if (BUS_ERROR(ec)) {

		if (!xec)
			pr_cont("during system linefill.\n");
		else
			pr_cont(" Internal %s condition.\n",
				((xec == 1) ? "livelock" : "deadlock"));
	} else
		ret = false;

	return ret;
}

static void amd_decode_dc_mce(struct mce *m)
{
	u16 ec = m->status & 0xffff;
	u8 xec = (m->status >> 16) & xec_mask;

	pr_emerg(HW_ERR "Data Cache Error: ");

	/* TLB error signatures are the same across families */
	if (TLB_ERROR(ec)) {
		u8 tt = (ec >> 2) & 0x3;

		if (tt == TT_DATA) {
			pr_cont("%s TLB %s.\n", LL_MSG(ec),
				((xec == 2) ? "locked miss"
					    : (xec ? "multimatch" : "parity")));
			return;
		}
	} else if (fam_ops->dc_mce(ec, xec))
		;
	else
		pr_emerg(HW_ERR "Corrupted DC MCE info?\n");
}

static bool k8_ic_mce(u16 ec, u8 xec)
{
	u8 ll	 = ec & 0x3;
	u8 r4	 = (ec >> 4) & 0xf;
	bool ret = true;

	if (!MEM_ERROR(ec))
		return false;

	if (ll == 0x2)
		pr_cont("during a linefill from L2.\n");
	else if (ll == 0x1) {
		switch (r4) {
		case R4_IRD:
			pr_cont("Parity error during data load.\n");
			break;

		case R4_EVICT:
			pr_cont("Copyback Parity/Victim error.\n");
			break;

		case R4_SNOOP:
			pr_cont("Tag Snoop error.\n");
			break;

		default:
			ret = false;
			break;
		}
	} else
		ret = false;

	return ret;
}

static bool f14h_ic_mce(u16 ec, u8 xec)
{
	u8 ll    = ec & 0x3;
	u8 tt    = (ec >> 2) & 0x3;
	u8 r4  = (ec >> 4) & 0xf;
	bool ret = true;

	if (MEM_ERROR(ec)) {
		if (tt != 0 || ll != 1)
			ret = false;

		if (r4 == R4_IRD)
			pr_cont("Data/tag array parity error for a tag hit.\n");
		else if (r4 == R4_SNOOP)
			pr_cont("Tag error during snoop/victimization.\n");
		else
			ret = false;
	}
	return ret;
}

static bool f15h_ic_mce(u16 ec, u8 xec)
{
	bool ret = true;

	if (!MEM_ERROR(ec))
		return false;

	switch (xec) {
	case 0x0 ... 0xa:
		pr_cont("%s.\n", f15h_ic_mce_desc[xec]);
		break;

	case 0xd:
		pr_cont("%s.\n", f15h_ic_mce_desc[xec-2]);
		break;

	case 0x10 ... 0x14:
		pr_cont("Decoder %s parity error.\n", f15h_ic_mce_desc[xec-4]);
		break;

	default:
		ret = false;
	}
	return ret;
}

static void amd_decode_ic_mce(struct mce *m)
{
	u16 ec = m->status & 0xffff;
	u8 xec = (m->status >> 16) & xec_mask;

	pr_emerg(HW_ERR "Instruction Cache Error: ");

	if (TLB_ERROR(ec))
		pr_cont("%s TLB %s.\n", LL_MSG(ec),
			(xec ? "multimatch" : "parity error"));
	else if (BUS_ERROR(ec)) {
		bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58)));

		pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read"));
	} else if (fam_ops->ic_mce(ec, xec))
		;
	else
		pr_emerg(HW_ERR "Corrupted IC MCE info?\n");
}

static void amd_decode_bu_mce(struct mce *m)
{
	u32 ec = m->status & 0xffff;
	u32 xec = (m->status >> 16) & xec_mask;

	pr_emerg(HW_ERR "Bus Unit Error");

	if (xec == 0x1)
		pr_cont(" in the write data buffers.\n");
	else if (xec == 0x3)
		pr_cont(" in the victim data buffers.\n");
	else if (xec == 0x2 && MEM_ERROR(ec))
		pr_cont(": %s error in the L2 cache tags.\n", RRRR_MSG(ec));
	else if (xec == 0x0) {
		if (TLB_ERROR(ec))
			pr_cont(": %s error in a Page Descriptor Cache or "
				"Guest TLB.\n", TT_MSG(ec));
		else if (BUS_ERROR(ec))
			pr_cont(": %s/ECC error in data read from NB: %s.\n",
				RRRR_MSG(ec), PP_MSG(ec));
		else if (MEM_ERROR(ec)) {
			u8 rrrr = (ec >> 4) & 0xf;

			if (rrrr >= 0x7)
				pr_cont(": %s error during data copyback.\n",
					RRRR_MSG(ec));
			else if (rrrr <= 0x1)
				pr_cont(": %s parity/ECC error during data "
					"access from L2.\n", RRRR_MSG(ec));
			else
				goto wrong_bu_mce;
		} else
			goto wrong_bu_mce;
	} else
		goto wrong_bu_mce;

	return;

wrong_bu_mce:
	pr_emerg(HW_ERR "Corrupted BU MCE info?\n");
}

static void amd_decode_cu_mce(struct mce *m)
{
	u16 ec = m->status & 0xffff;
	u8 xec = (m->status >> 16) & xec_mask;

	pr_emerg(HW_ERR "Combined Unit Error: ");

	if (TLB_ERROR(ec)) {
		if (xec == 0x0)
			pr_cont("Data parity TLB read error.\n");
		else if (xec == 0x1)
			pr_cont("Poison data provided for TLB fill.\n");
		else
			goto wrong_cu_mce;
	} else if (BUS_ERROR(ec)) {
		if (xec > 2)
			goto wrong_cu_mce;

		pr_cont("Error during attempted NB data read.\n");
	} else if (MEM_ERROR(ec)) {
		switch (xec) {
		case 0x4 ... 0xc:
			pr_cont("%s.\n", f15h_cu_mce_desc[xec - 0x4]);
			break;

		case 0x10 ... 0x14:
			pr_cont("%s.\n", f15h_cu_mce_desc[xec - 0x7]);
			break;

		default:
			goto wrong_cu_mce;
		}
	}

	return;

wrong_cu_mce:
	pr_emerg(HW_ERR "Corrupted CU MCE info?\n");
}

static void amd_decode_ls_mce(struct mce *m)
{
	u16 ec = m->status & 0xffff;
	u8 xec = (m->status >> 16) & xec_mask;

	if (boot_cpu_data.x86 >= 0x14) {
		pr_emerg("You shouldn't be seeing an LS MCE on this cpu family,"
			 " please report on LKML.\n");
		return;
	}

	pr_emerg(HW_ERR "Load Store Error");

	if (xec == 0x0) {
		u8 r4 = (ec >> 4) & 0xf;

		if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR))
			goto wrong_ls_mce;

		pr_cont(" during %s.\n", RRRR_MSG(ec));
	} else
		goto wrong_ls_mce;

	return;

wrong_ls_mce:
	pr_emerg(HW_ERR "Corrupted LS MCE info?\n");
}

static bool k8_nb_mce(u16 ec, u8 xec)
{
	bool ret = true;

	switch (xec) {
	case 0x1:
		pr_cont("CRC error detected on HT link.\n");
		break;

	case 0x5:
		pr_cont("Invalid GART PTE entry during GART table walk.\n");
		break;

	case 0x6:
		pr_cont("Unsupported atomic RMW received from an IO link.\n");
		break;

	case 0x0:
	case 0x8:
		if (boot_cpu_data.x86 == 0x11)
			return false;

		pr_cont("DRAM ECC error detected on the NB.\n");
		break;

	case 0xd:
		pr_cont("Parity error on the DRAM addr/ctl signals.\n");
		break;

	default:
		ret = false;
		break;
	}

	return ret;
}

static bool f10h_nb_mce(u16 ec, u8 xec)
{
	bool ret = true;
	u8 offset = 0;

	if (k8_nb_mce(ec, xec))
		return true;

	switch(xec) {
	case 0xa ... 0xc:
		offset = 10;
		break;

	case 0xe:
		offset = 11;
		break;

	case 0xf:
		if (TLB_ERROR(ec))
			pr_cont("GART Table Walk data error.\n");
		else if (BUS_ERROR(ec))
			pr_cont("DMA Exclusion Vector Table Walk error.\n");
		else
			ret = false;

		goto out;
		break;

	case 0x1c ... 0x1f:
		offset = 24;
		break;

	default:
		ret = false;

		goto out;
		break;
	}

	pr_cont("%s.\n", f10h_nb_mce_desc[xec - offset]);

out:
	return ret;
}

static bool nb_noop_mce(u16 ec, u8 xec)
{
	return false;
}

void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg)
{
	u8 xec   = (m->status >> 16) & 0x1f;
	u16 ec   = m->status & 0xffff;
	u32 nbsh = (u32)(m->status >> 32);

	pr_emerg(HW_ERR "Northbridge Error, node %d: ", node_id);

	/*
	 * F10h, revD can disable ErrCpu[3:0] so check that first and also the
	 * value encoding has changed so interpret those differently
	 */
	if ((boot_cpu_data.x86 == 0x10) &&
	    (boot_cpu_data.x86_model > 7)) {
		if (nbsh & K8_NBSH_ERR_CPU_VAL)
			pr_cont(", core: %u", (u8)(nbsh & nb_err_cpumask));
	} else {
		u8 assoc_cpus = nbsh & nb_err_cpumask;

		if (assoc_cpus > 0)
			pr_cont(", core: %d", fls(assoc_cpus) - 1);
	}

	switch (xec) {
	case 0x2:
		pr_cont("Sync error (sync packets on HT link detected).\n");
		return;

	case 0x3:
		pr_cont("HT Master abort.\n");
		return;

	case 0x4:
		pr_cont("HT Target abort.\n");
		return;

	case 0x7:
		pr_cont("NB Watchdog timeout.\n");
		return;

	case 0x9:
		pr_cont("SVM DMA Exclusion Vector error.\n");
		return;

	default:
		break;
	}

	if (!fam_ops->nb_mce(ec, xec))
		goto wrong_nb_mce;

	if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10)
		if ((xec == 0x8 || xec == 0x0) && nb_bus_decoder)
			nb_bus_decoder(node_id, m, nbcfg);

	return;

wrong_nb_mce:
	pr_emerg(HW_ERR "Corrupted NB MCE info?\n");
}
EXPORT_SYMBOL_GPL(amd_decode_nb_mce);

static void amd_decode_fr_mce(struct mce *m)
{
	if (boot_cpu_data.x86 == 0xf ||
	    boot_cpu_data.x86 == 0x11)
		goto wrong_fr_mce;

	/* we have only one error signature so match all fields at once. */
	if ((m->status & 0xffff) == 0x0f0f) {
		pr_emerg(HW_ERR "FR Error: CPU Watchdog timer expire.\n");
		return;
	}

wrong_fr_mce:
	pr_emerg(HW_ERR "Corrupted FR MCE info?\n");
}

static inline void amd_decode_err_code(u16 ec)
{
	if (TLB_ERROR(ec)) {
		pr_emerg(HW_ERR "Transaction: %s, Cache Level: %s\n",
			 TT_MSG(ec), LL_MSG(ec));
	} else if (MEM_ERROR(ec)) {
		pr_emerg(HW_ERR "Transaction: %s, Type: %s, Cache Level: %s\n",
			 RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
	} else if (BUS_ERROR(ec)) {
		pr_emerg(HW_ERR "Transaction: %s (%s), %s, Cache Level: %s, "
			 "Participating Processor: %s\n",
			  RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec),
			  PP_MSG(ec));
	} else
		pr_emerg(HW_ERR "Huh? Unknown MCE error 0x%x\n", ec);
}

/*
 * Filter out unwanted MCE signatures here.
 */
static bool amd_filter_mce(struct mce *m)
{
	u8 xec = (m->status >> 16) & 0x1f;

	/*
	 * NB GART TLB error reporting is disabled by default.
	 */
	if (m->bank == 4 && xec == 0x5 && !report_gart_errors)
		return true;

	return false;
}

int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
{
	struct mce *m = (struct mce *)data;
	int node, ecc;

	if (amd_filter_mce(m))
		return NOTIFY_STOP;

	pr_emerg(HW_ERR "MC%d_STATUS: ", m->bank);

	pr_cont("%sorrected error, other errors lost: %s, "
		 "CPU context corrupt: %s",
		 ((m->status & MCI_STATUS_UC) ? "Unc"  : "C"),
		 ((m->status & MCI_STATUS_OVER) ? "yes"  : "no"),
		 ((m->status & MCI_STATUS_PCC) ? "yes" : "no"));

	/* do the two bits[14:13] together */
	ecc = (m->status >> 45) & 0x3;
	if (ecc)
		pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));

	pr_cont("\n");

	switch (m->bank) {
	case 0:
		amd_decode_dc_mce(m);
		break;

	case 1:
		amd_decode_ic_mce(m);
		break;

	case 2:
		if (boot_cpu_data.x86 == 0x15)
			amd_decode_cu_mce(m);
		else
			amd_decode_bu_mce(m);
		break;

	case 3:
		amd_decode_ls_mce(m);
		break;

	case 4:
		node = amd_get_nb_id(m->extcpu);
		amd_decode_nb_mce(node, m, 0);
		break;

	case 5:
		amd_decode_fr_mce(m);
		break;

	default:
		break;
	}

	amd_decode_err_code(m->status & 0xffff);

	return NOTIFY_STOP;
}
EXPORT_SYMBOL_GPL(amd_decode_mce);

static struct notifier_block amd_mce_dec_nb = {
	.notifier_call	= amd_decode_mce,
};

static int __init mce_amd_init(void)
{
	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
		return 0;

	if ((boot_cpu_data.x86 < 0xf || boot_cpu_data.x86 > 0x12) &&
	    (boot_cpu_data.x86 != 0x14 || boot_cpu_data.x86_model > 0xf))
		return 0;

	fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
	if (!fam_ops)
		return -ENOMEM;

	switch (boot_cpu_data.x86) {
	case 0xf:
		fam_ops->dc_mce = k8_dc_mce;
		fam_ops->ic_mce = k8_ic_mce;
		fam_ops->nb_mce = k8_nb_mce;
		break;

	case 0x10:
		fam_ops->dc_mce = f10h_dc_mce;
		fam_ops->ic_mce = k8_ic_mce;
		fam_ops->nb_mce = f10h_nb_mce;
		break;

	case 0x11:
		fam_ops->dc_mce = k8_dc_mce;
		fam_ops->ic_mce = k8_ic_mce;
		fam_ops->nb_mce = f10h_nb_mce;
		break;

	case 0x12:
		fam_ops->dc_mce = f12h_dc_mce;
		fam_ops->ic_mce = k8_ic_mce;
		fam_ops->nb_mce = nb_noop_mce;
		break;

	case 0x14:
		nb_err_cpumask  = 0x3;
		fam_ops->dc_mce = f14h_dc_mce;
		fam_ops->ic_mce = f14h_ic_mce;
		fam_ops->nb_mce = nb_noop_mce;
		break;

	case 0x15:
		xec_mask = 0x1f;
		fam_ops->dc_mce = f15h_dc_mce;
		fam_ops->ic_mce = f15h_ic_mce;
		break;

	default:
		printk(KERN_WARNING "Huh? What family is that: %d?!\n",
				    boot_cpu_data.x86);
		kfree(fam_ops);
		return -EINVAL;
	}

	pr_info("MCE: In-kernel MCE decoding enabled.\n");

	atomic_notifier_chain_register(&x86_mce_decoder_chain, &amd_mce_dec_nb);

	return 0;
}
early_initcall(mce_amd_init);

#ifdef MODULE
static void __exit mce_amd_exit(void)
{
	atomic_notifier_chain_unregister(&x86_mce_decoder_chain, &amd_mce_dec_nb);
	kfree(fam_ops);
}

MODULE_DESCRIPTION("AMD MCE decoder");
MODULE_ALIAS("edac-mce-amd");
MODULE_LICENSE("GPL");
module_exit(mce_amd_exit);
#endif