diff options
| author | Stefan Roese <sr@denx.de> | 2016-07-13 09:55:18 (GMT) |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2016-08-08 14:16:31 (GMT) |
| commit | 0160a4b68987ef8df1d57529d13be7ed4f674374 (patch) | |
| tree | be0880718f84aedcc660b97c025a436bbd619b8e /arch/arm/boot/dts/armada-388-rd.dts | |
| parent | 1113603e39b1ea10d02f97c86c25d57b971cb470 (diff) | |
| download | linux-0160a4b68987ef8df1d57529d13be7ed4f674374.tar.xz | |
ARM: dts: mvebu: A37x/XP/38x/39x: Move SPI controller nodes into 'soc' node
This patch moves all Armada 370/XP/38x/39x SPI controller nodes from the
'internal-regs' node down into the 'soc' node. This is in preparation
to enable the usage of the SPI direct access mode. A follow-up patch
will add the static MBus mappings for the SPI devices into the 'reg'
property of the SPI controller DT node.
By moving these SPI controller nodes, this patch also makes use of
the labels rather than keeping the tree structure.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Mark Brown <broonie@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/armada-388-rd.dts')
| -rw-r--r-- | arch/arm/boot/dts/armada-388-rd.dts | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts index 853f973..dd3462dd 100644 --- a/arch/arm/boot/dts/armada-388-rd.dts +++ b/arch/arm/boot/dts/armada-388-rd.dts @@ -70,18 +70,6 @@ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; internal-regs { - spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; - }; - i2c@11000 { status = "okay"; clock-frequency = <100000>; @@ -142,3 +130,16 @@ }; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; +}; + |