summaryrefslogtreecommitdiff
path: root/drivers/clk/pxa
diff options
context:
space:
mode:
authorRobert Jarzmik <robert.jarzmik@free.fr>2015-08-04 06:21:33 (GMT)
committerStephen Boyd <sboyd@codeaurora.org>2015-08-07 23:53:13 (GMT)
commitb93028c9af807b9474789e6aba34a6135b6cb708 (patch)
treee5fb6830d01b30aae84c56c197b716908287a447 /drivers/clk/pxa
parentbc0195aad0daa2ad5b0d76cce22b167bc3435590 (diff)
downloadlinux-b93028c9af807b9474789e6aba34a6135b6cb708.tar.xz
clk: pxa: pxa3xx: fix CKEN register access
Clocks 0 to 31 are on CKENA, and not CKENB. The clock register names were inadequately inverted. As a consequence, all clock operations were happening on CKENB, because almost all but 2 clocks are on CKENA. As the clocks were activated by the bootloader in the former tests, it escaped the testing that the wrong clock gate was manipulated. The error was revealed by changing the pxa3xx-nand driver to a module, where upon unloading, the wrong clock was disabled in CKENB. Fixes: 9bbb8a338fb2 ("clk: pxa: add pxa3xx clock driver") Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/pxa')
-rw-r--r--drivers/clk/pxa/clk-pxa3xx.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/pxa/clk-pxa3xx.c b/drivers/clk/pxa/clk-pxa3xx.c
index 4b93a1e..ac03ba4 100644
--- a/drivers/clk/pxa/clk-pxa3xx.c
+++ b/drivers/clk/pxa/clk-pxa3xx.c
@@ -126,7 +126,7 @@ PARENTS(pxa3xx_ac97_bus) = { "ring_osc_60mhz", "ac97" };
PARENTS(pxa3xx_sbus) = { "ring_osc_60mhz", "system_bus" };
PARENTS(pxa3xx_smemcbus) = { "ring_osc_60mhz", "smemc" };
-#define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? &CKENA : &CKENB)
+#define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? &CKENB : &CKENA)
#define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp, \
div_hp, bit, is_lp, flags) \
PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp, \