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| author | Alex Shi <alex.shi@linaro.org> | 2017-11-09 04:02:01 (GMT) |
|---|---|---|
| committer | Alex Shi <alex.shi@linaro.org> | 2017-11-09 04:02:01 (GMT) |
| commit | 3871608e4cb995b0fb9c630da9ac45b246151fef (patch) | |
| tree | 1a7d65ae9b815e73ec9ffe00d6a3778ab66d5dc8 /drivers/net/phy | |
| parent | d177d7df2673ea81e8ee1e3d468398eeb7e580f5 (diff) | |
| parent | 5caae9d1419914177994363218616b869659e871 (diff) | |
| download | linux-3871608e4cb995b0fb9c630da9ac45b246151fef.tar.xz | |
Merge tag 'v4.9.61' into linux-linaro-lsk-v4.9
This is the 4.9.61 stable release
Diffstat (limited to 'drivers/net/phy')
| -rw-r--r-- | drivers/net/phy/dp83867.c | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 01cf094..8f84961 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -33,6 +33,7 @@ /* Extended Registers */ #define DP83867_RGMIICTL 0x0032 +#define DP83867_STRAP_STS1 0x006E #define DP83867_RGMIIDCTL 0x0086 #define DP83867_SW_RESET BIT(15) @@ -56,9 +57,13 @@ #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) +/* STRAP_STS1 bits */ +#define DP83867_STRAP_STS1_RESERVED BIT(11) + /* PHY CTRL bits */ #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 #define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14) +#define DP83867_PHYCR_RESERVED_MASK BIT(11) /* RGMIIDCTL bits */ #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 @@ -141,7 +146,7 @@ static int dp83867_of_init(struct phy_device *phydev) static int dp83867_config_init(struct phy_device *phydev) { struct dp83867_private *dp83867; - int ret, val; + int ret, val, bs; u16 delay; if (!phydev->priv) { @@ -164,6 +169,22 @@ static int dp83867_config_init(struct phy_device *phydev) return val; val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK; val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT); + + /* The code below checks if "port mirroring" N/A MODE4 has been + * enabled during power on bootstrap. + * + * Such N/A mode enabled by mistake can put PHY IC in some + * internal testing mode and disable RGMII transmission. + * + * In this particular case one needs to check STRAP_STS1 + * register's bit 11 (marked as RESERVED). + */ + + bs = phy_read_mmd_indirect(phydev, DP83867_STRAP_STS1, + DP83867_DEVADDR); + if (bs & DP83867_STRAP_STS1_RESERVED) + val &= ~DP83867_PHYCR_RESERVED_MASK; + ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); if (ret) return ret; |