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author | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-06-03 10:00:09 (GMT) |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-06-25 16:07:51 (GMT) |
commit | e9d7a45a039913497a57887d85f5decfda4679f0 (patch) | |
tree | 8ed57a4bf50f052324de06d25bfb8ff2a5517754 /drivers/tty/serial/sh-sci.c | |
parent | d2b9775d795ec05fb42504c0f47dd06ba5fd709e (diff) | |
download | linux-e9d7a45a039913497a57887d85f5decfda4679f0.tar.xz |
serial: sh-sci: Add pin initialization for SCIFA/SCIFB
Before, the driver relied on initialization by the boot loader, or by
implicit reset state.
Note that unlike on (H)SCIF, the RTS/CTS bits exist only if dedicated
RTS/CTS pins are available, which depends on the SoC and UART instance.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty/serial/sh-sci.c')
-rw-r--r-- | drivers/tty/serial/sh-sci.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index c46999f..b9d027a 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -712,7 +712,21 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag) return; } - if (sci_getreg(port, SCSPTR)->size) { + if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { + u16 ctrl = serial_port_in(port, SCPCR); + + /* Enable RXD and TXD pin functions */ + ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); + if (to_sci_port(port)->cfg->capabilities & SCIx_HAVE_RTSCTS) { + /* RTS# is output, driven 1 */ + ctrl |= SCPCR_RTSC; + serial_port_out(port, SCPDR, + serial_port_in(port, SCPDR) | SCPDR_RTSD); + /* Enable CTS# pin function */ + ctrl &= ~SCPCR_CTSC; + } + serial_port_out(port, SCPCR, ctrl); + } else if (sci_getreg(port, SCSPTR)->size) { u16 status = serial_port_in(port, SCSPTR); /* RTS# is output, driven 1 */ |