From e3668833955ad3a3d7459376179b7f9157c8b467 Mon Sep 17 00:00:00 2001 From: Claudiu Manoil Date: Thu, 7 Dec 2017 18:44:23 +0200 Subject: gianfar: Disable EEE autoneg by default This controller does not support EEE, but it may connect to a PHY which supports EEE and advertises EEE by default, while its link partner also advertises EEE. If this happens, the PHY enters low power mode when the traffic rate is low and causes packet loss. This patch disables EEE advertisement by default for any PHY that gianfar connects to, to prevent the above unwanted outcome. Signed-off-by: Shaohui Xie Tested-by: Yangbo Lu Signed-off-by: Claudiu Manoil Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller diff --git a/drivers/net/ethernet/freescale/gianfar.c b/drivers/net/ethernet/freescale/gianfar.c index 6fba88e..99836ee 100644 --- a/drivers/net/ethernet/freescale/gianfar.c +++ b/drivers/net/ethernet/freescale/gianfar.c @@ -1787,6 +1787,7 @@ static int init_phy(struct net_device *dev) GFAR_SUPPORTED_GBIT : 0; phy_interface_t interface; struct phy_device *phydev; + struct ethtool_eee edata; priv->oldlink = 0; priv->oldspeed = 0; @@ -1811,6 +1812,10 @@ static int init_phy(struct net_device *dev) /* Add support for flow control, but don't advertise it by default */ phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause); + /* disable EEE autoneg, EEE not supported by eTSEC */ + memset(&edata, 0, sizeof(struct ethtool_eee)); + phy_ethtool_set_eee(phydev, &edata); + return 0; } -- cgit v0.10.2 From a5e5a7bcf3bae018e65f090dec0062c2cbf36de8 Mon Sep 17 00:00:00 2001 From: Zhang Ying-22455 Date: Fri, 1 Dec 2017 15:59:28 +0800 Subject: i2c: imx: implement bus recovery with gpio for Layerscape Based on the I2C specification, if the data line (SDA) is stuck low, the master should send nine clock pulses. The I2C slave device that held the bus low should release it sometime within those nine clocks. Because pinctrl is not supported on Layerscape, current bus recovery is not avalible for Layerscape. This patch uses an open drain GPIO pin to connect to the IICx_SCL to drive nine clock pulses to unlock the I2C bus. Signed-off-by: Zhang Ying-22455 diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c index a35c366..6617e60 100644 --- a/drivers/i2c/busses/i2c-imx.c +++ b/drivers/i2c/busses/i2c-imx.c @@ -53,6 +53,11 @@ #include #include #include +#include +#include +#include +#include +#include /* This will be the driver name the kernel reports */ #define DRIVER_NAME "imx-i2c" @@ -117,6 +122,54 @@ #define I2C_PM_TIMEOUT 10 /* ms */ +enum pinmux_endian_type { + BIG_ENDIAN, + LITTLE_ENDIAN, +}; + +struct pinmux_cfg { + enum pinmux_endian_type endian; /* endian of RCWPMUXCR0 */ + u32 pmuxcr_offset; + u32 pmuxcr_set_bit; /* pin mux of RCWPMUXCR0 */ +}; + +static struct pinmux_cfg ls1012a_pinmux_cfg = { + .endian = BIG_ENDIAN, + .pmuxcr_offset = 0x430, + .pmuxcr_set_bit = 0x10, +}; + +static struct pinmux_cfg ls1043a_pinmux_cfg = { + .endian = BIG_ENDIAN, + .pmuxcr_offset = 0x40C, + .pmuxcr_set_bit = 0x10, +}; + +static struct pinmux_cfg ls1046a_pinmux_cfg = { + .endian = BIG_ENDIAN, + .pmuxcr_offset = 0x40C, + .pmuxcr_set_bit = 0x80000000, +}; + +static const struct of_device_id pinmux_of_match[] = { + { .compatible = "fsl,ls1012a-vf610-i2c", .data = &ls1012a_pinmux_cfg}, + { .compatible = "fsl,ls1043a-vf610-i2c", .data = &ls1043a_pinmux_cfg}, + { .compatible = "fsl,ls1046a-vf610-i2c", .data = &ls1046a_pinmux_cfg}, + {}, +}; +MODULE_DEVICE_TABLE(of, pinmux_of_match); + +/* The SCFG, Supplemental Configuration Unit, provides SoC specific + * configuration and status registers for the device. There is a + * SDHC IO VSEL control register on SCFG for some platforms. It's + * used to support SDHC IO voltage switching. + */ +static const struct of_device_id scfg_device_ids[] = { + { .compatible = "fsl,ls1012a-scfg", }, + { .compatible = "fsl,ls1043a-scfg", }, + { .compatible = "fsl,ls1046a-scfg", }, + {} +}; /* * sorted list of clock divider, register value pairs * taken from table 26-5, p.26-9, Freescale i.MX @@ -210,6 +263,12 @@ struct imx_i2c_struct { struct pinctrl_state *pinctrl_pins_gpio; struct imx_i2c_dma *dma; + int layerscape_bus_recover; + int gpio; + int need_set_pmuxcr; + int pmuxcr_set; + int pmuxcr_endian; + void __iomem *pmuxcr_addr; }; static const struct imx_i2c_hwdata imx1_i2c_hwdata = { @@ -879,6 +938,78 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bo return 0; } +/* + * Based on the I2C specification, if the data line (SDA) is + * stuck low, the master should send nine * clock pulses. + * The I2C slave device that held the bus low should release it + * sometime within * those nine clocks. Due to this erratum, + * the I2C controller cannot generate nine clock pulses. + */ +static int i2c_imx_recovery_for_layerscape(struct imx_i2c_struct *i2c_imx) +{ + u32 pmuxcr = 0; + int ret; + unsigned int i, temp; + + /* configure IICx_SCL/GPIO pin as a GPIO */ + if (i2c_imx->need_set_pmuxcr == 1) { + pmuxcr = ioread32be(i2c_imx->pmuxcr_addr); + if (i2c_imx->pmuxcr_endian == BIG_ENDIAN) + iowrite32be(i2c_imx->pmuxcr_set|pmuxcr, + i2c_imx->pmuxcr_addr); + else + iowrite32(i2c_imx->pmuxcr_set|pmuxcr, + i2c_imx->pmuxcr_addr); + } + + ret = gpio_request(i2c_imx->gpio, i2c_imx->adapter.name); + if (ret) { + dev_err(&i2c_imx->adapter.dev, + "can't get gpio: %d\n", ret); + return ret; + } + + /* Configure GPIO pin as an output and open drain. */ + gpio_direction_output(i2c_imx->gpio, 1); + udelay(10); + + /* Write data to generate 9 pulses */ + for (i = 0; i < 9; i++) { + gpio_set_value(i2c_imx->gpio, 1); + udelay(10); + gpio_set_value(i2c_imx->gpio, 0); + udelay(10); + } + /* ensure that the last level sent is always high */ + gpio_set_value(i2c_imx->gpio, 1); + + /* + * Set I2Cx_IBCR = 0h00 to generate a STOP and then + * set I2Cx_IBCR = 0h80 to reset + */ + temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); + temp &= ~(I2CR_MSTA | I2CR_MTX); + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); + + /* Restore the saved value of the register SCFG_RCWPMUXCR0 */ + if (i2c_imx->need_set_pmuxcr == 1) { + if (i2c_imx->pmuxcr_endian == BIG_ENDIAN) + iowrite32be(pmuxcr, i2c_imx->pmuxcr_addr); + else + iowrite32(pmuxcr, i2c_imx->pmuxcr_addr); + } + /* + * Set I2C_IBSR[IBAL] to clear the IBAL bit if- + * I2C_IBSR[IBAL] = 1 + */ + temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); + if (temp & I2SR_IAL) { + temp &= ~I2SR_IAL; + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); + } + return 0; +} + static int i2c_imx_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) { @@ -894,8 +1025,13 @@ static int i2c_imx_xfer(struct i2c_adapter *adapter, * before switching to master mode and attempting a Start cycle */ result = i2c_imx_bus_busy(i2c_imx, 0); - if (result) - goto out; + if (result) { + /* timeout */ + if ((result == -ETIMEDOUT) && (i2c_imx->layerscape_bus_recover == 1)) + i2c_imx_recovery_for_layerscape(i2c_imx); + else + goto out; + } result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent); if (result < 0) @@ -1039,6 +1175,50 @@ static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, return 0; } +/* + * switch SCL and SDA to their GPIO function and do some bitbanging + * for bus recovery. + * There are platforms such as Layerscape that don't support pinctrl, so add + * workaround for layerscape, it has no effect for other platforms. + */ +static int i2c_imx_init_recovery_for_layerscape( + struct imx_i2c_struct *i2c_imx, + struct platform_device *pdev) +{ + const struct of_device_id *of_id; + struct device_node *np = pdev->dev.of_node; + struct pinmux_cfg *pinmux_cfg; + struct device_node *scfg_node; + void __iomem *scfg_base = NULL; + + i2c_imx->gpio = of_get_named_gpio(np, "fsl-scl-gpio", 0); + if (!gpio_is_valid(i2c_imx->gpio)) { + dev_info(&pdev->dev, "fsl-scl-gpio not found\n"); + return 0; + } + pinmux_cfg = devm_kzalloc(&pdev->dev, sizeof(*pinmux_cfg), GFP_KERNEL); + if (!pinmux_cfg) + return -ENOMEM; + + i2c_imx->need_set_pmuxcr = 0; + of_id = of_match_node(pinmux_of_match, np); + if (of_id) { + pinmux_cfg = (struct pinmux_cfg *)of_id->data; + i2c_imx->pmuxcr_endian = pinmux_cfg->endian; + i2c_imx->pmuxcr_set = pinmux_cfg->pmuxcr_set_bit; + scfg_node = of_find_matching_node(NULL, scfg_device_ids); + if (scfg_node) { + scfg_base = of_iomap(scfg_node, 0); + if (scfg_base) { + i2c_imx->pmuxcr_addr = scfg_base + pinmux_cfg->pmuxcr_offset; + i2c_imx->need_set_pmuxcr = 1; + } + } + } + i2c_imx->layerscape_bus_recover = 1; + return 0; +} + static u32 i2c_imx_func(struct i2c_adapter *adapter) { return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL @@ -1094,6 +1274,11 @@ static int i2c_imx_probe(struct platform_device *pdev) i2c_imx->adapter.dev.of_node = pdev->dev.of_node; i2c_imx->base = base; + /* Init optional bus recovery for layerscape */ + ret = i2c_imx_init_recovery_for_layerscape(i2c_imx, pdev); + if (ret) + return ret; + /* Get I2C clock */ i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(i2c_imx->clk)) { -- cgit v0.10.2 From b62b10a57ae9fe6dcb5bf392b05142e37e697e31 Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Mon, 4 Dec 2017 15:59:29 +0800 Subject: clk: qoriq: add more divider clocks support More divider clocks are needed for IP use. So enlarge the PLL divider array to accommodate more divider clocks. Signed-off-by: Tang Yuantian diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index 1bd2c76..737148e 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -69,6 +69,7 @@ second cell is the clock index for the specified type. 2 hwaccel index (n in CLKCGnHWACSR) 3 fman 0 for fm1, 1 for fm2 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4 + 4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8 3. Example diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index 0e7de00..d62ccb2 100644 --- a/drivers/clk/clk-qoriq.c +++ b/drivers/clk/clk-qoriq.c @@ -41,7 +41,7 @@ struct clockgen_pll_div { }; struct clockgen_pll { - struct clockgen_pll_div div[4]; + struct clockgen_pll_div div[8]; }; #define CLKSEL_VALID 1 @@ -1127,6 +1127,13 @@ static void __init create_one_pll(struct clockgen *cg, int idx) struct clk *clk; int ret; + /* + * For platform PLL, there are 8 divider clocks. + * For core PLL, there are 4 divider clocks at most. + */ + if (idx != 0 && i >= 4) + break; + snprintf(pll->div[i].name, sizeof(pll->div[i].name), "cg-pll%d-div%d", idx, i + 1); -- cgit v0.10.2 From b0c4ae093b3df772d27ef109ca810fefab005fca Mon Sep 17 00:00:00 2001 From: Madalin Bucur Date: Wed, 7 Dec 2016 17:14:56 +0200 Subject: powerpc/fsl/dts: add FMan node for t1042d4rdb Signed-off-by: Madalin Bucur Signed-off-by: Scott Wood diff --git a/arch/powerpc/boot/dts/fsl/t1042d4rdb.dts b/arch/powerpc/boot/dts/fsl/t1042d4rdb.dts index 2a5a90d..fcd2aeb 100644 --- a/arch/powerpc/boot/dts/fsl/t1042d4rdb.dts +++ b/arch/powerpc/boot/dts/fsl/t1042d4rdb.dts @@ -48,6 +48,58 @@ "fsl,deepsleep-cpld"; }; }; + + soc: soc@ffe000000 { + fman0: fman@400000 { + ethernet@e0000 { + phy-handle = <&phy_sgmii_0>; + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-handle = <&phy_sgmii_1>; + phy-connection-type = "sgmii"; + }; + + ethernet@e4000 { + phy-handle = <&phy_sgmii_2>; + phy-connection-type = "sgmii"; + }; + + ethernet@e6000 { + phy-handle = <&phy_rgmii_0>; + phy-connection-type = "rgmii"; + }; + + ethernet@e8000 { + phy-handle = <&phy_rgmii_1>; + phy-connection-type = "rgmii"; + }; + + mdio0: mdio@fc000 { + phy_sgmii_0: ethernet-phy@02 { + reg = <0x02>; + }; + + phy_sgmii_1: ethernet-phy@03 { + reg = <0x03>; + }; + + phy_sgmii_2: ethernet-phy@01 { + reg = <0x01>; + }; + + phy_rgmii_0: ethernet-phy@04 { + reg = <0x04>; + }; + + phy_rgmii_1: ethernet-phy@05 { + reg = <0x05>; + }; + }; + }; + }; + }; #include "t1042si-post.dtsi" -- cgit v0.10.2 From 980b261e8c2e8b22afe08c7bab438433c44ab485 Mon Sep 17 00:00:00 2001 From: Zhang Ying-22455 Date: Wed, 1 Nov 2017 10:31:47 +0800 Subject: arm64: dts: ls1012a: correct the i2c clock to 1/4 platform pll Signed-off-by: Zhang Ying-22455 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index ea56b80..071fa88 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -380,7 +380,7 @@ #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen 4 3>; status = "disabled"; }; @@ -390,7 +390,7 @@ #size-cells = <0>; reg = <0x0 0x2190000 0x0 0x10000>; interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen 4 3>; status = "disabled"; }; -- cgit v0.10.2 From 405c970bc3056aac578feeec24b1a58056931c69 Mon Sep 17 00:00:00 2001 From: Zhang Ying-22455 Date: Wed, 1 Nov 2017 10:34:04 +0800 Subject: arm64: dts: ls208xa: correct the i2c clock to 1/2 platform pll Signed-off-by: Zhang Ying-22455 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 4dd400f..9bef9e1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -689,7 +689,7 @@ reg = <0x0 0x2000000 0x0 0x10000>; interrupts = <0 34 0x4>; /* Level high type */ clock-names = "i2c"; - clocks = <&clockgen 4 3>; + clocks = <&clockgen 4 1>; }; i2c1: i2c@2010000 { @@ -700,7 +700,7 @@ reg = <0x0 0x2010000 0x0 0x10000>; interrupts = <0 34 0x4>; /* Level high type */ clock-names = "i2c"; - clocks = <&clockgen 4 3>; + clocks = <&clockgen 4 1>; }; i2c2: i2c@2020000 { @@ -711,7 +711,7 @@ reg = <0x0 0x2020000 0x0 0x10000>; interrupts = <0 35 0x4>; /* Level high type */ clock-names = "i2c"; - clocks = <&clockgen 4 3>; + clocks = <&clockgen 4 1>; }; i2c3: i2c@2030000 { @@ -722,7 +722,7 @@ reg = <0x0 0x2030000 0x0 0x10000>; interrupts = <0 35 0x4>; /* Level high type */ clock-names = "i2c"; - clocks = <&clockgen 4 3>; + clocks = <&clockgen 4 1>; }; ifc: ifc@2240000 { -- cgit v0.10.2 From e8ac3011f1160155997ce391efa7f37cc08ae836 Mon Sep 17 00:00:00 2001 From: Zhang Ying-22455 Date: Thu, 2 Nov 2017 10:36:48 +0800 Subject: arm64: dts: ls1088a: correct the i2c clock to 1/8 platform pll Signed-off-by: Zhang Ying-22455 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index dc5d7f6..9aa4483 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -523,7 +523,7 @@ #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>; + clocks = <&clockgen 4 7>; status = "disabled"; }; @@ -533,7 +533,7 @@ #size-cells = <0>; reg = <0x0 0x2010000 0x0 0x10000>; interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>; + clocks = <&clockgen 4 7>; status = "disabled"; }; @@ -543,7 +543,7 @@ #size-cells = <0>; reg = <0x0 0x2020000 0x0 0x10000>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>; + clocks = <&clockgen 4 7>; status = "disabled"; }; @@ -553,7 +553,7 @@ #size-cells = <0>; reg = <0x0 0x2030000 0x0 0x10000>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>; + clocks = <&clockgen 4 7>; status = "disabled"; }; -- cgit v0.10.2 From 6eb1b2059b8d74a3cb99420f506960b41ef7fb5a Mon Sep 17 00:00:00 2001 From: Pankaj Bansal Date: Wed, 22 Nov 2017 19:19:10 +0530 Subject: powerpc: dts: P1010: Add endianness property to flexcan node The flexcan driver assumed that flexcan controller is big endian for powerpc architecture and little endian for other architectures. But this is not universally true. flexcan controller can be little or big endian on any architecture. Therefore the flexcan driver has been modified to check for "big-endian" device tree property for controllers that are big endian. consequently add the property to freescale P1010 SOC device tree. Signed-off-by: Pankaj Bansal Reviewed-by: Poonam Aggrwal diff --git a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi index af12ead..1b4aafc 100644 --- a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi @@ -137,12 +137,14 @@ compatible = "fsl,p1010-flexcan"; reg = <0x1c000 0x1000>; interrupts = <48 0x2 0 0>; + big-endian; }; can1: can@1d000 { compatible = "fsl,p1010-flexcan"; reg = <0x1d000 0x1000>; interrupts = <61 0x2 0 0>; + big-endian; }; L2: l2-cache-controller@20000 { -- cgit v0.10.2 From df5e585e3ff798595315306345b721f241c863ce Mon Sep 17 00:00:00 2001 From: Pankaj Bansal Date: Wed, 22 Nov 2017 19:41:34 +0530 Subject: arm: dts: Remove p1010-flexcan compatible from imx series dts The flexcan driver has been modified to check for big-endian dts property for be read/write to flexcan registers/mb. An exception to this rule is powerpc P1010RDB, which is always big-endian, even if big-endian is not present in dts. This is checked using p1010-flexcan compatible in dts. Therefore, remove p1010-flexcan compatible from imx series dts, as their flexcan core is little endian. Signed-off-by: Pankaj Bansal diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index af6af87..2ff0773 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -105,7 +105,7 @@ }; can1: can@43f88000 { - compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan"; + compatible = "fsl,imx25-flexcan"; reg = <0x43f88000 0x4000>; interrupts = <43>; clocks = <&clks 75>, <&clks 75>; @@ -114,7 +114,7 @@ }; can2: can@43f8c000 { - compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan"; + compatible = "fsl,imx25-flexcan"; reg = <0x43f8c000 0x4000>; interrupts = <44>; clocks = <&clks 76>, <&clks 76>; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 0ad893b..2e06ef8 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -1001,7 +1001,7 @@ }; can0: can@80032000 { - compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; + compatible = "fsl,imx28-flexcan"; reg = <0x80032000 0x2000>; interrupts = <8>; clocks = <&clks 58>, <&clks 58>; @@ -1010,7 +1010,7 @@ }; can1: can@80034000 { - compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; + compatible = "fsl,imx28-flexcan"; reg = <0x80034000 0x2000>; interrupts = <9>; clocks = <&clks 59>, <&clks 59>; diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index f812d58..2d4998d 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -292,7 +292,7 @@ }; can1: can@53fe4000 { - compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan"; + compatible = "fsl,imx35-flexcan"; reg = <0x53fe4000 0x1000>; clocks = <&clks 33>, <&clks 33>; clock-names = "ipg", "per"; @@ -301,7 +301,7 @@ }; can2: can@53fe8000 { - compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan"; + compatible = "fsl,imx35-flexcan"; reg = <0x53fe8000 0x1000>; clocks = <&clks 34>, <&clks 34>; clock-names = "ipg", "per"; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 0777b41..da893b5 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -526,7 +526,7 @@ }; can1: can@53fc8000 { - compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; + compatible = "fsl,imx53-flexcan"; reg = <0x53fc8000 0x4000>; interrupts = <82>; clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, @@ -536,7 +536,7 @@ }; can2: can@53fcc000 { - compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; + compatible = "fsl,imx53-flexcan"; reg = <0x53fcc000 0x4000>; interrupts = <83>; clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, -- cgit v0.10.2 From d348e6cd7077c86971ed65fa2754c9326f9b0769 Mon Sep 17 00:00:00 2001 From: Pankaj Bansal Date: Tue, 14 Nov 2017 14:23:36 +0530 Subject: arm/dts: Add nodes for flexcan devices present on LS1021A-Rev2 SoC This patch adds the device nodes for flexcan controller(s) present on LS1021A-Rev2 SoC. Signed-off-by: Pankaj Bansal Signed-off-by: Bhupesh Sharma Signed-off-by: Sakar Arora Reviewed-by: Zhengxiong Jin Reviewed-by: Poonam Aggrwal diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts index 5611a9c..f6280a6 100644 --- a/arch/arm/boot/dts/ls1021a-qds.dts +++ b/arch/arm/boot/dts/ls1021a-qds.dts @@ -344,3 +344,11 @@ &uart1 { status = "okay"; }; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts index 94d4714..777a830 100644 --- a/arch/arm/boot/dts/ls1021a-twr.dts +++ b/arch/arm/boot/dts/ls1021a-twr.dts @@ -260,3 +260,11 @@ &uart1 { status = "okay"; }; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 31b4b3b..3c8ee96 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -697,5 +697,45 @@ <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; }; + + can0: can@2a70000 { + compatible = "fsl,ls1021ar2-flexcan"; + reg = <0x0 0x2a70000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + big-endian; + status = "disabled"; + }; + + can1: can@2a80000 { + compatible = "fsl,ls1021ar2-flexcan"; + reg = <0x0 0x2a80000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + big-endian; + status = "disabled"; + }; + + can2: can@2a90000 { + compatible = "fsl,ls1021ar2-flexcan"; + reg = <0x0 0x2a90000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + big-endian; + status = "disabled"; + }; + + can3: can@2aa0000 { + compatible = "fsl,ls1021ar2-flexcan"; + reg = <0x0 0x2aa0000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + big-endian; + status = "disabled"; + }; }; }; -- cgit v0.10.2 From 247e303ccb9ce054576816a72a349b156e311d9e Mon Sep 17 00:00:00 2001 From: Camelia Groza Date: Thu, 7 Dec 2017 15:29:46 +0200 Subject: arm64: dts: add dma coherent flags for DPAA 1.x Ethernet nodes The performance is impacted if the memory is mapped as non coherent. Signed-off-by: Camelia Groza diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts index c375af4..c1d671de2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts @@ -68,6 +68,7 @@ ethernet@9 { compatible = "fsl,dpa-ethernet"; fsl,fman-mac = <&enet7>; + dma-coherent; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts index bfe2f36..87f598c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts @@ -68,6 +68,7 @@ ethernet@9 { compatible = "fsl,dpa-ethernet"; fsl,fman-mac = <&enet7>; + dma-coherent; }; }; diff --git a/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi index eb5af91..5c6be92 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi @@ -37,30 +37,37 @@ fsldpaa: fsl,dpaa { ethernet@0 { compatible = "fsl,dpa-ethernet"; fsl,fman-mac = <&enet0>; + dma-coherent; }; ethernet@1 { compatible = "fsl,dpa-ethernet"; fsl,fman-mac = <&enet1>; + dma-coherent; }; ethernet@2 { compatible = "fsl,dpa-ethernet"; fsl,fman-mac = <&enet2>; + dma-coherent; }; ethernet@3 { compatible = "fsl,dpa-ethernet"; fsl,fman-mac = <&enet3>; + dma-coherent; }; ethernet@4 { compatible = "fsl,dpa-ethernet"; fsl,fman-mac = <&enet4>; + dma-coherent; }; ethernet@5 { compatible = "fsl,dpa-ethernet"; fsl,fman-mac = <&enet5>; + dma-coherent; }; ethernet@8 { compatible = "fsl,dpa-ethernet"; fsl,fman-mac = <&enet6>; + dma-coherent; }; }; -- cgit v0.10.2 From 85464a211ccb5e3874b323623a7cf2f07bce9fc1 Mon Sep 17 00:00:00 2001 From: Camelia Groza Date: Thu, 7 Dec 2017 15:31:31 +0200 Subject: arm64: dts: ls1046a: disable Ethernet nodes 0 and 1 The Ethernet nodes 0 and 1 aren't present on LS1046A RDB platforms. Remove the nodes in order to avoid error messages at boot time. Signed-off-by: Camelia Groza diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts index 87f598c..f84e49b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts @@ -65,6 +65,12 @@ }; &fsldpaa { + ethernet@0 { + status = "disabled"; + }; + ethernet@1 { + status = "disabled"; + }; ethernet@9 { compatible = "fsl,dpa-ethernet"; fsl,fman-mac = <&enet7>; -- cgit v0.10.2