From cfeaa93f8a13ae9117ae20933a38a406de80849e Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Mon, 6 May 2013 14:30:17 +0000 Subject: genirq: Generic chip: Remove the local cur_regs() function Since we already have an irq_data_get_chip_type() function which returns a pointer to irq_chip_type, use that instead of cur_regs(). Signed-off-by: Gerlando Falauto Cc: Andrew Lunn Cc: Joey Oravec Cc: Lennert Buytenhek Cc: Russell King - ARM Linux Cc: Jason Gunthorpe Cc: Holger Brunck Cc: Ezequiel Garcia Acked-by: Grant Likely Cc: Sebastian Hesselbarth Cc: Jason Cooper Cc: Arnd Bergmann Cc: devicetree-discuss@lists.ozlabs.org Cc: Rob Herring Cc: Ben Dooks Cc: Gregory Clement Cc: Simon Guinot Cc: linux-arm-kernel@lists.infradead.org Cc: Thomas Petazzoni Cc: Jean-Francois Moine Cc: Nicolas Pitre Cc: Rob Landley Cc: Maxime Ripard Link: http://lkml.kernel.org/r/20130506142539.010164766@linutronix.de Signed-off-by: Thomas Gleixner diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index c89295a..0e6ba78 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -16,11 +16,6 @@ static LIST_HEAD(gc_list); static DEFINE_RAW_SPINLOCK(gc_lock); -static inline struct irq_chip_regs *cur_regs(struct irq_data *d) -{ - return &container_of(d->chip, struct irq_chip_type, chip)->regs; -} - /** * irq_gc_noop - NOOP function * @d: irq_data @@ -39,10 +34,11 @@ void irq_gc_noop(struct irq_data *d) void irq_gc_mask_disable_reg(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - irq_reg_writel(mask, gc->reg_base + cur_regs(d)->disable); + irq_reg_writel(mask, gc->reg_base + ct->regs.disable); gc->mask_cache &= ~mask; irq_gc_unlock(gc); } @@ -57,11 +53,12 @@ void irq_gc_mask_disable_reg(struct irq_data *d) void irq_gc_mask_set_bit(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); gc->mask_cache |= mask; - irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask); + irq_reg_writel(gc->mask_cache, gc->reg_base + ct->regs.mask); irq_gc_unlock(gc); } @@ -75,11 +72,12 @@ void irq_gc_mask_set_bit(struct irq_data *d) void irq_gc_mask_clr_bit(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); gc->mask_cache &= ~mask; - irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask); + irq_reg_writel(gc->mask_cache, gc->reg_base + ct->regs.mask); irq_gc_unlock(gc); } @@ -93,10 +91,11 @@ void irq_gc_mask_clr_bit(struct irq_data *d) void irq_gc_unmask_enable_reg(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - irq_reg_writel(mask, gc->reg_base + cur_regs(d)->enable); + irq_reg_writel(mask, gc->reg_base + ct->regs.enable); gc->mask_cache |= mask; irq_gc_unlock(gc); } @@ -108,10 +107,11 @@ void irq_gc_unmask_enable_reg(struct irq_data *d) void irq_gc_ack_set_bit(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack); + irq_reg_writel(mask, gc->reg_base + ct->regs.ack); irq_gc_unlock(gc); } @@ -122,10 +122,11 @@ void irq_gc_ack_set_bit(struct irq_data *d) void irq_gc_ack_clr_bit(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); u32 mask = ~(1 << (d->irq - gc->irq_base)); irq_gc_lock(gc); - irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack); + irq_reg_writel(mask, gc->reg_base + ct->regs.ack); irq_gc_unlock(gc); } @@ -136,11 +137,12 @@ void irq_gc_ack_clr_bit(struct irq_data *d) void irq_gc_mask_disable_reg_and_ack(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - irq_reg_writel(mask, gc->reg_base + cur_regs(d)->mask); - irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack); + irq_reg_writel(mask, gc->reg_base + ct->regs.mask); + irq_reg_writel(mask, gc->reg_base + ct->regs.ack); irq_gc_unlock(gc); } @@ -151,10 +153,11 @@ void irq_gc_mask_disable_reg_and_ack(struct irq_data *d) void irq_gc_eoi(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - irq_reg_writel(mask, gc->reg_base + cur_regs(d)->eoi); + irq_reg_writel(mask, gc->reg_base + ct->regs.eoi); irq_gc_unlock(gc); } -- cgit v0.10.2 From 899f0e66fff36ebb6dd6a83af9aa631f6cb7e0dc Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Mon, 6 May 2013 14:30:19 +0000 Subject: genirq: Generic chip: Add support for per chip type mask cache Today the same interrupt mask cache (stored within struct irq_chip_generic) is shared between all the irq_chip_type instances. As there are instances where each irq_chip_type uses a distinct mask register (as it is the case for Orion SoCs), sharing a single mask cache may be incorrect. So add a distinct pointer for each irq_chip_type, which for now points to the original mask register within irq_chip_generic. So no functional changes here. [ tglx: Minor cosmetic tweaks ] Reported-by: Joey Oravec Signed-off-by: Simon Guinot Signed-off-by: Holger Brunck Signed-off-by: Gerlando Falauto Cc: Andrew Lunn Cc: Lennert Buytenhek Cc: Russell King - ARM Linux Cc: Jason Gunthorpe Cc: Holger Brunck Cc: Ezequiel Garcia Acked-by: Grant Likely Cc: Sebastian Hesselbarth Cc: Jason Cooper Cc: Arnd Bergmann Cc: devicetree-discuss@lists.ozlabs.org Cc: Rob Herring Cc: Ben Dooks Cc: Gregory Clement Cc: Simon Guinot Cc: linux-arm-kernel@lists.infradead.org Cc: Thomas Petazzoni Cc: Jean-Francois Moine Cc: Nicolas Pitre Cc: Rob Landley Cc: Maxime Ripard Link: http://lkml.kernel.org/r/20130506142539.082226607@linutronix.de Signed-off-by: Thomas Gleixner diff --git a/include/linux/irq.h b/include/linux/irq.h index bc4e066..38709a3a 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -644,6 +644,8 @@ struct irq_chip_regs { * @regs: Register offsets for this chip * @handler: Flow handler associated with this chip * @type: Chip can handle these flow types + * @mask_cache_priv: Cached mask register private to the chip type + * @mask_cache: Pointer to cached mask register * * A irq_generic_chip can have several instances of irq_chip_type when * it requires different functions and register offsets for different @@ -654,6 +656,8 @@ struct irq_chip_type { struct irq_chip_regs regs; irq_flow_handler_t handler; u32 type; + u32 mask_cache_priv; + u32 *mask_cache; }; /** @@ -662,7 +666,7 @@ struct irq_chip_type { * @reg_base: Register base address (virtual) * @irq_base: Interrupt base nr for this chip * @irq_cnt: Number of interrupts handled by this chip - * @mask_cache: Cached mask register + * @mask_cache: Cached mask register shared between all chip types * @type_cache: Cached type register * @polarity_cache: Cached polarity register * @wake_enabled: Interrupt can wakeup from suspend diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index 0e6ba78..113d9eb 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -39,7 +39,7 @@ void irq_gc_mask_disable_reg(struct irq_data *d) irq_gc_lock(gc); irq_reg_writel(mask, gc->reg_base + ct->regs.disable); - gc->mask_cache &= ~mask; + *ct->mask_cache &= ~mask; irq_gc_unlock(gc); } @@ -57,8 +57,8 @@ void irq_gc_mask_set_bit(struct irq_data *d) u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - gc->mask_cache |= mask; - irq_reg_writel(gc->mask_cache, gc->reg_base + ct->regs.mask); + *ct->mask_cache |= mask; + irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask); irq_gc_unlock(gc); } @@ -76,8 +76,8 @@ void irq_gc_mask_clr_bit(struct irq_data *d) u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - gc->mask_cache &= ~mask; - irq_reg_writel(gc->mask_cache, gc->reg_base + ct->regs.mask); + *ct->mask_cache &= ~mask; + irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask); irq_gc_unlock(gc); } @@ -96,7 +96,7 @@ void irq_gc_unmask_enable_reg(struct irq_data *d) irq_gc_lock(gc); irq_reg_writel(mask, gc->reg_base + ct->regs.enable); - gc->mask_cache |= mask; + *ct->mask_cache |= mask; irq_gc_unlock(gc); } @@ -250,6 +250,10 @@ void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, if (flags & IRQ_GC_INIT_MASK_CACHE) gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask); + /* Initialize mask cache pointer */ + for (i = 0; i < gc->num_ct; i++) + ct[i].mask_cache = &gc->mask_cache; + for (i = gc->irq_base; msk; msk >>= 1, i++) { if (!(msk & 0x01)) continue; -- cgit v0.10.2 From af80b0fed67261dcba2ce2406db1d553d07cbe75 Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Mon, 6 May 2013 14:30:21 +0000 Subject: genirq: Generic chip: Handle separate mask registers There are cases where all irq_chip_type instances have separate mask registers, making a shared mask register cache unsuitable for the purpose. Introduce a new flag IRQ_GC_MASK_CACHE_PER_TYPE. If set, point the per chip mask pointer to the per chip private mask cache instead. [ tglx: Simplified code, renamed flag and massaged changelog ] Signed-off-by: Gerlando Falauto Cc: Andrew Lunn Cc: Joey Oravec Cc: Lennert Buytenhek Cc: Russell King - ARM Linux Cc: Jason Gunthorpe Cc: Holger Brunck Cc: Ezequiel Garcia Acked-by: Grant Likely Cc: Sebastian Hesselbarth Cc: Jason Cooper Cc: Arnd Bergmann Cc: devicetree-discuss@lists.ozlabs.org Cc: Rob Herring Cc: Ben Dooks Cc: Gregory Clement Cc: Simon Guinot Cc: linux-arm-kernel@lists.infradead.org Cc: Thomas Petazzoni Cc: Jean-Francois Moine Cc: Nicolas Pitre Cc: Rob Landley Cc: Maxime Ripard Link: http://lkml.kernel.org/r/20130506142539.152569748@linutronix.de Signed-off-by: Thomas Gleixner diff --git a/include/linux/irq.h b/include/linux/irq.h index 38709a3a..7f1f015 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -704,10 +704,12 @@ struct irq_chip_generic { * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for * irq chips which need to call irq_set_wake() on * the parent irq. Usually GPIO implementations + * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private */ enum irq_gc_flags { IRQ_GC_INIT_MASK_CACHE = 1 << 0, IRQ_GC_INIT_NESTED_LOCK = 1 << 1, + IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, }; /* Generic chip callback functions */ diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index 113d9eb..da2a941 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -241,18 +241,21 @@ void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, { struct irq_chip_type *ct = gc->chip_types; unsigned int i; + u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask; raw_spin_lock(&gc_lock); list_add_tail(&gc->list, &gc_list); raw_spin_unlock(&gc_lock); - /* Init mask cache ? */ - if (flags & IRQ_GC_INIT_MASK_CACHE) - gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask); - - /* Initialize mask cache pointer */ - for (i = 0; i < gc->num_ct; i++) - ct[i].mask_cache = &gc->mask_cache; + for (i = 0; i < gc->num_ct; i++) { + if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) { + mskptr = &ct[i].mask_cache_priv; + mskreg = ct[i].regs.mask; + } + ct[i].mask_cache = mskptr; + if (flags & IRQ_GC_INIT_MASK_CACHE) + *mskptr = irq_reg_readl(gc->reg_base + mskreg); + } for (i = gc->irq_base; msk; msk >>= 1, i++) { if (!(msk & 0x01)) -- cgit v0.10.2 From 966dc736b819999cd2d3a6408d47d33b579f7d56 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 6 May 2013 14:30:22 +0000 Subject: genirq: Generic chip: Cache per irq bit mask Cache the per irq bit mask instead of recalculating it over and over. Signed-off-by: Thomas Gleixner Cc: Thomas Petazzoni Cc: Andrew Lunn Cc: Russell King - ARM Linux Cc: Jason Cooper Cc: Arnd Bergmann Cc: Jean-Francois Moine Cc: devicetree-discuss@lists.ozlabs.org Cc: Rob Herring Cc: Jason Gunthorpe Cc: Gregory Clement Cc: Gerlando Falauto Cc: Rob Landley Acked-by: Grant Likely Cc: Maxime Ripard Cc: Ezequiel Garcia Cc: linux-arm-kernel@lists.infradead.org Cc: Sebastian Hesselbarth Link: http://lkml.kernel.org/r/20130506142539.227119865@linutronix.de Signed-off-by: Thomas Gleixner diff --git a/include/linux/irq.h b/include/linux/irq.h index 7f1f015..d5fc7f5 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -119,6 +119,7 @@ struct irq_domain; /** * struct irq_data - per irq and irq chip data passed down to chip functions + * @mask: precomputed bitmask for accessing the chip registers * @irq: interrupt number * @hwirq: hardware interrupt number, local to the interrupt domain * @node: node index useful for balancing @@ -138,6 +139,7 @@ struct irq_domain; * irq_data. */ struct irq_data { + u32 mask; unsigned int irq; unsigned long hwirq; unsigned int node; @@ -705,11 +707,13 @@ struct irq_chip_generic { * irq chips which need to call irq_set_wake() on * the parent irq. Usually GPIO implementations * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private + * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask */ enum irq_gc_flags { IRQ_GC_INIT_MASK_CACHE = 1 << 0, IRQ_GC_INIT_NESTED_LOCK = 1 << 1, IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, + IRQ_GC_NO_MASK = 1 << 3, }; /* Generic chip callback functions */ diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index da2a941..957155c 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -35,7 +35,7 @@ void irq_gc_mask_disable_reg(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct irq_chip_type *ct = irq_data_get_chip_type(d); - u32 mask = 1 << (d->irq - gc->irq_base); + u32 mask = d->mask; irq_gc_lock(gc); irq_reg_writel(mask, gc->reg_base + ct->regs.disable); @@ -54,7 +54,7 @@ void irq_gc_mask_set_bit(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct irq_chip_type *ct = irq_data_get_chip_type(d); - u32 mask = 1 << (d->irq - gc->irq_base); + u32 mask = d->mask; irq_gc_lock(gc); *ct->mask_cache |= mask; @@ -73,7 +73,7 @@ void irq_gc_mask_clr_bit(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct irq_chip_type *ct = irq_data_get_chip_type(d); - u32 mask = 1 << (d->irq - gc->irq_base); + u32 mask = d->mask; irq_gc_lock(gc); *ct->mask_cache &= ~mask; @@ -92,7 +92,7 @@ void irq_gc_unmask_enable_reg(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct irq_chip_type *ct = irq_data_get_chip_type(d); - u32 mask = 1 << (d->irq - gc->irq_base); + u32 mask = d->mask; irq_gc_lock(gc); irq_reg_writel(mask, gc->reg_base + ct->regs.enable); @@ -108,7 +108,7 @@ void irq_gc_ack_set_bit(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct irq_chip_type *ct = irq_data_get_chip_type(d); - u32 mask = 1 << (d->irq - gc->irq_base); + u32 mask = d->mask; irq_gc_lock(gc); irq_reg_writel(mask, gc->reg_base + ct->regs.ack); @@ -123,7 +123,7 @@ void irq_gc_ack_clr_bit(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct irq_chip_type *ct = irq_data_get_chip_type(d); - u32 mask = ~(1 << (d->irq - gc->irq_base)); + u32 mask = ~d->mask; irq_gc_lock(gc); irq_reg_writel(mask, gc->reg_base + ct->regs.ack); @@ -138,7 +138,7 @@ void irq_gc_mask_disable_reg_and_ack(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct irq_chip_type *ct = irq_data_get_chip_type(d); - u32 mask = 1 << (d->irq - gc->irq_base); + u32 mask = d->mask; irq_gc_lock(gc); irq_reg_writel(mask, gc->reg_base + ct->regs.mask); @@ -154,7 +154,7 @@ void irq_gc_eoi(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct irq_chip_type *ct = irq_data_get_chip_type(d); - u32 mask = 1 << (d->irq - gc->irq_base); + u32 mask = d->mask; irq_gc_lock(gc); irq_reg_writel(mask, gc->reg_base + ct->regs.eoi); @@ -172,7 +172,7 @@ void irq_gc_eoi(struct irq_data *d) int irq_gc_set_wake(struct irq_data *d, unsigned int on) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - u32 mask = 1 << (d->irq - gc->irq_base); + u32 mask = d->mask; if (!(mask & gc->wake_enabled)) return -EINVAL; @@ -264,6 +264,11 @@ void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, if (flags & IRQ_GC_INIT_NESTED_LOCK) irq_set_lockdep_class(i, &irq_nested_lock_class); + if (!(flags & IRQ_GC_NO_MASK)) { + struct irq_data *d = irq_get_irq_data(i); + + d->mask = 1 << (i - gc->irq_base); + } irq_set_chip_and_handler(i, &ct->chip, ct->handler); irq_set_chip_data(i, gc); irq_modify_status(i, clr, set); -- cgit v0.10.2 From d0051816e619f8f082582bec07ffa51bdb4f2104 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 6 May 2013 14:30:24 +0000 Subject: genirq: irqchip: Add a mask calculation function Some chips have weird bit mask access patterns instead of the linear you expect. Allow them to calculate the cached mask themself. Signed-off-by: Thomas Gleixner Cc: Thomas Petazzoni Cc: Andrew Lunn Cc: Russell King - ARM Linux Cc: Jason Cooper Cc: Arnd Bergmann Cc: Jean-Francois Moine Cc: devicetree-discuss@lists.ozlabs.org Cc: Rob Herring Cc: Jason Gunthorpe Cc: Gregory Clement Cc: Gerlando Falauto Cc: Rob Landley Acked-by: Grant Likely Cc: Maxime Ripard Cc: Ezequiel Garcia Cc: linux-arm-kernel@lists.infradead.org Cc: Sebastian Hesselbarth Link: http://lkml.kernel.org/r/20130506142539.302898834@linutronix.de Signed-off-by: Thomas Gleixner diff --git a/include/linux/irq.h b/include/linux/irq.h index d5fc7f5..ab8169f 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -296,6 +296,7 @@ static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) * @irq_suspend: function called from core code on suspend once per chip * @irq_resume: function called from core code on resume once per chip * @irq_pm_shutdown: function called from core code on shutdown once per chip + * @irq_calc_mask: Optional function to set irq_data.mask for special cases * @irq_print_chip: optional to print special chip info in show_interrupts * @flags: chip specific flags */ @@ -327,6 +328,8 @@ struct irq_chip { void (*irq_resume)(struct irq_data *data); void (*irq_pm_shutdown)(struct irq_data *data); + void (*irq_calc_mask)(struct irq_data *data); + void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); unsigned long flags; diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index 957155c..5068fe3 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -240,6 +240,7 @@ void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, unsigned int set) { struct irq_chip_type *ct = gc->chip_types; + struct irq_chip *chip = &ct->chip; unsigned int i; u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask; @@ -267,9 +268,12 @@ void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, if (!(flags & IRQ_GC_NO_MASK)) { struct irq_data *d = irq_get_irq_data(i); - d->mask = 1 << (i - gc->irq_base); + if (chip->irq_calc_mask) + chip->irq_calc_mask(d); + else + d->mask = 1 << (i - gc->irq_base); } - irq_set_chip_and_handler(i, &ct->chip, ct->handler); + irq_set_chip_and_handler(i, chip, ct->handler); irq_set_chip_data(i, gc); irq_modify_status(i, clr, set); } -- cgit v0.10.2 From 3528d82b684680b72fa31881c8c572c5a98b51de Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 6 May 2013 14:30:25 +0000 Subject: genirq: Generic chip: Split out code into separate functions Preparatory patch for linear interrupt domains. Signed-off-by: Thomas Gleixner Cc: Thomas Petazzoni Cc: Andrew Lunn Cc: Russell King - ARM Linux Cc: Jason Cooper Cc: Arnd Bergmann Cc: Jean-Francois Moine Cc: devicetree-discuss@lists.ozlabs.org Cc: Rob Herring Cc: Jason Gunthorpe Cc: Gregory Clement Cc: Gerlando Falauto Cc: Rob Landley Acked-by: Grant Likely Cc: Maxime Ripard Cc: Ezequiel Garcia Cc: linux-arm-kernel@lists.infradead.org Cc: Sebastian Hesselbarth Link: http://lkml.kernel.org/r/20130506142539.377017672@linutronix.de Signed-off-by: Thomas Gleixner diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index 5068fe3..3deb333 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -186,6 +186,19 @@ int irq_gc_set_wake(struct irq_data *d, unsigned int on) return 0; } +static void +irq_init_generic_chip(struct irq_chip_generic *gc, const char *name, + int num_ct, unsigned int irq_base, + void __iomem *reg_base, irq_flow_handler_t handler) +{ + raw_spin_lock_init(&gc->lock); + gc->num_ct = num_ct; + gc->irq_base = irq_base; + gc->reg_base = reg_base; + gc->chip_types->chip.name = name; + gc->chip_types->handler = handler; +} + /** * irq_alloc_generic_chip - Allocate a generic chip and initialize it * @name: Name of the irq chip @@ -206,17 +219,31 @@ irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base, gc = kzalloc(sz, GFP_KERNEL); if (gc) { - raw_spin_lock_init(&gc->lock); - gc->num_ct = num_ct; - gc->irq_base = irq_base; - gc->reg_base = reg_base; - gc->chip_types->chip.name = name; - gc->chip_types->handler = handler; + irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base, + handler); } return gc; } EXPORT_SYMBOL_GPL(irq_alloc_generic_chip); +static void +irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags) +{ + struct irq_chip_type *ct = gc->chip_types; + u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask; + int i; + + for (i = 0; i < gc->num_ct; i++) { + if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) { + mskptr = &ct[i].mask_cache_priv; + mskreg = ct[i].regs.mask; + } + ct[i].mask_cache = mskptr; + if (flags & IRQ_GC_INIT_MASK_CACHE) + *mskptr = irq_reg_readl(gc->reg_base + mskreg); + } +} + /* * Separate lockdep class for interrupt chip which can nest irq_desc * lock. @@ -242,21 +269,12 @@ void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, struct irq_chip_type *ct = gc->chip_types; struct irq_chip *chip = &ct->chip; unsigned int i; - u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask; raw_spin_lock(&gc_lock); list_add_tail(&gc->list, &gc_list); raw_spin_unlock(&gc_lock); - for (i = 0; i < gc->num_ct; i++) { - if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) { - mskptr = &ct[i].mask_cache_priv; - mskreg = ct[i].regs.mask; - } - ct[i].mask_cache = mskptr; - if (flags & IRQ_GC_INIT_MASK_CACHE) - *mskptr = irq_reg_readl(gc->reg_base + mskreg); - } + irq_gc_init_mask_cache(gc, flags); for (i = gc->irq_base; msk; msk >>= 1, i++) { if (!(msk & 0x01)) -- cgit v0.10.2 From 088f40b7b027dad6519712ff224a5798dd62a204 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 6 May 2013 14:30:27 +0000 Subject: genirq: Generic chip: Add linear irq domain support Provide infrastructure for irq chip implementations which work on linear irq domains. - Interface to allocate multiple generic chips which are associated to the irq domain. - Interface to get the generic chip pointer for a particular hardware interrupt in the domain. - irq domain mapping function to install the chip for a particular interrupt. Note: This lacks a removal function for now. [ Sebastian Hesselbarth: Mask cache and pointer math fixups ] Signed-off-by: Thomas Gleixner Cc: Thomas Petazzoni Cc: Andrew Lunn Cc: Russell King - ARM Linux Cc: Jason Cooper Cc: Arnd Bergmann Cc: Jean-Francois Moine Cc: devicetree-discuss@lists.ozlabs.org Cc: Rob Herring Cc: Jason Gunthorpe Cc: Gregory Clement Cc: Gerlando Falauto Cc: Rob Landley Acked-by: Grant Likely Cc: Maxime Ripard Cc: Ezequiel Garcia Cc: linux-arm-kernel@lists.infradead.org Cc: Sebastian Hesselbarth Link: http://lkml.kernel.org/r/20130506142539.450634298@linutronix.de Signed-off-by: Thomas Gleixner diff --git a/include/linux/irq.h b/include/linux/irq.h index ab8169f..af7052c 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -678,6 +678,8 @@ struct irq_chip_type { * @wake_active: Interrupt is marked as an wakeup from suspend source * @num_ct: Number of available irq_chip_type instances (usually 1) * @private: Private data for non generic chip callbacks + * @installed: bitfield to denote installed interrupts + * @domain: irq domain pointer * @list: List head for keeping track of instances * @chip_types: Array of interrupt irq_chip_types * @@ -699,6 +701,8 @@ struct irq_chip_generic { u32 wake_active; unsigned int num_ct; void *private; + unsigned long installed; + struct irq_domain *domain; struct list_head list; struct irq_chip_type chip_types[0]; }; @@ -719,6 +723,24 @@ enum irq_gc_flags { IRQ_GC_NO_MASK = 1 << 3, }; +/* + * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains + * @irqs_per_chip: Number of interrupts per chip + * @num_chips: Number of chips + * @irq_flags_to_set: IRQ* flags to set on irq setup + * @irq_flags_to_clear: IRQ* flags to clear on irq setup + * @gc_flags: Generic chip specific setup flags + * @gc: Array of pointers to generic interrupt chips + */ +struct irq_domain_chip_generic { + unsigned int irqs_per_chip; + unsigned int num_chips; + unsigned int irq_flags_to_clear; + unsigned int irq_flags_to_set; + enum irq_gc_flags gc_flags; + struct irq_chip_generic *gc[0]; +}; + /* Generic chip callback functions */ void irq_gc_noop(struct irq_data *d); void irq_gc_mask_disable_reg(struct irq_data *d); @@ -742,6 +764,14 @@ int irq_setup_alt_chip(struct irq_data *d, unsigned int type); void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, unsigned int clr, unsigned int set); +struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); +int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, + int num_ct, const char *name, + irq_flow_handler_t handler, + unsigned int clr, unsigned int set, + enum irq_gc_flags flags); + + static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) { return container_of(d->chip, struct irq_chip_type, chip); diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h index 0d5b17b..ba2c708 100644 --- a/include/linux/irqdomain.h +++ b/include/linux/irqdomain.h @@ -66,6 +66,10 @@ struct irq_domain_ops { unsigned long *out_hwirq, unsigned int *out_type); }; +extern struct irq_domain_ops irq_generic_chip_ops; + +struct irq_domain_chip_generic; + /** * struct irq_domain - Hardware interrupt number translation object * @link: Element in global irq_domain list. @@ -109,8 +113,16 @@ struct irq_domain { /* Optional device node pointer */ struct device_node *of_node; + /* Optional pointer to generic interrupt chips */ + struct irq_domain_chip_generic *gc; }; +#define IRQ_DOMAIN_MAP_LEGACY 0 /* driver allocated fixed range of irqs. + * ie. legacy 8259, gets irqs 1..15 */ +#define IRQ_DOMAIN_MAP_NOMAP 1 /* no fast reverse mapping */ +#define IRQ_DOMAIN_MAP_LINEAR 2 /* linear map of interrupts */ +#define IRQ_DOMAIN_MAP_TREE 3 /* radix tree */ + #ifdef CONFIG_IRQ_DOMAIN struct irq_domain *irq_domain_add_simple(struct device_node *of_node, unsigned int size, diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index 3deb333..8743d62 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -244,6 +245,90 @@ irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags) } } +/** + * irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain + * @d: irq domain for which to allocate chips + * @irqs_per_chip: Number of interrupts each chip handles + * @num_ct: Number of irq_chip_type instances associated with this + * @name: Name of the irq chip + * @handler: Default flow handler associated with these chips + * @clr: IRQ_* bits to clear in the mapping function + * @set: IRQ_* bits to set in the mapping function + */ +int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, + int num_ct, const char *name, + irq_flow_handler_t handler, + unsigned int clr, unsigned int set, + enum irq_gc_flags gcflags) +{ + struct irq_domain_chip_generic *dgc; + struct irq_chip_generic *gc; + int numchips, sz, i; + unsigned long flags; + void *tmp; + + if (d->gc) + return -EBUSY; + + if (d->revmap_type != IRQ_DOMAIN_MAP_LINEAR) + return -EINVAL; + + numchips = d->revmap_data.linear.size / irqs_per_chip; + if (!numchips) + return -EINVAL; + + /* Allocate a pointer, generic chip and chiptypes for each chip */ + sz = sizeof(*dgc) + numchips * sizeof(gc); + sz += numchips * (sizeof(*gc) + num_ct * sizeof(struct irq_chip_type)); + + tmp = dgc = kzalloc(sz, GFP_KERNEL); + if (!dgc) + return -ENOMEM; + dgc->irqs_per_chip = irqs_per_chip; + dgc->num_chips = numchips; + dgc->irq_flags_to_set = set; + dgc->irq_flags_to_clear = clr; + dgc->gc_flags = gcflags; + d->gc = dgc; + + /* Calc pointer to the first generic chip */ + tmp += sizeof(*dgc) + numchips * sizeof(gc); + for (i = 0; i < numchips; i++) { + /* Store the pointer to the generic chip */ + dgc->gc[i] = gc = tmp; + irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip, + NULL, handler); + gc->domain = d; + raw_spin_lock_irqsave(&gc_lock, flags); + list_add_tail(&gc->list, &gc_list); + raw_spin_unlock_irqrestore(&gc_lock, flags); + /* Calc pointer to the next generic chip */ + tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type); + } + return 0; +} +EXPORT_SYMBOL_GPL(irq_alloc_domain_generic_chips); + +/** + * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq + * @d: irq domain pointer + * @hw_irq: Hardware interrupt number + */ +struct irq_chip_generic * +irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq) +{ + struct irq_domain_chip_generic *dgc = d->gc; + int idx; + + if (!dgc) + return NULL; + idx = hw_irq / dgc->irqs_per_chip; + if (idx >= dgc->num_chips) + return NULL; + return dgc->gc[idx]; +} +EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip); + /* * Separate lockdep class for interrupt chip which can nest irq_desc * lock. @@ -251,6 +336,66 @@ irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags) static struct lock_class_key irq_nested_lock_class; /** + * irq_map_generic_chip - Map a generic chip for an irq domain + */ +static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hw_irq) +{ + struct irq_data *data = irq_get_irq_data(virq); + struct irq_domain_chip_generic *dgc = d->gc; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + struct irq_chip *chip; + unsigned long flags; + int idx; + + if (!d->gc) + return -ENODEV; + + idx = hw_irq / dgc->irqs_per_chip; + if (idx >= dgc->num_chips) + return -EINVAL; + gc = dgc->gc[idx]; + + idx = hw_irq % dgc->irqs_per_chip; + + if (test_bit(idx, &gc->installed)) + return -EBUSY; + + ct = gc->chip_types; + chip = &ct->chip; + + /* We only init the cache for the first mapping of a generic chip */ + if (!gc->installed) { + raw_spin_lock_irqsave(&gc->lock, flags); + irq_gc_init_mask_cache(gc, dgc->gc_flags); + raw_spin_unlock_irqrestore(&gc->lock, flags); + } + + /* Mark the interrupt as installed */ + set_bit(idx, &gc->installed); + + if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK) + irq_set_lockdep_class(virq, &irq_nested_lock_class); + + if (chip->irq_calc_mask) + chip->irq_calc_mask(data); + else + data->mask = 1 << idx; + + irq_set_chip_and_handler(virq, chip, ct->handler); + irq_set_chip_data(virq, gc); + irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set); + return 0; +} + +struct irq_domain_ops irq_generic_chip_ops = { + .map = irq_map_generic_chip, + .xlate = irq_domain_xlate_onetwocell, +}; +EXPORT_SYMBOL_GPL(irq_generic_chip_ops); + +/** * irq_setup_generic_chip - Setup a range of interrupts with a generic chip * @gc: Generic irq chip holding all data * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base @@ -354,6 +499,24 @@ void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, } EXPORT_SYMBOL_GPL(irq_remove_generic_chip); +static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc) +{ + unsigned int virq; + + if (!gc->domain) + return irq_get_irq_data(gc->irq_base); + + /* + * We don't know which of the irqs has been actually + * installed. Use the first one. + */ + if (!gc->installed) + return NULL; + + virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed)); + return virq ? irq_get_irq_data(virq) : NULL; +} + #ifdef CONFIG_PM static int irq_gc_suspend(void) { @@ -362,8 +525,12 @@ static int irq_gc_suspend(void) list_for_each_entry(gc, &gc_list, list) { struct irq_chip_type *ct = gc->chip_types; - if (ct->chip.irq_suspend) - ct->chip.irq_suspend(irq_get_irq_data(gc->irq_base)); + if (ct->chip.irq_suspend) { + struct irq_data *data = irq_gc_get_irq_data(gc); + + if (data) + ct->chip.irq_suspend(data); + } } return 0; } @@ -375,8 +542,12 @@ static void irq_gc_resume(void) list_for_each_entry(gc, &gc_list, list) { struct irq_chip_type *ct = gc->chip_types; - if (ct->chip.irq_resume) - ct->chip.irq_resume(irq_get_irq_data(gc->irq_base)); + if (ct->chip.irq_resume) { + struct irq_data *data = irq_gc_get_irq_data(gc); + + if (data) + ct->chip.irq_resume(data); + } } } #else @@ -391,8 +562,12 @@ static void irq_gc_shutdown(void) list_for_each_entry(gc, &gc_list, list) { struct irq_chip_type *ct = gc->chip_types; - if (ct->chip.irq_pm_shutdown) - ct->chip.irq_pm_shutdown(irq_get_irq_data(gc->irq_base)); + if (ct->chip.irq_pm_shutdown) { + struct irq_data *data = irq_gc_get_irq_data(gc); + + if (data) + ct->chip.irq_pm_shutdown(data); + } } } diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index 5a83dde..1db9e70 100644 --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -16,12 +16,6 @@ #include #include -#define IRQ_DOMAIN_MAP_LEGACY 0 /* driver allocated fixed range of irqs. - * ie. legacy 8259, gets irqs 1..15 */ -#define IRQ_DOMAIN_MAP_NOMAP 1 /* no fast reverse mapping */ -#define IRQ_DOMAIN_MAP_LINEAR 2 /* linear map of interrupts */ -#define IRQ_DOMAIN_MAP_TREE 3 /* radix tree */ - static LIST_HEAD(irq_domain_list); static DEFINE_MUTEX(irq_domain_mutex); -- cgit v0.10.2 From e8bd834f73714378ef110a64287db1b77033c8da Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Wed, 29 May 2013 03:10:52 +0100 Subject: genirq: irqchip: Add mask to block out invalid irqs Some controllers have irqs that aren't wired up and must never be used. For the generic chip attached to an irq_domain this provides a mask that can be used to block out particular irqs so that they never get mapped. Signed-off-by: Grant Likely Link: http://lkml.kernel.org/r/1369793454-19197-2-git-send-email-grant.likely@linaro.org Signed-off-by: Thomas Gleixner diff --git a/include/linux/irq.h b/include/linux/irq.h index af7052c..298a9b9 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -679,6 +679,7 @@ struct irq_chip_type { * @num_ct: Number of available irq_chip_type instances (usually 1) * @private: Private data for non generic chip callbacks * @installed: bitfield to denote installed interrupts + * @unused: bitfield to denote unused interrupts * @domain: irq domain pointer * @list: List head for keeping track of instances * @chip_types: Array of interrupt irq_chip_types @@ -702,6 +703,7 @@ struct irq_chip_generic { unsigned int num_ct; void *private; unsigned long installed; + unsigned long unused; struct irq_domain *domain; struct list_head list; struct irq_chip_type chip_types[0]; diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index 8743d62..95575d8 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -359,6 +359,9 @@ static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, idx = hw_irq % dgc->irqs_per_chip; + if (test_bit(idx, &gc->unused)) + return -ENOTSUPP; + if (test_bit(idx, &gc->installed)) return -EBUSY; -- cgit v0.10.2 From d671a605580d2caafc77f1a25bcf8435795df6fe Mon Sep 17 00:00:00 2001 From: Andreas Fenkart Date: Fri, 10 May 2013 12:21:30 +0200 Subject: genirq: Add kerneldoc for irq_disable. Document the lazy disable functionality. comment based on changelog of d209a699a0b975ad Signed-off-by: Andreas Fenkart Cc: balbi@ti.com Link: http://lkml.kernel.org/r/1368181290-1583-1-git-send-email-andreas.fenkart@streamunlimited.com Signed-off-by: Thomas Gleixner diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index cbd97ce..a3bb14f 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -213,6 +213,19 @@ void irq_enable(struct irq_desc *desc) irq_state_clr_masked(desc); } +/** + * irq_disable - Mark interupt disabled + * @desc: irq descriptor which should be disabled + * + * If the chip does not implement the irq_disable callback, we + * use a lazy disable approach. That means we mark the interrupt + * disabled, but leave the hardware unmasked. That's an + * optimization because we avoid the hardware access for the + * common case where no interrupt happens after we marked it + * disabled. If an interrupt happens, then the interrupt flow + * handler masks the line at the hardware level and marks it + * pending. + */ void irq_disable(struct irq_desc *desc) { irq_state_set_disabled(desc); -- cgit v0.10.2 From 9dbd90f17e4f380593ec5194c2a4d5e52c5f72d1 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Thu, 6 Jun 2013 18:27:09 +0200 Subject: irqchip: Add support for Marvell Orion SoCs This patch adds an irqchip driver for the main interrupt controller found on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation). Corresponding device tree documentation is also added. Signed-off-by: Sebastian Hesselbarth Acked-by: Grant Likely Cc: Rob Herring Cc: Rob Landley Cc: John Stultz Cc: Russell King Cc: Jason Cooper Cc: Andrew Lunn Cc: Thomas Petazzoni Cc: Gregory Clement Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1370536034-23956-2-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Thomas Gleixner diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt new file mode 100644 index 0000000..2c11ac7 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt @@ -0,0 +1,48 @@ +Marvell Orion SoC interrupt controllers + +* Main interrupt controller + +Required properties: +- compatible: shall be "marvell,orion-intc" +- reg: base address(es) of interrupt registers starting with CAUSE register +- interrupt-controller: identifies the node as an interrupt controller +- #interrupt-cells: number of cells to encode an interrupt source, shall be 1 + +The interrupt sources map to the corresponding bits in the interrupt +registers, i.e. +- 0 maps to bit 0 of first base address, +- 1 maps to bit 1 of first base address, +- 32 maps to bit 0 of second base address, and so on. + +Example: + intc: interrupt-controller { + compatible = "marvell,orion-intc"; + interrupt-controller; + #interrupt-cells = <1>; + /* Dove has 64 first level interrupts */ + reg = <0x20200 0x10>, <0x20210 0x10>; + }; + +* Bridge interrupt controller + +Required properties: +- compatible: shall be "marvell,orion-bridge-intc" +- reg: base address of bridge interrupt registers starting with CAUSE register +- interrupts: bridge interrupt of the main interrupt controller +- interrupt-controller: identifies the node as an interrupt controller +- #interrupt-cells: number of cells to encode an interrupt source, shall be 1 + +Optional properties: +- marvell,#interrupts: number of interrupts provided by bridge interrupt + controller, defaults to 32 if not set + +Example: + bridge_intc: interrupt-controller { + compatible = "marvell,orion-bridge-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20110 0x8>; + interrupts = <0>; + /* Dove bridge provides 5 interrupts */ + marvell,#interrupts = <5>; + }; diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 4a33351..68c3107 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -25,6 +25,11 @@ config ARM_VIC_NR The maximum number of VICs available in the system, for power management. +config ORION_IRQCHIP + bool + select IRQ_DOMAIN + select MULTI_IRQ_HANDLER + config RENESAS_INTC_IRQPIN bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index cda4cb5..55df3bd 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_ARCH_MXS) += irq-mxs.o obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o obj-$(CONFIG_METAG) += irq-metag-ext.o obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o +obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o obj-$(CONFIG_ARM_GIC) += irq-gic.o diff --git a/drivers/irqchip/irq-orion.c b/drivers/irqchip/irq-orion.c new file mode 100644 index 0000000..e51d400 --- /dev/null +++ b/drivers/irqchip/irq-orion.c @@ -0,0 +1,192 @@ +/* + * Marvell Orion SoCs IRQ chip driver. + * + * Sebastian Hesselbarth + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "irqchip.h" + +/* + * Orion SoC main interrupt controller + */ +#define ORION_IRQS_PER_CHIP 32 + +#define ORION_IRQ_CAUSE 0x00 +#define ORION_IRQ_MASK 0x04 +#define ORION_IRQ_FIQ_MASK 0x08 +#define ORION_IRQ_ENDP_MASK 0x0c + +static struct irq_domain *orion_irq_domain; + +static asmlinkage void +__exception_irq_entry orion_handle_irq(struct pt_regs *regs) +{ + struct irq_domain_chip_generic *dgc = orion_irq_domain->gc; + int n, base = 0; + + for (n = 0; n < dgc->num_chips; n++, base += ORION_IRQS_PER_CHIP) { + struct irq_chip_generic *gc = + irq_get_domain_generic_chip(orion_irq_domain, base); + u32 stat = readl_relaxed(gc->reg_base + ORION_IRQ_CAUSE) & + gc->mask_cache; + while (stat) { + u32 hwirq = ffs(stat) - 1; + u32 irq = irq_find_mapping(orion_irq_domain, + gc->irq_base + hwirq); + handle_IRQ(irq, regs); + stat &= ~(1 << hwirq); + } + } +} + +static int __init orion_irq_init(struct device_node *np, + struct device_node *parent) +{ + unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; + int n, ret, base, num_chips = 0; + struct resource r; + + /* count number of irq chips by valid reg addresses */ + while (of_address_to_resource(np, num_chips, &r) == 0) + num_chips++; + + orion_irq_domain = irq_domain_add_linear(np, + num_chips * ORION_IRQS_PER_CHIP, + &irq_generic_chip_ops, NULL); + if (!orion_irq_domain) + panic("%s: unable to add irq domain\n", np->name); + + ret = irq_alloc_domain_generic_chips(orion_irq_domain, + ORION_IRQS_PER_CHIP, 1, np->name, + handle_level_irq, clr, 0, + IRQ_GC_INIT_MASK_CACHE); + if (ret) + panic("%s: unable to alloc irq domain gc\n", np->name); + + for (n = 0, base = 0; n < num_chips; n++, base += ORION_IRQS_PER_CHIP) { + struct irq_chip_generic *gc = + irq_get_domain_generic_chip(orion_irq_domain, base); + + of_address_to_resource(np, n, &r); + + if (!request_mem_region(r.start, resource_size(&r), np->name)) + panic("%s: unable to request mem region %d", + np->name, n); + + gc->reg_base = ioremap(r.start, resource_size(&r)); + if (!gc->reg_base) + panic("%s: unable to map resource %d", np->name, n); + + gc->chip_types[0].regs.mask = ORION_IRQ_MASK; + gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; + gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; + + /* mask all interrupts */ + writel(0, gc->reg_base + ORION_IRQ_MASK); + } + + set_handle_irq(orion_handle_irq); + return 0; +} +IRQCHIP_DECLARE(orion_intc, "marvell,orion-intc", orion_irq_init); + +/* + * Orion SoC bridge interrupt controller + */ +#define ORION_BRIDGE_IRQ_CAUSE 0x00 +#define ORION_BRIDGE_IRQ_MASK 0x04 + +static void orion_bridge_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct irq_domain *d = irq_get_handler_data(irq); + struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, irq); + u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) & + gc->mask_cache; + + while (stat) { + u32 hwirq = ffs(stat) - 1; + + generic_handle_irq(irq_find_mapping(d, gc->irq_base + hwirq)); + stat &= ~(1 << hwirq); + } +} + +static int __init orion_bridge_irq_init(struct device_node *np, + struct device_node *parent) +{ + unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; + struct resource r; + struct irq_domain *domain; + struct irq_chip_generic *gc; + int ret, irq, nrirqs = 32; + + /* get optional number of interrupts provided */ + of_property_read_u32(np, "marvell,#interrupts", &nrirqs); + + domain = irq_domain_add_linear(np, nrirqs, + &irq_generic_chip_ops, NULL); + if (!domain) { + pr_err("%s: unable to add irq domain\n", np->name); + return -ENOMEM; + } + + ret = irq_alloc_domain_generic_chips(domain, nrirqs, 1, np->name, + handle_level_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE); + if (ret) { + pr_err("%s: unable to alloc irq domain gc\n", np->name); + return ret; + } + + ret = of_address_to_resource(np, 0, &r); + if (ret) { + pr_err("%s: unable to get resource\n", np->name); + return ret; + } + + if (!request_mem_region(r.start, resource_size(&r), np->name)) { + pr_err("%s: unable to request mem region\n", np->name); + return -ENOMEM; + } + + /* Map the parent interrupt for the chained handler */ + irq = irq_of_parse_and_map(np, 0); + if (irq <= 0) { + pr_err("%s: unable to parse irq\n", np->name); + return -EINVAL; + } + + gc = irq_get_domain_generic_chip(domain, 0); + gc->reg_base = ioremap(r.start, resource_size(&r)); + if (!gc->reg_base) { + pr_err("%s: unable to map resource\n", np->name); + return -ENOMEM; + } + + gc->chip_types[0].regs.ack = ORION_BRIDGE_IRQ_CAUSE; + gc->chip_types[0].regs.mask = ORION_BRIDGE_IRQ_MASK; + gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit; + gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; + gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; + + /* mask all interrupts */ + writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK); + + irq_set_handler_data(irq, domain); + irq_set_chained_handler(irq, orion_bridge_irq_handler); + + return 0; +} +IRQCHIP_DECLARE(orion_bridge_intc, + "marvell,orion-bridge-intc", orion_bridge_irq_init); -- cgit v0.10.2 From ee23871389d51e07380d23887333622fbe7d3dd9 Mon Sep 17 00:00:00 2001 From: Ivo Sieben Date: Mon, 3 Jun 2013 12:12:02 +0200 Subject: genirq: Set irq thread to RT priority on creation When a threaded irq handler is installed the irq thread is initially created on normal scheduling priority. Only after the irq thread is woken up it sets its priority to RT_FIFO MAX_USER_RT_PRIO/2 itself. This means that interrupts that occur directly after the irq handler is installed will be handled on a normal scheduling priority instead of the realtime priority that one would expect. Fix this by setting the RT priority on creation of the irq_thread. Signed-off-by: Ivo Sieben Cc: Sebastian Andrzej Siewior Cc: Steven Rostedt Link: http://lkml.kernel.org/r/1370254322-17240-1-git-send-email-meltedpianoman@gmail.com Signed-off-by: Thomas Gleixner diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index fa17855..e16caa8 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -840,9 +840,6 @@ static void irq_thread_dtor(struct callback_head *unused) static int irq_thread(void *data) { struct callback_head on_exit_work; - static const struct sched_param param = { - .sched_priority = MAX_USER_RT_PRIO/2, - }; struct irqaction *action = data; struct irq_desc *desc = irq_to_desc(action->irq); irqreturn_t (*handler_fn)(struct irq_desc *desc, @@ -854,8 +851,6 @@ static int irq_thread(void *data) else handler_fn = irq_thread_fn; - sched_setscheduler(current, SCHED_FIFO, ¶m); - init_task_work(&on_exit_work, irq_thread_dtor); task_work_add(current, &on_exit_work, false); @@ -950,6 +945,9 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) */ if (new->thread_fn && !nested) { struct task_struct *t; + static const struct sched_param param = { + .sched_priority = MAX_USER_RT_PRIO/2, + }; t = kthread_create(irq_thread, new, "irq/%d-%s", irq, new->name); @@ -957,6 +955,9 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) ret = PTR_ERR(t); goto out_mput; } + + sched_setscheduler(t, SCHED_FIFO, ¶m); + /* * We keep the reference to the task struct even if * the thread dies to avoid that the interrupt code -- cgit v0.10.2 From 6fff8314046276331314ae32cea34c6d11c440d2 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Tue, 18 Jun 2013 15:08:33 +0100 Subject: genirq: Irqchip: document gcflags arg of irq_alloc_domain_generic_chips Commit 088f40b7b027dad6519712ff224a5798dd62a204 ("genirq: Generic chip: Add linear irq domain support") missed kerneldoc for the gcflags argument of irq_alloc_domain_generic_chips(). Add it now. Signed-off-by: James Hogan Acked-by: Grant Likely Link: http://lkml.kernel.org/r/1371564513-4327-1-git-send-email-james.hogan@imgtec.com Signed-off-by: Thomas Gleixner diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index 95575d8..a746a8f 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -254,6 +254,7 @@ irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags) * @handler: Default flow handler associated with these chips * @clr: IRQ_* bits to clear in the mapping function * @set: IRQ_* bits to set in the mapping function + * @gcflags: Generic chip specific setup flags */ int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, int num_ct, const char *name, -- cgit v0.10.2 From 1f6236bfd7c38d5f9f7648fae7215e65274b9e63 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Fri, 14 Jun 2013 18:40:43 +0200 Subject: genirq: Add irq_get_trigger_type() to get IRQ flags Drivers that want to get the trigger edge/level type flags for a given interrupt have to call irq_get_irq_data(irq) to get the struct irq_data and then irqd_get_trigger_type(irq_data) to obtain the IRQ flags. This is not only error prone but also unnecessary exposes the struct irq_data to callers. It's better to have an irq_get_trigger_type() function to obtain the edge/level flags for an IRQ. Signed-off-by: Javier Martinez Canillas Acked-by: Grant Likely Cc: Linus Walleij Cc: Samuel Ortiz Cc: Jason Cooper Cc: Andrew Lunn Cc: Russell King Cc: Ralf Baechle Cc: Benjamin Herrenschmidt Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mips@linux-mips.org Link: http://lkml.kernel.org/r/1371228049-27080-2-git-send-email-javier.martinez@collabora.co.uk Signed-off-by: Thomas Gleixner diff --git a/include/linux/irq.h b/include/linux/irq.h index 298a9b9..f04d3ba 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -584,6 +584,12 @@ static inline struct msi_desc *irq_data_get_msi(struct irq_data *d) return d->msi_desc; } +static inline u32 irq_get_trigger_type(unsigned int irq) +{ + struct irq_data *d = irq_get_irq_data(irq); + return d ? irqd_get_trigger_type(d) : 0; +} + int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, struct module *owner); -- cgit v0.10.2 From fb90c22ab5e926bd35526f197097793cf479b254 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Fri, 14 Jun 2013 18:40:44 +0200 Subject: gpio: mvebu: Use irq_get_trigger_type() to get IRQ flags Use irq_get_trigger_type() to get the IRQ trigger type flags instead calling irqd_get_trigger_type(irq_get_irq_data(irq)) Signed-off-by: Javier Martinez Canillas Acked-by: Grant Likely Cc: Linus Walleij Cc: Samuel Ortiz Acked-by: Jason Cooper Cc: Andrew Lunn Cc: Russell King Cc: Ralf Baechle Cc: Benjamin Herrenschmidt Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mips@linux-mips.org Link: http://lkml.kernel.org/r/1371228049-27080-3-git-send-email-javier.martinez@collabora.co.uk Signed-off-by: Thomas Gleixner diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c index 3a4816a..80ad35e 100644 --- a/drivers/gpio/gpio-mvebu.c +++ b/drivers/gpio/gpio-mvebu.c @@ -457,7 +457,7 @@ static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) if (!(cause & (1 << i))) continue; - type = irqd_get_trigger_type(irq_get_irq_data(irq)); + type = irq_get_trigger_type(irq); if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { /* Swap polarity (race with GPIO line) */ u32 polarity; -- cgit v0.10.2 From 5dbf79d496f3a9ad141dfd1ce4a9c4d7e12c9e2c Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Fri, 14 Jun 2013 18:40:45 +0200 Subject: mfd: twl4030-irq: Use irq_get_trigger_type() to get IRQ flags Use irq_get_trigger_type() to get the IRQ trigger type flags instead calling irqd_get_trigger_type(irq_get_irq_data(irq)) Signed-off-by: Javier Martinez Canillas Acked-by: Grant Likely Cc: Linus Walleij Acked-by: Samuel Ortiz Cc: Jason Cooper Cc: Andrew Lunn Cc: Russell King Cc: Ralf Baechle Cc: Benjamin Herrenschmidt Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mips@linux-mips.org Link: http://lkml.kernel.org/r/1371228049-27080-4-git-send-email-javier.martinez@collabora.co.uk Signed-off-by: Thomas Gleixner diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c index a5f9888..9d2d1ba 100644 --- a/drivers/mfd/twl4030-irq.c +++ b/drivers/mfd/twl4030-irq.c @@ -537,16 +537,13 @@ static void twl4030_sih_bus_sync_unlock(struct irq_data *data) /* Modify only the bits we know must change */ while (edge_change) { int i = fls(edge_change) - 1; - struct irq_data *idata; int byte = i >> 2; int off = (i & 0x3) * 2; unsigned int type; - idata = irq_get_irq_data(i + agent->irq_base); - bytes[byte] &= ~(0x03 << off); - type = irqd_get_trigger_type(idata); + type = irq_get_trigger_type(i + agent->irq_base); if (type & IRQ_TYPE_EDGE_RISING) bytes[byte] |= BIT(off + 1); if (type & IRQ_TYPE_EDGE_FALLING) -- cgit v0.10.2 From 1a5595cb288411840298f25dc3d8944a90e4b5ab Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Fri, 14 Jun 2013 18:40:46 +0200 Subject: mfd: stmpe: use irq_get_trigger_type() to get IRQ flags Use irq_get_trigger_type() to get the IRQ trigger type flags instead calling irqd_get_trigger_type(irq_get_irq_data(irq)) Signed-off-by: Javier Martinez Canillas Acked-by: Grant Likely Acked-by: Linus Walleij Acked-by: Samuel Ortiz Cc: Jason Cooper Cc: Andrew Lunn Cc: Russell King Cc: Ralf Baechle Cc: Benjamin Herrenschmidt Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mips@linux-mips.org Link: http://lkml.kernel.org/r/1371228049-27080-5-git-send-email-javier.martinez@collabora.co.uk Signed-off-by: Thomas Gleixner diff --git a/drivers/mfd/stmpe.c b/drivers/mfd/stmpe.c index bbccd51..5d5e6f9 100644 --- a/drivers/mfd/stmpe.c +++ b/drivers/mfd/stmpe.c @@ -1208,8 +1208,7 @@ int stmpe_probe(struct stmpe_client_info *ci, int partnum) } stmpe->variant = stmpe_noirq_variant_info[stmpe->partnum]; } else if (pdata->irq_trigger == IRQF_TRIGGER_NONE) { - pdata->irq_trigger = - irqd_get_trigger_type(irq_get_irq_data(stmpe->irq)); + pdata->irq_trigger = irq_get_trigger_type(stmpe->irq); } ret = stmpe_chip_init(stmpe); -- cgit v0.10.2 From f88704c95b5a2634eff99e2d720031555c67fe81 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Fri, 14 Jun 2013 18:40:47 +0200 Subject: arm: orion: Use irq_get_trigger_type() to get IRQ flags Use irq_get_trigger_type() to get the IRQ trigger type flags instead calling irqd_get_trigger_type(irq_get_irq_data(irq)) Signed-off-by: Javier Martinez Canillas Cc: Grant Likely Cc: Linus Walleij Cc: Samuel Ortiz Acked-by: Jason Cooper Cc: Andrew Lunn Cc: Russell King Cc: Ralf Baechle Cc: Benjamin Herrenschmidt Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mips@linux-mips.org Link: http://lkml.kernel.org/r/1371228049-27080-6-git-send-email-javier.martinez@collabora.co.uk Signed-off-by: Thomas Gleixner diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index 249fe63..6816192 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -426,7 +426,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) if (!(cause & (1 << i))) continue; - type = irqd_get_trigger_type(irq_get_irq_data(irq)); + type = irq_get_trigger_type(irq); if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { /* Swap polarity (race with GPIO line) */ u32 polarity; -- cgit v0.10.2 From 5ebf1f29e20de9b37937f808dc2ac8dd15311450 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Fri, 14 Jun 2013 18:40:48 +0200 Subject: MIPS: octeon: Use irq_get_trigger_type() to get IRQ flags Use irq_get_trigger_type() to get the IRQ trigger type flags instead calling irqd_get_trigger_type(irq_desc_get_irq_data(irq)) Signed-off-by: Javier Martinez Canillas Acked-by: David Daney Cc: Grant Likely Cc: Linus Walleij Cc: Samuel Ortiz Cc: Jason Cooper Cc: Andrew Lunn Cc: Russell King Cc: Ralf Baechle Cc: Benjamin Herrenschmidt Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mips@linux-mips.org Link: http://lkml.kernel.org/r/1371228049-27080-7-git-send-email-javier.martinez@collabora.co.uk Signed-off-by: Thomas Gleixner diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index a22f06a..7181def 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -607,7 +607,7 @@ static void octeon_irq_ciu_gpio_ack(struct irq_data *data) static void octeon_irq_handle_gpio(unsigned int irq, struct irq_desc *desc) { - if (irqd_get_trigger_type(irq_desc_get_irq_data(desc)) & IRQ_TYPE_EDGE_BOTH) + if (irq_get_trigger_type(irq) & IRQ_TYPE_EDGE_BOTH) handle_edge_irq(irq, desc); else handle_level_irq(irq, desc); -- cgit v0.10.2 From fbab62c5cd57a6acd9ed80903532c86897d2d560 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Fri, 14 Jun 2013 18:40:49 +0200 Subject: irqdomain: Use irq_get_trigger_type() to get IRQ flags Use irq_get_trigger_type() to get the IRQ trigger type flags instead calling irqd_get_trigger_type(irq_desc_get_irq_data(virq)) Signed-off-by: Javier Martinez Canillas Acked-by: Grant Likely Cc: Linus Walleij Cc: Samuel Ortiz Cc: Jason Cooper Cc: Andrew Lunn Cc: Russell King Cc: Ralf Baechle Cc: Benjamin Herrenschmidt Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mips@linux-mips.org Link: http://lkml.kernel.org/r/1371228049-27080-8-git-send-email-javier.martinez@collabora.co.uk Signed-off-by: Thomas Gleixner diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index 1db9e70..489921e 100644 --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -687,7 +687,7 @@ unsigned int irq_create_of_mapping(struct device_node *controller, /* Set type if specified and different than the current one */ if (type != IRQ_TYPE_NONE && - type != (irqd_get_trigger_type(irq_get_irq_data(virq)))) + type != irq_get_trigger_type(virq)) irq_set_irq_type(virq, type); return virq; } -- cgit v0.10.2 From b06eb0173ef1d9366d14b4ca3e8e38dc72b03e8b Mon Sep 17 00:00:00 2001 From: Christian Ruppert Date: Tue, 25 Jun 2013 18:29:57 +0200 Subject: irqchip: Add TB10x interrupt controller driver The SOC interrupt controller driver for the Abilis Systems TB10x series of SOCs based on ARC700 CPUs. Signed-off-by: Christian Ruppert Signed-off-by: Pierrick Hascoet Cc: Vineet Gupta Cc: Grant Likely Cc: Rob Herring Cc: Rob Landley Cc: devicetree-discuss@lists.ozlabs.org Link: http://lkml.kernel.org/r/1372177797-9458-1-git-send-email-christian.ruppert@abilis.com Signed-off-by: Thomas Gleixner diff --git a/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.txt new file mode 100644 index 0000000..9d52d5a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.txt @@ -0,0 +1,38 @@ +TB10x Top Level Interrupt Controller +==================================== + +The Abilis TB10x SOC contains a custom interrupt controller. It performs +one-to-one mapping of external interrupt sources to CPU interrupts and +provides support for reconfigurable trigger modes. + +Required properties +------------------- + +- compatible: Should be "abilis,tb10x-ictl" +- reg: specifies physical base address and size of register range. +- interrupt-congroller: Identifies the node as an interrupt controller. +- #interrupt cells: Specifies the number of cells used to encode an interrupt + source connected to this controller. The value shall be 2. +- interrupt-parent: Specifies the parent interrupt controller. +- interrupts: Specifies the list of interrupt lines which are handled by + the interrupt controller in the parent controller's notation. Interrupts + are mapped one-to-one to parent interrupts. + +Example +------- + +intc: interrupt-controller { /* Parent interrupt controller */ + interrupt-controller; + #interrupt-cells = <1>; /* For example below */ + /* ... */ +}; + +tb10x_ictl: pic@2000 { /* TB10x interrupt controller */ + compatible = "abilis,tb10x-ictl"; + reg = <0x2000 0x20>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 30 31>; +}; diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 68c3107..d4d1f4b 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -38,6 +38,11 @@ config RENESAS_IRQC bool select IRQ_DOMAIN +config TB10X_IRQC + bool + select IRQ_DOMAIN + select GENERIC_IRQ_CHIP + config VERSATILE_FPGA_IRQ bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 55df3bd..8fe6ad5 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o +obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o diff --git a/drivers/irqchip/irq-tb10x.c b/drivers/irqchip/irq-tb10x.c new file mode 100644 index 0000000..7c44c99 --- /dev/null +++ b/drivers/irqchip/irq-tb10x.c @@ -0,0 +1,195 @@ +/* + * Abilis Systems interrupt controller driver + * + * Copyright (C) Abilis Systems 2012 + * + * Author: Christian Ruppert + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "irqchip.h" + +#define AB_IRQCTL_INT_ENABLE 0x00 +#define AB_IRQCTL_INT_STATUS 0x04 +#define AB_IRQCTL_SRC_MODE 0x08 +#define AB_IRQCTL_SRC_POLARITY 0x0C +#define AB_IRQCTL_INT_MODE 0x10 +#define AB_IRQCTL_INT_POLARITY 0x14 +#define AB_IRQCTL_INT_FORCE 0x18 + +#define AB_IRQCTL_MAXIRQ 32 + +static inline void ab_irqctl_writereg(struct irq_chip_generic *gc, u32 reg, + u32 val) +{ + irq_reg_writel(val, gc->reg_base + reg); +} + +static inline u32 ab_irqctl_readreg(struct irq_chip_generic *gc, u32 reg) +{ + return irq_reg_readl(gc->reg_base + reg); +} + +static int tb10x_irq_set_type(struct irq_data *data, unsigned int flow_type) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); + uint32_t im, mod, pol; + + im = data->mask; + + irq_gc_lock(gc); + + mod = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_MODE) | im; + pol = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_POLARITY) | im; + + switch (flow_type & IRQF_TRIGGER_MASK) { + case IRQ_TYPE_EDGE_FALLING: + pol ^= im; + break; + case IRQ_TYPE_LEVEL_HIGH: + mod ^= im; + break; + case IRQ_TYPE_NONE: + flow_type = IRQ_TYPE_LEVEL_LOW; + case IRQ_TYPE_LEVEL_LOW: + mod ^= im; + pol ^= im; + break; + case IRQ_TYPE_EDGE_RISING: + break; + default: + irq_gc_unlock(gc); + pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n", + __func__, data->irq); + return -EBADR; + } + + irqd_set_trigger_type(data, flow_type); + irq_setup_alt_chip(data, flow_type); + + ab_irqctl_writereg(gc, AB_IRQCTL_SRC_MODE, mod); + ab_irqctl_writereg(gc, AB_IRQCTL_SRC_POLARITY, pol); + ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, im); + + irq_gc_unlock(gc); + + return IRQ_SET_MASK_OK; +} + +static void tb10x_irq_cascade(unsigned int irq, struct irq_desc *desc) +{ + struct irq_domain *domain = irq_desc_get_handler_data(desc); + + generic_handle_irq(irq_find_mapping(domain, irq)); +} + +static int __init of_tb10x_init_irq(struct device_node *ictl, + struct device_node *parent) +{ + int i, ret, nrirqs = of_irq_count(ictl); + struct resource mem; + struct irq_chip_generic *gc; + struct irq_domain *domain; + void __iomem *reg_base; + + if (of_address_to_resource(ictl, 0, &mem)) { + pr_err("%s: No registers declared in DeviceTree.\n", + ictl->name); + return -EINVAL; + } + + if (!request_mem_region(mem.start, resource_size(&mem), + ictl->name)) { + pr_err("%s: Request mem region failed.\n", ictl->name); + return -EBUSY; + } + + reg_base = ioremap(mem.start, resource_size(&mem)); + if (!reg_base) { + ret = -EBUSY; + pr_err("%s: ioremap failed.\n", ictl->name); + goto ioremap_fail; + } + + domain = irq_domain_add_linear(ictl, AB_IRQCTL_MAXIRQ, + &irq_generic_chip_ops, NULL); + if (!domain) { + ret = -ENOMEM; + pr_err("%s: Could not register interrupt domain.\n", + ictl->name); + goto irq_domain_add_fail; + } + + ret = irq_alloc_domain_generic_chips(domain, AB_IRQCTL_MAXIRQ, + 2, ictl->name, handle_level_irq, + IRQ_NOREQUEST, IRQ_NOPROBE, + IRQ_GC_INIT_MASK_CACHE); + if (ret) { + pr_err("%s: Could not allocate generic interrupt chip.\n", + ictl->name); + goto gc_alloc_fail; + } + + gc = domain->gc->gc[0]; + gc->reg_base = reg_base; + + gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; + gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; + gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; + gc->chip_types[0].chip.irq_set_type = tb10x_irq_set_type; + gc->chip_types[0].regs.mask = AB_IRQCTL_INT_ENABLE; + + gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; + gc->chip_types[1].chip.name = gc->chip_types[0].chip.name; + gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit; + gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit; + gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit; + gc->chip_types[1].chip.irq_set_type = tb10x_irq_set_type; + gc->chip_types[1].regs.ack = AB_IRQCTL_INT_STATUS; + gc->chip_types[1].regs.mask = AB_IRQCTL_INT_ENABLE; + gc->chip_types[1].handler = handle_edge_irq; + + for (i = 0; i < nrirqs; i++) { + unsigned int irq = irq_of_parse_and_map(ictl, i); + + irq_set_handler_data(irq, domain); + irq_set_chained_handler(irq, tb10x_irq_cascade); + } + + ab_irqctl_writereg(gc, AB_IRQCTL_INT_ENABLE, 0); + ab_irqctl_writereg(gc, AB_IRQCTL_INT_MODE, 0); + ab_irqctl_writereg(gc, AB_IRQCTL_INT_POLARITY, 0); + ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, ~0UL); + + return 0; + +gc_alloc_fail: + irq_domain_remove(domain); +irq_domain_add_fail: + iounmap(reg_base); +ioremap_fail: + release_mem_region(mem.start, resource_size(&mem)); + return ret; +} +IRQCHIP_DECLARE(tb10x_intc, "abilis,tb10x-ictl", of_tb10x_init_irq); -- cgit v0.10.2 From 292ec080491d87c888c29c5e161c10eb86e5961e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 26 Jun 2013 09:18:48 +0200 Subject: irqchip: Add support for ARMv7-M NVIC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This interrupt controller is integrated in all Cortex-M3 and Cortex-M4 machines. Support for this controller appeared in Catalin's Cortex tree based on 2.6.33 but was nearly completely rewritten. Signed-off-by: Uwe Kleine-König Acked-by: Catalin Marinas Acked-by: Arnd Bergmann Acked-by: Grant Likely Cc: linux-arm-kernel@lists.infradead.org Cc: Jonathan Austin Cc: kernel@pengutronix.de Link: http://lkml.kernel.org/r/1372231128-11802-1-git-send-email-u.kleine-koenig@pengutronix.de Signed-off-by: Thomas Gleixner diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index d4d1f4b..1fea003 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -10,6 +10,11 @@ config ARM_GIC config GIC_NON_BANKED bool +config ARM_NVIC + bool + select IRQ_DOMAIN + select GENERIC_IRQ_CHIP + config ARM_VIC bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 8fe6ad5..2065ef6 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o obj-$(CONFIG_ARM_GIC) += irq-gic.o +obj-$(CONFIG_ARM_NVIC) += irq-nvic.o obj-$(CONFIG_ARM_VIC) += irq-vic.o obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o diff --git a/drivers/irqchip/irq-nvic.c b/drivers/irqchip/irq-nvic.c new file mode 100644 index 0000000..8d0c8b3 --- /dev/null +++ b/drivers/irqchip/irq-nvic.c @@ -0,0 +1,117 @@ +/* + * drivers/irq/irq-nvic.c + * + * Copyright (C) 2008 ARM Limited, All Rights Reserved. + * Copyright (C) 2013 Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Support for the Nested Vectored Interrupt Controller found on the + * ARMv7-M CPUs (Cortex-M3/M4) + */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "irqchip.h" + +#define NVIC_ISER 0x000 +#define NVIC_ICER 0x080 +#define NVIC_IPR 0x300 + +#define NVIC_MAX_BANKS 16 +/* + * Each bank handles 32 irqs. Only the 16th (= last) bank handles only + * 16 irqs. + */ +#define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16) + +static struct irq_domain *nvic_irq_domain; + +asmlinkage void __exception_irq_entry +nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs) +{ + unsigned int irq = irq_linear_revmap(nvic_irq_domain, hwirq); + + handle_IRQ(irq, regs); +} + +static void nvic_eoi(struct irq_data *d) +{ + /* + * This is a no-op as end of interrupt is signaled by the exception + * return sequence. + */ +} + +static int __init nvic_of_init(struct device_node *node, + struct device_node *parent) +{ + unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; + unsigned int irqs, i, ret, numbanks; + void __iomem *nvic_base; + + numbanks = (readl_relaxed(V7M_SCS_ICTR) & + V7M_SCS_ICTR_INTLINESNUM_MASK) + 1; + + nvic_base = of_iomap(node, 0); + if (!nvic_base) { + pr_warn("unable to map nvic registers\n"); + return -ENOMEM; + } + + irqs = numbanks * 32; + if (irqs > NVIC_MAX_IRQ) + irqs = NVIC_MAX_IRQ; + + nvic_irq_domain = + irq_domain_add_linear(node, irqs, &irq_generic_chip_ops, NULL); + if (!nvic_irq_domain) { + pr_warn("Failed to allocate irq domain\n"); + return -ENOMEM; + } + + ret = irq_alloc_domain_generic_chips(nvic_irq_domain, 32, numbanks, + "nvic_irq", handle_fasteoi_irq, + clr, 0, IRQ_GC_INIT_MASK_CACHE); + if (ret) { + pr_warn("Failed to allocate irq chips\n"); + irq_domain_remove(nvic_irq_domain); + return ret; + } + + for (i = 0; i < numbanks; ++i) { + struct irq_chip_generic *gc; + + gc = irq_get_domain_generic_chip(nvic_irq_domain, 32 * i); + gc->reg_base = nvic_base + 4 * i; + gc->chip_types[0].regs.enable = NVIC_ISER; + gc->chip_types[0].regs.disable = NVIC_ICER; + gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; + gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; + gc->chip_types[0].chip.irq_eoi = nvic_eoi; + + /* disable interrupts */ + writel_relaxed(~0, gc->reg_base + NVIC_ICER); + } + + /* Set priority on all interrupts */ + for (i = 0; i < irqs; i += 4) + writel_relaxed(0, nvic_base + NVIC_IPR + i); + + return 0; +} +IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init); -- cgit v0.10.2 From b8394dee787bbd7d52614b7ca44ea7aa05feb9ad Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Wed, 26 Jun 2013 17:06:37 +0530 Subject: irqchip: exynos-combiner: Staticize combiner_init combiner_init() is referenced only in this file. Make it static. Signed-off-by: Sachin Kamat Cc: linux-arm-kernel@lists.infradead.org Cc: kgene.kim@samsung.com Cc: t.figa@samsung.com Cc: arnd@arndb.de Cc: patches@linaro.org Link: http://lkml.kernel.org/r/1372246597-32323-2-git-send-email-sachin.kamat@linaro.org Signed-off-by: Thomas Gleixner diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c index a9d2b2f..4c68265 100644 --- a/drivers/irqchip/exynos-combiner.c +++ b/drivers/irqchip/exynos-combiner.c @@ -204,10 +204,10 @@ static unsigned int combiner_lookup_irq(int group) return 0; } -void __init combiner_init(void __iomem *combiner_base, - struct device_node *np, - unsigned int max_nr, - int irq_base) +static void __init combiner_init(void __iomem *combiner_base, + struct device_node *np, + unsigned int max_nr, + int irq_base) { int i, irq; unsigned int nr_irq; -- cgit v0.10.2 From 2779db8d37d4b542d9ca2575f5f178dbeaca6c86 Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Fri, 28 Jun 2013 02:40:30 +0100 Subject: genirq: Fix can_request_irq() for IRQs without an action Commit 02725e7471b8 ('genirq: Use irq_get/put functions'), inadvertently changed can_request_irq() to return 0 for IRQs that have no action. This causes pcibios_lookup_irq() to select only IRQs that already have an action with IRQF_SHARED set, or to fail if there are none. Change can_request_irq() to return 1 for IRQs that have no action (if the first two conditions are met). Reported-by: Bjarni Ingi Gislason Tested-by: Bjarni Ingi Gislason (against 3.2) Signed-off-by: Ben Hutchings Cc: 709647@bugs.debian.org Cc: stable@vger.kernel.org # 2.6.39+ Link: http://bugs.debian.org/709647 Link: http://lkml.kernel.org/r/1372383630.23847.40.camel@deadeye.wl.decadent.org.uk Signed-off-by: Thomas Gleixner diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index e16caa8..514bcfd 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -555,9 +555,9 @@ int can_request_irq(unsigned int irq, unsigned long irqflags) return 0; if (irq_settings_can_request(desc)) { - if (desc->action) - if (irqflags & desc->action->flags & IRQF_SHARED) - canrequest =1; + if (!desc->action || + irqflags & desc->action->flags & IRQF_SHARED) + canrequest = 1; } irq_put_desc_unlock(desc, flags); return canrequest; -- cgit v0.10.2 From d55f0cc4c9a70e3105f1e813ab5f221a65ac2ec3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 28 Jun 2013 00:23:09 -0300 Subject: genirq: generic-chip: Export some irq_gc_ functions When building imx_v6_v7_defconfig with imx-drm drivers selected as modules, we get the following build errors: ERROR: "irq_gc_mask_clr_bit" [drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.ko] undefined! ERROR: "irq_gc_mask_set_bit" [drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.ko] undefined! ERROR: "irq_gc_ack_set_bit" [drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.ko] undefined! Export the required functions to avoid this problem. Signed-off-by: Fabio Estevam Cc: shawn.guo@linaro.org Cc: kernel@pengutronix.de Link: http://lkml.kernel.org/r/1372389789-7048-1-git-send-email-festevam@gmail.com Signed-off-by: Thomas Gleixner diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index a746a8f..76ea748 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -62,6 +62,7 @@ void irq_gc_mask_set_bit(struct irq_data *d) irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask); irq_gc_unlock(gc); } +EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit); /** * irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register @@ -81,6 +82,7 @@ void irq_gc_mask_clr_bit(struct irq_data *d) irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask); irq_gc_unlock(gc); } +EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit); /** * irq_gc_unmask_enable_reg - Unmask chip via enable register @@ -115,6 +117,7 @@ void irq_gc_ack_set_bit(struct irq_data *d) irq_reg_writel(mask, gc->reg_base + ct->regs.ack); irq_gc_unlock(gc); } +EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit); /** * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit -- cgit v0.10.2 From ccc414f83914178c7ab04ac4d4f0331fe4c37231 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Fri, 28 Jun 2013 11:45:15 +0200 Subject: genirq: Add the generic chip to the genirq docbook Signed-off-by: Thomas Gleixner Cc: Randy Dunlap diff --git a/Documentation/DocBook/genericirq.tmpl b/Documentation/DocBook/genericirq.tmpl index b342234..d16d21b 100644 --- a/Documentation/DocBook/genericirq.tmpl +++ b/Documentation/DocBook/genericirq.tmpl @@ -464,6 +464,19 @@ if (desc->irq_data.chip->irq_eoi) protected via desc->lock, by the generic layer. + + + Generic interrupt chip + + To avoid copies of identical implementations of irq chips the + core provides a configurable generic interrupt chip + implementation. Developers should check carefuly whether the + generic chip fits their needs before implementing the same + functionality slightly different themself. + +!Ekernel/irq/generic-chip.c + + Structures diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index 76ea748..1c39ecc 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -45,7 +45,7 @@ void irq_gc_mask_disable_reg(struct irq_data *d) } /** - * irq_gc_mask_set_mask_bit - Mask chip via setting bit in mask register + * irq_gc_mask_set_bit - Mask chip via setting bit in mask register * @d: irq_data * * Chip has a single mask register. Values of this register are cached @@ -65,7 +65,7 @@ void irq_gc_mask_set_bit(struct irq_data *d) EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit); /** - * irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register + * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register * @d: irq_data * * Chip has a single mask register. Values of this register are cached @@ -167,7 +167,8 @@ void irq_gc_eoi(struct irq_data *d) /** * irq_gc_set_wake - Set/clr wake bit for an interrupt - * @d: irq_data + * @d: irq_data + * @on: Indicates whether the wake bit should be set or cleared * * For chips where the wake from suspend functionality is not * configured in a separate register and the wakeup active state is @@ -339,7 +340,7 @@ EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip); */ static struct lock_class_key irq_nested_lock_class; -/** +/* * irq_map_generic_chip - Map a generic chip for an irq domain */ static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, @@ -454,7 +455,7 @@ EXPORT_SYMBOL_GPL(irq_setup_generic_chip); /** * irq_setup_alt_chip - Switch to alternative chip * @d: irq_data for this interrupt - * @type Flow type to be initialized + * @type: Flow type to be initialized * * Only to be called from chip->irq_set_type() callbacks. */ -- cgit v0.10.2 From d2e08473f2488d53a71c2f53455f934ec6c44c53 Mon Sep 17 00:00:00 2001 From: Davidlohr Bueso Date: Tue, 30 Apr 2013 11:46:09 -0700 Subject: softirq: Use _RET_IP_ Use the already defined macro to pass the function return address. Signed-off-by: Davidlohr Bueso Cc: Frederic Weisbecker Link: http://lkml.kernel.org/r/1367347569.1784.3.camel@buesod1.americas.hpqcorp.net Signed-off-by: Thomas Gleixner diff --git a/kernel/softirq.c b/kernel/softirq.c index b5197dc..a5f8836 100644 --- a/kernel/softirq.c +++ b/kernel/softirq.c @@ -127,8 +127,7 @@ static inline void __local_bh_disable(unsigned long ip, unsigned int cnt) void local_bh_disable(void) { - __local_bh_disable((unsigned long)__builtin_return_address(0), - SOFTIRQ_DISABLE_OFFSET); + __local_bh_disable(_RET_IP_, SOFTIRQ_DISABLE_OFFSET); } EXPORT_SYMBOL(local_bh_disable); @@ -139,7 +138,7 @@ static void __local_bh_enable(unsigned int cnt) WARN_ON_ONCE(!irqs_disabled()); if (softirq_count() == cnt) - trace_softirqs_on((unsigned long)__builtin_return_address(0)); + trace_softirqs_on(_RET_IP_); sub_preempt_count(cnt); } @@ -184,7 +183,7 @@ static inline void _local_bh_enable_ip(unsigned long ip) void local_bh_enable(void) { - _local_bh_enable_ip((unsigned long)__builtin_return_address(0)); + _local_bh_enable_ip(_RET_IP_); } EXPORT_SYMBOL(local_bh_enable); @@ -223,8 +222,7 @@ asmlinkage void __do_softirq(void) pending = local_softirq_pending(); account_irq_enter_time(current); - __local_bh_disable((unsigned long)__builtin_return_address(0), - SOFTIRQ_OFFSET); + __local_bh_disable(_RET_IP_, SOFTIRQ_OFFSET); lockdep_softirq_enter(); cpu = smp_processor_id(); -- cgit v0.10.2