From aedf24ff354e3d8f32f0264edcb37f07a1826f59 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 14 Jan 2015 11:50:20 +1000 Subject: drm/nouveau/ce: rename from copy (no binary change) Switch to NVIDIA's name for the device. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index d5da658..0fe2091 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -129,11 +129,11 @@ struct nv_device_v0 { #define NV_DEVICE_V0_DISABLE_CIPHER 0x0000001000000000ULL #define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL #define NV_DEVICE_V0_DISABLE_PPP 0x0000004000000000ULL -#define NV_DEVICE_V0_DISABLE_COPY0 0x0000008000000000ULL -#define NV_DEVICE_V0_DISABLE_COPY1 0x0000010000000000ULL +#define NV_DEVICE_V0_DISABLE_CE0 0x0000008000000000ULL +#define NV_DEVICE_V0_DISABLE_CE1 0x0000010000000000ULL #define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL #define NV_DEVICE_V0_DISABLE_VENC 0x0000040000000000ULL -#define NV_DEVICE_V0_DISABLE_COPY2 0x0000080000000000ULL +#define NV_DEVICE_V0_DISABLE_CE2 0x0000080000000000ULL #define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL #define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL __u64 disable; /* disable particular subsystems */ diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h index cefa877..952e36c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h @@ -52,9 +52,9 @@ enum nv_subdev_type { NVDEV_ENGINE_CIPHER, NVDEV_ENGINE_BSP, NVDEV_ENGINE_PPP, - NVDEV_ENGINE_COPY0, - NVDEV_ENGINE_COPY1, - NVDEV_ENGINE_COPY2, + NVDEV_ENGINE_CE0, + NVDEV_ENGINE_CE1, + NVDEV_ENGINE_CE2, NVDEV_ENGINE_VIC, NVDEV_ENGINE_VENC, NVDEV_ENGINE_DISP, diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h new file mode 100644 index 0000000..639d0fd --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h @@ -0,0 +1,13 @@ +#ifndef __NVKM_CE_H__ +#define __NVKM_CE_H__ + +void nva3_ce_intr(struct nouveau_subdev *); + +extern struct nouveau_oclass nva3_ce_oclass; +extern struct nouveau_oclass nvc0_ce0_oclass; +extern struct nouveau_oclass nvc0_ce1_oclass; +extern struct nouveau_oclass nve0_ce0_oclass; +extern struct nouveau_oclass nve0_ce1_oclass; +extern struct nouveau_oclass nve0_ce2_oclass; + +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/copy.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/copy.h deleted file mode 100644 index 316a28a..0000000 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/copy.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __NOUVEAU_COPY_H__ -#define __NOUVEAU_COPY_H__ - -void nva3_copy_intr(struct nouveau_subdev *); - -extern struct nouveau_oclass nva3_copy_oclass; -extern struct nouveau_oclass nvc0_copy0_oclass; -extern struct nouveau_oclass nvc0_copy1_oclass; -extern struct nouveau_oclass nve0_copy0_oclass; -extern struct nouveau_oclass nve0_copy1_oclass; -extern struct nouveau_oclass nve0_copy2_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild index aad171d..71d6542 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild @@ -3,7 +3,7 @@ nvkm-y += nvkm/engine/xtensa.o include $(src)/nvkm/engine/bsp/Kbuild include $(src)/nvkm/engine/cipher/Kbuild -include $(src)/nvkm/engine/copy/Kbuild +include $(src)/nvkm/engine/ce/Kbuild include $(src)/nvkm/engine/device/Kbuild include $(src)/nvkm/engine/disp/Kbuild include $(src)/nvkm/engine/dmaobj/Kbuild diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild new file mode 100644 index 0000000..834523d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild @@ -0,0 +1,3 @@ +nvkm-y += nvkm/engine/ce/nva3.o +nvkm-y += nvkm/engine/ce/nvc0.o +nvkm-y += nvkm/engine/ce/nve0.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/com.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/com.fuc new file mode 100644 index 0000000..fcc4ba1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/com.fuc @@ -0,0 +1,871 @@ +/* fuc microcode for copy engine on nva3- chipsets + * + * Copyright 2011 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +/* To build for nva3:nvc0 + * m4 -DNVA3 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nva3_copy.fuc.h + * + * To build for nvc0- + * m4 -DNVC0 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_copy.fuc.h + */ + +#ifdef NVA3 +.section #nva3_pce_data +#else +.section #nvc0_pce_data +#endif + +ctx_object: .b32 0 +#ifdef NVA3 +ctx_dma: +ctx_dma_query: .b32 0 +ctx_dma_src: .b32 0 +ctx_dma_dst: .b32 0 +#endif +.equ #ctx_dma_count 3 +ctx_query_address_high: .b32 0 +ctx_query_address_low: .b32 0 +ctx_query_counter: .b32 0 +ctx_src_address_high: .b32 0 +ctx_src_address_low: .b32 0 +ctx_src_pitch: .b32 0 +ctx_src_tile_mode: .b32 0 +ctx_src_xsize: .b32 0 +ctx_src_ysize: .b32 0 +ctx_src_zsize: .b32 0 +ctx_src_zoff: .b32 0 +ctx_src_xoff: .b32 0 +ctx_src_yoff: .b32 0 +ctx_src_cpp: .b32 0 +ctx_dst_address_high: .b32 0 +ctx_dst_address_low: .b32 0 +ctx_dst_pitch: .b32 0 +ctx_dst_tile_mode: .b32 0 +ctx_dst_xsize: .b32 0 +ctx_dst_ysize: .b32 0 +ctx_dst_zsize: .b32 0 +ctx_dst_zoff: .b32 0 +ctx_dst_xoff: .b32 0 +ctx_dst_yoff: .b32 0 +ctx_dst_cpp: .b32 0 +ctx_format: .b32 0 +ctx_swz_const0: .b32 0 +ctx_swz_const1: .b32 0 +ctx_xcnt: .b32 0 +ctx_ycnt: .b32 0 +.align 256 + +dispatch_table: +// mthd 0x0000, NAME +.b16 0x000 1 +.b32 #ctx_object ~0xffffffff +// mthd 0x0100, NOP +.b16 0x040 1 +.b32 0x00010000 + #cmd_nop ~0xffffffff +// mthd 0x0140, PM_TRIGGER +.b16 0x050 1 +.b32 0x00010000 + #cmd_pm_trigger ~0xffffffff +#ifdef NVA3 +// mthd 0x0180-0x018c, DMA_ +.b16 0x060 #ctx_dma_count +dispatch_dma: +.b32 0x00010000 + #cmd_dma ~0xffffffff +.b32 0x00010000 + #cmd_dma ~0xffffffff +.b32 0x00010000 + #cmd_dma ~0xffffffff +#endif +// mthd 0x0200-0x0218, SRC_TILE +.b16 0x80 7 +.b32 #ctx_src_tile_mode ~0x00000fff +.b32 #ctx_src_xsize ~0x0007ffff +.b32 #ctx_src_ysize ~0x00001fff +.b32 #ctx_src_zsize ~0x000007ff +.b32 #ctx_src_zoff ~0x00000fff +.b32 #ctx_src_xoff ~0x0007ffff +.b32 #ctx_src_yoff ~0x00001fff +// mthd 0x0220-0x0238, DST_TILE +.b16 0x88 7 +.b32 #ctx_dst_tile_mode ~0x00000fff +.b32 #ctx_dst_xsize ~0x0007ffff +.b32 #ctx_dst_ysize ~0x00001fff +.b32 #ctx_dst_zsize ~0x000007ff +.b32 #ctx_dst_zoff ~0x00000fff +.b32 #ctx_dst_xoff ~0x0007ffff +.b32 #ctx_dst_yoff ~0x00001fff +// mthd 0x0300-0x0304, EXEC, WRCACHE_FLUSH +.b16 0xc0 2 +.b32 0x00010000 + #cmd_exec ~0xffffffff +.b32 0x00010000 + #cmd_wrcache_flush ~0xffffffff +// mthd 0x030c-0x0340, various stuff +.b16 0xc3 14 +.b32 #ctx_src_address_high ~0x000000ff +.b32 #ctx_src_address_low ~0xffffffff +.b32 #ctx_dst_address_high ~0x000000ff +.b32 #ctx_dst_address_low ~0xffffffff +.b32 #ctx_src_pitch ~0x0007ffff +.b32 #ctx_dst_pitch ~0x0007ffff +.b32 #ctx_xcnt ~0x0000ffff +.b32 #ctx_ycnt ~0x00001fff +.b32 #ctx_format ~0x0333ffff +.b32 #ctx_swz_const0 ~0xffffffff +.b32 #ctx_swz_const1 ~0xffffffff +.b32 #ctx_query_address_high ~0x000000ff +.b32 #ctx_query_address_low ~0xffffffff +.b32 #ctx_query_counter ~0xffffffff +.b16 0x800 0 + +#ifdef NVA3 +.section #nva3_pce_code +#else +.section #nvc0_pce_code +#endif + +main: + clear b32 $r0 + mov $sp $r0 + + // setup i0 handler and route fifo and ctxswitch to it + mov $r1 #ih + mov $iv0 $r1 + mov $r1 0x400 + movw $r2 0xfff3 + sethi $r2 0 + iowr I[$r1 + 0x300] $r2 + + // enable interrupts + or $r2 0xc + iowr I[$r1] $r2 + bset $flags ie0 + + // enable fifo access and context switching + mov $r1 0x1200 + mov $r2 3 + iowr I[$r1] $r2 + + // sleep forever, waking for interrupts + bset $flags $p0 + spin: + sleep $p0 + bra #spin + +// i0 handler +ih: + iord $r1 I[$r0 + 0x200] + + and $r2 $r1 0x00000008 + bra e #ih_no_chsw + call #chsw + ih_no_chsw: + and $r2 $r1 0x00000004 + bra e #ih_no_cmd + call #dispatch + + ih_no_cmd: + and $r1 $r1 0x0000000c + iowr I[$r0 + 0x100] $r1 + iret + +// $p1 direction (0 = unload, 1 = load) +// $r3 channel +swctx: + mov $r4 0x7700 + mov $xtargets $r4 +#ifdef NVA3 + // target 7 hardcoded to ctx dma object + mov $xdbase $r0 +#else + // read SCRATCH3 to decide if we are PCOPY0 or PCOPY1 + mov $r4 0x2100 + iord $r4 I[$r4 + 0] + and $r4 1 + shl b32 $r4 4 + add b32 $r4 0x30 + + // channel is in vram + mov $r15 0x61c + shl b32 $r15 6 + mov $r5 0x114 + iowrs I[$r15] $r5 + + // read 16-byte PCOPYn info, containing context pointer, from channel + shl b32 $r5 $r3 4 + add b32 $r5 2 + mov $xdbase $r5 + mov $r5 $sp + // get a chunk of stack space, aligned to 256 byte boundary + sub b32 $r5 0x100 + mov $r6 0xff + not b32 $r6 + and $r5 $r6 + sethi $r5 0x00020000 + xdld $r4 $r5 + xdwait + sethi $r5 0 + + // set context pointer, from within channel VM + mov $r14 0 + iowrs I[$r15] $r14 + ld b32 $r4 D[$r5 + 0] + shr b32 $r4 8 + ld b32 $r6 D[$r5 + 4] + shl b32 $r6 24 + or $r4 $r6 + mov $xdbase $r4 +#endif + // 256-byte context, at start of data segment + mov b32 $r4 $r0 + sethi $r4 0x60000 + + // swap! + bra $p1 #swctx_load + xdst $r0 $r4 + bra #swctx_done + swctx_load: + xdld $r0 $r4 + swctx_done: + xdwait + ret + +chsw: + // read current channel + mov $r2 0x1400 + iord $r3 I[$r2] + + // if it's active, unload it and return + xbit $r15 $r3 0x1e + bra e #chsw_no_unload + bclr $flags $p1 + call #swctx + bclr $r3 0x1e + iowr I[$r2] $r3 + mov $r4 1 + iowr I[$r2 + 0x200] $r4 + ret + + // read next channel + chsw_no_unload: + iord $r3 I[$r2 + 0x100] + + // is there a channel waiting to be loaded? + xbit $r13 $r3 0x1e + bra e #chsw_finish_load + bset $flags $p1 + call #swctx +#ifdef NVA3 + // load dma objects back into TARGET regs + mov $r5 #ctx_dma + mov $r6 #ctx_dma_count + chsw_load_ctx_dma: + ld b32 $r7 D[$r5 + $r6 * 4] + add b32 $r8 $r6 0x180 + shl b32 $r8 8 + iowr I[$r8] $r7 + sub b32 $r6 1 + bra nc #chsw_load_ctx_dma +#endif + chsw_finish_load: + mov $r3 2 + iowr I[$r2 + 0x200] $r3 + ret + +dispatch: + // read incoming fifo command + mov $r3 0x1900 + iord $r2 I[$r3 + 0x100] + iord $r3 I[$r3 + 0x000] + and $r4 $r2 0x7ff + // $r2 will be used to store exception data + shl b32 $r2 0x10 + + // lookup method in the dispatch table, ILLEGAL_MTHD if not found + mov $r5 #dispatch_table + clear b32 $r6 + clear b32 $r7 + dispatch_loop: + ld b16 $r6 D[$r5 + 0] + ld b16 $r7 D[$r5 + 2] + add b32 $r5 4 + cmpu b32 $r4 $r6 + bra c #dispatch_illegal_mthd + add b32 $r7 $r6 + cmpu b32 $r4 $r7 + bra c #dispatch_valid_mthd + sub b32 $r7 $r6 + shl b32 $r7 3 + add b32 $r5 $r7 + bra #dispatch_loop + + // ensure no bits set in reserved fields, INVALID_BITFIELD + dispatch_valid_mthd: + sub b32 $r4 $r6 + shl b32 $r4 3 + add b32 $r4 $r5 + ld b32 $r5 D[$r4 + 4] + and $r5 $r3 + cmpu b32 $r5 0 + bra ne #dispatch_invalid_bitfield + + // depending on dispatch flags: execute method, or save data as state + ld b16 $r5 D[$r4 + 0] + ld b16 $r6 D[$r4 + 2] + cmpu b32 $r6 0 + bra ne #dispatch_cmd + st b32 D[$r5] $r3 + bra #dispatch_done + dispatch_cmd: + bclr $flags $p1 + call $r5 + bra $p1 #dispatch_error + bra #dispatch_done + + dispatch_invalid_bitfield: + or $r2 2 + dispatch_illegal_mthd: + or $r2 1 + + // store exception data in SCRATCH0/SCRATCH1, signal hostirq + dispatch_error: + mov $r4 0x1000 + iowr I[$r4 + 0x000] $r2 + iowr I[$r4 + 0x100] $r3 + mov $r2 0x40 + iowr I[$r0] $r2 + hostirq_wait: + iord $r2 I[$r0 + 0x200] + and $r2 0x40 + cmpu b32 $r2 0 + bra ne #hostirq_wait + + dispatch_done: + mov $r2 0x1d00 + mov $r3 1 + iowr I[$r2] $r3 + ret + +// No-operation +// +// Inputs: +// $r1: irqh state +// $r2: hostirq state +// $r3: data +// $r4: dispatch table entry +// Outputs: +// $r1: irqh state +// $p1: set on error +// $r2: hostirq state +// $r3: data +cmd_nop: + ret + +// PM_TRIGGER +// +// Inputs: +// $r1: irqh state +// $r2: hostirq state +// $r3: data +// $r4: dispatch table entry +// Outputs: +// $r1: irqh state +// $p1: set on error +// $r2: hostirq state +// $r3: data +cmd_pm_trigger: + mov $r2 0x2200 + clear b32 $r3 + sethi $r3 0x20000 + iowr I[$r2] $r3 + ret + +#ifdef NVA3 +// SET_DMA_* method handler +// +// Inputs: +// $r1: irqh state +// $r2: hostirq state +// $r3: data +// $r4: dispatch table entry +// Outputs: +// $r1: irqh state +// $p1: set on error +// $r2: hostirq state +// $r3: data +cmd_dma: + sub b32 $r4 #dispatch_dma + shr b32 $r4 1 + bset $r3 0x1e + st b32 D[$r4 + #ctx_dma] $r3 + add b32 $r4 0x600 + shl b32 $r4 6 + iowr I[$r4] $r3 + ret +#endif + +// Calculates the hw swizzle mask and adjusts the surface's xcnt to match +// +cmd_exec_set_format: + // zero out a chunk of the stack to store the swizzle into + add $sp -0x10 + st b32 D[$sp + 0x00] $r0 + st b32 D[$sp + 0x04] $r0 + st b32 D[$sp + 0x08] $r0 + st b32 D[$sp + 0x0c] $r0 + + // extract cpp, src_ncomp and dst_ncomp from FORMAT + ld b32 $r4 D[$r0 + #ctx_format] + extr $r5 $r4 16:17 + add b32 $r5 1 + extr $r6 $r4 20:21 + add b32 $r6 1 + extr $r7 $r4 24:25 + add b32 $r7 1 + + // convert FORMAT swizzle mask to hw swizzle mask + bclr $flags $p2 + clear b32 $r8 + clear b32 $r9 + ncomp_loop: + and $r10 $r4 0xf + shr b32 $r4 4 + clear b32 $r11 + bpc_loop: + cmpu b8 $r10 4 + bra nc #cmp_c0 + mulu $r12 $r10 $r5 + add b32 $r12 $r11 + bset $flags $p2 + bra #bpc_next + cmp_c0: + bra ne #cmp_c1 + mov $r12 0x10 + add b32 $r12 $r11 + bra #bpc_next + cmp_c1: + cmpu b8 $r10 6 + bra nc #cmp_zero + mov $r12 0x14 + add b32 $r12 $r11 + bra #bpc_next + cmp_zero: + mov $r12 0x80 + bpc_next: + st b8 D[$sp + $r8] $r12 + add b32 $r8 1 + add b32 $r11 1 + cmpu b32 $r11 $r5 + bra c #bpc_loop + add b32 $r9 1 + cmpu b32 $r9 $r7 + bra c #ncomp_loop + + // SRC_XCNT = (xcnt * src_cpp), or 0 if no src ref in swz (hw will hang) + mulu $r6 $r5 + st b32 D[$r0 + #ctx_src_cpp] $r6 + ld b32 $r8 D[$r0 + #ctx_xcnt] + mulu $r6 $r8 + bra $p2 #dst_xcnt + clear b32 $r6 + + dst_xcnt: + mulu $r7 $r5 + st b32 D[$r0 + #ctx_dst_cpp] $r7 + mulu $r7 $r8 + + mov $r5 0x810 + shl b32 $r5 6 + iowr I[$r5 + 0x000] $r6 + iowr I[$r5 + 0x100] $r7 + add b32 $r5 0x800 + ld b32 $r6 D[$r0 + #ctx_dst_cpp] + sub b32 $r6 1 + shl b32 $r6 8 + ld b32 $r7 D[$r0 + #ctx_src_cpp] + sub b32 $r7 1 + or $r6 $r7 + iowr I[$r5 + 0x000] $r6 + add b32 $r5 0x100 + ld b32 $r6 D[$sp + 0x00] + iowr I[$r5 + 0x000] $r6 + ld b32 $r6 D[$sp + 0x04] + iowr I[$r5 + 0x100] $r6 + ld b32 $r6 D[$sp + 0x08] + iowr I[$r5 + 0x200] $r6 + ld b32 $r6 D[$sp + 0x0c] + iowr I[$r5 + 0x300] $r6 + add b32 $r5 0x400 + ld b32 $r6 D[$r0 + #ctx_swz_const0] + iowr I[$r5 + 0x000] $r6 + ld b32 $r6 D[$r0 + #ctx_swz_const1] + iowr I[$r5 + 0x100] $r6 + add $sp 0x10 + ret + +// Setup to handle a tiled surface +// +// Calculates a number of parameters the hardware requires in order +// to correctly handle tiling. +// +// Offset calculation is performed as follows (Tp/Th/Td from TILE_MODE): +// nTx = round_up(w * cpp, 1 << Tp) >> Tp +// nTy = round_up(h, 1 << Th) >> Th +// Txo = (x * cpp) & ((1 << Tp) - 1) +// Tx = (x * cpp) >> Tp +// Tyo = y & ((1 << Th) - 1) +// Ty = y >> Th +// Tzo = z & ((1 << Td) - 1) +// Tz = z >> Td +// +// off = (Tzo << Tp << Th) + (Tyo << Tp) + Txo +// off += ((Tz * nTy * nTx)) + (Ty * nTx) + Tx) << Td << Th << Tp; +// +// Inputs: +// $r4: hw command (0x104800) +// $r5: ctx offset adjustment for src/dst selection +// $p2: set if dst surface +// +cmd_exec_set_surface_tiled: + // translate TILE_MODE into Tp, Th, Td shift values + ld b32 $r7 D[$r5 + #ctx_src_tile_mode] + extr $r9 $r7 8:11 + extr $r8 $r7 4:7 +#ifdef NVA3 + add b32 $r8 2 +#else + add b32 $r8 3 +#endif + extr $r7 $r7 0:3 + cmp b32 $r7 0xe + bra ne #xtile64 + mov $r7 4 + bra #xtileok + xtile64: + xbit $r7 $flags $p2 + add b32 $r7 17 + bset $r4 $r7 + mov $r7 6 + xtileok: + + // Op = (x * cpp) & ((1 << Tp) - 1) + // Tx = (x * cpp) >> Tp + ld b32 $r10 D[$r5 + #ctx_src_xoff] + ld b32 $r11 D[$r5 + #ctx_src_cpp] + mulu $r10 $r11 + mov $r11 1 + shl b32 $r11 $r7 + sub b32 $r11 1 + and $r12 $r10 $r11 + shr b32 $r10 $r7 + + // Tyo = y & ((1 << Th) - 1) + // Ty = y >> Th + ld b32 $r13 D[$r5 + #ctx_src_yoff] + mov $r14 1 + shl b32 $r14 $r8 + sub b32 $r14 1 + and $r11 $r13 $r14 + shr b32 $r13 $r8 + + // YTILE = ((1 << Th) << 12) | ((1 << Th) - Tyo) + add b32 $r14 1 + shl b32 $r15 $r14 12 + sub b32 $r14 $r11 + or $r15 $r14 + xbit $r6 $flags $p2 + add b32 $r6 0x208 + shl b32 $r6 8 + iowr I[$r6 + 0x000] $r15 + + // Op += Tyo << Tp + shl b32 $r11 $r7 + add b32 $r12 $r11 + + // nTx = ((w * cpp) + ((1 << Tp) - 1) >> Tp) + ld b32 $r15 D[$r5 + #ctx_src_xsize] + ld b32 $r11 D[$r5 + #ctx_src_cpp] + mulu $r15 $r11 + mov $r11 1 + shl b32 $r11 $r7 + sub b32 $r11 1 + add b32 $r15 $r11 + shr b32 $r15 $r7 + push $r15 + + // nTy = (h + ((1 << Th) - 1)) >> Th + ld b32 $r15 D[$r5 + #ctx_src_ysize] + mov $r11 1 + shl b32 $r11 $r8 + sub b32 $r11 1 + add b32 $r15 $r11 + shr b32 $r15 $r8 + push $r15 + + // Tys = Tp + Th + // CFG_YZ_TILE_SIZE = ((1 << Th) >> 2) << Td + add b32 $r7 $r8 + sub b32 $r8 2 + mov $r11 1 + shl b32 $r11 $r8 + shl b32 $r11 $r9 + + // Tzo = z & ((1 << Td) - 1) + // Tz = z >> Td + // Op += Tzo << Tys + // Ts = Tys + Td + ld b32 $r8 D[$r5 + #ctx_src_zoff] + mov $r14 1 + shl b32 $r14 $r9 + sub b32 $r14 1 + and $r15 $r8 $r14 + shl b32 $r15 $r7 + add b32 $r12 $r15 + add b32 $r7 $r9 + shr b32 $r8 $r9 + + // Ot = ((Tz * nTy * nTx) + (Ty * nTx) + Tx) << Ts + pop $r15 + pop $r9 + mulu $r13 $r9 + add b32 $r10 $r13 + mulu $r8 $r9 + mulu $r8 $r15 + add b32 $r10 $r8 + shl b32 $r10 $r7 + + // PITCH = (nTx - 1) << Ts + sub b32 $r9 1 + shl b32 $r9 $r7 + iowr I[$r6 + 0x200] $r9 + + // SRC_ADDRESS_LOW = (Ot + Op) & 0xffffffff + // CFG_ADDRESS_HIGH |= ((Ot + Op) >> 32) << 16 + ld b32 $r7 D[$r5 + #ctx_src_address_low] + ld b32 $r8 D[$r5 + #ctx_src_address_high] + add b32 $r10 $r12 + add b32 $r7 $r10 + adc b32 $r8 0 + shl b32 $r8 16 + or $r8 $r11 + sub b32 $r6 0x600 + iowr I[$r6 + 0x000] $r7 + add b32 $r6 0x400 + iowr I[$r6 + 0x000] $r8 + ret + +// Setup to handle a linear surface +// +// Nothing to see here.. Sets ADDRESS and PITCH, pretty non-exciting +// +cmd_exec_set_surface_linear: + xbit $r6 $flags $p2 + add b32 $r6 0x202 + shl b32 $r6 8 + ld b32 $r7 D[$r5 + #ctx_src_address_low] + iowr I[$r6 + 0x000] $r7 + add b32 $r6 0x400 + ld b32 $r7 D[$r5 + #ctx_src_address_high] + shl b32 $r7 16 + iowr I[$r6 + 0x000] $r7 + add b32 $r6 0x400 + ld b32 $r7 D[$r5 + #ctx_src_pitch] + iowr I[$r6 + 0x000] $r7 + ret + +// wait for regs to be available for use +cmd_exec_wait: + push $r0 + push $r1 + mov $r0 0x800 + shl b32 $r0 6 + loop: + iord $r1 I[$r0] + and $r1 1 + bra ne #loop + pop $r1 + pop $r0 + ret + +cmd_exec_query: + // if QUERY_SHORT not set, write out { -, 0, TIME_LO, TIME_HI } + xbit $r4 $r3 13 + bra ne #query_counter + call #cmd_exec_wait + mov $r4 0x80c + shl b32 $r4 6 + ld b32 $r5 D[$r0 + #ctx_query_address_low] + add b32 $r5 4 + iowr I[$r4 + 0x000] $r5 + iowr I[$r4 + 0x100] $r0 + mov $r5 0xc + iowr I[$r4 + 0x200] $r5 + add b32 $r4 0x400 + ld b32 $r5 D[$r0 + #ctx_query_address_high] + shl b32 $r5 16 + iowr I[$r4 + 0x000] $r5 + add b32 $r4 0x500 + mov $r5 0x00000b00 + sethi $r5 0x00010000 + iowr I[$r4 + 0x000] $r5 + mov $r5 0x00004040 + shl b32 $r5 1 + sethi $r5 0x80800000 + iowr I[$r4 + 0x100] $r5 + mov $r5 0x00001110 + sethi $r5 0x13120000 + iowr I[$r4 + 0x200] $r5 + mov $r5 0x00001514 + sethi $r5 0x17160000 + iowr I[$r4 + 0x300] $r5 + mov $r5 0x00002601 + sethi $r5 0x00010000 + mov $r4 0x800 + shl b32 $r4 6 + iowr I[$r4 + 0x000] $r5 + + // write COUNTER + query_counter: + call #cmd_exec_wait + mov $r4 0x80c + shl b32 $r4 6 + ld b32 $r5 D[$r0 + #ctx_query_address_low] + iowr I[$r4 + 0x000] $r5 + iowr I[$r4 + 0x100] $r0 + mov $r5 0x4 + iowr I[$r4 + 0x200] $r5 + add b32 $r4 0x400 + ld b32 $r5 D[$r0 + #ctx_query_address_high] + shl b32 $r5 16 + iowr I[$r4 + 0x000] $r5 + add b32 $r4 0x500 + mov $r5 0x00000300 + iowr I[$r4 + 0x000] $r5 + mov $r5 0x00001110 + sethi $r5 0x13120000 + iowr I[$r4 + 0x100] $r5 + ld b32 $r5 D[$r0 + #ctx_query_counter] + add b32 $r4 0x500 + iowr I[$r4 + 0x000] $r5 + mov $r5 0x00002601 + sethi $r5 0x00010000 + mov $r4 0x800 + shl b32 $r4 6 + iowr I[$r4 + 0x000] $r5 + ret + +// Execute a copy operation +// +// Inputs: +// $r1: irqh state +// $r2: hostirq state +// $r3: data +// 000002000 QUERY_SHORT +// 000001000 QUERY +// 000000100 DST_LINEAR +// 000000010 SRC_LINEAR +// 000000001 FORMAT +// $r4: dispatch table entry +// Outputs: +// $r1: irqh state +// $p1: set on error +// $r2: hostirq state +// $r3: data +cmd_exec: + call #cmd_exec_wait + + // if format requested, call function to calculate it, otherwise + // fill in cpp/xcnt for both surfaces as if (cpp == 1) + xbit $r15 $r3 0 + bra e #cmd_exec_no_format + call #cmd_exec_set_format + mov $r4 0x200 + bra #cmd_exec_init_src_surface + cmd_exec_no_format: + mov $r6 0x810 + shl b32 $r6 6 + mov $r7 1 + st b32 D[$r0 + #ctx_src_cpp] $r7 + st b32 D[$r0 + #ctx_dst_cpp] $r7 + ld b32 $r7 D[$r0 + #ctx_xcnt] + iowr I[$r6 + 0x000] $r7 + iowr I[$r6 + 0x100] $r7 + clear b32 $r4 + + cmd_exec_init_src_surface: + bclr $flags $p2 + clear b32 $r5 + xbit $r15 $r3 4 + bra e #src_tiled + call #cmd_exec_set_surface_linear + bra #cmd_exec_init_dst_surface + src_tiled: + call #cmd_exec_set_surface_tiled + bset $r4 7 + + cmd_exec_init_dst_surface: + bset $flags $p2 + mov $r5 #ctx_dst_address_high - #ctx_src_address_high + xbit $r15 $r3 8 + bra e #dst_tiled + call #cmd_exec_set_surface_linear + bra #cmd_exec_kick + dst_tiled: + call #cmd_exec_set_surface_tiled + bset $r4 8 + + cmd_exec_kick: + mov $r5 0x800 + shl b32 $r5 6 + ld b32 $r6 D[$r0 + #ctx_ycnt] + iowr I[$r5 + 0x100] $r6 + mov $r6 0x0041 + // SRC_TARGET = 1, DST_TARGET = 2 + sethi $r6 0x44000000 + or $r4 $r6 + iowr I[$r5] $r4 + + // if requested, queue up a QUERY write after the copy has completed + xbit $r15 $r3 12 + bra e #cmd_exec_done + call #cmd_exec_query + + cmd_exec_done: + ret + +// Flush write cache +// +// Inputs: +// $r1: irqh state +// $r2: hostirq state +// $r3: data +// $r4: dispatch table entry +// Outputs: +// $r1: irqh state +// $p1: set on error +// $r2: hostirq state +// $r3: data +cmd_wrcache_flush: + mov $r2 0x2200 + clear b32 $r3 + sethi $r3 0x10000 + iowr I[$r2] $r3 + ret + +.align 0x100 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3 new file mode 100644 index 0000000..e670620 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3 @@ -0,0 +1,2 @@ +#define NVA3 +#include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3.h new file mode 100644 index 0000000..362872d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3.h @@ -0,0 +1,620 @@ +uint32_t nva3_pce_data[] = { +/* 0x0000: ctx_object */ + 0x00000000, +/* 0x0004: ctx_dma */ +/* 0x0004: ctx_dma_query */ + 0x00000000, +/* 0x0008: ctx_dma_src */ + 0x00000000, +/* 0x000c: ctx_dma_dst */ + 0x00000000, +/* 0x0010: ctx_query_address_high */ + 0x00000000, +/* 0x0014: ctx_query_address_low */ + 0x00000000, +/* 0x0018: ctx_query_counter */ + 0x00000000, +/* 0x001c: ctx_src_address_high */ + 0x00000000, +/* 0x0020: ctx_src_address_low */ + 0x00000000, +/* 0x0024: ctx_src_pitch */ + 0x00000000, +/* 0x0028: ctx_src_tile_mode */ + 0x00000000, +/* 0x002c: ctx_src_xsize */ + 0x00000000, +/* 0x0030: ctx_src_ysize */ + 0x00000000, +/* 0x0034: ctx_src_zsize */ + 0x00000000, +/* 0x0038: ctx_src_zoff */ + 0x00000000, +/* 0x003c: ctx_src_xoff */ + 0x00000000, +/* 0x0040: ctx_src_yoff */ + 0x00000000, +/* 0x0044: ctx_src_cpp */ + 0x00000000, +/* 0x0048: ctx_dst_address_high */ + 0x00000000, +/* 0x004c: ctx_dst_address_low */ + 0x00000000, +/* 0x0050: ctx_dst_pitch */ + 0x00000000, +/* 0x0054: ctx_dst_tile_mode */ + 0x00000000, +/* 0x0058: ctx_dst_xsize */ + 0x00000000, +/* 0x005c: ctx_dst_ysize */ + 0x00000000, +/* 0x0060: ctx_dst_zsize */ + 0x00000000, +/* 0x0064: ctx_dst_zoff */ + 0x00000000, +/* 0x0068: ctx_dst_xoff */ + 0x00000000, +/* 0x006c: ctx_dst_yoff */ + 0x00000000, +/* 0x0070: ctx_dst_cpp */ + 0x00000000, +/* 0x0074: ctx_format */ + 0x00000000, +/* 0x0078: ctx_swz_const0 */ + 0x00000000, +/* 0x007c: ctx_swz_const1 */ + 0x00000000, +/* 0x0080: ctx_xcnt */ + 0x00000000, +/* 0x0084: ctx_ycnt */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0100: dispatch_table */ + 0x00010000, + 0x00000000, + 0x00000000, + 0x00010040, + 0x00010160, + 0x00000000, + 0x00010050, + 0x00010162, + 0x00000000, + 0x00030060, +/* 0x0128: dispatch_dma */ + 0x00010170, + 0x00000000, + 0x00010170, + 0x00000000, + 0x00010170, + 0x00000000, + 0x00070080, + 0x00000028, + 0xfffff000, + 0x0000002c, + 0xfff80000, + 0x00000030, + 0xffffe000, + 0x00000034, + 0xfffff800, + 0x00000038, + 0xfffff000, + 0x0000003c, + 0xfff80000, + 0x00000040, + 0xffffe000, + 0x00070088, + 0x00000054, + 0xfffff000, + 0x00000058, + 0xfff80000, + 0x0000005c, + 0xffffe000, + 0x00000060, + 0xfffff800, + 0x00000064, + 0xfffff000, + 0x00000068, + 0xfff80000, + 0x0000006c, + 0xffffe000, + 0x000200c0, + 0x00010492, + 0x00000000, + 0x0001051b, + 0x00000000, + 0x000e00c3, + 0x0000001c, + 0xffffff00, + 0x00000020, + 0x00000000, + 0x00000048, + 0xffffff00, + 0x0000004c, + 0x00000000, + 0x00000024, + 0xfff80000, + 0x00000050, + 0xfff80000, + 0x00000080, + 0xffff0000, + 0x00000084, + 0xffffe000, + 0x00000074, + 0xfccc0000, + 0x00000078, + 0x00000000, + 0x0000007c, + 0x00000000, + 0x00000010, + 0xffffff00, + 0x00000014, + 0x00000000, + 0x00000018, + 0x00000000, + 0x00000800, +}; + +uint32_t nva3_pce_code[] = { +/* 0x0000: main */ + 0x04fe04bd, + 0x3517f000, + 0xf10010fe, + 0xf1040017, + 0xf0fff327, + 0x12d00023, + 0x0c25f0c0, + 0xf40012d0, + 0x17f11031, + 0x27f01200, + 0x0012d003, +/* 0x002f: spin */ + 0xf40031f4, + 0x0ef40028, +/* 0x0035: ih */ + 0x8001cffd, + 0xf40812c4, + 0x21f4060b, +/* 0x0041: ih_no_chsw */ + 0x0412c472, + 0xf4060bf4, +/* 0x004a: ih_no_cmd */ + 0x11c4c321, + 0x4001d00c, +/* 0x0052: swctx */ + 0x47f101f8, + 0x4bfe7700, + 0x0007fe00, + 0xf00204b9, + 0x01f40643, + 0x0604fa09, +/* 0x006b: swctx_load */ + 0xfa060ef4, +/* 0x006e: swctx_done */ + 0x03f80504, +/* 0x0072: chsw */ + 0x27f100f8, + 0x23cf1400, + 0x1e3fc800, + 0xf4170bf4, + 0x21f40132, + 0x1e3af052, + 0xf00023d0, + 0x24d00147, +/* 0x0093: chsw_no_unload */ + 0xcf00f880, + 0x3dc84023, + 0x220bf41e, + 0xf40131f4, + 0x57f05221, + 0x0367f004, +/* 0x00a8: chsw_load_ctx_dma */ + 0xa07856bc, + 0xb6018068, + 0x87d00884, + 0x0162b600, +/* 0x00bb: chsw_finish_load */ + 0xf0f018f4, + 0x23d00237, +/* 0x00c3: dispatch */ + 0xf100f880, + 0xcf190037, + 0x33cf4032, + 0xff24e400, + 0x1024b607, + 0x010057f1, + 0x74bd64bd, +/* 0x00dc: dispatch_loop */ + 0x58005658, + 0x50b60157, + 0x0446b804, + 0xbb4d08f4, + 0x47b80076, + 0x0f08f404, + 0xb60276bb, + 0x57bb0374, + 0xdf0ef400, +/* 0x0100: dispatch_valid_mthd */ + 0xb60246bb, + 0x45bb0344, + 0x01459800, + 0xb00453fd, + 0x1bf40054, + 0x00455820, + 0xb0014658, + 0x1bf40064, + 0x00538009, +/* 0x0127: dispatch_cmd */ + 0xf4300ef4, + 0x55f90132, + 0xf40c01f4, +/* 0x0132: dispatch_invalid_bitfield */ + 0x25f0250e, +/* 0x0135: dispatch_illegal_mthd */ + 0x0125f002, +/* 0x0138: dispatch_error */ + 0x100047f1, + 0xd00042d0, + 0x27f04043, + 0x0002d040, +/* 0x0148: hostirq_wait */ + 0xf08002cf, + 0x24b04024, + 0xf71bf400, +/* 0x0154: dispatch_done */ + 0x1d0027f1, + 0xd00137f0, + 0x00f80023, +/* 0x0160: cmd_nop */ +/* 0x0162: cmd_pm_trigger */ + 0x27f100f8, + 0x34bd2200, + 0xd00233f0, + 0x00f80023, +/* 0x0170: cmd_dma */ + 0x012842b7, + 0xf00145b6, + 0x43801e39, + 0x0040b701, + 0x0644b606, + 0xf80043d0, +/* 0x0189: cmd_exec_set_format */ + 0xf030f400, + 0xb00001b0, + 0x01b00101, + 0x0301b002, + 0xc71d0498, + 0x50b63045, + 0x3446c701, + 0xc70160b6, + 0x70b63847, + 0x0232f401, + 0x94bd84bd, +/* 0x01b4: ncomp_loop */ + 0xb60f4ac4, + 0xb4bd0445, +/* 0x01bc: bpc_loop */ + 0xf404a430, + 0xa5ff0f18, + 0x00cbbbc0, + 0xf40231f4, +/* 0x01ce: cmp_c0 */ + 0x1bf4220e, + 0x10c7f00c, + 0xf400cbbb, +/* 0x01da: cmp_c1 */ + 0xa430160e, + 0x0c18f406, + 0xbb14c7f0, + 0x0ef400cb, +/* 0x01e9: cmp_zero */ + 0x80c7f107, +/* 0x01ed: bpc_next */ + 0x01c83800, + 0xb60180b6, + 0xb5b801b0, + 0xc308f404, + 0xb80190b6, + 0x08f40497, + 0x0065fdb2, + 0x98110680, + 0x68fd2008, + 0x0502f400, +/* 0x0216: dst_xcnt */ + 0x75fd64bd, + 0x1c078000, + 0xf10078fd, + 0xb6081057, + 0x56d00654, + 0x4057d000, + 0x080050b7, + 0xb61c0698, + 0x64b60162, + 0x11079808, + 0xfd0172b6, + 0x56d00567, + 0x0050b700, + 0x0060b401, + 0xb40056d0, + 0x56d00160, + 0x0260b440, + 0xb48056d0, + 0x56d00360, + 0x0050b7c0, + 0x1e069804, + 0x980056d0, + 0x56d01f06, + 0x1030f440, +/* 0x0276: cmd_exec_set_surface_tiled */ + 0x579800f8, + 0x6879c70a, + 0xb66478c7, + 0x77c70280, + 0x0e76b060, + 0xf0091bf4, + 0x0ef40477, +/* 0x0291: xtile64 */ + 0x027cf00f, + 0xfd1170b6, + 0x77f00947, +/* 0x029d: xtileok */ + 0x0f5a9806, + 0xfd115b98, + 0xb7f000ab, + 0x04b7bb01, + 0xff01b2b6, + 0xa7bbc4ab, + 0x105d9805, + 0xbb01e7f0, + 0xe2b604e8, + 0xb4deff01, + 0xb605d8bb, + 0xef9401e0, + 0x02ebbb0c, + 0xf005fefd, + 0x60b7026c, + 0x64b60208, + 0x006fd008, + 0xbb04b7bb, + 0x5f9800cb, + 0x115b980b, + 0xf000fbfd, + 0xb7bb01b7, + 0x01b2b604, + 0xbb00fbbb, + 0xf0f905f7, + 0xf00c5f98, + 0xb8bb01b7, + 0x01b2b604, + 0xbb00fbbb, + 0xf0f905f8, + 0xb60078bb, + 0xb7f00282, + 0x04b8bb01, + 0x9804b9bb, + 0xe7f00e58, + 0x04e9bb01, + 0xff01e2b6, + 0xf7bbf48e, + 0x00cfbb04, + 0xbb0079bb, + 0xf0fc0589, + 0xd9fd90fc, + 0x00adbb00, + 0xfd0089fd, + 0xa8bb008f, + 0x04a7bb00, + 0xbb0192b6, + 0x69d00497, + 0x08579880, + 0xbb075898, + 0x7abb00ac, + 0x0081b600, + 0xfd1084b6, + 0x62b7058b, + 0x67d00600, + 0x0060b700, + 0x0068d004, +/* 0x0382: cmd_exec_set_surface_linear */ + 0x6cf000f8, + 0x0260b702, + 0x0864b602, + 0xd0085798, + 0x60b70067, + 0x57980400, + 0x1074b607, + 0xb70067d0, + 0x98040060, + 0x67d00957, +/* 0x03ab: cmd_exec_wait */ + 0xf900f800, + 0xf110f900, + 0xb6080007, +/* 0x03b6: loop */ + 0x01cf0604, + 0x0114f000, + 0xfcfa1bf4, + 0xf800fc10, +/* 0x03c5: cmd_exec_query */ + 0x0d34c800, + 0xf5701bf4, + 0xf103ab21, + 0xb6080c47, + 0x05980644, + 0x0450b605, + 0xd00045d0, + 0x57f04040, + 0x8045d00c, + 0x040040b7, + 0xb6040598, + 0x45d01054, + 0x0040b700, + 0x0057f105, + 0x0153f00b, + 0xf10045d0, + 0xb6404057, + 0x53f10154, + 0x45d08080, + 0x1057f140, + 0x1253f111, + 0x8045d013, + 0x151457f1, + 0x171653f1, + 0xf1c045d0, + 0xf0260157, + 0x47f10153, + 0x44b60800, + 0x0045d006, +/* 0x0438: query_counter */ + 0x03ab21f5, + 0x080c47f1, + 0x980644b6, + 0x45d00505, + 0x4040d000, + 0xd00457f0, + 0x40b78045, + 0x05980400, + 0x1054b604, + 0xb70045d0, + 0xf1050040, + 0xd0030057, + 0x57f10045, + 0x53f11110, + 0x45d01312, + 0x06059840, + 0x050040b7, + 0xf10045d0, + 0xf0260157, + 0x47f10153, + 0x44b60800, + 0x0045d006, +/* 0x0492: cmd_exec */ + 0x21f500f8, + 0x3fc803ab, + 0x0e0bf400, + 0x018921f5, + 0x020047f1, +/* 0x04a7: cmd_exec_no_format */ + 0xf11e0ef4, + 0xb6081067, + 0x77f00664, + 0x11078001, + 0x981c0780, + 0x67d02007, + 0x4067d000, +/* 0x04c2: cmd_exec_init_src_surface */ + 0x32f444bd, + 0xc854bd02, + 0x0bf4043f, + 0x8221f50a, + 0x0a0ef403, +/* 0x04d4: src_tiled */ + 0x027621f5, +/* 0x04db: cmd_exec_init_dst_surface */ + 0xf40749f0, + 0x57f00231, + 0x083fc82c, + 0xf50a0bf4, + 0xf4038221, +/* 0x04ee: dst_tiled */ + 0x21f50a0e, + 0x49f00276, +/* 0x04f5: cmd_exec_kick */ + 0x0057f108, + 0x0654b608, + 0xd0210698, + 0x67f04056, + 0x0063f141, + 0x0546fd44, + 0xc80054d0, + 0x0bf40c3f, + 0xc521f507, +/* 0x0519: cmd_exec_done */ +/* 0x051b: cmd_wrcache_flush */ + 0xf100f803, + 0xbd220027, + 0x0133f034, + 0xf80023d0, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3 new file mode 100644 index 0000000..df6866c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3 @@ -0,0 +1,2 @@ +#define NVC0 +#include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3.h new file mode 100644 index 0000000..042257d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3.h @@ -0,0 +1,606 @@ +uint32_t nvc0_pce_data[] = { +/* 0x0000: ctx_object */ + 0x00000000, +/* 0x0004: ctx_query_address_high */ + 0x00000000, +/* 0x0008: ctx_query_address_low */ + 0x00000000, +/* 0x000c: ctx_query_counter */ + 0x00000000, +/* 0x0010: ctx_src_address_high */ + 0x00000000, +/* 0x0014: ctx_src_address_low */ + 0x00000000, +/* 0x0018: ctx_src_pitch */ + 0x00000000, +/* 0x001c: ctx_src_tile_mode */ + 0x00000000, +/* 0x0020: ctx_src_xsize */ + 0x00000000, +/* 0x0024: ctx_src_ysize */ + 0x00000000, +/* 0x0028: ctx_src_zsize */ + 0x00000000, +/* 0x002c: ctx_src_zoff */ + 0x00000000, +/* 0x0030: ctx_src_xoff */ + 0x00000000, +/* 0x0034: ctx_src_yoff */ + 0x00000000, +/* 0x0038: ctx_src_cpp */ + 0x00000000, +/* 0x003c: ctx_dst_address_high */ + 0x00000000, +/* 0x0040: ctx_dst_address_low */ + 0x00000000, +/* 0x0044: ctx_dst_pitch */ + 0x00000000, +/* 0x0048: ctx_dst_tile_mode */ + 0x00000000, +/* 0x004c: ctx_dst_xsize */ + 0x00000000, +/* 0x0050: ctx_dst_ysize */ + 0x00000000, +/* 0x0054: ctx_dst_zsize */ + 0x00000000, +/* 0x0058: ctx_dst_zoff */ + 0x00000000, +/* 0x005c: ctx_dst_xoff */ + 0x00000000, +/* 0x0060: ctx_dst_yoff */ + 0x00000000, +/* 0x0064: ctx_dst_cpp */ + 0x00000000, +/* 0x0068: ctx_format */ + 0x00000000, +/* 0x006c: ctx_swz_const0 */ + 0x00000000, +/* 0x0070: ctx_swz_const1 */ + 0x00000000, +/* 0x0074: ctx_xcnt */ + 0x00000000, +/* 0x0078: ctx_ycnt */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0100: dispatch_table */ + 0x00010000, + 0x00000000, + 0x00000000, + 0x00010040, + 0x0001019f, + 0x00000000, + 0x00010050, + 0x000101a1, + 0x00000000, + 0x00070080, + 0x0000001c, + 0xfffff000, + 0x00000020, + 0xfff80000, + 0x00000024, + 0xffffe000, + 0x00000028, + 0xfffff800, + 0x0000002c, + 0xfffff000, + 0x00000030, + 0xfff80000, + 0x00000034, + 0xffffe000, + 0x00070088, + 0x00000048, + 0xfffff000, + 0x0000004c, + 0xfff80000, + 0x00000050, + 0xffffe000, + 0x00000054, + 0xfffff800, + 0x00000058, + 0xfffff000, + 0x0000005c, + 0xfff80000, + 0x00000060, + 0xffffe000, + 0x000200c0, + 0x000104b8, + 0x00000000, + 0x00010541, + 0x00000000, + 0x000e00c3, + 0x00000010, + 0xffffff00, + 0x00000014, + 0x00000000, + 0x0000003c, + 0xffffff00, + 0x00000040, + 0x00000000, + 0x00000018, + 0xfff80000, + 0x00000044, + 0xfff80000, + 0x00000074, + 0xffff0000, + 0x00000078, + 0xffffe000, + 0x00000068, + 0xfccc0000, + 0x0000006c, + 0x00000000, + 0x00000070, + 0x00000000, + 0x00000004, + 0xffffff00, + 0x00000008, + 0x00000000, + 0x0000000c, + 0x00000000, + 0x00000800, +}; + +uint32_t nvc0_pce_code[] = { +/* 0x0000: main */ + 0x04fe04bd, + 0x3517f000, + 0xf10010fe, + 0xf1040017, + 0xf0fff327, + 0x12d00023, + 0x0c25f0c0, + 0xf40012d0, + 0x17f11031, + 0x27f01200, + 0x0012d003, +/* 0x002f: spin */ + 0xf40031f4, + 0x0ef40028, +/* 0x0035: ih */ + 0x8001cffd, + 0xf40812c4, + 0x21f4060b, +/* 0x0041: ih_no_chsw */ + 0x0412c4ca, + 0xf5070bf4, +/* 0x004b: ih_no_cmd */ + 0xc4010221, + 0x01d00c11, +/* 0x0053: swctx */ + 0xf101f840, + 0xfe770047, + 0x47f1004b, + 0x44cf2100, + 0x0144f000, + 0xb60444b6, + 0xf7f13040, + 0xf4b6061c, + 0x1457f106, + 0x00f5d101, + 0xb6043594, + 0x57fe0250, + 0x0145fe00, + 0x010052b7, + 0x00ff67f1, + 0x56fd60bd, + 0x0253f004, + 0xf80545fa, + 0x0053f003, + 0xd100e7f0, + 0x549800fe, + 0x0845b600, + 0xb6015698, + 0x46fd1864, + 0x0047fe05, + 0xf00204b9, + 0x01f40643, + 0x0604fa09, +/* 0x00c3: swctx_load */ + 0xfa060ef4, +/* 0x00c6: swctx_done */ + 0x03f80504, +/* 0x00ca: chsw */ + 0x27f100f8, + 0x23cf1400, + 0x1e3fc800, + 0xf4170bf4, + 0x21f40132, + 0x1e3af053, + 0xf00023d0, + 0x24d00147, +/* 0x00eb: chsw_no_unload */ + 0xcf00f880, + 0x3dc84023, + 0x090bf41e, + 0xf40131f4, +/* 0x00fa: chsw_finish_load */ + 0x37f05321, + 0x8023d002, +/* 0x0102: dispatch */ + 0x37f100f8, + 0x32cf1900, + 0x0033cf40, + 0x07ff24e4, + 0xf11024b6, + 0xbd010057, +/* 0x011b: dispatch_loop */ + 0x5874bd64, + 0x57580056, + 0x0450b601, + 0xf40446b8, + 0x76bb4d08, + 0x0447b800, + 0xbb0f08f4, + 0x74b60276, + 0x0057bb03, +/* 0x013f: dispatch_valid_mthd */ + 0xbbdf0ef4, + 0x44b60246, + 0x0045bb03, + 0xfd014598, + 0x54b00453, + 0x201bf400, + 0x58004558, + 0x64b00146, + 0x091bf400, + 0xf4005380, +/* 0x0166: dispatch_cmd */ + 0x32f4300e, + 0xf455f901, + 0x0ef40c01, +/* 0x0171: dispatch_invalid_bitfield */ + 0x0225f025, +/* 0x0174: dispatch_illegal_mthd */ +/* 0x0177: dispatch_error */ + 0xf10125f0, + 0xd0100047, + 0x43d00042, + 0x4027f040, +/* 0x0187: hostirq_wait */ + 0xcf0002d0, + 0x24f08002, + 0x0024b040, +/* 0x0193: dispatch_done */ + 0xf1f71bf4, + 0xf01d0027, + 0x23d00137, +/* 0x019f: cmd_nop */ + 0xf800f800, +/* 0x01a1: cmd_pm_trigger */ + 0x0027f100, + 0xf034bd22, + 0x23d00233, +/* 0x01af: cmd_exec_set_format */ + 0xf400f800, + 0x01b0f030, + 0x0101b000, + 0xb00201b0, + 0x04980301, + 0x3045c71a, + 0xc70150b6, + 0x60b63446, + 0x3847c701, + 0xf40170b6, + 0x84bd0232, +/* 0x01da: ncomp_loop */ + 0x4ac494bd, + 0x0445b60f, +/* 0x01e2: bpc_loop */ + 0xa430b4bd, + 0x0f18f404, + 0xbbc0a5ff, + 0x31f400cb, + 0x220ef402, +/* 0x01f4: cmp_c0 */ + 0xf00c1bf4, + 0xcbbb10c7, + 0x160ef400, +/* 0x0200: cmp_c1 */ + 0xf406a430, + 0xc7f00c18, + 0x00cbbb14, +/* 0x020f: cmp_zero */ + 0xf1070ef4, +/* 0x0213: bpc_next */ + 0x380080c7, + 0x80b601c8, + 0x01b0b601, + 0xf404b5b8, + 0x90b6c308, + 0x0497b801, + 0xfdb208f4, + 0x06800065, + 0x1d08980e, + 0xf40068fd, + 0x64bd0502, +/* 0x023c: dst_xcnt */ + 0x800075fd, + 0x78fd1907, + 0x1057f100, + 0x0654b608, + 0xd00056d0, + 0x50b74057, + 0x06980800, + 0x0162b619, + 0x980864b6, + 0x72b60e07, + 0x0567fd01, + 0xb70056d0, + 0xb4010050, + 0x56d00060, + 0x0160b400, + 0xb44056d0, + 0x56d00260, + 0x0360b480, + 0xb7c056d0, + 0x98040050, + 0x56d01b06, + 0x1c069800, + 0xf44056d0, + 0x00f81030, +/* 0x029c: cmd_exec_set_surface_tiled */ + 0xc7075798, + 0x78c76879, + 0x0380b664, + 0xb06077c7, + 0x1bf40e76, + 0x0477f009, +/* 0x02b7: xtile64 */ + 0xf00f0ef4, + 0x70b6027c, + 0x0947fd11, +/* 0x02c3: xtileok */ + 0x980677f0, + 0x5b980c5a, + 0x00abfd0e, + 0xbb01b7f0, + 0xb2b604b7, + 0xc4abff01, + 0x9805a7bb, + 0xe7f00d5d, + 0x04e8bb01, + 0xff01e2b6, + 0xd8bbb4de, + 0x01e0b605, + 0xbb0cef94, + 0xfefd02eb, + 0x026cf005, + 0x020860b7, + 0xd00864b6, + 0xb7bb006f, + 0x00cbbb04, + 0x98085f98, + 0xfbfd0e5b, + 0x01b7f000, + 0xb604b7bb, + 0xfbbb01b2, + 0x05f7bb00, + 0x5f98f0f9, + 0x01b7f009, + 0xb604b8bb, + 0xfbbb01b2, + 0x05f8bb00, + 0x78bbf0f9, + 0x0282b600, + 0xbb01b7f0, + 0xb9bb04b8, + 0x0b589804, + 0xbb01e7f0, + 0xe2b604e9, + 0xf48eff01, + 0xbb04f7bb, + 0x79bb00cf, + 0x0589bb00, + 0x90fcf0fc, + 0xbb00d9fd, + 0x89fd00ad, + 0x008ffd00, + 0xbb00a8bb, + 0x92b604a7, + 0x0497bb01, + 0x988069d0, + 0x58980557, + 0x00acbb04, + 0xb6007abb, + 0x84b60081, + 0x058bfd10, + 0x060062b7, + 0xb70067d0, + 0xd0040060, + 0x00f80068, +/* 0x03a8: cmd_exec_set_surface_linear */ + 0xb7026cf0, + 0xb6020260, + 0x57980864, + 0x0067d005, + 0x040060b7, + 0xb6045798, + 0x67d01074, + 0x0060b700, + 0x06579804, + 0xf80067d0, +/* 0x03d1: cmd_exec_wait */ + 0xf900f900, + 0x0007f110, + 0x0604b608, +/* 0x03dc: loop */ + 0xf00001cf, + 0x1bf40114, + 0xfc10fcfa, +/* 0x03eb: cmd_exec_query */ + 0xc800f800, + 0x1bf40d34, + 0xd121f570, + 0x0c47f103, + 0x0644b608, + 0xb6020598, + 0x45d00450, + 0x4040d000, + 0xd00c57f0, + 0x40b78045, + 0x05980400, + 0x1054b601, + 0xb70045d0, + 0xf1050040, + 0xf00b0057, + 0x45d00153, + 0x4057f100, + 0x0154b640, + 0x808053f1, + 0xf14045d0, + 0xf1111057, + 0xd0131253, + 0x57f18045, + 0x53f11514, + 0x45d01716, + 0x0157f1c0, + 0x0153f026, + 0x080047f1, + 0xd00644b6, +/* 0x045e: query_counter */ + 0x21f50045, + 0x47f103d1, + 0x44b6080c, + 0x02059806, + 0xd00045d0, + 0x57f04040, + 0x8045d004, + 0x040040b7, + 0xb6010598, + 0x45d01054, + 0x0040b700, + 0x0057f105, + 0x0045d003, + 0x111057f1, + 0x131253f1, + 0x984045d0, + 0x40b70305, + 0x45d00500, + 0x0157f100, + 0x0153f026, + 0x080047f1, + 0xd00644b6, + 0x00f80045, +/* 0x04b8: cmd_exec */ + 0x03d121f5, + 0xf4003fc8, + 0x21f50e0b, + 0x47f101af, + 0x0ef40200, +/* 0x04cd: cmd_exec_no_format */ + 0x1067f11e, + 0x0664b608, + 0x800177f0, + 0x07800e07, + 0x1d079819, + 0xd00067d0, + 0x44bd4067, +/* 0x04e8: cmd_exec_init_src_surface */ + 0xbd0232f4, + 0x043fc854, + 0xf50a0bf4, + 0xf403a821, +/* 0x04fa: src_tiled */ + 0x21f50a0e, + 0x49f0029c, +/* 0x0501: cmd_exec_init_dst_surface */ + 0x0231f407, + 0xc82c57f0, + 0x0bf4083f, + 0xa821f50a, + 0x0a0ef403, +/* 0x0514: dst_tiled */ + 0x029c21f5, +/* 0x051b: cmd_exec_kick */ + 0xf10849f0, + 0xb6080057, + 0x06980654, + 0x4056d01e, + 0xf14167f0, + 0xfd440063, + 0x54d00546, + 0x0c3fc800, + 0xf5070bf4, +/* 0x053f: cmd_exec_done */ + 0xf803eb21, +/* 0x0541: cmd_wrcache_flush */ + 0x0027f100, + 0xf034bd22, + 0x23d00133, + 0x0000f800, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c new file mode 100644 index 0000000..b193b5f --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c @@ -0,0 +1,156 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include +#include + +#include +#include + +#include +#include + + +#include "fuc/nva3.fuc3.h" + +struct nva3_ce_priv { + struct nouveau_falcon base; +}; + +/******************************************************************************* + * Copy object classes + ******************************************************************************/ + +static struct nouveau_oclass +nva3_ce_sclass[] = { + { 0x85b5, &nouveau_object_ofuncs }, + {} +}; + +/******************************************************************************* + * PCE context + ******************************************************************************/ + +static struct nouveau_oclass +nva3_ce_cclass = { + .handle = NV_ENGCTX(CE0, 0xa3), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = _nouveau_falcon_context_ctor, + .dtor = _nouveau_falcon_context_dtor, + .init = _nouveau_falcon_context_init, + .fini = _nouveau_falcon_context_fini, + .rd32 = _nouveau_falcon_context_rd32, + .wr32 = _nouveau_falcon_context_wr32, + + }, +}; + +/******************************************************************************* + * PCE engine/subdev functions + ******************************************************************************/ + +static const struct nouveau_enum nva3_ce_isr_error_name[] = { + { 0x0001, "ILLEGAL_MTHD" }, + { 0x0002, "INVALID_ENUM" }, + { 0x0003, "INVALID_BITFIELD" }, + {} +}; + +void +nva3_ce_intr(struct nouveau_subdev *subdev) +{ + struct nouveau_fifo *pfifo = nouveau_fifo(subdev); + struct nouveau_engine *engine = nv_engine(subdev); + struct nouveau_falcon *falcon = (void *)subdev; + struct nouveau_object *engctx; + u32 dispatch = nv_ro32(falcon, 0x01c); + u32 stat = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16); + u64 inst = nv_ro32(falcon, 0x050) & 0x3fffffff; + u32 ssta = nv_ro32(falcon, 0x040) & 0x0000ffff; + u32 addr = nv_ro32(falcon, 0x040) >> 16; + u32 mthd = (addr & 0x07ff) << 2; + u32 subc = (addr & 0x3800) >> 11; + u32 data = nv_ro32(falcon, 0x044); + int chid; + + engctx = nouveau_engctx_get(engine, inst); + chid = pfifo->chid(pfifo, engctx); + + if (stat & 0x00000040) { + nv_error(falcon, "DISPATCH_ERROR ["); + nouveau_enum_print(nva3_ce_isr_error_name, ssta); + pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n", + chid, inst << 12, nouveau_client_name(engctx), subc, + mthd, data); + nv_wo32(falcon, 0x004, 0x00000040); + stat &= ~0x00000040; + } + + if (stat) { + nv_error(falcon, "unhandled intr 0x%08x\n", stat); + nv_wo32(falcon, 0x004, stat); + } + + nouveau_engctx_put(engctx); +} + +static int +nva3_ce_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + bool enable = (nv_device(parent)->chipset != 0xaf); + struct nva3_ce_priv *priv; + int ret; + + ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, enable, + "PCE0", "ce0", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00802000; + nv_subdev(priv)->intr = nva3_ce_intr; + nv_engine(priv)->cclass = &nva3_ce_cclass; + nv_engine(priv)->sclass = nva3_ce_sclass; + nv_falcon(priv)->code.data = nva3_pce_code; + nv_falcon(priv)->code.size = sizeof(nva3_pce_code); + nv_falcon(priv)->data.data = nva3_pce_data; + nv_falcon(priv)->data.size = sizeof(nva3_pce_data); + return 0; +} + +struct nouveau_oclass +nva3_ce_oclass = { + .handle = NV_ENGINE(CE0, 0xa3), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nva3_ce_ctor, + .dtor = _nouveau_falcon_dtor, + .init = _nouveau_falcon_init, + .fini = _nouveau_falcon_fini, + .rd32 = _nouveau_falcon_rd32, + .wr32 = _nouveau_falcon_wr32, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nvc0.c new file mode 100644 index 0000000..f5dff13 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nvc0.c @@ -0,0 +1,172 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include +#include + +#include +#include + +#include "fuc/nvc0.fuc3.h" + +struct nvc0_ce_priv { + struct nouveau_falcon base; +}; + +/******************************************************************************* + * Copy object classes + ******************************************************************************/ + +static struct nouveau_oclass +nvc0_ce0_sclass[] = { + { 0x90b5, &nouveau_object_ofuncs }, + {}, +}; + +static struct nouveau_oclass +nvc0_ce1_sclass[] = { + { 0x90b8, &nouveau_object_ofuncs }, + {}, +}; + +/******************************************************************************* + * PCE context + ******************************************************************************/ + +static struct nouveau_ofuncs +nvc0_ce_context_ofuncs = { + .ctor = _nouveau_falcon_context_ctor, + .dtor = _nouveau_falcon_context_dtor, + .init = _nouveau_falcon_context_init, + .fini = _nouveau_falcon_context_fini, + .rd32 = _nouveau_falcon_context_rd32, + .wr32 = _nouveau_falcon_context_wr32, +}; + +static struct nouveau_oclass +nvc0_ce0_cclass = { + .handle = NV_ENGCTX(CE0, 0xc0), + .ofuncs = &nvc0_ce_context_ofuncs, +}; + +static struct nouveau_oclass +nvc0_ce1_cclass = { + .handle = NV_ENGCTX(CE1, 0xc0), + .ofuncs = &nvc0_ce_context_ofuncs, +}; + +/******************************************************************************* + * PCE engine/subdev functions + ******************************************************************************/ + +static int +nvc0_ce_init(struct nouveau_object *object) +{ + struct nvc0_ce_priv *priv = (void *)object; + int ret; + + ret = nouveau_falcon_init(&priv->base); + if (ret) + return ret; + + nv_wo32(priv, 0x084, nv_engidx(&priv->base.base) - NVDEV_ENGINE_CE0); + return 0; +} + +static int +nvc0_ce0_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nvc0_ce_priv *priv; + int ret; + + ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, true, + "PCE0", "ce0", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00000040; + nv_subdev(priv)->intr = nva3_ce_intr; + nv_engine(priv)->cclass = &nvc0_ce0_cclass; + nv_engine(priv)->sclass = nvc0_ce0_sclass; + nv_falcon(priv)->code.data = nvc0_pce_code; + nv_falcon(priv)->code.size = sizeof(nvc0_pce_code); + nv_falcon(priv)->data.data = nvc0_pce_data; + nv_falcon(priv)->data.size = sizeof(nvc0_pce_data); + return 0; +} + +static int +nvc0_ce1_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nvc0_ce_priv *priv; + int ret; + + ret = nouveau_falcon_create(parent, engine, oclass, 0x105000, true, + "PCE1", "ce1", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00000080; + nv_subdev(priv)->intr = nva3_ce_intr; + nv_engine(priv)->cclass = &nvc0_ce1_cclass; + nv_engine(priv)->sclass = nvc0_ce1_sclass; + nv_falcon(priv)->code.data = nvc0_pce_code; + nv_falcon(priv)->code.size = sizeof(nvc0_pce_code); + nv_falcon(priv)->data.data = nvc0_pce_data; + nv_falcon(priv)->data.size = sizeof(nvc0_pce_data); + return 0; +} + +struct nouveau_oclass +nvc0_ce0_oclass = { + .handle = NV_ENGINE(CE0, 0xc0), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_ce0_ctor, + .dtor = _nouveau_falcon_dtor, + .init = nvc0_ce_init, + .fini = _nouveau_falcon_fini, + .rd32 = _nouveau_falcon_rd32, + .wr32 = _nouveau_falcon_wr32, + }, +}; + +struct nouveau_oclass +nvc0_ce1_oclass = { + .handle = NV_ENGINE(CE1, 0xc0), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_ce1_ctor, + .dtor = _nouveau_falcon_dtor, + .init = nvc0_ce_init, + .fini = _nouveau_falcon_fini, + .rd32 = _nouveau_falcon_rd32, + .wr32 = _nouveau_falcon_wr32, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nve0.c new file mode 100644 index 0000000..b2b31d1b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nve0.c @@ -0,0 +1,176 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include +#include + +#include + +struct nve0_ce_priv { + struct nouveau_engine base; +}; + +/******************************************************************************* + * Copy object classes + ******************************************************************************/ + +static struct nouveau_oclass +nve0_ce_sclass[] = { + { 0xa0b5, &nouveau_object_ofuncs }, + {}, +}; + +/******************************************************************************* + * PCE context + ******************************************************************************/ + +static struct nouveau_ofuncs +nve0_ce_context_ofuncs = { + .ctor = _nouveau_engctx_ctor, + .dtor = _nouveau_engctx_dtor, + .init = _nouveau_engctx_init, + .fini = _nouveau_engctx_fini, + .rd32 = _nouveau_engctx_rd32, + .wr32 = _nouveau_engctx_wr32, +}; + +static struct nouveau_oclass +nve0_ce_cclass = { + .handle = NV_ENGCTX(CE0, 0xc0), + .ofuncs = &nve0_ce_context_ofuncs, +}; + +/******************************************************************************* + * PCE engine/subdev functions + ******************************************************************************/ + +static void +nve0_ce_intr(struct nouveau_subdev *subdev) +{ + const int ce = nv_subidx(subdev) - NVDEV_ENGINE_CE0; + struct nve0_ce_priv *priv = (void *)subdev; + u32 stat = nv_rd32(priv, 0x104908 + (ce * 0x1000)); + + if (stat) { + nv_warn(priv, "unhandled intr 0x%08x\n", stat); + nv_wr32(priv, 0x104908 + (ce * 0x1000), stat); + } +} + +static int +nve0_ce0_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nve0_ce_priv *priv; + int ret; + + ret = nouveau_engine_create(parent, engine, oclass, true, + "PCE0", "ce0", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00000040; + nv_subdev(priv)->intr = nve0_ce_intr; + nv_engine(priv)->cclass = &nve0_ce_cclass; + nv_engine(priv)->sclass = nve0_ce_sclass; + return 0; +} + +static int +nve0_ce1_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nve0_ce_priv *priv; + int ret; + + ret = nouveau_engine_create(parent, engine, oclass, true, + "PCE1", "ce1", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00000080; + nv_subdev(priv)->intr = nve0_ce_intr; + nv_engine(priv)->cclass = &nve0_ce_cclass; + nv_engine(priv)->sclass = nve0_ce_sclass; + return 0; +} + +static int +nve0_ce2_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nve0_ce_priv *priv; + int ret; + + ret = nouveau_engine_create(parent, engine, oclass, true, + "PCE2", "ce2", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00200000; + nv_subdev(priv)->intr = nve0_ce_intr; + nv_engine(priv)->cclass = &nve0_ce_cclass; + nv_engine(priv)->sclass = nve0_ce_sclass; + return 0; +} + +struct nouveau_oclass +nve0_ce0_oclass = { + .handle = NV_ENGINE(CE0, 0xe0), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nve0_ce0_ctor, + .dtor = _nouveau_engine_dtor, + .init = _nouveau_engine_init, + .fini = _nouveau_engine_fini, + }, +}; + +struct nouveau_oclass +nve0_ce1_oclass = { + .handle = NV_ENGINE(CE1, 0xe0), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nve0_ce1_ctor, + .dtor = _nouveau_engine_dtor, + .init = _nouveau_engine_init, + .fini = _nouveau_engine_fini, + }, +}; + +struct nouveau_oclass +nve0_ce2_oclass = { + .handle = NV_ENGINE(CE2, 0xe0), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nve0_ce2_ctor, + .dtor = _nouveau_engine_dtor, + .init = _nouveau_engine_init, + .fini = _nouveau_engine_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/copy/Kbuild deleted file mode 100644 index d8aa5ed..0000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/Kbuild +++ /dev/null @@ -1,3 +0,0 @@ -nvkm-y += nvkm/engine/copy/nva3.o -nvkm-y += nvkm/engine/copy/nvc0.o -nvkm-y += nvkm/engine/copy/nve0.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/com.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/com.fuc deleted file mode 100644 index 33b67dc..0000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/com.fuc +++ /dev/null @@ -1,871 +0,0 @@ -/* fuc microcode for copy engine on nva3- chipsets - * - * Copyright 2011 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -/* To build for nva3:nvc0 - * m4 -DNVA3 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nva3_copy.fuc.h - * - * To build for nvc0- - * m4 -DNVC0 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_copy.fuc.h - */ - -#ifdef NVA3 -.section #nva3_pcopy_data -#else -.section #nvc0_pcopy_data -#endif - -ctx_object: .b32 0 -#ifdef NVA3 -ctx_dma: -ctx_dma_query: .b32 0 -ctx_dma_src: .b32 0 -ctx_dma_dst: .b32 0 -#endif -.equ #ctx_dma_count 3 -ctx_query_address_high: .b32 0 -ctx_query_address_low: .b32 0 -ctx_query_counter: .b32 0 -ctx_src_address_high: .b32 0 -ctx_src_address_low: .b32 0 -ctx_src_pitch: .b32 0 -ctx_src_tile_mode: .b32 0 -ctx_src_xsize: .b32 0 -ctx_src_ysize: .b32 0 -ctx_src_zsize: .b32 0 -ctx_src_zoff: .b32 0 -ctx_src_xoff: .b32 0 -ctx_src_yoff: .b32 0 -ctx_src_cpp: .b32 0 -ctx_dst_address_high: .b32 0 -ctx_dst_address_low: .b32 0 -ctx_dst_pitch: .b32 0 -ctx_dst_tile_mode: .b32 0 -ctx_dst_xsize: .b32 0 -ctx_dst_ysize: .b32 0 -ctx_dst_zsize: .b32 0 -ctx_dst_zoff: .b32 0 -ctx_dst_xoff: .b32 0 -ctx_dst_yoff: .b32 0 -ctx_dst_cpp: .b32 0 -ctx_format: .b32 0 -ctx_swz_const0: .b32 0 -ctx_swz_const1: .b32 0 -ctx_xcnt: .b32 0 -ctx_ycnt: .b32 0 -.align 256 - -dispatch_table: -// mthd 0x0000, NAME -.b16 0x000 1 -.b32 #ctx_object ~0xffffffff -// mthd 0x0100, NOP -.b16 0x040 1 -.b32 0x00010000 + #cmd_nop ~0xffffffff -// mthd 0x0140, PM_TRIGGER -.b16 0x050 1 -.b32 0x00010000 + #cmd_pm_trigger ~0xffffffff -#ifdef NVA3 -// mthd 0x0180-0x018c, DMA_ -.b16 0x060 #ctx_dma_count -dispatch_dma: -.b32 0x00010000 + #cmd_dma ~0xffffffff -.b32 0x00010000 + #cmd_dma ~0xffffffff -.b32 0x00010000 + #cmd_dma ~0xffffffff -#endif -// mthd 0x0200-0x0218, SRC_TILE -.b16 0x80 7 -.b32 #ctx_src_tile_mode ~0x00000fff -.b32 #ctx_src_xsize ~0x0007ffff -.b32 #ctx_src_ysize ~0x00001fff -.b32 #ctx_src_zsize ~0x000007ff -.b32 #ctx_src_zoff ~0x00000fff -.b32 #ctx_src_xoff ~0x0007ffff -.b32 #ctx_src_yoff ~0x00001fff -// mthd 0x0220-0x0238, DST_TILE -.b16 0x88 7 -.b32 #ctx_dst_tile_mode ~0x00000fff -.b32 #ctx_dst_xsize ~0x0007ffff -.b32 #ctx_dst_ysize ~0x00001fff -.b32 #ctx_dst_zsize ~0x000007ff -.b32 #ctx_dst_zoff ~0x00000fff -.b32 #ctx_dst_xoff ~0x0007ffff -.b32 #ctx_dst_yoff ~0x00001fff -// mthd 0x0300-0x0304, EXEC, WRCACHE_FLUSH -.b16 0xc0 2 -.b32 0x00010000 + #cmd_exec ~0xffffffff -.b32 0x00010000 + #cmd_wrcache_flush ~0xffffffff -// mthd 0x030c-0x0340, various stuff -.b16 0xc3 14 -.b32 #ctx_src_address_high ~0x000000ff -.b32 #ctx_src_address_low ~0xffffffff -.b32 #ctx_dst_address_high ~0x000000ff -.b32 #ctx_dst_address_low ~0xffffffff -.b32 #ctx_src_pitch ~0x0007ffff -.b32 #ctx_dst_pitch ~0x0007ffff -.b32 #ctx_xcnt ~0x0000ffff -.b32 #ctx_ycnt ~0x00001fff -.b32 #ctx_format ~0x0333ffff -.b32 #ctx_swz_const0 ~0xffffffff -.b32 #ctx_swz_const1 ~0xffffffff -.b32 #ctx_query_address_high ~0x000000ff -.b32 #ctx_query_address_low ~0xffffffff -.b32 #ctx_query_counter ~0xffffffff -.b16 0x800 0 - -#ifdef NVA3 -.section #nva3_pcopy_code -#else -.section #nvc0_pcopy_code -#endif - -main: - clear b32 $r0 - mov $sp $r0 - - // setup i0 handler and route fifo and ctxswitch to it - mov $r1 #ih - mov $iv0 $r1 - mov $r1 0x400 - movw $r2 0xfff3 - sethi $r2 0 - iowr I[$r1 + 0x300] $r2 - - // enable interrupts - or $r2 0xc - iowr I[$r1] $r2 - bset $flags ie0 - - // enable fifo access and context switching - mov $r1 0x1200 - mov $r2 3 - iowr I[$r1] $r2 - - // sleep forever, waking for interrupts - bset $flags $p0 - spin: - sleep $p0 - bra #spin - -// i0 handler -ih: - iord $r1 I[$r0 + 0x200] - - and $r2 $r1 0x00000008 - bra e #ih_no_chsw - call #chsw - ih_no_chsw: - and $r2 $r1 0x00000004 - bra e #ih_no_cmd - call #dispatch - - ih_no_cmd: - and $r1 $r1 0x0000000c - iowr I[$r0 + 0x100] $r1 - iret - -// $p1 direction (0 = unload, 1 = load) -// $r3 channel -swctx: - mov $r4 0x7700 - mov $xtargets $r4 -#ifdef NVA3 - // target 7 hardcoded to ctx dma object - mov $xdbase $r0 -#else - // read SCRATCH3 to decide if we are PCOPY0 or PCOPY1 - mov $r4 0x2100 - iord $r4 I[$r4 + 0] - and $r4 1 - shl b32 $r4 4 - add b32 $r4 0x30 - - // channel is in vram - mov $r15 0x61c - shl b32 $r15 6 - mov $r5 0x114 - iowrs I[$r15] $r5 - - // read 16-byte PCOPYn info, containing context pointer, from channel - shl b32 $r5 $r3 4 - add b32 $r5 2 - mov $xdbase $r5 - mov $r5 $sp - // get a chunk of stack space, aligned to 256 byte boundary - sub b32 $r5 0x100 - mov $r6 0xff - not b32 $r6 - and $r5 $r6 - sethi $r5 0x00020000 - xdld $r4 $r5 - xdwait - sethi $r5 0 - - // set context pointer, from within channel VM - mov $r14 0 - iowrs I[$r15] $r14 - ld b32 $r4 D[$r5 + 0] - shr b32 $r4 8 - ld b32 $r6 D[$r5 + 4] - shl b32 $r6 24 - or $r4 $r6 - mov $xdbase $r4 -#endif - // 256-byte context, at start of data segment - mov b32 $r4 $r0 - sethi $r4 0x60000 - - // swap! - bra $p1 #swctx_load - xdst $r0 $r4 - bra #swctx_done - swctx_load: - xdld $r0 $r4 - swctx_done: - xdwait - ret - -chsw: - // read current channel - mov $r2 0x1400 - iord $r3 I[$r2] - - // if it's active, unload it and return - xbit $r15 $r3 0x1e - bra e #chsw_no_unload - bclr $flags $p1 - call #swctx - bclr $r3 0x1e - iowr I[$r2] $r3 - mov $r4 1 - iowr I[$r2 + 0x200] $r4 - ret - - // read next channel - chsw_no_unload: - iord $r3 I[$r2 + 0x100] - - // is there a channel waiting to be loaded? - xbit $r13 $r3 0x1e - bra e #chsw_finish_load - bset $flags $p1 - call #swctx -#ifdef NVA3 - // load dma objects back into TARGET regs - mov $r5 #ctx_dma - mov $r6 #ctx_dma_count - chsw_load_ctx_dma: - ld b32 $r7 D[$r5 + $r6 * 4] - add b32 $r8 $r6 0x180 - shl b32 $r8 8 - iowr I[$r8] $r7 - sub b32 $r6 1 - bra nc #chsw_load_ctx_dma -#endif - chsw_finish_load: - mov $r3 2 - iowr I[$r2 + 0x200] $r3 - ret - -dispatch: - // read incoming fifo command - mov $r3 0x1900 - iord $r2 I[$r3 + 0x100] - iord $r3 I[$r3 + 0x000] - and $r4 $r2 0x7ff - // $r2 will be used to store exception data - shl b32 $r2 0x10 - - // lookup method in the dispatch table, ILLEGAL_MTHD if not found - mov $r5 #dispatch_table - clear b32 $r6 - clear b32 $r7 - dispatch_loop: - ld b16 $r6 D[$r5 + 0] - ld b16 $r7 D[$r5 + 2] - add b32 $r5 4 - cmpu b32 $r4 $r6 - bra c #dispatch_illegal_mthd - add b32 $r7 $r6 - cmpu b32 $r4 $r7 - bra c #dispatch_valid_mthd - sub b32 $r7 $r6 - shl b32 $r7 3 - add b32 $r5 $r7 - bra #dispatch_loop - - // ensure no bits set in reserved fields, INVALID_BITFIELD - dispatch_valid_mthd: - sub b32 $r4 $r6 - shl b32 $r4 3 - add b32 $r4 $r5 - ld b32 $r5 D[$r4 + 4] - and $r5 $r3 - cmpu b32 $r5 0 - bra ne #dispatch_invalid_bitfield - - // depending on dispatch flags: execute method, or save data as state - ld b16 $r5 D[$r4 + 0] - ld b16 $r6 D[$r4 + 2] - cmpu b32 $r6 0 - bra ne #dispatch_cmd - st b32 D[$r5] $r3 - bra #dispatch_done - dispatch_cmd: - bclr $flags $p1 - call $r5 - bra $p1 #dispatch_error - bra #dispatch_done - - dispatch_invalid_bitfield: - or $r2 2 - dispatch_illegal_mthd: - or $r2 1 - - // store exception data in SCRATCH0/SCRATCH1, signal hostirq - dispatch_error: - mov $r4 0x1000 - iowr I[$r4 + 0x000] $r2 - iowr I[$r4 + 0x100] $r3 - mov $r2 0x40 - iowr I[$r0] $r2 - hostirq_wait: - iord $r2 I[$r0 + 0x200] - and $r2 0x40 - cmpu b32 $r2 0 - bra ne #hostirq_wait - - dispatch_done: - mov $r2 0x1d00 - mov $r3 1 - iowr I[$r2] $r3 - ret - -// No-operation -// -// Inputs: -// $r1: irqh state -// $r2: hostirq state -// $r3: data -// $r4: dispatch table entry -// Outputs: -// $r1: irqh state -// $p1: set on error -// $r2: hostirq state -// $r3: data -cmd_nop: - ret - -// PM_TRIGGER -// -// Inputs: -// $r1: irqh state -// $r2: hostirq state -// $r3: data -// $r4: dispatch table entry -// Outputs: -// $r1: irqh state -// $p1: set on error -// $r2: hostirq state -// $r3: data -cmd_pm_trigger: - mov $r2 0x2200 - clear b32 $r3 - sethi $r3 0x20000 - iowr I[$r2] $r3 - ret - -#ifdef NVA3 -// SET_DMA_* method handler -// -// Inputs: -// $r1: irqh state -// $r2: hostirq state -// $r3: data -// $r4: dispatch table entry -// Outputs: -// $r1: irqh state -// $p1: set on error -// $r2: hostirq state -// $r3: data -cmd_dma: - sub b32 $r4 #dispatch_dma - shr b32 $r4 1 - bset $r3 0x1e - st b32 D[$r4 + #ctx_dma] $r3 - add b32 $r4 0x600 - shl b32 $r4 6 - iowr I[$r4] $r3 - ret -#endif - -// Calculates the hw swizzle mask and adjusts the surface's xcnt to match -// -cmd_exec_set_format: - // zero out a chunk of the stack to store the swizzle into - add $sp -0x10 - st b32 D[$sp + 0x00] $r0 - st b32 D[$sp + 0x04] $r0 - st b32 D[$sp + 0x08] $r0 - st b32 D[$sp + 0x0c] $r0 - - // extract cpp, src_ncomp and dst_ncomp from FORMAT - ld b32 $r4 D[$r0 + #ctx_format] - extr $r5 $r4 16:17 - add b32 $r5 1 - extr $r6 $r4 20:21 - add b32 $r6 1 - extr $r7 $r4 24:25 - add b32 $r7 1 - - // convert FORMAT swizzle mask to hw swizzle mask - bclr $flags $p2 - clear b32 $r8 - clear b32 $r9 - ncomp_loop: - and $r10 $r4 0xf - shr b32 $r4 4 - clear b32 $r11 - bpc_loop: - cmpu b8 $r10 4 - bra nc #cmp_c0 - mulu $r12 $r10 $r5 - add b32 $r12 $r11 - bset $flags $p2 - bra #bpc_next - cmp_c0: - bra ne #cmp_c1 - mov $r12 0x10 - add b32 $r12 $r11 - bra #bpc_next - cmp_c1: - cmpu b8 $r10 6 - bra nc #cmp_zero - mov $r12 0x14 - add b32 $r12 $r11 - bra #bpc_next - cmp_zero: - mov $r12 0x80 - bpc_next: - st b8 D[$sp + $r8] $r12 - add b32 $r8 1 - add b32 $r11 1 - cmpu b32 $r11 $r5 - bra c #bpc_loop - add b32 $r9 1 - cmpu b32 $r9 $r7 - bra c #ncomp_loop - - // SRC_XCNT = (xcnt * src_cpp), or 0 if no src ref in swz (hw will hang) - mulu $r6 $r5 - st b32 D[$r0 + #ctx_src_cpp] $r6 - ld b32 $r8 D[$r0 + #ctx_xcnt] - mulu $r6 $r8 - bra $p2 #dst_xcnt - clear b32 $r6 - - dst_xcnt: - mulu $r7 $r5 - st b32 D[$r0 + #ctx_dst_cpp] $r7 - mulu $r7 $r8 - - mov $r5 0x810 - shl b32 $r5 6 - iowr I[$r5 + 0x000] $r6 - iowr I[$r5 + 0x100] $r7 - add b32 $r5 0x800 - ld b32 $r6 D[$r0 + #ctx_dst_cpp] - sub b32 $r6 1 - shl b32 $r6 8 - ld b32 $r7 D[$r0 + #ctx_src_cpp] - sub b32 $r7 1 - or $r6 $r7 - iowr I[$r5 + 0x000] $r6 - add b32 $r5 0x100 - ld b32 $r6 D[$sp + 0x00] - iowr I[$r5 + 0x000] $r6 - ld b32 $r6 D[$sp + 0x04] - iowr I[$r5 + 0x100] $r6 - ld b32 $r6 D[$sp + 0x08] - iowr I[$r5 + 0x200] $r6 - ld b32 $r6 D[$sp + 0x0c] - iowr I[$r5 + 0x300] $r6 - add b32 $r5 0x400 - ld b32 $r6 D[$r0 + #ctx_swz_const0] - iowr I[$r5 + 0x000] $r6 - ld b32 $r6 D[$r0 + #ctx_swz_const1] - iowr I[$r5 + 0x100] $r6 - add $sp 0x10 - ret - -// Setup to handle a tiled surface -// -// Calculates a number of parameters the hardware requires in order -// to correctly handle tiling. -// -// Offset calculation is performed as follows (Tp/Th/Td from TILE_MODE): -// nTx = round_up(w * cpp, 1 << Tp) >> Tp -// nTy = round_up(h, 1 << Th) >> Th -// Txo = (x * cpp) & ((1 << Tp) - 1) -// Tx = (x * cpp) >> Tp -// Tyo = y & ((1 << Th) - 1) -// Ty = y >> Th -// Tzo = z & ((1 << Td) - 1) -// Tz = z >> Td -// -// off = (Tzo << Tp << Th) + (Tyo << Tp) + Txo -// off += ((Tz * nTy * nTx)) + (Ty * nTx) + Tx) << Td << Th << Tp; -// -// Inputs: -// $r4: hw command (0x104800) -// $r5: ctx offset adjustment for src/dst selection -// $p2: set if dst surface -// -cmd_exec_set_surface_tiled: - // translate TILE_MODE into Tp, Th, Td shift values - ld b32 $r7 D[$r5 + #ctx_src_tile_mode] - extr $r9 $r7 8:11 - extr $r8 $r7 4:7 -#ifdef NVA3 - add b32 $r8 2 -#else - add b32 $r8 3 -#endif - extr $r7 $r7 0:3 - cmp b32 $r7 0xe - bra ne #xtile64 - mov $r7 4 - bra #xtileok - xtile64: - xbit $r7 $flags $p2 - add b32 $r7 17 - bset $r4 $r7 - mov $r7 6 - xtileok: - - // Op = (x * cpp) & ((1 << Tp) - 1) - // Tx = (x * cpp) >> Tp - ld b32 $r10 D[$r5 + #ctx_src_xoff] - ld b32 $r11 D[$r5 + #ctx_src_cpp] - mulu $r10 $r11 - mov $r11 1 - shl b32 $r11 $r7 - sub b32 $r11 1 - and $r12 $r10 $r11 - shr b32 $r10 $r7 - - // Tyo = y & ((1 << Th) - 1) - // Ty = y >> Th - ld b32 $r13 D[$r5 + #ctx_src_yoff] - mov $r14 1 - shl b32 $r14 $r8 - sub b32 $r14 1 - and $r11 $r13 $r14 - shr b32 $r13 $r8 - - // YTILE = ((1 << Th) << 12) | ((1 << Th) - Tyo) - add b32 $r14 1 - shl b32 $r15 $r14 12 - sub b32 $r14 $r11 - or $r15 $r14 - xbit $r6 $flags $p2 - add b32 $r6 0x208 - shl b32 $r6 8 - iowr I[$r6 + 0x000] $r15 - - // Op += Tyo << Tp - shl b32 $r11 $r7 - add b32 $r12 $r11 - - // nTx = ((w * cpp) + ((1 << Tp) - 1) >> Tp) - ld b32 $r15 D[$r5 + #ctx_src_xsize] - ld b32 $r11 D[$r5 + #ctx_src_cpp] - mulu $r15 $r11 - mov $r11 1 - shl b32 $r11 $r7 - sub b32 $r11 1 - add b32 $r15 $r11 - shr b32 $r15 $r7 - push $r15 - - // nTy = (h + ((1 << Th) - 1)) >> Th - ld b32 $r15 D[$r5 + #ctx_src_ysize] - mov $r11 1 - shl b32 $r11 $r8 - sub b32 $r11 1 - add b32 $r15 $r11 - shr b32 $r15 $r8 - push $r15 - - // Tys = Tp + Th - // CFG_YZ_TILE_SIZE = ((1 << Th) >> 2) << Td - add b32 $r7 $r8 - sub b32 $r8 2 - mov $r11 1 - shl b32 $r11 $r8 - shl b32 $r11 $r9 - - // Tzo = z & ((1 << Td) - 1) - // Tz = z >> Td - // Op += Tzo << Tys - // Ts = Tys + Td - ld b32 $r8 D[$r5 + #ctx_src_zoff] - mov $r14 1 - shl b32 $r14 $r9 - sub b32 $r14 1 - and $r15 $r8 $r14 - shl b32 $r15 $r7 - add b32 $r12 $r15 - add b32 $r7 $r9 - shr b32 $r8 $r9 - - // Ot = ((Tz * nTy * nTx) + (Ty * nTx) + Tx) << Ts - pop $r15 - pop $r9 - mulu $r13 $r9 - add b32 $r10 $r13 - mulu $r8 $r9 - mulu $r8 $r15 - add b32 $r10 $r8 - shl b32 $r10 $r7 - - // PITCH = (nTx - 1) << Ts - sub b32 $r9 1 - shl b32 $r9 $r7 - iowr I[$r6 + 0x200] $r9 - - // SRC_ADDRESS_LOW = (Ot + Op) & 0xffffffff - // CFG_ADDRESS_HIGH |= ((Ot + Op) >> 32) << 16 - ld b32 $r7 D[$r5 + #ctx_src_address_low] - ld b32 $r8 D[$r5 + #ctx_src_address_high] - add b32 $r10 $r12 - add b32 $r7 $r10 - adc b32 $r8 0 - shl b32 $r8 16 - or $r8 $r11 - sub b32 $r6 0x600 - iowr I[$r6 + 0x000] $r7 - add b32 $r6 0x400 - iowr I[$r6 + 0x000] $r8 - ret - -// Setup to handle a linear surface -// -// Nothing to see here.. Sets ADDRESS and PITCH, pretty non-exciting -// -cmd_exec_set_surface_linear: - xbit $r6 $flags $p2 - add b32 $r6 0x202 - shl b32 $r6 8 - ld b32 $r7 D[$r5 + #ctx_src_address_low] - iowr I[$r6 + 0x000] $r7 - add b32 $r6 0x400 - ld b32 $r7 D[$r5 + #ctx_src_address_high] - shl b32 $r7 16 - iowr I[$r6 + 0x000] $r7 - add b32 $r6 0x400 - ld b32 $r7 D[$r5 + #ctx_src_pitch] - iowr I[$r6 + 0x000] $r7 - ret - -// wait for regs to be available for use -cmd_exec_wait: - push $r0 - push $r1 - mov $r0 0x800 - shl b32 $r0 6 - loop: - iord $r1 I[$r0] - and $r1 1 - bra ne #loop - pop $r1 - pop $r0 - ret - -cmd_exec_query: - // if QUERY_SHORT not set, write out { -, 0, TIME_LO, TIME_HI } - xbit $r4 $r3 13 - bra ne #query_counter - call #cmd_exec_wait - mov $r4 0x80c - shl b32 $r4 6 - ld b32 $r5 D[$r0 + #ctx_query_address_low] - add b32 $r5 4 - iowr I[$r4 + 0x000] $r5 - iowr I[$r4 + 0x100] $r0 - mov $r5 0xc - iowr I[$r4 + 0x200] $r5 - add b32 $r4 0x400 - ld b32 $r5 D[$r0 + #ctx_query_address_high] - shl b32 $r5 16 - iowr I[$r4 + 0x000] $r5 - add b32 $r4 0x500 - mov $r5 0x00000b00 - sethi $r5 0x00010000 - iowr I[$r4 + 0x000] $r5 - mov $r5 0x00004040 - shl b32 $r5 1 - sethi $r5 0x80800000 - iowr I[$r4 + 0x100] $r5 - mov $r5 0x00001110 - sethi $r5 0x13120000 - iowr I[$r4 + 0x200] $r5 - mov $r5 0x00001514 - sethi $r5 0x17160000 - iowr I[$r4 + 0x300] $r5 - mov $r5 0x00002601 - sethi $r5 0x00010000 - mov $r4 0x800 - shl b32 $r4 6 - iowr I[$r4 + 0x000] $r5 - - // write COUNTER - query_counter: - call #cmd_exec_wait - mov $r4 0x80c - shl b32 $r4 6 - ld b32 $r5 D[$r0 + #ctx_query_address_low] - iowr I[$r4 + 0x000] $r5 - iowr I[$r4 + 0x100] $r0 - mov $r5 0x4 - iowr I[$r4 + 0x200] $r5 - add b32 $r4 0x400 - ld b32 $r5 D[$r0 + #ctx_query_address_high] - shl b32 $r5 16 - iowr I[$r4 + 0x000] $r5 - add b32 $r4 0x500 - mov $r5 0x00000300 - iowr I[$r4 + 0x000] $r5 - mov $r5 0x00001110 - sethi $r5 0x13120000 - iowr I[$r4 + 0x100] $r5 - ld b32 $r5 D[$r0 + #ctx_query_counter] - add b32 $r4 0x500 - iowr I[$r4 + 0x000] $r5 - mov $r5 0x00002601 - sethi $r5 0x00010000 - mov $r4 0x800 - shl b32 $r4 6 - iowr I[$r4 + 0x000] $r5 - ret - -// Execute a copy operation -// -// Inputs: -// $r1: irqh state -// $r2: hostirq state -// $r3: data -// 000002000 QUERY_SHORT -// 000001000 QUERY -// 000000100 DST_LINEAR -// 000000010 SRC_LINEAR -// 000000001 FORMAT -// $r4: dispatch table entry -// Outputs: -// $r1: irqh state -// $p1: set on error -// $r2: hostirq state -// $r3: data -cmd_exec: - call #cmd_exec_wait - - // if format requested, call function to calculate it, otherwise - // fill in cpp/xcnt for both surfaces as if (cpp == 1) - xbit $r15 $r3 0 - bra e #cmd_exec_no_format - call #cmd_exec_set_format - mov $r4 0x200 - bra #cmd_exec_init_src_surface - cmd_exec_no_format: - mov $r6 0x810 - shl b32 $r6 6 - mov $r7 1 - st b32 D[$r0 + #ctx_src_cpp] $r7 - st b32 D[$r0 + #ctx_dst_cpp] $r7 - ld b32 $r7 D[$r0 + #ctx_xcnt] - iowr I[$r6 + 0x000] $r7 - iowr I[$r6 + 0x100] $r7 - clear b32 $r4 - - cmd_exec_init_src_surface: - bclr $flags $p2 - clear b32 $r5 - xbit $r15 $r3 4 - bra e #src_tiled - call #cmd_exec_set_surface_linear - bra #cmd_exec_init_dst_surface - src_tiled: - call #cmd_exec_set_surface_tiled - bset $r4 7 - - cmd_exec_init_dst_surface: - bset $flags $p2 - mov $r5 #ctx_dst_address_high - #ctx_src_address_high - xbit $r15 $r3 8 - bra e #dst_tiled - call #cmd_exec_set_surface_linear - bra #cmd_exec_kick - dst_tiled: - call #cmd_exec_set_surface_tiled - bset $r4 8 - - cmd_exec_kick: - mov $r5 0x800 - shl b32 $r5 6 - ld b32 $r6 D[$r0 + #ctx_ycnt] - iowr I[$r5 + 0x100] $r6 - mov $r6 0x0041 - // SRC_TARGET = 1, DST_TARGET = 2 - sethi $r6 0x44000000 - or $r4 $r6 - iowr I[$r5] $r4 - - // if requested, queue up a QUERY write after the copy has completed - xbit $r15 $r3 12 - bra e #cmd_exec_done - call #cmd_exec_query - - cmd_exec_done: - ret - -// Flush write cache -// -// Inputs: -// $r1: irqh state -// $r2: hostirq state -// $r3: data -// $r4: dispatch table entry -// Outputs: -// $r1: irqh state -// $p1: set on error -// $r2: hostirq state -// $r3: data -cmd_wrcache_flush: - mov $r2 0x2200 - clear b32 $r3 - sethi $r3 0x10000 - iowr I[$r2] $r3 - ret - -.align 0x100 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nva3.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nva3.fuc3 deleted file mode 100644 index e670620..0000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nva3.fuc3 +++ /dev/null @@ -1,2 +0,0 @@ -#define NVA3 -#include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nva3.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nva3.fuc3.h deleted file mode 100644 index 241b272..0000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nva3.fuc3.h +++ /dev/null @@ -1,620 +0,0 @@ -uint32_t nva3_pcopy_data[] = { -/* 0x0000: ctx_object */ - 0x00000000, -/* 0x0004: ctx_dma */ -/* 0x0004: ctx_dma_query */ - 0x00000000, -/* 0x0008: ctx_dma_src */ - 0x00000000, -/* 0x000c: ctx_dma_dst */ - 0x00000000, -/* 0x0010: ctx_query_address_high */ - 0x00000000, -/* 0x0014: ctx_query_address_low */ - 0x00000000, -/* 0x0018: ctx_query_counter */ - 0x00000000, -/* 0x001c: ctx_src_address_high */ - 0x00000000, -/* 0x0020: ctx_src_address_low */ - 0x00000000, -/* 0x0024: ctx_src_pitch */ - 0x00000000, -/* 0x0028: ctx_src_tile_mode */ - 0x00000000, -/* 0x002c: ctx_src_xsize */ - 0x00000000, -/* 0x0030: ctx_src_ysize */ - 0x00000000, -/* 0x0034: ctx_src_zsize */ - 0x00000000, -/* 0x0038: ctx_src_zoff */ - 0x00000000, -/* 0x003c: ctx_src_xoff */ - 0x00000000, -/* 0x0040: ctx_src_yoff */ - 0x00000000, -/* 0x0044: ctx_src_cpp */ - 0x00000000, -/* 0x0048: ctx_dst_address_high */ - 0x00000000, -/* 0x004c: ctx_dst_address_low */ - 0x00000000, -/* 0x0050: ctx_dst_pitch */ - 0x00000000, -/* 0x0054: ctx_dst_tile_mode */ - 0x00000000, -/* 0x0058: ctx_dst_xsize */ - 0x00000000, -/* 0x005c: ctx_dst_ysize */ - 0x00000000, -/* 0x0060: ctx_dst_zsize */ - 0x00000000, -/* 0x0064: ctx_dst_zoff */ - 0x00000000, -/* 0x0068: ctx_dst_xoff */ - 0x00000000, -/* 0x006c: ctx_dst_yoff */ - 0x00000000, -/* 0x0070: ctx_dst_cpp */ - 0x00000000, -/* 0x0074: ctx_format */ - 0x00000000, -/* 0x0078: ctx_swz_const0 */ - 0x00000000, -/* 0x007c: ctx_swz_const1 */ - 0x00000000, -/* 0x0080: ctx_xcnt */ - 0x00000000, -/* 0x0084: ctx_ycnt */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0100: dispatch_table */ - 0x00010000, - 0x00000000, - 0x00000000, - 0x00010040, - 0x00010160, - 0x00000000, - 0x00010050, - 0x00010162, - 0x00000000, - 0x00030060, -/* 0x0128: dispatch_dma */ - 0x00010170, - 0x00000000, - 0x00010170, - 0x00000000, - 0x00010170, - 0x00000000, - 0x00070080, - 0x00000028, - 0xfffff000, - 0x0000002c, - 0xfff80000, - 0x00000030, - 0xffffe000, - 0x00000034, - 0xfffff800, - 0x00000038, - 0xfffff000, - 0x0000003c, - 0xfff80000, - 0x00000040, - 0xffffe000, - 0x00070088, - 0x00000054, - 0xfffff000, - 0x00000058, - 0xfff80000, - 0x0000005c, - 0xffffe000, - 0x00000060, - 0xfffff800, - 0x00000064, - 0xfffff000, - 0x00000068, - 0xfff80000, - 0x0000006c, - 0xffffe000, - 0x000200c0, - 0x00010492, - 0x00000000, - 0x0001051b, - 0x00000000, - 0x000e00c3, - 0x0000001c, - 0xffffff00, - 0x00000020, - 0x00000000, - 0x00000048, - 0xffffff00, - 0x0000004c, - 0x00000000, - 0x00000024, - 0xfff80000, - 0x00000050, - 0xfff80000, - 0x00000080, - 0xffff0000, - 0x00000084, - 0xffffe000, - 0x00000074, - 0xfccc0000, - 0x00000078, - 0x00000000, - 0x0000007c, - 0x00000000, - 0x00000010, - 0xffffff00, - 0x00000014, - 0x00000000, - 0x00000018, - 0x00000000, - 0x00000800, -}; - -uint32_t nva3_pcopy_code[] = { -/* 0x0000: main */ - 0x04fe04bd, - 0x3517f000, - 0xf10010fe, - 0xf1040017, - 0xf0fff327, - 0x12d00023, - 0x0c25f0c0, - 0xf40012d0, - 0x17f11031, - 0x27f01200, - 0x0012d003, -/* 0x002f: spin */ - 0xf40031f4, - 0x0ef40028, -/* 0x0035: ih */ - 0x8001cffd, - 0xf40812c4, - 0x21f4060b, -/* 0x0041: ih_no_chsw */ - 0x0412c472, - 0xf4060bf4, -/* 0x004a: ih_no_cmd */ - 0x11c4c321, - 0x4001d00c, -/* 0x0052: swctx */ - 0x47f101f8, - 0x4bfe7700, - 0x0007fe00, - 0xf00204b9, - 0x01f40643, - 0x0604fa09, -/* 0x006b: swctx_load */ - 0xfa060ef4, -/* 0x006e: swctx_done */ - 0x03f80504, -/* 0x0072: chsw */ - 0x27f100f8, - 0x23cf1400, - 0x1e3fc800, - 0xf4170bf4, - 0x21f40132, - 0x1e3af052, - 0xf00023d0, - 0x24d00147, -/* 0x0093: chsw_no_unload */ - 0xcf00f880, - 0x3dc84023, - 0x220bf41e, - 0xf40131f4, - 0x57f05221, - 0x0367f004, -/* 0x00a8: chsw_load_ctx_dma */ - 0xa07856bc, - 0xb6018068, - 0x87d00884, - 0x0162b600, -/* 0x00bb: chsw_finish_load */ - 0xf0f018f4, - 0x23d00237, -/* 0x00c3: dispatch */ - 0xf100f880, - 0xcf190037, - 0x33cf4032, - 0xff24e400, - 0x1024b607, - 0x010057f1, - 0x74bd64bd, -/* 0x00dc: dispatch_loop */ - 0x58005658, - 0x50b60157, - 0x0446b804, - 0xbb4d08f4, - 0x47b80076, - 0x0f08f404, - 0xb60276bb, - 0x57bb0374, - 0xdf0ef400, -/* 0x0100: dispatch_valid_mthd */ - 0xb60246bb, - 0x45bb0344, - 0x01459800, - 0xb00453fd, - 0x1bf40054, - 0x00455820, - 0xb0014658, - 0x1bf40064, - 0x00538009, -/* 0x0127: dispatch_cmd */ - 0xf4300ef4, - 0x55f90132, - 0xf40c01f4, -/* 0x0132: dispatch_invalid_bitfield */ - 0x25f0250e, -/* 0x0135: dispatch_illegal_mthd */ - 0x0125f002, -/* 0x0138: dispatch_error */ - 0x100047f1, - 0xd00042d0, - 0x27f04043, - 0x0002d040, -/* 0x0148: hostirq_wait */ - 0xf08002cf, - 0x24b04024, - 0xf71bf400, -/* 0x0154: dispatch_done */ - 0x1d0027f1, - 0xd00137f0, - 0x00f80023, -/* 0x0160: cmd_nop */ -/* 0x0162: cmd_pm_trigger */ - 0x27f100f8, - 0x34bd2200, - 0xd00233f0, - 0x00f80023, -/* 0x0170: cmd_dma */ - 0x012842b7, - 0xf00145b6, - 0x43801e39, - 0x0040b701, - 0x0644b606, - 0xf80043d0, -/* 0x0189: cmd_exec_set_format */ - 0xf030f400, - 0xb00001b0, - 0x01b00101, - 0x0301b002, - 0xc71d0498, - 0x50b63045, - 0x3446c701, - 0xc70160b6, - 0x70b63847, - 0x0232f401, - 0x94bd84bd, -/* 0x01b4: ncomp_loop */ - 0xb60f4ac4, - 0xb4bd0445, -/* 0x01bc: bpc_loop */ - 0xf404a430, - 0xa5ff0f18, - 0x00cbbbc0, - 0xf40231f4, -/* 0x01ce: cmp_c0 */ - 0x1bf4220e, - 0x10c7f00c, - 0xf400cbbb, -/* 0x01da: cmp_c1 */ - 0xa430160e, - 0x0c18f406, - 0xbb14c7f0, - 0x0ef400cb, -/* 0x01e9: cmp_zero */ - 0x80c7f107, -/* 0x01ed: bpc_next */ - 0x01c83800, - 0xb60180b6, - 0xb5b801b0, - 0xc308f404, - 0xb80190b6, - 0x08f40497, - 0x0065fdb2, - 0x98110680, - 0x68fd2008, - 0x0502f400, -/* 0x0216: dst_xcnt */ - 0x75fd64bd, - 0x1c078000, - 0xf10078fd, - 0xb6081057, - 0x56d00654, - 0x4057d000, - 0x080050b7, - 0xb61c0698, - 0x64b60162, - 0x11079808, - 0xfd0172b6, - 0x56d00567, - 0x0050b700, - 0x0060b401, - 0xb40056d0, - 0x56d00160, - 0x0260b440, - 0xb48056d0, - 0x56d00360, - 0x0050b7c0, - 0x1e069804, - 0x980056d0, - 0x56d01f06, - 0x1030f440, -/* 0x0276: cmd_exec_set_surface_tiled */ - 0x579800f8, - 0x6879c70a, - 0xb66478c7, - 0x77c70280, - 0x0e76b060, - 0xf0091bf4, - 0x0ef40477, -/* 0x0291: xtile64 */ - 0x027cf00f, - 0xfd1170b6, - 0x77f00947, -/* 0x029d: xtileok */ - 0x0f5a9806, - 0xfd115b98, - 0xb7f000ab, - 0x04b7bb01, - 0xff01b2b6, - 0xa7bbc4ab, - 0x105d9805, - 0xbb01e7f0, - 0xe2b604e8, - 0xb4deff01, - 0xb605d8bb, - 0xef9401e0, - 0x02ebbb0c, - 0xf005fefd, - 0x60b7026c, - 0x64b60208, - 0x006fd008, - 0xbb04b7bb, - 0x5f9800cb, - 0x115b980b, - 0xf000fbfd, - 0xb7bb01b7, - 0x01b2b604, - 0xbb00fbbb, - 0xf0f905f7, - 0xf00c5f98, - 0xb8bb01b7, - 0x01b2b604, - 0xbb00fbbb, - 0xf0f905f8, - 0xb60078bb, - 0xb7f00282, - 0x04b8bb01, - 0x9804b9bb, - 0xe7f00e58, - 0x04e9bb01, - 0xff01e2b6, - 0xf7bbf48e, - 0x00cfbb04, - 0xbb0079bb, - 0xf0fc0589, - 0xd9fd90fc, - 0x00adbb00, - 0xfd0089fd, - 0xa8bb008f, - 0x04a7bb00, - 0xbb0192b6, - 0x69d00497, - 0x08579880, - 0xbb075898, - 0x7abb00ac, - 0x0081b600, - 0xfd1084b6, - 0x62b7058b, - 0x67d00600, - 0x0060b700, - 0x0068d004, -/* 0x0382: cmd_exec_set_surface_linear */ - 0x6cf000f8, - 0x0260b702, - 0x0864b602, - 0xd0085798, - 0x60b70067, - 0x57980400, - 0x1074b607, - 0xb70067d0, - 0x98040060, - 0x67d00957, -/* 0x03ab: cmd_exec_wait */ - 0xf900f800, - 0xf110f900, - 0xb6080007, -/* 0x03b6: loop */ - 0x01cf0604, - 0x0114f000, - 0xfcfa1bf4, - 0xf800fc10, -/* 0x03c5: cmd_exec_query */ - 0x0d34c800, - 0xf5701bf4, - 0xf103ab21, - 0xb6080c47, - 0x05980644, - 0x0450b605, - 0xd00045d0, - 0x57f04040, - 0x8045d00c, - 0x040040b7, - 0xb6040598, - 0x45d01054, - 0x0040b700, - 0x0057f105, - 0x0153f00b, - 0xf10045d0, - 0xb6404057, - 0x53f10154, - 0x45d08080, - 0x1057f140, - 0x1253f111, - 0x8045d013, - 0x151457f1, - 0x171653f1, - 0xf1c045d0, - 0xf0260157, - 0x47f10153, - 0x44b60800, - 0x0045d006, -/* 0x0438: query_counter */ - 0x03ab21f5, - 0x080c47f1, - 0x980644b6, - 0x45d00505, - 0x4040d000, - 0xd00457f0, - 0x40b78045, - 0x05980400, - 0x1054b604, - 0xb70045d0, - 0xf1050040, - 0xd0030057, - 0x57f10045, - 0x53f11110, - 0x45d01312, - 0x06059840, - 0x050040b7, - 0xf10045d0, - 0xf0260157, - 0x47f10153, - 0x44b60800, - 0x0045d006, -/* 0x0492: cmd_exec */ - 0x21f500f8, - 0x3fc803ab, - 0x0e0bf400, - 0x018921f5, - 0x020047f1, -/* 0x04a7: cmd_exec_no_format */ - 0xf11e0ef4, - 0xb6081067, - 0x77f00664, - 0x11078001, - 0x981c0780, - 0x67d02007, - 0x4067d000, -/* 0x04c2: cmd_exec_init_src_surface */ - 0x32f444bd, - 0xc854bd02, - 0x0bf4043f, - 0x8221f50a, - 0x0a0ef403, -/* 0x04d4: src_tiled */ - 0x027621f5, -/* 0x04db: cmd_exec_init_dst_surface */ - 0xf40749f0, - 0x57f00231, - 0x083fc82c, - 0xf50a0bf4, - 0xf4038221, -/* 0x04ee: dst_tiled */ - 0x21f50a0e, - 0x49f00276, -/* 0x04f5: cmd_exec_kick */ - 0x0057f108, - 0x0654b608, - 0xd0210698, - 0x67f04056, - 0x0063f141, - 0x0546fd44, - 0xc80054d0, - 0x0bf40c3f, - 0xc521f507, -/* 0x0519: cmd_exec_done */ -/* 0x051b: cmd_wrcache_flush */ - 0xf100f803, - 0xbd220027, - 0x0133f034, - 0xf80023d0, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nvc0.fuc3 deleted file mode 100644 index df6866c..0000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nvc0.fuc3 +++ /dev/null @@ -1,2 +0,0 @@ -#define NVC0 -#include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nvc0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nvc0.fuc3.h deleted file mode 100644 index 98cc421..0000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nvc0.fuc3.h +++ /dev/null @@ -1,606 +0,0 @@ -uint32_t nvc0_pcopy_data[] = { -/* 0x0000: ctx_object */ - 0x00000000, -/* 0x0004: ctx_query_address_high */ - 0x00000000, -/* 0x0008: ctx_query_address_low */ - 0x00000000, -/* 0x000c: ctx_query_counter */ - 0x00000000, -/* 0x0010: ctx_src_address_high */ - 0x00000000, -/* 0x0014: ctx_src_address_low */ - 0x00000000, -/* 0x0018: ctx_src_pitch */ - 0x00000000, -/* 0x001c: ctx_src_tile_mode */ - 0x00000000, -/* 0x0020: ctx_src_xsize */ - 0x00000000, -/* 0x0024: ctx_src_ysize */ - 0x00000000, -/* 0x0028: ctx_src_zsize */ - 0x00000000, -/* 0x002c: ctx_src_zoff */ - 0x00000000, -/* 0x0030: ctx_src_xoff */ - 0x00000000, -/* 0x0034: ctx_src_yoff */ - 0x00000000, -/* 0x0038: ctx_src_cpp */ - 0x00000000, -/* 0x003c: ctx_dst_address_high */ - 0x00000000, -/* 0x0040: ctx_dst_address_low */ - 0x00000000, -/* 0x0044: ctx_dst_pitch */ - 0x00000000, -/* 0x0048: ctx_dst_tile_mode */ - 0x00000000, -/* 0x004c: ctx_dst_xsize */ - 0x00000000, -/* 0x0050: ctx_dst_ysize */ - 0x00000000, -/* 0x0054: ctx_dst_zsize */ - 0x00000000, -/* 0x0058: ctx_dst_zoff */ - 0x00000000, -/* 0x005c: ctx_dst_xoff */ - 0x00000000, -/* 0x0060: ctx_dst_yoff */ - 0x00000000, -/* 0x0064: ctx_dst_cpp */ - 0x00000000, -/* 0x0068: ctx_format */ - 0x00000000, -/* 0x006c: ctx_swz_const0 */ - 0x00000000, -/* 0x0070: ctx_swz_const1 */ - 0x00000000, -/* 0x0074: ctx_xcnt */ - 0x00000000, -/* 0x0078: ctx_ycnt */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0100: dispatch_table */ - 0x00010000, - 0x00000000, - 0x00000000, - 0x00010040, - 0x0001019f, - 0x00000000, - 0x00010050, - 0x000101a1, - 0x00000000, - 0x00070080, - 0x0000001c, - 0xfffff000, - 0x00000020, - 0xfff80000, - 0x00000024, - 0xffffe000, - 0x00000028, - 0xfffff800, - 0x0000002c, - 0xfffff000, - 0x00000030, - 0xfff80000, - 0x00000034, - 0xffffe000, - 0x00070088, - 0x00000048, - 0xfffff000, - 0x0000004c, - 0xfff80000, - 0x00000050, - 0xffffe000, - 0x00000054, - 0xfffff800, - 0x00000058, - 0xfffff000, - 0x0000005c, - 0xfff80000, - 0x00000060, - 0xffffe000, - 0x000200c0, - 0x000104b8, - 0x00000000, - 0x00010541, - 0x00000000, - 0x000e00c3, - 0x00000010, - 0xffffff00, - 0x00000014, - 0x00000000, - 0x0000003c, - 0xffffff00, - 0x00000040, - 0x00000000, - 0x00000018, - 0xfff80000, - 0x00000044, - 0xfff80000, - 0x00000074, - 0xffff0000, - 0x00000078, - 0xffffe000, - 0x00000068, - 0xfccc0000, - 0x0000006c, - 0x00000000, - 0x00000070, - 0x00000000, - 0x00000004, - 0xffffff00, - 0x00000008, - 0x00000000, - 0x0000000c, - 0x00000000, - 0x00000800, -}; - -uint32_t nvc0_pcopy_code[] = { -/* 0x0000: main */ - 0x04fe04bd, - 0x3517f000, - 0xf10010fe, - 0xf1040017, - 0xf0fff327, - 0x12d00023, - 0x0c25f0c0, - 0xf40012d0, - 0x17f11031, - 0x27f01200, - 0x0012d003, -/* 0x002f: spin */ - 0xf40031f4, - 0x0ef40028, -/* 0x0035: ih */ - 0x8001cffd, - 0xf40812c4, - 0x21f4060b, -/* 0x0041: ih_no_chsw */ - 0x0412c4ca, - 0xf5070bf4, -/* 0x004b: ih_no_cmd */ - 0xc4010221, - 0x01d00c11, -/* 0x0053: swctx */ - 0xf101f840, - 0xfe770047, - 0x47f1004b, - 0x44cf2100, - 0x0144f000, - 0xb60444b6, - 0xf7f13040, - 0xf4b6061c, - 0x1457f106, - 0x00f5d101, - 0xb6043594, - 0x57fe0250, - 0x0145fe00, - 0x010052b7, - 0x00ff67f1, - 0x56fd60bd, - 0x0253f004, - 0xf80545fa, - 0x0053f003, - 0xd100e7f0, - 0x549800fe, - 0x0845b600, - 0xb6015698, - 0x46fd1864, - 0x0047fe05, - 0xf00204b9, - 0x01f40643, - 0x0604fa09, -/* 0x00c3: swctx_load */ - 0xfa060ef4, -/* 0x00c6: swctx_done */ - 0x03f80504, -/* 0x00ca: chsw */ - 0x27f100f8, - 0x23cf1400, - 0x1e3fc800, - 0xf4170bf4, - 0x21f40132, - 0x1e3af053, - 0xf00023d0, - 0x24d00147, -/* 0x00eb: chsw_no_unload */ - 0xcf00f880, - 0x3dc84023, - 0x090bf41e, - 0xf40131f4, -/* 0x00fa: chsw_finish_load */ - 0x37f05321, - 0x8023d002, -/* 0x0102: dispatch */ - 0x37f100f8, - 0x32cf1900, - 0x0033cf40, - 0x07ff24e4, - 0xf11024b6, - 0xbd010057, -/* 0x011b: dispatch_loop */ - 0x5874bd64, - 0x57580056, - 0x0450b601, - 0xf40446b8, - 0x76bb4d08, - 0x0447b800, - 0xbb0f08f4, - 0x74b60276, - 0x0057bb03, -/* 0x013f: dispatch_valid_mthd */ - 0xbbdf0ef4, - 0x44b60246, - 0x0045bb03, - 0xfd014598, - 0x54b00453, - 0x201bf400, - 0x58004558, - 0x64b00146, - 0x091bf400, - 0xf4005380, -/* 0x0166: dispatch_cmd */ - 0x32f4300e, - 0xf455f901, - 0x0ef40c01, -/* 0x0171: dispatch_invalid_bitfield */ - 0x0225f025, -/* 0x0174: dispatch_illegal_mthd */ -/* 0x0177: dispatch_error */ - 0xf10125f0, - 0xd0100047, - 0x43d00042, - 0x4027f040, -/* 0x0187: hostirq_wait */ - 0xcf0002d0, - 0x24f08002, - 0x0024b040, -/* 0x0193: dispatch_done */ - 0xf1f71bf4, - 0xf01d0027, - 0x23d00137, -/* 0x019f: cmd_nop */ - 0xf800f800, -/* 0x01a1: cmd_pm_trigger */ - 0x0027f100, - 0xf034bd22, - 0x23d00233, -/* 0x01af: cmd_exec_set_format */ - 0xf400f800, - 0x01b0f030, - 0x0101b000, - 0xb00201b0, - 0x04980301, - 0x3045c71a, - 0xc70150b6, - 0x60b63446, - 0x3847c701, - 0xf40170b6, - 0x84bd0232, -/* 0x01da: ncomp_loop */ - 0x4ac494bd, - 0x0445b60f, -/* 0x01e2: bpc_loop */ - 0xa430b4bd, - 0x0f18f404, - 0xbbc0a5ff, - 0x31f400cb, - 0x220ef402, -/* 0x01f4: cmp_c0 */ - 0xf00c1bf4, - 0xcbbb10c7, - 0x160ef400, -/* 0x0200: cmp_c1 */ - 0xf406a430, - 0xc7f00c18, - 0x00cbbb14, -/* 0x020f: cmp_zero */ - 0xf1070ef4, -/* 0x0213: bpc_next */ - 0x380080c7, - 0x80b601c8, - 0x01b0b601, - 0xf404b5b8, - 0x90b6c308, - 0x0497b801, - 0xfdb208f4, - 0x06800065, - 0x1d08980e, - 0xf40068fd, - 0x64bd0502, -/* 0x023c: dst_xcnt */ - 0x800075fd, - 0x78fd1907, - 0x1057f100, - 0x0654b608, - 0xd00056d0, - 0x50b74057, - 0x06980800, - 0x0162b619, - 0x980864b6, - 0x72b60e07, - 0x0567fd01, - 0xb70056d0, - 0xb4010050, - 0x56d00060, - 0x0160b400, - 0xb44056d0, - 0x56d00260, - 0x0360b480, - 0xb7c056d0, - 0x98040050, - 0x56d01b06, - 0x1c069800, - 0xf44056d0, - 0x00f81030, -/* 0x029c: cmd_exec_set_surface_tiled */ - 0xc7075798, - 0x78c76879, - 0x0380b664, - 0xb06077c7, - 0x1bf40e76, - 0x0477f009, -/* 0x02b7: xtile64 */ - 0xf00f0ef4, - 0x70b6027c, - 0x0947fd11, -/* 0x02c3: xtileok */ - 0x980677f0, - 0x5b980c5a, - 0x00abfd0e, - 0xbb01b7f0, - 0xb2b604b7, - 0xc4abff01, - 0x9805a7bb, - 0xe7f00d5d, - 0x04e8bb01, - 0xff01e2b6, - 0xd8bbb4de, - 0x01e0b605, - 0xbb0cef94, - 0xfefd02eb, - 0x026cf005, - 0x020860b7, - 0xd00864b6, - 0xb7bb006f, - 0x00cbbb04, - 0x98085f98, - 0xfbfd0e5b, - 0x01b7f000, - 0xb604b7bb, - 0xfbbb01b2, - 0x05f7bb00, - 0x5f98f0f9, - 0x01b7f009, - 0xb604b8bb, - 0xfbbb01b2, - 0x05f8bb00, - 0x78bbf0f9, - 0x0282b600, - 0xbb01b7f0, - 0xb9bb04b8, - 0x0b589804, - 0xbb01e7f0, - 0xe2b604e9, - 0xf48eff01, - 0xbb04f7bb, - 0x79bb00cf, - 0x0589bb00, - 0x90fcf0fc, - 0xbb00d9fd, - 0x89fd00ad, - 0x008ffd00, - 0xbb00a8bb, - 0x92b604a7, - 0x0497bb01, - 0x988069d0, - 0x58980557, - 0x00acbb04, - 0xb6007abb, - 0x84b60081, - 0x058bfd10, - 0x060062b7, - 0xb70067d0, - 0xd0040060, - 0x00f80068, -/* 0x03a8: cmd_exec_set_surface_linear */ - 0xb7026cf0, - 0xb6020260, - 0x57980864, - 0x0067d005, - 0x040060b7, - 0xb6045798, - 0x67d01074, - 0x0060b700, - 0x06579804, - 0xf80067d0, -/* 0x03d1: cmd_exec_wait */ - 0xf900f900, - 0x0007f110, - 0x0604b608, -/* 0x03dc: loop */ - 0xf00001cf, - 0x1bf40114, - 0xfc10fcfa, -/* 0x03eb: cmd_exec_query */ - 0xc800f800, - 0x1bf40d34, - 0xd121f570, - 0x0c47f103, - 0x0644b608, - 0xb6020598, - 0x45d00450, - 0x4040d000, - 0xd00c57f0, - 0x40b78045, - 0x05980400, - 0x1054b601, - 0xb70045d0, - 0xf1050040, - 0xf00b0057, - 0x45d00153, - 0x4057f100, - 0x0154b640, - 0x808053f1, - 0xf14045d0, - 0xf1111057, - 0xd0131253, - 0x57f18045, - 0x53f11514, - 0x45d01716, - 0x0157f1c0, - 0x0153f026, - 0x080047f1, - 0xd00644b6, -/* 0x045e: query_counter */ - 0x21f50045, - 0x47f103d1, - 0x44b6080c, - 0x02059806, - 0xd00045d0, - 0x57f04040, - 0x8045d004, - 0x040040b7, - 0xb6010598, - 0x45d01054, - 0x0040b700, - 0x0057f105, - 0x0045d003, - 0x111057f1, - 0x131253f1, - 0x984045d0, - 0x40b70305, - 0x45d00500, - 0x0157f100, - 0x0153f026, - 0x080047f1, - 0xd00644b6, - 0x00f80045, -/* 0x04b8: cmd_exec */ - 0x03d121f5, - 0xf4003fc8, - 0x21f50e0b, - 0x47f101af, - 0x0ef40200, -/* 0x04cd: cmd_exec_no_format */ - 0x1067f11e, - 0x0664b608, - 0x800177f0, - 0x07800e07, - 0x1d079819, - 0xd00067d0, - 0x44bd4067, -/* 0x04e8: cmd_exec_init_src_surface */ - 0xbd0232f4, - 0x043fc854, - 0xf50a0bf4, - 0xf403a821, -/* 0x04fa: src_tiled */ - 0x21f50a0e, - 0x49f0029c, -/* 0x0501: cmd_exec_init_dst_surface */ - 0x0231f407, - 0xc82c57f0, - 0x0bf4083f, - 0xa821f50a, - 0x0a0ef403, -/* 0x0514: dst_tiled */ - 0x029c21f5, -/* 0x051b: cmd_exec_kick */ - 0xf10849f0, - 0xb6080057, - 0x06980654, - 0x4056d01e, - 0xf14167f0, - 0xfd440063, - 0x54d00546, - 0x0c3fc800, - 0xf5070bf4, -/* 0x053f: cmd_exec_done */ - 0xf803eb21, -/* 0x0541: cmd_wrcache_flush */ - 0x0027f100, - 0xf034bd22, - 0x23d00133, - 0x0000f800, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c deleted file mode 100644 index 6ae6496..0000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include -#include - -#include -#include - -#include -#include - - -#include "fuc/nva3.fuc3.h" - -struct nva3_copy_priv { - struct nouveau_falcon base; -}; - -/******************************************************************************* - * Copy object classes - ******************************************************************************/ - -static struct nouveau_oclass -nva3_copy_sclass[] = { - { 0x85b5, &nouveau_object_ofuncs }, - {} -}; - -/******************************************************************************* - * PCOPY context - ******************************************************************************/ - -static struct nouveau_oclass -nva3_copy_cclass = { - .handle = NV_ENGCTX(COPY0, 0xa3), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_falcon_context_ctor, - .dtor = _nouveau_falcon_context_dtor, - .init = _nouveau_falcon_context_init, - .fini = _nouveau_falcon_context_fini, - .rd32 = _nouveau_falcon_context_rd32, - .wr32 = _nouveau_falcon_context_wr32, - - }, -}; - -/******************************************************************************* - * PCOPY engine/subdev functions - ******************************************************************************/ - -static const struct nouveau_enum nva3_copy_isr_error_name[] = { - { 0x0001, "ILLEGAL_MTHD" }, - { 0x0002, "INVALID_ENUM" }, - { 0x0003, "INVALID_BITFIELD" }, - {} -}; - -void -nva3_copy_intr(struct nouveau_subdev *subdev) -{ - struct nouveau_fifo *pfifo = nouveau_fifo(subdev); - struct nouveau_engine *engine = nv_engine(subdev); - struct nouveau_falcon *falcon = (void *)subdev; - struct nouveau_object *engctx; - u32 dispatch = nv_ro32(falcon, 0x01c); - u32 stat = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16); - u64 inst = nv_ro32(falcon, 0x050) & 0x3fffffff; - u32 ssta = nv_ro32(falcon, 0x040) & 0x0000ffff; - u32 addr = nv_ro32(falcon, 0x040) >> 16; - u32 mthd = (addr & 0x07ff) << 2; - u32 subc = (addr & 0x3800) >> 11; - u32 data = nv_ro32(falcon, 0x044); - int chid; - - engctx = nouveau_engctx_get(engine, inst); - chid = pfifo->chid(pfifo, engctx); - - if (stat & 0x00000040) { - nv_error(falcon, "DISPATCH_ERROR ["); - nouveau_enum_print(nva3_copy_isr_error_name, ssta); - pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n", - chid, inst << 12, nouveau_client_name(engctx), subc, - mthd, data); - nv_wo32(falcon, 0x004, 0x00000040); - stat &= ~0x00000040; - } - - if (stat) { - nv_error(falcon, "unhandled intr 0x%08x\n", stat); - nv_wo32(falcon, 0x004, stat); - } - - nouveau_engctx_put(engctx); -} - -static int -nva3_copy_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - bool enable = (nv_device(parent)->chipset != 0xaf); - struct nva3_copy_priv *priv; - int ret; - - ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, enable, - "PCE0", "copy0", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00802000; - nv_subdev(priv)->intr = nva3_copy_intr; - nv_engine(priv)->cclass = &nva3_copy_cclass; - nv_engine(priv)->sclass = nva3_copy_sclass; - nv_falcon(priv)->code.data = nva3_pcopy_code; - nv_falcon(priv)->code.size = sizeof(nva3_pcopy_code); - nv_falcon(priv)->data.data = nva3_pcopy_data; - nv_falcon(priv)->data.size = sizeof(nva3_pcopy_data); - return 0; -} - -struct nouveau_oclass -nva3_copy_oclass = { - .handle = NV_ENGINE(COPY0, 0xa3), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nva3_copy_ctor, - .dtor = _nouveau_falcon_dtor, - .init = _nouveau_falcon_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/copy/nvc0.c deleted file mode 100644 index abe3249..0000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nvc0.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include -#include - -#include -#include - -#include "fuc/nvc0.fuc3.h" - -struct nvc0_copy_priv { - struct nouveau_falcon base; -}; - -/******************************************************************************* - * Copy object classes - ******************************************************************************/ - -static struct nouveau_oclass -nvc0_copy0_sclass[] = { - { 0x90b5, &nouveau_object_ofuncs }, - {}, -}; - -static struct nouveau_oclass -nvc0_copy1_sclass[] = { - { 0x90b8, &nouveau_object_ofuncs }, - {}, -}; - -/******************************************************************************* - * PCOPY context - ******************************************************************************/ - -static struct nouveau_ofuncs -nvc0_copy_context_ofuncs = { - .ctor = _nouveau_falcon_context_ctor, - .dtor = _nouveau_falcon_context_dtor, - .init = _nouveau_falcon_context_init, - .fini = _nouveau_falcon_context_fini, - .rd32 = _nouveau_falcon_context_rd32, - .wr32 = _nouveau_falcon_context_wr32, -}; - -static struct nouveau_oclass -nvc0_copy0_cclass = { - .handle = NV_ENGCTX(COPY0, 0xc0), - .ofuncs = &nvc0_copy_context_ofuncs, -}; - -static struct nouveau_oclass -nvc0_copy1_cclass = { - .handle = NV_ENGCTX(COPY1, 0xc0), - .ofuncs = &nvc0_copy_context_ofuncs, -}; - -/******************************************************************************* - * PCOPY engine/subdev functions - ******************************************************************************/ - -static int -nvc0_copy_init(struct nouveau_object *object) -{ - struct nvc0_copy_priv *priv = (void *)object; - int ret; - - ret = nouveau_falcon_init(&priv->base); - if (ret) - return ret; - - nv_wo32(priv, 0x084, nv_engidx(&priv->base.base) - NVDEV_ENGINE_COPY0); - return 0; -} - -static int -nvc0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvc0_copy_priv *priv; - int ret; - - ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, true, - "PCE0", "copy0", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00000040; - nv_subdev(priv)->intr = nva3_copy_intr; - nv_engine(priv)->cclass = &nvc0_copy0_cclass; - nv_engine(priv)->sclass = nvc0_copy0_sclass; - nv_falcon(priv)->code.data = nvc0_pcopy_code; - nv_falcon(priv)->code.size = sizeof(nvc0_pcopy_code); - nv_falcon(priv)->data.data = nvc0_pcopy_data; - nv_falcon(priv)->data.size = sizeof(nvc0_pcopy_data); - return 0; -} - -static int -nvc0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvc0_copy_priv *priv; - int ret; - - ret = nouveau_falcon_create(parent, engine, oclass, 0x105000, true, - "PCE1", "copy1", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00000080; - nv_subdev(priv)->intr = nva3_copy_intr; - nv_engine(priv)->cclass = &nvc0_copy1_cclass; - nv_engine(priv)->sclass = nvc0_copy1_sclass; - nv_falcon(priv)->code.data = nvc0_pcopy_code; - nv_falcon(priv)->code.size = sizeof(nvc0_pcopy_code); - nv_falcon(priv)->data.data = nvc0_pcopy_data; - nv_falcon(priv)->data.size = sizeof(nvc0_pcopy_data); - return 0; -} - -struct nouveau_oclass -nvc0_copy0_oclass = { - .handle = NV_ENGINE(COPY0, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_copy0_ctor, - .dtor = _nouveau_falcon_dtor, - .init = nvc0_copy_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, - }, -}; - -struct nouveau_oclass -nvc0_copy1_oclass = { - .handle = NV_ENGINE(COPY1, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_copy1_ctor, - .dtor = _nouveau_falcon_dtor, - .init = nvc0_copy_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/copy/nve0.c deleted file mode 100644 index b140a01..0000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nve0.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include -#include - -#include - -struct nve0_copy_priv { - struct nouveau_engine base; -}; - -/******************************************************************************* - * Copy object classes - ******************************************************************************/ - -static struct nouveau_oclass -nve0_copy_sclass[] = { - { 0xa0b5, &nouveau_object_ofuncs }, - {}, -}; - -/******************************************************************************* - * PCOPY context - ******************************************************************************/ - -static struct nouveau_ofuncs -nve0_copy_context_ofuncs = { - .ctor = _nouveau_engctx_ctor, - .dtor = _nouveau_engctx_dtor, - .init = _nouveau_engctx_init, - .fini = _nouveau_engctx_fini, - .rd32 = _nouveau_engctx_rd32, - .wr32 = _nouveau_engctx_wr32, -}; - -static struct nouveau_oclass -nve0_copy_cclass = { - .handle = NV_ENGCTX(COPY0, 0xc0), - .ofuncs = &nve0_copy_context_ofuncs, -}; - -/******************************************************************************* - * PCOPY engine/subdev functions - ******************************************************************************/ - -static void -nve0_copy_intr(struct nouveau_subdev *subdev) -{ - const int ce = nv_subidx(subdev) - NVDEV_ENGINE_COPY0; - struct nve0_copy_priv *priv = (void *)subdev; - u32 stat = nv_rd32(priv, 0x104908 + (ce * 0x1000)); - - if (stat) { - nv_warn(priv, "unhandled intr 0x%08x\n", stat); - nv_wr32(priv, 0x104908 + (ce * 0x1000), stat); - } -} - -static int -nve0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nve0_copy_priv *priv; - int ret; - - ret = nouveau_engine_create(parent, engine, oclass, true, - "PCE0", "copy0", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00000040; - nv_subdev(priv)->intr = nve0_copy_intr; - nv_engine(priv)->cclass = &nve0_copy_cclass; - nv_engine(priv)->sclass = nve0_copy_sclass; - return 0; -} - -static int -nve0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nve0_copy_priv *priv; - int ret; - - ret = nouveau_engine_create(parent, engine, oclass, true, - "PCE1", "copy1", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00000080; - nv_subdev(priv)->intr = nve0_copy_intr; - nv_engine(priv)->cclass = &nve0_copy_cclass; - nv_engine(priv)->sclass = nve0_copy_sclass; - return 0; -} - -static int -nve0_copy2_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nve0_copy_priv *priv; - int ret; - - ret = nouveau_engine_create(parent, engine, oclass, true, - "PCE2", "copy2", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00200000; - nv_subdev(priv)->intr = nve0_copy_intr; - nv_engine(priv)->cclass = &nve0_copy_cclass; - nv_engine(priv)->sclass = nve0_copy_sclass; - return 0; -} - -struct nouveau_oclass -nve0_copy0_oclass = { - .handle = NV_ENGINE(COPY0, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_copy0_ctor, - .dtor = _nouveau_engine_dtor, - .init = _nouveau_engine_init, - .fini = _nouveau_engine_fini, - }, -}; - -struct nouveau_oclass -nve0_copy1_oclass = { - .handle = NV_ENGINE(COPY1, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_copy1_ctor, - .dtor = _nouveau_engine_dtor, - .init = _nouveau_engine_init, - .fini = _nouveau_engine_fini, - }, -}; - -struct nouveau_oclass -nve0_copy2_oclass = { - .handle = NV_ENGINE(COPY2, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_copy2_ctor, - .dtor = _nouveau_engine_dtor, - .init = _nouveau_engine_init, - .fini = _nouveau_engine_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index fe269ef..96050a4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -235,9 +235,9 @@ static const u64 disable_map[] = { [NVDEV_ENGINE_CIPHER] = NV_DEVICE_V0_DISABLE_CIPHER, [NVDEV_ENGINE_BSP] = NV_DEVICE_V0_DISABLE_BSP, [NVDEV_ENGINE_PPP] = NV_DEVICE_V0_DISABLE_PPP, - [NVDEV_ENGINE_COPY0] = NV_DEVICE_V0_DISABLE_COPY0, - [NVDEV_ENGINE_COPY1] = NV_DEVICE_V0_DISABLE_COPY1, - [NVDEV_ENGINE_COPY2] = NV_DEVICE_V0_DISABLE_COPY1, + [NVDEV_ENGINE_CE0] = NV_DEVICE_V0_DISABLE_CE0, + [NVDEV_ENGINE_CE1] = NV_DEVICE_V0_DISABLE_CE1, + [NVDEV_ENGINE_CE2] = NV_DEVICE_V0_DISABLE_CE2, [NVDEV_ENGINE_VIC] = NV_DEVICE_V0_DISABLE_VIC, [NVDEV_ENGINE_VENC] = NV_DEVICE_V0_DISABLE_VENC, [NVDEV_ENGINE_DISP] = NV_DEVICE_V0_DISABLE_DISP, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index 391369a..c9c18dc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -48,7 +48,7 @@ #include #include #include -#include +#include #include #include #include @@ -88,11 +88,11 @@ gm100_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm107_graph_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; #if 0 - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; #endif - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; #if 0 device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; @@ -134,9 +134,9 @@ gm100_identify(struct nouveau_device *device) #endif device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass; #if 0 - device->oclass[NVDEV_ENGINE_COPY0 ] = &gm204_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &gm204_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &gm204_copy2_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index 2fb06eb..cb97802 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -52,7 +52,7 @@ #include #include #include -#include +#include #include #include @@ -374,7 +374,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; break; @@ -404,7 +404,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; break; @@ -434,7 +434,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; break; @@ -464,7 +464,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c index 0e1be5e..39bf7d1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c @@ -51,7 +51,7 @@ #include #include #include -#include +#include #include #include @@ -87,8 +87,8 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; break; @@ -120,8 +120,8 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; break; @@ -153,7 +153,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; break; @@ -185,8 +185,8 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; break; @@ -218,7 +218,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; break; @@ -250,7 +250,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; break; @@ -282,8 +282,8 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; break; @@ -315,7 +315,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; break; @@ -345,7 +345,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c index 1460a16..1f6d515 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c @@ -48,7 +48,7 @@ #include #include #include -#include +#include #include #include #include @@ -85,9 +85,9 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -119,9 +119,9 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -153,9 +153,9 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -178,7 +178,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk20a_graph_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass; @@ -209,9 +209,9 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -243,9 +243,9 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk110b_graph_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -277,9 +277,9 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -310,9 +310,9 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c index 3928439..4a3638e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c @@ -64,7 +64,7 @@ nv84_fifo_context_attach(struct nouveau_object *parent, case NVDEV_ENGINE_MSVLD : addr = 0x0080; break; case NVDEV_ENGINE_CIPHER: case NVDEV_ENGINE_SEC : addr = 0x00a0; break; - case NVDEV_ENGINE_COPY0 : addr = 0x00c0; break; + case NVDEV_ENGINE_CE0 : addr = 0x00c0; break; default: return -EINVAL; } @@ -102,7 +102,7 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend, case NVDEV_ENGINE_MSVLD : engn = 5; addr = 0x0080; break; case NVDEV_ENGINE_CIPHER: case NVDEV_ENGINE_SEC : engn = 4; addr = 0x00a0; break; - case NVDEV_ENGINE_COPY0 : engn = 2; addr = 0x00c0; break; + case NVDEV_ENGINE_CE0 : engn = 2; addr = 0x00c0; break; default: return -EINVAL; } @@ -147,7 +147,7 @@ nv84_fifo_object_attach(struct nouveau_object *parent, case NVDEV_ENGINE_MPEG : case NVDEV_ENGINE_PPP : context |= 0x00200000; break; case NVDEV_ENGINE_ME : - case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break; + case NVDEV_ENGINE_CE0 : context |= 0x00300000; break; case NVDEV_ENGINE_VP : context |= 0x00400000; break; case NVDEV_ENGINE_CIPHER: case NVDEV_ENGINE_SEC : @@ -196,7 +196,7 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent, (1ULL << NVDEV_ENGINE_BSP) | (1ULL << NVDEV_ENGINE_MSVLD) | (1ULL << NVDEV_ENGINE_PPP) | - (1ULL << NVDEV_ENGINE_COPY0) | + (1ULL << NVDEV_ENGINE_CE0) | (1ULL << NVDEV_ENGINE_VIC), &chan); *pobject = nv_object(chan); if (ret) @@ -271,7 +271,7 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent, (1ULL << NVDEV_ENGINE_BSP) | (1ULL << NVDEV_ENGINE_MSVLD) | (1ULL << NVDEV_ENGINE_PPP) | - (1ULL << NVDEV_ENGINE_COPY0) | + (1ULL << NVDEV_ENGINE_CE0) | (1ULL << NVDEV_ENGINE_VIC), &chan); *pobject = nv_object(chan); if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c index 2af40b2..1511e38 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c @@ -122,8 +122,8 @@ nvc0_fifo_context_attach(struct nouveau_object *parent, switch (nv_engidx(object->engine)) { case NVDEV_ENGINE_SW : return 0; case NVDEV_ENGINE_GR : addr = 0x0210; break; - case NVDEV_ENGINE_COPY0: addr = 0x0230; break; - case NVDEV_ENGINE_COPY1: addr = 0x0240; break; + case NVDEV_ENGINE_CE0 : addr = 0x0230; break; + case NVDEV_ENGINE_CE1 : addr = 0x0240; break; case NVDEV_ENGINE_MSVLD: addr = 0x0270; break; case NVDEV_ENGINE_VP : addr = 0x0250; break; case NVDEV_ENGINE_PPP : addr = 0x0260; break; @@ -159,8 +159,8 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend, switch (nv_engidx(object->engine)) { case NVDEV_ENGINE_SW : return 0; case NVDEV_ENGINE_GR : addr = 0x0210; break; - case NVDEV_ENGINE_COPY0: addr = 0x0230; break; - case NVDEV_ENGINE_COPY1: addr = 0x0240; break; + case NVDEV_ENGINE_CE0 : addr = 0x0230; break; + case NVDEV_ENGINE_CE1 : addr = 0x0240; break; case NVDEV_ENGINE_MSVLD: addr = 0x0270; break; case NVDEV_ENGINE_VP : addr = 0x0250; break; case NVDEV_ENGINE_PPP : addr = 0x0260; break; @@ -212,8 +212,8 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent, args->v0.pushbuf, (1ULL << NVDEV_ENGINE_SW) | (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_COPY0) | - (1ULL << NVDEV_ENGINE_COPY1) | + (1ULL << NVDEV_ENGINE_CE0) | + (1ULL << NVDEV_ENGINE_CE1) | (1ULL << NVDEV_ENGINE_MSVLD) | (1ULL << NVDEV_ENGINE_VP) | (1ULL << NVDEV_ENGINE_PPP), &chan); @@ -385,8 +385,8 @@ nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn) case NVDEV_ENGINE_MSVLD: engn = 1; break; case NVDEV_ENGINE_PPP : engn = 2; break; case NVDEV_ENGINE_VP : engn = 3; break; - case NVDEV_ENGINE_COPY0: engn = 4; break; - case NVDEV_ENGINE_COPY1: engn = 5; break; + case NVDEV_ENGINE_CE0 : engn = 4; break; + case NVDEV_ENGINE_CE1 : engn = 5; break; default: return -1; } @@ -402,8 +402,8 @@ nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn) case 1: engn = NVDEV_ENGINE_MSVLD; break; case 2: engn = NVDEV_ENGINE_PPP; break; case 3: engn = NVDEV_ENGINE_VP; break; - case 4: engn = NVDEV_ENGINE_COPY0; break; - case 5: engn = NVDEV_ENGINE_COPY1; break; + case 4: engn = NVDEV_ENGINE_CE0; break; + case 5: engn = NVDEV_ENGINE_CE1; break; default: return NULL; } @@ -552,8 +552,8 @@ nvc0_fifo_fault_engine[] = { { 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP }, { 0x13, "PCOUNTER" }, { 0x14, "PVP", NULL, NVDEV_ENGINE_VP }, - { 0x15, "PCOPY0", NULL, NVDEV_ENGINE_COPY0 }, - { 0x16, "PCOPY1", NULL, NVDEV_ENGINE_COPY1 }, + { 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 }, + { 0x16, "PCE1", NULL, NVDEV_ENGINE_CE1 }, { 0x17, "PDAEMON" }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c index b415b30..324008e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c @@ -47,12 +47,12 @@ static const struct { u64 mask; } fifo_engine[] = { _(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_COPY2)), + (1ULL << NVDEV_ENGINE_CE2)), _(NVDEV_ENGINE_VP , 0), _(NVDEV_ENGINE_PPP , 0), _(NVDEV_ENGINE_MSVLD , 0), - _(NVDEV_ENGINE_COPY0 , 0), - _(NVDEV_ENGINE_COPY1 , 0), + _(NVDEV_ENGINE_CE0 , 0), + _(NVDEV_ENGINE_CE1 , 0), _(NVDEV_ENGINE_VENC , 0), }; #undef _ @@ -143,9 +143,9 @@ nve0_fifo_context_attach(struct nouveau_object *parent, switch (nv_engidx(object->engine)) { case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_COPY0: - case NVDEV_ENGINE_COPY1: - case NVDEV_ENGINE_COPY2: + case NVDEV_ENGINE_CE0: + case NVDEV_ENGINE_CE1: + case NVDEV_ENGINE_CE2: nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; return 0; case NVDEV_ENGINE_GR : addr = 0x0210; break; @@ -183,9 +183,9 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend, switch (nv_engidx(object->engine)) { case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_COPY0: - case NVDEV_ENGINE_COPY1: - case NVDEV_ENGINE_COPY2: addr = 0x0000; break; + case NVDEV_ENGINE_CE0 : + case NVDEV_ENGINE_CE1 : + case NVDEV_ENGINE_CE2 : addr = 0x0000; break; case NVDEV_ENGINE_GR : addr = 0x0210; break; case NVDEV_ENGINE_MSVLD: addr = 0x0270; break; case NVDEV_ENGINE_VP : addr = 0x0250; break; @@ -415,12 +415,12 @@ nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn) { switch (engn) { case NVDEV_ENGINE_GR : - case NVDEV_ENGINE_COPY2: engn = 0; break; + case NVDEV_ENGINE_CE2 : engn = 0; break; case NVDEV_ENGINE_MSVLD: engn = 1; break; case NVDEV_ENGINE_PPP : engn = 2; break; case NVDEV_ENGINE_VP : engn = 3; break; - case NVDEV_ENGINE_COPY0: engn = 4; break; - case NVDEV_ENGINE_COPY1: engn = 5; break; + case NVDEV_ENGINE_CE0 : engn = 4; break; + case NVDEV_ENGINE_CE1 : engn = 5; break; case NVDEV_ENGINE_VENC : engn = 6; break; default: return -1; @@ -623,11 +623,11 @@ nve0_fifo_fault_engine[] = { { 0x11, "MSPPP", NULL, NVDEV_ENGINE_PPP }, { 0x13, "PERF" }, { 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP }, - { 0x15, "CE0", NULL, NVDEV_ENGINE_COPY0 }, - { 0x16, "CE1", NULL, NVDEV_ENGINE_COPY1 }, + { 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 }, + { 0x16, "CE1", NULL, NVDEV_ENGINE_CE1 }, { 0x17, "PMU" }, { 0x19, "MSENC", NULL, NVDEV_ENGINE_VENC }, - { 0x1b, "CE2", NULL, NVDEV_ENGINE_COPY2 }, + { 0x1b, "CE2", NULL, NVDEV_ENGINE_CE2 }, {} }; @@ -678,7 +678,7 @@ nve0_fifo_fault_hubclient[] = { { 0x15, "SCC_NB" }, { 0x16, "SEC" }, { 0x17, "SSYNC" }, - { 0x18, "GR_COPY" }, + { 0x18, "GR_CE" }, { 0x19, "CE2" }, { 0x1a, "XV" }, { 0x1b, "MMU_NB" }, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c index 4ba43d6..04c04ef 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c @@ -33,9 +33,9 @@ gm107_devinit_disable(struct nouveau_devinit *devinit) u64 disable = 0ULL; if (r021c00 & 0x00000001) - disable |= (1ULL << NVDEV_ENGINE_COPY0); + disable |= (1ULL << NVDEV_ENGINE_CE0); if (r021c00 & 0x00000004) - disable |= (1ULL << NVDEV_ENGINE_COPY2); + disable |= (1ULL << NVDEV_ENGINE_CE2); if (r021c04 & 0x00000001) disable |= (1ULL << NVDEV_ENGINE_DISP); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c index f662a26..b116f80 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c @@ -76,7 +76,7 @@ nva3_devinit_disable(struct nouveau_devinit *devinit) if (!(r00154c & 0x00000020)) disable |= (1ULL << NVDEV_ENGINE_MSVLD); if (!(r00154c & 0x00000200)) - disable |= (1ULL << NVDEV_ENGINE_COPY0); + disable |= (1ULL << NVDEV_ENGINE_CE0); return disable; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c index 6f8ef89..140c300 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c @@ -44,7 +44,7 @@ nvaf_devinit_disable(struct nouveau_devinit *devinit) if (!(r00154c & 0x00000040)) disable |= (1ULL << NVDEV_ENGINE_VIC); if (!(r00154c & 0x00000200)) - disable |= (1ULL << NVDEV_ENGINE_COPY0); + disable |= (1ULL << NVDEV_ENGINE_CE0); return disable; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c index ac699a3..c7b2311 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c @@ -79,9 +79,9 @@ nvc0_devinit_disable(struct nouveau_devinit *devinit) if (r022500 & 0x00000008) disable |= (1ULL << NVDEV_ENGINE_VENC); if (r022500 & 0x00000100) - disable |= (1ULL << NVDEV_ENGINE_COPY0); + disable |= (1ULL << NVDEV_ENGINE_CE0); if (r022500 & 0x00000200) - disable |= (1ULL << NVDEV_ENGINE_COPY1); + disable |= (1ULL << NVDEV_ENGINE_CE1); return disable; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index 31c90db..be129c3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -127,7 +127,7 @@ static const struct nouveau_enum vm_engine[] = { { 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CIPHER }, { 0x0000000b, "PCOUNTER", NULL }, { 0x0000000c, "SEMAPHORE_BG", NULL }, - { 0x0000000d, "PCOPY", NULL, NVDEV_ENGINE_COPY0 }, + { 0x0000000d, "PCE0", NULL, NVDEV_ENGINE_CE0 }, { 0x0000000e, "PDAEMON", NULL }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c index 17ea7e7..60b250f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c @@ -38,7 +38,7 @@ nv98_mc_intr[] = { { 0x00100000, NVDEV_SUBDEV_TIMER }, { 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */ { 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */ - { 0x00400000, NVDEV_ENGINE_COPY0 }, /* NVA3- */ + { 0x00400000, NVDEV_ENGINE_CE0 }, /* NVA3- */ { 0x10000000, NVDEV_SUBDEV_BUS }, { 0x80000000, NVDEV_ENGINE_SW }, { 0x0042d101, NVDEV_SUBDEV_FB }, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c index 1e35215..5217a5a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c @@ -28,9 +28,9 @@ const struct nouveau_mc_intr nvc0_mc_intr[] = { { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work. */ { 0x00000001, NVDEV_ENGINE_PPP }, - { 0x00000020, NVDEV_ENGINE_COPY0 }, - { 0x00000040, NVDEV_ENGINE_COPY1 }, - { 0x00000080, NVDEV_ENGINE_COPY2 }, + { 0x00000020, NVDEV_ENGINE_CE0 }, + { 0x00000040, NVDEV_ENGINE_CE1 }, + { 0x00000080, NVDEV_ENGINE_CE2 }, { 0x00000100, NVDEV_ENGINE_FIFO }, { 0x00001000, NVDEV_ENGINE_GR }, { 0x00002000, NVDEV_SUBDEV_FB }, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c index 9a8cbfb..701b9c4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c @@ -180,7 +180,7 @@ nv50_vm_flush(struct nouveau_vm *vm) case NVDEV_ENGINE_MSVLD : vme = 0x09; break; case NVDEV_ENGINE_CIPHER: case NVDEV_ENGINE_SEC : vme = 0x0a; break; - case NVDEV_ENGINE_COPY0 : vme = 0x0d; break; + case NVDEV_ENGINE_CE0 : vme = 0x0d; break; default: continue; } -- cgit v0.10.2