From bbb4ce50f3169b08764f9965fd5b9655646d545a Mon Sep 17 00:00:00 2001 From: "Shimoda, Yoshihiro" Date: Fri, 6 Apr 2012 09:59:14 +0900 Subject: serial: sh-sci: modify sci_break_ctl() SCIF modules which have SCSPTR can output the break signal. Now that we have a way of determining port features/capabilities, add trivial break control via SCSPTR support. Tested on sh7757lcr. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Simon Horman Signed-off-by: Paul Mundt diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 3158e17..3e471fc 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -1564,10 +1564,32 @@ static void sci_enable_ms(struct uart_port *port) static void sci_break_ctl(struct uart_port *port, int break_state) { - /* - * Not supported by hardware. Most parts couple break and rx - * interrupts together, with break detection always enabled. - */ + struct sci_port *s = to_sci_port(port); + unsigned short scscr, scsptr; + + switch (s->cfg->regtype) { + case SCIx_SH4_SCIF_REGTYPE: + scsptr = serial_port_in(port, SCSPTR); + scscr = serial_port_in(port, SCSCR); + + if (break_state == -1) { + scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; + scscr &= ~SCSCR_TE; + } else { + scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; + scscr |= SCSCR_TE; + } + + serial_port_out(port, SCSPTR, scsptr); + serial_port_out(port, SCSCR, scscr); + break; + default: + /* + * Not supported by hardware. Most parts couple break and rx + * interrupts together, with break detection always enabled. + */ + break; + } } #ifdef CONFIG_SERIAL_SH_SCI_DMA diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h index 7877907..eb763ad 100644 --- a/include/linux/serial_sci.h +++ b/include/linux/serial_sci.h @@ -52,6 +52,8 @@ enum { /* SCSPTR, optional */ #define SCSPTR_RTSIO (1 << 7) #define SCSPTR_CTSIO (1 << 5) +#define SCSPTR_SPB2IO (1 << 1) +#define SCSPTR_SPB2DT (1 << 0) /* Offsets into the sci_port->irqs array */ enum { -- cgit v0.10.2 From 14f087d839d9bd3f90ad69d4b3fde7d236c156b1 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 10 Apr 2012 12:39:55 +0900 Subject: sh: kgdb: Fix up basic SMP support. kgdb needs a kgdb_roundup_cpus() definition in the architecture backend, so just copy over the MIPS version, which already does what we want. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/kgdb.c b/arch/sh/kernel/kgdb.c index b117781..9345888 100644 --- a/arch/sh/kernel/kgdb.c +++ b/arch/sh/kernel/kgdb.c @@ -264,6 +264,18 @@ BUILD_TRAP_HANDLER(singlestep) local_irq_restore(flags); } +static void kgdb_call_nmi_hook(void *ignored) +{ + kgdb_nmicallback(raw_smp_processor_id(), NULL); +} + +void kgdb_roundup_cpus(unsigned long flags) +{ + local_irq_enable(); + smp_call_function(kgdb_call_nmi_hook, NULL, 0); + local_irq_disable(); +} + static int __kgdb_notify(struct die_args *args, unsigned long cmd) { int ret; -- cgit v0.10.2 From fd03e81812a8fb6121773226a4e0c702926077ae Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 10 Apr 2012 13:42:56 +0900 Subject: sh: kgdb: Individual register get/set support. This updates sh following the generic kgdb changes adding support for individual register get/set for kgdb/kdb use. Signed-off-by: Paul Mundt diff --git a/arch/sh/include/asm/kgdb.h b/arch/sh/include/asm/kgdb.h index f361395..0048519 100644 --- a/arch/sh/include/asm/kgdb.h +++ b/arch/sh/include/asm/kgdb.h @@ -4,18 +4,6 @@ #include #include -/* Same as pt_regs but has vbr in place of syscall_nr */ -struct kgdb_regs { - unsigned long regs[16]; - unsigned long pc; - unsigned long pr; - unsigned long sr; - unsigned long gbr; - unsigned long mach; - unsigned long macl; - unsigned long vbr; -}; - enum regnames { GDB_R0, GDB_R1, GDB_R2, GDB_R3, GDB_R4, GDB_R5, GDB_R6, GDB_R7, GDB_R8, GDB_R9, GDB_R10, GDB_R11, GDB_R12, GDB_R13, GDB_R14, GDB_R15, @@ -23,7 +11,12 @@ enum regnames { GDB_PC, GDB_PR, GDB_SR, GDB_GBR, GDB_MACH, GDB_MACL, GDB_VBR, }; -#define NUMREGBYTES ((GDB_VBR + 1) * 4) +#define _GP_REGS 16 +#define _EXTRA_REGS 7 +#define GDB_SIZEOF_REG sizeof(u32) + +#define DBG_MAX_REG_NUM (_GP_REGS + _EXTRA_REGS) +#define NUMREGBYTES (DBG_MAX_REG_NUM * sizeof(GDB_SIZEOF_REG)) static inline void arch_kgdb_breakpoint(void) { diff --git a/arch/sh/kernel/kgdb.c b/arch/sh/kernel/kgdb.c index 9345888..d25b5ed 100644 --- a/arch/sh/kernel/kgdb.c +++ b/arch/sh/kernel/kgdb.c @@ -1,7 +1,7 @@ /* * SuperH KGDB support * - * Copyright (C) 2008 - 2009 Paul Mundt + * Copyright (C) 2008 - 2012 Paul Mundt * * Single stepping taken from the old stub by Henry Bell and Jeremy Siegel. * @@ -164,36 +164,60 @@ static void undo_single_step(struct pt_regs *linux_regs) stepped_opcode = 0; } -void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) -{ - int i; +struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = { + { "r0", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[0]) }, + { "r1", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[1]) }, + { "r2", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[2]) }, + { "r3", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[3]) }, + { "r4", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[4]) }, + { "r5", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[5]) }, + { "r6", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[6]) }, + { "r7", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[7]) }, + { "r8", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[8]) }, + { "r9", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[9]) }, + { "r10", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[10]) }, + { "r11", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[11]) }, + { "r12", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[12]) }, + { "r13", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[13]) }, + { "r14", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[14]) }, + { "r15", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[15]) }, + { "pc", GDB_SIZEOF_REG, offsetof(struct pt_regs, pc) }, + { "pr", GDB_SIZEOF_REG, offsetof(struct pt_regs, pr) }, + { "sr", GDB_SIZEOF_REG, offsetof(struct pt_regs, sr) }, + { "gbr", GDB_SIZEOF_REG, offsetof(struct pt_regs, gbr) }, + { "mach", GDB_SIZEOF_REG, offsetof(struct pt_regs, mach) }, + { "macl", GDB_SIZEOF_REG, offsetof(struct pt_regs, macl) }, + { "vbr", GDB_SIZEOF_REG, -1 }, +}; - for (i = 0; i < 16; i++) - gdb_regs[GDB_R0 + i] = regs->regs[i]; +int dbg_set_reg(int regno, void *mem, struct pt_regs *regs) +{ + if (regno < 0 || regno >= DBG_MAX_REG_NUM) + return -EINVAL; - gdb_regs[GDB_PC] = regs->pc; - gdb_regs[GDB_PR] = regs->pr; - gdb_regs[GDB_SR] = regs->sr; - gdb_regs[GDB_GBR] = regs->gbr; - gdb_regs[GDB_MACH] = regs->mach; - gdb_regs[GDB_MACL] = regs->macl; + if (dbg_reg_def[regno].offset != -1) + memcpy((void *)regs + dbg_reg_def[regno].offset, mem, + dbg_reg_def[regno].size); - __asm__ __volatile__ ("stc vbr, %0" : "=r" (gdb_regs[GDB_VBR])); + return 0; } -void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs) +char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs) { - int i; + if (regno >= DBG_MAX_REG_NUM || regno < 0) + return NULL; - for (i = 0; i < 16; i++) - regs->regs[GDB_R0 + i] = gdb_regs[GDB_R0 + i]; + if (dbg_reg_def[regno].size != -1) + memcpy(mem, (void *)regs + dbg_reg_def[regno].offset, + dbg_reg_def[regno].size); + + switch (regno) { + case GDB_VBR: + __asm__ __volatile__ ("stc vbr, %0" : "=r" (mem)); + break; + } - regs->pc = gdb_regs[GDB_PC]; - regs->pr = gdb_regs[GDB_PR]; - regs->sr = gdb_regs[GDB_SR]; - regs->gbr = gdb_regs[GDB_GBR]; - regs->mach = gdb_regs[GDB_MACH]; - regs->macl = gdb_regs[GDB_MACL]; + return dbg_reg_def[regno].name; } void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p) -- cgit v0.10.2 From 10c5e4e137dc97e54cabd62a6109988ff8670faa Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 10 Apr 2012 14:00:30 +0900 Subject: sh: kgdb: Fill out sleeping_thread_to_gdb_regs() state. Presently we're using a pretty dumbed-down implementation that copies over register state visible from the thread info, leaving the bulk of the switch_to state uncopied. Given that we're also depending on register bank toggling for switch_to optimization we ought to also explicitly zero out the GP regs that reside in an alternate bank in order to prevent handing back garbage. There are a few extra registers that we have state for in switch_to, so copy those over while we're at it. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/kgdb.c b/arch/sh/kernel/kgdb.c index d25b5ed..ba8e763 100644 --- a/arch/sh/kernel/kgdb.c +++ b/arch/sh/kernel/kgdb.c @@ -222,8 +222,31 @@ char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs) void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p) { + struct pt_regs *thread_regs = task_pt_regs(p); + int reg; + + /* Initialize to zero */ + for (reg = 0; reg < DBG_MAX_REG_NUM; reg++) + gdb_regs[reg] = 0; + + /* + * Copy out GP regs 8 to 14. + * + * switch_to() relies on SR.RB toggling, so regs 0->7 are banked + * and need privileged instructions to get to. The r15 value we + * fetch from the thread info directly. + */ + for (reg = GDB_R8; reg < GDB_R15; reg++) + gdb_regs[reg] = thread_regs->regs[reg]; + gdb_regs[GDB_R15] = p->thread.sp; gdb_regs[GDB_PC] = p->thread.pc; + + /* + * Additional registers we have context for + */ + gdb_regs[GDB_PR] = thread_regs->pr; + gdb_regs[GDB_GBR] = thread_regs->gbr; } int kgdb_arch_handle_exception(int e_vector, int signo, int err_code, -- cgit v0.10.2 From fd34ef9bc44b87d746b7178e9c4ba51163b46884 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 10 Apr 2012 14:22:39 +0900 Subject: sh: kgdb: Fix up NULL pointer deref by kgdb_nmicallback. kgdb_nmicallback expects valid register state, so just fetch the register state with get_irq_regs() as on other platforms. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/kgdb.c b/arch/sh/kernel/kgdb.c index ba8e763..38b3139 100644 --- a/arch/sh/kernel/kgdb.c +++ b/arch/sh/kernel/kgdb.c @@ -313,7 +313,7 @@ BUILD_TRAP_HANDLER(singlestep) static void kgdb_call_nmi_hook(void *ignored) { - kgdb_nmicallback(raw_smp_processor_id(), NULL); + kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs()); } void kgdb_roundup_cpus(unsigned long flags) -- cgit v0.10.2 From 21cb20d758254e68a369ba83c721f8ce083e6659 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 11 Apr 2012 10:48:24 +0900 Subject: sh: kgdb: Unset CACHE_FLUSH_IS_SAFE for SMP. Our SMP cache flush ops use CPU cross calls to deal with things like I-cache accesses not being broadcast in hardware, so ensure that the CACHE_FLUSH_IS_SAFE reflects this. Signed-off-by: Paul Mundt diff --git a/arch/sh/include/asm/kgdb.h b/arch/sh/include/asm/kgdb.h index 0048519..9e7d2d1 100644 --- a/arch/sh/include/asm/kgdb.h +++ b/arch/sh/include/asm/kgdb.h @@ -23,10 +23,15 @@ static inline void arch_kgdb_breakpoint(void) __asm__ __volatile__ ("trapa #0x3c\n"); } -#define BUFMAX 2048 - -#define CACHE_FLUSH_IS_SAFE 1 #define BREAK_INSTR_SIZE 2 +#define BUFMAX 2048 + +#ifdef CONFIG_SMP +# define CACHE_FLUSH_IS_SAFE 0 +#else +# define CACHE_FLUSH_IS_SAFE 1 +#endif + #define GDB_ADJUSTS_BREAK_OFFSET #endif /* __ASM_SH_KGDB_H */ -- cgit v0.10.2 From 4d6ddb08acc48368c5b7ac431f9d00db7227d2ed Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 11 Apr 2012 12:05:50 +0900 Subject: sh: clkfwk: Support variable size accesses for MSTP clocks. The bulk of the MSTP users require 32-bit access, but this isn't the case for some of the SH-2A parts, so add in some basic infrastructure to let the CPU define its required access size in preparation. Requested-by: Phil Edworthy Signed-off-by: Paul Mundt diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c index 91b6d52..6cbda48 100644 --- a/drivers/sh/clk/cpg.c +++ b/drivers/sh/clk/cpg.c @@ -2,6 +2,7 @@ * Helper routines for SuperH Clock Pulse Generator blocks (CPG). * * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2010 - 2012 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -13,26 +14,41 @@ #include #include -static int sh_clk_mstp32_enable(struct clk *clk) +static int sh_clk_mstp_enable(struct clk *clk) { - iowrite32(ioread32(clk->mapped_reg) & ~(1 << clk->enable_bit), - clk->mapped_reg); + if (clk->flags & CLK_ENABLE_REG_8BIT) + iowrite8(ioread8(clk->mapped_reg) & ~(1 << clk->enable_bit), + clk->mapped_reg); + else if (clk->flags & CLK_ENABLE_REG_16BIT) + iowrite16(ioread16(clk->mapped_reg) & ~(1 << clk->enable_bit), + clk->mapped_reg); + else + iowrite32(ioread32(clk->mapped_reg) & ~(1 << clk->enable_bit), + clk->mapped_reg); + return 0; } -static void sh_clk_mstp32_disable(struct clk *clk) +static void sh_clk_mstp_disable(struct clk *clk) { - iowrite32(ioread32(clk->mapped_reg) | (1 << clk->enable_bit), - clk->mapped_reg); + if (clk->flags & CLK_ENABLE_REG_8BIT) + iowrite8(ioread8(clk->mapped_reg) | (1 << clk->enable_bit), + clk->mapped_reg); + else if (clk->flags & CLK_ENABLE_REG_16BIT) + iowrite16(ioread16(clk->mapped_reg) | (1 << clk->enable_bit), + clk->mapped_reg); + else + iowrite32(ioread32(clk->mapped_reg) | (1 << clk->enable_bit), + clk->mapped_reg); } -static struct sh_clk_ops sh_clk_mstp32_clk_ops = { - .enable = sh_clk_mstp32_enable, - .disable = sh_clk_mstp32_disable, +static struct sh_clk_ops sh_clk_mstp_clk_ops = { + .enable = sh_clk_mstp_enable, + .disable = sh_clk_mstp_disable, .recalc = followparent_recalc, }; -int __init sh_clk_mstp32_register(struct clk *clks, int nr) +int __init sh_clk_mstp_register(struct clk *clks, int nr) { struct clk *clkp; int ret = 0; @@ -40,7 +56,7 @@ int __init sh_clk_mstp32_register(struct clk *clks, int nr) for (k = 0; !ret && (k < nr); k++) { clkp = clks + k; - clkp->ops = &sh_clk_mstp32_clk_ops; + clkp->ops = &sh_clk_mstp_clk_ops; ret |= clk_register(clkp); } diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h index 0a9d8f2..c513b73 100644 --- a/include/linux/sh_clk.h +++ b/include/linux/sh_clk.h @@ -59,7 +59,15 @@ struct clk { unsigned int nr_freqs; }; -#define CLK_ENABLE_ON_INIT (1 << 0) +#define CLK_ENABLE_ON_INIT BIT(0) + +#define CLK_ENABLE_REG_32BIT BIT(1) /* default access size */ +#define CLK_ENABLE_REG_16BIT BIT(2) +#define CLK_ENABLE_REG_8BIT BIT(3) + +#define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \ + CLK_ENABLE_REG_16BIT | \ + CLK_ENABLE_REG_8BIT) /* drivers/sh/clk.c */ unsigned long followparent_recalc(struct clk *); @@ -102,7 +110,7 @@ long clk_round_parent(struct clk *clk, unsigned long target, unsigned long *best_freq, unsigned long *parent_freq, unsigned int div_min, unsigned int div_max); -#define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \ +#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \ { \ .parent = _parent, \ .enable_reg = (void __iomem *)_enable_reg, \ @@ -110,7 +118,27 @@ long clk_round_parent(struct clk *clk, unsigned long target, .flags = _flags, \ } -int sh_clk_mstp32_register(struct clk *clks, int nr); +#define SH_CLK_MSTP32(_p, _r, _b, _f) \ + SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT) + +#define SH_CLK_MSTP16(_p, _r, _b, _f) \ + SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT) + +#define SH_CLK_MSTP8(_p, _r, _b, _f) \ + SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT) + +int sh_clk_mstp_register(struct clk *clks, int nr); + +/* + * MSTP registration never really cared about access size, despite the + * original enable/disable pairs assuming a 32-bit access. Clocks are + * responsible for defining their access sizes either directly or via the + * clock definition wrappers. + */ +static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr) +{ + return sh_clk_mstp_register(clks, nr); +} #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ { \ -- cgit v0.10.2 From 11fd982400a8779cb4b5f7cdc806008569ff545c Mon Sep 17 00:00:00 2001 From: Kautuk Consul Date: Sat, 31 Mar 2012 08:06:11 -0400 Subject: sh/mm/fault_32.c: Port OOM changes to do_page_fault Commit d065bd810b6deb67d4897a14bfe21f8eb526ba99 (mm: retry page fault when blocking on disk transfer) and commit 37b23e0525d393d48a7d59f870b3bc061a30ccdb (x86,mm: make pagefault killable) The above commits introduced changes into the x86 pagefault handler for making the page fault handler retryable as well as killable. These changes reduce the mmap_sem hold time, which is crucial during OOM killer invocation. Port these changes to the 32-bit SH platform. Signed-off-by: Kautuk Consul Signed-off-by: Paul Mundt diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c index 324eef9..98e88a6 100644 --- a/arch/sh/mm/fault_32.c +++ b/arch/sh/mm/fault_32.c @@ -129,6 +129,8 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, int si_code; int fault; siginfo_t info; + unsigned int flags = (FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE | + (writeaccess ? FAULT_FLAG_WRITE : 0)); tsk = current; mm = tsk->mm; @@ -169,6 +171,7 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, if (in_atomic() || !mm) goto no_context; +retry: down_read(&mm->mmap_sem); vma = find_vma(mm, address); @@ -200,7 +203,11 @@ good_area: * make sure we exit gracefully rather than endlessly redo * the fault. */ - fault = handle_mm_fault(mm, vma, address, writeaccess ? FAULT_FLAG_WRITE : 0); + fault = handle_mm_fault(mm, vma, address, flags); + + if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) + return; + if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; @@ -208,14 +215,27 @@ good_area: goto do_sigbus; BUG(); } - if (fault & VM_FAULT_MAJOR) { - tsk->maj_flt++; - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, - regs, address); - } else { - tsk->min_flt++; - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, - regs, address); + + if (flags & FAULT_FLAG_ALLOW_RETRY) { + if (fault & VM_FAULT_MAJOR) { + tsk->maj_flt++; + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, + regs, address); + } else { + tsk->min_flt++; + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, + regs, address); + } + if (fault & VM_FAULT_RETRY) { + flags &= ~FAULT_FLAG_ALLOW_RETRY; + + /* + * No need to up_read(&mm->mmap_sem) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ + goto retry; + } } up_read(&mm->mmap_sem); -- cgit v0.10.2 From a1e2030122d4c2605089e60dce28d2fcf9c3ef98 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 11 Apr 2012 12:44:50 +0900 Subject: sh64: Port OOM changes to do_page_fault Reflect the sh32 OOM changes for the sh64 page fault handler, too. Signed-off-by: Paul Mundt diff --git a/arch/sh/mm/tlbflush_64.c b/arch/sh/mm/tlbflush_64.c index 11c5a18..70b3c27 100644 --- a/arch/sh/mm/tlbflush_64.c +++ b/arch/sh/mm/tlbflush_64.c @@ -3,7 +3,7 @@ * * Copyright (C) 2000, 2001 Paolo Alberelli * Copyright (C) 2003 Richard Curnow (/proc/tlb, bug fixes) - * Copyright (C) 2003 - 2009 Paul Mundt + * Copyright (C) 2003 - 2012 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -95,6 +95,8 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long writeaccess, struct mm_struct *mm; struct vm_area_struct * vma; const struct exception_table_entry *fixup; + unsigned int flags = (FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE | + (writeaccess ? FAULT_FLAG_WRITE : 0)); pte_t *pte; int fault; @@ -124,6 +126,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long writeaccess, if (in_atomic() || !mm) goto no_context; +retry: /* TLB misses upon some cache flushes get done under cli() */ down_read(&mm->mmap_sem); @@ -188,7 +191,11 @@ good_area: * make sure we exit gracefully rather than endlessly redo * the fault. */ - fault = handle_mm_fault(mm, vma, address, writeaccess ? FAULT_FLAG_WRITE : 0); + fault = handle_mm_fault(mm, vma, address, flags); + + if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) + return; + if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; @@ -197,14 +204,27 @@ good_area: BUG(); } - if (fault & VM_FAULT_MAJOR) { - tsk->maj_flt++; - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, - regs, address); - } else { - tsk->min_flt++; - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, - regs, address); + if (flags & FAULT_FLAG_ALLOW_RETRY) { + if (fault & VM_FAULT_MAJOR) { + tsk->maj_flt++; + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, + regs, address); + } else { + tsk->min_flt++; + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, + regs, address); + } + + if (fault & VM_FAULT_RETRY) { + flags &= ~FAULT_FLAG_ALLOW_RETRY; + + /* + * No need to up_read(&mm->mmap_sem) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ + goto retry; + } } /* If we get here, the page fault has been handled. Do the TLB refill -- cgit v0.10.2 From ba2a3cdf76c32861c95e9a226b75dbecaec99469 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 11 Apr 2012 12:53:06 +0900 Subject: sh64: Kill off dead page fault debug cruft. In the future we'll be unifying some of the 32/64 page fault path, so start to tidy up the _64 one by killing off some of the unused debug cruft. Signed-off-by: Paul Mundt diff --git a/arch/sh/mm/tlbflush_64.c b/arch/sh/mm/tlbflush_64.c index 70b3c27..605dc65 100644 --- a/arch/sh/mm/tlbflush_64.c +++ b/arch/sh/mm/tlbflush_64.c @@ -28,33 +28,6 @@ #include #include -extern void die(const char *,struct pt_regs *,long); - -#define PFLAG(val,flag) (( (val) & (flag) ) ? #flag : "" ) -#define PPROT(flag) PFLAG(pgprot_val(prot),flag) - -static inline void print_prots(pgprot_t prot) -{ - printk("prot is 0x%016llx\n",pgprot_val(prot)); - - printk("%s %s %s %s %s\n",PPROT(_PAGE_SHARED),PPROT(_PAGE_READ), - PPROT(_PAGE_EXECUTE),PPROT(_PAGE_WRITE),PPROT(_PAGE_USER)); -} - -static inline void print_vma(struct vm_area_struct *vma) -{ - printk("vma start 0x%08lx\n", vma->vm_start); - printk("vma end 0x%08lx\n", vma->vm_end); - - print_prots(vma->vm_page_prot); - printk("vm_flags 0x%08lx\n", vma->vm_flags); -} - -static inline void print_task(struct task_struct *tsk) -{ - printk("Task pid %d\n", task_pid_nr(tsk)); -} - static pte_t *lookup_pte(struct mm_struct *mm, unsigned long address) { pgd_t *dir; @@ -131,43 +104,15 @@ retry: down_read(&mm->mmap_sem); vma = find_vma(mm, address); - - if (!vma) { -#ifdef DEBUG_FAULT - print_task(tsk); - printk("%s:%d fault, address is 0x%08x PC %016Lx textaccess %d writeaccess %d\n", - __func__, __LINE__, - address,regs->pc,textaccess,writeaccess); - show_regs(regs); -#endif + if (!vma) goto bad_area; - } - if (vma->vm_start <= address) { + if (vma->vm_start <= address) goto good_area; - } - - if (!(vma->vm_flags & VM_GROWSDOWN)) { -#ifdef DEBUG_FAULT - print_task(tsk); - printk("%s:%d fault, address is 0x%08x PC %016Lx textaccess %d writeaccess %d\n", - __func__, __LINE__, - address,regs->pc,textaccess,writeaccess); - show_regs(regs); - - print_vma(vma); -#endif + if (!(vma->vm_flags & VM_GROWSDOWN)) goto bad_area; - } - if (expand_stack(vma, address)) { -#ifdef DEBUG_FAULT - print_task(tsk); - printk("%s:%d fault, address is 0x%08x PC %016Lx textaccess %d writeaccess %d\n", - __func__, __LINE__, - address,regs->pc,textaccess,writeaccess); - show_regs(regs); -#endif + if (expand_stack(vma, address)) goto bad_area; - } + /* * Ok, we have a good vm_area for this memory access, so * we can handle it.. @@ -251,9 +196,6 @@ no_pte: * Fix it, but check if it's kernel or user first.. */ bad_area: -#ifdef DEBUG_FAULT - printk("fault:bad area\n"); -#endif up_read(&mm->mmap_sem); if (user_mode(regs)) { @@ -266,9 +208,6 @@ bad_area: printk("user mode bad_area address=%08lx pid=%d (%s) pc=%08lx\n", address, task_pid_nr(current), current->comm, (unsigned long) regs->pc); -#if 0 - show_regs(regs); -#endif } if (is_global_init(tsk)) { panic("INIT had user mode bad_area\n"); @@ -283,9 +222,6 @@ bad_area: } no_context: -#ifdef DEBUG_FAULT - printk("fault:No context\n"); -#endif /* Are we prepared to handle this kernel fault? */ fixup = search_exception_tables(regs->pc); if (fixup) { -- cgit v0.10.2 From ee565105ccedc63728a83f4deb1c10dc57091959 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 11 Apr 2012 12:58:33 +0900 Subject: MAINTAINERS: Update git URL for SH. Signed-off-by: Paul Mundt diff --git a/MAINTAINERS b/MAINTAINERS index 2dcfca8..0b568b6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6545,7 +6545,7 @@ M: Paul Mundt L: linux-sh@vger.kernel.org W: http://www.linux-sh.org Q: http://patchwork.kernel.org/project/linux-sh/list/ -T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6.git sh-latest +T: git git://github.com/pmundt/linux-sh.git sh-latest S: Supported F: Documentation/sh/ F: arch/sh/ -- cgit v0.10.2 From a4e02f6d83d4fcdb13bcaba76878fc5ea0da9911 Mon Sep 17 00:00:00 2001 From: "Shimoda, Yoshihiro" Date: Thu, 12 Apr 2012 19:19:21 +0900 Subject: serial: sh-sci: Update break_ctl handling for all SCSPTR-capable regtypes. This updates the earlier break_ctl support regardless of regtype so long as the requisite SCSPTR exists. This is the same approach used by sci_init_pins() for providing a generic solution now that we're able to detect register capabilities on a per-port basis. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Paul Mundt diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 3e471fc..be31d85 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -1565,31 +1565,31 @@ static void sci_enable_ms(struct uart_port *port) static void sci_break_ctl(struct uart_port *port, int break_state) { struct sci_port *s = to_sci_port(port); + struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; unsigned short scscr, scsptr; - switch (s->cfg->regtype) { - case SCIx_SH4_SCIF_REGTYPE: - scsptr = serial_port_in(port, SCSPTR); - scscr = serial_port_in(port, SCSCR); - - if (break_state == -1) { - scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; - scscr &= ~SCSCR_TE; - } else { - scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; - scscr |= SCSCR_TE; - } - - serial_port_out(port, SCSPTR, scsptr); - serial_port_out(port, SCSCR, scscr); - break; - default: + /* check wheter the port has SCSPTR */ + if (!reg->size) { /* * Not supported by hardware. Most parts couple break and rx * interrupts together, with break detection always enabled. */ - break; + return; } + + scsptr = serial_port_in(port, SCSPTR); + scscr = serial_port_in(port, SCSCR); + + if (break_state == -1) { + scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; + scscr &= ~SCSCR_TE; + } else { + scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; + scscr |= SCSCR_TE; + } + + serial_port_out(port, SCSPTR, scsptr); + serial_port_out(port, SCSCR, scscr); } #ifdef CONFIG_SERIAL_SH_SCI_DMA -- cgit v0.10.2 From 104fa61a7dd83197160d5cafedc0e94ad9cd7fcc Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 12 Apr 2012 19:50:40 +0900 Subject: sh: clkfwk: Support variable size accesses for div4/div6 clocks. This follows the MSTP clock change and implements variable access size support for the rest of the CPG clocks, too. Upcoming SH-2A support has need of this for 16-bit div4 clocks, while others will follow. Signed-off-by: Paul Mundt diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c index 6cbda48..f0d015d 100644 --- a/drivers/sh/clk/cpg.c +++ b/drivers/sh/clk/cpg.c @@ -14,32 +14,35 @@ #include #include -static int sh_clk_mstp_enable(struct clk *clk) +static unsigned int sh_clk_read(struct clk *clk) { if (clk->flags & CLK_ENABLE_REG_8BIT) - iowrite8(ioread8(clk->mapped_reg) & ~(1 << clk->enable_bit), - clk->mapped_reg); + return ioread8(clk->mapped_reg); else if (clk->flags & CLK_ENABLE_REG_16BIT) - iowrite16(ioread16(clk->mapped_reg) & ~(1 << clk->enable_bit), - clk->mapped_reg); - else - iowrite32(ioread32(clk->mapped_reg) & ~(1 << clk->enable_bit), - clk->mapped_reg); + return ioread16(clk->mapped_reg); - return 0; + return ioread32(clk->mapped_reg); } -static void sh_clk_mstp_disable(struct clk *clk) +static void sh_clk_write(int value, struct clk *clk) { if (clk->flags & CLK_ENABLE_REG_8BIT) - iowrite8(ioread8(clk->mapped_reg) | (1 << clk->enable_bit), - clk->mapped_reg); + iowrite8(value, clk->mapped_reg); else if (clk->flags & CLK_ENABLE_REG_16BIT) - iowrite16(ioread16(clk->mapped_reg) | (1 << clk->enable_bit), - clk->mapped_reg); + iowrite16(value, clk->mapped_reg); else - iowrite32(ioread32(clk->mapped_reg) | (1 << clk->enable_bit), - clk->mapped_reg); + iowrite32(value, clk->mapped_reg); +} + +static int sh_clk_mstp_enable(struct clk *clk) +{ + sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); + return 0; +} + +static void sh_clk_mstp_disable(struct clk *clk) +{ + sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk); } static struct sh_clk_ops sh_clk_mstp_clk_ops = { @@ -88,7 +91,7 @@ static unsigned long sh_clk_div6_recalc(struct clk *clk) clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, table, NULL); - idx = ioread32(clk->mapped_reg) & 0x003f; + idx = sh_clk_read(clk) & 0x003f; return clk->freq_table[idx].frequency; } @@ -114,10 +117,10 @@ static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent) if (ret < 0) return ret; - value = ioread32(clk->mapped_reg) & + value = sh_clk_read(clk) & ~(((1 << clk->src_width) - 1) << clk->src_shift); - iowrite32(value | (i << clk->src_shift), clk->mapped_reg); + sh_clk_write(value | (i << clk->src_shift), clk); /* Rebuild the frequency table */ clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, @@ -135,10 +138,10 @@ static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate) if (idx < 0) return idx; - value = ioread32(clk->mapped_reg); + value = sh_clk_read(clk); value &= ~0x3f; value |= idx; - iowrite32(value, clk->mapped_reg); + sh_clk_write(value, clk); return 0; } @@ -149,9 +152,9 @@ static int sh_clk_div6_enable(struct clk *clk) ret = sh_clk_div6_set_rate(clk, clk->rate); if (ret == 0) { - value = ioread32(clk->mapped_reg); + value = sh_clk_read(clk); value &= ~0x100; /* clear stop bit to enable clock */ - iowrite32(value, clk->mapped_reg); + sh_clk_write(value, clk); } return ret; } @@ -160,10 +163,10 @@ static void sh_clk_div6_disable(struct clk *clk) { unsigned long value; - value = ioread32(clk->mapped_reg); + value = sh_clk_read(clk); value |= 0x100; /* stop clock */ value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */ - iowrite32(value, clk->mapped_reg); + sh_clk_write(value, clk); } static struct sh_clk_ops sh_clk_div6_clk_ops = { @@ -198,7 +201,7 @@ static int __init sh_clk_init_parent(struct clk *clk) return -EINVAL; } - val = (ioread32(clk->mapped_reg) >> clk->src_shift); + val = (sh_clk_read(clk) >> clk->src_shift); val &= (1 << clk->src_width) - 1; if (val >= clk->parent_num) { @@ -268,7 +271,7 @@ static unsigned long sh_clk_div4_recalc(struct clk *clk) clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, table, &clk->arch_flags); - idx = (ioread32(clk->mapped_reg) >> clk->enable_bit) & 0x000f; + idx = (sh_clk_read(clk) >> clk->enable_bit) & 0x000f; return clk->freq_table[idx].frequency; } @@ -286,15 +289,15 @@ static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent) */ if (parent->flags & CLK_ENABLE_ON_INIT) - value = ioread32(clk->mapped_reg) & ~(1 << 7); + value = sh_clk_read(clk) & ~(1 << 7); else - value = ioread32(clk->mapped_reg) | (1 << 7); + value = sh_clk_read(clk) | (1 << 7); ret = clk_reparent(clk, parent); if (ret < 0) return ret; - iowrite32(value, clk->mapped_reg); + sh_clk_write(value, clk); /* Rebiuld the frequency table */ clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, @@ -311,10 +314,10 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate) if (idx < 0) return idx; - value = ioread32(clk->mapped_reg); + value = sh_clk_read(clk); value &= ~(0xf << clk->enable_bit); value |= (idx << clk->enable_bit); - iowrite32(value, clk->mapped_reg); + sh_clk_write(value, clk); if (d4t->kick) d4t->kick(clk); @@ -324,13 +327,13 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate) static int sh_clk_div4_enable(struct clk *clk) { - iowrite32(ioread32(clk->mapped_reg) & ~(1 << 8), clk->mapped_reg); + sh_clk_write(sh_clk_read(clk) & ~(1 << 8), clk); return 0; } static void sh_clk_div4_disable(struct clk *clk) { - iowrite32(ioread32(clk->mapped_reg) | (1 << 8), clk->mapped_reg); + sh_clk_write(sh_clk_read(clk) | (1 << 8), clk); } static struct sh_clk_ops sh_clk_div4_clk_ops = { -- cgit v0.10.2 From eb0cdbe6b8cde26318666f86f8f5fb08d2336ce5 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 13 Apr 2012 12:14:00 +0900 Subject: sh: sh4a: Change the specification method of IRQ to SCIx_IRQ_MUXED Some SCIF devices specify the same IRQ. We can use SCIx_IRQ_MUXED for this. And change use to evt2irq(), without specifying the value of IRQ directly. This is correction to the SH4A series. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c index 1b88483..476f474 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c @@ -22,7 +22,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)), }; static struct platform_device scif0_device = { @@ -39,7 +39,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 81, 81, 81, 81 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xC20)), }; static struct platform_device scif1_device = { @@ -56,7 +56,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 82, 82, 82, 82 }, + .irq = SCIx_IRQ_MUXED(evt2irq(0xC40)), }; static struct platform_device scif2_device = { @@ -73,7 +73,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 83, 83, 83, 83 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xC60)), }; static struct platform_device scif3_device = { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c index 8777386..20f9e36 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c @@ -25,7 +25,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)), }; static struct platform_device scif0_device = { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index 8420d4b..34b2ee5 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c @@ -182,7 +182,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)), .ops = &sh7722_sci_port_ops, .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; @@ -201,7 +201,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 81, 81, 81, 81 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xC20)), .ops = &sh7722_sci_port_ops, .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; @@ -220,7 +220,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 82, 82, 82, 82 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xC40)), .ops = &sh7722_sci_port_ops, .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index a188c9e..3c1da7e 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c @@ -28,7 +28,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; @@ -47,7 +47,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 81, 81, 81, 81 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xC20)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; @@ -66,7 +66,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 82, 82, 82, 82 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xC40)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index 4c671cf..20623ba 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c @@ -295,7 +295,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; @@ -314,7 +314,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 81, 81, 81, 81 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xC20)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; @@ -333,7 +333,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 82, 82, 82, 82 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xC40)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; @@ -352,7 +352,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_3, .type = PORT_SCIFA, - .irqs = { 56, 56, 56, 56 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), }; static struct platform_device scif3_device = { @@ -370,7 +370,7 @@ static struct plat_sci_port scif4_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_3, .type = PORT_SCIFA, - .irqs = { 88, 88, 88, 88 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xD00)), }; static struct platform_device scif4_device = { @@ -388,7 +388,7 @@ static struct plat_sci_port scif5_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_3, .type = PORT_SCIFA, - .irqs = { 109, 109, 109, 109 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xFA0)), }; static struct platform_device scif5_device = { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c index c8836cf..fe45e4c 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c @@ -28,7 +28,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 40, 40, 40, 40 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), }; static struct platform_device scif2_device = { @@ -45,7 +45,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 76, 76, 76, 76 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xB80)), }; static struct platform_device scif3_device = { @@ -62,7 +62,7 @@ static struct plat_sci_port scif4_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 104, 104, 104, 104 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xF00)), }; static struct platform_device scif4_device = { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c index 0011351..197e4c9 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c @@ -22,7 +22,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 40, 40, 40, 40 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -40,7 +40,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 76, 76, 76, 76 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xB80)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -58,7 +58,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 104, 104, 104, 104 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xF00)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c index 2c6aa22..46ea870 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c @@ -20,7 +20,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 61, 61, 61, 61 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x9A0)), }; static struct platform_device scif0_device = { @@ -37,7 +37,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 62, 62, 62, 62 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x9C0)), }; static struct platform_device scif1_device = { @@ -54,7 +54,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 63, 63, 63, 63 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x9E0)), }; static struct platform_device scif2_device = { @@ -71,7 +71,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 64, 64, 64, 64 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xA00)), }; static struct platform_device scif3_device = { @@ -88,7 +88,7 @@ static struct plat_sci_port scif4_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 65, 65, 65, 65 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xA20)), }; static struct platform_device scif4_device = { @@ -105,7 +105,7 @@ static struct plat_sci_port scif5_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 66, 66, 66, 66 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xA40)), }; static struct platform_device scif5_device = { @@ -122,7 +122,7 @@ static struct plat_sci_port scif6_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 67, 67, 67, 67 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xA60)), }; static struct platform_device scif6_device = { @@ -139,7 +139,7 @@ static struct plat_sci_port scif7_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 68, 68, 68, 68 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xA80)), }; static struct platform_device scif7_device = { @@ -156,7 +156,7 @@ static struct plat_sci_port scif8_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 69, 69, 69, 69 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xAA0)), }; static struct platform_device scif8_device = { @@ -173,7 +173,7 @@ static struct plat_sci_port scif9_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 70, 70, 70, 70 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xAC0)), }; static struct platform_device scif9_device = { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c index 81588ef..304339f 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c @@ -24,7 +24,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 40, 40, 40, 40 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -42,7 +42,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 44, 44, 44, 44 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -60,7 +60,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 60, 60, 60, 60 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x980)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -78,7 +78,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 61, 61, 61, 61 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x9A0)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -96,7 +96,7 @@ static struct plat_sci_port scif4_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 62, 62, 62, 62 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x9C0)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -114,7 +114,7 @@ static struct plat_sci_port scif5_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 63, 63, 63, 63 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x9E0)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c index 599022d..9befe2d 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c @@ -53,7 +53,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 44, 44, 44, 44 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -71,7 +71,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 50, 50, 50, 50 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x840)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -89,7 +89,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 51, 51, 51, 51 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x860)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -107,7 +107,7 @@ static struct plat_sci_port scif4_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 52, 52, 52, 52 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -125,7 +125,7 @@ static struct plat_sci_port scif5_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 53, 53, 53, 53 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x8A0)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; -- cgit v0.10.2 From 51edfb3375d276ba81ba26220c699a524be71f59 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 13 Apr 2012 12:14:01 +0900 Subject: sh: sh4: Change the specification method of IRQ to SCIx_IRQ_MUXED Some SCIF devices specify the same IRQ. We can use SCIx_IRQ_MUXED for this. And change use to evt2irq(), without specifying the value of IRQ directly. This is correction to the SH4 series. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c index 98cc0c7..56b3bdc 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c @@ -43,7 +43,7 @@ static struct plat_sci_port sci_platform_data = { .scscr = SCSCR_TE | SCSCR_RE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCI, - .irqs = { 23, 23, 23, 0 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xE40)), .regshift = 2, }; @@ -61,7 +61,7 @@ static struct plat_sci_port scif_platform_data = { .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 40, 40, 40, 40 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), }; static struct platform_device scif_device = { -- cgit v0.10.2 From 545f3bcf32b6d43d9ac89998e9e72fcdf7accca3 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 13 Apr 2012 12:14:02 +0900 Subject: sh: sh3: Change the specification method of IRQ to SCIx_IRQ_MUXED Some SCIF devices specify the same IRQ. We can use SCIx_IRQ_MUXED for this. And change use to evt2irq(), without specifying the value of IRQ directly. This is correction to the SH3 series. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c index 2309618..97416a5 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c @@ -75,7 +75,7 @@ static struct plat_sci_port scif0_platform_data = { SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIF, - .irqs = { 56, 56, 56 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), .ops = &sh770x_sci_port_ops, .regtype = SCIx_SH7705_SCIF_REGTYPE, }; @@ -94,7 +94,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIF, - .irqs = { 52, 52, 52 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), .ops = &sh770x_sci_port_ops, .regtype = SCIx_SH7705_SCIF_REGTYPE, }; diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c index 3f3d5fe..50f95a3 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c @@ -114,7 +114,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_TE | SCSCR_RE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCI, - .irqs = { 23, 23, 23, 0 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x4E0)), .ops = &sh770x_sci_port_ops, .regshift = 1, }; @@ -135,7 +135,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_TE | SCSCR_RE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 56, 56, 56, 56 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), .ops = &sh770x_sci_port_ops, .regtype = SCIx_SH3_SCIF_REGTYPE, }; @@ -157,7 +157,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_TE | SCSCR_RE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_IRDA, - .irqs = { 52, 52, 52, 52 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), .ops = &sh770x_sci_port_ops, .regshift = 1, }; diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c index 78f6b01..7ef2487 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c @@ -103,7 +103,7 @@ static struct plat_sci_port scif0_platform_data = { SCSCR_CKE1 | SCSCR_CKE0, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 52, 52, 52, 52 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), }; static struct platform_device scif0_device = { @@ -121,7 +121,7 @@ static struct plat_sci_port scif1_platform_data = { SCSCR_CKE1 | SCSCR_CKE0, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 56, 56, 56, 56 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), }; static struct platform_device scif1_device = { diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c index 9492034..b255748 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c @@ -55,7 +55,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)), .ops = &sh7720_sci_port_ops, .regtype = SCIx_SH7705_SCIF_REGTYPE, }; @@ -74,7 +74,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIF, - .irqs = { 81, 81, 81, 81 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xC20)), .ops = &sh7720_sci_port_ops, .regtype = SCIx_SH7705_SCIF_REGTYPE, }; -- cgit v0.10.2 From e00e7cb3b70e8aec5aa732b51394b841c7b4b571 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 13 Apr 2012 12:14:03 +0900 Subject: sh: sh2: Change the specification method of IRQ to SCIx_IRQ_MUXED Some SCIF devices specify the same IRQ. We can use SCIx_IRQ_MUXED for this. This is correction to the SH2/SH2A series. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c index 0f8befc..e0b740c 100644 --- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c +++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c @@ -65,7 +65,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 88, 88, 88, 88 }, + .irqs = SCIx_IRQ_MUXED(88), }; static struct platform_device scif0_device = { @@ -82,7 +82,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 92, 92, 92, 92 }, + .irqs = SCIx_IRQ_MUXED(92), }; static struct platform_device scif1_device = { @@ -99,7 +99,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 96, 96, 96, 96 }, + .irqs = SCIx_IRQ_MUXED(96), }; static struct platform_device scif2_device = { diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c index 949bf2b..f7f1cf2 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c +++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c @@ -204,7 +204,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 220, 220, 220, 220 }, + .irqs = SCIx_IRQ_MUXED(220), }; static struct platform_device scif0_device = { diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c index 9df558d..7b84785 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c @@ -183,7 +183,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 180, 180, 180, 180 } + .irqs = SCIx_IRQ_MUXED(180), }; static struct platform_device scif0_device = { @@ -200,7 +200,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 184, 184, 184, 184 } + .irqs = SCIx_IRQ_MUXED(184), }; static struct platform_device scif1_device = { @@ -217,7 +217,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 188, 188, 188, 188 } + .irqs = SCIx_IRQ_MUXED(188), }; static struct platform_device scif2_device = { @@ -234,7 +234,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 192, 192, 192, 192 } + .irqs = SCIx_IRQ_MUXED(192), }; static struct platform_device scif3_device = { @@ -251,7 +251,7 @@ static struct plat_sci_port scif4_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 196, 196, 196, 196 } + .irqs = SCIx_IRQ_MUXED(196), }; static struct platform_device scif4_device = { @@ -268,7 +268,7 @@ static struct plat_sci_port scif5_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 200, 200, 200, 200 } + .irqs = SCIx_IRQ_MUXED(200), }; static struct platform_device scif5_device = { @@ -285,7 +285,7 @@ static struct plat_sci_port scif6_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 204, 204, 204, 204 } + .irqs = SCIx_IRQ_MUXED(204), }; static struct platform_device scif6_device = { @@ -302,7 +302,7 @@ static struct plat_sci_port scif7_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 208, 208, 208, 208 } + .irqs = SCIx_IRQ_MUXED(208), }; static struct platform_device scif7_device = { diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c index 0bd744f..bfc33f6 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c @@ -180,7 +180,7 @@ static struct plat_sci_port scif0_platform_data = { SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 192, 192, 192, 192 }, + .irqs = SCIx_IRQ_MUXED(192), .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; @@ -199,7 +199,7 @@ static struct plat_sci_port scif1_platform_data = { SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 196, 196, 196, 196 }, + .irqs = SCIx_IRQ_MUXED(196), .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; @@ -218,7 +218,7 @@ static struct plat_sci_port scif2_platform_data = { SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 200, 200, 200, 200 }, + .irqs = SCIx_IRQ_MUXED(200), .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; @@ -237,7 +237,7 @@ static struct plat_sci_port scif3_platform_data = { SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 204, 204, 204, 204 }, + .irqs = SCIx_IRQ_MUXED(204), .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c index 5d14f84..a501074 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c @@ -139,7 +139,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 240, 240, 240, 240 }, + .irqs = SCIx_IRQ_MUXED(240), }; static struct platform_device scif0_device = { @@ -156,7 +156,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 244, 244, 244, 244 }, + .irqs = SCIx_IRQ_MUXED(244), }; static struct platform_device scif1_device = { @@ -173,7 +173,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 248, 248, 248, 248 }, + .irqs = SCIx_IRQ_MUXED(248), }; static struct platform_device scif2_device = { @@ -190,7 +190,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 252, 252, 252, 252 }, + .irqs = SCIx_IRQ_MUXED(252), }; static struct platform_device scif3_device = { -- cgit v0.10.2 From fea88a0c02822fbb91a0b8301bf9af04377876a3 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 12 Apr 2012 15:45:32 +0900 Subject: sh: Add initial support for SH7734 CPU subtype This implements initial support for the SH7734. This adds support SCIF, TMU and RTC. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Paul Mundt diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index ff9e033..ed2419f 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -427,6 +427,16 @@ config CPU_SUBTYPE_SH7724 help Select SH7724 if you have an SH-MobileR2R CPU. +config CPU_SUBTYPE_SH7734 + bool "Support SH7734 processor" + select CPU_SH4A + select CPU_SHX2 + select ARCH_WANT_OPTIONAL_GPIOLIB + select USB_ARCH_HAS_OHCI + select USB_ARCH_HAS_EHCI + help + Select SH7734 if you have a SH4A SH7734 CPU. + config CPU_SUBTYPE_SH7757 bool "Support SH7757 processor" select CPU_SH4A @@ -584,7 +594,7 @@ config SH_CLK_CPG config SH_CLK_CPG_LEGACY depends on SH_CLK_CPG def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \ - !CPU_SHX3 && !CPU_SUBTYPE_SH7757 + !CPU_SHX3 && !CPU_SUBTYPE_SH7757 && !CPU_SUBTYPE_SH7734 source "kernel/time/Kconfig" diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h index a229c39..26b12fd 100644 --- a/arch/sh/include/asm/processor.h +++ b/arch/sh/include/asm/processor.h @@ -32,7 +32,7 @@ enum cpu_type { /* SH-4A types */ CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, - CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3, + CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SH7734, CPU_SHX3, /* SH4AL-DSP types */ CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372, diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h index cffd25e..1631fc2 100644 --- a/arch/sh/include/cpu-sh4/cpu/freq.h +++ b/arch/sh/include/cpu-sh4/cpu/freq.h @@ -47,6 +47,11 @@ #define MSTPCR1 0xa4150034 #define MSTPCR2 0xa4150038 +#elif defined(CONFIG_CPU_SUBTYPE_SH7734) +#define FRQCR0 0xffc80000 +#define FRQCR2 0xffc80008 +#define FRQMR1 0xffc80014 +#define FRQMR2 0xffc80018 #elif defined(CONFIG_CPU_SUBTYPE_SH7785) #define FRQCR0 0xffc80000 #define FRQCR1 0xffc80004 diff --git a/arch/sh/include/cpu-sh4/cpu/sh7734.h b/arch/sh/include/cpu-sh4/cpu/sh7734.h new file mode 100644 index 0000000..2fb9a7b --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/sh7734.h @@ -0,0 +1,306 @@ +#ifndef __ASM_SH7734_H__ +#define __ASM_SH7734_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU + */ +enum { + GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, + GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, + GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, + GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, + GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, + GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, + GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, + GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, + + GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, + GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, + GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, + GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, + GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, + GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, + GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, + GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31, + + GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, + GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, + GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, + GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, + GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, + GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, + GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, + GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31, + + GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, + GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, + GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, + GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, + GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, + GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, + GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, + GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, + + GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, + GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, + GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, + GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, + GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, + GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, + GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, + GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, + + GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, + GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, + GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, + + GPIO_FN_CLKOUT, GPIO_FN_BS, GPIO_FN_CS0, GPIO_FN_EX_CS0, GPIO_FN_RD, + GPIO_FN_WE0, GPIO_FN_WE1, + + GPIO_FN_SCL0, GPIO_FN_PENC0, GPIO_FN_USB_OVC0, + + GPIO_FN_IRQ2_B, GPIO_FN_IRQ3_B, + + /* IPSR0 */ + GPIO_FN_A15, GPIO_FN_ST0_VCO_CLKIN, GPIO_FN_LCD_DATA15_A, + GPIO_FN_TIOC3D_C, + GPIO_FN_A14, GPIO_FN_LCD_DATA14_A, GPIO_FN_TIOC3C_C, + GPIO_FN_A13, GPIO_FN_LCD_DATA13_A, GPIO_FN_TIOC3B_C, + GPIO_FN_A12, GPIO_FN_LCD_DATA12_A, GPIO_FN_TIOC3A_C, + GPIO_FN_A11, GPIO_FN_ST0_D7, GPIO_FN_LCD_DATA11_A, + GPIO_FN_TIOC2B_C, + GPIO_FN_A10, GPIO_FN_ST0_D6, GPIO_FN_LCD_DATA10_A, + GPIO_FN_TIOC2A_C, + GPIO_FN_A9, GPIO_FN_ST0_D5, GPIO_FN_LCD_DATA9_A, + GPIO_FN_TIOC1B_C, + GPIO_FN_A8, GPIO_FN_ST0_D4, GPIO_FN_LCD_DATA8_A, + GPIO_FN_TIOC1A_C, + GPIO_FN_A7, GPIO_FN_ST0_D3, GPIO_FN_LCD_DATA7_A, GPIO_FN_TIOC0D_C, + GPIO_FN_A6, GPIO_FN_ST0_D2, GPIO_FN_LCD_DATA6_A, GPIO_FN_TIOC0C_C, + GPIO_FN_A5, GPIO_FN_ST0_D1, GPIO_FN_LCD_DATA5_A, GPIO_FN_TIOC0B_C, + GPIO_FN_A4, GPIO_FN_ST0_D0, GPIO_FN_LCD_DATA4_A, GPIO_FN_TIOC0A_C, + GPIO_FN_A3, GPIO_FN_ST0_VLD, GPIO_FN_LCD_DATA3_A, GPIO_FN_TCLKD_C, + GPIO_FN_A2, GPIO_FN_ST0_SYC, GPIO_FN_LCD_DATA2_A, GPIO_FN_TCLKC_C, + GPIO_FN_A1, GPIO_FN_ST0_REQ, GPIO_FN_LCD_DATA1_A, GPIO_FN_TCLKB_C, + GPIO_FN_A0, GPIO_FN_ST0_CLKIN, GPIO_FN_LCD_DATA0_A, GPIO_FN_TCLKA_C, + + /* IPSR1 */ + GPIO_FN_D3, GPIO_FN_SD0_DAT3_A, GPIO_FN_MMC_D3_A, GPIO_FN_ST1_D6, + GPIO_FN_FD3_A, + GPIO_FN_D2, GPIO_FN_SD0_DAT2_A, GPIO_FN_MMC_D2_A, GPIO_FN_ST1_D5, + GPIO_FN_FD2_A, + GPIO_FN_D1, GPIO_FN_SD0_DAT1_A, GPIO_FN_MMC_D1_A, GPIO_FN_ST1_D4, + GPIO_FN_FD1_A, + GPIO_FN_D0, GPIO_FN_SD0_DAT0_A, GPIO_FN_MMC_D0_A, GPIO_FN_ST1_D3, + GPIO_FN_FD0_A, + GPIO_FN_A25, GPIO_FN_TX2_D, GPIO_FN_ST1_D2, + GPIO_FN_A24, GPIO_FN_RX2_D, GPIO_FN_ST1_D1, + GPIO_FN_A23, GPIO_FN_ST1_D0, GPIO_FN_LCD_M_DISP_A, + GPIO_FN_A22, GPIO_FN_ST1_VLD, GPIO_FN_LCD_VEPWC_A, + GPIO_FN_A21, GPIO_FN_ST1_SYC, GPIO_FN_LCD_VCPWC_A, + GPIO_FN_A20, GPIO_FN_ST1_REQ, GPIO_FN_LCD_FLM_A, + GPIO_FN_A19, GPIO_FN_ST1_CLKIN, GPIO_FN_LCD_CLK_A, GPIO_FN_TIOC4D_C, + GPIO_FN_A18, GPIO_FN_ST1_PWM, GPIO_FN_LCD_CL2_A, GPIO_FN_TIOC4C_C, + GPIO_FN_A17, GPIO_FN_ST1_VCO_CLKIN, GPIO_FN_LCD_CL1_A, GPIO_FN_TIOC4B_C, + GPIO_FN_A16, GPIO_FN_ST0_PWM, GPIO_FN_LCD_DON_A, GPIO_FN_TIOC4A_C, + + /* IPSR2 */ + GPIO_FN_D14, GPIO_FN_TX2_B, GPIO_FN_FSE_A, GPIO_FN_ET0_TX_CLK_B, + GPIO_FN_D13, GPIO_FN_RX2_B, GPIO_FN_FRB_A, GPIO_FN_ET0_ETXD6_B, + GPIO_FN_D12, GPIO_FN_FWE_A, GPIO_FN_ET0_ETXD5_B, + GPIO_FN_D11, GPIO_FN_RSPI_MISO_A, GPIO_FN_QMI_QIO1_A, + GPIO_FN_FRE_A, GPIO_FN_ET0_ETXD3_B, + GPIO_FN_D10, GPIO_FN_RSPI_MOSI_A, GPIO_FN_QMO_QIO0_A, + GPIO_FN_FALE_A, GPIO_FN_ET0_ETXD2_B, + GPIO_FN_D9, GPIO_FN_SD0_CMD_A, GPIO_FN_MMC_CMD_A, GPIO_FN_QIO3_A, + GPIO_FN_FCLE_A, GPIO_FN_ET0_ETXD1_B, + GPIO_FN_D8, GPIO_FN_SD0_CLK_A, GPIO_FN_MMC_CLK_A, GPIO_FN_QIO2_A, + GPIO_FN_FCE_A, GPIO_FN_ET0_GTX_CLK_B, + GPIO_FN_D7, GPIO_FN_RSPI_SSL_A, GPIO_FN_MMC_D7_A, GPIO_FN_QSSL_A, + GPIO_FN_FD7_A, + GPIO_FN_D6, GPIO_FN_RSPI_RSPCK_A, GPIO_FN_MMC_D6_A, GPIO_FN_QSPCLK_A, + GPIO_FN_FD6_A, + GPIO_FN_D5, GPIO_FN_SD0_WP_A, GPIO_FN_MMC_D5_A, GPIO_FN_FD5_A, + GPIO_FN_D4, GPIO_FN_SD0_CD_A, GPIO_FN_MMC_D4_A, GPIO_FN_ST1_D7, + GPIO_FN_FD4_A, + + /* IPSR3 */ + GPIO_FN_DRACK0, GPIO_FN_SD1_DAT2_A, GPIO_FN_ATAG, GPIO_FN_TCLK1_A, + GPIO_FN_ET0_ETXD7, + GPIO_FN_EX_WAIT2, GPIO_FN_SD1_DAT1_A, GPIO_FN_DACK2, GPIO_FN_CAN1_RX_C, + GPIO_FN_ET0_MAGIC_C, GPIO_FN_ET0_ETXD6_A, + GPIO_FN_EX_WAIT1, GPIO_FN_SD1_DAT0_A, GPIO_FN_DREQ2, GPIO_FN_CAN1_TX_C, + GPIO_FN_ET0_LINK_C, GPIO_FN_ET0_ETXD5_A, + GPIO_FN_EX_WAIT0, GPIO_FN_TCLK1_B, + GPIO_FN_RD_WR, GPIO_FN_TCLK0, + GPIO_FN_EX_CS5, GPIO_FN_SD1_CMD_A, GPIO_FN_ATADIR, GPIO_FN_QSSL_B, + GPIO_FN_ET0_ETXD3_A, + GPIO_FN_EX_CS4, GPIO_FN_SD1_WP_A, GPIO_FN_ATAWR, GPIO_FN_QMI_QIO1_B, + GPIO_FN_ET0_ETXD2_A, + GPIO_FN_EX_CS3, GPIO_FN_SD1_CD_A, GPIO_FN_ATARD, GPIO_FN_QMO_QIO0_B, + GPIO_FN_ET0_ETXD1_A, + GPIO_FN_EX_CS2, GPIO_FN_TX3_B, GPIO_FN_ATACS1, GPIO_FN_QSPCLK_B, + GPIO_FN_ET0_GTX_CLK_A, + GPIO_FN_EX_CS1, GPIO_FN_RX3_B, GPIO_FN_ATACS0, GPIO_FN_QIO2_B, + GPIO_FN_ET0_ETXD0, + GPIO_FN_CS1_A26, GPIO_FN_QIO3_B, + GPIO_FN_D15, GPIO_FN_SCK2_B, + + /* IPSR4 */ + GPIO_FN_SCK2_A, GPIO_FN_VI0_G3, + GPIO_FN_RTS1_B, GPIO_FN_VI0_G2, + GPIO_FN_CTS1_B, GPIO_FN_VI0_DATA7_VI0_G1, + GPIO_FN_TX1_B, GPIO_FN_VI0_DATA6_VI0_G0, GPIO_FN_ET0_PHY_INT_A, + GPIO_FN_RX1_B, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_ET0_MAGIC_A, + GPIO_FN_SCK1_B, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ET0_LINK_A, + GPIO_FN_RTS0_B, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ET0_MDIO_A, + GPIO_FN_CTS0_B, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_RMII0_MDIO_A, + GPIO_FN_ET0_MDC, + GPIO_FN_HTX0_A, GPIO_FN_TX1_A, GPIO_FN_VI0_DATA1_VI0_B1, + GPIO_FN_RMII0_MDC_A, GPIO_FN_ET0_COL, + GPIO_FN_HRX0_A, GPIO_FN_RX1_A, GPIO_FN_VI0_DATA0_VI0_B0, + GPIO_FN_RMII0_CRS_DV_A, GPIO_FN_ET0_CRS, + GPIO_FN_HSCK0_A, GPIO_FN_SCK1_A, GPIO_FN_VI0_VSYNC, + GPIO_FN_RMII0_RX_ER_A, GPIO_FN_ET0_RX_ER, + GPIO_FN_HRTS0_A, GPIO_FN_RTS1_A, GPIO_FN_VI0_HSYNC, + GPIO_FN_RMII0_TXD_EN_A, GPIO_FN_ET0_RX_DV, + GPIO_FN_HCTS0_A, GPIO_FN_CTS1_A, GPIO_FN_VI0_FIELD, + GPIO_FN_RMII0_RXD1_A, GPIO_FN_ET0_ERXD7, + + /* IPSR5 */ + GPIO_FN_SD2_CLK_A, GPIO_FN_RX2_A, GPIO_FN_VI0_G4, GPIO_FN_ET0_RX_CLK_B, + GPIO_FN_SD2_CMD_A, GPIO_FN_TX2_A, GPIO_FN_VI0_G5, GPIO_FN_ET0_ERXD2_B, + GPIO_FN_SD2_DAT0_A, GPIO_FN_RX3_A, GPIO_FN_VI0_R0, GPIO_FN_ET0_ERXD3_B, + GPIO_FN_SD2_DAT1_A, GPIO_FN_TX3_A, GPIO_FN_VI0_R1, GPIO_FN_ET0_MDIO_B, + GPIO_FN_SD2_DAT2_A, GPIO_FN_RX4_A, GPIO_FN_VI0_R2, GPIO_FN_ET0_LINK_B, + GPIO_FN_SD2_DAT3_A, GPIO_FN_TX4_A, GPIO_FN_VI0_R3, GPIO_FN_ET0_MAGIC_B, + GPIO_FN_SD2_CD_A, GPIO_FN_RX5_A, GPIO_FN_VI0_R4, GPIO_FN_ET0_PHY_INT_B, + GPIO_FN_SD2_WP_A, GPIO_FN_TX5_A, GPIO_FN_VI0_R5, + GPIO_FN_REF125CK, GPIO_FN_ADTRG, GPIO_FN_RX5_C, + GPIO_FN_REF50CK, GPIO_FN_CTS1_E, GPIO_FN_HCTS0_D, + + /* IPSR6 */ + GPIO_FN_DU0_DR0, GPIO_FN_SCIF_CLK_B, GPIO_FN_HRX0_D, GPIO_FN_IETX_A, + GPIO_FN_TCLKA_A, GPIO_FN_HIFD00, + GPIO_FN_DU0_DR1, GPIO_FN_SCK0_B, GPIO_FN_HTX0_D, GPIO_FN_IERX_A, + GPIO_FN_TCLKB_A, GPIO_FN_HIFD01, + GPIO_FN_DU0_DR2, GPIO_FN_RX0_B, GPIO_FN_TCLKC_A, GPIO_FN_HIFD02, + GPIO_FN_DU0_DR3, GPIO_FN_TX0_B, GPIO_FN_TCLKD_A, GPIO_FN_HIFD03, + GPIO_FN_DU0_DR4, GPIO_FN_CTS0_C, GPIO_FN_TIOC0A_A, GPIO_FN_HIFD04, + GPIO_FN_DU0_DR5, GPIO_FN_RTS0_C, GPIO_FN_TIOC0B_A, GPIO_FN_HIFD05, + GPIO_FN_DU0_DR6, GPIO_FN_SCK1_C, GPIO_FN_TIOC0C_A, GPIO_FN_HIFD06, + GPIO_FN_DU0_DR7, GPIO_FN_RX1_C, GPIO_FN_TIOC0D_A, GPIO_FN_HIFD07, + GPIO_FN_DU0_DG0, GPIO_FN_TX1_C, GPIO_FN_HSCK0_D, GPIO_FN_IECLK_A, + GPIO_FN_TIOC1A_A, GPIO_FN_HIFD08, + GPIO_FN_DU0_DG1, GPIO_FN_CTS1_C, GPIO_FN_HRTS0_D, GPIO_FN_TIOC1B_A, + GPIO_FN_HIFD09, + + /* IPSR7 */ + GPIO_FN_DU0_DG2, GPIO_FN_RTS1_C, GPIO_FN_RMII0_MDC_B, GPIO_FN_TIOC2A_A, + GPIO_FN_HIFD10, + GPIO_FN_DU0_DG3, GPIO_FN_SCK2_C, GPIO_FN_RMII0_MDIO_B, GPIO_FN_TIOC2B_A, + GPIO_FN_HIFD11, + GPIO_FN_DU0_DG4, GPIO_FN_RX2_C, GPIO_FN_RMII0_CRS_DV_B, + GPIO_FN_TIOC3A_A, GPIO_FN_HIFD12, + GPIO_FN_DU0_DG5, GPIO_FN_TX2_C, GPIO_FN_RMII0_RX_ER_B, + GPIO_FN_TIOC3B_A, GPIO_FN_HIFD13, + GPIO_FN_DU0_DG6, GPIO_FN_RX3_C, GPIO_FN_RMII0_RXD0_B, + GPIO_FN_TIOC3C_A, GPIO_FN_HIFD14, + GPIO_FN_DU0_DG7, GPIO_FN_TX3_C, GPIO_FN_RMII0_RXD1_B, + GPIO_FN_TIOC3D_A, GPIO_FN_HIFD15, + GPIO_FN_DU0_DB0, GPIO_FN_RX4_C, GPIO_FN_RMII0_TXD_EN_B, + GPIO_FN_TIOC4A_A, GPIO_FN_HIFCS, + GPIO_FN_DU0_DB1, GPIO_FN_TX4_C, GPIO_FN_RMII0_TXD0_B, + GPIO_FN_TIOC4B_A, GPIO_FN_HIFRS, + GPIO_FN_DU0_DB2, GPIO_FN_RX5_B, GPIO_FN_RMII0_TXD1_B, + GPIO_FN_TIOC4C_A, GPIO_FN_HIFWR, + GPIO_FN_DU0_DB3, GPIO_FN_TX5_B, GPIO_FN_TIOC4D_A, GPIO_FN_HIFRD, + GPIO_FN_DU0_DB4, GPIO_FN_HIFINT, + + /* IPSR8 */ + GPIO_FN_DU0_DB5, GPIO_FN_HIFDREQ, + GPIO_FN_DU0_DB6, GPIO_FN_HIFRDY, + GPIO_FN_DU0_DB7, GPIO_FN_SSI_SCK0_B, GPIO_FN_HIFEBL_B, + GPIO_FN_DU0_DOTCLKIN, GPIO_FN_HSPI_CS0_C, GPIO_FN_SSI_WS0_B, + GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_HSPI_CLK0_C, GPIO_FN_SSI_SDATA0_B, + GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_HSPI_TX0_C, GPIO_FN_SSI_SCK1_B, + GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_HSPI_RX0_C, GPIO_FN_SSI_WS1_B, + GPIO_FN_DU0_EXODDF_DU0_ODDF, GPIO_FN_CAN0_RX_B, GPIO_FN_HSCK0_B, + GPIO_FN_SSI_SDATA1_B, + GPIO_FN_DU0_DISP, GPIO_FN_CAN0_TX_B, GPIO_FN_HRX0_B, + GPIO_FN_AUDIO_CLKA_B, + GPIO_FN_DU0_CDE, GPIO_FN_HTX0_B, GPIO_FN_AUDIO_CLKB_B, + GPIO_FN_LCD_VCPWC_B, + GPIO_FN_IRQ0_A, GPIO_FN_HSPI_TX_B, GPIO_FN_RX3_E, GPIO_FN_ET0_ERXD0, + GPIO_FN_IRQ1_A, GPIO_FN_HSPI_RX_B, GPIO_FN_TX3_E, GPIO_FN_ET0_ERXD1, + GPIO_FN_IRQ2_A, GPIO_FN_CTS0_A, GPIO_FN_HCTS0_B, GPIO_FN_ET0_ERXD2_A, + GPIO_FN_IRQ3_A, GPIO_FN_RTS0_A, GPIO_FN_HRTS0_B, GPIO_FN_ET0_ERXD3_A, + + /* IPSR9 */ + GPIO_FN_VI1_CLK_A, GPIO_FN_FD0_B, GPIO_FN_LCD_DATA0_B, + GPIO_FN_VI1_0_A, GPIO_FN_FD1_B, GPIO_FN_LCD_DATA1_B, + GPIO_FN_VI1_1_A, GPIO_FN_FD2_B, GPIO_FN_LCD_DATA2_B, + GPIO_FN_VI1_2_A, GPIO_FN_FD3_B, GPIO_FN_LCD_DATA3_B, + GPIO_FN_VI1_3_A, GPIO_FN_FD4_B, GPIO_FN_LCD_DATA4_B, + GPIO_FN_VI1_4_A, GPIO_FN_FD5_B, GPIO_FN_LCD_DATA5_B, + GPIO_FN_VI1_5_A, GPIO_FN_FD6_B, GPIO_FN_LCD_DATA6_B, + GPIO_FN_VI1_6_A, GPIO_FN_FD7_B, GPIO_FN_LCD_DATA7_B, + GPIO_FN_VI1_7_A, GPIO_FN_FCE_B, GPIO_FN_LCD_DATA8_B, + GPIO_FN_SSI_SCK0_A, GPIO_FN_TIOC1A_B, GPIO_FN_LCD_DATA9_B, + GPIO_FN_SSI_WS0_A, GPIO_FN_TIOC1B_B, GPIO_FN_LCD_DATA10_B, + GPIO_FN_SSI_SDATA0_A, GPIO_FN_VI1_0_B, GPIO_FN_TIOC2A_B, + GPIO_FN_LCD_DATA11_B, + GPIO_FN_SSI_SCK1_A, GPIO_FN_VI1_1_B, GPIO_FN_TIOC2B_B, + GPIO_FN_LCD_DATA12_B, + GPIO_FN_SSI_WS1_A, GPIO_FN_VI1_2_B, GPIO_FN_LCD_DATA13_B, + GPIO_FN_SSI_SDATA1_A, GPIO_FN_VI1_3_B, GPIO_FN_LCD_DATA14_B, + + /* IPSR10 */ + GPIO_FN_SSI_SCK23, GPIO_FN_VI1_4_B, GPIO_FN_RX1_D, GPIO_FN_FCLE_B, + GPIO_FN_LCD_DATA15_B, + GPIO_FN_SSI_WS23, GPIO_FN_VI1_5_B, GPIO_FN_TX1_D, GPIO_FN_HSCK0_C, + GPIO_FN_FALE_B, GPIO_FN_LCD_DON_B, + GPIO_FN_SSI_SDATA2, GPIO_FN_VI1_6_B, GPIO_FN_HRX0_C, GPIO_FN_FRE_B, + GPIO_FN_LCD_CL1_B, + GPIO_FN_SSI_SDATA3, GPIO_FN_VI1_7_B, GPIO_FN_HTX0_C, GPIO_FN_FWE_B, + GPIO_FN_LCD_CL2_B, + GPIO_FN_AUDIO_CLKA_A, GPIO_FN_VI1_CLK_B, GPIO_FN_SCK1_D, + GPIO_FN_IECLK_B, GPIO_FN_LCD_FLM_B, + GPIO_FN_AUDIO_CLKB_A, GPIO_FN_LCD_CLK_B, + GPIO_FN_AUDIO_CLKC, GPIO_FN_SCK1_E, GPIO_FN_HCTS0_C, GPIO_FN_FRB_B, + GPIO_FN_LCD_VEPWC_B, + GPIO_FN_AUDIO_CLKOUT, GPIO_FN_TX1_E, GPIO_FN_HRTS0_C, GPIO_FN_FSE_B, + GPIO_FN_LCD_M_DISP_B, + GPIO_FN_CAN_CLK_A, GPIO_FN_RX4_D, + GPIO_FN_CAN0_TX_A, GPIO_FN_TX4_D, GPIO_FN_MLB_CLK, + GPIO_FN_CAN1_RX_A, GPIO_FN_IRQ1_B, + GPIO_FN_CAN0_RX_A, GPIO_FN_IRQ0_B, GPIO_FN_MLB_SIG, + GPIO_FN_CAN1_TX_A, GPIO_FN_TX5_C, GPIO_FN_MLB_DAT, + + /* IPSR11 */ + GPIO_FN_SCL1, GPIO_FN_SCIF_CLK_C, + GPIO_FN_SDA1, GPIO_FN_RX1_E, + GPIO_FN_SDA0, GPIO_FN_HIFEBL_A, + GPIO_FN_SDSELF, GPIO_FN_RTS1_E, + GPIO_FN_SCIF_CLK_A, GPIO_FN_HSPI_CLK_A, GPIO_FN_VI0_CLK, + GPIO_FN_RMII0_TXD0_A, GPIO_FN_ET0_ERXD4, + GPIO_FN_SCK0_A, GPIO_FN_HSPI_CS_A, GPIO_FN_VI0_CLKENB, + GPIO_FN_RMII0_TXD1_A, GPIO_FN_ET0_ERXD5, + GPIO_FN_RX0_A, GPIO_FN_HSPI_RX_A, GPIO_FN_RMII0_RXD0_A, + GPIO_FN_ET0_ERXD6, + GPIO_FN_TX0_A, GPIO_FN_HSPI_TX_A, + GPIO_FN_PENC1, GPIO_FN_TX3_D, GPIO_FN_CAN1_TX_B, GPIO_FN_TX5_D, + GPIO_FN_IETX_B, + GPIO_FN_USB_OVC1, GPIO_FN_RX3_D, GPIO_FN_CAN1_RX_B, GPIO_FN_RX5_D, + GPIO_FN_IERX_B, + GPIO_FN_DREQ0, GPIO_FN_SD1_CLK_A, GPIO_FN_ET0_TX_EN, + GPIO_FN_DACK0, GPIO_FN_SD1_DAT3_A, GPIO_FN_ET0_TX_ER, + GPIO_FN_DREQ1, GPIO_FN_HSPI_CLK_B, GPIO_FN_RX4_B, GPIO_FN_ET0_PHY_INT_C, + GPIO_FN_ET0_TX_CLK_A, + GPIO_FN_DACK1, GPIO_FN_HSPI_CS_B, GPIO_FN_TX4_B, GPIO_FN_ET0_RX_CLK_A, + GPIO_FN_PRESETOUT, GPIO_FN_ST_CLKOUT, + +}; + +#endif /* __ASM_SH7734_H__ */ diff --git a/arch/sh/kernel/cpu/proc.c b/arch/sh/kernel/cpu/proc.c index f47be87..e3a16d1 100644 --- a/arch/sh/kernel/cpu/proc.c +++ b/arch/sh/kernel/cpu/proc.c @@ -25,7 +25,8 @@ static const char *cpu_name[] = { [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103", [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723", [CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724", - [CPU_SH7372] = "SH7372", [CPU_SH_NONE] = "Unknown" + [CPU_SH7372] = "SH7372", [CPU_SH7734] = "SH7734", + [CPU_SH_NONE] = "Unknown" }; const char *get_cpu_subtype(struct sh_cpuinfo *c) diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c index 971cf0f..0fbbd50 100644 --- a/arch/sh/kernel/cpu/sh4/probe.c +++ b/arch/sh/kernel/cpu/sh4/probe.c @@ -158,6 +158,9 @@ void __cpuinit cpu_probe(void) case 0x40: /* yon-ten-go */ boot_cpu_data.type = CPU_SH7372; break; + case 0xE0: /* 0x4E0 */ + boot_cpu_data.type = CPU_SH7734; /* SH7733/SH7734 */ + break; } break; diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile index 0b22d10..ed71c3f 100644 --- a/arch/sh/kernel/cpu/sh4a/Makefile +++ b/arch/sh/kernel/cpu/sh4a/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o serial-sh7722.o obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o +obj-$(CONFIG_CPU_SUBTYPE_SH7734) += setup-sh7734.o obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o intc-shx3.o @@ -30,6 +31,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o +clock-$(CONFIG_CPU_SUBTYPE_SH7734) := clock-sh7734.o clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7734.c b/arch/sh/kernel/cpu/sh4a/clock-sh7734.c new file mode 100644 index 0000000..1697642 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7734.c @@ -0,0 +1,266 @@ +/* + * arch/sh/kernel/cpu/sh4a/clock-sh7734.c + * + * Clock framework for SH7734 + * + * Copyright (C) 2011, 2012 Nobuhiro Iwamatsu + * Copyright (C) 2011, 2012 Renesas Solutions Corp. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +static struct clk extal_clk = { + .rate = 33333333, +}; + +#define MODEMR (0xFFCC0020) +#define MODEMR_MASK (0x6) +#define MODEMR_533MHZ (0x2) + +static unsigned long pll_recalc(struct clk *clk) +{ + int mode = 12; + u32 r = __raw_readl(MODEMR); + + if ((r & MODEMR_MASK) & MODEMR_533MHZ) + mode = 16; + + return clk->parent->rate * mode; +} + +static struct sh_clk_ops pll_clk_ops = { + .recalc = pll_recalc, +}; + +static struct clk pll_clk = { + .ops = &pll_clk_ops, + .parent = &extal_clk, + .flags = CLK_ENABLE_ON_INIT, +}; + +static struct clk *main_clks[] = { + &extal_clk, + &pll_clk, +}; + +static int multipliers[] = { 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; +static int divisors[] = { 1, 3, 2, 3, 4, 6, 8, 9, 12, 16, 18, 24 }; + +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = divisors, + .nr_divisors = ARRAY_SIZE(divisors), + .multipliers = multipliers, + .nr_multipliers = ARRAY_SIZE(multipliers), +}; + +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, +}; + +enum { DIV4_I, DIV4_S, DIV4_B, DIV4_M, DIV4_S1, DIV4_P, DIV4_NR }; + +#define DIV4(_reg, _bit, _mask, _flags) \ + SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) + +struct clk div4_clks[DIV4_NR] = { + [DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT), + [DIV4_S] = DIV4(FRQMR1, 20, 0x000C, CLK_ENABLE_ON_INIT), + [DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT), + [DIV4_M] = DIV4(FRQMR1, 12, 0x0004, CLK_ENABLE_ON_INIT), + [DIV4_S1] = DIV4(FRQMR1, 4, 0x0030, CLK_ENABLE_ON_INIT), + [DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT), +}; + +#define MSTPCR0 0xFFC80030 +#define MSTPCR1 0xFFC80034 +#define MSTPCR3 0xFFC8003C + +enum { + MSTP030, MSTP029, /* IIC */ + MSTP026, MSTP025, MSTP024, /* SCIF */ + MSTP023, + MSTP022, MSTP021, + MSTP019, /* HSCIF */ + MSTP016, MSTP015, MSTP014, /* TMU / TIMER */ + MSTP012, MSTP011, MSTP010, MSTP009, MSTP008, /* SSI */ + MSTP007, /* HSPI */ + MSTP115, /* ADMAC */ + MSTP114, /* GETHER */ + MSTP111, /* DMAC */ + MSTP109, /* VIDEOIN1 */ + MSTP108, /* VIDEOIN0 */ + MSTP107, /* RGPVBG */ + MSTP106, /* 2DG */ + MSTP103, /* VIEW */ + MSTP100, /* USB */ + MSTP331, /* MMC */ + MSTP330, /* MIMLB */ + MSTP323, /* SDHI0 */ + MSTP322, /* SDHI1 */ + MSTP321, /* SDHI2 */ + MSTP320, /* RQSPI */ + MSTP319, /* SRC0 */ + MSTP318, /* SRC1 */ + MSTP317, /* RSPI */ + MSTP316, /* RCAN0 */ + MSTP315, /* RCAN1 */ + MSTP314, /* FLTCL */ + MSTP313, /* ADC */ + MSTP312, /* MTU */ + MSTP304, /* IE-BUS */ + MSTP303, /* RTC */ + MSTP302, /* HIF */ + MSTP301, /* STIF0 */ + MSTP300, /* STIF1 */ + MSTP_NR }; + +static struct clk mstp_clks[MSTP_NR] = { + /* MSTPCR0 */ + [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), + [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), + [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), + [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), + [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), + [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), + [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), + [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), + [MSTP019] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0), + [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), + [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), + [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), + [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0), + [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0), + [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), + [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), + [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), + [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), + + /* MSTPCR1 */ + [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), + [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0), + [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0), + [MSTP109] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), + [MSTP108] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0), + [MSTP107] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 7, 0), + [MSTP106] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 6, 0), + [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0), + [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), + + /* MSTPCR3 */ + [MSTP331] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 31, 0), + [MSTP330] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 30, 0), + [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), + [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), + [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), + [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), + [MSTP319] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 19, 0), + [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 18, 0), + [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 17, 0), + [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 16, 0), + [MSTP315] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 15, 0), + [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 14, 0), + [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 13, 0), + [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 12, 0), + [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 4, 0), + [MSTP303] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 3, 0), + [MSTP302] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 2, 0), + [MSTP301] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 1, 0), + [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 0, 0), +}; + +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("pll_clk", &pll_clk), + + /* clocks */ + CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), + CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]), + CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_M]), + CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), + CLKDEV_CON_ID("shyway_clk1", &div4_clks[DIV4_S1]), + CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + + /* MSTP32 clocks */ + CLKDEV_DEV_ID("i2c-sh7734.0", &mstp_clks[MSTP030]), + CLKDEV_DEV_ID("i2c-sh7734.1", &mstp_clks[MSTP029]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP026]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP024]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP023]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP022]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP021]), + CLKDEV_CON_ID("hscif", &mstp_clks[MSTP019]), + CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[MSTP016]), + CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[MSTP016]), + CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[MSTP016]), + CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[MSTP015]), + CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[MSTP015]), + CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[MSTP015]), + CLKDEV_ICK_ID("tmu_fck", "sh_tmu.6", &mstp_clks[MSTP014]), + CLKDEV_ICK_ID("tmu_fck", "sh_tmu.7", &mstp_clks[MSTP014]), + CLKDEV_ICK_ID("tmu_fck", "sh_tmu.8", &mstp_clks[MSTP014]), + CLKDEV_CON_ID("ssi0", &mstp_clks[MSTP012]), + CLKDEV_CON_ID("ssi1", &mstp_clks[MSTP011]), + CLKDEV_CON_ID("ssi2", &mstp_clks[MSTP010]), + CLKDEV_CON_ID("ssi3", &mstp_clks[MSTP009]), + CLKDEV_CON_ID("sss", &mstp_clks[MSTP008]), + CLKDEV_CON_ID("hspi", &mstp_clks[MSTP007]), + CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP100]), + CLKDEV_CON_ID("videoin0", &mstp_clks[MSTP109]), + CLKDEV_CON_ID("videoin1", &mstp_clks[MSTP108]), + CLKDEV_CON_ID("rgpvg", &mstp_clks[MSTP107]), + CLKDEV_CON_ID("2dg", &mstp_clks[MSTP106]), + CLKDEV_CON_ID("view", &mstp_clks[MSTP103]), + + CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP331]), + CLKDEV_CON_ID("mimlb0", &mstp_clks[MSTP330]), + CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP323]), + CLKDEV_CON_ID("sdhi1", &mstp_clks[MSTP322]), + CLKDEV_CON_ID("sdhi2", &mstp_clks[MSTP321]), + CLKDEV_CON_ID("rqspi0", &mstp_clks[MSTP320]), + CLKDEV_CON_ID("src0", &mstp_clks[MSTP319]), + CLKDEV_CON_ID("src1", &mstp_clks[MSTP318]), + CLKDEV_CON_ID("rsp0", &mstp_clks[MSTP317]), + CLKDEV_CON_ID("rcan0", &mstp_clks[MSTP316]), + CLKDEV_CON_ID("rcan1", &mstp_clks[MSTP315]), + CLKDEV_CON_ID("fltcl0", &mstp_clks[MSTP314]), + CLKDEV_CON_ID("adc0", &mstp_clks[MSTP313]), + CLKDEV_CON_ID("mtu0", &mstp_clks[MSTP312]), + CLKDEV_CON_ID("iebus0", &mstp_clks[MSTP304]), + CLKDEV_DEV_ID("sh-eth.0", &mstp_clks[MSTP114]), + CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP303]), + CLKDEV_CON_ID("hif0", &mstp_clks[MSTP302]), + CLKDEV_CON_ID("stif0", &mstp_clks[MSTP301]), + CLKDEV_CON_ID("stif1", &mstp_clks[MSTP300]), +}; + +int __init arch_clk_init(void) +{ + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(main_clks); i++) + ret |= clk_register(main_clks[i]); + + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); + + if (!ret) + ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), + &div4_table); + + if (!ret) + ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); + + return ret; +} diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c new file mode 100644 index 0000000..f799971 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c @@ -0,0 +1,800 @@ +/* + * arch/sh/kernel/cpu/sh4a/setup-sh7734.c + + * SH7734 Setup + * + * Copyright (C) 2011,2012 Nobuhiro Iwamatsu + * Copyright (C) 2011,2012 Renesas Solutions Corp. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* SCIF */ +static struct plat_sci_port scif0_platform_data = { + .mapbase = 0xFFE40000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x8C0)), + .regtype = SCIx_SH4_SCIF_REGTYPE, +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +static struct plat_sci_port scif1_platform_data = { + .mapbase = 0xFFE41000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x8E0)), + .regtype = SCIx_SH4_SCIF_REGTYPE, +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +static struct plat_sci_port scif2_platform_data = { + .mapbase = 0xFFE42000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), + .regtype = SCIx_SH4_SCIF_REGTYPE, +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .dev = { + .platform_data = &scif2_platform_data, + }, +}; + +static struct plat_sci_port scif3_platform_data = { + .mapbase = 0xFFE43000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x920)), + .regtype = SCIx_SH4_SCIF_REGTYPE, +}; + +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 3, + .dev = { + .platform_data = &scif3_platform_data, + }, +}; + +static struct plat_sci_port scif4_platform_data = { + .mapbase = 0xFFE44000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x940)), + .regtype = SCIx_SH4_SCIF_REGTYPE, +}; + +static struct platform_device scif4_device = { + .name = "sh-sci", + .id = 4, + .dev = { + .platform_data = &scif4_platform_data, + }, +}; + +static struct plat_sci_port scif5_platform_data = { + .mapbase = 0xFFE43000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x960)), + .regtype = SCIx_SH4_SCIF_REGTYPE, +}; + +static struct platform_device scif5_device = { + .name = "sh-sci", + .id = 5, + .dev = { + .platform_data = &scif5_platform_data, + }, +}; + +/* RTC */ +static struct resource rtc_resources[] = { + [0] = { + .name = "rtc", + .start = 0xFFFC5000, + .end = 0xFFFC5000 + 0x26 - 1, + .flags = IORESOURCE_IO, + }, + [1] = { + .start = evt2irq(0xC00), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device rtc_device = { + .name = "sh-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; + +/* I2C 0 */ +static struct resource i2c0_resources[] = { + [0] = { + .name = "IIC0", + .start = 0xFFC70000, + .end = 0xFFC7000A - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x860), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device i2c0_device = { + .name = "i2c-sh7734", + .id = 0, + .num_resources = ARRAY_SIZE(i2c0_resources), + .resource = i2c0_resources, +}; + +/* TMU */ +static struct sh_timer_config tmu0_platform_data = { + .channel_offset = 0x04, + .timer_bit = 0, + .clockevent_rating = 200, +}; + +static struct resource tmu0_resources[] = { + [0] = { + .start = 0xFFD80008, + .end = 0xFFD80014 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x400), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tmu0_device = { + .name = "sh_tmu", + .id = 0, + .dev = { + .platform_data = &tmu0_platform_data, + }, + .resource = tmu0_resources, + .num_resources = ARRAY_SIZE(tmu0_resources), +}; + +static struct sh_timer_config tmu1_platform_data = { + .channel_offset = 0x10, + .timer_bit = 1, + .clocksource_rating = 200, +}; + +static struct resource tmu1_resources[] = { + [0] = { + .start = 0xFFD80014, + .end = 0xFFD80020 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x420), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tmu1_device = { + .name = "sh_tmu", + .id = 1, + .dev = { + .platform_data = &tmu1_platform_data, + }, + .resource = tmu1_resources, + .num_resources = ARRAY_SIZE(tmu1_resources), +}; + +static struct sh_timer_config tmu2_platform_data = { + .channel_offset = 0x1c, + .timer_bit = 2, +}; + +static struct resource tmu2_resources[] = { + [0] = { + .start = 0xFFD80020, + .end = 0xFFD80030 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x440), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tmu2_device = { + .name = "sh_tmu", + .id = 2, + .dev = { + .platform_data = &tmu2_platform_data, + }, + .resource = tmu2_resources, + .num_resources = ARRAY_SIZE(tmu2_resources), +}; + + +static struct sh_timer_config tmu3_platform_data = { + .channel_offset = 0x04, + .timer_bit = 0, +}; + +static struct resource tmu3_resources[] = { + [0] = { + .start = 0xFFD81008, + .end = 0xFFD81014 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x480), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tmu3_device = { + .name = "sh_tmu", + .id = 3, + .dev = { + .platform_data = &tmu3_platform_data, + }, + .resource = tmu3_resources, + .num_resources = ARRAY_SIZE(tmu3_resources), +}; + +static struct sh_timer_config tmu4_platform_data = { + .channel_offset = 0x10, + .timer_bit = 1, +}; + +static struct resource tmu4_resources[] = { + [0] = { + .start = 0xFFD81014, + .end = 0xFFD81020 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x4A0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tmu4_device = { + .name = "sh_tmu", + .id = 4, + .dev = { + .platform_data = &tmu4_platform_data, + }, + .resource = tmu4_resources, + .num_resources = ARRAY_SIZE(tmu4_resources), +}; + +static struct sh_timer_config tmu5_platform_data = { + .channel_offset = 0x1c, + .timer_bit = 2, +}; + +static struct resource tmu5_resources[] = { + [0] = { + .start = 0xFFD81020, + .end = 0xFFD81030 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x4C0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tmu5_device = { + .name = "sh_tmu", + .id = 5, + .dev = { + .platform_data = &tmu5_platform_data, + }, + .resource = tmu5_resources, + .num_resources = ARRAY_SIZE(tmu5_resources), +}; + +static struct sh_timer_config tmu6_platform_data = { + .channel_offset = 0x4, + .timer_bit = 0, +}; + +static struct resource tmu6_resources[] = { + [0] = { + .start = 0xFFD82008, + .end = 0xFFD82014 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x500), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tmu6_device = { + .name = "sh_tmu", + .id = 6, + .dev = { + .platform_data = &tmu6_platform_data, + }, + .resource = tmu6_resources, + .num_resources = ARRAY_SIZE(tmu6_resources), +}; + +static struct sh_timer_config tmu7_platform_data = { + .channel_offset = 0x10, + .timer_bit = 1, +}; + +static struct resource tmu7_resources[] = { + [0] = { + .start = 0xFFD82014, + .end = 0xFFD82020 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x520), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tmu7_device = { + .name = "sh_tmu", + .id = 7, + .dev = { + .platform_data = &tmu7_platform_data, + }, + .resource = tmu7_resources, + .num_resources = ARRAY_SIZE(tmu7_resources), +}; + +static struct sh_timer_config tmu8_platform_data = { + .channel_offset = 0x1c, + .timer_bit = 2, +}; + +static struct resource tmu8_resources[] = { + [0] = { + .start = 0xFFD82020, + .end = 0xFFD82030 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x540), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tmu8_device = { + .name = "sh_tmu", + .id = 8, + .dev = { + .platform_data = &tmu8_platform_data, + }, + .resource = tmu8_resources, + .num_resources = ARRAY_SIZE(tmu8_resources), +}; + +static struct platform_device *sh7734_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &tmu0_device, + &tmu1_device, + &tmu2_device, + &tmu3_device, + &tmu4_device, + &tmu5_device, + &tmu6_device, + &tmu7_device, + &tmu8_device, + &rtc_device, +}; + +static struct platform_device *sh7734_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &tmu0_device, + &tmu1_device, + &tmu2_device, + &tmu3_device, + &tmu4_device, + &tmu5_device, + &tmu6_device, + &tmu7_device, + &tmu8_device, +}; + +void __init plat_early_device_setup(void) +{ + early_platform_add_devices(sh7734_early_devices, + ARRAY_SIZE(sh7734_early_devices)); +} + +#define GROUP 0 +enum { + UNUSED = 0, + + /* interrupt sources */ + + IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, + IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, + IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, + IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, + + IRQ0, IRQ1, IRQ2, IRQ3, + DU, + TMU00, TMU10, TMU20, TMU21, + TMU30, TMU40, TMU50, TMU51, + TMU60, TMU70, TMU80, + RESET_WDT, + USB, + HUDI, + SHDMAC, + SSI0, SSI1, SSI2, SSI3, + VIN0, + RGPVG, + _2DG, + MMC, + HSPI, + LBSCATA, + I2C0, + RCAN0, + MIMLB, + SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, + LBSCDMAC0, LBSCDMAC1, LBSCDMAC2, + RCAN1, + SDHI0, SDHI1, + IEBUS, + HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22, HPBDMAC23_25_27_28, + RTC, + VIN1, + LCDC, + SRC0, SRC1, + GETHER, + SDHI2, + GPIO0_3, GPIO4_5, + STIF0, STIF1, + ADMAC, + HIF, + FLCTL, + ADC, + MTU2, + RSPI, + QSPI, + HSCIF, + VEU3F_VE3, + + /* Group */ + /* Mask */ + STIF_M, + GPIO_M, + HPBDMAC_M, + LBSCDMAC_M, + RCAN_M, + SRC_M, + SCIF_M, + LCDC_M, + _2DG_M, + VIN_M, + TMU_3_M, + TMU_0_M, + + /* Priority */ + RCAN_P, + LBSCDMAC_P, + + /* Common */ + SDHI, + SSI, + SPI, +}; + +static struct intc_vect vectors[] __initdata = { + INTC_VECT(DU, 0x3E0), + INTC_VECT(TMU00, 0x400), + INTC_VECT(TMU10, 0x420), + INTC_VECT(TMU20, 0x440), + INTC_VECT(TMU30, 0x480), + INTC_VECT(TMU40, 0x4A0), + INTC_VECT(TMU50, 0x4C0), + INTC_VECT(TMU51, 0x4E0), + INTC_VECT(TMU60, 0x500), + INTC_VECT(TMU70, 0x520), + INTC_VECT(TMU80, 0x540), + INTC_VECT(RESET_WDT, 0x560), + INTC_VECT(USB, 0x580), + INTC_VECT(HUDI, 0x600), + INTC_VECT(SHDMAC, 0x620), + INTC_VECT(SSI0, 0x6C0), + INTC_VECT(SSI1, 0x6E0), + INTC_VECT(SSI2, 0x700), + INTC_VECT(SSI3, 0x720), + INTC_VECT(VIN0, 0x740), + INTC_VECT(RGPVG, 0x760), + INTC_VECT(_2DG, 0x780), + INTC_VECT(MMC, 0x7A0), + INTC_VECT(HSPI, 0x7E0), + INTC_VECT(LBSCATA, 0x840), + INTC_VECT(I2C0, 0x860), + INTC_VECT(RCAN0, 0x880), + INTC_VECT(SCIF0, 0x8A0), + INTC_VECT(SCIF1, 0x8C0), + INTC_VECT(SCIF2, 0x900), + INTC_VECT(SCIF3, 0x920), + INTC_VECT(SCIF4, 0x940), + INTC_VECT(SCIF5, 0x960), + INTC_VECT(LBSCDMAC0, 0x9E0), + INTC_VECT(LBSCDMAC1, 0xA00), + INTC_VECT(LBSCDMAC2, 0xA20), + INTC_VECT(RCAN1, 0xA60), + INTC_VECT(SDHI0, 0xAE0), + INTC_VECT(SDHI1, 0xB00), + INTC_VECT(IEBUS, 0xB20), + INTC_VECT(HPBDMAC0_3, 0xB60), + INTC_VECT(HPBDMAC4_10, 0xB80), + INTC_VECT(HPBDMAC11_18, 0xBA0), + INTC_VECT(HPBDMAC19_22, 0xBC0), + INTC_VECT(HPBDMAC23_25_27_28, 0xBE0), + INTC_VECT(RTC, 0xC00), + INTC_VECT(VIN1, 0xC20), + INTC_VECT(LCDC, 0xC40), + INTC_VECT(SRC0, 0xC60), + INTC_VECT(SRC1, 0xC80), + INTC_VECT(GETHER, 0xCA0), + INTC_VECT(SDHI2, 0xCC0), + INTC_VECT(GPIO0_3, 0xCE0), + INTC_VECT(GPIO4_5, 0xD00), + INTC_VECT(STIF0, 0xD20), + INTC_VECT(STIF1, 0xD40), + INTC_VECT(ADMAC, 0xDA0), + INTC_VECT(HIF, 0xDC0), + INTC_VECT(FLCTL, 0xDE0), + INTC_VECT(ADC, 0xE00), + INTC_VECT(MTU2, 0xE20), + INTC_VECT(RSPI, 0xE40), + INTC_VECT(QSPI, 0xE60), + INTC_VECT(HSCIF, 0xFC0), + INTC_VECT(VEU3F_VE3, 0xF40), +}; + +static struct intc_group groups[] __initdata = { + /* Common */ + INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2), + INTC_GROUP(SPI, HSPI, RSPI, QSPI), + INTC_GROUP(SSI, SSI0, SSI1, SSI2, SSI3), + + /* Mask group */ + INTC_GROUP(STIF_M, STIF0, STIF1), /* 22 */ + INTC_GROUP(GPIO_M, GPIO0_3, GPIO4_5), /* 21 */ + INTC_GROUP(HPBDMAC_M, HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, + HPBDMAC19_22, HPBDMAC23_25_27_28), /* 19 */ + INTC_GROUP(LBSCDMAC_M, LBSCDMAC0, LBSCDMAC1, LBSCDMAC2), /* 18 */ + INTC_GROUP(RCAN_M, RCAN0, RCAN1, IEBUS), /* 17 */ + INTC_GROUP(SRC_M, SRC0, SRC1), /* 16 */ + INTC_GROUP(SCIF_M, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, + HSCIF), /* 14 */ + INTC_GROUP(LCDC_M, LCDC, MIMLB), /* 13 */ + INTC_GROUP(_2DG_M, _2DG, RGPVG), /* 12 */ + INTC_GROUP(VIN_M, VIN0, VIN1), /* 10 */ + INTC_GROUP(TMU_3_M, TMU30, TMU40, TMU50, TMU51, + TMU60, TMU60, TMU70, TMU80), /* 2 */ + INTC_GROUP(TMU_0_M, TMU00, TMU10, TMU20, TMU21), /* 1 */ + + /* Priority group*/ + INTC_GROUP(RCAN_P, RCAN0, RCAN1), /* INT2PRI5 */ + INTC_GROUP(LBSCDMAC_P, LBSCDMAC0, LBSCDMAC1), /* INT2PRI5 */ +}; + +static struct intc_mask_reg mask_registers[] __initdata = { + { 0xFF804040, 0xFF804044, 32, /* INT2MSKRG / INT2MSKCR */ + { 0, + VEU3F_VE3, + SDHI, /* SDHI 0-2 */ + ADMAC, + FLCTL, + RESET_WDT, + HIF, + ADC, + MTU2, + STIF_M, /* STIF 0,1 */ + GPIO_M, /* GPIO 0-5*/ + GETHER, + HPBDMAC_M, /* HPBDMAC 0_3 - 23_25_27_28 */ + LBSCDMAC_M, /* LBSCDMAC 0 - 2 */ + RCAN_M, /* RCAN, IEBUS */ + SRC_M, /* SRC 0,1 */ + LBSCATA, + SCIF_M, /* SCIF 0-5, HSCIF */ + LCDC_M, /* LCDC, MIMLB */ + _2DG_M, /* 2DG, RGPVG */ + SPI, /* HSPI, RSPI, QSPI */ + VIN_M, /* VIN0, 1 */ + SSI, /* SSI 0-3 */ + USB, + SHDMAC, + HUDI, + MMC, + RTC, + I2C0, /* I2C */ /* I2C 0, 1*/ + TMU_3_M, /* TMU30 - TMU80 */ + TMU_0_M, /* TMU00 - TMU21 */ + DU } }, +}; + +static struct intc_prio_reg prio_registers[] __initdata = { + { 0xFF804000, 0, 32, 8, /* INT2PRI0 */ + { DU, TMU00, TMU10, TMU20 } }, + { 0xFF804004, 0, 32, 8, /* INT2PRI1 */ + { TMU30, TMU60, RTC, SDHI } }, + { 0xFF804008, 0, 32, 8, /* INT2PRI2 */ + { HUDI, SHDMAC, USB, SSI } }, + { 0xFF80400C, 0, 32, 8, /* INT2PRI3 */ + { VIN0, SPI, _2DG, LBSCATA } }, + { 0xFF804010, 0, 32, 8, /* INT2PRI4 */ + { SCIF0, SCIF3, HSCIF, LCDC } }, + { 0xFF804014, 0, 32, 8, /* INT2PRI5 */ + { RCAN_P, LBSCDMAC_P, LBSCDMAC2, MMC } }, + { 0xFF804018, 0, 32, 8, /* INT2PRI6 */ + { HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22 } }, + { 0xFF80401C, 0, 32, 8, /* INT2PRI7 */ + { HPBDMAC23_25_27_28, I2C0, SRC0, SRC1 } }, + { 0xFF804020, 0, 32, 8, /* INT2PRI8 */ + { 0 /* ADIF */, VIN1, RESET_WDT, HIF } }, + { 0xFF804024, 0, 32, 8, /* INT2PRI9 */ + { ADMAC, FLCTL, GPIO0_3, GPIO4_5 } }, + { 0xFF804028, 0, 32, 8, /* INT2PRI10 */ + { STIF0, STIF1, VEU3F_VE3, GETHER } }, + { 0xFF80402C, 0, 32, 8, /* INT2PRI11 */ + { MTU2, RGPVG, MIMLB, IEBUS } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7734", vectors, groups, + mask_registers, prio_registers, NULL); + +/* Support for external interrupt pins in IRQ mode */ + +static struct intc_vect irq3210_vectors[] __initdata = { + INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), + INTC_VECT(IRQ2, 0x2C0), INTC_VECT(IRQ3, 0x300), +}; + +static struct intc_sense_reg irq3210_sense_registers[] __initdata = { + { 0xFF80201C, 32, 2, /* ICR1 */ + { IRQ0, IRQ1, IRQ2, IRQ3, } }, +}; + +static struct intc_mask_reg irq3210_ack_registers[] __initdata = { + { 0xFF802024, 0, 32, /* INTREQ */ + { IRQ0, IRQ1, IRQ2, IRQ3, } }, +}; + +static struct intc_mask_reg irq3210_mask_registers[] __initdata = { + { 0xFF802044, 0xFF802064, 32, /* INTMSK0 / INTMSKCLR0 */ + { IRQ0, IRQ1, IRQ2, IRQ3, } }, +}; + +static struct intc_prio_reg irq3210_prio_registers[] __initdata = { + { 0xFF802010, 0, 32, 4, /* INTPRI */ + { IRQ0, IRQ1, IRQ2, IRQ3, } }, +}; + +static DECLARE_INTC_DESC_ACK(intc_desc_irq3210, "sh7734-irq3210", + irq3210_vectors, NULL, + irq3210_mask_registers, irq3210_prio_registers, + irq3210_sense_registers, irq3210_ack_registers); + +/* External interrupt pins in IRL mode */ + +static struct intc_vect vectors_irl3210[] __initdata = { + INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220), + INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260), + INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0), + INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0), + INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320), + INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360), + INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0), + INTC_VECT(IRL0_HHHL, 0x3c0), +}; + +static DECLARE_INTC_DESC(intc_desc_irl3210, "sh7734-irl3210", + vectors_irl3210, NULL, mask_registers, NULL, NULL); + +#define INTC_ICR0 0xFF802000 +#define INTC_INTMSK0 0xFF802044 +#define INTC_INTMSK1 0xFF802048 +#define INTC_INTMSKCLR0 0xFF802064 +#define INTC_INTMSKCLR1 0xFF802068 + +void __init plat_irq_setup(void) +{ + /* disable IRQ3-0 */ + __raw_writel(0xF0000000, INTC_INTMSK0); + + /* disable IRL3-0 */ + __raw_writel(0x80000000, INTC_INTMSK1); + + /* select IRL mode for IRL3-0 */ + __raw_writel(__raw_readl(INTC_ICR0) & ~0x00800000, INTC_ICR0); + + /* disable holding function, ie enable "SH-4 Mode (LVLMODE)" */ + __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); + + register_intc_controller(&intc_desc); +} + +void __init plat_irq_setup_pins(int mode) +{ + switch (mode) { + case IRQ_MODE_IRQ3210: + /* select IRQ mode for IRL3-0 */ + __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); + register_intc_controller(&intc_desc_irq3210); + break; + case IRQ_MODE_IRL3210: + /* enable IRL0-3 but don't provide any masking */ + __raw_writel(0x80000000, INTC_INTMSKCLR1); + __raw_writel(0xf0000000, INTC_INTMSKCLR0); + break; + case IRQ_MODE_IRL3210_MASK: + /* enable IRL0-3 and mask using cpu intc controller */ + __raw_writel(0x80000000, INTC_INTMSKCLR0); + register_intc_controller(&intc_desc_irl3210); + break; + default: + BUG(); + } +} -- cgit v0.10.2 From 856cb4bb337ee50427e2b8daaf3a8d61de8a4f44 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 12 Apr 2012 15:45:33 +0900 Subject: sh: Add support pinmux for SH7734 Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile index ed71c3f..8fc6ec2 100644 --- a/arch/sh/kernel/cpu/sh4a/Makefile +++ b/arch/sh/kernel/cpu/sh4a/Makefile @@ -39,6 +39,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o +pinmux-$(CONFIG_CPU_SUBTYPE_SH7734) := pinmux-sh7734.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7734.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7734.c new file mode 100644 index 0000000..eed3b9d --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7734.c @@ -0,0 +1,2497 @@ +/* + * SH7734 processor support - PFC hardware block + * + * Copyright (C) 2012 Renesas Solutions Corp. + * Copyright (C) 2012 Nobuhiro Iwamatsu + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include + +#define CPU_32_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_1(fn, pfx##31, sfx) + +#define CPU_32_PORT5(fn, pfx, sfx) \ + PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ + PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ + PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ + PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx), \ + PORT_1(fn, pfx##10, sfx), PORT_1(fn, pfx##11, sfx) + +/* GPSR0 - GPSR5 */ +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT(fn, pfx##_0_, sfx), \ + CPU_32_PORT(fn, pfx##_1_, sfx), \ + CPU_32_PORT(fn, pfx##_2_, sfx), \ + CPU_32_PORT(fn, pfx##_3_, sfx), \ + CPU_32_PORT(fn, pfx##_4_, sfx), \ + CPU_32_PORT5(fn, pfx##_5_, sfx) + +#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) +#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ + GP##pfx##_IN, GP##pfx##_OUT) + +#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT +#define _GP_INDT(pfx, sfx) GP##pfx##_DATA + +#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) + +#define PORT_10_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ + PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ + PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ + PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) + +#define CPU_32_PORT_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ + PORT_10_REV(fn, pfx, sfx) + +#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) +#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) + +#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) +#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ + FN_##ipsr, FN_##fn) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), /* GP_0_0_DATA -> GP_5_11_DATA */ + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + GP_ALL(IN), /* GP_0_0_IN -> GP_5_11_IN */ + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + GP_ALL(OUT), /* GP_0_0_OUT -> GP_5_11_OUT */ + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), /* GP_0_0_FN -> GP_5_11_FN */ + + /* GPSR0 */ + FN_IP1_9_8, FN_IP1_11_10, FN_IP1_13_12, FN_IP1_15_14, + FN_IP0_7_6, FN_IP0_9_8, FN_IP0_11_10, FN_IP0_13_12, + FN_IP0_15_14, FN_IP0_17_16, FN_IP0_19_18, FN_IP0_21_20, + FN_IP0_23_22, FN_IP0_25_24, FN_IP0_27_26, FN_IP0_29_28, + FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, + FN_IP1_7_6, FN_IP11_28, FN_IP0_1_0, FN_IP0_3_2, + FN_IP0_5_4, FN_IP1_17_16, FN_IP1_19_18, FN_IP1_22_20, + FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, + + /* GPSR1 */ + FN_IP3_20, FN_IP3_29_27, FN_IP11_20_19, FN_IP11_22_21, + FN_IP2_16_14, FN_IP2_19_17, FN_IP2_22_20, FN_IP2_24_23, + FN_IP2_27_25, FN_IP2_30_28, FN_IP3_1_0, FN_CLKOUT, + FN_BS, FN_CS0, FN_IP3_2, FN_EX_CS0, + FN_IP3_5_3, FN_IP3_8_6, FN_IP3_11_9, FN_IP3_14_12, + FN_IP3_17_15, FN_RD, FN_IP3_19_18, FN_WE0, + FN_WE1, FN_IP2_4_3, FN_IP3_23_21, FN_IP3_26_24, + FN_IP2_7_5, FN_IP2_10_8, FN_IP2_13_11, FN_IP11_25_23, + + /* GPSR2 */ + FN_IP11_6_4, FN_IP11_9_7, FN_IP11_11_10, FN_IP4_2_0, + FN_IP8_29_28, FN_IP11_27_26, FN_IP8_22_20, FN_IP8_25_23, + FN_IP11_12, FN_IP8_27_26, FN_IP4_5_3, FN_IP4_8_6, + FN_IP4_11_9, FN_IP4_14_12, FN_IP4_17_15, FN_IP4_19_18, + FN_IP4_21_20, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26, + FN_IP4_29_28, FN_IP4_31_30, FN_IP5_2_0, FN_IP5_5_3, + FN_IP5_8_6, FN_IP5_11_9, FN_IP5_14_12, FN_IP5_17_15, + FN_IP5_20_18, FN_IP5_22_21, FN_IP5_24_23, FN_IP5_26_25, + + /* GPSR3 */ + FN_IP6_2_0, FN_IP6_5_3, FN_IP6_7_6, FN_IP6_9_8, + FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_17_16, + FN_IP6_20_18, FN_IP6_23_21, FN_IP7_2_0, FN_IP7_5_3, + FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, + FN_IP7_20_18, FN_IP7_23_21, FN_IP7_26_24, FN_IP7_28_27, + FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4, + FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, + FN_IP8_15_14, FN_IP8_17_16, FN_IP8_19_18, FN_IP9_1_0, + + /* GPSR4 */ + FN_IP9_19_18, FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, + FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14, FN_IP9_17_16, + FN_IP9_3_2, FN_IP9_5_4, FN_IP9_7_6, FN_IP9_9_8, + FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3, + FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_15, + FN_IP10_18_16, FN_IP10_21_19, FN_IP11_0, FN_IP11_1, + FN_SCL0, FN_IP11_2, FN_PENC0, FN_IP11_15_13, /* Need check*/ + FN_USB_OVC0, FN_IP11_18_16, + FN_IP10_22, FN_IP10_24_23, + + /* GPSR5 */ + FN_IP10_25, FN_IP11_3, FN_IRQ2_B, FN_IRQ3_B, + FN_IP10_27_26, /* 10 */ + FN_IP10_29_28, /* 11 */ + + /* IPSR0 */ + FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A, FN_TIOC3D_C, + FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C, + FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C, + FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C, + FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C, + FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C, + FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C, + FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C, + FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C, + FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C, + FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C, + FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C, + FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C, + FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C, + FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C, + FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C, + + /* IPSR1 */ + FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6, FN_FD3_A, + FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5, FN_FD2_A, + FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4, FN_FD1_A, + FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3, FN_FD0_A, + FN_A25, FN_TX2_D, FN_ST1_D2, + FN_A24, FN_RX2_D, FN_ST1_D1, + FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A, + FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A, + FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A, + FN_A20, FN_ST1_REQ, FN_LCD_FLM_A, + FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A, FN_TIOC4D_C, + FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C, + FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C, + FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C, + + /* IPSR2 */ + FN_D14, FN_TX2_B, FN_FSE_A, FN_ET0_TX_CLK_B, + FN_D13, FN_RX2_B, FN_FRB_A, FN_ET0_ETXD6_B, + FN_D12, FN_FWE_A, FN_ET0_ETXD5_B, + FN_D11, FN_RSPI_MISO_A, FN_QMI_QIO1_A, FN_FRE_A, + FN_ET0_ETXD3_B, + FN_D10, FN_RSPI_MOSI_A, FN_QMO_QIO0_A, FN_FALE_A, + FN_ET0_ETXD2_B, + FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A, FN_FCLE_A, + FN_ET0_ETXD1_B, + FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A, FN_FCE_A, + FN_ET0_GTX_CLK_B, + FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A, FN_FD7_A, + FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A, FN_FD6_A, + FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A, + FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7, FN_FD4_A, + + /* IPSR3 */ + FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A, FN_ET0_ETXD7, + FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C, + FN_ET0_MAGIC_C, FN_ET0_ETXD6_A, + FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C, + FN_ET0_LINK_C, FN_ET0_ETXD5_A, + FN_EX_WAIT0, FN_TCLK1_B, + FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4, + FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B, FN_ET0_ETXD3_A, + FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B, FN_ET0_ETXD2_A, + FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B, FN_ET0_ETXD1_A, + FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B, FN_ET0_GTX_CLK_A, + FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B, FN_ET0_ETXD0, + FN_CS1_A26, FN_QIO3_B, + FN_D15, FN_SCK2_B, + + /* IPSR4 */ + FN_SCK2_A, FN_VI0_G3, + FN_RTS1_B, FN_VI0_G2, + FN_CTS1_B, FN_VI0_DATA7_VI0_G1, + FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A, + FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A, + FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A, + FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A, + FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A, FN_ET0_MDC, + FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A, FN_ET0_COL, + FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A, FN_ET0_CRS, + FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A, FN_ET0_RX_ER, + FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A, FN_ET0_RX_DV, + FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A, FN_ET0_ERXD7, + + /* IPSR5 */ + FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, FN_ET0_RX_CLK_B, + FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, FN_ET0_ERXD2_B, + FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, FN_ET0_ERXD3_B, + FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, FN_ET0_MDIO_B, + FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, FN_ET0_LINK_B, + FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, FN_ET0_MAGIC_B, + FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, FN_ET0_PHY_INT_B, + FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5, + FN_REF125CK, FN_ADTRG, FN_RX5_C, + FN_REF50CK, FN_CTS1_E, FN_HCTS0_D, + + /* IPSR6 */ + FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A, FN_TCLKA_A, FN_HIFD00, + FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A, FN_TCLKB_A, FN_HIFD01, + FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02, + FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03, + FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04, + FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05, + FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06, + FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07, + FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A, FN_TIOC1A_A, FN_HIFD08, + FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A, FN_HIFD09, + + /* IPSR7 */ + FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A, FN_HIFD10, + FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A, FN_HIFD11, + FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A, FN_HIFD12, + FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A, FN_HIFD13, + FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A, FN_HIFD14, + FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A, FN_HIFD15, + FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A, FN_HIFCS, + FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A, FN_HIFRS, + FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A, FN_HIFWR, + FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD, + FN_DU0_DB4, FN_HIFINT, + + /* IPSR8 */ + FN_DU0_DB5, FN_HIFDREQ, + FN_DU0_DB6, FN_HIFRDY, + FN_DU0_DB7, FN_SSI_SCK0_B, FN_HIFEBL_B, + FN_DU0_DOTCLKIN, FN_HSPI_CS0_C, FN_SSI_WS0_B, + FN_DU0_DOTCLKOUT, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B, + FN_DU0_EXHSYNC_DU0_HSYNC, FN_HSPI_TX0_C, FN_SSI_SCK1_B, + FN_DU0_EXVSYNC_DU0_VSYNC, FN_HSPI_RX0_C, FN_SSI_WS1_B, + FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B, FN_SSI_SDATA1_B, + FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B, + FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B, + FN_IRQ0_A, FN_HSPI_TX_B, FN_RX3_E, FN_ET0_ERXD0, + FN_IRQ1_A, FN_HSPI_RX_B, FN_TX3_E, FN_ET0_ERXD1, + FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A, + FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A, + + /* IPSR9 */ + FN_VI1_CLK_A, FN_FD0_B, FN_LCD_DATA0_B, + FN_VI1_0_A, FN_FD1_B, FN_LCD_DATA1_B, + FN_VI1_1_A, FN_FD2_B, FN_LCD_DATA2_B, + FN_VI1_2_A, FN_FD3_B, FN_LCD_DATA3_B, + FN_VI1_3_A, FN_FD4_B, FN_LCD_DATA4_B, + FN_VI1_4_A, FN_FD5_B, FN_LCD_DATA5_B, + FN_VI1_5_A, FN_FD6_B, FN_LCD_DATA6_B, + FN_VI1_6_A, FN_FD7_B, FN_LCD_DATA7_B, + FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B, + FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B, + FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B, + FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B, + FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B, + FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B, + FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B, + + /* IPSR10 */ + FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B, FN_LCD_DATA15_B, + FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B, FN_LCD_DON_B, + FN_SSI_SDATA2, FN_VI1_6_B, FN_HRX0_C, FN_FRE_B, FN_LCD_CL1_B, + FN_SSI_SDATA3, FN_VI1_7_B, FN_HTX0_C, FN_FWE_B, FN_LCD_CL2_B, + FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B, FN_LCD_FLM_B, + FN_AUDIO_CLKB_A, FN_LCD_CLK_B, + FN_AUDIO_CLKC, FN_SCK1_E, FN_HCTS0_C, FN_FRB_B, FN_LCD_VEPWC_B, + FN_AUDIO_CLKOUT, FN_TX1_E, FN_HRTS0_C, FN_FSE_B, FN_LCD_M_DISP_B, + FN_CAN_CLK_A, FN_RX4_D, + FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK, + FN_CAN1_RX_A, FN_IRQ1_B, + FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG, + FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT, + + /* IPSR11 */ + FN_SCL1, FN_SCIF_CLK_C, + FN_SDA1, FN_RX1_E, + FN_SDA0, FN_HIFEBL_A, + FN_SDSELF, FN_RTS1_E, + FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A, FN_ET0_ERXD4, + FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A, FN_ET0_ERXD5, + FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6, + FN_TX0_A, FN_HSPI_TX_A, + FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D, FN_IETX_B, + FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D, FN_IERX_B, + FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN, + FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER, + FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C, FN_ET0_TX_CLK_A, + FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A, + FN_PRESETOUT, FN_ST_CLKOUT, + + /* MOD_SEL1 */ + FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, + FN_SEL_RQSPI_0, FN_SEL_RQSPI_1, + FN_SEL_VIN1_0, FN_SEL_VIN1_1, + FN_SEL_HIF_0, FN_SEL_HIF_1, + FN_SEL_RSPI_0, FN_SEL_RSPI_1, + FN_SEL_LCDC_0, FN_SEL_LCDC_1, + FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2, + FN_SEL_ET0_0, FN_SEL_ET0_1, + FN_SEL_RMII_0, FN_SEL_RMII_1, + FN_SEL_TMU_0, FN_SEL_TMU_1, + FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2, + FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3, + FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1, + FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2, + FN_SEL_RCAN0_0, FN_SEL_RCAN0_1, + FN_SEL_SDHI2_0, FN_SEL_SDHI2_1, + FN_SEL_SDHI1_0, FN_SEL_SDHI1_1, + FN_SEL_SDHI0_0, FN_SEL_SDHI0_1, + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + FN_SEL_SSI0_0, FN_SEL_SSI0_1, + FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1, + FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1, + FN_SEL_FLCTL_0, FN_SEL_FLCTL_1, + FN_SEL_MMC_0, FN_SEL_MMC_1, + FN_SEL_INTC_0, FN_SEL_INTC_1, + + /* MOD_SEL2 */ + FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1, + FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1, + FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1, + FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2, + FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2, + FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1, + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, + FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, + FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, + FN_SEL_SCIF3_3, FN_SEL_SCIF3_4, + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, + FN_SEL_SCIF2_3, + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, + FN_SEL_SCIF1_3, FN_SEL_SCIF1_4, + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, + FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2, + + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + CLKOUT_MARK, BS_MARK, CS0_MARK, EX_CS0_MARK, RD_MARK, + WE0_MARK, WE1_MARK, + + SCL0_MARK, PENC0_MARK, USB_OVC0_MARK, + + IRQ2_B_MARK, IRQ3_B_MARK, + + /* IPSR0 */ + A15_MARK, ST0_VCO_CLKIN_MARK, LCD_DATA15_A_MARK, TIOC3D_C_MARK, + A14_MARK, LCD_DATA14_A_MARK, TIOC3C_C_MARK, + A13_MARK, LCD_DATA13_A_MARK, TIOC3B_C_MARK, + A12_MARK, LCD_DATA12_A_MARK, TIOC3A_C_MARK, + A11_MARK, ST0_D7_MARK, LCD_DATA11_A_MARK, TIOC2B_C_MARK, + A10_MARK, ST0_D6_MARK, LCD_DATA10_A_MARK, TIOC2A_C_MARK, + A9_MARK, ST0_D5_MARK, LCD_DATA9_A_MARK, TIOC1B_C_MARK, + A8_MARK, ST0_D4_MARK, LCD_DATA8_A_MARK, TIOC1A_C_MARK, + A7_MARK, ST0_D3_MARK, LCD_DATA7_A_MARK, TIOC0D_C_MARK, + A6_MARK, ST0_D2_MARK, LCD_DATA6_A_MARK, TIOC0C_C_MARK, + A5_MARK, ST0_D1_MARK, LCD_DATA5_A_MARK, TIOC0B_C_MARK, + A4_MARK, ST0_D0_MARK, LCD_DATA4_A_MARK, TIOC0A_C_MARK, + A3_MARK, ST0_VLD_MARK, LCD_DATA3_A_MARK, TCLKD_C_MARK, + A2_MARK, ST0_SYC_MARK, LCD_DATA2_A_MARK, TCLKC_C_MARK, + A1_MARK, ST0_REQ_MARK, LCD_DATA1_A_MARK, TCLKB_C_MARK, + A0_MARK, ST0_CLKIN_MARK, LCD_DATA0_A_MARK, TCLKA_C_MARK, + + /* IPSR1 */ + D3_MARK, SD0_DAT3_A_MARK, MMC_D3_A_MARK, ST1_D6_MARK, FD3_A_MARK, + D2_MARK, SD0_DAT2_A_MARK, MMC_D2_A_MARK, ST1_D5_MARK, FD2_A_MARK, + D1_MARK, SD0_DAT1_A_MARK, MMC_D1_A_MARK, ST1_D4_MARK, FD1_A_MARK, + D0_MARK, SD0_DAT0_A_MARK, MMC_D0_A_MARK, ST1_D3_MARK, FD0_A_MARK, + A25_MARK, TX2_D_MARK, ST1_D2_MARK, + A24_MARK, RX2_D_MARK, ST1_D1_MARK, + A23_MARK, ST1_D0_MARK, LCD_M_DISP_A_MARK, + A22_MARK, ST1_VLD_MARK, LCD_VEPWC_A_MARK, + A21_MARK, ST1_SYC_MARK, LCD_VCPWC_A_MARK, + A20_MARK, ST1_REQ_MARK, LCD_FLM_A_MARK, + A19_MARK, ST1_CLKIN_MARK, LCD_CLK_A_MARK, TIOC4D_C_MARK, + A18_MARK, ST1_PWM_MARK, LCD_CL2_A_MARK, TIOC4C_C_MARK, + A17_MARK, ST1_VCO_CLKIN_MARK, LCD_CL1_A_MARK, TIOC4B_C_MARK, + A16_MARK, ST0_PWM_MARK, LCD_DON_A_MARK, TIOC4A_C_MARK, + + /* IPSR2 */ + D14_MARK, TX2_B_MARK, FSE_A_MARK, ET0_TX_CLK_B_MARK, + D13_MARK, RX2_B_MARK, FRB_A_MARK, ET0_ETXD6_B_MARK, + D12_MARK, FWE_A_MARK, ET0_ETXD5_B_MARK, + D11_MARK, RSPI_MISO_A_MARK, QMI_QIO1_A_MARK, FRE_A_MARK, + ET0_ETXD3_B_MARK, + D10_MARK, RSPI_MOSI_A_MARK, QMO_QIO0_A_MARK, FALE_A_MARK, + ET0_ETXD2_B_MARK, + D9_MARK, SD0_CMD_A_MARK, MMC_CMD_A_MARK, QIO3_A_MARK, + FCLE_A_MARK, ET0_ETXD1_B_MARK, + D8_MARK, SD0_CLK_A_MARK, MMC_CLK_A_MARK, QIO2_A_MARK, + FCE_A_MARK, ET0_GTX_CLK_B_MARK, + D7_MARK, RSPI_SSL_A_MARK, MMC_D7_A_MARK, QSSL_A_MARK, + FD7_A_MARK, + D6_MARK, RSPI_RSPCK_A_MARK, MMC_D6_A_MARK, QSPCLK_A_MARK, + FD6_A_MARK, + D5_MARK, SD0_WP_A_MARK, MMC_D5_A_MARK, FD5_A_MARK, + D4_MARK, SD0_CD_A_MARK, MMC_D4_A_MARK, ST1_D7_MARK, + FD4_A_MARK, + + /* IPSR3 */ + DRACK0_MARK, SD1_DAT2_A_MARK, ATAG_MARK, TCLK1_A_MARK, ET0_ETXD7_MARK, + EX_WAIT2_MARK, SD1_DAT1_A_MARK, DACK2_MARK, CAN1_RX_C_MARK, + ET0_MAGIC_C_MARK, ET0_ETXD6_A_MARK, + EX_WAIT1_MARK, SD1_DAT0_A_MARK, DREQ2_MARK, CAN1_TX_C_MARK, + ET0_LINK_C_MARK, ET0_ETXD5_A_MARK, + EX_WAIT0_MARK, TCLK1_B_MARK, + RD_WR_MARK, TCLK0_MARK, CAN_CLK_B_MARK, ET0_ETXD4_MARK, + EX_CS5_MARK, SD1_CMD_A_MARK, ATADIR_MARK, QSSL_B_MARK, + ET0_ETXD3_A_MARK, + EX_CS4_MARK, SD1_WP_A_MARK, ATAWR_MARK, QMI_QIO1_B_MARK, + ET0_ETXD2_A_MARK, + EX_CS3_MARK, SD1_CD_A_MARK, ATARD_MARK, QMO_QIO0_B_MARK, + ET0_ETXD1_A_MARK, + EX_CS2_MARK, TX3_B_MARK, ATACS1_MARK, QSPCLK_B_MARK, + ET0_GTX_CLK_A_MARK, + EX_CS1_MARK, RX3_B_MARK, ATACS0_MARK, QIO2_B_MARK, + ET0_ETXD0_MARK, + CS1_A26_MARK, QIO3_B_MARK, + D15_MARK, SCK2_B_MARK, + + /* IPSR4 */ + SCK2_A_MARK, VI0_G3_MARK, + RTS1_B_MARK, VI0_G2_MARK, + CTS1_B_MARK, VI0_DATA7_VI0_G1_MARK, + TX1_B_MARK, VI0_DATA6_VI0_G0_MARK, ET0_PHY_INT_A_MARK, + RX1_B_MARK, VI0_DATA5_VI0_B5_MARK, ET0_MAGIC_A_MARK, + SCK1_B_MARK, VI0_DATA4_VI0_B4_MARK, ET0_LINK_A_MARK, + RTS0_B_MARK, VI0_DATA3_VI0_B3_MARK, ET0_MDIO_A_MARK, + CTS0_B_MARK, VI0_DATA2_VI0_B2_MARK, RMII0_MDIO_A_MARK, + ET0_MDC_MARK, + HTX0_A_MARK, TX1_A_MARK, VI0_DATA1_VI0_B1_MARK, + RMII0_MDC_A_MARK, ET0_COL_MARK, + HRX0_A_MARK, RX1_A_MARK, VI0_DATA0_VI0_B0_MARK, + RMII0_CRS_DV_A_MARK, ET0_CRS_MARK, + HSCK0_A_MARK, SCK1_A_MARK, VI0_VSYNC_MARK, + RMII0_RX_ER_A_MARK, ET0_RX_ER_MARK, + HRTS0_A_MARK, RTS1_A_MARK, VI0_HSYNC_MARK, + RMII0_TXD_EN_A_MARK, ET0_RX_DV_MARK, + HCTS0_A_MARK, CTS1_A_MARK, VI0_FIELD_MARK, + RMII0_RXD1_A_MARK, ET0_ERXD7_MARK, + + /* IPSR5 */ + SD2_CLK_A_MARK, RX2_A_MARK, VI0_G4_MARK, ET0_RX_CLK_B_MARK, + SD2_CMD_A_MARK, TX2_A_MARK, VI0_G5_MARK, ET0_ERXD2_B_MARK, + SD2_DAT0_A_MARK, RX3_A_MARK, VI0_R0_MARK, ET0_ERXD3_B_MARK, + SD2_DAT1_A_MARK, TX3_A_MARK, VI0_R1_MARK, ET0_MDIO_B_MARK, + SD2_DAT2_A_MARK, RX4_A_MARK, VI0_R2_MARK, ET0_LINK_B_MARK, + SD2_DAT3_A_MARK, TX4_A_MARK, VI0_R3_MARK, ET0_MAGIC_B_MARK, + SD2_CD_A_MARK, RX5_A_MARK, VI0_R4_MARK, ET0_PHY_INT_B_MARK, + SD2_WP_A_MARK, TX5_A_MARK, VI0_R5_MARK, + REF125CK_MARK, ADTRG_MARK, RX5_C_MARK, + REF50CK_MARK, CTS1_E_MARK, HCTS0_D_MARK, + + /* IPSR6 */ + DU0_DR0_MARK, SCIF_CLK_B_MARK, HRX0_D_MARK, IETX_A_MARK, + TCLKA_A_MARK, HIFD00_MARK, + DU0_DR1_MARK, SCK0_B_MARK, HTX0_D_MARK, IERX_A_MARK, + TCLKB_A_MARK, HIFD01_MARK, + DU0_DR2_MARK, RX0_B_MARK, TCLKC_A_MARK, HIFD02_MARK, + DU0_DR3_MARK, TX0_B_MARK, TCLKD_A_MARK, HIFD03_MARK, + DU0_DR4_MARK, CTS0_C_MARK, TIOC0A_A_MARK, HIFD04_MARK, + DU0_DR5_MARK, RTS0_C_MARK, TIOC0B_A_MARK, HIFD05_MARK, + DU0_DR6_MARK, SCK1_C_MARK, TIOC0C_A_MARK, HIFD06_MARK, + DU0_DR7_MARK, RX1_C_MARK, TIOC0D_A_MARK, HIFD07_MARK, + DU0_DG0_MARK, TX1_C_MARK, HSCK0_D_MARK, IECLK_A_MARK, + TIOC1A_A_MARK, HIFD08_MARK, + DU0_DG1_MARK, CTS1_C_MARK, HRTS0_D_MARK, TIOC1B_A_MARK, + HIFD09_MARK, + + /* IPSR7 */ + DU0_DG2_MARK, RTS1_C_MARK, RMII0_MDC_B_MARK, TIOC2A_A_MARK, + HIFD10_MARK, + DU0_DG3_MARK, SCK2_C_MARK, RMII0_MDIO_B_MARK, TIOC2B_A_MARK, + HIFD11_MARK, + DU0_DG4_MARK, RX2_C_MARK, RMII0_CRS_DV_B_MARK, TIOC3A_A_MARK, + HIFD12_MARK, + DU0_DG5_MARK, TX2_C_MARK, RMII0_RX_ER_B_MARK, TIOC3B_A_MARK, + HIFD13_MARK, + DU0_DG6_MARK, RX3_C_MARK, RMII0_RXD0_B_MARK, TIOC3C_A_MARK, + HIFD14_MARK, + DU0_DG7_MARK, TX3_C_MARK, RMII0_RXD1_B_MARK, TIOC3D_A_MARK, + HIFD15_MARK, + DU0_DB0_MARK, RX4_C_MARK, RMII0_TXD_EN_B_MARK, TIOC4A_A_MARK, + HIFCS_MARK, + DU0_DB1_MARK, TX4_C_MARK, RMII0_TXD0_B_MARK, TIOC4B_A_MARK, + HIFRS_MARK, + DU0_DB2_MARK, RX5_B_MARK, RMII0_TXD1_B_MARK, TIOC4C_A_MARK, + HIFWR_MARK, + DU0_DB3_MARK, TX5_B_MARK, TIOC4D_A_MARK, HIFRD_MARK, + DU0_DB4_MARK, HIFINT_MARK, + + /* IPSR8 */ + DU0_DB5_MARK, HIFDREQ_MARK, + DU0_DB6_MARK, HIFRDY_MARK, + DU0_DB7_MARK, SSI_SCK0_B_MARK, HIFEBL_B_MARK, + DU0_DOTCLKIN_MARK, HSPI_CS0_C_MARK, SSI_WS0_B_MARK, + DU0_DOTCLKOUT_MARK, HSPI_CLK0_C_MARK, SSI_SDATA0_B_MARK, + DU0_EXHSYNC_DU0_HSYNC_MARK, HSPI_TX0_C_MARK, SSI_SCK1_B_MARK, + DU0_EXVSYNC_DU0_VSYNC_MARK, HSPI_RX0_C_MARK, SSI_WS1_B_MARK, + DU0_EXODDF_DU0_ODDF_MARK, CAN0_RX_B_MARK, HSCK0_B_MARK, + SSI_SDATA1_B_MARK, + DU0_DISP_MARK, CAN0_TX_B_MARK, HRX0_B_MARK, AUDIO_CLKA_B_MARK, + DU0_CDE_MARK, HTX0_B_MARK, AUDIO_CLKB_B_MARK, LCD_VCPWC_B_MARK, + IRQ0_A_MARK, HSPI_TX_B_MARK, RX3_E_MARK, ET0_ERXD0_MARK, + IRQ1_A_MARK, HSPI_RX_B_MARK, TX3_E_MARK, ET0_ERXD1_MARK, + IRQ2_A_MARK, CTS0_A_MARK, HCTS0_B_MARK, ET0_ERXD2_A_MARK, + IRQ3_A_MARK, RTS0_A_MARK, HRTS0_B_MARK, ET0_ERXD3_A_MARK, + + /* IPSR9 */ + VI1_CLK_A_MARK, FD0_B_MARK, LCD_DATA0_B_MARK, + VI1_0_A_MARK, FD1_B_MARK, LCD_DATA1_B_MARK, + VI1_1_A_MARK, FD2_B_MARK, LCD_DATA2_B_MARK, + VI1_2_A_MARK, FD3_B_MARK, LCD_DATA3_B_MARK, + VI1_3_A_MARK, FD4_B_MARK, LCD_DATA4_B_MARK, + VI1_4_A_MARK, FD5_B_MARK, LCD_DATA5_B_MARK, + VI1_5_A_MARK, FD6_B_MARK, LCD_DATA6_B_MARK, + VI1_6_A_MARK, FD7_B_MARK, LCD_DATA7_B_MARK, + VI1_7_A_MARK, FCE_B_MARK, LCD_DATA8_B_MARK, + SSI_SCK0_A_MARK, TIOC1A_B_MARK, LCD_DATA9_B_MARK, + SSI_WS0_A_MARK, TIOC1B_B_MARK, LCD_DATA10_B_MARK, + SSI_SDATA0_A_MARK, VI1_0_B_MARK, TIOC2A_B_MARK, LCD_DATA11_B_MARK, + SSI_SCK1_A_MARK, VI1_1_B_MARK, TIOC2B_B_MARK, LCD_DATA12_B_MARK, + SSI_WS1_A_MARK, VI1_2_B_MARK, LCD_DATA13_B_MARK, + SSI_SDATA1_A_MARK, VI1_3_B_MARK, LCD_DATA14_B_MARK, + + /* IPSR10 */ + SSI_SCK23_MARK, VI1_4_B_MARK, RX1_D_MARK, FCLE_B_MARK, + LCD_DATA15_B_MARK, + SSI_WS23_MARK, VI1_5_B_MARK, TX1_D_MARK, HSCK0_C_MARK, + FALE_B_MARK, LCD_DON_B_MARK, + SSI_SDATA2_MARK, VI1_6_B_MARK, HRX0_C_MARK, FRE_B_MARK, + LCD_CL1_B_MARK, + SSI_SDATA3_MARK, VI1_7_B_MARK, HTX0_C_MARK, FWE_B_MARK, + LCD_CL2_B_MARK, + AUDIO_CLKA_A_MARK, VI1_CLK_B_MARK, SCK1_D_MARK, IECLK_B_MARK, + LCD_FLM_B_MARK, + AUDIO_CLKB_A_MARK, LCD_CLK_B_MARK, + AUDIO_CLKC_MARK, SCK1_E_MARK, HCTS0_C_MARK, FRB_B_MARK, + LCD_VEPWC_B_MARK, + AUDIO_CLKOUT_MARK, TX1_E_MARK, HRTS0_C_MARK, FSE_B_MARK, + LCD_M_DISP_B_MARK, + CAN_CLK_A_MARK, RX4_D_MARK, + CAN0_TX_A_MARK, TX4_D_MARK, MLB_CLK_MARK, + CAN1_RX_A_MARK, IRQ1_B_MARK, + CAN0_RX_A_MARK, IRQ0_B_MARK, MLB_SIG_MARK, + CAN1_TX_A_MARK, TX5_C_MARK, MLB_DAT_MARK, + + /* IPSR11 */ + SCL1_MARK, SCIF_CLK_C_MARK, + SDA1_MARK, RX1_E_MARK, + SDA0_MARK, HIFEBL_A_MARK, + SDSELF_MARK, RTS1_E_MARK, + SCIF_CLK_A_MARK, HSPI_CLK_A_MARK, VI0_CLK_MARK, RMII0_TXD0_A_MARK, + ET0_ERXD4_MARK, + SCK0_A_MARK, HSPI_CS_A_MARK, VI0_CLKENB_MARK, RMII0_TXD1_A_MARK, + ET0_ERXD5_MARK, + RX0_A_MARK, HSPI_RX_A_MARK, RMII0_RXD0_A_MARK, ET0_ERXD6_MARK, + TX0_A_MARK, HSPI_TX_A_MARK, + PENC1_MARK, TX3_D_MARK, CAN1_TX_B_MARK, TX5_D_MARK, + IETX_B_MARK, + USB_OVC1_MARK, RX3_D_MARK, CAN1_RX_B_MARK, RX5_D_MARK, + IERX_B_MARK, + DREQ0_MARK, SD1_CLK_A_MARK, ET0_TX_EN_MARK, + DACK0_MARK, SD1_DAT3_A_MARK, ET0_TX_ER_MARK, + DREQ1_MARK, HSPI_CLK_B_MARK, RX4_B_MARK, ET0_PHY_INT_C_MARK, + ET0_TX_CLK_A_MARK, + DACK1_MARK, HSPI_CS_B_MARK, TX4_B_MARK, ET0_RX_CLK_A_MARK, + PRESETOUT_MARK, ST_CLKOUT_MARK, + + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT), + PINMUX_DATA(BS_MARK, FN_BS), PINMUX_DATA(CS0_MARK, FN_CS0), + PINMUX_DATA(EX_CS0_MARK, FN_EX_CS0), + PINMUX_DATA(RD_MARK, FN_RD), PINMUX_DATA(WE0_MARK, FN_WE0), + PINMUX_DATA(WE1_MARK, FN_WE1), + PINMUX_DATA(SCL0_MARK, FN_SCL0), PINMUX_DATA(PENC0_MARK, FN_PENC0), + PINMUX_DATA(USB_OVC0_MARK, FN_USB_OVC0), + PINMUX_DATA(IRQ2_B_MARK, FN_IRQ2_B), + PINMUX_DATA(IRQ3_B_MARK, FN_IRQ3_B), + + /* IPSR0 */ + PINMUX_IPSR_DATA(IP0_1_0, A0), + PINMUX_IPSR_DATA(IP0_1_0, ST0_CLKIN), + PINMUX_IPSR_MODSEL_DATA(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1), + + PINMUX_IPSR_DATA(IP0_3_2, A1), + PINMUX_IPSR_DATA(IP0_3_2, ST0_REQ), + PINMUX_IPSR_MODSEL_DATA(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1), + + PINMUX_IPSR_DATA(IP0_5_4, A2), + PINMUX_IPSR_DATA(IP0_5_4, ST0_SYC), + PINMUX_IPSR_MODSEL_DATA(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1), + + PINMUX_IPSR_DATA(IP0_7_6, A3), + PINMUX_IPSR_DATA(IP0_7_6, ST0_VLD), + PINMUX_IPSR_MODSEL_DATA(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1), + + PINMUX_IPSR_DATA(IP0_9_8, A4), + PINMUX_IPSR_DATA(IP0_9_8, ST0_D0), + PINMUX_IPSR_MODSEL_DATA(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1), + + PINMUX_IPSR_DATA(IP0_11_10, A5), + PINMUX_IPSR_DATA(IP0_11_10, ST0_D1), + PINMUX_IPSR_MODSEL_DATA(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1), + + PINMUX_IPSR_DATA(IP0_13_12, A6), + PINMUX_IPSR_DATA(IP0_13_12, ST0_D2), + PINMUX_IPSR_MODSEL_DATA(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1), + + PINMUX_IPSR_DATA(IP0_15_14, A7), + PINMUX_IPSR_DATA(IP0_15_14, ST0_D3), + PINMUX_IPSR_MODSEL_DATA(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1), + + PINMUX_IPSR_DATA(IP0_17_16, A8), + PINMUX_IPSR_DATA(IP0_17_16, ST0_D4), + PINMUX_IPSR_MODSEL_DATA(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2), + + PINMUX_IPSR_DATA(IP0_19_18, A9), + PINMUX_IPSR_DATA(IP0_19_18, ST0_D5), + PINMUX_IPSR_MODSEL_DATA(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2), + + PINMUX_IPSR_DATA(IP0_21_20, A10), + PINMUX_IPSR_DATA(IP0_21_20, ST0_D6), + PINMUX_IPSR_MODSEL_DATA(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2), + + PINMUX_IPSR_DATA(IP0_23_22, A11), + PINMUX_IPSR_DATA(IP0_23_22, ST0_D7), + PINMUX_IPSR_MODSEL_DATA(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2), + + PINMUX_IPSR_DATA(IP0_25_24, A12), + PINMUX_IPSR_MODSEL_DATA(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1), + + PINMUX_IPSR_DATA(IP0_27_26, A13), + PINMUX_IPSR_MODSEL_DATA(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1), + + PINMUX_IPSR_DATA(IP0_29_28, A14), + PINMUX_IPSR_MODSEL_DATA(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1), + + PINMUX_IPSR_DATA(IP0_31_30, A15), + PINMUX_IPSR_DATA(IP0_31_30, ST0_VCO_CLKIN), + PINMUX_IPSR_MODSEL_DATA(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1), + + + /* IPSR1 */ + PINMUX_IPSR_DATA(IP1_1_0, A16), + PINMUX_IPSR_DATA(IP1_1_0, ST0_PWM), + PINMUX_IPSR_MODSEL_DATA(IP1_1_0, LCD_DON_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1), + + PINMUX_IPSR_DATA(IP1_3_2, A17), + PINMUX_IPSR_DATA(IP1_3_2, ST1_VCO_CLKIN), + PINMUX_IPSR_MODSEL_DATA(IP1_3_2, LCD_CL1_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1), + + PINMUX_IPSR_DATA(IP1_5_4, A18), + PINMUX_IPSR_DATA(IP1_5_4, ST1_PWM), + PINMUX_IPSR_MODSEL_DATA(IP1_5_4, LCD_CL2_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1), + + PINMUX_IPSR_DATA(IP1_7_6, A19), + PINMUX_IPSR_DATA(IP1_7_6, ST1_CLKIN), + PINMUX_IPSR_MODSEL_DATA(IP1_7_6, LCD_CLK_A, SEL_LCDC_0), + PINMUX_IPSR_MODSEL_DATA(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1), + + PINMUX_IPSR_DATA(IP1_9_8, A20), + PINMUX_IPSR_DATA(IP1_9_8, ST1_REQ), + PINMUX_IPSR_MODSEL_DATA(IP1_9_8, LCD_FLM_A, SEL_LCDC_0), + + PINMUX_IPSR_DATA(IP1_11_10, A21), + PINMUX_IPSR_DATA(IP1_11_10, ST1_SYC), + PINMUX_IPSR_MODSEL_DATA(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0), + + PINMUX_IPSR_DATA(IP1_13_12, A22), + PINMUX_IPSR_DATA(IP1_13_12, ST1_VLD), + PINMUX_IPSR_MODSEL_DATA(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0), + + PINMUX_IPSR_DATA(IP1_15_14, A23), + PINMUX_IPSR_DATA(IP1_15_14, ST1_D0), + PINMUX_IPSR_MODSEL_DATA(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0), + + PINMUX_IPSR_DATA(IP1_17_16, A24), + PINMUX_IPSR_MODSEL_DATA(IP1_17_16, RX2_D, SEL_SCIF2_3), + PINMUX_IPSR_DATA(IP1_17_16, ST1_D1), + + PINMUX_IPSR_DATA(IP1_19_18, A25), + PINMUX_IPSR_MODSEL_DATA(IP1_17_16, RX2_D, SEL_SCIF2_3), + PINMUX_IPSR_DATA(IP1_17_16, ST1_D2), + + PINMUX_IPSR_DATA(IP1_22_20, D0), + PINMUX_IPSR_MODSEL_DATA(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_22_20, MMC_D0_A, SEL_MMC_0), + PINMUX_IPSR_DATA(IP1_22_20, ST1_D3), + PINMUX_IPSR_MODSEL_DATA(IP1_22_20, FD0_A, SEL_FLCTL_0), + + PINMUX_IPSR_DATA(IP1_25_23, D1), + PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_25_23, MMC_D1_A, SEL_MMC_0), + PINMUX_IPSR_DATA(IP1_25_23, ST1_D4), + PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FD1_A, SEL_FLCTL_0), + + PINMUX_IPSR_DATA(IP1_28_26, D2), + PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_28_26, MMC_D2_A, SEL_MMC_0), + PINMUX_IPSR_DATA(IP1_28_26, ST1_D5), + PINMUX_IPSR_MODSEL_DATA(IP1_28_26, FD2_A, SEL_FLCTL_0), + + PINMUX_IPSR_DATA(IP1_31_29, D3), + PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_31_29, MMC_D3_A, SEL_MMC_0), + PINMUX_IPSR_DATA(IP1_31_29, ST1_D6), + PINMUX_IPSR_MODSEL_DATA(IP1_31_29, FD3_A, SEL_FLCTL_0), + + /* IPSR2 */ + PINMUX_IPSR_DATA(IP2_2_0, D4), + PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SD0_CD_A, SEL_SDHI0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MMC_D4_A, SEL_MMC_0), + PINMUX_IPSR_DATA(IP2_2_0, ST1_D7), + PINMUX_IPSR_MODSEL_DATA(IP2_2_0, FD4_A, SEL_FLCTL_0), + + PINMUX_IPSR_DATA(IP2_4_3, D5), + PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SD0_WP_A, SEL_SDHI0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_4_3, MMC_D5_A, SEL_MMC_0), + PINMUX_IPSR_MODSEL_DATA(IP2_4_3, FD5_A, SEL_FLCTL_0), + + PINMUX_IPSR_DATA(IP2_7_5, D6), + PINMUX_IPSR_MODSEL_DATA(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0), + PINMUX_IPSR_MODSEL_DATA(IP2_7_5, MMC_D6_A, SEL_MMC_0), + PINMUX_IPSR_MODSEL_DATA(IP2_7_5, QSPCLK_A, SEL_RQSPI_0), + PINMUX_IPSR_MODSEL_DATA(IP2_7_5, FD6_A, SEL_FLCTL_0), + + PINMUX_IPSR_DATA(IP2_10_8, D7), + PINMUX_IPSR_MODSEL_DATA(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0), + PINMUX_IPSR_MODSEL_DATA(IP2_10_8, MMC_D7_A, SEL_MMC_0), + PINMUX_IPSR_MODSEL_DATA(IP2_10_8, QSSL_A, SEL_RQSPI_0), + PINMUX_IPSR_MODSEL_DATA(IP2_10_8, FD7_A, SEL_FLCTL_0), + + PINMUX_IPSR_DATA(IP2_13_11, D8), + PINMUX_IPSR_MODSEL_DATA(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_13_11, MMC_CLK_A, SEL_MMC_0), + PINMUX_IPSR_MODSEL_DATA(IP2_13_11, QIO2_A, SEL_RQSPI_0), + PINMUX_IPSR_MODSEL_DATA(IP2_13_11, FCE_A, SEL_FLCTL_0), + PINMUX_IPSR_MODSEL_DATA(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1), + + PINMUX_IPSR_DATA(IP2_16_14, D9), + PINMUX_IPSR_MODSEL_DATA(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_16_14, MMC_CMD_A, SEL_MMC_0), + PINMUX_IPSR_MODSEL_DATA(IP2_16_14, QIO3_A, SEL_RQSPI_0), + PINMUX_IPSR_MODSEL_DATA(IP2_16_14, FCLE_A, SEL_FLCTL_0), + PINMUX_IPSR_MODSEL_DATA(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1), + + PINMUX_IPSR_DATA(IP2_19_17, D10), + PINMUX_IPSR_MODSEL_DATA(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0), + PINMUX_IPSR_MODSEL_DATA(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0), + PINMUX_IPSR_MODSEL_DATA(IP2_19_17, FALE_A, SEL_FLCTL_0), + PINMUX_IPSR_MODSEL_DATA(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1), + + PINMUX_IPSR_DATA(IP2_22_20, D11), + PINMUX_IPSR_MODSEL_DATA(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0), + PINMUX_IPSR_MODSEL_DATA(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0), + PINMUX_IPSR_MODSEL_DATA(IP2_22_20, FRE_A, SEL_FLCTL_0), + + PINMUX_IPSR_DATA(IP2_24_23, D12), + PINMUX_IPSR_MODSEL_DATA(IP2_24_23, FWE_A, SEL_FLCTL_0), + PINMUX_IPSR_MODSEL_DATA(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1), + + PINMUX_IPSR_DATA(IP2_27_25, D13), + PINMUX_IPSR_MODSEL_DATA(IP2_27_25, RX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MODSEL_DATA(IP2_27_25, FRB_A, SEL_FLCTL_0), + PINMUX_IPSR_MODSEL_DATA(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1), + + PINMUX_IPSR_DATA(IP2_30_28, D14), + PINMUX_IPSR_MODSEL_DATA(IP2_30_28, TX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MODSEL_DATA(IP2_30_28, FSE_A, SEL_FLCTL_0), + PINMUX_IPSR_MODSEL_DATA(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1), + + /* IPSR3 */ + PINMUX_IPSR_DATA(IP3_1_0, D15), + PINMUX_IPSR_MODSEL_DATA(IP3_1_0, SCK2_B, SEL_SCIF2_1), + + PINMUX_IPSR_DATA(IP3_2, CS1_A26), + PINMUX_IPSR_MODSEL_DATA(IP3_2, QIO3_B, SEL_RQSPI_1), + + PINMUX_IPSR_DATA(IP3_5_3, EX_CS1), + PINMUX_IPSR_MODSEL_DATA(IP3_5_3, RX3_B, SEL_SCIF2_1), + PINMUX_IPSR_DATA(IP3_5_3, ATACS0), + PINMUX_IPSR_MODSEL_DATA(IP3_5_3, QIO2_B, SEL_RQSPI_1), + PINMUX_IPSR_DATA(IP3_5_3, ET0_ETXD0), + + PINMUX_IPSR_DATA(IP3_8_6, EX_CS2), + PINMUX_IPSR_MODSEL_DATA(IP3_8_6, TX3_B, SEL_SCIF3_1), + PINMUX_IPSR_DATA(IP3_8_6, ATACS1), + PINMUX_IPSR_MODSEL_DATA(IP3_8_6, QSPCLK_B, SEL_RQSPI_1), + PINMUX_IPSR_MODSEL_DATA(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0), + + PINMUX_IPSR_DATA(IP3_11_9, EX_CS3), + PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SD1_CD_A, SEL_SDHI1_0), + PINMUX_IPSR_DATA(IP3_11_9, ATARD), + PINMUX_IPSR_MODSEL_DATA(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1), + PINMUX_IPSR_MODSEL_DATA(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0), + + PINMUX_IPSR_DATA(IP3_14_12, EX_CS4), + PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SD1_WP_A, SEL_SDHI1_0), + PINMUX_IPSR_DATA(IP3_14_12, ATAWR), + PINMUX_IPSR_MODSEL_DATA(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1), + PINMUX_IPSR_MODSEL_DATA(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0), + + PINMUX_IPSR_DATA(IP3_17_15, EX_CS5), + PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0), + PINMUX_IPSR_DATA(IP3_17_15, ATADIR), + PINMUX_IPSR_MODSEL_DATA(IP3_17_15, QSSL_B, SEL_RQSPI_1), + PINMUX_IPSR_MODSEL_DATA(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0), + + PINMUX_IPSR_DATA(IP3_19_18, RD_WR), + PINMUX_IPSR_DATA(IP3_19_18, TCLK0), + PINMUX_IPSR_MODSEL_DATA(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1), + PINMUX_IPSR_DATA(IP3_19_18, ET0_ETXD4), + + PINMUX_IPSR_DATA(IP3_20, EX_WAIT0), + PINMUX_IPSR_MODSEL_DATA(IP3_20, TCLK1_B, SEL_TMU_1), + + PINMUX_IPSR_DATA(IP3_23_21, EX_WAIT1), + PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0), + PINMUX_IPSR_DATA(IP3_23_21, DREQ2), + PINMUX_IPSR_MODSEL_DATA(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2), + PINMUX_IPSR_MODSEL_DATA(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2), + PINMUX_IPSR_MODSEL_DATA(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0), + + PINMUX_IPSR_DATA(IP3_26_24, EX_WAIT2), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0), + PINMUX_IPSR_DATA(IP3_26_24, DACK2), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0), + + PINMUX_IPSR_DATA(IP3_29_27, DRACK0), + PINMUX_IPSR_MODSEL_DATA(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0), + PINMUX_IPSR_DATA(IP3_29_27, ATAG), + PINMUX_IPSR_MODSEL_DATA(IP3_29_27, TCLK1_A, SEL_TMU_0), + PINMUX_IPSR_DATA(IP3_29_27, ET0_ETXD7), + + /* IPSR4 */ + PINMUX_IPSR_MODSEL_DATA(IP4_2_0, HCTS0_A, SEL_HSCIF_0), + PINMUX_IPSR_MODSEL_DATA(IP4_2_0, CTS1_A, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP4_2_0, VI0_FIELD), + PINMUX_IPSR_MODSEL_DATA(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0), + PINMUX_IPSR_DATA(IP4_2_0, ET0_ERXD7), + + PINMUX_IPSR_MODSEL_DATA(IP4_5_3, HRTS0_A, SEL_HSCIF_0), + PINMUX_IPSR_MODSEL_DATA(IP4_5_3, RTS1_A, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP4_5_3, VI0_HSYNC), + PINMUX_IPSR_MODSEL_DATA(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0), + PINMUX_IPSR_DATA(IP4_5_3, ET0_RX_DV), + + PINMUX_IPSR_MODSEL_DATA(IP4_8_6, HSCK0_A, SEL_HSCIF_0), + PINMUX_IPSR_MODSEL_DATA(IP4_8_6, SCK1_A, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP4_8_6, VI0_VSYNC), + PINMUX_IPSR_MODSEL_DATA(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0), + PINMUX_IPSR_DATA(IP4_8_6, ET0_RX_ER), + + PINMUX_IPSR_MODSEL_DATA(IP4_11_9, HRX0_A, SEL_HSCIF_0), + PINMUX_IPSR_MODSEL_DATA(IP4_11_9, RX1_A, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP4_11_9, VI0_DATA0_VI0_B0), + PINMUX_IPSR_MODSEL_DATA(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0), + PINMUX_IPSR_DATA(IP4_11_9, ET0_CRS), + + PINMUX_IPSR_MODSEL_DATA(IP4_14_12, HTX0_A, SEL_HSCIF_0), + PINMUX_IPSR_MODSEL_DATA(IP4_14_12, TX1_A, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP4_14_12, VI0_DATA1_VI0_B1), + PINMUX_IPSR_MODSEL_DATA(IP4_14_12, RMII0_MDC_A, SEL_RMII_0), + PINMUX_IPSR_DATA(IP4_14_12, ET0_COL), + + PINMUX_IPSR_MODSEL_DATA(IP4_17_15, CTS0_B, SEL_SCIF0_1), + PINMUX_IPSR_DATA(IP4_17_15, VI0_DATA2_VI0_B2), + PINMUX_IPSR_MODSEL_DATA(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0), + PINMUX_IPSR_DATA(IP4_17_15, ET0_MDC), + + PINMUX_IPSR_MODSEL_DATA(IP4_19_18, RTS0_B, SEL_SCIF0_1), + PINMUX_IPSR_DATA(IP4_19_18, VI0_DATA3_VI0_B3), + PINMUX_IPSR_MODSEL_DATA(IP4_19_18, ET0_MDIO_A, SEL_ET0_0), + + PINMUX_IPSR_MODSEL_DATA(IP4_21_20, SCK1_B, SEL_SCIF1_1), + PINMUX_IPSR_DATA(IP4_21_20, VI0_DATA4_VI0_B4), + PINMUX_IPSR_MODSEL_DATA(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0), + + PINMUX_IPSR_MODSEL_DATA(IP4_23_22, RX1_B, SEL_SCIF1_1), + PINMUX_IPSR_DATA(IP4_23_22, VI0_DATA5_VI0_B5), + PINMUX_IPSR_MODSEL_DATA(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0), + + PINMUX_IPSR_MODSEL_DATA(IP4_25_24, TX1_B, SEL_SCIF1_1), + PINMUX_IPSR_DATA(IP4_25_24, VI0_DATA6_VI0_G0), + PINMUX_IPSR_MODSEL_DATA(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0), + + PINMUX_IPSR_MODSEL_DATA(IP4_27_26, CTS1_B, SEL_SCIF1_1), + PINMUX_IPSR_DATA(IP4_27_26, VI0_DATA7_VI0_G1), + + PINMUX_IPSR_MODSEL_DATA(IP4_29_28, RTS1_B, SEL_SCIF1_1), + PINMUX_IPSR_DATA(IP4_29_28, VI0_G2), + + PINMUX_IPSR_MODSEL_DATA(IP4_31_30, SCK2_A, SEL_SCIF2_0), + PINMUX_IPSR_DATA(IP4_31_30, VI0_G3), + + /* IPSR5 */ + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0), + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX2_A, SEL_SCIF2_0), + PINMUX_IPSR_DATA(IP5_2_0, VI0_G4), + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1), + + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TX2_A, SEL_SCIF2_0), + PINMUX_IPSR_DATA(IP5_5_3, VI0_G5), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1), + + PINMUX_IPSR_MODSEL_DATA(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0), + PINMUX_IPSR_MODSEL_DATA(IP5_8_6, RX3_A, SEL_SCIF3_0), + PINMUX_IPSR_DATA(IP4_8_6, VI0_R0), + PINMUX_IPSR_MODSEL_DATA(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1), + + PINMUX_IPSR_MODSEL_DATA(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0), + PINMUX_IPSR_MODSEL_DATA(IP5_11_9, TX3_A, SEL_SCIF3_0), + PINMUX_IPSR_DATA(IP5_11_9, VI0_R1), + PINMUX_IPSR_MODSEL_DATA(IP5_11_9, ET0_MDIO_B, SEL_ET0_1), + + PINMUX_IPSR_MODSEL_DATA(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0), + PINMUX_IPSR_MODSEL_DATA(IP5_14_12, RX4_A, SEL_SCIF4_0), + PINMUX_IPSR_DATA(IP5_14_12, VI0_R2), + PINMUX_IPSR_MODSEL_DATA(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1), + + PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0), + PINMUX_IPSR_MODSEL_DATA(IP5_17_15, TX4_A, SEL_SCIF4_0), + PINMUX_IPSR_DATA(IP5_17_15, VI0_R3), + PINMUX_IPSR_MODSEL_DATA(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1), + + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SD2_CD_A, SEL_SDHI2_0), + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, RX5_A, SEL_SCIF5_0), + PINMUX_IPSR_DATA(IP5_20_18, VI0_R4), + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1), + + PINMUX_IPSR_MODSEL_DATA(IP5_22_21, SD2_WP_A, SEL_SDHI2_0), + PINMUX_IPSR_MODSEL_DATA(IP5_22_21, TX5_A, SEL_SCIF5_0), + PINMUX_IPSR_DATA(IP5_22_21, VI0_R5), + + PINMUX_IPSR_DATA(IP5_24_23, REF125CK), + PINMUX_IPSR_DATA(IP5_24_23, ADTRG), + PINMUX_IPSR_MODSEL_DATA(IP5_24_23, RX5_C, SEL_SCIF5_2), + PINMUX_IPSR_DATA(IP5_26_25, REF50CK), + PINMUX_IPSR_MODSEL_DATA(IP5_26_25, CTS1_E, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP5_26_25, HCTS0_D, SEL_HSCIF_3), + + /* IPSR6 */ + PINMUX_IPSR_DATA(IP6_2_0, DU0_DR0), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, HRX0_D, SEL_HSCIF_3), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, IETX_A, SEL_IEBUS_0), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0), + PINMUX_IPSR_DATA(IP6_2_0, HIFD00), + + PINMUX_IPSR_DATA(IP6_5_3, DU0_DR1), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCK0_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, HTX0_D, SEL_HSCIF_3), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, IERX_A, SEL_IEBUS_0), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0), + PINMUX_IPSR_DATA(IP6_5_3, HIFD01), + + PINMUX_IPSR_DATA(IP6_7_6, DU0_DR2), + PINMUX_IPSR_MODSEL_DATA(IP6_7_6, RX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0), + PINMUX_IPSR_DATA(IP6_7_6, HIFD02), + + PINMUX_IPSR_DATA(IP6_9_8, DU0_DR3), + PINMUX_IPSR_MODSEL_DATA(IP6_9_8, TX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0), + PINMUX_IPSR_DATA(IP6_9_8, HIFD03), + + PINMUX_IPSR_DATA(IP6_11_10, DU0_DR4), + PINMUX_IPSR_MODSEL_DATA(IP6_11_10, CTS0_C, SEL_SCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0), + PINMUX_IPSR_DATA(IP6_11_10, HIFD04), + + PINMUX_IPSR_DATA(IP6_13_12, DU0_DR5), + PINMUX_IPSR_MODSEL_DATA(IP6_13_12, RTS0_C, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0), + PINMUX_IPSR_DATA(IP6_13_12, HIFD05), + + PINMUX_IPSR_DATA(IP6_15_14, DU0_DR6), + PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCK1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0), + PINMUX_IPSR_DATA(IP6_15_14, HIFD06), + + PINMUX_IPSR_DATA(IP6_17_16, DU0_DR7), + PINMUX_IPSR_MODSEL_DATA(IP6_17_16, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0), + PINMUX_IPSR_DATA(IP6_17_16, HIFD07), + + PINMUX_IPSR_DATA(IP6_20_18, DU0_DG0), + PINMUX_IPSR_MODSEL_DATA(IP6_20_18, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_20_18, HSCK0_D, SEL_HSCIF_3), + PINMUX_IPSR_MODSEL_DATA(IP6_20_18, IECLK_A, SEL_IEBUS_0), + PINMUX_IPSR_MODSEL_DATA(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0), + PINMUX_IPSR_DATA(IP6_20_18, HIFD08), + + PINMUX_IPSR_DATA(IP6_23_21, DU0_DG1), + PINMUX_IPSR_MODSEL_DATA(IP6_23_21, CTS1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HRTS0_D, SEL_HSCIF_3), + PINMUX_IPSR_MODSEL_DATA(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0), + PINMUX_IPSR_DATA(IP6_23_21, HIFD09), + + /* IPSR7 */ + PINMUX_IPSR_DATA(IP7_2_0, DU0_DG2), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, RTS1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, RMII0_MDC_B, SEL_RMII_1), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0), + PINMUX_IPSR_DATA(IP7_2_0, HIFD10), + + PINMUX_IPSR_DATA(IP7_5_3, DU0_DG3), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCK2_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0), + PINMUX_IPSR_DATA(IP7_5_3, HIFD11), + + PINMUX_IPSR_DATA(IP7_8_6, DU0_DG4), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX2_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0), + PINMUX_IPSR_DATA(IP7_8_6, HIFD12), + + PINMUX_IPSR_DATA(IP7_11_9, DU0_DG5), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, TX2_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0), + PINMUX_IPSR_DATA(IP7_11_9, HIFD13), + + PINMUX_IPSR_DATA(IP7_14_12, DU0_DG6), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, RX3_C, SEL_SCIF3_2), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0), + PINMUX_IPSR_DATA(IP7_14_12, HIFD14), + + PINMUX_IPSR_DATA(IP7_17_15, DU0_DG7), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, TX3_C, SEL_SCIF3_2), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0), + PINMUX_IPSR_DATA(IP7_17_15, HIFD15), + + PINMUX_IPSR_DATA(IP7_20_18, DU0_DB0), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, RX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0), + PINMUX_IPSR_DATA(IP7_20_18, HIFCS), + + PINMUX_IPSR_DATA(IP7_23_21, DU0_DB1), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0), + PINMUX_IPSR_DATA(IP7_23_21, HIFWR), + + PINMUX_IPSR_DATA(IP7_26_24, DU0_DB2), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0), + + PINMUX_IPSR_DATA(IP7_28_27, DU0_DB3), + PINMUX_IPSR_MODSEL_DATA(IP7_28_27, TX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MODSEL_DATA(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0), + PINMUX_IPSR_DATA(IP7_28_27, HIFRD), + + PINMUX_IPSR_DATA(IP7_30_29, DU0_DB4), + PINMUX_IPSR_DATA(IP7_30_29, HIFINT), + + /* IPSR8 */ + PINMUX_IPSR_DATA(IP8_1_0, DU0_DB5), + PINMUX_IPSR_DATA(IP8_1_0, HIFDREQ), + + PINMUX_IPSR_DATA(IP8_3_2, DU0_DB6), + PINMUX_IPSR_DATA(IP8_3_2, HIFRDY), + + PINMUX_IPSR_DATA(IP8_5_4, DU0_DB7), + PINMUX_IPSR_MODSEL_DATA(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1), + PINMUX_IPSR_MODSEL_DATA(IP8_5_4, HIFEBL_B, SEL_HIF_1), + + PINMUX_IPSR_DATA(IP8_7_6, DU0_DOTCLKIN), + PINMUX_IPSR_MODSEL_DATA(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2), + PINMUX_IPSR_MODSEL_DATA(IP8_7_6, SSI_WS0_B, SEL_SSI0_1), + + PINMUX_IPSR_DATA(IP8_9_8, DU0_DOTCLKOUT), + PINMUX_IPSR_MODSEL_DATA(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2), + PINMUX_IPSR_MODSEL_DATA(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1), + + PINMUX_IPSR_DATA(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC), + PINMUX_IPSR_MODSEL_DATA(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2), + PINMUX_IPSR_MODSEL_DATA(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1), + + PINMUX_IPSR_DATA(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC), + PINMUX_IPSR_MODSEL_DATA(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2), + PINMUX_IPSR_MODSEL_DATA(IP8_13_12, SSI_WS1_B, SEL_SSI1_1), + + PINMUX_IPSR_DATA(IP8_15_14, DU0_EXODDF_DU0_ODDF), + PINMUX_IPSR_MODSEL_DATA(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1), + PINMUX_IPSR_MODSEL_DATA(IP8_15_14, HSCK0_B, SEL_HSCIF_1), + PINMUX_IPSR_MODSEL_DATA(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1), + + PINMUX_IPSR_DATA(IP8_17_16, DU0_DISP), + PINMUX_IPSR_MODSEL_DATA(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1), + PINMUX_IPSR_MODSEL_DATA(IP8_17_16, HRX0_B, SEL_HSCIF_1), + PINMUX_IPSR_MODSEL_DATA(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1), + + PINMUX_IPSR_DATA(IP8_19_18, DU0_CDE), + PINMUX_IPSR_MODSEL_DATA(IP8_19_18, HTX0_B, SEL_HSCIF_1), + PINMUX_IPSR_MODSEL_DATA(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1), + PINMUX_IPSR_MODSEL_DATA(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, IRQ0_A, SEL_INTC_0), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, HSPI_TX_B, SEL_HSPI_1), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, RX3_E, SEL_SCIF3_4), + PINMUX_IPSR_DATA(IP8_22_20, ET0_ERXD0), + + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, IRQ1_A, SEL_INTC_0), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, HSPI_RX_B, SEL_HSPI_1), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TX3_E, SEL_SCIF3_4), + PINMUX_IPSR_DATA(IP8_25_23, ET0_ERXD1), + + PINMUX_IPSR_MODSEL_DATA(IP8_27_26, IRQ2_A, SEL_INTC_0), + PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CTS0_A, SEL_SCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP8_27_26, HCTS0_B, SEL_HSCIF_1), + PINMUX_IPSR_MODSEL_DATA(IP8_27_26, ET0_ERXD2_A, SEL_ET0_0), + + PINMUX_IPSR_MODSEL_DATA(IP8_29_28, IRQ3_A, SEL_INTC_0), + PINMUX_IPSR_MODSEL_DATA(IP8_29_28, RTS0_A, SEL_SCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP8_29_28, HRTS0_B, SEL_HSCIF_1), + PINMUX_IPSR_MODSEL_DATA(IP8_29_28, ET0_ERXD3_A, SEL_ET0_0), + + /* IPSR9 */ + PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_CLK_A, SEL_VIN1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_1_0, FD0_B, SEL_FLCTL_1), + PINMUX_IPSR_MODSEL_DATA(IP9_1_0, LCD_DATA0_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_0_A, SEL_VIN1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_3_2, FD1_B, SEL_FLCTL_1), + PINMUX_IPSR_MODSEL_DATA(IP9_3_2, LCD_DATA1_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_1_A, SEL_VIN1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_5_4, FD2_B, SEL_FLCTL_1), + PINMUX_IPSR_MODSEL_DATA(IP9_5_4, LCD_DATA2_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_2_A, SEL_VIN1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_7_6, FD3_B, SEL_FLCTL_1), + PINMUX_IPSR_MODSEL_DATA(IP9_7_6, LCD_DATA3_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP9_9_8, VI1_3_A, SEL_VIN1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_9_8, FD4_B, SEL_FLCTL_1), + PINMUX_IPSR_MODSEL_DATA(IP9_9_8, LCD_DATA4_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP9_11_10, VI1_4_A, SEL_VIN1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_11_10, FD5_B, SEL_FLCTL_1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_10, LCD_DATA5_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP9_13_12, VI1_5_A, SEL_VIN1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_13_12, FD6_B, SEL_FLCTL_1), + PINMUX_IPSR_MODSEL_DATA(IP9_13_12, LCD_DATA6_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP9_15_14, VI1_6_A, SEL_VIN1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_15_14, FD7_B, SEL_FLCTL_1), + PINMUX_IPSR_MODSEL_DATA(IP9_15_14, LCD_DATA7_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP9_17_16, VI1_7_A, SEL_VIN1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_17_16, FCE_B, SEL_FLCTL_1), + PINMUX_IPSR_MODSEL_DATA(IP9_17_16, LCD_DATA8_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SSI_SCK0_A, SEL_SSI0_0), + PINMUX_IPSR_MODSEL_DATA(IP9_19_18, TIOC1A_B, SEL_MTU2_CH1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_19_18, LCD_DATA9_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SSI_WS0_A, SEL_SSI0_0), + PINMUX_IPSR_MODSEL_DATA(IP9_21_20, TIOC1B_B, SEL_MTU2_CH1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_21_20, LCD_DATA10_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SSI_SDATA0_A, SEL_SSI0_0), + PINMUX_IPSR_MODSEL_DATA(IP9_23_22, VI1_0_B, SEL_VIN1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_23_22, TIOC2A_B, SEL_MTU2_CH2_1), + PINMUX_IPSR_MODSEL_DATA(IP9_23_22, LCD_DATA11_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SSI_SCK1_A, SEL_SSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_25_24, VI1_1_B, SEL_VIN1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_25_24, TIOC2B_B, SEL_MTU2_CH2_1), + PINMUX_IPSR_MODSEL_DATA(IP9_25_24, LCD_DATA12_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SSI_WS1_A, SEL_SSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_27_26, VI1_2_B, SEL_VIN1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_27_26, LCD_DATA13_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SSI_SDATA1_A, SEL_SSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_29_28, VI1_3_B, SEL_VIN1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1), + + /* IPSE10 */ + PINMUX_IPSR_DATA(IP10_2_0, SSI_SCK23), + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, VI1_4_B, SEL_VIN1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, RX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, FCLE_B, SEL_FLCTL_1), + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1), + + PINMUX_IPSR_DATA(IP10_5_3, SSI_WS23), + PINMUX_IPSR_MODSEL_DATA(IP10_5_3, VI1_5_B, SEL_VIN1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_5_3, TX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK0_C, SEL_HSCIF_2), + PINMUX_IPSR_MODSEL_DATA(IP10_5_3, FALE_B, SEL_FLCTL_1), + PINMUX_IPSR_MODSEL_DATA(IP10_5_3, LCD_DON_B, SEL_LCDC_1), + + PINMUX_IPSR_DATA(IP10_8_6, SSI_SDATA2), + PINMUX_IPSR_MODSEL_DATA(IP10_8_6, VI1_6_B, SEL_VIN1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX0_C, SEL_HSCIF_2), + PINMUX_IPSR_MODSEL_DATA(IP10_8_6, FRE_B, SEL_FLCTL_1), + PINMUX_IPSR_MODSEL_DATA(IP10_8_6, LCD_CL1_B, SEL_LCDC_1), + + PINMUX_IPSR_DATA(IP10_11_9, SSI_SDATA3), + PINMUX_IPSR_MODSEL_DATA(IP10_11_9, VI1_7_B, SEL_VIN1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX0_C, SEL_HSCIF_2), + PINMUX_IPSR_MODSEL_DATA(IP10_11_9, FWE_B, SEL_FLCTL_1), + PINMUX_IPSR_MODSEL_DATA(IP10_11_9, LCD_CL2_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP10_14_12, AUDIO_CLKA_A, SEL_AUDIO_CLKA_0), + PINMUX_IPSR_MODSEL_DATA(IP10_14_12, VI1_CLK_B, SEL_VIN1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCK1_D, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP10_14_12, IECLK_B, SEL_IEBUS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_14_12, LCD_FLM_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0), + PINMUX_IPSR_MODSEL_DATA(IP10_15, LCD_CLK_B, SEL_LCDC_1), + + PINMUX_IPSR_DATA(IP10_18_16, AUDIO_CLKC), + PINMUX_IPSR_MODSEL_DATA(IP10_18_16, SCK1_E, SEL_SCIF1_4), + PINMUX_IPSR_MODSEL_DATA(IP10_18_16, HCTS0_C, SEL_HSCIF_2), + PINMUX_IPSR_MODSEL_DATA(IP10_18_16, FRB_B, SEL_FLCTL_1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1), + + PINMUX_IPSR_DATA(IP10_21_19, AUDIO_CLKOUT), + PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TX1_E, SEL_SCIF1_4), + PINMUX_IPSR_MODSEL_DATA(IP10_21_19, HRTS0_C, SEL_HSCIF_2), + PINMUX_IPSR_MODSEL_DATA(IP10_21_19, FSE_B, SEL_FLCTL_1), + PINMUX_IPSR_MODSEL_DATA(IP10_21_19, LCD_M_DISP_B, SEL_LCDC_1), + + PINMUX_IPSR_MODSEL_DATA(IP10_22, CAN_CLK_A, SEL_RCAN_CLK_0), + PINMUX_IPSR_MODSEL_DATA(IP10_22, RX4_D, SEL_SCIF4_3), + + PINMUX_IPSR_MODSEL_DATA(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0), + PINMUX_IPSR_MODSEL_DATA(IP10_24_23, TX4_D, SEL_SCIF4_3), + PINMUX_IPSR_DATA(IP10_24_23, MLB_CLK), + + PINMUX_IPSR_MODSEL_DATA(IP10_25, CAN1_RX_A, SEL_RCAN1_0), + PINMUX_IPSR_MODSEL_DATA(IP10_25, IRQ1_B, SEL_INTC_1), + + PINMUX_IPSR_MODSEL_DATA(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0), + PINMUX_IPSR_MODSEL_DATA(IP10_27_26, IRQ0_B, SEL_INTC_1), + PINMUX_IPSR_DATA(IP10_27_26, MLB_SIG), + + PINMUX_IPSR_MODSEL_DATA(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0), + PINMUX_IPSR_MODSEL_DATA(IP10_29_28, TX5_C, SEL_SCIF1_2), + PINMUX_IPSR_DATA(IP10_29_28, MLB_DAT), + + /* IPSR11 */ + PINMUX_IPSR_DATA(IP11_0, SCL1), + PINMUX_IPSR_MODSEL_DATA(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2), + + PINMUX_IPSR_DATA(IP11_1, SDA1), + PINMUX_IPSR_MODSEL_DATA(IP11_0, RX1_E, SEL_SCIF1_4), + + PINMUX_IPSR_DATA(IP11_2, SDA0), + PINMUX_IPSR_MODSEL_DATA(IP11_2, HIFEBL_A, SEL_HIF_0), + + PINMUX_IPSR_DATA(IP11_3, SDSELF), + PINMUX_IPSR_MODSEL_DATA(IP11_3, RTS1_E, SEL_SCIF1_3), + + PINMUX_IPSR_MODSEL_DATA(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0), + PINMUX_IPSR_MODSEL_DATA(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0), + PINMUX_IPSR_DATA(IP11_6_4, VI0_CLK), + PINMUX_IPSR_MODSEL_DATA(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0), + PINMUX_IPSR_DATA(IP11_6_4, ET0_ERXD4), + + PINMUX_IPSR_MODSEL_DATA(IP11_9_7, SCK0_A, SEL_SCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP11_9_7, HSPI_CS_A, SEL_HSPI_0), + PINMUX_IPSR_DATA(IP11_9_7, VI0_CLKENB), + PINMUX_IPSR_MODSEL_DATA(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0), + PINMUX_IPSR_DATA(IP11_9_7, ET0_ERXD5), + + PINMUX_IPSR_MODSEL_DATA(IP11_11_10, RX0_A, SEL_SCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP11_11_10, HSPI_RX_A, SEL_HSPI_0), + PINMUX_IPSR_MODSEL_DATA(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0), + PINMUX_IPSR_DATA(IP11_11_10, ET0_ERXD6), + + PINMUX_IPSR_MODSEL_DATA(IP11_12, TX0_A, SEL_SCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP11_12, HSPI_TX_A, SEL_HSPI_0), + + PINMUX_IPSR_DATA(IP11_15_13, PENC1), + PINMUX_IPSR_MODSEL_DATA(IP11_15_13, TX3_D, SEL_SCIF3_3), + PINMUX_IPSR_MODSEL_DATA(IP11_15_13, CAN1_TX_B, SEL_RCAN1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_15_13, TX5_D, SEL_SCIF5_3), + PINMUX_IPSR_MODSEL_DATA(IP11_15_13, IETX_B, SEL_IEBUS_1), + + PINMUX_IPSR_DATA(IP11_18_16, USB_OVC1), + PINMUX_IPSR_MODSEL_DATA(IP11_18_16, RX3_D, SEL_SCIF3_3), + PINMUX_IPSR_MODSEL_DATA(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_18_16, RX5_D, SEL_SCIF5_3), + PINMUX_IPSR_MODSEL_DATA(IP11_18_16, IERX_B, SEL_IEBUS_1), + + PINMUX_IPSR_DATA(IP11_20_19, DREQ0), + PINMUX_IPSR_MODSEL_DATA(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0), + PINMUX_IPSR_DATA(IP11_20_19, ET0_TX_EN), + + PINMUX_IPSR_DATA(IP11_22_21, DACK0), + PINMUX_IPSR_MODSEL_DATA(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0), + PINMUX_IPSR_DATA(IP11_22_21, ET0_TX_ER), + + PINMUX_IPSR_DATA(IP11_25_23, DREQ1), + PINMUX_IPSR_MODSEL_DATA(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1), + PINMUX_IPSR_MODSEL_DATA(IP11_25_23, RX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0), + PINMUX_IPSR_MODSEL_DATA(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0), + + PINMUX_IPSR_DATA(IP11_27_26, DACK1), + PINMUX_IPSR_MODSEL_DATA(IP11_27_26, HSPI_CS_B, SEL_HSPI_1), + PINMUX_IPSR_MODSEL_DATA(IP11_27_26, TX4_B, SEL_SCIF3_1), + PINMUX_IPSR_MODSEL_DATA(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0), + + PINMUX_IPSR_DATA(IP11_28, PRESETOUT), + PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT), +}; + +static struct pinmux_gpio pinmux_gpios[] = { + PINMUX_GPIO_GP_ALL(), + + GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0), + GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1), + GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0), + GPIO_FN(IRQ2_B), GPIO_FN(IRQ3_B), + + /* IPSR0 */ + GPIO_FN(A0), GPIO_FN(ST0_CLKIN), GPIO_FN(LCD_DATA0_A), + GPIO_FN(TCLKA_C), + GPIO_FN(A1), GPIO_FN(ST0_REQ), GPIO_FN(LCD_DATA1_A), + GPIO_FN(TCLKB_C), + GPIO_FN(A2), GPIO_FN(ST0_SYC), GPIO_FN(LCD_DATA2_A), + GPIO_FN(TCLKC_C), + GPIO_FN(A3), GPIO_FN(ST0_VLD), GPIO_FN(LCD_DATA3_A), + GPIO_FN(TCLKD_C), + GPIO_FN(A4), GPIO_FN(ST0_D0), GPIO_FN(LCD_DATA4_A), + GPIO_FN(TIOC0A_C), + GPIO_FN(A5), GPIO_FN(ST0_D1), GPIO_FN(LCD_DATA5_A), + GPIO_FN(TIOC0B_C), + GPIO_FN(A6), GPIO_FN(ST0_D2), GPIO_FN(LCD_DATA6_A), + GPIO_FN(TIOC0C_C), + GPIO_FN(A7), GPIO_FN(ST0_D3), GPIO_FN(LCD_DATA7_A), + GPIO_FN(TIOC0D_C), + GPIO_FN(A8), GPIO_FN(ST0_D4), GPIO_FN(LCD_DATA8_A), + GPIO_FN(TIOC1A_C), + GPIO_FN(A9), GPIO_FN(ST0_D5), GPIO_FN(LCD_DATA9_A), + GPIO_FN(TIOC1B_C), + GPIO_FN(A10), GPIO_FN(ST0_D6), GPIO_FN(LCD_DATA10_A), + GPIO_FN(TIOC2A_C), + GPIO_FN(A11), GPIO_FN(ST0_D7), GPIO_FN(LCD_DATA11_A), + GPIO_FN(TIOC2B_C), + GPIO_FN(A12), GPIO_FN(LCD_DATA12_A), GPIO_FN(TIOC3A_C), + GPIO_FN(A13), GPIO_FN(LCD_DATA13_A), GPIO_FN(TIOC3B_C), + GPIO_FN(A14), GPIO_FN(LCD_DATA14_A), GPIO_FN(TIOC3C_C), + GPIO_FN(A15), GPIO_FN(ST0_VCO_CLKIN), GPIO_FN(LCD_DATA15_A), + GPIO_FN(TIOC3D_C), + + /* IPSR1 */ + GPIO_FN(A16), GPIO_FN(ST0_PWM), GPIO_FN(LCD_DON_A), + GPIO_FN(TIOC4A_C), + GPIO_FN(A17), GPIO_FN(ST1_VCO_CLKIN), GPIO_FN(LCD_CL1_A), + GPIO_FN(TIOC4B_C), + GPIO_FN(A18), GPIO_FN(ST1_PWM), GPIO_FN(LCD_CL2_A), + GPIO_FN(TIOC4C_C), + GPIO_FN(A19), GPIO_FN(ST1_CLKIN), GPIO_FN(LCD_CLK_A), + GPIO_FN(TIOC4D_C), + GPIO_FN(A20), GPIO_FN(ST1_REQ), GPIO_FN(LCD_FLM_A), + GPIO_FN(A21), GPIO_FN(ST1_SYC), GPIO_FN(LCD_VCPWC_A), + GPIO_FN(A22), GPIO_FN(ST1_VLD), GPIO_FN(LCD_VEPWC_A), + GPIO_FN(A23), GPIO_FN(ST1_D0), GPIO_FN(LCD_M_DISP_A), + GPIO_FN(A24), GPIO_FN(RX2_D), GPIO_FN(ST1_D1), + GPIO_FN(A25), GPIO_FN(TX2_D), GPIO_FN(ST1_D2), + GPIO_FN(D0), GPIO_FN(SD0_DAT0_A), GPIO_FN(MMC_D0_A), + GPIO_FN(ST1_D3), GPIO_FN(FD0_A), + GPIO_FN(D1), GPIO_FN(SD0_DAT1_A), GPIO_FN(MMC_D1_A), + GPIO_FN(ST1_D4), GPIO_FN(FD1_A), + GPIO_FN(D2), GPIO_FN(SD0_DAT2_A), GPIO_FN(MMC_D2_A), + GPIO_FN(ST1_D5), GPIO_FN(FD2_A), + GPIO_FN(D3), GPIO_FN(SD0_DAT3_A), GPIO_FN(MMC_D3_A), + GPIO_FN(ST1_D6), GPIO_FN(FD3_A), + + /* IPSR2 */ + GPIO_FN(D4), GPIO_FN(SD0_CD_A), GPIO_FN(MMC_D4_A), GPIO_FN(ST1_D7), + GPIO_FN(FD4_A), + GPIO_FN(D5), GPIO_FN(SD0_WP_A), GPIO_FN(MMC_D5_A), GPIO_FN(FD5_A), + GPIO_FN(D6), GPIO_FN(RSPI_RSPCK_A), GPIO_FN(MMC_D6_A), + GPIO_FN(QSPCLK_A), + GPIO_FN(FD6_A), + GPIO_FN(D7), GPIO_FN(RSPI_SSL_A), GPIO_FN(MMC_D7_A), GPIO_FN(QSSL_A), + GPIO_FN(FD7_A), + GPIO_FN(D8), GPIO_FN(SD0_CLK_A), GPIO_FN(MMC_CLK_A), GPIO_FN(QIO2_A), + GPIO_FN(FCE_A), GPIO_FN(ET0_GTX_CLK_B), + GPIO_FN(D9), GPIO_FN(SD0_CMD_A), GPIO_FN(MMC_CMD_A), GPIO_FN(QIO3_A), + GPIO_FN(FCLE_A), GPIO_FN(ET0_ETXD1_B), + GPIO_FN(D10), GPIO_FN(RSPI_MOSI_A), GPIO_FN(QMO_QIO0_A), + GPIO_FN(FALE_A), GPIO_FN(ET0_ETXD2_B), + GPIO_FN(D11), GPIO_FN(RSPI_MISO_A), GPIO_FN(QMI_QIO1_A), GPIO_FN(FRE_A), + GPIO_FN(ET0_ETXD3_B), + GPIO_FN(D12), GPIO_FN(FWE_A), GPIO_FN(ET0_ETXD5_B), + GPIO_FN(D13), GPIO_FN(RX2_B), GPIO_FN(FRB_A), GPIO_FN(ET0_ETXD6_B), + GPIO_FN(D14), GPIO_FN(TX2_B), GPIO_FN(FSE_A), GPIO_FN(ET0_TX_CLK_B), + + /* IPSR3 */ + GPIO_FN(D15), GPIO_FN(SCK2_B), + GPIO_FN(CS1_A26), GPIO_FN(QIO3_B), + GPIO_FN(EX_CS1), GPIO_FN(RX3_B), GPIO_FN(ATACS0), GPIO_FN(QIO2_B), + GPIO_FN(ET0_ETXD0), + GPIO_FN(EX_CS2), GPIO_FN(TX3_B), GPIO_FN(ATACS1), GPIO_FN(QSPCLK_B), + GPIO_FN(ET0_GTX_CLK_A), + GPIO_FN(EX_CS3), GPIO_FN(SD1_CD_A), GPIO_FN(ATARD), GPIO_FN(QMO_QIO0_B), + GPIO_FN(ET0_ETXD1_A), + GPIO_FN(EX_CS4), GPIO_FN(SD1_WP_A), GPIO_FN(ATAWR), GPIO_FN(QMI_QIO1_B), + GPIO_FN(ET0_ETXD2_A), + GPIO_FN(EX_CS5), GPIO_FN(SD1_CMD_A), GPIO_FN(ATADIR), GPIO_FN(QSSL_B), + GPIO_FN(ET0_ETXD3_A), + GPIO_FN(RD_WR), GPIO_FN(TCLK1_B), + GPIO_FN(EX_WAIT0), GPIO_FN(TCLK1_B), + GPIO_FN(EX_WAIT1), GPIO_FN(SD1_DAT0_A), GPIO_FN(DREQ2), + GPIO_FN(CAN1_TX_C), GPIO_FN(ET0_LINK_C), GPIO_FN(ET0_ETXD5_A), + GPIO_FN(EX_WAIT2), GPIO_FN(SD1_DAT1_A), GPIO_FN(DACK2), + GPIO_FN(CAN1_RX_C), GPIO_FN(ET0_MAGIC_C), GPIO_FN(ET0_ETXD6_A), + GPIO_FN(DRACK0), GPIO_FN(SD1_DAT2_A), GPIO_FN(ATAG), GPIO_FN(TCLK1_A), + GPIO_FN(ET0_ETXD7), + + /* IPSR4 */ + GPIO_FN(HCTS0_A), GPIO_FN(CTS1_A), GPIO_FN(VI0_FIELD), + GPIO_FN(RMII0_RXD1_A), GPIO_FN(ET0_ERXD7), + GPIO_FN(HRTS0_A), GPIO_FN(RTS1_A), GPIO_FN(VI0_HSYNC), + GPIO_FN(RMII0_TXD_EN_A), GPIO_FN(ET0_RX_DV), + GPIO_FN(HSCK0_A), GPIO_FN(SCK1_A), GPIO_FN(VI0_VSYNC), + GPIO_FN(RMII0_RX_ER_A), GPIO_FN(ET0_RX_ER), + GPIO_FN(HRX0_A), GPIO_FN(RX1_A), GPIO_FN(VI0_DATA0_VI0_B0), + GPIO_FN(RMII0_CRS_DV_A), GPIO_FN(ET0_CRS), + GPIO_FN(HTX0_A), GPIO_FN(TX1_A), GPIO_FN(VI0_DATA1_VI0_B1), + GPIO_FN(RMII0_MDC_A), GPIO_FN(ET0_COL), + GPIO_FN(CTS0_B), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(RMII0_MDIO_A), + GPIO_FN(ET0_MDC), + GPIO_FN(RTS0_B), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ET0_MDIO_A), + GPIO_FN(SCK1_B), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ET0_LINK_A), + GPIO_FN(RX1_B), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(ET0_MAGIC_A), + GPIO_FN(TX1_B), GPIO_FN(VI0_DATA6_VI0_G0), GPIO_FN(ET0_PHY_INT_A), + GPIO_FN(CTS1_B), GPIO_FN(VI0_DATA7_VI0_G1), + GPIO_FN(RTS1_B), GPIO_FN(VI0_G2), + GPIO_FN(SCK2_A), GPIO_FN(VI0_G3), + + /* IPSR5 */ + GPIO_FN(REF50CK), GPIO_FN(CTS1_E), GPIO_FN(HCTS0_D), + GPIO_FN(REF125CK), GPIO_FN(ADTRG), GPIO_FN(RX5_C), + GPIO_FN(SD2_WP_A), GPIO_FN(TX5_A), GPIO_FN(VI0_R5), + GPIO_FN(SD2_CD_A), GPIO_FN(RX5_A), GPIO_FN(VI0_R4), + GPIO_FN(ET0_PHY_INT_B), + GPIO_FN(SD2_DAT3_A), GPIO_FN(TX4_A), GPIO_FN(VI0_R3), + GPIO_FN(ET0_MAGIC_B), + GPIO_FN(SD2_DAT2_A), GPIO_FN(RX4_A), GPIO_FN(VI0_R2), + GPIO_FN(ET0_LINK_B), + GPIO_FN(SD2_DAT1_A), GPIO_FN(TX3_A), GPIO_FN(VI0_R1), + GPIO_FN(ET0_MDIO_B), + GPIO_FN(SD2_DAT0_A), GPIO_FN(RX3_A), GPIO_FN(VI0_R0), + GPIO_FN(ET0_ERXD3_B), + GPIO_FN(SD2_CMD_A), GPIO_FN(TX2_A), GPIO_FN(VI0_G5), + GPIO_FN(ET0_ERXD2_B), + GPIO_FN(SD2_CLK_A), GPIO_FN(RX2_A), GPIO_FN(VI0_G4), + GPIO_FN(ET0_RX_CLK_B), + + /* IPSR6 */ + GPIO_FN(DU0_DG1), GPIO_FN(CTS1_C), GPIO_FN(HRTS0_D), + GPIO_FN(TIOC1B_A), GPIO_FN(HIFD09), + GPIO_FN(DU0_DG0), GPIO_FN(TX1_C), GPIO_FN(HSCK0_D), + GPIO_FN(IECLK_A), GPIO_FN(TIOC1A_A), GPIO_FN(HIFD08), + GPIO_FN(DU0_DR7), GPIO_FN(RX1_C), GPIO_FN(TIOC0D_A), + GPIO_FN(HIFD07), + GPIO_FN(DU0_DR6), GPIO_FN(SCK1_C), GPIO_FN(TIOC0C_A), + GPIO_FN(HIFD06), + GPIO_FN(DU0_DR5), GPIO_FN(RTS0_C), GPIO_FN(TIOC0B_A), + GPIO_FN(HIFD05), + GPIO_FN(DU0_DR4), GPIO_FN(CTS0_C), GPIO_FN(TIOC0A_A), + GPIO_FN(HIFD04), + GPIO_FN(DU0_DR3), GPIO_FN(TX0_B), GPIO_FN(TCLKD_A), GPIO_FN(HIFD03), + GPIO_FN(DU0_DR2), GPIO_FN(RX0_B), GPIO_FN(TCLKC_A), GPIO_FN(HIFD02), + GPIO_FN(DU0_DR1), GPIO_FN(SCK0_B), GPIO_FN(HTX0_D), + GPIO_FN(IERX_A), GPIO_FN(TCLKB_A), GPIO_FN(HIFD01), + GPIO_FN(DU0_DR0), GPIO_FN(SCIF_CLK_B), GPIO_FN(HRX0_D), + GPIO_FN(IETX_A), GPIO_FN(TCLKA_A), GPIO_FN(HIFD00), + + /* IPSR7 */ + GPIO_FN(DU0_DB4), GPIO_FN(HIFINT), + GPIO_FN(DU0_DB3), GPIO_FN(TX5_B), GPIO_FN(TIOC4D_A), GPIO_FN(HIFRD), + GPIO_FN(DU0_DB2), GPIO_FN(RX5_B), GPIO_FN(RMII0_TXD1_B), + GPIO_FN(TIOC4C_A), GPIO_FN(HIFWR), + GPIO_FN(DU0_DB1), GPIO_FN(TX4_C), GPIO_FN(RMII0_TXD0_B), + GPIO_FN(TIOC4B_A), GPIO_FN(HIFRS), + GPIO_FN(DU0_DB0), GPIO_FN(RX4_C), GPIO_FN(RMII0_TXD_EN_B), + GPIO_FN(TIOC4A_A), GPIO_FN(HIFCS), + GPIO_FN(DU0_DG7), GPIO_FN(TX3_C), GPIO_FN(RMII0_RXD1_B), + GPIO_FN(TIOC3D_A), GPIO_FN(HIFD15), + GPIO_FN(DU0_DG6), GPIO_FN(RX3_C), GPIO_FN(RMII0_RXD0_B), + GPIO_FN(TIOC3C_A), GPIO_FN(HIFD14), + GPIO_FN(DU0_DG5), GPIO_FN(TX2_C), GPIO_FN(RMII0_RX_ER_B), + GPIO_FN(TIOC3B_A), GPIO_FN(HIFD13), + GPIO_FN(DU0_DG4), GPIO_FN(RX2_C), GPIO_FN(RMII0_CRS_DV_B), + GPIO_FN(TIOC3A_A), GPIO_FN(HIFD12), + GPIO_FN(DU0_DG3), GPIO_FN(SCK2_C), GPIO_FN(RMII0_MDIO_B), + GPIO_FN(TIOC2B_A), GPIO_FN(HIFD11), + GPIO_FN(DU0_DG2), GPIO_FN(RTS1_C), GPIO_FN(RMII0_MDC_B), + GPIO_FN(TIOC2A_A), GPIO_FN(HIFD10), + + /* IPSR8 */ + GPIO_FN(IRQ3_A), GPIO_FN(RTS0_A), GPIO_FN(HRTS0_B), + GPIO_FN(ET0_ERXD3_A), + GPIO_FN(IRQ2_A), GPIO_FN(CTS0_A), GPIO_FN(HCTS0_B), + GPIO_FN(ET0_ERXD2_A), + GPIO_FN(IRQ1_A), GPIO_FN(HSPI_RX_B), GPIO_FN(TX3_E), + GPIO_FN(ET0_ERXD1), + GPIO_FN(IRQ0_A), GPIO_FN(HSPI_TX_B), GPIO_FN(RX3_E), + GPIO_FN(ET0_ERXD0), + GPIO_FN(DU0_CDE), GPIO_FN(HTX0_B), GPIO_FN(AUDIO_CLKB_B), + GPIO_FN(LCD_VCPWC_B), + GPIO_FN(DU0_DISP), GPIO_FN(CAN0_TX_B), GPIO_FN(HRX0_B), + GPIO_FN(AUDIO_CLKA_B), + GPIO_FN(DU0_EXODDF_DU0_ODDF), GPIO_FN(CAN0_RX_B), GPIO_FN(HSCK0_B), + GPIO_FN(SSI_SDATA1_B), + GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(HSPI_RX0_C), + GPIO_FN(SSI_WS1_B), + GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(HSPI_TX0_C), + GPIO_FN(SSI_SCK1_B), + GPIO_FN(DU0_DOTCLKOUT), GPIO_FN(HSPI_CLK0_C), + GPIO_FN(SSI_SDATA0_B), + GPIO_FN(DU0_DOTCLKIN), GPIO_FN(HSPI_CS0_C), + GPIO_FN(SSI_WS0_B), + GPIO_FN(DU0_DB7), GPIO_FN(SSI_SCK0_B), GPIO_FN(HIFEBL_B), + GPIO_FN(DU0_DB6), GPIO_FN(HIFRDY), + GPIO_FN(DU0_DB5), GPIO_FN(HIFDREQ), + + /* IPSR9 */ + GPIO_FN(SSI_SDATA1_A), GPIO_FN(VI1_3_B), GPIO_FN(LCD_DATA14_B), + GPIO_FN(SSI_WS1_A), GPIO_FN(VI1_2_B), GPIO_FN(LCD_DATA13_B), + GPIO_FN(SSI_SCK1_A), GPIO_FN(VI1_1_B), GPIO_FN(TIOC2B_B), + GPIO_FN(LCD_DATA12_B), + GPIO_FN(SSI_SDATA0_A), GPIO_FN(VI1_0_B), GPIO_FN(TIOC2A_B), + GPIO_FN(LCD_DATA11_B), + GPIO_FN(SSI_WS0_A), GPIO_FN(TIOC1B_B), GPIO_FN(LCD_DATA10_B), + GPIO_FN(SSI_SCK0_A), GPIO_FN(TIOC1A_B), GPIO_FN(LCD_DATA9_B), + GPIO_FN(VI1_7_A), GPIO_FN(FCE_B), GPIO_FN(LCD_DATA8_B), + GPIO_FN(VI1_6_A), GPIO_FN(FD7_B), GPIO_FN(LCD_DATA7_B), + GPIO_FN(VI1_5_A), GPIO_FN(FD6_B), GPIO_FN(LCD_DATA6_B), + GPIO_FN(VI1_4_A), GPIO_FN(FD5_B), GPIO_FN(LCD_DATA5_B), + GPIO_FN(VI1_3_A), GPIO_FN(FD4_B), GPIO_FN(LCD_DATA4_B), + GPIO_FN(VI1_2_A), GPIO_FN(FD3_B), GPIO_FN(LCD_DATA3_B), + GPIO_FN(VI1_1_A), GPIO_FN(FD2_B), GPIO_FN(LCD_DATA2_B), + GPIO_FN(VI1_0_A), GPIO_FN(FD1_B), GPIO_FN(LCD_DATA1_B), + GPIO_FN(VI1_CLK_A), GPIO_FN(FD0_B), GPIO_FN(LCD_DATA0_B), + + /* IPSR10 */ + GPIO_FN(CAN1_TX_A), GPIO_FN(TX5_C), GPIO_FN(MLB_DAT), + GPIO_FN(CAN0_RX_A), GPIO_FN(IRQ0_B), GPIO_FN(MLB_SIG), + GPIO_FN(CAN1_RX_A), GPIO_FN(IRQ1_B), + GPIO_FN(CAN0_TX_A), GPIO_FN(TX4_D), GPIO_FN(MLB_CLK), + GPIO_FN(CAN_CLK_A), GPIO_FN(RX4_D), + GPIO_FN(AUDIO_CLKOUT), GPIO_FN(TX1_E), GPIO_FN(HRTS0_C), + GPIO_FN(FSE_B), GPIO_FN(LCD_M_DISP_B), + GPIO_FN(AUDIO_CLKC), GPIO_FN(SCK1_E), GPIO_FN(HCTS0_C), + GPIO_FN(FRB_B), GPIO_FN(LCD_VEPWC_B), + GPIO_FN(AUDIO_CLKB_A), GPIO_FN(LCD_CLK_B), + GPIO_FN(AUDIO_CLKA_A), GPIO_FN(VI1_CLK_B), GPIO_FN(SCK1_D), + GPIO_FN(IECLK_B), GPIO_FN(LCD_FLM_B), + GPIO_FN(SSI_SDATA3), GPIO_FN(VI1_7_B), GPIO_FN(HTX0_C), + GPIO_FN(FWE_B), GPIO_FN(LCD_CL2_B), + GPIO_FN(SSI_SDATA2), GPIO_FN(VI1_6_B), GPIO_FN(HRX0_C), + GPIO_FN(FRE_B), GPIO_FN(LCD_CL1_B), + GPIO_FN(SSI_WS23), GPIO_FN(VI1_5_B), GPIO_FN(TX1_D), + GPIO_FN(HSCK0_C), GPIO_FN(FALE_B), GPIO_FN(LCD_DON_B), + GPIO_FN(SSI_SCK23), GPIO_FN(VI1_4_B), GPIO_FN(RX1_D), + GPIO_FN(FCLE_B), GPIO_FN(LCD_DATA15_B), + + /* IPSR11 */ + GPIO_FN(PRESETOUT), GPIO_FN(ST_CLKOUT), + GPIO_FN(DACK1), GPIO_FN(HSPI_CS_B), GPIO_FN(TX4_B), + GPIO_FN(ET0_RX_CLK_A), + GPIO_FN(DREQ1), GPIO_FN(HSPI_CLK_B), GPIO_FN(RX4_B), + GPIO_FN(ET0_PHY_INT_C), GPIO_FN(ET0_TX_CLK_A), + GPIO_FN(DACK0), GPIO_FN(SD1_DAT3_A), GPIO_FN(ET0_TX_ER), + GPIO_FN(DREQ0), GPIO_FN(SD1_CLK_A), GPIO_FN(ET0_TX_EN), + GPIO_FN(USB_OVC1), GPIO_FN(RX3_D), GPIO_FN(CAN1_RX_B), + GPIO_FN(RX5_D), GPIO_FN(IERX_B), + GPIO_FN(PENC1), GPIO_FN(TX3_D), GPIO_FN(CAN1_TX_B), + GPIO_FN(TX5_D), GPIO_FN(IETX_B), + GPIO_FN(TX0_A), GPIO_FN(HSPI_TX_A), + GPIO_FN(RX0_A), GPIO_FN(HSPI_RX_A), GPIO_FN(RMII0_RXD0_A), + GPIO_FN(ET0_ERXD6), + GPIO_FN(SCK0_A), GPIO_FN(HSPI_CS_A), GPIO_FN(VI0_CLKENB), + GPIO_FN(RMII0_TXD1_A), GPIO_FN(ET0_ERXD5), + GPIO_FN(SCIF_CLK_A), GPIO_FN(HSPI_CLK_A), GPIO_FN(VI0_CLK), + GPIO_FN(RMII0_TXD0_A), GPIO_FN(ET0_ERXD4), + GPIO_FN(SDSELF), GPIO_FN(RTS1_E), + GPIO_FN(SDA0), GPIO_FN(HIFEBL_A), + GPIO_FN(SDA1), GPIO_FN(RX1_E), + GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) { + GP_0_31_FN, FN_IP2_2_0, + GP_0_30_FN, FN_IP1_31_29, + GP_0_29_FN, FN_IP1_28_26, + GP_0_28_FN, FN_IP1_25_23, + GP_0_27_FN, FN_IP1_22_20, + GP_0_26_FN, FN_IP1_19_18, + GP_0_25_FN, FN_IP1_17_16, + GP_0_24_FN, FN_IP0_5_4, + GP_0_23_FN, FN_IP0_3_2, + GP_0_22_FN, FN_IP0_1_0, + GP_0_21_FN, FN_IP11_28, + GP_0_20_FN, FN_IP1_7_6, + GP_0_19_FN, FN_IP1_5_4, + GP_0_18_FN, FN_IP1_3_2, + GP_0_17_FN, FN_IP1_1_0, + GP_0_16_FN, FN_IP0_31_30, + GP_0_15_FN, FN_IP0_29_28, + GP_0_14_FN, FN_IP0_27_26, + GP_0_13_FN, FN_IP0_25_24, + GP_0_12_FN, FN_IP0_23_22, + GP_0_11_FN, FN_IP0_21_20, + GP_0_10_FN, FN_IP0_19_18, + GP_0_9_FN, FN_IP0_17_16, + GP_0_8_FN, FN_IP0_15_14, + GP_0_7_FN, FN_IP0_13_12, + GP_0_6_FN, FN_IP0_11_10, + GP_0_5_FN, FN_IP0_9_8, + GP_0_4_FN, FN_IP0_7_6, + GP_0_3_FN, FN_IP1_15_14, + GP_0_2_FN, FN_IP1_13_12, + GP_0_1_FN, FN_IP1_11_10, + GP_0_0_FN, FN_IP1_9_8 } + }, + { PINMUX_CFG_REG("GPSR1", 0xFFFC0008, 32, 1) { + GP_1_31_FN, FN_IP11_25_23, + GP_1_30_FN, FN_IP2_13_11, + GP_1_29_FN, FN_IP2_10_8, + GP_1_28_FN, FN_IP2_7_5, + GP_1_27_FN, FN_IP3_26_24, + GP_1_26_FN, FN_IP3_23_21, + GP_1_25_FN, FN_IP2_4_3, + GP_1_24_FN, FN_WE1, + GP_1_23_FN, FN_WE0, + GP_1_22_FN, FN_IP3_19_18, + GP_1_21_FN, FN_RD, + GP_1_20_FN, FN_IP3_17_15, + GP_1_19_FN, FN_IP3_14_12, + GP_1_18_FN, FN_IP3_11_9, + GP_1_17_FN, FN_IP3_8_6, + GP_1_16_FN, FN_IP3_5_3, + GP_1_15_FN, FN_EX_CS0, + GP_1_14_FN, FN_IP3_2, + GP_1_13_FN, FN_CS0, + GP_1_12_FN, FN_BS, + GP_1_11_FN, FN_CLKOUT, + GP_1_10_FN, FN_IP3_1_0, + GP_1_9_FN, FN_IP2_30_28, + GP_1_8_FN, FN_IP2_27_25, + GP_1_7_FN, FN_IP2_24_23, + GP_1_6_FN, FN_IP2_22_20, + GP_1_5_FN, FN_IP2_19_17, + GP_1_4_FN, FN_IP2_16_14, + GP_1_3_FN, FN_IP11_22_21, + GP_1_2_FN, FN_IP11_20_19, + GP_1_1_FN, FN_IP3_29_27, + GP_1_0_FN, FN_IP3_20 } + }, + { PINMUX_CFG_REG("GPSR2", 0xFFFC000C, 32, 1) { + GP_2_31_FN, FN_IP4_31_30, + GP_2_30_FN, FN_IP5_2_0, + GP_2_29_FN, FN_IP5_5_3, + GP_2_28_FN, FN_IP5_8_6, + GP_2_27_FN, FN_IP5_11_9, + GP_2_26_FN, FN_IP5_14_12, + GP_2_25_FN, FN_IP5_17_15, + GP_2_24_FN, FN_IP5_20_18, + GP_2_23_FN, FN_IP5_22_21, + GP_2_22_FN, FN_IP5_24_23, + GP_2_21_FN, FN_IP5_26_25, + GP_2_20_FN, FN_IP4_29_28, + GP_2_19_FN, FN_IP4_27_26, + GP_2_18_FN, FN_IP4_25_24, + GP_2_17_FN, FN_IP4_23_22, + GP_2_16_FN, FN_IP4_21_20, + GP_2_15_FN, FN_IP4_19_18, + GP_2_14_FN, FN_IP4_17_15, + GP_2_13_FN, FN_IP4_14_12, + GP_2_12_FN, FN_IP4_11_9, + GP_2_11_FN, FN_IP4_8_6, + GP_2_10_FN, FN_IP4_5_3, + GP_2_9_FN, FN_IP8_27_26, + GP_2_8_FN, FN_IP11_12, + GP_2_7_FN, FN_IP8_25_23, + GP_2_6_FN, FN_IP8_22_20, + GP_2_5_FN, FN_IP11_27_26, + GP_2_4_FN, FN_IP8_29_28, + GP_2_3_FN, FN_IP4_2_0, + GP_2_2_FN, FN_IP11_11_10, + GP_2_1_FN, FN_IP11_9_7, + GP_2_0_FN, FN_IP11_6_4 } + }, + { PINMUX_CFG_REG("GPSR3", 0xFFFC0010, 32, 1) { + GP_3_31_FN, FN_IP9_1_0, + GP_3_30_FN, FN_IP8_19_18, + GP_3_29_FN, FN_IP8_17_16, + GP_3_28_FN, FN_IP8_15_14, + GP_3_27_FN, FN_IP8_13_12, + GP_3_26_FN, FN_IP8_11_10, + GP_3_25_FN, FN_IP8_9_8, + GP_3_24_FN, FN_IP8_7_6, + GP_3_23_FN, FN_IP8_5_4, + GP_3_22_FN, FN_IP8_3_2, + GP_3_21_FN, FN_IP8_1_0, + GP_3_20_FN, FN_IP7_30_29, + GP_3_19_FN, FN_IP7_28_27, + GP_3_18_FN, FN_IP7_26_24, + GP_3_17_FN, FN_IP7_23_21, + GP_3_16_FN, FN_IP7_20_18, + GP_3_15_FN, FN_IP7_17_15, + GP_3_14_FN, FN_IP7_14_12, + GP_3_13_FN, FN_IP7_11_9, + GP_3_12_FN, FN_IP7_8_6, + GP_3_11_FN, FN_IP7_5_3, + GP_3_10_FN, FN_IP7_2_0, + GP_3_9_FN, FN_IP6_23_21, + GP_3_8_FN, FN_IP6_20_18, + GP_3_7_FN, FN_IP6_17_16, + GP_3_6_FN, FN_IP6_15_14, + GP_3_5_FN, FN_IP6_13_12, + GP_3_4_FN, FN_IP6_11_10, + GP_3_3_FN, FN_IP6_9_8, + GP_3_2_FN, FN_IP6_7_6, + GP_3_1_FN, FN_IP6_5_3, + GP_3_0_FN, FN_IP6_2_0 } + }, + + { PINMUX_CFG_REG("GPSR4", 0xFFFC0014, 32, 1) { + GP_4_31_FN, FN_IP10_24_23, + GP_4_30_FN, FN_IP10_22, + GP_4_29_FN, FN_IP11_18_16, + GP_4_28_FN, FN_USB_OVC0, + GP_4_27_FN, FN_IP11_15_13, + GP_4_26_FN, FN_PENC0, + GP_4_25_FN, FN_IP11_2, + GP_4_24_FN, FN_SCL0, + GP_4_23_FN, FN_IP11_1, + GP_4_22_FN, FN_IP11_0, + GP_4_21_FN, FN_IP10_21_19, + GP_4_20_FN, FN_IP10_18_16, + GP_4_19_FN, FN_IP10_15, + GP_4_18_FN, FN_IP10_14_12, + GP_4_17_FN, FN_IP10_11_9, + GP_4_16_FN, FN_IP10_8_6, + GP_4_15_FN, FN_IP10_5_3, + GP_4_14_FN, FN_IP10_2_0, + GP_4_13_FN, FN_IP9_29_28, + GP_4_12_FN, FN_IP9_27_26, + GP_4_11_FN, FN_IP9_9_8, + GP_4_10_FN, FN_IP9_7_6, + GP_4_9_FN, FN_IP9_5_4, + GP_4_8_FN, FN_IP9_3_2, + GP_4_7_FN, FN_IP9_17_16, + GP_4_6_FN, FN_IP9_15_14, + GP_4_5_FN, FN_IP9_13_12, + GP_4_4_FN, FN_IP9_11_10, + GP_4_3_FN, FN_IP9_25_24, + GP_4_2_FN, FN_IP9_23_22, + GP_4_1_FN, FN_IP9_21_20, + GP_4_0_FN, FN_IP9_19_18 } + }, + { PINMUX_CFG_REG("GPSR5", 0xFFFC0018, 32, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 28 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 27 - 24 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 20 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 19 - 16 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */ + GP_5_11_FN, FN_IP10_29_28, + GP_5_10_FN, FN_IP10_27_26, + 0, 0, 0, 0, 0, 0, 0, 0, /* 9 - 6 */ + 0, 0, 0, 0, /* 5, 4 */ + GP_5_3_FN, FN_IRQ3_B, + GP_5_2_FN, FN_IRQ2_B, + GP_5_1_FN, FN_IP11_3, + GP_5_0_FN, FN_IP10_25 } + }, + + { PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32, + 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2) { + /* IP0_31_30 [2] */ + FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A, + FN_TIOC3D_C, + /* IP0_29_28 [2] */ + FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C, 0, + /* IP0_27_26 [2] */ + FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C, 0, + /* IP0_25_24 [2] */ + FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C, 0, + /* IP0_23_22 [2] */ + FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C, + /* IP0_21_20 [2] */ + FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C, + /* IP0_19_18 [2] */ + FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C, + /* IP0_17_16 [2] */ + FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C, + /* IP0_15_14 [2] */ + FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C, + /* IP0_13_12 [2] */ + FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C, + /* IP0_11_10 [2] */ + FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C, + /* IP0_9_8 [2] */ + FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C, + /* IP0_7_6 [2] */ + FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C, + /* IP0_5_4 [2] */ + FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C, + /* IP0_3_2 [2] */ + FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C, + /* IP0_1_0 [2] */ + FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C } + }, + { PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32, + 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) { + /* IP1_31_29 [3] */ + FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6, + FN_FD3_A, 0, 0, 0, + /* IP1_28_26 [3] */ + FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5, + FN_FD2_A, 0, 0, 0, + /* IP1_25_23 [3] */ + FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4, + FN_FD1_A, 0, 0, 0, + /* IP1_22_20 [3] */ + FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3, + FN_FD0_A, 0, 0, 0, + /* IP1_19_18 [2] */ + FN_A25, FN_TX2_D, FN_ST1_D2, 0, + /* IP1_17_16 [2] */ + FN_A24, FN_RX2_D, FN_ST1_D1, 0, + /* IP1_15_14 [2] */ + FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A, 0, + /* IP1_13_12 [2] */ + FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A, 0, + /* IP1_11_10 [2] */ + FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A, 0, + /* IP1_9_8 [2] */ + FN_A20, FN_ST1_REQ, FN_LCD_FLM_A, 0, + /* IP1_7_6 [2] */ + FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A, FN_TIOC4D_C, + /* IP1_5_4 [2] */ + FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C, + /* IP1_3_2 [2] */ + FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C, + /* IP1_1_0 [2] */ + FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C } + }, + { PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32, + 1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3) { + /* IP2_31 [1] */ + 0, 0, + /* IP2_30_28 [3] */ + FN_D14, FN_TX2_B, 0, FN_FSE_A, + FN_ET0_TX_CLK_B, 0, 0, 0, + /* IP2_27_25 [3] */ + FN_D13, FN_RX2_B, 0, FN_FRB_A, + FN_ET0_ETXD6_B, 0, 0, 0, + /* IP2_24_23 [2] */ + FN_D12, 0, FN_FWE_A, FN_ET0_ETXD5_B, + /* IP2_22_20 [3] */ + FN_D11, FN_RSPI_MISO_A, 0, FN_QMI_QIO1_A, + FN_FRE_A, FN_ET0_ETXD3_B, 0, 0, + /* IP2_19_17 [3] */ + FN_D10, FN_RSPI_MOSI_A, 0, FN_QMO_QIO0_A, + FN_FALE_A, FN_ET0_ETXD2_B, 0, 0, + /* IP2_16_14 [3] */ + FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A, + FN_FCLE_A, FN_ET0_ETXD1_B, 0, 0, + /* IP2_13_11 [3] */ + FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A, + FN_FCE_A, FN_ET0_GTX_CLK_B, 0, 0, + /* IP2_10_8 [3] */ + FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A, + FN_FD7_A, 0, 0, 0, + /* IP2_7_5 [3] */ + FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A, + FN_FD6_A, 0, 0, 0, + /* IP2_4_3 [2] */ + FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A, + /* IP2_2_0 [3] */ + FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7, + FN_FD4_A, 0, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32, + 2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2) { + /* IP3_31_30 [2] */ + 0, 0, 0, 0, + /* IP3_29_27 [3] */ + FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A, + FN_ET0_ETXD7, 0, 0, 0, + /* IP3_26_24 [3] */ + FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C, + FN_ET0_MAGIC_C, FN_ET0_ETXD6_A, 0, 0, + /* IP3_23_21 [3] */ + FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C, + FN_ET0_LINK_C, FN_ET0_ETXD5_A, 0, 0, + /* IP3_20 [1] */ + FN_EX_WAIT0, FN_TCLK1_B, + /* IP3_19_18 [2] */ + FN_RD_WR, FN_TCLK1_B, 0, 0, + /* IP3_17_15 [3] */ + FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B, + FN_ET0_ETXD3_A, 0, 0, 0, + /* IP3_14_12 [3] */ + FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B, + FN_ET0_ETXD2_A, 0, 0, 0, + /* IP3_11_9 [3] */ + FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B, + FN_ET0_ETXD1_A, 0, 0, 0, + /* IP3_8_6 [3] */ + FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B, + FN_ET0_GTX_CLK_A, 0, 0, 0, + /* IP3_5_3 [3] */ + FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B, + FN_ET0_ETXD0, 0, 0, 0, + /* IP3_2 [1] */ + FN_CS1_A26, FN_QIO3_B, + /* IP3_1_0 [2] */ + FN_D15, FN_SCK2_B, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32, + 2, 2, 2, 2, 2, 2 , 2, 3, 3, 3, 3, 3, 3) { + /* IP4_31_30 [2] */ + 0, FN_SCK2_A, FN_VI0_G3, 0, + /* IP4_29_28 [2] */ + 0, FN_RTS1_B, FN_VI0_G2, 0, + /* IP4_27_26 [2] */ + 0, FN_CTS1_B, FN_VI0_DATA7_VI0_G1, 0, + /* IP4_25_24 [2] */ + 0, FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A, + /* IP4_23_22 [2] */ + 0, FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A, + /* IP4_21_20 [2] */ + 0, FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A, + /* IP4_19_18 [2] */ + 0, FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A, + /* IP4_17_15 [3] */ + 0, FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A, + FN_ET0_MDC, 0, 0, 0, + /* IP4_14_12 [3] */ + FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A, + FN_ET0_COL, 0, 0, 0, + /* IP4_11_9 [3] */ + FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A, + FN_ET0_CRS, 0, 0, 0, + /* IP4_8_6 [3] */ + FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A, + FN_ET0_RX_ER, 0, 0, 0, + /* IP4_5_3 [3] */ + FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A, + FN_ET0_RX_DV, 0, 0, 0, + /* IP4_2_0 [3] */ + FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A, + FN_ET0_ERXD7, 0, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32, + 1, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3) { + /* IP5_31 [1] */ + 0, 0, + /* IP5_30 [1] */ + 0, 0, + /* IP5_29 [1] */ + 0, 0, + /* IP5_28 [1] */ + 0, 0, + /* IP5_27 [1] */ + 0, 0, + /* IP5_26_25 [2] */ + FN_REF50CK, FN_CTS1_E, FN_HCTS0_D, 0, + /* IP5_24_23 [2] */ + FN_REF125CK, FN_ADTRG, FN_RX5_C, 0, + /* IP5_22_21 [2] */ + FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5, 0, + /* IP5_20_18 [3] */ + FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, 0, + 0, 0, 0, FN_ET0_PHY_INT_B, + /* IP5_17_15 [3] */ + FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, 0, + 0, 0, 0, FN_ET0_MAGIC_B, + /* IP5_14_12 [3] */ + FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, 0, + 0, 0, 0, FN_ET0_LINK_B, + /* IP5_11_9 [3] */ + FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, 0, + 0, 0, 0, FN_ET0_MDIO_B, + /* IP5_8_6 [3] */ + FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, 0, + 0, 0, 0, FN_ET0_ERXD3_B, + /* IP5_5_3 [3] */ + FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, 0, + 0, 0, 0, FN_ET0_ERXD2_B, + /* IP5_2_0 [3] */ + FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, 0, + FN_ET0_RX_CLK_B, 0, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32, + 1, 1, 1, 1, 1, 1, 1, 1, + 3, 3, 2, 2, 2, 2, 2, 2, 3, 3) { + /* IP5_31 [1] */ + 0, 0, + /* IP6_30 [1] */ + 0, 0, + /* IP6_29 [1] */ + 0, 0, + /* IP6_28 [1] */ + 0, 0, + /* IP6_27 [1] */ + 0, 0, + /* IP6_26 [1] */ + 0, 0, + /* IP6_25 [1] */ + 0, 0, + /* IP6_24 [1] */ + 0, 0, + /* IP6_23_21 [3] */ + FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A, + FN_HIFD09, 0, 0, 0, + /* IP6_20_18 [3] */ + FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A, + FN_TIOC1A_A, FN_HIFD08, 0, 0, + /* IP6_17_16 [2] */ + FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07, + /* IP6_15_14 [2] */ + FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06, + /* IP6_13_12 [2] */ + FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05, + /* IP6_11_10 [2] */ + FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04, + /* IP6_9_8 [2] */ + FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03, + /* IP6_7_6 [2] */ + FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02, + /* IP6_5_3 [3] */ + FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A, + FN_TCLKB_A, FN_HIFD01, 0, 0, + /* IP6_2_0 [3] */ + FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A, + FN_TCLKA_A, FN_HIFD00, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32, + 1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP7_31 [1] */ + 0, 0, + /* IP7_30_29 [2] */ + FN_DU0_DB4, 0, FN_HIFINT, 0, + /* IP7_28_27 [2] */ + FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD, + /* IP7_26_24 [3] */ + FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A, + FN_HIFWR, 0, 0, 0, + /* IP7_23_21 [3] */ + FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A, + FN_HIFRS, 0, 0, 0, + /* IP7_20_18 [3] */ + FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A, + FN_HIFCS, 0, 0, 0, + /* IP7_17_15 [3] */ + FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A, + FN_HIFD15, 0, 0, 0, + /* IP7_14_12 [3] */ + FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A, + FN_HIFD14, 0, 0, 0, + /* IP7_11_9 [3] */ + FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A, + FN_HIFD13, 0, 0, 0, + /* IP7_8_6 [3] */ + FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A, + FN_HIFD12, 0, 0, 0, + /* IP7_5_3 [3] */ + FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A, + FN_HIFD11, 0, 0, 0, + /* IP7_2_0 [3] */ + FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A, + FN_HIFD10, 0, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32, + 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) { + /* IP9_31_30 [2] */ + 0, 0, 0, 0, + /* IP8_29_28 [2] */ + FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A, + /* IP8_27_26 [2] */ + FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A, + /* IP8_25_23 [3] */ + FN_IRQ1_A, 0, FN_HSPI_RX_B, FN_TX3_E, + FN_ET0_ERXD1, 0, 0, 0, + /* IP8_22_20 [3] */ + FN_IRQ0_A, 0, FN_HSPI_TX_B, FN_RX3_E, + FN_ET0_ERXD0, 0, 0, 0, + /* IP8_19_18 [2] */ + FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B, + /* IP8_17_16 [2] */ + FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B, + /* IP8_15_14 [2] */ + FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B, + FN_SSI_SDATA1_B, + /* IP8_13_12 [2] */ + FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_HSPI_RX0_C, FN_SSI_WS1_B, + /* IP8_11_10 [2] */ + FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_HSPI_TX0_C, FN_SSI_SCK1_B, + /* IP8_9_8 [2] */ + FN_DU0_DOTCLKOUT, 0, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B, + /* IP8_7_6 [2] */ + FN_DU0_DOTCLKIN, 0, FN_HSPI_CS0_C, FN_SSI_WS0_B, + /* IP8_5_4 [2] */ + FN_DU0_DB7, 0, FN_SSI_SCK0_B, FN_HIFEBL_B, + /* IP8_3_2 [2] */ + FN_DU0_DB6, 0, FN_HIFRDY, 0, + /* IP8_1_0 [2] */ + FN_DU0_DB5, 0, FN_HIFDREQ, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32, + 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2) { + /* IP9_31_30 [2] */ + 0, 0, 0, 0, + /* IP9_29_28 [2] */ + FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B, 0, + /* IP9_27_26 [2] */ + FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B, 0, + /* IP9_25_24 [2] */ + FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B, + /* IP9_23_22 [2] */ + FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B, + /* IP9_21_20 [2] */ + FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B, 0, + /* IP9_19_18 [2] */ + FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B, 0, + /* IP9_17_16 [2] */ + FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B, 0, + /* IP9_15_14 [2] */ + FN_VI1_6_A, 0, FN_FD7_B, FN_LCD_DATA7_B, + /* IP9_13_12 [2] */ + FN_VI1_5_A, 0, FN_FD6_B, FN_LCD_DATA6_B, + /* IP9_11_10 [2] */ + FN_VI1_4_A, 0, FN_FD5_B, FN_LCD_DATA5_B, + /* IP9_9_8 [2] */ + FN_VI1_3_A, 0, FN_FD4_B, FN_LCD_DATA4_B, + /* IP9_7_6 [2] */ + FN_VI1_2_A, 0, FN_FD3_B, FN_LCD_DATA3_B, + /* IP9_5_4 [2] */ + FN_VI1_1_A, 0, FN_FD2_B, FN_LCD_DATA2_B, + /* IP9_3_2 [2] */ + FN_VI1_0_A, 0, FN_FD1_B, FN_LCD_DATA1_B, + /* IP9_1_0 [2] */ + FN_VI1_CLK_A, 0, FN_FD0_B, FN_LCD_DATA0_B } + }, + { PINMUX_CFG_REG_VAR("IPSR10", 0xFFFC0044, 32, + 2, 2, 2, 1, 2, 1, 3, + 3, 1, 3, 3, 3, 3, 3) { + /* IP9_31_30 [2] */ + 0, 0, 0, 0, + /* IP10_29_28 [2] */ + FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT, 0, + /* IP10_27_26 [2] */ + FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG, 0, + /* IP10_25 [1] */ + FN_CAN1_RX_A, FN_IRQ1_B, + /* IP10_24_23 [2] */ + FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK, 0, + /* IP10_22 [1] */ + FN_CAN_CLK_A, FN_RX4_D, + /* IP10_21_19 [3] */ + FN_AUDIO_CLKOUT, FN_TX1_E, FN_HRTS0_C, FN_FSE_B, + FN_LCD_M_DISP_B, 0, 0, 0, + /* IP10_18_16 [3] */ + FN_AUDIO_CLKC, FN_SCK1_E, FN_HCTS0_C, FN_FRB_B, + FN_LCD_VEPWC_B, 0, 0, 0, + /* IP10_15 [1] */ + FN_AUDIO_CLKB_A, FN_LCD_CLK_B, + /* IP10_14_12 [3] */ + FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B, + FN_LCD_FLM_B, 0, 0, 0, + /* IP10_11_9 [3] */ + FN_SSI_SDATA3, FN_VI1_7_B, FN_HTX0_C, FN_FWE_B, + FN_LCD_CL2_B, 0, 0, 0, + /* IP10_8_6 [3] */ + FN_SSI_SDATA2, FN_VI1_6_B, FN_HRX0_C, FN_FRE_B, + FN_LCD_CL1_B, 0, 0, 0, + /* IP10_5_3 [3] */ + FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B, + FN_LCD_DON_B, 0, 0, 0, + /* IP10_2_0 [3] */ + FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B, + FN_LCD_DATA15_B, 0, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32, + 3, 1, 2, 2, 2, 3, 3, 1, 2, 3, 3, 1, 1, 1, 1) { + /* IP11_31_29 [3] */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP11_28 [1] */ + FN_PRESETOUT, FN_ST_CLKOUT, + /* IP11_27_26 [2] */ + FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A, + /* IP11_25_23 [3] */ + FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C, + FN_ET0_TX_CLK_A, 0, 0, 0, + /* IP11_22_21 [2] */ + FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER, 0, + /* IP11_20_19 [2] */ + FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN, 0, + /* IP11_18_16 [3] */ + FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D, + FN_IERX_B, 0, 0, 0, + /* IP11_15_13 [3] */ + FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D, + FN_IETX_B, 0, 0, 0, + /* IP11_12 [1] */ + FN_TX0_A, FN_HSPI_TX_A, + /* IP11_11_10 [2] */ + FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6, + /* IP11_9_7 [3] */ + FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A, + FN_ET0_ERXD5, 0, 0, 0, + /* IP11_6_4 [3] */ + FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A, + FN_ET0_ERXD4, 0, 0, 0, + /* IP11_3 [1] */ + FN_SDSELF, FN_RTS1_E, + /* IP11_2 [1] */ + FN_SDA0, FN_HIFEBL_A, + /* IP11_1 [1] */ + FN_SDA1, FN_RX1_E, + /* IP11_0 [1] */ + FN_SCL1, FN_SCIF_CLK_C } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xFFFC004C, 32, + 3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2, 2, + 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { + /* SEL1_31_29 [3] */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* SEL1_28 [1] */ + FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, + /* SEL1_27 [1] */ + FN_SEL_RQSPI_0, FN_SEL_RQSPI_1, + /* SEL1_26 [1] */ + FN_SEL_VIN1_0, FN_SEL_VIN1_1, + /* SEL1_25 [1] */ + FN_SEL_HIF_0, FN_SEL_HIF_1, + /* SEL1_24 [1] */ + FN_SEL_RSPI_0, FN_SEL_RSPI_1, + /* SEL1_23 [1] */ + FN_SEL_LCDC_0, FN_SEL_LCDC_1, + /* SEL1_22_21 [2] */ + FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2, 0, + /* SEL1_20 [1] */ + FN_SEL_ET0_0, FN_SEL_ET0_1, + /* SEL1_19 [1] */ + FN_SEL_RMII_0, FN_SEL_RMII_1, + /* SEL1_18 [1] */ + FN_SEL_TMU_0, FN_SEL_TMU_1, + /* SEL1_17_16 [2] */ + FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2, 0, + /* SEL1_15_14 [2] */ + FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3, + /* SEL1_13 [1] */ + FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1, + /* SEL1_12_11 [2] */ + FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2, 0, + /* SEL1_10 [1] */ + FN_SEL_RCAN0_0, FN_SEL_RCAN0_1, + /* SEL1_9 [1] */ + FN_SEL_SDHI2_0, FN_SEL_SDHI2_1, + /* SEL1_8 [1] */ + FN_SEL_SDHI1_0, FN_SEL_SDHI1_1, + /* SEL1_7 [1] */ + FN_SEL_SDHI0_0, FN_SEL_SDHI0_1, + /* SEL1_6 [1] */ + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + /* SEL1_5 [1] */ + FN_SEL_SSI0_0, FN_SEL_SSI0_1, + /* SEL1_4 [1] */ + FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1, + /* SEL1_3 [1] */ + FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1, + /* SEL1_2 [1] */ + FN_SEL_FLCTL_0, FN_SEL_FLCTL_1, + /* SEL1_1 [1] */ + FN_SEL_MMC_0, FN_SEL_MMC_1, + /* SEL1_0 [1] */ + FN_SEL_INTC_0, FN_SEL_INTC_1 } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xFFFC0050, 32, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 2, 2, 1, 2, 2, 3, 2, 3, 2, 2) { + /* SEL2_31 [1] */ + 0, 0, + /* SEL2_30 [1] */ + 0, 0, + /* SEL2_29 [1] */ + 0, 0, + /* SEL2_28 [1] */ + 0, 0, + /* SEL2_27 [1] */ + 0, 0, + /* SEL2_26 [1] */ + 0, 0, + /* SEL2_25 [1] */ + 0, 0, + /* SEL2_24 [1] */ + 0, 0, + /* SEL2_23 [1] */ + FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1, + /* SEL2_22 [1] */ + FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1, + /* SEL2_21 [1] */ + FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1, + /* SEL2_20_19 [2] */ + FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2, 0, + /* SEL2_18_17 [2] */ + FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2, 0, + /* SEL2_16 [1] */ + FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1, + /* SEL2_15_14 [2] */ + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, + /* SEL2_13_12 [2] */ + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + /* SEL2_11_9 [3] */ + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, + FN_SEL_SCIF3_4, 0, 0, 0, + /* SEL2_8_7 [2] */ + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, + /* SEL2_6_4 [3] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIF1_4, 0, 0, 0, + /* SEL2_3_2 [2] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 0, + /* SEL2_1_0 [2] */ + FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2, 0 } + }, + /* GPIO 0 - 5*/ + { PINMUX_CFG_REG("INOUTSEL0", 0xFFC40004, 32, 1) { GP_INOUTSEL(0) } }, + { PINMUX_CFG_REG("INOUTSEL1", 0xFFC41004, 32, 1) { GP_INOUTSEL(1) } }, + { PINMUX_CFG_REG("INOUTSEL2", 0xFFC42004, 32, 1) { GP_INOUTSEL(2) } }, + { PINMUX_CFG_REG("INOUTSEL3", 0xFFC43004, 32, 1) { GP_INOUTSEL(3) } }, + { PINMUX_CFG_REG("INOUTSEL4", 0xFFC44004, 32, 1) { GP_INOUTSEL(4) } }, + { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 24 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 16 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */ + GP_5_11_IN, GP_5_11_OUT, + GP_5_10_IN, GP_5_10_OUT, + GP_5_9_IN, GP_5_9_OUT, + GP_5_8_IN, GP_5_8_OUT, + GP_5_7_IN, GP_5_7_OUT, + GP_5_6_IN, GP_5_6_OUT, + GP_5_5_IN, GP_5_5_OUT, + GP_5_4_IN, GP_5_4_OUT, + GP_5_3_IN, GP_5_3_OUT, + GP_5_2_IN, GP_5_2_OUT, + GP_5_1_IN, GP_5_1_OUT, + GP_5_0_IN, GP_5_0_OUT } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + /* GPIO 0 - 5*/ + { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } }, + { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } }, + { PINMUX_DATA_REG("INDT2", 0xFFC4200C, 32) { GP_INDT(2) } }, + { PINMUX_DATA_REG("INDT3", 0xFFC4300C, 32) { GP_INDT(3) } }, + { PINMUX_DATA_REG("INDT4", 0xFFC4400C, 32) { GP_INDT(4) } }, + { PINMUX_DATA_REG("INDT5", 0xFFC4500C, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, + GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA, + GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA, + GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA } + }, + { }, +}; + +static struct resource sh7734_pfc_resources[] = { + [0] = { /* PFC */ + .start = 0xFFFC0000, + .end = 0xFFFC011C, + .flags = IORESOURCE_MEM, + }, + [1] = { /* GPIO */ + .start = 0xFFC40000, + .end = 0xFFC4502B, + .flags = IORESOURCE_MEM, + } +}; + +static struct pinmux_info sh7734_pinmux_info = { + .name = "sh7734_pfc", + + .resource = sh7734_pfc_resources, + .num_resources = ARRAY_SIZE(sh7734_pfc_resources), + + .unlock_reg = 0xFFFC0000, + + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_GP_0_0, + .last_gpio = GPIO_FN_ST_CLKOUT, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +static int __init plat_pinmux_setup(void) +{ + return register_pinmux(&sh7734_pinmux_info); +} +arch_initcall(plat_pinmux_setup); -- cgit v0.10.2 From 5d920bb929a99446062a48cf90867bbca57b8e77 Mon Sep 17 00:00:00 2001 From: Filippo Arcidiacono Date: Thu, 19 Apr 2012 15:45:57 +0900 Subject: sh: initial stack protector support. This implements basic -fstack-protector support, based on the early ARM version in c743f38013aeff58ef6252601e397b5ba281c633. The SMP case is limited to the initial canary value, while the UP case handles per-task granularity (limited to 32-bit sh until a new enough sh64 compiler manifests itself). Signed-off-by: Filippo Arcidiacono Reviewed-by: Carmelo Amoroso Signed-off-by: Stuart Menefy Signed-off-by: Paul Mundt diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index ff9e033..60ed366 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -685,6 +685,20 @@ config SECCOMP If unsure, say N. +config CC_STACKPROTECTOR + bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" + depends on SUPERH32 && EXPERIMENTAL + help + This option turns on the -fstack-protector GCC feature. This + feature puts, at the beginning of functions, a canary value on + the stack just before the return address, and validates + the value just before actually returning. Stack based buffer + overflows (that need to overwrite this return address) now also + overwrite the canary, which gets detected and the attack is then + neutralized via a kernel panic. + + This feature requires gcc version 4.2 or above. + config SMP bool "Symmetric multi-processing support" depends on SYS_SUPPORTS_SMP diff --git a/arch/sh/Makefile b/arch/sh/Makefile index 3fc0f41..24875c8 100644 --- a/arch/sh/Makefile +++ b/arch/sh/Makefile @@ -199,6 +199,10 @@ ifeq ($(CONFIG_DWARF_UNWINDER),y) KBUILD_CFLAGS += -fasynchronous-unwind-tables endif +ifeq ($(CONFIG_CC_STACKPROTECTOR),y) + KBUILD_CFLAGS += -fstack-protector +endif + libs-$(CONFIG_SUPERH32) := arch/sh/lib/ $(libs-y) libs-$(CONFIG_SUPERH64) := arch/sh/lib64/ $(libs-y) diff --git a/arch/sh/include/asm/stackprotector.h b/arch/sh/include/asm/stackprotector.h new file mode 100644 index 0000000..d9df3a7 --- /dev/null +++ b/arch/sh/include/asm/stackprotector.h @@ -0,0 +1,27 @@ +#ifndef __ASM_SH_STACKPROTECTOR_H +#define __ASM_SH_STACKPROTECTOR_H + +#include +#include + +extern unsigned long __stack_chk_guard; + +/* + * Initialize the stackprotector canary value. + * + * NOTE: this must only be called from functions that never return, + * and it must always be inlined. + */ +static __always_inline void boot_init_stack_canary(void) +{ + unsigned long canary; + + /* Try to get a semi random initial value. */ + get_random_bytes(&canary, sizeof(canary)); + canary ^= LINUX_VERSION_CODE; + + current->stack_canary = canary; + __stack_chk_guard = current->stack_canary; +} + +#endif /* __ASM_SH_STACKPROTECTOR_H */ diff --git a/arch/sh/kernel/process.c b/arch/sh/kernel/process.c index 325f98b..f3f03e4 100644 --- a/arch/sh/kernel/process.c +++ b/arch/sh/kernel/process.c @@ -2,10 +2,17 @@ #include #include #include +#include +#include struct kmem_cache *task_xstate_cachep = NULL; unsigned int xstate_size; +#ifdef CONFIG_CC_STACKPROTECTOR +unsigned long __stack_chk_guard __read_mostly; +EXPORT_SYMBOL(__stack_chk_guard); +#endif + int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) { *dst = *src; diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c index 94273aa..f78cc42 100644 --- a/arch/sh/kernel/process_32.c +++ b/arch/sh/kernel/process_32.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -220,6 +221,10 @@ __switch_to(struct task_struct *prev, struct task_struct *next) { struct thread_struct *next_t = &next->thread; +#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) + __stack_chk_guard = next->stack_canary; +#endif + unlazy_fpu(prev, task_pt_regs(prev)); /* we're going to use this soon, after a few expensive things */ -- cgit v0.10.2 From 45c0e0e25eae2c5e8bb9e2dfaf73afb396e0928d Mon Sep 17 00:00:00 2001 From: Stuart Menefy Date: Thu, 19 Apr 2012 17:25:03 +0900 Subject: sh: Improve oops error reporting In some cases the opps error reporting doesn't give enough information to diagnose the problem, only printing information if it is thought to be valid. Replace the current code with more detailed output. This code is based on the ARM reporting, with minor changes for the SH. [lethal@linux-sh.org: fixed up for 64-bit PTEs and pte_offset_kernel()] Signed-off-by: Stuart Menefy Signed-off-by: Paul Mundt diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c index e99b104..c5cd878 100644 --- a/arch/sh/mm/fault_32.c +++ b/arch/sh/mm/fault_32.c @@ -35,6 +35,74 @@ static inline int notify_page_fault(struct pt_regs *regs, int trap) return ret; } +/* + * This is useful to dump out the page tables associated with + * 'addr' in mm 'mm'. + */ +static void show_pte(struct mm_struct *mm, unsigned long addr) +{ + pgd_t *pgd; + + if (mm) + pgd = mm->pgd; + else + pgd = get_TTB(); + + printk(KERN_ALERT "pgd = %p\n", pgd); + pgd += pgd_index(addr); + printk(KERN_ALERT "[%08lx] *pgd=%0*Lx", addr, + sizeof(*pgd) * 2, (u64)pgd_val(*pgd)); + + do { + pud_t *pud; + pmd_t *pmd; + pte_t *pte; + + if (pgd_none(*pgd)) + break; + + if (pgd_bad(*pgd)) { + printk("(bad)"); + break; + } + + pud = pud_offset(pgd, addr); + if (PTRS_PER_PUD != 1) + printk(", *pud=%0*Lx", sizeof(*pud) * 2, + (u64)pud_val(*pud)); + + if (pud_none(*pud)) + break; + + if (pud_bad(*pud)) { + printk("(bad)"); + break; + } + + pmd = pmd_offset(pud, addr); + if (PTRS_PER_PMD != 1) + printk(", *pmd=%0*Lx", sizeof(*pmd) * 2, + (u64)pmd_val(*pmd)); + + if (pmd_none(*pmd)) + break; + + if (pmd_bad(*pmd)) { + printk("(bad)"); + break; + } + + /* We must not map this if we have highmem enabled */ + if (PageHighMem(pfn_to_page(pmd_val(*pmd) >> PAGE_SHIFT))) + break; + + pte = pte_offset_kernel(pmd, addr); + printk(", *pte=%0*Lx", sizeof(*pte) * 2, (u64)pte_val(*pte)); + } while (0); + + printk("\n"); +} + static inline pmd_t *vmalloc_sync_one(pgd_t *pgd, unsigned long address) { unsigned index = pgd_index(address); @@ -254,29 +322,12 @@ no_context: bust_spinlocks(1); if (oops_may_print()) { - unsigned long page; - - if (address < PAGE_SIZE) - printk(KERN_ALERT "Unable to handle kernel NULL " - "pointer dereference"); - else - printk(KERN_ALERT "Unable to handle kernel paging " - "request"); - printk(" at virtual address %08lx\n", address); - printk(KERN_ALERT "pc = %08lx\n", regs->pc); - page = (unsigned long)get_TTB(); - if (page) { - page = ((__typeof__(page) *)page)[address >> PGDIR_SHIFT]; - printk(KERN_ALERT "*pde = %08lx\n", page); - if (page & _PAGE_PRESENT) { - page &= PAGE_MASK; - address &= 0x003ff000; - page = ((__typeof__(page) *) - __va(page))[address >> - PAGE_SHIFT]; - printk(KERN_ALERT "*pte = %08lx\n", page); - } - } + printk(KERN_ALERT + "Unable to handle kernel %s at virtual address %08lx\n", + (address < PAGE_SIZE) ? "NULL pointer dereference" : + "paging request", address); + + show_pte(mm, address); } die("Oops", regs, writeaccess); -- cgit v0.10.2 From 9e7f60a37d1817460ffcdfc2001a00861ac3e121 Mon Sep 17 00:00:00 2001 From: Stuart Menefy Date: Thu, 19 Apr 2012 17:29:38 +0900 Subject: sh: Move board specific options into the Board support menu Move the sourcing of the board specific Kconfig files into the "Board support" menu. Without this they appear underneath the "Board support" menu, in the "System type" menu. [lethal@linux-sh.org: handle the magicpanelr2 case, too] Signed-off-by: Stuart Menefy Signed-off-by: Paul Mundt diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index d893411..6c96daa 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -338,8 +338,6 @@ config SH_APSH4AD0A help Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A. -endmenu - source "arch/sh/boards/mach-r2d/Kconfig" source "arch/sh/boards/mach-highlander/Kconfig" source "arch/sh/boards/mach-sdk7780/Kconfig" @@ -359,3 +357,5 @@ config SH_MAGIC_PANEL_R2_VERSION endmenu endif + +endmenu -- cgit v0.10.2 From b2212ea41dacda8cce0e7681a3a6ccc76c63802e Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 19 Apr 2012 17:52:20 +0900 Subject: sh64: Kill off unused trap_no/error_code from thread_struct. While the trap number and error code are passed around for debugging purposes, this occurs wholly independently of the thread struct values. These values were never part of the sigcontext ABI and are thus never passed anywhere, so we can just kill them off across the board. Signed-off-by: Paul Mundt diff --git a/arch/sh/include/asm/processor_64.h b/arch/sh/include/asm/processor_64.h index e25c4c7..740e268 100644 --- a/arch/sh/include/asm/processor_64.h +++ b/arch/sh/include/asm/processor_64.h @@ -121,7 +121,6 @@ struct thread_struct { NULL for a kernel thread. */ struct pt_regs *uregs; - unsigned long trap_no, error_code; unsigned long address; /* Hardware debugging registers may come here */ @@ -138,8 +137,6 @@ struct thread_struct { .pc = 0, \ .kregs = &fake_swapper_regs, \ .uregs = NULL, \ - .trap_no = 0, \ - .error_code = 0, \ .address = 0, \ .flags = 0, \ } diff --git a/arch/sh/kernel/cpu/sh5/fpu.c b/arch/sh/kernel/cpu/sh5/fpu.c index 4b3bb35..9f8713a 100644 --- a/arch/sh/kernel/cpu/sh5/fpu.c +++ b/arch/sh/kernel/cpu/sh5/fpu.c @@ -107,8 +107,5 @@ asmlinkage void do_fpu_error(unsigned long ex, struct pt_regs *regs) regs->pc += 4; - tsk->thread.trap_no = 11; - tsk->thread.error_code = 0; - force_sig(SIGFPE, tsk); } diff --git a/arch/sh/kernel/traps_64.c b/arch/sh/kernel/traps_64.c index 6c04860..8dae93e 100644 --- a/arch/sh/kernel/traps_64.c +++ b/arch/sh/kernel/traps_64.c @@ -283,8 +283,6 @@ static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_na unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk) { show_excp_regs(fn_name, trapnr, signr, regs); - tsk->thread.error_code = error_code; - tsk->thread.trap_no = trapnr; if (user_mode(regs)) force_sig(signr, tsk); diff --git a/arch/sh/mm/tlbflush_64.c b/arch/sh/mm/tlbflush_64.c index 605dc65..be01f92 100644 --- a/arch/sh/mm/tlbflush_64.c +++ b/arch/sh/mm/tlbflush_64.c @@ -213,7 +213,6 @@ bad_area: panic("INIT had user mode bad_area\n"); } tsk->thread.address = address; - tsk->thread.error_code = writeaccess; info.si_signo = SIGSEGV; info.si_errno = 0; info.si_addr = (void *) address; @@ -263,8 +262,6 @@ do_sigbus: * or user mode. */ tsk->thread.address = address; - tsk->thread.error_code = writeaccess; - tsk->thread.trap_no = 14; force_sig(SIGBUS, tsk); /* Kernel mode? Handle exceptions or die */ -- cgit v0.10.2 From 51ce30684e0d1ae50a154e1026de57d15d096286 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Wed, 9 May 2012 07:59:27 +0100 Subject: sh: Add sh7264 device This is an sh2a device with FPU, video display controller (VDC), 8 serial ports, 3 I2C channels, 2 CAN ports, SD and on-chip USB. Signed-off-by: Phil Edworthy Signed-off-by: Paul Mundt diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index ff9e033..44a22dd 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -288,6 +288,13 @@ config CPU_SUBTYPE_SH7263 select SYS_SUPPORTS_CMT select SYS_SUPPORTS_MTU2 +config CPU_SUBTYPE_SH7264 + bool "Support SH7264 processor" + select CPU_SH2A + select CPU_HAS_FPU + select SYS_SUPPORTS_CMT + select SYS_SUPPORTS_MTU2 + config CPU_SUBTYPE_MXG bool "Support MX-G processor" select CPU_SH2A @@ -584,7 +591,8 @@ config SH_CLK_CPG config SH_CLK_CPG_LEGACY depends on SH_CLK_CPG def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \ - !CPU_SHX3 && !CPU_SUBTYPE_SH7757 + !CPU_SHX3 && !CPU_SUBTYPE_SH7757 && \ + !CPU_SUBTYPE_SH7264 source "kernel/time/Kconfig" diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h index a229c39..898db19 100644 --- a/arch/sh/include/asm/processor.h +++ b/arch/sh/include/asm/processor.h @@ -18,7 +18,7 @@ enum cpu_type { CPU_SH7619, /* SH-2A types */ - CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG, + CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_MXG, /* SH-3 types */ CPU_SH7705, CPU_SH7706, CPU_SH7707, diff --git a/arch/sh/kernel/cpu/proc.c b/arch/sh/kernel/cpu/proc.c index f47be87..b5a9d8b 100644 --- a/arch/sh/kernel/cpu/proc.c +++ b/arch/sh/kernel/cpu/proc.c @@ -7,6 +7,7 @@ static const char *cpu_name[] = { [CPU_SH7201] = "SH7201", [CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263", + [CPU_SH7264] = "SH7264", [CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619", [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706", [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708", diff --git a/arch/sh/kernel/cpu/sh2a/Makefile b/arch/sh/kernel/cpu/sh2a/Makefile index 45f85c7..617ef25 100644 --- a/arch/sh/kernel/cpu/sh2a/Makefile +++ b/arch/sh/kernel/cpu/sh2a/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_SH_FPU) += fpu.o obj-$(CONFIG_CPU_SUBTYPE_SH7201) += setup-sh7201.o clock-sh7201.o obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o +obj-$(CONFIG_CPU_SUBTYPE_SH7264) += setup-sh7264.o clock-sh7264.o obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7264.c b/arch/sh/kernel/cpu/sh2a/clock-sh7264.c new file mode 100644 index 0000000..fdf585c --- /dev/null +++ b/arch/sh/kernel/cpu/sh2a/clock-sh7264.c @@ -0,0 +1,153 @@ +/* + * arch/sh/kernel/cpu/sh2a/clock-sh7264.c + * + * SH7264 clock framework support + * + * Copyright (C) 2012 Phil Edworthy + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include + +/* SH7264 registers */ +#define FRQCR 0xfffe0010 +#define STBCR3 0xfffe0408 +#define STBCR4 0xfffe040c +#define STBCR5 0xfffe0410 +#define STBCR6 0xfffe0414 +#define STBCR7 0xfffe0418 +#define STBCR8 0xfffe041c + +static const unsigned int pll1rate[] = {8, 12}; + +static unsigned int pll1_div; + +/* Fixed 32 KHz root clock for RTC */ +static struct clk r_clk = { + .rate = 32768, +}; + +/* + * Default rate for the root input clock, reset this with clk_set_rate() + * from the platform code. + */ +static struct clk extal_clk = { + .rate = 18000000, +}; + +static unsigned long pll_recalc(struct clk *clk) +{ + unsigned long rate = clk->parent->rate / pll1_div; + return rate * pll1rate[(__raw_readw(FRQCR) >> 8) & 1]; +} + +static struct sh_clk_ops pll_clk_ops = { + .recalc = pll_recalc, +}; + +static struct clk pll_clk = { + .ops = &pll_clk_ops, + .parent = &extal_clk, + .flags = CLK_ENABLE_ON_INIT, +}; + +struct clk *main_clks[] = { + &r_clk, + &extal_clk, + &pll_clk, +}; + +static int div2[] = { 1, 2, 3, 4, 6, 8, 12 }; + +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = div2, + .nr_divisors = ARRAY_SIZE(div2), +}; + +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, +}; + +enum { DIV4_I, DIV4_P, + DIV4_NR }; + +#define DIV4(_reg, _bit, _mask, _flags) \ + SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) + +/* The mask field specifies the div2 entries that are valid */ +struct clk div4_clks[DIV4_NR] = { + [DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT + | CLK_ENABLE_ON_INIT), + [DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT), +}; + +enum { MSTP77, MSTP74, MSTP72, + MSTP60, + MSTP35, MSTP34, MSTP33, MSTP32, MSTP30, + MSTP_NR }; + +static struct clk mstp_clks[MSTP_NR] = { + [MSTP77] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 7, 0), /* SCIF */ + [MSTP74] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 4, 0), /* VDC */ + [MSTP72] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 2, 0), /* CMT */ + [MSTP60] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR6, 0, 0), /* USB */ + [MSTP35] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 6, 0), /* MTU2 */ + [MSTP34] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 4, 0), /* SDHI0 */ + [MSTP33] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 3, 0), /* SDHI1 */ + [MSTP32] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 2, 0), /* ADC */ + [MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */ +}; + +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("rclk", &r_clk), + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("pll_clk", &pll_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), + CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + + /* MSTP clocks */ + CLKDEV_CON_ID("sci_ick", &mstp_clks[MSTP77]), + CLKDEV_CON_ID("vdc3", &mstp_clks[MSTP74]), + CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP72]), + CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]), + CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP35]), + CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP34]), + CLKDEV_CON_ID("sdhi1", &mstp_clks[MSTP33]), + CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]), + CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]), +}; + +int __init arch_clk_init(void) +{ + int k, ret = 0; + + if (test_mode_pin(MODE_PIN0)) { + if (test_mode_pin(MODE_PIN1)) + pll1_div = 3; + else + pll1_div = 4; + } else + pll1_div = 1; + + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + if (!ret) + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + + if (!ret) + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); + + return ret; +} diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c index 48e97a2..414b258 100644 --- a/arch/sh/kernel/cpu/sh2a/probe.c +++ b/arch/sh/kernel/cpu/sh2a/probe.c @@ -29,6 +29,9 @@ void __cpuinit cpu_probe(void) #elif defined(CONFIG_CPU_SUBTYPE_SH7263) boot_cpu_data.type = CPU_SH7263; boot_cpu_data.flags |= CPU_HAS_FPU; +#elif defined(CONFIG_CPU_SUBTYPE_SH7264) + boot_cpu_data.type = CPU_SH7264; + boot_cpu_data.flags |= CPU_HAS_FPU; #elif defined(CONFIG_CPU_SUBTYPE_SH7206) boot_cpu_data.type = CPU_SH7206; boot_cpu_data.flags |= CPU_HAS_DSP; diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c new file mode 100644 index 0000000..ce5c1b5 --- /dev/null +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c @@ -0,0 +1,606 @@ +/* + * SH7264 Setup + * + * Copyright (C) 2012 Renesas Electronics Europe Ltd + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include + +enum { + UNUSED = 0, + + /* interrupt sources */ + IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, + PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, + + DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, + DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15, + USB, VDC3, CMT0, CMT1, BSC, WDT, + MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU, + MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V, + PWMT1, PWMT2, ADC_ADI, + SSIF0, SSII1, SSII2, SSII3, + RSPDIF, + IIC30, IIC31, IIC32, IIC33, + SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, + SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI, + SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI, + SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI, + SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI, + SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI, + SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI, + SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI, + SIO_FIFO, RSPIC0, RSPIC1, + RCAN0, RCAN1, IEBC, CD_ROMD, + NFMC, SDHI, RTC, + SRCC0, SRCC1, DCOMU, OFFI, IFEI, + + /* interrupt groups */ + PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7, +}; + +static struct intc_vect vectors[] __initdata = { + INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), + INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), + INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), + INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), + + INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), + INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), + INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), + INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), + + INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109), + INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113), + INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117), + INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121), + INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125), + INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129), + INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133), + INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137), + INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141), + INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145), + INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149), + INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153), + INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157), + INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161), + INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165), + INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169), + + INTC_IRQ(USB, 170), + INTC_IRQ(VDC3, 171), INTC_IRQ(VDC3, 172), + INTC_IRQ(VDC3, 173), INTC_IRQ(VDC3, 174), + INTC_IRQ(CMT0, 175), INTC_IRQ(CMT1, 176), + INTC_IRQ(BSC, 177), INTC_IRQ(WDT, 178), + + INTC_IRQ(MTU0_ABCD, 179), INTC_IRQ(MTU0_ABCD, 180), + INTC_IRQ(MTU0_ABCD, 181), INTC_IRQ(MTU0_ABCD, 182), + INTC_IRQ(MTU0_VEF, 183), + INTC_IRQ(MTU0_VEF, 184), INTC_IRQ(MTU0_VEF, 185), + INTC_IRQ(MTU1_AB, 186), INTC_IRQ(MTU1_AB, 187), + INTC_IRQ(MTU1_VU, 188), INTC_IRQ(MTU1_VU, 189), + INTC_IRQ(MTU2_AB, 190), INTC_IRQ(MTU2_AB, 191), + INTC_IRQ(MTU2_VU, 192), INTC_IRQ(MTU2_VU, 193), + INTC_IRQ(MTU3_ABCD, 194), INTC_IRQ(MTU3_ABCD, 195), + INTC_IRQ(MTU3_ABCD, 196), INTC_IRQ(MTU3_ABCD, 197), + INTC_IRQ(MTU3_TCI3V, 198), + INTC_IRQ(MTU4_ABCD, 199), INTC_IRQ(MTU4_ABCD, 200), + INTC_IRQ(MTU4_ABCD, 201), INTC_IRQ(MTU4_ABCD, 202), + INTC_IRQ(MTU4_TCI4V, 203), + + INTC_IRQ(PWMT1, 204), INTC_IRQ(PWMT2, 205), + + INTC_IRQ(ADC_ADI, 206), + + INTC_IRQ(SSIF0, 207), INTC_IRQ(SSIF0, 208), + INTC_IRQ(SSIF0, 209), + INTC_IRQ(SSII1, 210), INTC_IRQ(SSII1, 211), + INTC_IRQ(SSII2, 212), INTC_IRQ(SSII2, 213), + INTC_IRQ(SSII3, 214), INTC_IRQ(SSII3, 215), + + INTC_IRQ(RSPDIF, 216), + + INTC_IRQ(IIC30, 217), INTC_IRQ(IIC30, 218), + INTC_IRQ(IIC30, 219), INTC_IRQ(IIC30, 220), + INTC_IRQ(IIC30, 221), + INTC_IRQ(IIC31, 222), INTC_IRQ(IIC31, 223), + INTC_IRQ(IIC31, 224), INTC_IRQ(IIC31, 225), + INTC_IRQ(IIC31, 226), + INTC_IRQ(IIC32, 227), INTC_IRQ(IIC32, 228), + INTC_IRQ(IIC32, 229), INTC_IRQ(IIC32, 230), + INTC_IRQ(IIC32, 231), + + INTC_IRQ(SCIF0_BRI, 232), INTC_IRQ(SCIF0_ERI, 233), + INTC_IRQ(SCIF0_RXI, 234), INTC_IRQ(SCIF0_TXI, 235), + INTC_IRQ(SCIF1_BRI, 236), INTC_IRQ(SCIF1_ERI, 237), + INTC_IRQ(SCIF1_RXI, 238), INTC_IRQ(SCIF1_TXI, 239), + INTC_IRQ(SCIF2_BRI, 240), INTC_IRQ(SCIF2_ERI, 241), + INTC_IRQ(SCIF2_RXI, 242), INTC_IRQ(SCIF2_TXI, 243), + INTC_IRQ(SCIF3_BRI, 244), INTC_IRQ(SCIF3_ERI, 245), + INTC_IRQ(SCIF3_RXI, 246), INTC_IRQ(SCIF3_TXI, 247), + INTC_IRQ(SCIF4_BRI, 248), INTC_IRQ(SCIF4_ERI, 249), + INTC_IRQ(SCIF4_RXI, 250), INTC_IRQ(SCIF4_TXI, 251), + INTC_IRQ(SCIF5_BRI, 252), INTC_IRQ(SCIF5_ERI, 253), + INTC_IRQ(SCIF5_RXI, 254), INTC_IRQ(SCIF5_TXI, 255), + INTC_IRQ(SCIF6_BRI, 256), INTC_IRQ(SCIF6_ERI, 257), + INTC_IRQ(SCIF6_RXI, 258), INTC_IRQ(SCIF6_TXI, 259), + INTC_IRQ(SCIF7_BRI, 260), INTC_IRQ(SCIF7_ERI, 261), + INTC_IRQ(SCIF7_RXI, 262), INTC_IRQ(SCIF7_TXI, 263), + + INTC_IRQ(SIO_FIFO, 264), + + INTC_IRQ(RSPIC0, 265), INTC_IRQ(RSPIC0, 266), + INTC_IRQ(RSPIC0, 267), + INTC_IRQ(RSPIC1, 268), INTC_IRQ(RSPIC1, 269), + INTC_IRQ(RSPIC1, 270), + + INTC_IRQ(RCAN0, 271), INTC_IRQ(RCAN0, 272), + INTC_IRQ(RCAN0, 273), INTC_IRQ(RCAN0, 274), + INTC_IRQ(RCAN0, 275), + INTC_IRQ(RCAN1, 276), INTC_IRQ(RCAN1, 277), + INTC_IRQ(RCAN1, 278), INTC_IRQ(RCAN1, 279), + INTC_IRQ(RCAN1, 280), + + INTC_IRQ(IEBC, 281), + + INTC_IRQ(CD_ROMD, 282), INTC_IRQ(CD_ROMD, 283), + INTC_IRQ(CD_ROMD, 284), INTC_IRQ(CD_ROMD, 285), + INTC_IRQ(CD_ROMD, 286), INTC_IRQ(CD_ROMD, 287), + + INTC_IRQ(NFMC, 288), INTC_IRQ(NFMC, 289), + INTC_IRQ(NFMC, 290), INTC_IRQ(NFMC, 291), + + INTC_IRQ(SDHI, 292), INTC_IRQ(SDHI, 293), + INTC_IRQ(SDHI, 294), + + INTC_IRQ(RTC, 296), INTC_IRQ(RTC, 297), + INTC_IRQ(RTC, 298), + + INTC_IRQ(SRCC0, 299), INTC_IRQ(SRCC0, 300), + INTC_IRQ(SRCC0, 301), INTC_IRQ(SRCC0, 302), + INTC_IRQ(SRCC0, 303), + INTC_IRQ(SRCC1, 304), INTC_IRQ(SRCC1, 305), + INTC_IRQ(SRCC1, 306), INTC_IRQ(SRCC1, 307), + INTC_IRQ(SRCC1, 308), + + INTC_IRQ(DCOMU, 310), INTC_IRQ(DCOMU, 311), + INTC_IRQ(DCOMU, 312), +}; + +static struct intc_group groups[] __initdata = { + INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, + PINT4, PINT5, PINT6, PINT7), + INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI), + INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI), + INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI), + INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI), + INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI), + INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI), + INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI), + INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI), +}; + +static struct intc_prio_reg prio_registers[] __initdata = { + { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, + { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, + { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } }, + { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } }, + { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } }, + { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8, DMAC9, + DMAC10, DMAC11 } }, + { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13, + DMAC14, DMAC15 } }, + { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC3, CMT0, CMT1 } }, + { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } }, + { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU1_AB, MTU1_VU, + MTU2_AB, MTU2_VU } }, + { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU3_ABCD, MTU3_TCI3V, + MTU4_ABCD, MTU4_TCI4V } }, + { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { PWMT1, PWMT2, ADC_ADI, 0 } }, + { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSIF0, SSII1, SSII2, SSII3 } }, + { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { RSPDIF, IIC30, IIC31, IIC32 } }, + { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { SCIF0, SCIF1, SCIF2, SCIF3 } }, + { 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SCIF4, SCIF5, SCIF6, SCIF7 } }, + { 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { SIO_FIFO, 0, RSPIC0, RSPIC1, } }, + { 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { RCAN0, RCAN1, IEBC, CD_ROMD } }, + { 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { NFMC, SDHI, RTC, 0 } }, + { 0xfffe0c20, 0, 16, 4, /* IPR22 */ { SRCC0, SRCC1, 0, DCOMU } }, +}; + +static struct intc_mask_reg mask_registers[] __initdata = { + { 0xfffe0808, 0, 16, /* PINTER */ + { 0, 0, 0, 0, 0, 0, 0, 0, + PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups, + mask_registers, prio_registers, NULL); + +static struct plat_sci_port scif0_platform_data = { + .mapbase = 0xfffe8000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | + SCSCR_REIE | SCSCR_TOIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { 233, 234, 235, 232 }, + .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +static struct plat_sci_port scif1_platform_data = { + .mapbase = 0xfffe8800, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | + SCSCR_REIE | SCSCR_TOIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { 237, 238, 239, 236 }, + .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +static struct plat_sci_port scif2_platform_data = { + .mapbase = 0xfffe9000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | + SCSCR_REIE | SCSCR_TOIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { 241, 242, 243, 240 }, + .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .dev = { + .platform_data = &scif2_platform_data, + }, +}; + +static struct plat_sci_port scif3_platform_data = { + .mapbase = 0xfffe9800, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | + SCSCR_REIE | SCSCR_TOIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { 245, 246, 247, 244 }, + .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, +}; + +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 3, + .dev = { + .platform_data = &scif3_platform_data, + }, +}; + +static struct plat_sci_port scif4_platform_data = { + .mapbase = 0xfffea000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | + SCSCR_REIE | SCSCR_TOIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { 249, 250, 251, 248 }, + .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, +}; + +static struct platform_device scif4_device = { + .name = "sh-sci", + .id = 4, + .dev = { + .platform_data = &scif4_platform_data, + }, +}; + +static struct plat_sci_port scif5_platform_data = { + .mapbase = 0xfffea800, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | + SCSCR_REIE | SCSCR_TOIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { 253, 254, 255, 252 }, + .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, +}; + +static struct platform_device scif5_device = { + .name = "sh-sci", + .id = 5, + .dev = { + .platform_data = &scif5_platform_data, + }, +}; + +static struct plat_sci_port scif6_platform_data = { + .mapbase = 0xfffeb000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | + SCSCR_REIE | SCSCR_TOIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { 257, 258, 259, 256 }, + .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, +}; + +static struct platform_device scif6_device = { + .name = "sh-sci", + .id = 6, + .dev = { + .platform_data = &scif6_platform_data, + }, +}; + +static struct plat_sci_port scif7_platform_data = { + .mapbase = 0xfffeb800, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | + SCSCR_REIE | SCSCR_TOIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { 261, 262, 263, 260 }, + .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, +}; + +static struct platform_device scif7_device = { + .name = "sh-sci", + .id = 7, + .dev = { + .platform_data = &scif7_platform_data, + }, +}; + +static struct sh_timer_config cmt0_platform_data = { + .channel_offset = 0x02, + .timer_bit = 0, + .clockevent_rating = 125, + .clocksource_rating = 0, /* disabled due to code generation issues */ +}; + +static struct resource cmt0_resources[] = { + [0] = { + .name = "CMT0", + .start = 0xfffec002, + .end = 0xfffec007, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 175, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cmt0_device = { + .name = "sh_cmt", + .id = 0, + .dev = { + .platform_data = &cmt0_platform_data, + }, + .resource = cmt0_resources, + .num_resources = ARRAY_SIZE(cmt0_resources), +}; + +static struct sh_timer_config cmt1_platform_data = { + .name = "CMT1", + .channel_offset = 0x08, + .timer_bit = 1, + .clockevent_rating = 125, + .clocksource_rating = 0, /* disabled due to code generation issues */ +}; + +static struct resource cmt1_resources[] = { + [0] = { + .name = "CMT1", + .start = 0xfffec008, + .end = 0xfffec00d, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 176, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cmt1_device = { + .name = "sh_cmt", + .id = 1, + .dev = { + .platform_data = &cmt1_platform_data, + }, + .resource = cmt1_resources, + .num_resources = ARRAY_SIZE(cmt1_resources), +}; + +static struct sh_timer_config mtu2_0_platform_data = { + .name = "MTU2_0", + .channel_offset = -0x80, + .timer_bit = 0, + .clockevent_rating = 200, +}; + +static struct resource mtu2_0_resources[] = { + [0] = { + .name = "MTU2_0", + .start = 0xfffe4300, + .end = 0xfffe4326, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 179, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mtu2_0_device = { + .name = "sh_mtu2", + .id = 0, + .dev = { + .platform_data = &mtu2_0_platform_data, + }, + .resource = mtu2_0_resources, + .num_resources = ARRAY_SIZE(mtu2_0_resources), +}; + +static struct sh_timer_config mtu2_1_platform_data = { + .name = "MTU2_1", + .channel_offset = -0x100, + .timer_bit = 1, + .clockevent_rating = 200, +}; + +static struct resource mtu2_1_resources[] = { + [0] = { + .name = "MTU2_1", + .start = 0xfffe4380, + .end = 0xfffe4390, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 186, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mtu2_1_device = { + .name = "sh_mtu2", + .id = 1, + .dev = { + .platform_data = &mtu2_1_platform_data, + }, + .resource = mtu2_1_resources, + .num_resources = ARRAY_SIZE(mtu2_1_resources), +}; + +static struct resource rtc_resources[] = { + [0] = { + .start = 0xfffe6000, + .end = 0xfffe6000 + 0x30 - 1, + .flags = IORESOURCE_IO, + }, + [1] = { + /* Shared Period/Carry/Alarm IRQ */ + .start = 296, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device rtc_device = { + .name = "sh-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; + +/* USB Host */ +static void usb_port_power(int port, int power) +{ + __raw_writew(0x200 , 0xffffc0c2) ; /* Initialise UACS25 */ +} + +static struct r8a66597_platdata r8a66597_data = { + .on_chip = 1, + .endian = 1, + .port_power = usb_port_power, +}; + +static struct resource r8a66597_usb_host_resources[] = { + [0] = { + .start = 0xffffc000, + .end = 0xffffc0e4, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 170, + .end = 170, + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct platform_device r8a66597_usb_host_device = { + .name = "r8a66597_hcd", + .id = 0, + .dev = { + .dma_mask = NULL, /* not use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &r8a66597_data, + }, + .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources), + .resource = r8a66597_usb_host_resources, +}; + +static struct platform_device *sh7264_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &scif6_device, + &scif7_device, + &cmt0_device, + &cmt1_device, + &mtu2_0_device, + &mtu2_1_device, + &rtc_device, + &r8a66597_usb_host_device, +}; + +static int __init sh7264_devices_setup(void) +{ + return platform_add_devices(sh7264_devices, + ARRAY_SIZE(sh7264_devices)); +} +arch_initcall(sh7264_devices_setup); + +void __init plat_irq_setup(void) +{ + register_intc_controller(&intc_desc); +} + +static struct platform_device *sh7264_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &scif6_device, + &scif7_device, + &cmt0_device, + &cmt1_device, + &mtu2_0_device, + &mtu2_1_device, +}; + +void __init plat_early_device_setup(void) +{ + early_platform_add_devices(sh7264_early_devices, + ARRAY_SIZE(sh7264_early_devices)); +} -- cgit v0.10.2 From d584e204ff574b43d4dcaa87ae233c4e9d08e1fb Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Wed, 9 May 2012 07:59:28 +0100 Subject: sh: Add RSK2+SH7264 board The RSK2+SH7264 board uses the sh7264 processor. It is often referred to as just rsk7264. NOR Flash, SDRAM, serial, USB Host and ethernet are working. Signed-off-by: Phil Edworthy Signed-off-by: Paul Mundt diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index d893411..ee92f42 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -133,7 +133,7 @@ config SH_RTS7751R2D config SH_RSK bool "Renesas Starter Kit" - depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203 + depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7264 help Select this option if configuring for any of the RSK+ MCU evaluation platforms. diff --git a/arch/sh/boards/mach-rsk/Kconfig b/arch/sh/boards/mach-rsk/Kconfig index aeff3b0..4abbdee 100644 --- a/arch/sh/boards/mach-rsk/Kconfig +++ b/arch/sh/boards/mach-rsk/Kconfig @@ -13,6 +13,10 @@ config SH_RSK7203 select ARCH_REQUIRE_GPIOLIB depends on CPU_SUBTYPE_SH7203 +config SH_RSK7264 + bool "RSK2+SH7264" + depends on CPU_SUBTYPE_SH7264 + endchoice endif diff --git a/arch/sh/boards/mach-rsk/Makefile b/arch/sh/boards/mach-rsk/Makefile index 498da75..bae6ae4 100644 --- a/arch/sh/boards/mach-rsk/Makefile +++ b/arch/sh/boards/mach-rsk/Makefile @@ -1,2 +1,3 @@ obj-y := setup.o obj-$(CONFIG_SH_RSK7203) += devices-rsk7203.o +obj-$(CONFIG_SH_RSK7264) += devices-rsk7264.o diff --git a/arch/sh/boards/mach-rsk/devices-rsk7264.c b/arch/sh/boards/mach-rsk/devices-rsk7264.c new file mode 100644 index 0000000..7251e37 --- /dev/null +++ b/arch/sh/boards/mach-rsk/devices-rsk7264.c @@ -0,0 +1,58 @@ +/* + * RSK+SH7264 Support. + * + * Copyright (C) 2012 Renesas Electronics Europe + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct smsc911x_platform_config smsc911x_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_16BIT | SMSC911X_SWAP_FIFO, +}; + +static struct resource smsc911x_resources[] = { + [0] = { + .start = 0x28000000, + .end = 0x280000ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 65, + .end = 65, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static struct platform_device *rsk7264_devices[] __initdata = { + &smsc911x_device, +}; + +static int __init rsk7264_devices_setup(void) +{ + return platform_add_devices(rsk7264_devices, + ARRAY_SIZE(rsk7264_devices)); +} +device_initcall(rsk7264_devices_setup); diff --git a/arch/sh/configs/rsk7264_defconfig b/arch/sh/configs/rsk7264_defconfig new file mode 100644 index 0000000..1600426 --- /dev/null +++ b/arch/sh/configs/rsk7264_defconfig @@ -0,0 +1,80 @@ +CONFIG_LOCALVERSION="uClinux RSK2+SH7264" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_IKCONFIG=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_NAMESPACES=y +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +CONFIG_PERF_COUNTERS=y +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_SLAB=y +CONFIG_MMAP_ALLOW_UNINITIALIZED=y +CONFIG_PROFILING=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_CPU_SUBTYPE_SH7264=y +CONFIG_MEMORY_START=0x0c000000 +CONFIG_FLATMEM_MANUAL=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_SH_RSK=y +# CONFIG_SH_TIMER_MTU2 is not set +CONFIG_BINFMT_FLAT=y +CONFIG_NET=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_NETDEVICES=y +CONFIG_SMSC911X=y +CONFIG_SMSC_PHY=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=8 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +# CONFIG_HWMON is not set +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_R8A66597_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DEBUG=y +CONFIG_USB_LIBUSUAL=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_VFAT_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_ENABLE_MUST_CHECK is not set +# CONFIG_FTRACE is not set diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types index 6dd56c4..d007c81 100644 --- a/arch/sh/tools/mach-types +++ b/arch/sh/tools/mach-types @@ -51,6 +51,7 @@ SDK7780 SH_SDK7780 MIGOR SH_MIGOR RSK7201 SH_RSK7201 RSK7203 SH_RSK7203 +RSK7264 SH_RSK7264 AP325RXA SH_AP325RXA SH2007 SH_SH2007 SH7757LCR SH_SH7757LCR -- cgit v0.10.2 From 41797f75486d8ca3b98d7658c2a506ac7879a8e5 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Wed, 9 May 2012 07:59:29 +0100 Subject: sh: Add pinmux for sh7264 Signed-off-by: Phil Edworthy Signed-off-by: Paul Mundt diff --git a/arch/sh/boards/mach-rsk/Kconfig b/arch/sh/boards/mach-rsk/Kconfig index 4abbdee..4315af5 100644 --- a/arch/sh/boards/mach-rsk/Kconfig +++ b/arch/sh/boards/mach-rsk/Kconfig @@ -15,6 +15,7 @@ config SH_RSK7203 config SH_RSK7264 bool "RSK2+SH7264" + select ARCH_REQUIRE_GPIOLIB depends on CPU_SUBTYPE_SH7264 endchoice diff --git a/arch/sh/include/cpu-sh2a/cpu/sh7264.h b/arch/sh/include/cpu-sh2a/cpu/sh7264.h new file mode 100644 index 0000000..4d1ef6d --- /dev/null +++ b/arch/sh/include/cpu-sh2a/cpu/sh7264.h @@ -0,0 +1,176 @@ +#ifndef __ASM_SH7264_H__ +#define __ASM_SH7264_H__ + +enum { + /* Port A */ + GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0, + + /* Port B */ + GPIO_PB22, GPIO_PB21, GPIO_PB20, + GPIO_PB19, GPIO_PB18, GPIO_PB17, GPIO_PB16, + GPIO_PB15, GPIO_PB14, GPIO_PB13, GPIO_PB12, + GPIO_PB11, GPIO_PB10, GPIO_PB9, GPIO_PB8, + GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4, + GPIO_PB3, GPIO_PB2, GPIO_PB1, + + /* Port C */ + GPIO_PC10, GPIO_PC9, GPIO_PC8, + GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4, + GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0, + + /* Port D */ + GPIO_PD15, GPIO_PD14, GPIO_PD13, GPIO_PD12, + GPIO_PD11, GPIO_PD10, GPIO_PD9, GPIO_PD8, + GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4, + GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0, + + /* Port E */ + GPIO_PE5, GPIO_PE4, + GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0, + + /* Port F */ + GPIO_PF12, + GPIO_PF11, GPIO_PF10, GPIO_PF9, GPIO_PF8, + GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4, + GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0, + + /* Port G */ + GPIO_PG24, + GPIO_PG23, GPIO_PG22, GPIO_PG21, GPIO_PG20, + GPIO_PG19, GPIO_PG18, GPIO_PG17, GPIO_PG16, + GPIO_PG15, GPIO_PG14, GPIO_PG13, GPIO_PG12, + GPIO_PG11, GPIO_PG10, GPIO_PG9, GPIO_PG8, + GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4, + GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0, + + /* Port H */ + GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4, + GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0, + + /* Port I - not on device */ + + /* Port J */ + GPIO_PJ11, GPIO_PJ10, GPIO_PJ9, GPIO_PJ8, + GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4, + GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0, + + /* Port K */ + GPIO_PK11, GPIO_PK10, GPIO_PK9, GPIO_PK8, + GPIO_PK7, GPIO_PK6, GPIO_PK5, GPIO_PK4, + GPIO_PK3, GPIO_PK2, GPIO_PK1, GPIO_PK0, + + /* INTC: IRQ and PINT on PB/PD/PE */ + GPIO_FN_PINT7_PG, GPIO_FN_PINT6_PG, GPIO_FN_PINT5_PG, GPIO_FN_PINT4_PG, + GPIO_FN_PINT3_PG, GPIO_FN_PINT2_PG, GPIO_FN_PINT1_PG, + + GPIO_FN_IRQ7_PC, GPIO_FN_IRQ6_PC, GPIO_FN_IRQ5_PC, GPIO_FN_IRQ4_PC, + GPIO_FN_IRQ3_PG, GPIO_FN_IRQ2_PG, GPIO_FN_IRQ1_PJ, GPIO_FN_IRQ0_PJ, + GPIO_FN_IRQ3_PE, GPIO_FN_IRQ2_PE, GPIO_FN_IRQ1_PE, GPIO_FN_IRQ0_PE, + + /* WDT */ + GPIO_FN_WDTOVF, + + /* CAN */ + GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1, + GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1, + + /* DMAC */ + GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0, + GPIO_FN_TEND1, GPIO_FN_DACK1, GPIO_FN_DREQ1, + + /* ADC */ + GPIO_FN_ADTRG, + + /* BSC */ + + GPIO_FN_A25, GPIO_FN_A24, + GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20, + GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16, + GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12, + GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8, + GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4, + GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0, + GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12, + GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8, + GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4, + GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0, + + GPIO_FN_BS, + GPIO_FN_CS4, GPIO_FN_CS3, GPIO_FN_CS2, GPIO_FN_CS1, GPIO_FN_CS0, + GPIO_FN_CS6CE1B, GPIO_FN_CS5CE1A, + GPIO_FN_CE2A, GPIO_FN_CE2B, + GPIO_FN_RD, GPIO_FN_RDWR, + GPIO_FN_ICIOWRAH, GPIO_FN_ICIORD, + GPIO_FN_WE1DQMUWE, GPIO_FN_WE0DQML, + GPIO_FN_RAS, GPIO_FN_CAS, GPIO_FN_CKE, + GPIO_FN_WAIT, GPIO_FN_BREQ, GPIO_FN_BACK, + GPIO_FN_IOIS16, + + /* TMU */ + GPIO_FN_TIOC4D, GPIO_FN_TIOC4C, GPIO_FN_TIOC4B, GPIO_FN_TIOC4A, + GPIO_FN_TIOC3D, GPIO_FN_TIOC3C, GPIO_FN_TIOC3B, GPIO_FN_TIOC3A, + GPIO_FN_TIOC2B, GPIO_FN_TIOC1B, GPIO_FN_TIOC2A, GPIO_FN_TIOC1A, + GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A, + GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA, + + /* SSU */ + GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD, + GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF, + GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD, + GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF, + + /* SCIF */ + GPIO_FN_SCK0, GPIO_FN_SCK1, GPIO_FN_SCK2, GPIO_FN_SCK3, + GPIO_FN_RXD0, GPIO_FN_RXD1, GPIO_FN_RXD2, GPIO_FN_RXD3, + GPIO_FN_TXD0, GPIO_FN_TXD1, GPIO_FN_TXD2, GPIO_FN_TXD3, + GPIO_FN_RXD4, GPIO_FN_RXD5, GPIO_FN_RXD6, GPIO_FN_RXD7, + GPIO_FN_TXD4, GPIO_FN_TXD5, GPIO_FN_TXD6, GPIO_FN_TXD7, + GPIO_FN_RTS1, GPIO_FN_RTS3, GPIO_FN_CTS1, GPIO_FN_CTS3, + + /* RSPI */ + GPIO_FN_RSPCK0, GPIO_FN_MOSI0, + GPIO_FN_MISO0_PF12, GPIO_FN_MISO1, + GPIO_FN_SSL00, + GPIO_FN_RSPCK1, GPIO_FN_MOSI1, + GPIO_FN_MISO1_PG19, GPIO_FN_SSL10, + + /* IIC3 */ + GPIO_FN_SCL0, GPIO_FN_SCL1, GPIO_FN_SCL2, + GPIO_FN_SDA2, GPIO_FN_SDA1, GPIO_FN_SDA0, + + /* SSI */ + GPIO_FN_SSISCK0, GPIO_FN_SSIWS0, GPIO_FN_SSITXD0, GPIO_FN_SSIRXD0, + GPIO_FN_SSIWS1, GPIO_FN_SSIWS2, GPIO_FN_SSIWS3, + GPIO_FN_SSISCK1, GPIO_FN_SSISCK2, GPIO_FN_SSISCK3, + GPIO_FN_SSIDATA1, GPIO_FN_SSIDATA2, GPIO_FN_SSIDATA3, + GPIO_FN_AUDIO_CLK, + + /* SIOF */ + GPIO_FN_SIOFTXD, GPIO_FN_SIOFRXD, GPIO_FN_SIOFSYNC, GPIO_FN_SIOFSCK, + + /* SPDIF */ + GPIO_FN_SPDIF_IN, + GPIO_FN_SPDIF_OUT, + + /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ + GPIO_FN_FCE, + GPIO_FN_FRB, + + /* VDC3 */ + GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC, + GPIO_FN_DV_DATA7, GPIO_FN_DV_DATA6, GPIO_FN_DV_DATA5, GPIO_FN_DV_DATA4, + GPIO_FN_DV_DATA3, GPIO_FN_DV_DATA2, GPIO_FN_DV_DATA1, GPIO_FN_DV_DATA0, + GPIO_FN_LCD_CLK, GPIO_FN_LCD_EXTCLK, + GPIO_FN_LCD_VSYNC, GPIO_FN_LCD_HSYNC, GPIO_FN_LCD_DE, + GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14, + GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12, + GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10, + GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8, + GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6, + GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4, + GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2, + GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0, + GPIO_FN_LCD_M_DISP, +}; + +#endif /* __ASM_SH7264_H__ */ diff --git a/arch/sh/kernel/cpu/sh2a/Makefile b/arch/sh/kernel/cpu/sh2a/Makefile index 617ef25..64b0986 100644 --- a/arch/sh/kernel/cpu/sh2a/Makefile +++ b/arch/sh/kernel/cpu/sh2a/Makefile @@ -17,5 +17,6 @@ obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o # Pinmux setup pinmux-$(CONFIG_CPU_SUBTYPE_SH7203) := pinmux-sh7203.o +pinmux-$(CONFIG_CPU_SUBTYPE_SH7264) := pinmux-sh7264.o obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y) diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c new file mode 100644 index 0000000..b055b55 --- /dev/null +++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c @@ -0,0 +1,2136 @@ +/* + * SH7264 Pinmux + * + * Copyright (C) 2012 Renesas Electronics Europe Ltd + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + /* Port A */ + PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA, + /* Port B */ + PB22_DATA, PB21_DATA, PB20_DATA, + PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA, + PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA, + PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA, + PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, + PB3_DATA, PB2_DATA, PB1_DATA, + /* Port C */ + PC10_DATA, PC9_DATA, PC8_DATA, + PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, + PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA, + /* Port D */ + PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA, + PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA, + PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, + PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, + /* Port E */ + PE5_DATA, PE4_DATA, + PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA, + /* Port F */ + PF12_DATA, + PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA, + PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, + PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, + /* Port G */ + PG24_DATA, + PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA, + PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA, + PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA, + PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA, + PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, + PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA, + /* Port H */ + /* NOTE - Port H does not have a Data Register, but PH Data is + connected to PH Port Register */ + PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA, + PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, + /* Port I - not on device */ + /* Port J */ + PJ12_DATA, + PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA, + PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, + PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA, + /* Port K */ + PK12_DATA, + PK11_DATA, PK10_DATA, PK9_DATA, PK8_DATA, + PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA, + PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA, + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + FORCE_IN, + /* Port A */ + PA3_IN, PA2_IN, PA1_IN, PA0_IN, + /* Port B */ + PB22_IN, PB21_IN, PB20_IN, + PB19_IN, PB18_IN, PB17_IN, PB16_IN, + PB15_IN, PB14_IN, PB13_IN, PB12_IN, + PB11_IN, PB10_IN, PB9_IN, PB8_IN, + PB7_IN, PB6_IN, PB5_IN, PB4_IN, + PB3_IN, PB2_IN, PB1_IN, + /* Port C */ + PC10_IN, PC9_IN, PC8_IN, + PC7_IN, PC6_IN, PC5_IN, PC4_IN, + PC3_IN, PC2_IN, PC1_IN, PC0_IN, + /* Port D */ + PD15_IN, PD14_IN, PD13_IN, PD12_IN, + PD11_IN, PD10_IN, PD9_IN, PD8_IN, + PD7_IN, PD6_IN, PD5_IN, PD4_IN, + PD3_IN, PD2_IN, PD1_IN, PD0_IN, + /* Port E */ + PE5_IN, PE4_IN, + PE3_IN, PE2_IN, PE1_IN, PE0_IN, + /* Port F */ + PF12_IN, + PF11_IN, PF10_IN, PF9_IN, PF8_IN, + PF7_IN, PF6_IN, PF5_IN, PF4_IN, + PF3_IN, PF2_IN, PF1_IN, PF0_IN, + /* Port G */ + PG24_IN, + PG23_IN, PG22_IN, PG21_IN, PG20_IN, + PG19_IN, PG18_IN, PG17_IN, PG16_IN, + PG15_IN, PG14_IN, PG13_IN, PG12_IN, + PG11_IN, PG10_IN, PG9_IN, PG8_IN, + PG7_IN, PG6_IN, PG5_IN, PG4_IN, + PG3_IN, PG2_IN, PG1_IN, PG0_IN, + /* Port H - Port H does not have a Data Register */ + /* Port I - not on device */ + /* Port J */ + PJ12_IN, + PJ11_IN, PJ10_IN, PJ9_IN, PJ8_IN, + PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN, + PJ3_IN, PJ2_IN, PJ1_IN, PJ0_IN, + /* Port K */ + PK12_IN, + PK11_IN, PK10_IN, PK9_IN, PK8_IN, + PK7_IN, PK6_IN, PK5_IN, PK4_IN, + PK3_IN, PK2_IN, PK1_IN, PK0_IN, + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + FORCE_OUT, + /* Port A */ + PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT, + /* Port B */ + PB22_OUT, PB21_OUT, PB20_OUT, + PB19_OUT, PB18_OUT, PB17_OUT, PB16_OUT, + PB15_OUT, PB14_OUT, PB13_OUT, PB12_OUT, + PB11_OUT, PB10_OUT, PB9_OUT, PB8_OUT, + PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT, + PB3_OUT, PB2_OUT, PB1_OUT, + /* Port C */ + PC10_OUT, PC9_OUT, PC8_OUT, + PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT, + PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT, + /* Port D */ + PD15_OUT, PD14_OUT, PD13_OUT, PD12_OUT, + PD11_OUT, PD10_OUT, PD9_OUT, PD8_OUT, + PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT, + PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT, + /* Port E */ + PE5_OUT, PE4_OUT, + PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT, + /* Port F */ + PF12_OUT, + PF11_OUT, PF10_OUT, PF9_OUT, PF8_OUT, + PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT, + PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT, + /* Port G */ + PG24_OUT, + PG23_OUT, PG22_OUT, PG21_OUT, PG20_OUT, + PG19_OUT, PG18_OUT, PG17_OUT, PG16_OUT, + PG15_OUT, PG14_OUT, PG13_OUT, PG12_OUT, + PG11_OUT, PG10_OUT, PG9_OUT, PG8_OUT, + PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT, + PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT, + /* Port H - Port H does not have a Data Register */ + /* Port I - not on device */ + /* Port J */ + PJ12_OUT, + PJ11_OUT, PJ10_OUT, PJ9_OUT, PJ8_OUT, + PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT, + PJ3_OUT, PJ2_OUT, PJ1_OUT, PJ0_OUT, + /* Port K */ + PK12_OUT, + PK11_OUT, PK10_OUT, PK9_OUT, PK8_OUT, + PK7_OUT, PK6_OUT, PK5_OUT, PK4_OUT, + PK3_OUT, PK2_OUT, PK1_OUT, PK0_OUT, + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + /* Port A */ + PA3_IOR_IN, PA3_IOR_OUT, + PA2_IOR_IN, PA2_IOR_OUT, + PA1_IOR_IN, PA1_IOR_OUT, + PA0_IOR_IN, PA0_IOR_OUT, + + /* Port B */ + PB11_IOR_IN, PB11_IOR_OUT, + PB10_IOR_IN, PB10_IOR_OUT, + PB9_IOR_IN, PB9_IOR_OUT, + PB8_IOR_IN, PB8_IOR_OUT, + + PB22MD_00, PB22MD_01, PB22MD_10, + PB21MD_0, PB21MD_1, + PB20MD_0, PB20MD_1, + PB19MD_00, PB19MD_01, PB19MD_10, PB19MD_11, + PB18MD_00, PB18MD_01, PB18MD_10, PB18MD_11, + PB17MD_00, PB17MD_01, PB17MD_10, PB17MD_11, + PB16MD_00, PB16MD_01, PB16MD_10, PB16MD_11, + PB15MD_00, PB15MD_01, PB15MD_10, PB15MD_11, + PB14MD_00, PB14MD_01, PB14MD_10, PB14MD_11, + PB13MD_00, PB13MD_01, PB13MD_10, PB13MD_11, + PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11, + PB11MD_00, PB11MD_01, PB11MD_10, PB11MD_11, + PB10MD_00, PB10MD_01, PB10MD_10, PB10MD_11, + PB9MD_00, PB9MD_01, PB9MD_10, PB9MD_11, + PB8MD_00, PB8MD_01, PB8MD_10, PB8MD_11, + PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11, + PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11, + PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11, + PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11, + PB3MD_0, PB3MD_1, + PB2MD_0, PB2MD_1, + PB1MD_0, PB1MD_1, + + /* Port C */ + PC14_IOR_IN, PC14_IOR_OUT, + PC13_IOR_IN, PC13_IOR_OUT, + PC12_IOR_IN, PC12_IOR_OUT, + PC11_IOR_IN, PC11_IOR_OUT, + PC10_IOR_IN, PC10_IOR_OUT, + PC9_IOR_IN, PC9_IOR_OUT, + PC8_IOR_IN, PC8_IOR_OUT, + PC7_IOR_IN, PC7_IOR_OUT, + PC6_IOR_IN, PC6_IOR_OUT, + PC5_IOR_IN, PC5_IOR_OUT, + PC4_IOR_IN, PC4_IOR_OUT, + PC3_IOR_IN, PC3_IOR_OUT, + PC2_IOR_IN, PC2_IOR_OUT, + PC1_IOR_IN, PC1_IOR_OUT, + PC0_IOR_IN, PC0_IOR_OUT, + + PC10MD_0, PC10MD_1, + PC9MD_0, PC9MD_1, + PC8MD_00, PC8MD_01, PC8MD_10, PC8MD_11, + PC7MD_00, PC7MD_01, PC7MD_10, PC7MD_11, + PC6MD_00, PC6MD_01, PC6MD_10, PC6MD_11, + PC5MD_00, PC5MD_01, PC5MD_10, PC5MD_11, + PC4MD_0, PC4MD_1, + PC3MD_0, PC3MD_1, + PC2MD_0, PC2MD_1, + PC1MD_0, PC1MD_1, + PC0MD_0, PC0MD_1, + + /* Port D */ + PD15_IOR_IN, PD15_IOR_OUT, + PD14_IOR_IN, PD14_IOR_OUT, + PD13_IOR_IN, PD13_IOR_OUT, + PD12_IOR_IN, PD12_IOR_OUT, + PD11_IOR_IN, PD11_IOR_OUT, + PD10_IOR_IN, PD10_IOR_OUT, + PD9_IOR_IN, PD9_IOR_OUT, + PD8_IOR_IN, PD8_IOR_OUT, + PD7_IOR_IN, PD7_IOR_OUT, + PD6_IOR_IN, PD6_IOR_OUT, + PD5_IOR_IN, PD5_IOR_OUT, + PD4_IOR_IN, PD4_IOR_OUT, + PD3_IOR_IN, PD3_IOR_OUT, + PD2_IOR_IN, PD2_IOR_OUT, + PD1_IOR_IN, PD1_IOR_OUT, + PD0_IOR_IN, PD0_IOR_OUT, + + PD15MD_00, PD15MD_01, PD15MD_10, PD15MD_11, + PD14MD_00, PD14MD_01, PD14MD_10, PD14MD_11, + PD13MD_00, PD13MD_01, PD13MD_10, PD13MD_11, + PD12MD_00, PD12MD_01, PD12MD_10, PD12MD_11, + PD11MD_00, PD11MD_01, PD11MD_10, PD11MD_11, + PD10MD_00, PD10MD_01, PD10MD_10, PD10MD_11, + PD9MD_00, PD9MD_01, PD9MD_10, PD9MD_11, + PD8MD_00, PD8MD_01, PD8MD_10, PD8MD_11, + PD7MD_00, PD7MD_01, PD7MD_10, PD7MD_11, + PD6MD_00, PD6MD_01, PD6MD_10, PD6MD_11, + PD5MD_00, PD5MD_01, PD5MD_10, PD5MD_11, + PD4MD_00, PD4MD_01, PD4MD_10, PD4MD_11, + PD3MD_00, PD3MD_01, PD3MD_10, PD3MD_11, + PD2MD_00, PD2MD_01, PD2MD_10, PD2MD_11, + PD1MD_00, PD1MD_01, PD1MD_10, PD1MD_11, + PD0MD_00, PD0MD_01, PD0MD_10, PD0MD_11, + + /* Port E */ + PE5_IOR_IN, PE5_IOR_OUT, + PE4_IOR_IN, PE4_IOR_OUT, + PE3_IOR_IN, PE3_IOR_OUT, + PE2_IOR_IN, PE2_IOR_OUT, + PE1_IOR_IN, PE1_IOR_OUT, + PE0_IOR_IN, PE0_IOR_OUT, + + PE5MD_00, PE5MD_01, PE5MD_10, PE5MD_11, + PE4MD_00, PE4MD_01, PE4MD_10, PE4MD_11, + PE3MD_00, PE3MD_01, PE3MD_10, PE3MD_11, + PE2MD_00, PE2MD_01, PE2MD_10, PE2MD_11, + PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011, + PE1MD_100, PE1MD_101, PE1MD_110, PE1MD_111, + PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, + + /* Port F */ + PF12_IOR_IN, PF12_IOR_OUT, + PF11_IOR_IN, PF11_IOR_OUT, + PF10_IOR_IN, PF10_IOR_OUT, + PF9_IOR_IN, PF9_IOR_OUT, + PF8_IOR_IN, PF8_IOR_OUT, + PF7_IOR_IN, PF7_IOR_OUT, + PF6_IOR_IN, PF6_IOR_OUT, + PF5_IOR_IN, PF5_IOR_OUT, + PF4_IOR_IN, PF4_IOR_OUT, + PF3_IOR_IN, PF3_IOR_OUT, + PF2_IOR_IN, PF2_IOR_OUT, + PF1_IOR_IN, PF1_IOR_OUT, + PF0_IOR_IN, PF0_IOR_OUT, + + PF12MD_000, PF12MD_001, PF12MD_010, PF12MD_011, + PF12MD_100, PF12MD_101, PF12MD_110, PF12MD_111, + PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011, + PF11MD_100, PF11MD_101, PF11MD_110, PF11MD_111, + PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011, + PF10MD_100, PF10MD_101, PF10MD_110, PF10MD_111, + PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011, + PF9MD_100, PF9MD_101, PF9MD_110, PF9MD_111, + PF8MD_00, PF8MD_01, PF8MD_10, PF8MD_11, + PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011, + PF7MD_100, PF7MD_101, PF7MD_110, PF7MD_111, + PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011, + PF6MD_100, PF6MD_101, PF6MD_110, PF6MD_111, + PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011, + PF5MD_100, PF5MD_101, PF5MD_110, PF5MD_111, + PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011, + PF4MD_100, PF4MD_101, PF4MD_110, PF4MD_111, + PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011, + PF3MD_100, PF3MD_101, PF3MD_110, PF3MD_111, + PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011, + PF2MD_100, PF2MD_101, PF2MD_110, PF2MD_111, + PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011, + PF1MD_100, PF1MD_101, PF1MD_110, PF1MD_111, + PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011, + PF0MD_100, PF0MD_101, PF0MD_110, PF0MD_111, + + /* Port G */ + PG24_IOR_IN, PG24_IOR_OUT, + PG23_IOR_IN, PG23_IOR_OUT, + PG22_IOR_IN, PG22_IOR_OUT, + PG21_IOR_IN, PG21_IOR_OUT, + PG20_IOR_IN, PG20_IOR_OUT, + PG19_IOR_IN, PG19_IOR_OUT, + PG18_IOR_IN, PG18_IOR_OUT, + PG17_IOR_IN, PG17_IOR_OUT, + PG16_IOR_IN, PG16_IOR_OUT, + PG15_IOR_IN, PG15_IOR_OUT, + PG14_IOR_IN, PG14_IOR_OUT, + PG13_IOR_IN, PG13_IOR_OUT, + PG12_IOR_IN, PG12_IOR_OUT, + PG11_IOR_IN, PG11_IOR_OUT, + PG10_IOR_IN, PG10_IOR_OUT, + PG9_IOR_IN, PG9_IOR_OUT, + PG8_IOR_IN, PG8_IOR_OUT, + PG7_IOR_IN, PG7_IOR_OUT, + PG6_IOR_IN, PG6_IOR_OUT, + PG5_IOR_IN, PG5_IOR_OUT, + PG4_IOR_IN, PG4_IOR_OUT, + PG3_IOR_IN, PG3_IOR_OUT, + PG2_IOR_IN, PG2_IOR_OUT, + PG1_IOR_IN, PG1_IOR_OUT, + PG0_IOR_IN, PG0_IOR_OUT, + + PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, + PG23MD_00, PG23MD_01, PG23MD_10, PG23MD_11, + PG22MD_00, PG22MD_01, PG22MD_10, PG22MD_11, + PG21MD_00, PG21MD_01, PG21MD_10, PG21MD_11, + PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011, + PG20MD_100, PG20MD_101, PG20MD_110, PG20MD_111, + PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011, + PG19MD_100, PG19MD_101, PG19MD_110, PG19MD_111, + PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011, + PG18MD_100, PG18MD_101, PG18MD_110, PG18MD_111, + PG17MD_000, PG17MD_001, PG17MD_010, PG17MD_011, + PG17MD_100, PG17MD_101, PG17MD_110, PG17MD_111, + PG16MD_000, PG16MD_001, PG16MD_010, PG16MD_011, + PG16MD_100, PG16MD_101, PG16MD_110, PG16MD_111, + PG15MD_000, PG15MD_001, PG15MD_010, PG15MD_011, + PG15MD_100, PG15MD_101, PG15MD_110, PG15MD_111, + PG14MD_000, PG14MD_001, PG14MD_010, PG14MD_011, + PG14MD_100, PG14MD_101, PG14MD_110, PG14MD_111, + PG13MD_000, PG13MD_001, PG13MD_010, PG13MD_011, + PG13MD_100, PG13MD_101, PG13MD_110, PG13MD_111, + PG12MD_000, PG12MD_001, PG12MD_010, PG12MD_011, + PG12MD_100, PG12MD_101, PG12MD_110, PG12MD_111, + PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011, + PG11MD_100, PG11MD_101, PG11MD_110, PG11MD_111, + PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011, + PG10MD_100, PG10MD_101, PG10MD_110, PG10MD_111, + PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011, + PG9MD_100, PG9MD_101, PG9MD_110, PG9MD_111, + PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011, + PG8MD_100, PG8MD_101, PG8MD_110, PG8MD_111, + PG7MD_00, PG7MD_01, PG7MD_10, PG7MD_11, + PG6MD_00, PG6MD_01, PG6MD_10, PG6MD_11, + PG5MD_00, PG5MD_01, PG5MD_10, PG5MD_11, + PG4MD_00, PG4MD_01, PG4MD_10, PG4MD_11, + PG3MD_00, PG3MD_01, PG3MD_10, PG3MD_11, + PG2MD_00, PG2MD_01, PG2MD_10, PG2MD_11, + PG1MD_00, PG1MD_01, PG1MD_10, PG1MD_11, + PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011, + PG0MD_100, PG0MD_101, PG0MD_110, PG0MD_111, + + /* Port H */ + PH7MD_0, PH7MD_1, + PH6MD_0, PH6MD_1, + PH5MD_0, PH5MD_1, + PH4MD_0, PH4MD_1, + PH3MD_0, PH3MD_1, + PH2MD_0, PH2MD_1, + PH1MD_0, PH1MD_1, + PH0MD_0, PH0MD_1, + + /* Port I - not on device */ + + /* Port J */ + PJ11_IOR_IN, PJ11_IOR_OUT, + PJ10_IOR_IN, PJ10_IOR_OUT, + PJ9_IOR_IN, PJ9_IOR_OUT, + PJ8_IOR_IN, PJ8_IOR_OUT, + PJ7_IOR_IN, PJ7_IOR_OUT, + PJ6_IOR_IN, PJ6_IOR_OUT, + PJ5_IOR_IN, PJ5_IOR_OUT, + PJ4_IOR_IN, PJ4_IOR_OUT, + PJ3_IOR_IN, PJ3_IOR_OUT, + PJ2_IOR_IN, PJ2_IOR_OUT, + PJ1_IOR_IN, PJ1_IOR_OUT, + PJ0_IOR_IN, PJ0_IOR_OUT, + + PJ11MD_00, PJ11MD_01, PJ11MD_10, PJ11MD_11, + PJ10MD_00, PJ10MD_01, PJ10MD_10, PJ10MD_11, + PJ9MD_00, PJ9MD_01, PJ9MD_10, PJ9MD_11, + PJ8MD_00, PJ8MD_01, PJ8MD_10, PJ8MD_11, + PJ7MD_00, PJ7MD_01, PJ7MD_10, PJ7MD_11, + PJ6MD_00, PJ6MD_01, PJ6MD_10, PJ6MD_11, + PJ5MD_00, PJ5MD_01, PJ5MD_10, PJ5MD_11, + PJ4MD_00, PJ4MD_01, PJ4MD_10, PJ4MD_11, + PJ3MD_00, PJ3MD_01, PJ3MD_10, PJ3MD_11, + PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011, + PJ2MD_100, PJ2MD_101, PJ2MD_110, PJ2MD_111, + PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011, + PJ1MD_100, PJ1MD_101, PJ1MD_110, PJ1MD_111, + PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011, + PJ0MD_100, PJ0MD_101, PJ0MD_110, PJ0MD_111, + + /* Port K */ + PK11_IOR_IN, PK11_IOR_OUT, + PK10_IOR_IN, PK10_IOR_OUT, + PK9_IOR_IN, PK9_IOR_OUT, + PK8_IOR_IN, PK8_IOR_OUT, + PK7_IOR_IN, PK7_IOR_OUT, + PK6_IOR_IN, PK6_IOR_OUT, + PK5_IOR_IN, PK5_IOR_OUT, + PK4_IOR_IN, PK4_IOR_OUT, + PK3_IOR_IN, PK3_IOR_OUT, + PK2_IOR_IN, PK2_IOR_OUT, + PK1_IOR_IN, PK1_IOR_OUT, + PK0_IOR_IN, PK0_IOR_OUT, + + PK11MD_00, PK11MD_01, PK11MD_10, PK11MD_11, + PK10MD_00, PK10MD_01, PK10MD_10, PK10MD_11, + PK9MD_00, PK9MD_01, PK9MD_10, PK9MD_11, + PK8MD_00, PK8MD_01, PK8MD_10, PK8MD_11, + PK7MD_00, PK7MD_01, PK7MD_10, PK7MD_11, + PK6MD_00, PK6MD_01, PK6MD_10, PK6MD_11, + PK5MD_00, PK5MD_01, PK5MD_10, PK5MD_11, + PK4MD_00, PK4MD_01, PK4MD_10, PK4MD_11, + PK3MD_00, PK3MD_01, PK3MD_10, PK3MD_11, + PK2MD_00, PK2MD_01, PK2MD_10, PK2MD_11, + PK1MD_00, PK1MD_01, PK1MD_10, PK1MD_11, + PK0MD_00, PK0MD_01, PK0MD_10, PK0MD_11, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + /* Port A */ + + /* Port B */ + + /* Port C */ + + /* Port D */ + + /* Port E */ + + /* Port F */ + + /* Port G */ + + /* Port H */ + PHAN7_MARK, PHAN6_MARK, PHAN5_MARK, PHAN4_MARK, + PHAN3_MARK, PHAN2_MARK, PHAN1_MARK, PHAN0_MARK, + + /* Port I - not on device */ + + /* Port J */ + + /* Port K */ + + IRQ7_PC_MARK, IRQ6_PC_MARK, IRQ5_PC_MARK, IRQ4_PC_MARK, + IRQ3_PG_MARK, IRQ2_PG_MARK, IRQ1_PJ_MARK, IRQ0_PJ_MARK, + IRQ3_PE_MARK, IRQ2_PE_MARK, IRQ1_PE_MARK, IRQ0_PE_MARK, + + PINT7_PG_MARK, PINT6_PG_MARK, PINT5_PG_MARK, PINT4_PG_MARK, + PINT3_PG_MARK, PINT2_PG_MARK, PINT1_PG_MARK, PINT0_PG_MARK, + + SD_CD_MARK, SD_D0_MARK, SD_D1_MARK, SD_D2_MARK, SD_D3_MARK, + SD_WP_MARK, SD_CLK_MARK, SD_CMD_MARK, + CRX0_MARK, CRX1_MARK, + CTX0_MARK, CTX1_MARK, + + PWM1A_MARK, PWM1B_MARK, PWM1C_MARK, PWM1D_MARK, + PWM1E_MARK, PWM1F_MARK, PWM1G_MARK, PWM1H_MARK, + PWM2A_MARK, PWM2B_MARK, PWM2C_MARK, PWM2D_MARK, + PWM2E_MARK, PWM2F_MARK, PWM2G_MARK, PWM2H_MARK, + IERXD_MARK, IETXD_MARK, + CRX0CRX1_MARK, + WDTOVF_MARK, + + CRX0X1_MARK, + + /* DMAC */ + TEND0_MARK, DACK0_MARK, DREQ0_MARK, + TEND1_MARK, DACK1_MARK, DREQ1_MARK, + + /* ADC */ + ADTRG_MARK, + + /* BSC */ + A25_MARK, A24_MARK, + A23_MARK, A22_MARK, A21_MARK, A20_MARK, + A19_MARK, A18_MARK, A17_MARK, A16_MARK, + A15_MARK, A14_MARK, A13_MARK, A12_MARK, + A11_MARK, A10_MARK, A9_MARK, A8_MARK, + A7_MARK, A6_MARK, A5_MARK, A4_MARK, + A3_MARK, A2_MARK, A1_MARK, A0_MARK, + D15_MARK, D14_MARK, D13_MARK, D12_MARK, + D11_MARK, D10_MARK, D9_MARK, D8_MARK, + D7_MARK, D6_MARK, D5_MARK, D4_MARK, + D3_MARK, D2_MARK, D1_MARK, D0_MARK, + BS_MARK, + CS4_MARK, CS3_MARK, CS2_MARK, CS1_MARK, CS0_MARK, + CS6CE1B_MARK, CS5CE1A_MARK, + CE2A_MARK, CE2B_MARK, + RD_MARK, RDWR_MARK, + ICIOWRAH_MARK, + ICIORD_MARK, + WE1DQMUWE_MARK, + WE0DQML_MARK, + RAS_MARK, CAS_MARK, CKE_MARK, + WAIT_MARK, BREQ_MARK, BACK_MARK, IOIS16_MARK, + + /* TMU */ + TIOC0A_MARK, TIOC0B_MARK, TIOC0C_MARK, TIOC0D_MARK, + TIOC1A_MARK, TIOC1B_MARK, + TIOC2A_MARK, TIOC2B_MARK, + TIOC3A_MARK, TIOC3B_MARK, TIOC3C_MARK, TIOC3D_MARK, + TIOC4A_MARK, TIOC4B_MARK, TIOC4C_MARK, TIOC4D_MARK, + TCLKA_MARK, TCLKB_MARK, TCLKC_MARK, TCLKD_MARK, + + /* SCIF */ + SCK0_MARK, SCK1_MARK, SCK2_MARK, SCK3_MARK, + RXD0_MARK, RXD1_MARK, RXD2_MARK, RXD3_MARK, + TXD0_MARK, TXD1_MARK, TXD2_MARK, TXD3_MARK, + RXD4_MARK, RXD5_MARK, RXD6_MARK, RXD7_MARK, + TXD4_MARK, TXD5_MARK, TXD6_MARK, TXD7_MARK, + RTS1_MARK, RTS3_MARK, + CTS1_MARK, CTS3_MARK, + + /* RSPI */ + RSPCK0_MARK, RSPCK1_MARK, + MOSI0_MARK, MOSI1_MARK, + MISO0_PF12_MARK, MISO1_MARK, MISO1_PG19_MARK, + SSL00_MARK, SSL10_MARK, + + /* IIC3 */ + SCL0_MARK, SCL1_MARK, SCL2_MARK, + SDA0_MARK, SDA1_MARK, SDA2_MARK, + + /* SSI */ + SSISCK0_MARK, + SSIWS0_MARK, + SSITXD0_MARK, + SSIRXD0_MARK, + SSIWS1_MARK, SSIWS2_MARK, SSIWS3_MARK, + SSISCK1_MARK, SSISCK2_MARK, SSISCK3_MARK, + SSIDATA1_MARK, SSIDATA2_MARK, SSIDATA3_MARK, + AUDIO_CLK_MARK, + + /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */ + SIOFTXD_MARK, SIOFRXD_MARK, SIOFSYNC_MARK, SIOFSCK_MARK, + + /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */ + SPDIF_IN_MARK, SPDIF_OUT_MARK, + + /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ + FCE_MARK, + FRB_MARK, + + /* VDC3 */ + DV_CLK_MARK, + DV_VSYNC_MARK, DV_HSYNC_MARK, + DV_DATA7_MARK, DV_DATA6_MARK, DV_DATA5_MARK, DV_DATA4_MARK, + DV_DATA3_MARK, DV_DATA2_MARK, DV_DATA1_MARK, DV_DATA0_MARK, + LCD_CLK_MARK, LCD_EXTCLK_MARK, + LCD_VSYNC_MARK, LCD_HSYNC_MARK, LCD_DE_MARK, + LCD_DATA15_MARK, LCD_DATA14_MARK, LCD_DATA13_MARK, LCD_DATA12_MARK, + LCD_DATA11_MARK, LCD_DATA10_MARK, LCD_DATA9_MARK, LCD_DATA8_MARK, + LCD_DATA7_MARK, LCD_DATA6_MARK, LCD_DATA5_MARK, LCD_DATA4_MARK, + LCD_DATA3_MARK, LCD_DATA2_MARK, LCD_DATA1_MARK, LCD_DATA0_MARK, + LCD_M_DISP_MARK, + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + + /* Port A */ + PINMUX_DATA(PA3_DATA, PA3_IN), + PINMUX_DATA(PA2_DATA, PA2_IN), + PINMUX_DATA(PA1_DATA, PA1_IN), + PINMUX_DATA(PA0_DATA, PA0_IN), + + /* Port B */ + PINMUX_DATA(PB22_DATA, PB22MD_00, PB22_IN, PB22_OUT), + PINMUX_DATA(A22_MARK, PB22MD_01), + PINMUX_DATA(CS4_MARK, PB22MD_10), + + PINMUX_DATA(PB21_DATA, PB21MD_0, PB21_IN, PB21_OUT), + PINMUX_DATA(A21_MARK, PB21MD_1), + PINMUX_DATA(A20_MARK, PB20MD_1), + PINMUX_DATA(A19_MARK, PB19MD_01), + PINMUX_DATA(A18_MARK, PB18MD_01), + PINMUX_DATA(A17_MARK, PB17MD_01), + PINMUX_DATA(A16_MARK, PB16MD_01), + PINMUX_DATA(A15_MARK, PB15MD_01), + PINMUX_DATA(A14_MARK, PB14MD_01), + PINMUX_DATA(A13_MARK, PB13MD_01), + PINMUX_DATA(A12_MARK, PB12MD_01), + PINMUX_DATA(A11_MARK, PB11MD_01), + PINMUX_DATA(A10_MARK, PB10MD_01), + PINMUX_DATA(A9_MARK, PB9MD_01), + PINMUX_DATA(A8_MARK, PB8MD_01), + PINMUX_DATA(A7_MARK, PB7MD_01), + PINMUX_DATA(A6_MARK, PB6MD_01), + PINMUX_DATA(A5_MARK, PB5MD_01), + PINMUX_DATA(A4_MARK, PB4MD_01), + PINMUX_DATA(A3_MARK, PB3MD_1), + PINMUX_DATA(A2_MARK, PB2MD_1), + PINMUX_DATA(A1_MARK, PB1MD_1), + + /* Port C */ + PINMUX_DATA(PC10_DATA, PC10MD_0), + PINMUX_DATA(TIOC2B_MARK, PC1MD_1), + PINMUX_DATA(PC9_DATA, PC9MD_0), + PINMUX_DATA(TIOC2A_MARK, PC9MD_1), + PINMUX_DATA(PC8_DATA, PC8MD_00), + PINMUX_DATA(CS3_MARK, PC8MD_01), + PINMUX_DATA(TIOC4D_MARK, PC8MD_10), + PINMUX_DATA(IRQ7_PC_MARK, PC8MD_11), + PINMUX_DATA(PC7_DATA, PC7MD_00), + PINMUX_DATA(CKE_MARK, PC7MD_01), + PINMUX_DATA(TIOC4C_MARK, PC7MD_10), + PINMUX_DATA(IRQ6_PC_MARK, PC7MD_11), + PINMUX_DATA(PC6_DATA, PC6MD_00), + PINMUX_DATA(CAS_MARK, PC6MD_01), + PINMUX_DATA(TIOC4B_MARK, PC6MD_10), + PINMUX_DATA(IRQ5_PC_MARK, PC6MD_11), + PINMUX_DATA(PC5_DATA, PC5MD_00), + PINMUX_DATA(RAS_MARK, PC5MD_01), + PINMUX_DATA(TIOC4A_MARK, PC5MD_10), + PINMUX_DATA(IRQ4_PC_MARK, PC5MD_11), + PINMUX_DATA(PC4_DATA, PC4MD_0), + PINMUX_DATA(WE1DQMUWE_MARK, PC4MD_1), + PINMUX_DATA(PC3_DATA, PC3MD_0), + PINMUX_DATA(WE0DQML_MARK, PC3MD_1), + PINMUX_DATA(PC2_DATA, PC2MD_0), + PINMUX_DATA(RDWR_MARK, PC2MD_1), + PINMUX_DATA(PC1_DATA, PC1MD_0), + PINMUX_DATA(RD_MARK, PC1MD_1), + PINMUX_DATA(PC0_DATA, PC0MD_0), + PINMUX_DATA(CS0_MARK, PC0MD_1), + + /* Port D */ + PINMUX_DATA(D15_MARK, PD15MD_01), + PINMUX_DATA(D14_MARK, PD14MD_01), + PINMUX_DATA(D13_MARK, PD13MD_01), + PINMUX_DATA(D12_MARK, PD12MD_01), + PINMUX_DATA(D11_MARK, PD11MD_01), + PINMUX_DATA(D10_MARK, PD10MD_01), + PINMUX_DATA(D9_MARK, PD9MD_01), + PINMUX_DATA(D8_MARK, PD8MD_01), + PINMUX_DATA(D7_MARK, PD7MD_01), + PINMUX_DATA(D6_MARK, PD6MD_01), + PINMUX_DATA(D5_MARK, PD5MD_01), + PINMUX_DATA(D4_MARK, PD4MD_01), + PINMUX_DATA(D3_MARK, PD3MD_01), + PINMUX_DATA(D2_MARK, PD2MD_01), + PINMUX_DATA(D1_MARK, PD1MD_01), + PINMUX_DATA(D0_MARK, PD0MD_01), + + /* Port E */ + PINMUX_DATA(PE5_DATA, PE5MD_00), + PINMUX_DATA(SDA2_MARK, PE5MD_01), + PINMUX_DATA(DV_HSYNC_MARK, PE5MD_11), + + PINMUX_DATA(PE4_DATA, PE4MD_00), + PINMUX_DATA(SCL2_MARK, PE4MD_01), + PINMUX_DATA(DV_VSYNC_MARK, PE4MD_11), + + PINMUX_DATA(PE3_DATA, PE3MD_00), + PINMUX_DATA(SDA1_MARK, PE3MD_01), + PINMUX_DATA(IRQ3_PE_MARK, PE3MD_11), + + PINMUX_DATA(PE2_DATA, PE2MD_00), + PINMUX_DATA(SCL1_MARK, PE2MD_01), + PINMUX_DATA(IRQ2_PE_MARK, PE2MD_11), + + PINMUX_DATA(PE1_DATA, PE1MD_000), + PINMUX_DATA(SDA0_MARK, PE1MD_001), + PINMUX_DATA(IOIS16_MARK, PE1MD_010), + PINMUX_DATA(IRQ1_PE_MARK, PE1MD_011), + PINMUX_DATA(TCLKA_MARK, PE1MD_100), + PINMUX_DATA(ADTRG_MARK, PE1MD_101), + + PINMUX_DATA(PE0_DATA, PE0MD_00), + PINMUX_DATA(SCL0_MARK, PE0MD_01), + PINMUX_DATA(AUDIO_CLK_MARK, PE0MD_10), + PINMUX_DATA(IRQ0_PE_MARK, PE0MD_11), + + /* Port F */ + PINMUX_DATA(PF12_DATA, PF12MD_000), + PINMUX_DATA(BS_MARK, PF12MD_001), + PINMUX_DATA(MISO0_PF12_MARK, PF12MD_011), + PINMUX_DATA(TIOC3D_MARK, PF12MD_100), + PINMUX_DATA(SPDIF_OUT_MARK, PF12MD_101), + + PINMUX_DATA(PF11_DATA, PF11MD_000), + PINMUX_DATA(A25_MARK, PF11MD_001), + PINMUX_DATA(SSIDATA3_MARK, PF11MD_010), + PINMUX_DATA(MOSI0_MARK, PF11MD_011), + PINMUX_DATA(TIOC3C_MARK, PF11MD_100), + PINMUX_DATA(SPDIF_IN_MARK, PF11MD_101), + + PINMUX_DATA(PF10_DATA, PF10MD_000), + PINMUX_DATA(A24_MARK, PF10MD_001), + PINMUX_DATA(SSIWS3_MARK, PF10MD_010), + PINMUX_DATA(SSL00_MARK, PF10MD_011), + PINMUX_DATA(TIOC3B_MARK, PF10MD_100), + PINMUX_DATA(FCE_MARK, PF10MD_101), + + PINMUX_DATA(PF9_DATA, PF9MD_000), + PINMUX_DATA(A23_MARK, PF9MD_001), + PINMUX_DATA(SSISCK3_MARK, PF9MD_010), + PINMUX_DATA(RSPCK0_MARK, PF9MD_011), + PINMUX_DATA(TIOC3A_MARK, PF9MD_100), + PINMUX_DATA(FRB_MARK, PF9MD_101), + + PINMUX_DATA(PF8_DATA, PF8MD_00), + PINMUX_DATA(CE2B_MARK, PF8MD_01), + PINMUX_DATA(SSIDATA3_MARK, PF8MD_10), + PINMUX_DATA(DV_CLK_MARK, PF8MD_11), + + PINMUX_DATA(PF7_DATA, PF7MD_000), + PINMUX_DATA(CE2A_MARK, PF7MD_001), + PINMUX_DATA(SSIWS3_MARK, PF7MD_010), + PINMUX_DATA(DV_DATA7_MARK, PF7MD_011), + PINMUX_DATA(TCLKD_MARK, PF7MD_100), + + PINMUX_DATA(PF6_DATA, PF6MD_000), + PINMUX_DATA(CS6CE1B_MARK, PF6MD_001), + PINMUX_DATA(SSISCK3_MARK, PF6MD_010), + PINMUX_DATA(DV_DATA6_MARK, PF6MD_011), + PINMUX_DATA(TCLKB_MARK, PF6MD_100), + + PINMUX_DATA(PF5_DATA, PF5MD_000), + PINMUX_DATA(CS5CE1A_MARK, PF5MD_001), + PINMUX_DATA(SSIDATA2_MARK, PF5MD_010), + PINMUX_DATA(DV_DATA5_MARK, PF5MD_011), + PINMUX_DATA(TCLKC_MARK, PF5MD_100), + + PINMUX_DATA(PF4_DATA, PF4MD_000), + PINMUX_DATA(ICIOWRAH_MARK, PF4MD_001), + PINMUX_DATA(SSIWS2_MARK, PF4MD_010), + PINMUX_DATA(DV_DATA4_MARK, PF4MD_011), + PINMUX_DATA(TXD3_MARK, PF4MD_100), + + PINMUX_DATA(PF3_DATA, PF3MD_000), + PINMUX_DATA(ICIORD_MARK, PF3MD_001), + PINMUX_DATA(SSISCK2_MARK, PF3MD_010), + PINMUX_DATA(DV_DATA3_MARK, PF3MD_011), + PINMUX_DATA(RXD3_MARK, PF3MD_100), + + PINMUX_DATA(PF2_DATA, PF2MD_000), + PINMUX_DATA(BACK_MARK, PF2MD_001), + PINMUX_DATA(SSIDATA1_MARK, PF2MD_010), + PINMUX_DATA(DV_DATA2_MARK, PF2MD_011), + PINMUX_DATA(TXD2_MARK, PF2MD_100), + PINMUX_DATA(DACK0_MARK, PF2MD_101), + + PINMUX_DATA(PF1_DATA, PF1MD_000), + PINMUX_DATA(BREQ_MARK, PF1MD_001), + PINMUX_DATA(SSIWS1_MARK, PF1MD_010), + PINMUX_DATA(DV_DATA1_MARK, PF1MD_011), + PINMUX_DATA(RXD2_MARK, PF1MD_100), + PINMUX_DATA(DREQ0_MARK, PF1MD_101), + + PINMUX_DATA(PF0_DATA, PF0MD_000), + PINMUX_DATA(WAIT_MARK, PF0MD_001), + PINMUX_DATA(SSISCK1_MARK, PF0MD_010), + PINMUX_DATA(DV_DATA0_MARK, PF0MD_011), + PINMUX_DATA(SCK2_MARK, PF0MD_100), + PINMUX_DATA(TEND0_MARK, PF0MD_101), + + /* Port G */ + PINMUX_DATA(PG24_DATA, PG24MD_00), + PINMUX_DATA(MOSI0_MARK, PG24MD_01), + PINMUX_DATA(TIOC0D_MARK, PG24MD_10), + + PINMUX_DATA(PG23_DATA, PG23MD_00), + PINMUX_DATA(MOSI1_MARK, PG23MD_01), + PINMUX_DATA(TIOC0C_MARK, PG23MD_10), + + PINMUX_DATA(PG22_DATA, PG22MD_00), + PINMUX_DATA(SSL10_MARK, PG22MD_01), + PINMUX_DATA(TIOC0B_MARK, PG22MD_10), + + PINMUX_DATA(PG21_DATA, PG21MD_00), + PINMUX_DATA(RSPCK1_MARK, PG21MD_01), + PINMUX_DATA(TIOC0A_MARK, PG21MD_10), + + PINMUX_DATA(PG20_DATA, PG20MD_000), + PINMUX_DATA(LCD_EXTCLK_MARK, PG20MD_001), + PINMUX_DATA(MISO1_MARK, PG20MD_011), + PINMUX_DATA(TXD7_MARK, PG20MD_100), + + PINMUX_DATA(PG19_DATA, PG19MD_000), + PINMUX_DATA(LCD_CLK_MARK, PG19MD_001), + PINMUX_DATA(TIOC2B_MARK, PG19MD_010), + PINMUX_DATA(MISO1_PG19_MARK, PG19MD_011), + PINMUX_DATA(RXD7_MARK, PG19MD_100), + + PINMUX_DATA(PG18_DATA, PG18MD_000), + PINMUX_DATA(LCD_DE_MARK, PG18MD_001), + PINMUX_DATA(TIOC2A_MARK, PG18MD_010), + PINMUX_DATA(SSL10_MARK, PG18MD_011), + PINMUX_DATA(TXD6_MARK, PG18MD_100), + + PINMUX_DATA(PG17_DATA, PG17MD_000), + PINMUX_DATA(LCD_HSYNC_MARK, PG17MD_001), + PINMUX_DATA(TIOC1B_MARK, PG17MD_010), + PINMUX_DATA(RSPCK1_MARK, PG17MD_011), + PINMUX_DATA(RXD6_MARK, PG17MD_100), + + PINMUX_DATA(PG16_DATA, PG16MD_000), + PINMUX_DATA(LCD_VSYNC_MARK, PG16MD_001), + PINMUX_DATA(TIOC1A_MARK, PG16MD_010), + PINMUX_DATA(TXD3_MARK, PG16MD_011), + PINMUX_DATA(CTS1_MARK, PG16MD_100), + + PINMUX_DATA(PG15_DATA, PG15MD_000), + PINMUX_DATA(LCD_DATA15_MARK, PG15MD_001), + PINMUX_DATA(TIOC0D_MARK, PG15MD_010), + PINMUX_DATA(RXD3_MARK, PG15MD_011), + PINMUX_DATA(RTS1_MARK, PG15MD_100), + + PINMUX_DATA(PG14_DATA, PG14MD_000), + PINMUX_DATA(LCD_DATA14_MARK, PG14MD_001), + PINMUX_DATA(TIOC0C_MARK, PG14MD_010), + PINMUX_DATA(SCK1_MARK, PG14MD_100), + + PINMUX_DATA(PG13_DATA, PG13MD_000), + PINMUX_DATA(LCD_DATA13_MARK, PG13MD_001), + PINMUX_DATA(TIOC0B_MARK, PG13MD_010), + PINMUX_DATA(TXD1_MARK, PG13MD_100), + + PINMUX_DATA(PG12_DATA, PG12MD_000), + PINMUX_DATA(LCD_DATA12_MARK, PG12MD_001), + PINMUX_DATA(TIOC0A_MARK, PG12MD_010), + PINMUX_DATA(RXD1_MARK, PG12MD_100), + + PINMUX_DATA(PG11_DATA, PG11MD_000), + PINMUX_DATA(LCD_DATA11_MARK, PG11MD_001), + PINMUX_DATA(SSITXD0_MARK, PG11MD_010), + PINMUX_DATA(IRQ3_PG_MARK, PG11MD_011), + PINMUX_DATA(TXD5_MARK, PG11MD_100), + PINMUX_DATA(SIOFTXD_MARK, PG11MD_101), + + PINMUX_DATA(PG10_DATA, PG10MD_000), + PINMUX_DATA(LCD_DATA10_MARK, PG10MD_001), + PINMUX_DATA(SSIRXD0_MARK, PG10MD_010), + PINMUX_DATA(IRQ2_PG_MARK, PG10MD_011), + PINMUX_DATA(RXD5_MARK, PG10MD_100), + PINMUX_DATA(SIOFRXD_MARK, PG10MD_101), + + PINMUX_DATA(PG9_DATA, PG9MD_000), + PINMUX_DATA(LCD_DATA9_MARK, PG9MD_001), + PINMUX_DATA(SSIWS0_MARK, PG9MD_010), + PINMUX_DATA(TXD4_MARK, PG9MD_100), + PINMUX_DATA(SIOFSYNC_MARK, PG9MD_101), + + PINMUX_DATA(PG8_DATA, PG8MD_000), + PINMUX_DATA(LCD_DATA8_MARK, PG8MD_001), + PINMUX_DATA(SSISCK0_MARK, PG8MD_010), + PINMUX_DATA(RXD4_MARK, PG8MD_100), + PINMUX_DATA(SIOFSCK_MARK, PG8MD_101), + + PINMUX_DATA(PG7_DATA, PG7MD_00), + PINMUX_DATA(LCD_DATA7_MARK, PG7MD_01), + PINMUX_DATA(SD_CD_MARK, PG7MD_10), + PINMUX_DATA(PINT7_PG_MARK, PG7MD_11), + + PINMUX_DATA(PG6_DATA, PG7MD_00), + PINMUX_DATA(LCD_DATA6_MARK, PG7MD_01), + PINMUX_DATA(SD_WP_MARK, PG7MD_10), + PINMUX_DATA(PINT6_PG_MARK, PG7MD_11), + + PINMUX_DATA(PG5_DATA, PG5MD_00), + PINMUX_DATA(LCD_DATA5_MARK, PG5MD_01), + PINMUX_DATA(SD_D1_MARK, PG5MD_10), + PINMUX_DATA(PINT5_PG_MARK, PG5MD_11), + + PINMUX_DATA(PG4_DATA, PG4MD_00), + PINMUX_DATA(LCD_DATA4_MARK, PG4MD_01), + PINMUX_DATA(SD_D0_MARK, PG4MD_10), + PINMUX_DATA(PINT4_PG_MARK, PG4MD_11), + + PINMUX_DATA(PG3_DATA, PG3MD_00), + PINMUX_DATA(LCD_DATA3_MARK, PG3MD_01), + PINMUX_DATA(SD_CLK_MARK, PG3MD_10), + PINMUX_DATA(PINT3_PG_MARK, PG3MD_11), + + PINMUX_DATA(PG2_DATA, PG2MD_00), + PINMUX_DATA(LCD_DATA2_MARK, PG2MD_01), + PINMUX_DATA(SD_CMD_MARK, PG2MD_10), + PINMUX_DATA(PINT2_PG_MARK, PG2MD_11), + + PINMUX_DATA(PG1_DATA, PG1MD_00), + PINMUX_DATA(LCD_DATA1_MARK, PG1MD_01), + PINMUX_DATA(SD_D3_MARK, PG1MD_10), + PINMUX_DATA(PINT1_PG_MARK, PG1MD_11), + + PINMUX_DATA(PG0_DATA, PG0MD_000), + PINMUX_DATA(LCD_DATA0_MARK, PG0MD_001), + PINMUX_DATA(SD_D2_MARK, PG0MD_010), + PINMUX_DATA(PINT0_PG_MARK, PG0MD_011), + PINMUX_DATA(WDTOVF_MARK, PG0MD_100), + + /* Port H */ + PINMUX_DATA(PH7_DATA, PH7MD_0), + PINMUX_DATA(PHAN7_MARK, PH7MD_1), + + PINMUX_DATA(PH6_DATA, PH6MD_0), + PINMUX_DATA(PHAN6_MARK, PH6MD_1), + + PINMUX_DATA(PH5_DATA, PH5MD_0), + PINMUX_DATA(PHAN5_MARK, PH5MD_1), + + PINMUX_DATA(PH4_DATA, PH4MD_0), + PINMUX_DATA(PHAN4_MARK, PH4MD_1), + + PINMUX_DATA(PH3_DATA, PH3MD_0), + PINMUX_DATA(PHAN3_MARK, PH3MD_1), + + PINMUX_DATA(PH2_DATA, PH2MD_0), + PINMUX_DATA(PHAN2_MARK, PH2MD_1), + + PINMUX_DATA(PH1_DATA, PH1MD_0), + PINMUX_DATA(PHAN1_MARK, PH1MD_1), + + PINMUX_DATA(PH0_DATA, PH0MD_0), + PINMUX_DATA(PHAN0_MARK, PH0MD_1), + + /* Port I - not on device */ + + /* Port J */ + PINMUX_DATA(PJ11_DATA, PJ11MD_00), + PINMUX_DATA(PWM2H_MARK, PJ11MD_01), + PINMUX_DATA(DACK1_MARK, PJ11MD_10), + + PINMUX_DATA(PJ10_DATA, PJ10MD_00), + PINMUX_DATA(PWM2G_MARK, PJ10MD_01), + PINMUX_DATA(DREQ1_MARK, PJ10MD_10), + + PINMUX_DATA(PJ9_DATA, PJ9MD_00), + PINMUX_DATA(PWM2F_MARK, PJ9MD_01), + PINMUX_DATA(TEND1_MARK, PJ9MD_10), + + PINMUX_DATA(PJ8_DATA, PJ8MD_00), + PINMUX_DATA(PWM2E_MARK, PJ8MD_01), + PINMUX_DATA(RTS3_MARK, PJ8MD_10), + + PINMUX_DATA(PJ7_DATA, PJ7MD_00), + PINMUX_DATA(TIOC1B_MARK, PJ7MD_01), + PINMUX_DATA(CTS3_MARK, PJ7MD_10), + + PINMUX_DATA(PJ6_DATA, PJ6MD_00), + PINMUX_DATA(TIOC1A_MARK, PJ6MD_01), + PINMUX_DATA(SCK3_MARK, PJ6MD_10), + + PINMUX_DATA(PJ5_DATA, PJ5MD_00), + PINMUX_DATA(IERXD_MARK, PJ5MD_01), + PINMUX_DATA(TXD3_MARK, PJ5MD_10), + + PINMUX_DATA(PJ4_DATA, PJ4MD_00), + PINMUX_DATA(IETXD_MARK, PJ4MD_01), + PINMUX_DATA(RXD3_MARK, PJ4MD_10), + + PINMUX_DATA(PJ3_DATA, PJ3MD_00), + PINMUX_DATA(CRX1_MARK, PJ3MD_01), + PINMUX_DATA(CRX0X1_MARK, PJ3MD_10), + PINMUX_DATA(IRQ1_PJ_MARK, PJ3MD_11), + + PINMUX_DATA(PJ2_DATA, PJ2MD_000), + PINMUX_DATA(CTX1_MARK, PJ2MD_001), + PINMUX_DATA(CRX0CRX1_MARK, PJ2MD_010), + PINMUX_DATA(CS2_MARK, PJ2MD_011), + PINMUX_DATA(SCK0_MARK, PJ2MD_100), + PINMUX_DATA(LCD_M_DISP_MARK, PJ2MD_101), + + PINMUX_DATA(PJ1_DATA, PJ1MD_000), + PINMUX_DATA(CRX0_MARK, PJ1MD_001), + PINMUX_DATA(IERXD_MARK, PJ1MD_010), + PINMUX_DATA(IRQ0_PJ_MARK, PJ1MD_011), + PINMUX_DATA(RXD0_MARK, PJ1MD_100), + + PINMUX_DATA(PJ0_DATA, PJ0MD_000), + PINMUX_DATA(CTX0_MARK, PJ0MD_001), + PINMUX_DATA(IERXD_MARK, PJ0MD_010), + PINMUX_DATA(CS1_MARK, PJ0MD_011), + PINMUX_DATA(TXD0_MARK, PJ0MD_100), + PINMUX_DATA(A0_MARK, PJ0MD_101), + + /* Port K */ + PINMUX_DATA(PK11_DATA, PK11MD_00), + PINMUX_DATA(PWM2D_MARK, PK11MD_01), + PINMUX_DATA(SSITXD0_MARK, PK11MD_10), + + PINMUX_DATA(PK10_DATA, PK10MD_00), + PINMUX_DATA(PWM2C_MARK, PK10MD_01), + PINMUX_DATA(SSIRXD0_MARK, PK10MD_10), + + PINMUX_DATA(PK9_DATA, PK9MD_00), + PINMUX_DATA(PWM2B_MARK, PK9MD_01), + PINMUX_DATA(SSIWS0_MARK, PK9MD_10), + + PINMUX_DATA(PK8_DATA, PK8MD_00), + PINMUX_DATA(PWM2A_MARK, PK8MD_01), + PINMUX_DATA(SSISCK0_MARK, PK8MD_10), + + PINMUX_DATA(PK7_DATA, PK7MD_00), + PINMUX_DATA(PWM1H_MARK, PK7MD_01), + PINMUX_DATA(SD_CD_MARK, PK7MD_10), + + PINMUX_DATA(PK6_DATA, PK6MD_00), + PINMUX_DATA(PWM1G_MARK, PK6MD_01), + PINMUX_DATA(SD_WP_MARK, PK6MD_10), + + PINMUX_DATA(PK5_DATA, PK5MD_00), + PINMUX_DATA(PWM1F_MARK, PK5MD_01), + PINMUX_DATA(SD_D1_MARK, PK5MD_10), + + PINMUX_DATA(PK4_DATA, PK4MD_00), + PINMUX_DATA(PWM1E_MARK, PK4MD_01), + PINMUX_DATA(SD_D0_MARK, PK4MD_10), + + PINMUX_DATA(PK3_DATA, PK3MD_00), + PINMUX_DATA(PWM1D_MARK, PK3MD_01), + PINMUX_DATA(SD_CLK_MARK, PK3MD_10), + + PINMUX_DATA(PK2_DATA, PK2MD_00), + PINMUX_DATA(PWM1C_MARK, PK2MD_01), + PINMUX_DATA(SD_CMD_MARK, PK2MD_10), + + PINMUX_DATA(PK1_DATA, PK1MD_00), + PINMUX_DATA(PWM1B_MARK, PK1MD_01), + PINMUX_DATA(SD_D3_MARK, PK1MD_10), + + PINMUX_DATA(PK0_DATA, PK0MD_00), + PINMUX_DATA(PWM1A_MARK, PK0MD_01), + PINMUX_DATA(SD_D2_MARK, PK0MD_10), +}; + +static struct pinmux_gpio pinmux_gpios[] = { + + /* Port A */ + PINMUX_GPIO(GPIO_PA3, PA3_DATA), + PINMUX_GPIO(GPIO_PA2, PA2_DATA), + PINMUX_GPIO(GPIO_PA1, PA1_DATA), + PINMUX_GPIO(GPIO_PA0, PA0_DATA), + + /* Port B */ + PINMUX_GPIO(GPIO_PB22, PB22_DATA), + PINMUX_GPIO(GPIO_PB21, PB21_DATA), + PINMUX_GPIO(GPIO_PB20, PB20_DATA), + PINMUX_GPIO(GPIO_PB19, PB19_DATA), + PINMUX_GPIO(GPIO_PB18, PB18_DATA), + PINMUX_GPIO(GPIO_PB17, PB17_DATA), + PINMUX_GPIO(GPIO_PB16, PB16_DATA), + PINMUX_GPIO(GPIO_PB15, PB15_DATA), + PINMUX_GPIO(GPIO_PB14, PB14_DATA), + PINMUX_GPIO(GPIO_PB13, PB13_DATA), + PINMUX_GPIO(GPIO_PB12, PB12_DATA), + PINMUX_GPIO(GPIO_PB11, PB11_DATA), + PINMUX_GPIO(GPIO_PB10, PB10_DATA), + PINMUX_GPIO(GPIO_PB9, PB9_DATA), + PINMUX_GPIO(GPIO_PB8, PB8_DATA), + PINMUX_GPIO(GPIO_PB7, PB7_DATA), + PINMUX_GPIO(GPIO_PB6, PB6_DATA), + PINMUX_GPIO(GPIO_PB5, PB5_DATA), + PINMUX_GPIO(GPIO_PB4, PB4_DATA), + PINMUX_GPIO(GPIO_PB3, PB3_DATA), + PINMUX_GPIO(GPIO_PB2, PB2_DATA), + PINMUX_GPIO(GPIO_PB1, PB1_DATA), + + /* Port C */ + PINMUX_GPIO(GPIO_PC10, PC10_DATA), + PINMUX_GPIO(GPIO_PC9, PC9_DATA), + PINMUX_GPIO(GPIO_PC8, PC8_DATA), + PINMUX_GPIO(GPIO_PC7, PC7_DATA), + PINMUX_GPIO(GPIO_PC6, PC6_DATA), + PINMUX_GPIO(GPIO_PC5, PC5_DATA), + PINMUX_GPIO(GPIO_PC4, PC4_DATA), + PINMUX_GPIO(GPIO_PC3, PC3_DATA), + PINMUX_GPIO(GPIO_PC2, PC2_DATA), + PINMUX_GPIO(GPIO_PC1, PC1_DATA), + PINMUX_GPIO(GPIO_PC0, PC0_DATA), + + /* Port D */ + PINMUX_GPIO(GPIO_PD15, PD15_DATA), + PINMUX_GPIO(GPIO_PD14, PD14_DATA), + PINMUX_GPIO(GPIO_PD13, PD13_DATA), + PINMUX_GPIO(GPIO_PD12, PD12_DATA), + PINMUX_GPIO(GPIO_PD11, PD11_DATA), + PINMUX_GPIO(GPIO_PD10, PD10_DATA), + PINMUX_GPIO(GPIO_PD9, PD9_DATA), + PINMUX_GPIO(GPIO_PD8, PD8_DATA), + PINMUX_GPIO(GPIO_PD7, PD7_DATA), + PINMUX_GPIO(GPIO_PD6, PD6_DATA), + PINMUX_GPIO(GPIO_PD5, PD5_DATA), + PINMUX_GPIO(GPIO_PD4, PD4_DATA), + PINMUX_GPIO(GPIO_PD3, PD3_DATA), + PINMUX_GPIO(GPIO_PD2, PD2_DATA), + PINMUX_GPIO(GPIO_PD1, PD1_DATA), + PINMUX_GPIO(GPIO_PD0, PD0_DATA), + + /* Port E */ + PINMUX_GPIO(GPIO_PE5, PE5_DATA), + PINMUX_GPIO(GPIO_PE4, PE4_DATA), + PINMUX_GPIO(GPIO_PE3, PE3_DATA), + PINMUX_GPIO(GPIO_PE2, PE2_DATA), + PINMUX_GPIO(GPIO_PE1, PE1_DATA), + PINMUX_GPIO(GPIO_PE0, PE0_DATA), + + /* Port F */ + PINMUX_GPIO(GPIO_PF12, PF12_DATA), + PINMUX_GPIO(GPIO_PF11, PF11_DATA), + PINMUX_GPIO(GPIO_PF10, PF10_DATA), + PINMUX_GPIO(GPIO_PF9, PF9_DATA), + PINMUX_GPIO(GPIO_PF8, PF8_DATA), + PINMUX_GPIO(GPIO_PF7, PF7_DATA), + PINMUX_GPIO(GPIO_PF6, PF6_DATA), + PINMUX_GPIO(GPIO_PF5, PF5_DATA), + PINMUX_GPIO(GPIO_PF4, PF4_DATA), + PINMUX_GPIO(GPIO_PF3, PF3_DATA), + PINMUX_GPIO(GPIO_PF2, PF2_DATA), + PINMUX_GPIO(GPIO_PF1, PF1_DATA), + PINMUX_GPIO(GPIO_PF0, PF0_DATA), + + /* Port G */ + PINMUX_GPIO(GPIO_PG24, PG24_DATA), + PINMUX_GPIO(GPIO_PG23, PG23_DATA), + PINMUX_GPIO(GPIO_PG22, PG22_DATA), + PINMUX_GPIO(GPIO_PG21, PG21_DATA), + PINMUX_GPIO(GPIO_PG20, PG20_DATA), + PINMUX_GPIO(GPIO_PG19, PG19_DATA), + PINMUX_GPIO(GPIO_PG18, PG18_DATA), + PINMUX_GPIO(GPIO_PG17, PG17_DATA), + PINMUX_GPIO(GPIO_PG16, PG16_DATA), + PINMUX_GPIO(GPIO_PG15, PG15_DATA), + PINMUX_GPIO(GPIO_PG14, PG14_DATA), + PINMUX_GPIO(GPIO_PG13, PG13_DATA), + PINMUX_GPIO(GPIO_PG12, PG12_DATA), + PINMUX_GPIO(GPIO_PG11, PG11_DATA), + PINMUX_GPIO(GPIO_PG10, PG10_DATA), + PINMUX_GPIO(GPIO_PG9, PG9_DATA), + PINMUX_GPIO(GPIO_PG8, PG8_DATA), + PINMUX_GPIO(GPIO_PG7, PG7_DATA), + PINMUX_GPIO(GPIO_PG6, PG6_DATA), + PINMUX_GPIO(GPIO_PG5, PG5_DATA), + PINMUX_GPIO(GPIO_PG4, PG4_DATA), + PINMUX_GPIO(GPIO_PG3, PG3_DATA), + PINMUX_GPIO(GPIO_PG2, PG2_DATA), + PINMUX_GPIO(GPIO_PG1, PG1_DATA), + PINMUX_GPIO(GPIO_PG0, PG0_DATA), + + /* Port H - Port H does not have a Data Register */ + + /* Port I - not on device */ + + /* Port J */ + PINMUX_GPIO(GPIO_PJ11, PJ11_DATA), + PINMUX_GPIO(GPIO_PJ10, PJ10_DATA), + PINMUX_GPIO(GPIO_PJ9, PJ9_DATA), + PINMUX_GPIO(GPIO_PJ8, PJ8_DATA), + PINMUX_GPIO(GPIO_PJ7, PJ7_DATA), + PINMUX_GPIO(GPIO_PJ6, PJ6_DATA), + PINMUX_GPIO(GPIO_PJ5, PJ5_DATA), + PINMUX_GPIO(GPIO_PJ4, PJ4_DATA), + PINMUX_GPIO(GPIO_PJ3, PJ3_DATA), + PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), + PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), + PINMUX_GPIO(GPIO_PJ0, PJ0_DATA), + + /* Port K */ + PINMUX_GPIO(GPIO_PK11, PK11_DATA), + PINMUX_GPIO(GPIO_PK10, PK10_DATA), + PINMUX_GPIO(GPIO_PK9, PK9_DATA), + PINMUX_GPIO(GPIO_PK8, PK8_DATA), + PINMUX_GPIO(GPIO_PK7, PK7_DATA), + PINMUX_GPIO(GPIO_PK6, PK6_DATA), + PINMUX_GPIO(GPIO_PK5, PK5_DATA), + PINMUX_GPIO(GPIO_PK4, PK4_DATA), + PINMUX_GPIO(GPIO_PK3, PK3_DATA), + PINMUX_GPIO(GPIO_PK2, PK2_DATA), + PINMUX_GPIO(GPIO_PK1, PK1_DATA), + PINMUX_GPIO(GPIO_PK0, PK0_DATA), + + /* INTC */ + PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK), + + PINMUX_GPIO(GPIO_FN_IRQ7_PC, IRQ7_PC_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6_PC, IRQ6_PC_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5_PC, IRQ5_PC_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4_PC, IRQ4_PC_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK), + + /* WDT */ + PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), + + /* CAN */ + PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), + PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), + PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), + PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), + PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0CRX1_MARK), + + /* DMAC */ + PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), + PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), + PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + + /* ADC */ + PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), + + /* BSCh */ + PINMUX_GPIO(GPIO_FN_A25, A25_MARK), + PINMUX_GPIO(GPIO_FN_A24, A24_MARK), + PINMUX_GPIO(GPIO_FN_A23, A23_MARK), + PINMUX_GPIO(GPIO_FN_A22, A22_MARK), + PINMUX_GPIO(GPIO_FN_A21, A21_MARK), + PINMUX_GPIO(GPIO_FN_A20, A20_MARK), + PINMUX_GPIO(GPIO_FN_A19, A19_MARK), + PINMUX_GPIO(GPIO_FN_A18, A18_MARK), + PINMUX_GPIO(GPIO_FN_A17, A17_MARK), + PINMUX_GPIO(GPIO_FN_A16, A16_MARK), + PINMUX_GPIO(GPIO_FN_A15, A15_MARK), + PINMUX_GPIO(GPIO_FN_A14, A14_MARK), + PINMUX_GPIO(GPIO_FN_A13, A13_MARK), + PINMUX_GPIO(GPIO_FN_A12, A12_MARK), + PINMUX_GPIO(GPIO_FN_A11, A11_MARK), + PINMUX_GPIO(GPIO_FN_A10, A10_MARK), + PINMUX_GPIO(GPIO_FN_A9, A9_MARK), + PINMUX_GPIO(GPIO_FN_A8, A8_MARK), + PINMUX_GPIO(GPIO_FN_A7, A7_MARK), + PINMUX_GPIO(GPIO_FN_A6, A6_MARK), + PINMUX_GPIO(GPIO_FN_A5, A5_MARK), + PINMUX_GPIO(GPIO_FN_A4, A4_MARK), + PINMUX_GPIO(GPIO_FN_A3, A3_MARK), + PINMUX_GPIO(GPIO_FN_A2, A2_MARK), + PINMUX_GPIO(GPIO_FN_A1, A1_MARK), + PINMUX_GPIO(GPIO_FN_A0, A0_MARK), + + PINMUX_GPIO(GPIO_FN_D15, D15_MARK), + PINMUX_GPIO(GPIO_FN_D14, D14_MARK), + PINMUX_GPIO(GPIO_FN_D13, D13_MARK), + PINMUX_GPIO(GPIO_FN_D12, D12_MARK), + PINMUX_GPIO(GPIO_FN_D11, D11_MARK), + PINMUX_GPIO(GPIO_FN_D10, D10_MARK), + PINMUX_GPIO(GPIO_FN_D9, D9_MARK), + PINMUX_GPIO(GPIO_FN_D8, D8_MARK), + PINMUX_GPIO(GPIO_FN_D7, D7_MARK), + PINMUX_GPIO(GPIO_FN_D6, D6_MARK), + PINMUX_GPIO(GPIO_FN_D5, D5_MARK), + PINMUX_GPIO(GPIO_FN_D4, D4_MARK), + PINMUX_GPIO(GPIO_FN_D3, D3_MARK), + PINMUX_GPIO(GPIO_FN_D2, D2_MARK), + PINMUX_GPIO(GPIO_FN_D1, D1_MARK), + PINMUX_GPIO(GPIO_FN_D0, D0_MARK), + + PINMUX_GPIO(GPIO_FN_BS, BS_MARK), + PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), + PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), + PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), + PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), + PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), + PINMUX_GPIO(GPIO_FN_CS6CE1B, CS6CE1B_MARK), + PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK), + PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), + PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), + PINMUX_GPIO(GPIO_FN_RD, RD_MARK), + PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), + PINMUX_GPIO(GPIO_FN_ICIOWRAH, ICIOWRAH_MARK), + PINMUX_GPIO(GPIO_FN_ICIORD, ICIORD_MARK), + PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK), + PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK), + PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), + PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), + PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), + PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), + PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), + PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + + /* TMU */ + PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), + PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK), + PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK), + PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK), + PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK), + + /* SCIF */ + PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), + PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), + PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), + PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), + PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), + PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), + PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), + PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), + PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), + PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), + PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), + PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), + PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), + PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), + PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), + PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), + PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK), + PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK), + PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK), + PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK), + PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK), + PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK), + PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK), + PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK), + + /* RSPI */ + PINMUX_GPIO(GPIO_FN_RSPCK0, RSPCK0_MARK), + PINMUX_GPIO(GPIO_FN_MOSI0, MOSI0_MARK), + PINMUX_GPIO(GPIO_FN_MISO0_PF12, MISO0_PF12_MARK), + PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK), + PINMUX_GPIO(GPIO_FN_SSL00, SSL00_MARK), + PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK), + PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK), + PINMUX_GPIO(GPIO_FN_MISO1_PG19, MISO1_PG19_MARK), + PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK), + + /* IIC3 */ + PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), + PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), + PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), + PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), + PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), + PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), + + /* SSI */ + PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), + PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK), + PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), + PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), + + /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */ + PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK), + PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK), + + /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */ + PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK), + PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK), + + /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ + PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), + PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), + + /* VDC3 */ + PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), + PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), + PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), + + PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK), + + PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), + PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK), + PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK), + PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK), + + PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), + + PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PA3_IN, PA3_OUT, + PA2_IN, PA2_OUT, + PA1_IN, PA1_OUT, + PA0_IN, PA0_OUT } + }, + + { PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PB22MD_00, PB22MD_01, PB22MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PB21MD_0, PB21MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PB20MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + + }, + { PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4) { + 0, PB19MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PB18MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PB17MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PB16MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4) { + 0, PB15MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PB14MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PB13MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PB12MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4) { + 0, PB11MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PB10MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PB9MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PB8MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4) { + 0, PB7MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PB6MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PB5MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PB4MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4) { + 0, PB3MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PB2MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PB1MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, + PB22_IN, PB22_OUT, + PB21_IN, PB21_OUT, + PB20_IN, PB20_OUT, + PB19_IN, PB19_OUT, + PB18_IN, PB18_OUT, + PB17_IN, PB17_OUT, + PB16_IN, PB16_OUT } + }, + + { PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1) { + PB15_IN, PB15_OUT, + PB14_IN, PB14_OUT, + PB13_IN, PB13_OUT, + PB12_IN, PB12_OUT, + PB11_IN, PB11_OUT, + PB10_IN, PB10_OUT, + PB9_IN, PB9_OUT, + PB8_IN, PB8_OUT, + PB7_IN, PB7_OUT, + PB6_IN, PB6_OUT, + PB5_IN, PB5_OUT, + PB4_IN, PB4_OUT, + PB3_IN, PB3_OUT, + PB2_IN, PB2_OUT, + PB1_IN, PB1_OUT, + 0, 0 } + }, + + { PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PC10MD_0, PC10MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PC9MD_0, PC9MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PC8MD_00, PC8MD_01, PC8MD_10, PC8MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PCCR1", 0xfffe384c, 16, 4) { + PC7MD_00, PC7MD_01, PC7MD_10, PC7MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PC6MD_00, PC6MD_01, PC6MD_10, PC6MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PC5MD_00, PC5MD_01, PC5MD_10, PC5MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PC4MD_0, PC4MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PCCR0", 0xfffe384e, 16, 4) { + PC3MD_0, PC3MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PC2MD_0, PC2MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PC1MD_0, PC1MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PC0MD_0, PC0MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + PC10_IN, PC10_OUT, + PC9_IN, PC9_OUT, + PC8_IN, PC8_OUT, + PC7_IN, PC7_OUT, + PC6_IN, PC6_OUT, + PC5_IN, PC5_OUT, + PC4_IN, PC4_OUT, + PC3_IN, PC3_OUT, + PC2_IN, PC2_OUT, + PC1_IN, PC1_OUT, + PC0_IN, PC0_OUT + } + }, + + { PINMUX_CFG_REG("PDCR3", 0xfffe3868, 16, 4) { + 0, PD15MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PD14MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PD13MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PD12MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PDCR2", 0xfffe386a, 16, 4) { + 0, PD11MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PD10MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PD9MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PD8MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PDCR1", 0xfffe386c, 16, 4) { + 0, PD7MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PD6MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PD5MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PD4MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PDCR0", 0xfffe386e, 16, 4) { + 0, PD3MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PD2MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PD1MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PD0MD_01, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PDIOR0", 0xfffe3872, 16, 1) { + PD15_IN, PD15_OUT, + PD14_IN, PD14_OUT, + PD13_IN, PD13_OUT, + PD12_IN, PD12_OUT, + PD11_IN, PD11_OUT, + PD10_IN, PD10_OUT, + PD9_IN, PD9_OUT, + PD8_IN, PD8_OUT, + PD7_IN, PD7_OUT, + PD6_IN, PD6_OUT, + PD5_IN, PD5_OUT, + PD4_IN, PD4_OUT, + PD3_IN, PD3_OUT, + PD2_IN, PD2_OUT, + PD1_IN, PD1_OUT, + PD0_IN, PD0_OUT } + }, + + { PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PE5MD_00, PE5MD_01, 0, PE5MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PE4MD_00, PE4MD_01, 0, PE4MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PECR0", 0xfffe388e, 16, 4) { + PE3MD_00, PE3MD_01, 0, PE3MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PE2MD_00, PE2MD_01, 0, PE2MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011, + PE1MD_100, PE1MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, + PE5_IN, PE5_OUT, + PE4_IN, PE4_OUT, + PE3_IN, PE3_OUT, + PE2_IN, PE2_OUT, + PE1_IN, PE1_OUT, + PE0_IN, PE0_OUT } + }, + + { PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4) { + PF12MD_000, PF12MD_001, 0, PF12MD_011, + PF12MD_100, PF12MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PFCR2", 0xfffe38aa, 16, 4) { + PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011, + PF11MD_100, PF11MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011, + PF10MD_100, PF10MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011, + PF9MD_100, PF9MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PF8MD_00, PF8MD_01, PF8MD_10, PF8MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PFCR1", 0xfffe38ac, 16, 4) { + PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011, + PF7MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011, + PF6MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011, + PF5MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011, + PF4MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PFCR0", 0xfffe38ae, 16, 4) { + PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011, + PF3MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011, + PF2MD_100, PF2MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011, + PF1MD_100, PF1MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + } + }, + + { PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1) { + 0, 0, 0, 0, 0, 0, + PF12_IN, PF12_OUT, + PF11_IN, PF11_OUT, + PF10_IN, PF10_OUT, + PF9_IN, PF9_OUT, + PF8_IN, PF8_OUT, + PF7_IN, PF7_OUT, + PF6_IN, PF6_OUT, + PF5_IN, PF5_OUT, + PF4_IN, PF4_OUT, + PF3_IN, PF3_OUT, + PF2_IN, PF2_OUT, + PF1_IN, PF1_OUT, + PF0_IN, PF0_OUT } + }, + + { PINMUX_CFG_REG("PGCR7", 0xfffe38c0, 16, 4) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011, + PG0MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PGCR5", 0xfffe38c4, 16, 4) { + PG23MD_00, PG23MD_01, PG23MD_10, PG23MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG22MD_00, PG22MD_01, PG22MD_10, PG22MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG21MD_00, PG21MD_01, PG21MD_10, PG21MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011, + PG20MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PGCR4", 0xfffe38c6, 16, 4) { + PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011, + PG19MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011, + PG18MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG17MD_000, PG17MD_001, PG17MD_010, PG17MD_011, + PG17MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG16MD_000, PG16MD_001, PG16MD_010, PG16MD_011, + PG16MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PGCR3", 0xfffe38c8, 16, 4) { + PG15MD_000, PG15MD_001, PG15MD_010, PG15MD_011, + PG15MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG14MD_000, PG14MD_001, PG14MD_010, 0, + PG14MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG13MD_000, PG13MD_001, PG13MD_010, 0, + PG13MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG12MD_000, PG12MD_001, PG12MD_010, 0, + PG12MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PGCR2", 0xfffe38ca, 16, 4) { + PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011, + PG11MD_100, PG11MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011, + PG10MD_100, PG10MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011, + PG9MD_100, PG9MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011, + PG8MD_100, PG8MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PGCR1", 0xfffe38cc, 16, 4) { + PG7MD_00, PG7MD_01, PG7MD_10, PG7MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG6MD_00, PG6MD_01, PG6MD_10, PG6MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG5MD_00, PG5MD_01, PG5MD_10, PG5MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG4MD_00, PG4MD_01, PG4MD_10, PG4MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4) { + PG3MD_00, PG3MD_01, PG3MD_10, PG3MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG2MD_00, PG2MD_01, PG2MD_10, PG2MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PG1MD_00, PG1MD_01, PG1MD_10, PG1MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + PG24_IN, PG24_OUT, + PG23_IN, PG23_OUT, + PG22_IN, PG22_OUT, + PG21_IN, PG21_OUT, + PG20_IN, PG20_OUT, + PG19_IN, PG19_OUT, + PG18_IN, PG18_OUT, + PG17_IN, PG17_OUT, + PG16_IN, PG16_OUT } + }, + + { PINMUX_CFG_REG("PGIOR0", 0xfffe38d2, 16, 1) { + PG15_IN, PG15_OUT, + PG14_IN, PG14_OUT, + PG13_IN, PG13_OUT, + PG12_IN, PG12_OUT, + PG11_IN, PG11_OUT, + PG10_IN, PG10_OUT, + PG9_IN, PG9_OUT, + PG8_IN, PG8_OUT, + PG7_IN, PG7_OUT, + PG6_IN, PG6_OUT, + PG5_IN, PG5_OUT, + PG4_IN, PG4_OUT, + PG3_IN, PG3_OUT, + PG2_IN, PG2_OUT, + PG1_IN, PG1_OUT, + PG0_IN, PG0_OUT + } + }, + + { PINMUX_CFG_REG("PHCR1", 0xfffe38ec, 16, 4) { + PH7MD_0, PH7MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PH6MD_0, PH6MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PH5MD_0, PH5MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PH4MD_0, PH4MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PHCR0", 0xfffe38ee, 16, 4) { + PH3MD_0, PH3MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PH2MD_0, PH2MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PH1MD_0, PH1MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PH0MD_0, PH0MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PJCR2", 0xfffe390a, 16, 4) { + PJ11MD_00, PJ11MD_01, PJ11MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PJ10MD_00, PJ10MD_01, PJ10MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PJ9MD_00, PJ9MD_01, PJ9MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PJ8MD_00, PJ8MD_01, PJ8MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PJCR1", 0xfffe390c, 16, 4) { + PJ7MD_00, PJ7MD_01, PJ7MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PJ6MD_00, PJ6MD_01, PJ6MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PJ5MD_00, PJ5MD_01, PJ5MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PJ4MD_00, PJ4MD_01, PJ4MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PJCR0", 0xfffe390e, 16, 4) { + PJ3MD_00, PJ3MD_01, PJ3MD_10, PJ3MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011, + PJ2MD_100, PJ2MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011, + PJ1MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011, + PJ0MD_100, PJ0MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG("PJIOR0", 0xfffe3912, 16, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, + PJ11_IN, PJ11_OUT, + PJ10_IN, PJ10_OUT, + PJ9_IN, PJ9_OUT, + PJ8_IN, PJ8_OUT, + PJ7_IN, PJ7_OUT, + PJ6_IN, PJ6_OUT, + PJ5_IN, PJ5_OUT, + PJ4_IN, PJ4_OUT, + PJ3_IN, PJ3_OUT, + PJ2_IN, PJ2_OUT, + PJ1_IN, PJ1_OUT, + PJ0_IN, PJ0_OUT } + }, + + { PINMUX_CFG_REG("PKCR2", 0xfffe392a, 16, 4) { + PK11MD_00, PK11MD_01, PK11MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PK10MD_00, PK10MD_01, PK10MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PK9MD_00, PK9MD_01, PK9MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PK8MD_00, PK8MD_01, PK8MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PKCR1", 0xfffe392c, 16, 4) { + PK7MD_00, PK7MD_01, PK7MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PK6MD_00, PK6MD_01, PK6MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PK5MD_00, PK5MD_01, PK5MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PK4MD_00, PK4MD_01, PK4MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PKCR0", 0xfffe392e, 16, 4) { + PK3MD_00, PK3MD_01, PK3MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PK2MD_00, PK2MD_01, PK2MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PK1MD_00, PK1MD_01, PK1MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PK0MD_00, PK0MD_01, PK0MD_10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PKIOR0", 0xfffe3932, 16, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, + PJ11_IN, PJ11_OUT, + PJ10_IN, PJ10_OUT, + PJ9_IN, PJ9_OUT, + PJ8_IN, PJ8_OUT, + PJ7_IN, PJ7_OUT, + PJ6_IN, PJ6_OUT, + PJ5_IN, PJ5_OUT, + PJ4_IN, PJ4_OUT, + PJ3_IN, PJ3_OUT, + PJ2_IN, PJ2_OUT, + PJ1_IN, PJ1_OUT, + PJ0_IN, PJ0_OUT } + }, + {} +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) { + 0, 0, 0, 0, 0, 0, 0, PA3_DATA, + 0, 0, 0, 0, 0, 0, 0, PA2_DATA } + }, + + { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) { + 0, 0, 0, 0, 0, 0, 0, PA1_DATA, + 0, 0, 0, 0, 0, 0, 0, PA0_DATA } + }, + + { PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PB22_DATA, PB21_DATA, PB20_DATA, + PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA } + }, + + { PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16) { + PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA, + PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA, + PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, + PB3_DATA, PB2_DATA, PB1_DATA, 0 } + }, + + { PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16) { + 0, 0, 0, 0, + 0, PC10_DATA, PC9_DATA, PC8_DATA, + PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, + PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA } + }, + + { PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16) { + PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA, + PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA, + PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, + PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA } + }, + + { PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, PE5_DATA, PE4_DATA, + PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA } + }, + + { PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16) { + 0, 0, 0, PF12_DATA, + PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA, + PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, + PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA } + }, + + { PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16) { + 0, 0, 0, 0, 0, 0, 0, PG24_DATA, + PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA, + PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA } + }, + + { PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16) { + PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA, + PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA, + PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, + PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA } + }, + { PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16) { + 0, 0, 0, PJ12_DATA, + PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA, + PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, + PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA } + }, + { PINMUX_DATA_REG("PKDR0", 0xfffe3936, 16) { + 0, 0, 0, PK12_DATA, + PK11_DATA, PK10_DATA, PK9_DATA, PK8_DATA, + PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA, + PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA } + }, + { } +}; + +static struct pinmux_info sh7264_pinmux_info = { + .name = "sh7264_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PA3, + .last_gpio = GPIO_FN_LCD_M_DISP, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +static int __init plat_pinmux_setup(void) +{ + return register_pinmux(&sh7264_pinmux_info); +} +arch_initcall(plat_pinmux_setup); -- cgit v0.10.2 From c5e50fa90ce42b1689692f587d4881308881b73d Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 10 May 2012 13:07:55 +0900 Subject: sh: Provide stubbed I/O routines for NO_IOPORT case. Too many drivers fail at IOPORT vs IOMEM checking before blindly calling in to the API, so we may as well just provide basic stubs to get more build coverage. Other platforms already do this, too (tile, parisc, etc.) Signed-off-by: Paul Mundt diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h index ec464a6..0cf60a6 100644 --- a/arch/sh/include/asm/io.h +++ b/arch/sh/include/asm/io.h @@ -218,8 +218,13 @@ __BUILD_IOPORT_STRING(w, u16) __BUILD_IOPORT_STRING(l, u32) __BUILD_IOPORT_STRING(q, u64) +#else /* !CONFIG_HAS_IOPORT */ + +#include + #endif + #define IO_SPACE_LIMIT 0xffffffff /* synco on SH-4A, otherwise a nop */ diff --git a/arch/sh/include/asm/io_noioport.h b/arch/sh/include/asm/io_noioport.h new file mode 100644 index 0000000..e136d28 --- /dev/null +++ b/arch/sh/include/asm/io_noioport.h @@ -0,0 +1,41 @@ +#ifndef __ASM_SH_IO_NOIOPORT_H +#define __ASM_SH_IO_NOIOPORT_H + +static inline u8 inb(unsigned long addr) +{ + BUG(); + return -1; +} + +static inline u16 inw(unsigned long addr) +{ + BUG(); + return -1; +} + +static inline u32 inl(unsigned long addr) +{ + BUG(); + return -1; +} + +#define outb(x, y) BUG() +#define outw(x, y) BUG() +#define outl(x, y) BUG() + +#define inb_p(addr) inb(addr) +#define inw_p(addr) inw(addr) +#define inl_p(addr) inl(addr) +#define outb_p(x, addr) outb((x), (addr)) +#define outw_p(x, addr) outw((x), (addr)) +#define outl_p(x, addr) outl((x), (addr)) + +#define insb(a, b, c) BUG() +#define insw(a, b, c) BUG() +#define insl(a, b, c) BUG() + +#define outsb(a, b, c) BUG() +#define outsw(a, b, c) BUG() +#define outsl(a, b, c) BUG() + +#endif /* __ASM_SH_IO_NOIOPORT_H */ -- cgit v0.10.2 From 40968126366219d11201257b5006878f939c1c5c Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 10 May 2012 14:21:15 +0900 Subject: watchdog: shwdt: Migrate from reboot notifier to platform shutdown. It's possible to do the same work via the platform driver shutdown method, so wire that up and dump the reboot notifier. Signed-off-by: Paul Mundt diff --git a/drivers/watchdog/shwdt.c b/drivers/watchdog/shwdt.c index 93958a7..74a261f 100644 --- a/drivers/watchdog/shwdt.c +++ b/drivers/watchdog/shwdt.c @@ -3,7 +3,7 @@ * * Watchdog driver for integrated watchdog in the SuperH processors. * - * Copyright (C) 2001 - 2010 Paul Mundt + * Copyright (C) 2001 - 2012 Paul Mundt * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -27,8 +27,6 @@ #include #include #include -#include -#include #include #include #include @@ -293,17 +291,6 @@ static long sh_wdt_ioctl(struct file *file, unsigned int cmd, return 0; } -static int sh_wdt_notify_sys(struct notifier_block *this, - unsigned long code, void *unused) -{ - struct sh_wdt *wdt = platform_get_drvdata(sh_wdt_dev); - - if (code == SYS_DOWN || code == SYS_HALT) - sh_wdt_stop(wdt); - - return NOTIFY_DONE; -} - static const struct file_operations sh_wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, @@ -320,10 +307,6 @@ static const struct watchdog_info sh_wdt_info = { .identity = "SH WDT", }; -static struct notifier_block sh_wdt_notifier = { - .notifier_call = sh_wdt_notify_sys, -}; - static struct miscdevice sh_wdt_miscdev = { .minor = WATCHDOG_MINOR, .name = "watchdog", @@ -365,13 +348,6 @@ static int __devinit sh_wdt_probe(struct platform_device *pdev) goto out_err; } - rc = register_reboot_notifier(&sh_wdt_notifier); - if (unlikely(rc)) { - dev_err(&pdev->dev, - "Can't register reboot notifier (err=%d)\n", rc); - goto out_unmap; - } - sh_wdt_miscdev.parent = wdt->dev; rc = misc_register(&sh_wdt_miscdev); @@ -379,7 +355,7 @@ static int __devinit sh_wdt_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Can't register miscdev on minor=%d (err=%d)\n", sh_wdt_miscdev.minor, rc); - goto out_unreg; + goto out_unmap; } init_timer(&wdt->timer); @@ -394,8 +370,6 @@ static int __devinit sh_wdt_probe(struct platform_device *pdev) return 0; -out_unreg: - unregister_reboot_notifier(&sh_wdt_notifier); out_unmap: devm_iounmap(&pdev->dev, wdt->base); out_err: @@ -417,7 +391,6 @@ static int __devexit sh_wdt_remove(struct platform_device *pdev) sh_wdt_dev = NULL; - unregister_reboot_notifier(&sh_wdt_notifier); devm_release_mem_region(&pdev->dev, res->start, resource_size(res)); devm_iounmap(&pdev->dev, wdt->base); devm_kfree(&pdev->dev, wdt); @@ -425,14 +398,22 @@ static int __devexit sh_wdt_remove(struct platform_device *pdev) return 0; } +static void sh_wdt_shutdown(struct platform_device *pdev) +{ + struct sh_wdt *wdt = platform_get_drvdata(pdev); + + sh_wdt_stop(wdt); +} + static struct platform_driver sh_wdt_driver = { .driver = { .name = DRV_NAME, .owner = THIS_MODULE, }, - .probe = sh_wdt_probe, - .remove = __devexit_p(sh_wdt_remove), + .probe = sh_wdt_probe, + .remove = __devexit_p(sh_wdt_remove), + .shutdown = sh_wdt_shutdown, }; static int __init sh_wdt_init(void) -- cgit v0.10.2 From 1950f499df4eacb5d89cf0151f5edda139b800f4 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 10 May 2012 15:07:53 +0900 Subject: watchdog: shwdt: Conversion to watchdog core. Fairly straightforward conversion to utilize watchdog core support. Signed-off-by: Paul Mundt diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 3709624..6795739 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -1138,6 +1138,7 @@ config ZVM_WATCHDOG config SH_WDT tristate "SuperH Watchdog" depends on SUPERH && (CPU_SH3 || CPU_SH4) + select WATCHDOG_CORE help This driver adds watchdog support for the integrated watchdog in the SuperH processors. If you have one of these processors and wish diff --git a/drivers/watchdog/shwdt.c b/drivers/watchdog/shwdt.c index 74a261f..0beabf2 100644 --- a/drivers/watchdog/shwdt.c +++ b/drivers/watchdog/shwdt.c @@ -27,12 +27,10 @@ #include #include #include -#include #include #include #include #include -#include #include #define DRV_NAME "sh-wdt" @@ -67,8 +65,6 @@ static int clock_division_ratio = WTCSR_CKS_4096; #define next_ping_period(cks) (jiffies + msecs_to_jiffies(cks - 4)) -static const struct watchdog_info sh_wdt_info; -static struct platform_device *sh_wdt_dev; static DEFINE_SPINLOCK(shwdt_lock); #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */ @@ -86,8 +82,9 @@ struct sh_wdt { char expect_close; }; -static void sh_wdt_start(struct sh_wdt *wdt) +static int sh_wdt_start(struct watchdog_device *wdt_dev) { + struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev); unsigned long flags; u8 csr; @@ -121,10 +118,13 @@ static void sh_wdt_start(struct sh_wdt *wdt) sh_wdt_write_rstcsr(csr); #endif spin_unlock_irqrestore(&shwdt_lock, flags); + + return 0; } -static void sh_wdt_stop(struct sh_wdt *wdt) +static int sh_wdt_stop(struct watchdog_device *wdt_dev) { + struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev); unsigned long flags; u8 csr; @@ -137,18 +137,22 @@ static void sh_wdt_stop(struct sh_wdt *wdt) sh_wdt_write_csr(csr); spin_unlock_irqrestore(&shwdt_lock, flags); + + return 0; } -static inline void sh_wdt_keepalive(struct sh_wdt *wdt) +static int sh_wdt_keepalive(struct watchdog_device *wdt_dev) { unsigned long flags; spin_lock_irqsave(&shwdt_lock, flags); next_heartbeat = jiffies + (heartbeat * HZ); spin_unlock_irqrestore(&shwdt_lock, flags); + + return 0; } -static int sh_wdt_set_heartbeat(int t) +static int sh_wdt_set_heartbeat(struct watchdog_device *wdt_dev, unsigned t) { unsigned long flags; @@ -157,7 +161,9 @@ static int sh_wdt_set_heartbeat(int t) spin_lock_irqsave(&shwdt_lock, flags); heartbeat = t; + wdt_dev->timeout = t; spin_unlock_irqrestore(&shwdt_lock, flags); + return 0; } @@ -183,123 +189,6 @@ static void sh_wdt_ping(unsigned long data) spin_unlock_irqrestore(&shwdt_lock, flags); } -static int sh_wdt_open(struct inode *inode, struct file *file) -{ - struct sh_wdt *wdt = platform_get_drvdata(sh_wdt_dev); - - if (test_and_set_bit(0, &wdt->enabled)) - return -EBUSY; - if (nowayout) - __module_get(THIS_MODULE); - - file->private_data = wdt; - - sh_wdt_start(wdt); - - return nonseekable_open(inode, file); -} - -static int sh_wdt_close(struct inode *inode, struct file *file) -{ - struct sh_wdt *wdt = file->private_data; - - if (wdt->expect_close == 42) { - sh_wdt_stop(wdt); - } else { - dev_crit(wdt->dev, "Unexpected close, not " - "stopping watchdog!\n"); - sh_wdt_keepalive(wdt); - } - - clear_bit(0, &wdt->enabled); - wdt->expect_close = 0; - - return 0; -} - -static ssize_t sh_wdt_write(struct file *file, const char *buf, - size_t count, loff_t *ppos) -{ - struct sh_wdt *wdt = file->private_data; - - if (count) { - if (!nowayout) { - size_t i; - - wdt->expect_close = 0; - - for (i = 0; i != count; i++) { - char c; - if (get_user(c, buf + i)) - return -EFAULT; - if (c == 'V') - wdt->expect_close = 42; - } - } - sh_wdt_keepalive(wdt); - } - - return count; -} - -static long sh_wdt_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) -{ - struct sh_wdt *wdt = file->private_data; - int new_heartbeat; - int options, retval = -EINVAL; - - switch (cmd) { - case WDIOC_GETSUPPORT: - return copy_to_user((struct watchdog_info *)arg, - &sh_wdt_info, sizeof(sh_wdt_info)) ? -EFAULT : 0; - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - return put_user(0, (int *)arg); - case WDIOC_SETOPTIONS: - if (get_user(options, (int *)arg)) - return -EFAULT; - - if (options & WDIOS_DISABLECARD) { - sh_wdt_stop(wdt); - retval = 0; - } - - if (options & WDIOS_ENABLECARD) { - sh_wdt_start(wdt); - retval = 0; - } - - return retval; - case WDIOC_KEEPALIVE: - sh_wdt_keepalive(wdt); - return 0; - case WDIOC_SETTIMEOUT: - if (get_user(new_heartbeat, (int *)arg)) - return -EFAULT; - - if (sh_wdt_set_heartbeat(new_heartbeat)) - return -EINVAL; - - sh_wdt_keepalive(wdt); - /* Fall */ - case WDIOC_GETTIMEOUT: - return put_user(heartbeat, (int *)arg); - default: - return -ENOTTY; - } - return 0; -} - -static const struct file_operations sh_wdt_fops = { - .owner = THIS_MODULE, - .llseek = no_llseek, - .write = sh_wdt_write, - .unlocked_ioctl = sh_wdt_ioctl, - .open = sh_wdt_open, - .release = sh_wdt_close, -}; - static const struct watchdog_info sh_wdt_info = { .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, @@ -307,10 +196,17 @@ static const struct watchdog_info sh_wdt_info = { .identity = "SH WDT", }; -static struct miscdevice sh_wdt_miscdev = { - .minor = WATCHDOG_MINOR, - .name = "watchdog", - .fops = &sh_wdt_fops, +static const struct watchdog_ops sh_wdt_ops = { + .owner = THIS_MODULE, + .start = sh_wdt_start, + .stop = sh_wdt_stop, + .ping = sh_wdt_keepalive, + .set_timeout = sh_wdt_set_heartbeat, +}; + +static struct watchdog_device sh_wdt_dev = { + .info = &sh_wdt_info, + .ops = &sh_wdt_ops, }; static int __devinit sh_wdt_probe(struct platform_device *pdev) @@ -348,13 +244,25 @@ static int __devinit sh_wdt_probe(struct platform_device *pdev) goto out_err; } - sh_wdt_miscdev.parent = wdt->dev; + rc = sh_wdt_set_heartbeat(&sh_wdt_dev, heartbeat); + if (unlikely(rc)) { + /* Default timeout if invalid */ + sh_wdt_set_heartbeat(&sh_wdt_dev, WATCHDOG_HEARTBEAT); + + dev_warn(&pdev->dev, + "heartbeat value must be 1<=x<=3600, using %d\n", + sh_wdt_dev.timeout); + } + + dev_info(&pdev->dev, "configured with heartbeat=%d sec (nowayout=%d)\n", + sh_wdt_dev.timeout, nowayout); - rc = misc_register(&sh_wdt_miscdev); + watchdog_set_nowayout(&sh_wdt_dev, nowayout); + watchdog_set_drvdata(&sh_wdt_dev, wdt); + + rc = watchdog_register_device(&sh_wdt_dev); if (unlikely(rc)) { - dev_err(&pdev->dev, - "Can't register miscdev on minor=%d (err=%d)\n", - sh_wdt_miscdev.minor, rc); + dev_err(&pdev->dev, "Can't register watchdog (err=%d)\n", rc); goto out_unmap; } @@ -364,7 +272,6 @@ static int __devinit sh_wdt_probe(struct platform_device *pdev) wdt->timer.expires = next_ping_period(clock_division_ratio); platform_set_drvdata(pdev, wdt); - sh_wdt_dev = pdev; dev_info(&pdev->dev, "initialized.\n"); @@ -387,9 +294,7 @@ static int __devexit sh_wdt_remove(struct platform_device *pdev) platform_set_drvdata(pdev, NULL); - misc_deregister(&sh_wdt_miscdev); - - sh_wdt_dev = NULL; + watchdog_unregister_device(&sh_wdt_dev); devm_release_mem_region(&pdev->dev, res->start, resource_size(res)); devm_iounmap(&pdev->dev, wdt->base); @@ -400,9 +305,7 @@ static int __devexit sh_wdt_remove(struct platform_device *pdev) static void sh_wdt_shutdown(struct platform_device *pdev) { - struct sh_wdt *wdt = platform_get_drvdata(pdev); - - sh_wdt_stop(wdt); + sh_wdt_stop(&sh_wdt_dev); } static struct platform_driver sh_wdt_driver = { @@ -418,8 +321,6 @@ static struct platform_driver sh_wdt_driver = { static int __init sh_wdt_init(void) { - int rc; - if (unlikely(clock_division_ratio < 0x5 || clock_division_ratio > 0x7)) { clock_division_ratio = WTCSR_CKS_4096; @@ -428,17 +329,6 @@ static int __init sh_wdt_init(void) clock_division_ratio); } - rc = sh_wdt_set_heartbeat(heartbeat); - if (unlikely(rc)) { - heartbeat = WATCHDOG_HEARTBEAT; - - pr_info("heartbeat value must be 1<=x<=3600, using %d\n", - heartbeat); - } - - pr_info("configured with heartbeat=%d sec (nowayout=%d)\n", - heartbeat, nowayout); - return platform_driver_register(&sh_wdt_driver); } -- cgit v0.10.2 From f9fb360cb3440fb7d22ad7061de4e99235a97e1c Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 10 May 2012 15:15:08 +0900 Subject: watchdog: shwdt: Migrate to per-device locking. Presently we've been using global locking for everything. Push the locking down to the per-device level in preparation for per-CPU watchdogs. Signed-off-by: Paul Mundt diff --git a/drivers/watchdog/shwdt.c b/drivers/watchdog/shwdt.c index 0beabf2..0d734a3 100644 --- a/drivers/watchdog/shwdt.c +++ b/drivers/watchdog/shwdt.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -65,8 +66,6 @@ static int clock_division_ratio = WTCSR_CKS_4096; #define next_ping_period(cks) (jiffies + msecs_to_jiffies(cks - 4)) -static DEFINE_SPINLOCK(shwdt_lock); - #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */ static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */ static bool nowayout = WATCHDOG_NOWAYOUT; @@ -75,6 +74,7 @@ static unsigned long next_heartbeat; struct sh_wdt { void __iomem *base; struct device *dev; + spinlock_t lock; struct timer_list timer; @@ -88,7 +88,7 @@ static int sh_wdt_start(struct watchdog_device *wdt_dev) unsigned long flags; u8 csr; - spin_lock_irqsave(&shwdt_lock, flags); + spin_lock_irqsave(&wdt->lock, flags); next_heartbeat = jiffies + (heartbeat * HZ); mod_timer(&wdt->timer, next_ping_period(clock_division_ratio)); @@ -117,7 +117,7 @@ static int sh_wdt_start(struct watchdog_device *wdt_dev) csr &= ~RSTCSR_RSTS; sh_wdt_write_rstcsr(csr); #endif - spin_unlock_irqrestore(&shwdt_lock, flags); + spin_unlock_irqrestore(&wdt->lock, flags); return 0; } @@ -128,7 +128,7 @@ static int sh_wdt_stop(struct watchdog_device *wdt_dev) unsigned long flags; u8 csr; - spin_lock_irqsave(&shwdt_lock, flags); + spin_lock_irqsave(&wdt->lock, flags); del_timer(&wdt->timer); @@ -136,33 +136,35 @@ static int sh_wdt_stop(struct watchdog_device *wdt_dev) csr &= ~WTCSR_TME; sh_wdt_write_csr(csr); - spin_unlock_irqrestore(&shwdt_lock, flags); + spin_unlock_irqrestore(&wdt->lock, flags); return 0; } static int sh_wdt_keepalive(struct watchdog_device *wdt_dev) { + struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev); unsigned long flags; - spin_lock_irqsave(&shwdt_lock, flags); + spin_lock_irqsave(&wdt->lock, flags); next_heartbeat = jiffies + (heartbeat * HZ); - spin_unlock_irqrestore(&shwdt_lock, flags); + spin_unlock_irqrestore(&wdt->lock, flags); return 0; } static int sh_wdt_set_heartbeat(struct watchdog_device *wdt_dev, unsigned t) { + struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev); unsigned long flags; if (unlikely(t < 1 || t > 3600)) /* arbitrary upper limit */ return -EINVAL; - spin_lock_irqsave(&shwdt_lock, flags); + spin_lock_irqsave(&wdt->lock, flags); heartbeat = t; wdt_dev->timeout = t; - spin_unlock_irqrestore(&shwdt_lock, flags); + spin_unlock_irqrestore(&wdt->lock, flags); return 0; } @@ -172,7 +174,7 @@ static void sh_wdt_ping(unsigned long data) struct sh_wdt *wdt = (struct sh_wdt *)data; unsigned long flags; - spin_lock_irqsave(&shwdt_lock, flags); + spin_lock_irqsave(&wdt->lock, flags); if (time_before(jiffies, next_heartbeat)) { u8 csr; @@ -186,7 +188,7 @@ static void sh_wdt_ping(unsigned long data) } else dev_warn(wdt->dev, "Heartbeat lost! Will not ping " "the watchdog\n"); - spin_unlock_irqrestore(&shwdt_lock, flags); + spin_unlock_irqrestore(&wdt->lock, flags); } static const struct watchdog_info sh_wdt_info = { @@ -238,12 +240,17 @@ static int __devinit sh_wdt_probe(struct platform_device *pdev) wdt->dev = &pdev->dev; + watchdog_set_nowayout(&sh_wdt_dev, nowayout); + watchdog_set_drvdata(&sh_wdt_dev, wdt); + wdt->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); if (unlikely(!wdt->base)) { rc = -ENXIO; goto out_err; } + spin_lock_init(&wdt->lock); + rc = sh_wdt_set_heartbeat(&sh_wdt_dev, heartbeat); if (unlikely(rc)) { /* Default timeout if invalid */ @@ -257,9 +264,6 @@ static int __devinit sh_wdt_probe(struct platform_device *pdev) dev_info(&pdev->dev, "configured with heartbeat=%d sec (nowayout=%d)\n", sh_wdt_dev.timeout, nowayout); - watchdog_set_nowayout(&sh_wdt_dev, nowayout); - watchdog_set_drvdata(&sh_wdt_dev, wdt); - rc = watchdog_register_device(&sh_wdt_dev); if (unlikely(rc)) { dev_err(&pdev->dev, "Can't register watchdog (err=%d)\n", rc); -- cgit v0.10.2 From f9e2eae6c66437a414988b44e1d2b8c025134883 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 10 May 2012 15:20:18 +0900 Subject: watchdog: shwdt: Trim down private data structure. Now that we're using the generic watchdog core, kill off unused elements from the private data structure. Signed-off-by: Paul Mundt diff --git a/drivers/watchdog/shwdt.c b/drivers/watchdog/shwdt.c index 0d734a3..de3630d 100644 --- a/drivers/watchdog/shwdt.c +++ b/drivers/watchdog/shwdt.c @@ -77,9 +77,6 @@ struct sh_wdt { spinlock_t lock; struct timer_list timer; - - unsigned long enabled; - char expect_close; }; static int sh_wdt_start(struct watchdog_device *wdt_dev) -- cgit v0.10.2 From 9ea6404691a520f734b819cbbd4757b0ea5f99c6 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 10 May 2012 15:46:48 +0900 Subject: watchdog: shwdt: Basic clock framework support. This plugs in basic clock framework support for the watchdog. As it's an optional MSTP bit, we don't particularly care if a platform has provided it or not, though a valid clock will need to be available for the more complex overflow period calculations found on newer parts -- this will be addressed later. Signed-off-by: Paul Mundt diff --git a/drivers/watchdog/shwdt.c b/drivers/watchdog/shwdt.c index de3630d..380ada4 100644 --- a/drivers/watchdog/shwdt.c +++ b/drivers/watchdog/shwdt.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #define DRV_NAME "sh-wdt" @@ -74,6 +75,7 @@ static unsigned long next_heartbeat; struct sh_wdt { void __iomem *base; struct device *dev; + struct clk *clk; spinlock_t lock; struct timer_list timer; @@ -225,27 +227,32 @@ static int __devinit sh_wdt_probe(struct platform_device *pdev) if (unlikely(!res)) return -EINVAL; - if (!devm_request_mem_region(&pdev->dev, res->start, - resource_size(res), DRV_NAME)) - return -EBUSY; - wdt = devm_kzalloc(&pdev->dev, sizeof(struct sh_wdt), GFP_KERNEL); - if (unlikely(!wdt)) { - rc = -ENOMEM; - goto out_release; - } + if (unlikely(!wdt)) + return -ENOMEM; wdt->dev = &pdev->dev; - watchdog_set_nowayout(&sh_wdt_dev, nowayout); - watchdog_set_drvdata(&sh_wdt_dev, wdt); + wdt->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(wdt->clk)) { + /* + * Clock framework support is optional, continue on + * anyways if we don't find a matching clock. + */ + wdt->clk = NULL; + } - wdt->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + clk_enable(wdt->clk); + + wdt->base = devm_request_and_ioremap(wdt->dev, res); if (unlikely(!wdt->base)) { - rc = -ENXIO; - goto out_err; + rc = -EADDRNOTAVAIL; + goto out_disable; } + watchdog_set_nowayout(&sh_wdt_dev, nowayout); + watchdog_set_drvdata(&sh_wdt_dev, wdt); + spin_lock_init(&wdt->lock); rc = sh_wdt_set_heartbeat(&sh_wdt_dev, heartbeat); @@ -264,7 +271,7 @@ static int __devinit sh_wdt_probe(struct platform_device *pdev) rc = watchdog_register_device(&sh_wdt_dev); if (unlikely(rc)) { dev_err(&pdev->dev, "Can't register watchdog (err=%d)\n", rc); - goto out_unmap; + goto out_disable; } init_timer(&wdt->timer); @@ -278,12 +285,9 @@ static int __devinit sh_wdt_probe(struct platform_device *pdev) return 0; -out_unmap: - devm_iounmap(&pdev->dev, wdt->base); -out_err: - devm_kfree(&pdev->dev, wdt); -out_release: - devm_release_mem_region(&pdev->dev, res->start, resource_size(res)); +out_disable: + clk_disable(wdt->clk); + clk_put(wdt->clk); return rc; } @@ -291,15 +295,13 @@ out_release: static int __devexit sh_wdt_remove(struct platform_device *pdev) { struct sh_wdt *wdt = platform_get_drvdata(pdev); - struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); platform_set_drvdata(pdev, NULL); watchdog_unregister_device(&sh_wdt_dev); - devm_release_mem_region(&pdev->dev, res->start, resource_size(res)); - devm_iounmap(&pdev->dev, wdt->base); - devm_kfree(&pdev->dev, wdt); + clk_disable(wdt->clk); + clk_put(wdt->clk); return 0; } -- cgit v0.10.2 From 8c013d964ac32c20afe2cdeadf59926d87012b37 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 10 May 2012 16:08:35 +0900 Subject: watchdog: shwdt: Preliminary runtime PM support. This plugs in some trivial runtime PM support in the probe/remove and start/stop paths. Signed-off-by: Paul Mundt diff --git a/drivers/watchdog/shwdt.c b/drivers/watchdog/shwdt.c index 380ada4..b1110470 100644 --- a/drivers/watchdog/shwdt.c +++ b/drivers/watchdog/shwdt.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -87,6 +88,8 @@ static int sh_wdt_start(struct watchdog_device *wdt_dev) unsigned long flags; u8 csr; + pm_runtime_get_sync(wdt->dev); + spin_lock_irqsave(&wdt->lock, flags); next_heartbeat = jiffies + (heartbeat * HZ); @@ -137,6 +140,8 @@ static int sh_wdt_stop(struct watchdog_device *wdt_dev) spin_unlock_irqrestore(&wdt->lock, flags); + pm_runtime_put_sync(wdt->dev); + return 0; } @@ -283,6 +288,8 @@ static int __devinit sh_wdt_probe(struct platform_device *pdev) dev_info(&pdev->dev, "initialized.\n"); + pm_runtime_enable(&pdev->dev); + return 0; out_disable: @@ -300,6 +307,7 @@ static int __devexit sh_wdt_remove(struct platform_device *pdev) watchdog_unregister_device(&sh_wdt_dev); + pm_runtime_disable(&pdev->dev); clk_disable(wdt->clk); clk_put(wdt->clk); -- cgit v0.10.2 From d42c97443da5a542201f6cbaf793606877115d05 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 10 May 2012 16:14:40 +0900 Subject: watchdog: shwdt: Use finer grained clock control. The clk enable/disable pairs can be pushed down to start/stop rather than probe/remove, along with the runtime PM callsites. This will allow us to keep the block powered off until userspace comes along and decides to do something with it. Signed-off-by: Paul Mundt diff --git a/drivers/watchdog/shwdt.c b/drivers/watchdog/shwdt.c index b1110470..e5b59be 100644 --- a/drivers/watchdog/shwdt.c +++ b/drivers/watchdog/shwdt.c @@ -89,6 +89,7 @@ static int sh_wdt_start(struct watchdog_device *wdt_dev) u8 csr; pm_runtime_get_sync(wdt->dev); + clk_enable(wdt->clk); spin_lock_irqsave(&wdt->lock, flags); @@ -140,6 +141,7 @@ static int sh_wdt_stop(struct watchdog_device *wdt_dev) spin_unlock_irqrestore(&wdt->lock, flags); + clk_disable(wdt->clk); pm_runtime_put_sync(wdt->dev); return 0; @@ -247,12 +249,10 @@ static int __devinit sh_wdt_probe(struct platform_device *pdev) wdt->clk = NULL; } - clk_enable(wdt->clk); - wdt->base = devm_request_and_ioremap(wdt->dev, res); if (unlikely(!wdt->base)) { rc = -EADDRNOTAVAIL; - goto out_disable; + goto err; } watchdog_set_nowayout(&sh_wdt_dev, nowayout); @@ -276,7 +276,7 @@ static int __devinit sh_wdt_probe(struct platform_device *pdev) rc = watchdog_register_device(&sh_wdt_dev); if (unlikely(rc)) { dev_err(&pdev->dev, "Can't register watchdog (err=%d)\n", rc); - goto out_disable; + goto err; } init_timer(&wdt->timer); @@ -292,8 +292,7 @@ static int __devinit sh_wdt_probe(struct platform_device *pdev) return 0; -out_disable: - clk_disable(wdt->clk); +err: clk_put(wdt->clk); return rc; @@ -308,7 +307,6 @@ static int __devexit sh_wdt_remove(struct platform_device *pdev) watchdog_unregister_device(&sh_wdt_dev); pm_runtime_disable(&pdev->dev); - clk_disable(wdt->clk); clk_put(wdt->clk); return 0; -- cgit v0.10.2 From 0b25b7c8cba83fa8c02fbf38eb905996f2455dd0 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Thu, 10 May 2012 09:26:52 +0100 Subject: sh: Add sh7269 device This is an sh2a device (max 266MHz) with FPU, video display controller (VDC), 8 serial ports, 4 I2C channels, 3 CAN ports, SD and on-chip USB. Signed-off-by: Phil Edworthy Signed-off-by: Paul Mundt diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 44a22dd..5970ae4 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -295,6 +295,13 @@ config CPU_SUBTYPE_SH7264 select SYS_SUPPORTS_CMT select SYS_SUPPORTS_MTU2 +config CPU_SUBTYPE_SH7269 + bool "Support SH7269 processor" + select CPU_SH2A + select CPU_HAS_FPU + select SYS_SUPPORTS_CMT + select SYS_SUPPORTS_MTU2 + config CPU_SUBTYPE_MXG bool "Support MX-G processor" select CPU_SH2A @@ -592,7 +599,7 @@ config SH_CLK_CPG_LEGACY depends on SH_CLK_CPG def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \ !CPU_SHX3 && !CPU_SUBTYPE_SH7757 && \ - !CPU_SUBTYPE_SH7264 + !CPU_SUBTYPE_SH7264 && !CPU_SUBTYPE_SH7269 source "kernel/time/Kconfig" diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h index 898db19..21f8342 100644 --- a/arch/sh/include/asm/processor.h +++ b/arch/sh/include/asm/processor.h @@ -18,7 +18,8 @@ enum cpu_type { CPU_SH7619, /* SH-2A types */ - CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_MXG, + CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_SH7269, + CPU_MXG, /* SH-3 types */ CPU_SH7705, CPU_SH7706, CPU_SH7707, diff --git a/arch/sh/kernel/cpu/proc.c b/arch/sh/kernel/cpu/proc.c index b5a9d8b..6ffb06f 100644 --- a/arch/sh/kernel/cpu/proc.c +++ b/arch/sh/kernel/cpu/proc.c @@ -7,7 +7,7 @@ static const char *cpu_name[] = { [CPU_SH7201] = "SH7201", [CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263", - [CPU_SH7264] = "SH7264", + [CPU_SH7264] = "SH7264", [CPU_SH7269] = "SH7269", [CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619", [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706", [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708", diff --git a/arch/sh/kernel/cpu/sh2a/Makefile b/arch/sh/kernel/cpu/sh2a/Makefile index 64b0986..dc52e36 100644 --- a/arch/sh/kernel/cpu/sh2a/Makefile +++ b/arch/sh/kernel/cpu/sh2a/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o obj-$(CONFIG_CPU_SUBTYPE_SH7264) += setup-sh7264.o clock-sh7264.o obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o +obj-$(CONFIG_CPU_SUBTYPE_SH7269) += setup-sh7269.o clock-sh7269.o obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o # Pinmux setup diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7269.c b/arch/sh/kernel/cpu/sh2a/clock-sh7269.c new file mode 100644 index 0000000..6b78762 --- /dev/null +++ b/arch/sh/kernel/cpu/sh2a/clock-sh7269.c @@ -0,0 +1,184 @@ +/* + * arch/sh/kernel/cpu/sh2a/clock-sh7269.c + * + * SH7269 clock framework support + * + * Copyright (C) 2012 Phil Edworthy + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include + +/* SH7269 registers */ +#define FRQCR 0xfffe0010 +#define STBCR3 0xfffe0408 +#define STBCR4 0xfffe040c +#define STBCR5 0xfffe0410 +#define STBCR6 0xfffe0414 +#define STBCR7 0xfffe0418 + +#define PLL_RATE 20 + +/* Fixed 32 KHz root clock for RTC */ +static struct clk r_clk = { + .rate = 32768, +}; + +/* + * Default rate for the root input clock, reset this with clk_set_rate() + * from the platform code. + */ +static struct clk extal_clk = { + .rate = 13340000, +}; + +static unsigned long pll_recalc(struct clk *clk) +{ + return clk->parent->rate * PLL_RATE; +} + +static struct sh_clk_ops pll_clk_ops = { + .recalc = pll_recalc, +}; + +static struct clk pll_clk = { + .ops = &pll_clk_ops, + .parent = &extal_clk, + .flags = CLK_ENABLE_ON_INIT, +}; + +static unsigned long peripheral0_recalc(struct clk *clk) +{ + return clk->parent->rate / 8; +} + +static struct sh_clk_ops peripheral0_clk_ops = { + .recalc = peripheral0_recalc, +}; + +static struct clk peripheral0_clk = { + .ops = &peripheral0_clk_ops, + .parent = &pll_clk, + .flags = CLK_ENABLE_ON_INIT, +}; + +static unsigned long peripheral1_recalc(struct clk *clk) +{ + return clk->parent->rate / 4; +} + +static struct sh_clk_ops peripheral1_clk_ops = { + .recalc = peripheral1_recalc, +}; + +static struct clk peripheral1_clk = { + .ops = &peripheral1_clk_ops, + .parent = &pll_clk, + .flags = CLK_ENABLE_ON_INIT, +}; + +struct clk *main_clks[] = { + &r_clk, + &extal_clk, + &pll_clk, + &peripheral0_clk, + &peripheral1_clk, +}; + +static int div2[] = { 1, 2, 0, 4 }; + +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = div2, + .nr_divisors = ARRAY_SIZE(div2), +}; + +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, +}; + +enum { DIV4_I, DIV4_B, + DIV4_NR }; + +#define DIV4(_reg, _bit, _mask, _flags) \ + SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) + +/* The mask field specifies the div2 entries that are valid */ +struct clk div4_clks[DIV4_NR] = { + [DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT + | CLK_ENABLE_ON_INIT), + [DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT + | CLK_ENABLE_ON_INIT), +}; + +enum { MSTP72, + MSTP60, + MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40, + MSTP35, MSTP32, MSTP30, + MSTP_NR }; + +static struct clk mstp_clks[MSTP_NR] = { + [MSTP72] = SH_CLK_MSTP8(&peripheral0_clk, STBCR7, 2, 0), /* CMT */ + [MSTP60] = SH_CLK_MSTP8(&peripheral1_clk, STBCR6, 0, 0), /* USB */ + [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */ + [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */ + [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */ + [MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */ + [MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */ + [MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */ + [MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */ + [MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */ + [MSTP35] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 5, 0), /* MTU2 */ + [MSTP32] = SH_CLK_MSTP8(&peripheral1_clk, STBCR3, 2, 0), /* ADC */ + [MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */ +}; + +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("rclk", &r_clk), + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("pll_clk", &pll_clk), + CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), + CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), + + /* MSTP clocks */ + CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]), + CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]), + CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP72]), + CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]), + CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP35]), + CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]), + CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]), +}; + +int __init arch_clk_init(void) +{ + int k, ret = 0; + + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + if (!ret) + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + + if (!ret) + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); + + return ret; +} diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c index 414b258..5170b6a 100644 --- a/arch/sh/kernel/cpu/sh2a/probe.c +++ b/arch/sh/kernel/cpu/sh2a/probe.c @@ -32,6 +32,9 @@ void __cpuinit cpu_probe(void) #elif defined(CONFIG_CPU_SUBTYPE_SH7264) boot_cpu_data.type = CPU_SH7264; boot_cpu_data.flags |= CPU_HAS_FPU; +#elif defined(CONFIG_CPU_SUBTYPE_SH7269) + boot_cpu_data.type = CPU_SH7269; + boot_cpu_data.flags |= CPU_HAS_FPU; #elif defined(CONFIG_CPU_SUBTYPE_SH7206) boot_cpu_data.type = CPU_SH7206; boot_cpu_data.flags |= CPU_HAS_DSP; diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c new file mode 100644 index 0000000..e82ae9d --- /dev/null +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c @@ -0,0 +1,615 @@ +/* + * SH7269 Setup + * + * Copyright (C) 2012 Renesas Electronics Europe Ltd + * Copyright (C) 2012 Phil Edworthy + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include + +enum { + UNUSED = 0, + + /* interrupt sources */ + IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, + PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, + + DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, + DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15, + USB, VDC4, CMT0, CMT1, BSC, WDT, + MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU, + MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V, + PWMT1, PWMT2, ADC_ADI, + SSIF0, SSII1, SSII2, SSII3, SSII4, SSII5, + RSPDIF, + IIC30, IIC31, IIC32, IIC33, + SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, + SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI, + SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI, + SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI, + SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI, + SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI, + SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI, + SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI, + RCAN0, RCAN1, RCAN2, + RSPIC0, RSPIC1, + IEBC, CD_ROMD, + NFMC, + SDHI0, SDHI1, + RTC, + SRCC0, SRCC1, SRCC2, + + /* interrupt groups */ + PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7, +}; + +static struct intc_vect vectors[] __initdata = { + INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), + INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), + INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), + INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), + + INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), + INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), + INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), + INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), + + INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109), + INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113), + INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117), + INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121), + INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125), + INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129), + INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133), + INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137), + INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141), + INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145), + INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149), + INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153), + INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157), + INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161), + INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165), + INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169), + + INTC_IRQ(USB, 170), + + INTC_IRQ(VDC4, 171), INTC_IRQ(VDC4, 172), + INTC_IRQ(VDC4, 173), INTC_IRQ(VDC4, 174), + INTC_IRQ(VDC4, 175), INTC_IRQ(VDC4, 176), + INTC_IRQ(VDC4, 177), INTC_IRQ(VDC4, 177), + + INTC_IRQ(CMT0, 188), INTC_IRQ(CMT1, 189), + + INTC_IRQ(BSC, 190), INTC_IRQ(WDT, 191), + + INTC_IRQ(MTU0_ABCD, 192), INTC_IRQ(MTU0_ABCD, 193), + INTC_IRQ(MTU0_ABCD, 194), INTC_IRQ(MTU0_ABCD, 195), + INTC_IRQ(MTU0_VEF, 196), INTC_IRQ(MTU0_VEF, 197), + INTC_IRQ(MTU0_VEF, 198), + INTC_IRQ(MTU1_AB, 199), INTC_IRQ(MTU1_AB, 200), + INTC_IRQ(MTU1_VU, 201), INTC_IRQ(MTU1_VU, 202), + INTC_IRQ(MTU2_AB, 203), INTC_IRQ(MTU2_AB, 204), + INTC_IRQ(MTU2_VU, 205), INTC_IRQ(MTU2_VU, 206), + INTC_IRQ(MTU3_ABCD, 207), INTC_IRQ(MTU3_ABCD, 208), + INTC_IRQ(MTU3_ABCD, 209), INTC_IRQ(MTU3_ABCD, 210), + INTC_IRQ(MTU3_TCI3V, 211), + INTC_IRQ(MTU4_ABCD, 212), INTC_IRQ(MTU4_ABCD, 213), + INTC_IRQ(MTU4_ABCD, 214), INTC_IRQ(MTU4_ABCD, 215), + INTC_IRQ(MTU4_TCI4V, 216), + + INTC_IRQ(PWMT1, 217), INTC_IRQ(PWMT2, 218), + + INTC_IRQ(ADC_ADI, 223), + + INTC_IRQ(SSIF0, 224), INTC_IRQ(SSIF0, 225), + INTC_IRQ(SSIF0, 226), + INTC_IRQ(SSII1, 227), INTC_IRQ(SSII1, 228), + INTC_IRQ(SSII2, 229), INTC_IRQ(SSII2, 230), + INTC_IRQ(SSII3, 231), INTC_IRQ(SSII3, 232), + INTC_IRQ(SSII4, 233), INTC_IRQ(SSII4, 234), + INTC_IRQ(SSII5, 235), INTC_IRQ(SSII5, 236), + + INTC_IRQ(RSPDIF, 237), + + INTC_IRQ(IIC30, 238), INTC_IRQ(IIC30, 239), + INTC_IRQ(IIC30, 240), INTC_IRQ(IIC30, 241), + INTC_IRQ(IIC30, 242), + INTC_IRQ(IIC31, 243), INTC_IRQ(IIC31, 244), + INTC_IRQ(IIC31, 245), INTC_IRQ(IIC31, 246), + INTC_IRQ(IIC31, 247), + INTC_IRQ(IIC32, 248), INTC_IRQ(IIC32, 249), + INTC_IRQ(IIC32, 250), INTC_IRQ(IIC32, 251), + INTC_IRQ(IIC32, 252), + INTC_IRQ(IIC33, 253), INTC_IRQ(IIC33, 254), + INTC_IRQ(IIC33, 255), INTC_IRQ(IIC33, 256), + INTC_IRQ(IIC33, 257), + + INTC_IRQ(SCIF0_BRI, 258), INTC_IRQ(SCIF0_ERI, 259), + INTC_IRQ(SCIF0_RXI, 260), INTC_IRQ(SCIF0_TXI, 261), + INTC_IRQ(SCIF1_BRI, 262), INTC_IRQ(SCIF1_ERI, 263), + INTC_IRQ(SCIF1_RXI, 264), INTC_IRQ(SCIF1_TXI, 265), + INTC_IRQ(SCIF2_BRI, 266), INTC_IRQ(SCIF2_ERI, 267), + INTC_IRQ(SCIF2_RXI, 268), INTC_IRQ(SCIF2_TXI, 269), + INTC_IRQ(SCIF3_BRI, 270), INTC_IRQ(SCIF3_ERI, 271), + INTC_IRQ(SCIF3_RXI, 272), INTC_IRQ(SCIF3_TXI, 273), + INTC_IRQ(SCIF4_BRI, 274), INTC_IRQ(SCIF4_ERI, 275), + INTC_IRQ(SCIF4_RXI, 276), INTC_IRQ(SCIF4_TXI, 277), + INTC_IRQ(SCIF5_BRI, 278), INTC_IRQ(SCIF5_ERI, 279), + INTC_IRQ(SCIF5_RXI, 280), INTC_IRQ(SCIF5_TXI, 281), + INTC_IRQ(SCIF6_BRI, 282), INTC_IRQ(SCIF6_ERI, 283), + INTC_IRQ(SCIF6_RXI, 284), INTC_IRQ(SCIF6_TXI, 285), + INTC_IRQ(SCIF7_BRI, 286), INTC_IRQ(SCIF7_ERI, 287), + INTC_IRQ(SCIF7_RXI, 288), INTC_IRQ(SCIF7_TXI, 289), + + INTC_IRQ(RCAN0, 291), INTC_IRQ(RCAN0, 292), + INTC_IRQ(RCAN0, 293), INTC_IRQ(RCAN0, 294), + INTC_IRQ(RCAN0, 295), + INTC_IRQ(RCAN1, 296), INTC_IRQ(RCAN1, 297), + INTC_IRQ(RCAN1, 298), INTC_IRQ(RCAN1, 299), + INTC_IRQ(RCAN1, 300), + INTC_IRQ(RCAN2, 301), INTC_IRQ(RCAN2, 302), + INTC_IRQ(RCAN2, 303), INTC_IRQ(RCAN2, 304), + INTC_IRQ(RCAN2, 305), + + INTC_IRQ(RSPIC0, 306), INTC_IRQ(RSPIC0, 307), + INTC_IRQ(RSPIC0, 308), + INTC_IRQ(RSPIC1, 309), INTC_IRQ(RSPIC1, 310), + INTC_IRQ(RSPIC1, 311), + + INTC_IRQ(IEBC, 318), + + INTC_IRQ(CD_ROMD, 319), INTC_IRQ(CD_ROMD, 320), + INTC_IRQ(CD_ROMD, 321), INTC_IRQ(CD_ROMD, 322), + INTC_IRQ(CD_ROMD, 323), INTC_IRQ(CD_ROMD, 324), + + INTC_IRQ(NFMC, 325), INTC_IRQ(NFMC, 326), + INTC_IRQ(NFMC, 327), INTC_IRQ(NFMC, 328), + + INTC_IRQ(SDHI0, 332), INTC_IRQ(SDHI0, 333), + INTC_IRQ(SDHI0, 334), + INTC_IRQ(SDHI1, 335), INTC_IRQ(SDHI1, 336), + INTC_IRQ(SDHI1, 337), + + INTC_IRQ(RTC, 338), INTC_IRQ(RTC, 339), + INTC_IRQ(RTC, 340), + + INTC_IRQ(SRCC0, 341), INTC_IRQ(SRCC0, 342), + INTC_IRQ(SRCC0, 343), INTC_IRQ(SRCC0, 344), + INTC_IRQ(SRCC0, 345), + INTC_IRQ(SRCC1, 346), INTC_IRQ(SRCC1, 347), + INTC_IRQ(SRCC1, 348), INTC_IRQ(SRCC1, 349), + INTC_IRQ(SRCC1, 350), + INTC_IRQ(SRCC2, 351), INTC_IRQ(SRCC2, 352), + INTC_IRQ(SRCC2, 353), INTC_IRQ(SRCC2, 354), + INTC_IRQ(SRCC2, 355), +}; + +static struct intc_group groups[] __initdata = { + INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, + PINT4, PINT5, PINT6, PINT7), + INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI), + INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI), + INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI), + INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI), + INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI), + INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI), + INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI), + INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI), +}; + +static struct intc_prio_reg prio_registers[] __initdata = { + { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, + { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, + { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } }, + { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } }, + { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } }, + { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8, DMAC9, + DMAC10, DMAC11 } }, + { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13, + DMAC14, DMAC15 } }, + { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC4, VDC4, VDC4 } }, + { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { 0, 0, 0, 0 } }, + { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { CMT0, CMT1, BSC, WDT } }, + { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU0_ABCD, MTU0_VEF, + MTU1_AB, MTU1_VU } }, + { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { MTU2_AB, MTU2_VU, + MTU3_ABCD, MTU3_TCI3V } }, + { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { MTU4_ABCD, MTU4_TCI4V, + PWMT1, PWMT2 } }, + { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { 0, 0, 0, 0 } }, + { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { ADC_ADI, SSIF0, SSII1, SSII2 } }, + { 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SSII3, SSII4, SSII5, RSPDIF} }, + { 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { IIC30, IIC31, IIC32, IIC33 } }, + { 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { SCIF0, SCIF1, SCIF2, SCIF3 } }, + { 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { SCIF4, SCIF5, SCIF6, SCIF7 } }, + { 0xfffe0c20, 0, 16, 4, /* IPR22 */ { 0, RCAN0, RCAN1, RCAN2 } }, + { 0xfffe0c22, 0, 16, 4, /* IPR23 */ { RSPIC0, RSPIC1, 0, 0 } }, + { 0xfffe0c24, 0, 16, 4, /* IPR24 */ { IEBC, CD_ROMD, NFMC, 0 } }, + { 0xfffe0c26, 0, 16, 4, /* IPR25 */ { SDHI0, SDHI1, RTC, 0 } }, + { 0xfffe0c28, 0, 16, 4, /* IPR26 */ { SRCC0, SRCC1, SRCC2, 0 } }, +}; + +static struct intc_mask_reg mask_registers[] __initdata = { + { 0xfffe0808, 0, 16, /* PINTER */ + { 0, 0, 0, 0, 0, 0, 0, 0, + PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups, + mask_registers, prio_registers, NULL); + +static struct plat_sci_port scif0_platform_data = { + .mapbase = 0xe8007000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | + SCSCR_REIE | SCSCR_TOIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { 259, 260, 261, 258 }, + .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +static struct plat_sci_port scif1_platform_data = { + .mapbase = 0xe8007800, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | + SCSCR_REIE | SCSCR_TOIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { 263, 264, 265, 262 }, + .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +static struct plat_sci_port scif2_platform_data = { + .mapbase = 0xe8008000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | + SCSCR_REIE | SCSCR_TOIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { 267, 268, 269, 266 }, + .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .dev = { + .platform_data = &scif2_platform_data, + }, +}; + +static struct plat_sci_port scif3_platform_data = { + .mapbase = 0xe8008800, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | + SCSCR_REIE | SCSCR_TOIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { 271, 272, 273, 270 }, + .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, +}; + +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 3, + .dev = { + .platform_data = &scif3_platform_data, + }, +}; + +static struct plat_sci_port scif4_platform_data = { + .mapbase = 0xe8009000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | + SCSCR_REIE | SCSCR_TOIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { 275, 276, 277, 274 }, + .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, +}; + +static struct platform_device scif4_device = { + .name = "sh-sci", + .id = 4, + .dev = { + .platform_data = &scif4_platform_data, + }, +}; + +static struct plat_sci_port scif5_platform_data = { + .mapbase = 0xe8009800, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | + SCSCR_REIE | SCSCR_TOIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { 279, 280, 281, 278 }, + .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, +}; + +static struct platform_device scif5_device = { + .name = "sh-sci", + .id = 5, + .dev = { + .platform_data = &scif5_platform_data, + }, +}; + +static struct plat_sci_port scif6_platform_data = { + .mapbase = 0xe800a000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | + SCSCR_REIE | SCSCR_TOIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { 283, 284, 285, 282 }, + .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, +}; + +static struct platform_device scif6_device = { + .name = "sh-sci", + .id = 6, + .dev = { + .platform_data = &scif6_platform_data, + }, +}; + +static struct plat_sci_port scif7_platform_data = { + .mapbase = 0xe800a800, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | + SCSCR_REIE | SCSCR_TOIE, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { 287, 288, 289, 286 }, + .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, +}; + +static struct platform_device scif7_device = { + .name = "sh-sci", + .id = 7, + .dev = { + .platform_data = &scif7_platform_data, + }, +}; + +static struct sh_timer_config cmt0_platform_data = { + .channel_offset = 0x02, + .timer_bit = 0, + .clockevent_rating = 125, + .clocksource_rating = 0, /* disabled due to code generation issues */ +}; + +static struct resource cmt0_resources[] = { + [0] = { + .start = 0xfffec002, + .end = 0xfffec007, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 188, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cmt0_device = { + .name = "sh_cmt", + .id = 0, + .dev = { + .platform_data = &cmt0_platform_data, + }, + .resource = cmt0_resources, + .num_resources = ARRAY_SIZE(cmt0_resources), +}; + +static struct sh_timer_config cmt1_platform_data = { + .channel_offset = 0x08, + .timer_bit = 1, + .clockevent_rating = 125, + .clocksource_rating = 0, /* disabled due to code generation issues */ +}; + +static struct resource cmt1_resources[] = { + [0] = { + .start = 0xfffec008, + .end = 0xfffec00d, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 189, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cmt1_device = { + .name = "sh_cmt", + .id = 1, + .dev = { + .platform_data = &cmt1_platform_data, + }, + .resource = cmt1_resources, + .num_resources = ARRAY_SIZE(cmt1_resources), +}; + +static struct sh_timer_config mtu2_0_platform_data = { + .channel_offset = -0x80, + .timer_bit = 0, + .clockevent_rating = 200, +}; + +static struct resource mtu2_0_resources[] = { + [0] = { + .start = 0xfffe4300, + .end = 0xfffe4326, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 192, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mtu2_0_device = { + .name = "sh_mtu2", + .id = 0, + .dev = { + .platform_data = &mtu2_0_platform_data, + }, + .resource = mtu2_0_resources, + .num_resources = ARRAY_SIZE(mtu2_0_resources), +}; + +static struct sh_timer_config mtu2_1_platform_data = { + .channel_offset = -0x100, + .timer_bit = 1, + .clockevent_rating = 200, +}; + +static struct resource mtu2_1_resources[] = { + [0] = { + .start = 0xfffe4380, + .end = 0xfffe4390, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 203, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mtu2_1_device = { + .name = "sh_mtu2", + .id = 1, + .dev = { + .platform_data = &mtu2_1_platform_data, + }, + .resource = mtu2_1_resources, + .num_resources = ARRAY_SIZE(mtu2_1_resources), +}; + +static struct resource rtc_resources[] = { + [0] = { + .start = 0xfffe6000, + .end = 0xfffe6000 + 0x30 - 1, + .flags = IORESOURCE_IO, + }, + [1] = { + /* Shared Period/Carry/Alarm IRQ */ + .start = 338, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device rtc_device = { + .name = "sh-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; + +/* USB Host */ +static struct r8a66597_platdata r8a66597_data = { + .on_chip = 1, + .endian = 1, +}; + +static struct resource r8a66597_usb_host_resources[] = { + [0] = { + .start = 0xe8010000, + .end = 0xe80100e4, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 170, + .end = 170, + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct platform_device r8a66597_usb_host_device = { + .name = "r8a66597_hcd", + .id = 0, + .dev = { + .dma_mask = NULL, /* not use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &r8a66597_data, + }, + .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources), + .resource = r8a66597_usb_host_resources, +}; + +static struct platform_device *sh7269_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &scif6_device, + &scif7_device, + &cmt0_device, + &cmt1_device, + &mtu2_0_device, + &mtu2_1_device, + &rtc_device, + &r8a66597_usb_host_device, +}; + +static int __init sh7269_devices_setup(void) +{ + return platform_add_devices(sh7269_devices, + ARRAY_SIZE(sh7269_devices)); +} +arch_initcall(sh7269_devices_setup); + +void __init plat_irq_setup(void) +{ + register_intc_controller(&intc_desc); +} + +static struct platform_device *sh7269_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &scif6_device, + &scif7_device, + &cmt0_device, + &cmt1_device, + &mtu2_0_device, + &mtu2_1_device, +}; + +void __init plat_early_device_setup(void) +{ + early_platform_add_devices(sh7269_early_devices, + ARRAY_SIZE(sh7269_early_devices)); +} -- cgit v0.10.2 From b6397435ec676271bd7fa1de9e62633718a754c1 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Thu, 10 May 2012 09:26:53 +0100 Subject: sh: Add RSK2+SH7269 board The RSK2+SH7269 board uses the SH7269 processor. It is often referred to as just rsk7269. NOR Flash, SDRAM, serial, USB Host and ethernet are working. Signed-off-by: Phil Edworthy Signed-off-by: Paul Mundt diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index ee92f42..7ee0498 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -133,7 +133,8 @@ config SH_RTS7751R2D config SH_RSK bool "Renesas Starter Kit" - depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7264 + depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203 || \ + CPU_SUBTYPE_SH7264 || CPU_SUBTYPE_SH7269 help Select this option if configuring for any of the RSK+ MCU evaluation platforms. diff --git a/arch/sh/boards/mach-rsk/Kconfig b/arch/sh/boards/mach-rsk/Kconfig index 4315af5..458a11f 100644 --- a/arch/sh/boards/mach-rsk/Kconfig +++ b/arch/sh/boards/mach-rsk/Kconfig @@ -18,6 +18,11 @@ config SH_RSK7264 select ARCH_REQUIRE_GPIOLIB depends on CPU_SUBTYPE_SH7264 +config SH_RSK7269 + bool "RSK2+SH7269" + select ARCH_REQUIRE_GPIOLIB + depends on CPU_SUBTYPE_SH7269 + endchoice endif diff --git a/arch/sh/boards/mach-rsk/Makefile b/arch/sh/boards/mach-rsk/Makefile index bae6ae4..6a4e1b5 100644 --- a/arch/sh/boards/mach-rsk/Makefile +++ b/arch/sh/boards/mach-rsk/Makefile @@ -1,3 +1,4 @@ obj-y := setup.o obj-$(CONFIG_SH_RSK7203) += devices-rsk7203.o obj-$(CONFIG_SH_RSK7264) += devices-rsk7264.o +obj-$(CONFIG_SH_RSK7269) += devices-rsk7269.o diff --git a/arch/sh/boards/mach-rsk/devices-rsk7269.c b/arch/sh/boards/mach-rsk/devices-rsk7269.c new file mode 100644 index 0000000..4a54459 --- /dev/null +++ b/arch/sh/boards/mach-rsk/devices-rsk7269.c @@ -0,0 +1,60 @@ +/* + * RSK+SH7269 Support + * + * Copyright (C) 2012 Renesas Electronics Europe Ltd + * Copyright (C) 2012 Phil Edworthy + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct smsc911x_platform_config smsc911x_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_16BIT | SMSC911X_SWAP_FIFO, +}; + +static struct resource smsc911x_resources[] = { + [0] = { + .start = 0x24000000, + .end = 0x240000ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 85, + .end = 85, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static struct platform_device *rsk7269_devices[] __initdata = { + &smsc911x_device, +}; + +static int __init rsk7269_devices_setup(void) +{ + return platform_add_devices(rsk7269_devices, + ARRAY_SIZE(rsk7269_devices)); +} +device_initcall(rsk7269_devices_setup); diff --git a/arch/sh/configs/rsk7269_defconfig b/arch/sh/configs/rsk7269_defconfig new file mode 100644 index 0000000..9f062b5 --- /dev/null +++ b/arch/sh/configs/rsk7269_defconfig @@ -0,0 +1,65 @@ +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_SLAB=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_SWAP_IO_SPACE=y +CONFIG_CPU_SUBTYPE_SH7269=y +CONFIG_MEMORY_START=0x0c000000 +CONFIG_MEMORY_SIZE=0x02000000 +CONFIG_FLATMEM_MANUAL=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_SH_RSK=y +# CONFIG_SH_TIMER_MTU2 is not set +CONFIG_SH_PCLK_FREQ=66700000 +CONFIG_BINFMT_FLAT=y +CONFIG_NET=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_FW_LOADER is not set +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_NETDEVICES=y +CONFIG_SMSC911X=y +CONFIG_SMSC_PHY=y +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=8 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +# CONFIG_HWMON is not set +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_R8A66597_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DEBUG=y +CONFIG_USB_LIBUSUAL=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_VFAT_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_FTRACE is not set diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types index d007c81..569977e 100644 --- a/arch/sh/tools/mach-types +++ b/arch/sh/tools/mach-types @@ -52,6 +52,7 @@ MIGOR SH_MIGOR RSK7201 SH_RSK7201 RSK7203 SH_RSK7203 RSK7264 SH_RSK7264 +RSK7269 SH_RSK7269 AP325RXA SH_AP325RXA SH2007 SH_SH2007 SH7757LCR SH_SH7757LCR -- cgit v0.10.2 From ef0fa5331a73e479a30f73e00937afb5109566d7 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Thu, 10 May 2012 09:26:54 +0100 Subject: sh: Add pinmux for sh7269 Signed-off-by: Phil Edworthy Signed-off-by: Paul Mundt diff --git a/arch/sh/include/cpu-sh2a/cpu/sh7269.h b/arch/sh/include/cpu-sh2a/cpu/sh7269.h new file mode 100644 index 0000000..48d1449 --- /dev/null +++ b/arch/sh/include/cpu-sh2a/cpu/sh7269.h @@ -0,0 +1,201 @@ +#ifndef __ASM_SH7269_H__ +#define __ASM_SH7269_H__ + +enum { + /* Port A */ + GPIO_PA1, GPIO_PA0, + + /* Port B */ + GPIO_PB22, GPIO_PB21, GPIO_PB20, + GPIO_PB19, GPIO_PB18, GPIO_PB17, GPIO_PB16, + GPIO_PB15, GPIO_PB14, GPIO_PB13, GPIO_PB12, + GPIO_PB11, GPIO_PB10, GPIO_PB9, GPIO_PB8, + GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4, + GPIO_PB3, GPIO_PB2, GPIO_PB1, + + /* Port C */ + GPIO_PC8, + GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4, + GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0, + + /* Port D */ + GPIO_PD15, GPIO_PD14, GPIO_PD13, GPIO_PD12, + GPIO_PD11, GPIO_PD10, GPIO_PD9, GPIO_PD8, + GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4, + GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0, + + /* Port E */ + GPIO_PE7, GPIO_PE6, GPIO_PE5, GPIO_PE4, + GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0, + + /* Port F */ + GPIO_PF23, GPIO_PF22, GPIO_PF21, GPIO_PF20, + GPIO_PF19, GPIO_PF18, GPIO_PF17, GPIO_PF16, + GPIO_PF15, GPIO_PF14, GPIO_PF13, GPIO_PF12, + GPIO_PF11, GPIO_PF10, GPIO_PF9, GPIO_PF8, + GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4, + GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0, + + /* Port G */ + GPIO_PG27, GPIO_PG26, GPIO_PG25, GPIO_PG24, + GPIO_PG23, GPIO_PG22, GPIO_PG21, GPIO_PG20, + GPIO_PG19, GPIO_PG18, GPIO_PG17, GPIO_PG16, + GPIO_PG15, GPIO_PG14, GPIO_PG13, GPIO_PG12, + GPIO_PG11, GPIO_PG10, GPIO_PG9, GPIO_PG8, + GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4, + GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0, + + /* Port H */ + GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4, + GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0, + + /* Port I - not on device */ + + /* Port J */ + GPIO_PJ31, GPIO_PJ30, GPIO_PJ29, GPIO_PJ28, + GPIO_PJ27, GPIO_PJ26, GPIO_PJ25, GPIO_PJ24, + GPIO_PJ23, GPIO_PJ22, GPIO_PJ21, GPIO_PJ20, + GPIO_PJ19, GPIO_PJ18, GPIO_PJ17, GPIO_PJ16, + GPIO_PJ15, GPIO_PJ14, GPIO_PJ13, GPIO_PJ12, + GPIO_PJ11, GPIO_PJ10, GPIO_PJ9, GPIO_PJ8, + GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4, + GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0, + + /* INTC: IRQ and PINT */ + GPIO_FN_IRQ7_PG, GPIO_FN_IRQ6_PG, GPIO_FN_IRQ5_PG, GPIO_FN_IRQ4_PG, + GPIO_FN_IRQ3_PG, GPIO_FN_IRQ2_PG, GPIO_FN_IRQ1_PG, GPIO_FN_IRQ0_PG, + GPIO_FN_IRQ7_PF, GPIO_FN_IRQ6_PF, GPIO_FN_IRQ5_PF, GPIO_FN_IRQ4_PF, + GPIO_FN_IRQ3_PJ, GPIO_FN_IRQ2_PJ, GPIO_FN_IRQ1_PJ, GPIO_FN_IRQ0_PJ, + GPIO_FN_IRQ1_PC, GPIO_FN_IRQ0_PC, + + GPIO_FN_PINT7_PG, GPIO_FN_PINT6_PG, GPIO_FN_PINT5_PG, GPIO_FN_PINT4_PG, + GPIO_FN_PINT3_PG, GPIO_FN_PINT2_PG, GPIO_FN_PINT1_PG, GPIO_FN_PINT0_PG, + GPIO_FN_PINT7_PH, GPIO_FN_PINT6_PH, GPIO_FN_PINT5_PH, GPIO_FN_PINT4_PH, + GPIO_FN_PINT3_PH, GPIO_FN_PINT2_PH, GPIO_FN_PINT1_PH, GPIO_FN_PINT0_PH, + GPIO_FN_PINT7_PJ, GPIO_FN_PINT6_PJ, GPIO_FN_PINT5_PJ, GPIO_FN_PINT4_PJ, + GPIO_FN_PINT3_PJ, GPIO_FN_PINT2_PJ, GPIO_FN_PINT1_PJ, GPIO_FN_PINT0_PJ, + + /* WDT */ + GPIO_FN_WDTOVF, + + /* CAN */ + GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1, + GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1, GPIO_FN_CRX0_CRX1_CRX2, + + /* DMAC */ + GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0, + GPIO_FN_TEND1, GPIO_FN_DACK1, GPIO_FN_DREQ1, + + /* ADC */ + GPIO_FN_ADTRG, + + /* BSC */ + GPIO_FN_A25, GPIO_FN_A24, + GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20, + GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16, + GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12, + GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8, + GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4, + GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0, + GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12, + GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8, + GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4, + GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0, + + GPIO_FN_BS, + GPIO_FN_CS4, GPIO_FN_CS3, GPIO_FN_CS2, GPIO_FN_CS1, GPIO_FN_CS0, + GPIO_FN_CS5CE1A, + GPIO_FN_CE2A, GPIO_FN_CE2B, + GPIO_FN_RD, GPIO_FN_RDWR, + GPIO_FN_WE3ICIOWRAHDQMUU, GPIO_FN_WE2ICIORDDQMUL, + GPIO_FN_WE1DQMUWE, GPIO_FN_WE0DQML, + GPIO_FN_RAS, GPIO_FN_CAS, GPIO_FN_CKE, + GPIO_FN_WAIT, GPIO_FN_BREQ, GPIO_FN_BACK, + GPIO_FN_IOIS16, + + /* TMU */ + GPIO_FN_TIOC4D, GPIO_FN_TIOC4C, GPIO_FN_TIOC4B, GPIO_FN_TIOC4A, + GPIO_FN_TIOC3D, GPIO_FN_TIOC3C, GPIO_FN_TIOC3B, GPIO_FN_TIOC3A, + GPIO_FN_TIOC2B, GPIO_FN_TIOC1B, GPIO_FN_TIOC2A, GPIO_FN_TIOC1A, + GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A, + GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA, + + /* SSU */ + GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD, + GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF, + GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD, + GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF, + + /* SCIF */ + GPIO_FN_SCK0, GPIO_FN_RXD0, GPIO_FN_TXD0, + GPIO_FN_SCK1, GPIO_FN_RXD1, GPIO_FN_TXD1, GPIO_FN_RTS1, GPIO_FN_CTS1, + GPIO_FN_SCK2, GPIO_FN_RXD2, GPIO_FN_TXD2, + GPIO_FN_SCK3, GPIO_FN_RXD3, GPIO_FN_TXD3, + GPIO_FN_SCK4, GPIO_FN_RXD4, GPIO_FN_TXD4, + GPIO_FN_SCK5, GPIO_FN_RXD5, GPIO_FN_TXD5, GPIO_FN_RTS5, GPIO_FN_CTS5, + GPIO_FN_SCK6, GPIO_FN_RXD6, GPIO_FN_TXD6, + GPIO_FN_SCK7, GPIO_FN_RXD7, GPIO_FN_TXD7, GPIO_FN_RTS7, GPIO_FN_CTS7, + + /* RSPI */ + GPIO_FN_MISO0_PJ19, GPIO_FN_MISO0_PB20, + GPIO_FN_MOSI0_PJ18, GPIO_FN_MOSI0_PB19, + GPIO_FN_SSL00_PJ17, GPIO_FN_SSL00_PB18, + GPIO_FN_RSPCK0_PJ16, GPIO_FN_RSPCK0_PB17, + GPIO_FN_RSPCK1, GPIO_FN_MOSI1, + GPIO_FN_MISO1, GPIO_FN_SSL10, + + /* IIC3 */ + GPIO_FN_SCL0, GPIO_FN_SCL1, GPIO_FN_SCL2, + GPIO_FN_SDA2, GPIO_FN_SDA1, GPIO_FN_SDA0, + + /* SSI */ + GPIO_FN_SSISCK0, GPIO_FN_SSIWS0, GPIO_FN_SSITXD0, GPIO_FN_SSIRXD0, + GPIO_FN_SSIWS1, GPIO_FN_SSIWS2, GPIO_FN_SSIWS3, + GPIO_FN_SSISCK1, GPIO_FN_SSISCK2, GPIO_FN_SSISCK3, + GPIO_FN_SSIDATA1, GPIO_FN_SSIDATA2, GPIO_FN_SSIDATA3, + GPIO_FN_AUDIO_CLK, + GPIO_FN_AUDIO_XOUT, + + /* SIOF */ + GPIO_FN_SIOFTXD, GPIO_FN_SIOFRXD, GPIO_FN_SIOFSYNC, GPIO_FN_SIOFSCK, + + /* SPDIF */ + GPIO_FN_SPDIF_IN, + GPIO_FN_SPDIF_OUT, + + /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ + GPIO_FN_FCE, + GPIO_FN_FRB, + + /* VDC */ + GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC, + GPIO_FN_DV_DATA23, GPIO_FN_DV_DATA22, + GPIO_FN_DV_DATA21, GPIO_FN_DV_DATA20, + GPIO_FN_DV_DATA19, GPIO_FN_DV_DATA18, + GPIO_FN_DV_DATA17, GPIO_FN_DV_DATA16, + GPIO_FN_DV_DATA15, GPIO_FN_DV_DATA14, + GPIO_FN_DV_DATA13, GPIO_FN_DV_DATA12, + GPIO_FN_DV_DATA11, GPIO_FN_DV_DATA10, + GPIO_FN_DV_DATA9, GPIO_FN_DV_DATA8, + GPIO_FN_DV_DATA7, GPIO_FN_DV_DATA6, + GPIO_FN_DV_DATA5, GPIO_FN_DV_DATA4, + GPIO_FN_DV_DATA3, GPIO_FN_DV_DATA2, + GPIO_FN_DV_DATA1, GPIO_FN_DV_DATA0, + GPIO_FN_LCD_CLK, GPIO_FN_LCD_EXTCLK, + GPIO_FN_LCD_VSYNC, GPIO_FN_LCD_HSYNC, GPIO_FN_LCD_DE, + GPIO_FN_LCD_DATA23, GPIO_FN_LCD_DATA22, + GPIO_FN_LCD_DATA21, GPIO_FN_LCD_DATA20, + GPIO_FN_LCD_DATA19, GPIO_FN_LCD_DATA18, + GPIO_FN_LCD_DATA17, GPIO_FN_LCD_DATA16, + GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14, + GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12, + GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10, + GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8, + GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6, + GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4, + GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2, + GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0, + GPIO_FN_LCD_M_DISP, +}; + +#endif /* __ASM_SH7269_H__ */ diff --git a/arch/sh/kernel/cpu/sh2a/Makefile b/arch/sh/kernel/cpu/sh2a/Makefile index dc52e36..7fdc102 100644 --- a/arch/sh/kernel/cpu/sh2a/Makefile +++ b/arch/sh/kernel/cpu/sh2a/Makefile @@ -19,5 +19,6 @@ obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o # Pinmux setup pinmux-$(CONFIG_CPU_SUBTYPE_SH7203) := pinmux-sh7203.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7264) := pinmux-sh7264.o +pinmux-$(CONFIG_CPU_SUBTYPE_SH7269) := pinmux-sh7269.o obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y) diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c new file mode 100644 index 0000000..9f0109f --- /dev/null +++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c @@ -0,0 +1,2799 @@ +/* + * SH7269 Pinmux + * + * Copyright (C) 2012 Renesas Electronics Europe Ltd + * Copyright (C) 2012 Phil Edworthy + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + /* Port A */ + PA1_DATA, PA0_DATA, + /* Port B */ + PB22_DATA, PB21_DATA, PB20_DATA, + PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA, + PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA, + PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA, + PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, + PB3_DATA, PB2_DATA, PB1_DATA, + /* Port C */ + PC8_DATA, + PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, + PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA, + /* Port D */ + PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA, + PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA, + PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, + PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, + /* Port E */ + PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA, + PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA, + /* Port F */ + PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA, + PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA, + PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA, + PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA, + PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, + PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, + /* Port G */ + PG27_DATA, PG26_DATA, PG25_DATA, PG24_DATA, + PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA, + PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA, + PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA, + PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA, + PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, + PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA, + /* Port H */ + /* NOTE - Port H does not have a Data Register, but PH Data is + connected to PH Port Register */ + PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA, + PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, + /* Port I - not on device */ + /* Port J */ + PJ31_DATA, PJ30_DATA, PJ29_DATA, PJ28_DATA, + PJ27_DATA, PJ26_DATA, PJ25_DATA, PJ24_DATA, + PJ23_DATA, PJ22_DATA, PJ21_DATA, PJ20_DATA, + PJ19_DATA, PJ18_DATA, PJ17_DATA, PJ16_DATA, + PJ15_DATA, PJ14_DATA, PJ13_DATA, PJ12_DATA, + PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA, + PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, + PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA, + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + FORCE_IN, + /* Port A */ + PA1_IN, PA0_IN, + /* Port B */ + PB22_IN, PB21_IN, PB20_IN, + PB19_IN, PB18_IN, PB17_IN, PB16_IN, + PB15_IN, PB14_IN, PB13_IN, PB12_IN, + PB11_IN, PB10_IN, PB9_IN, PB8_IN, + PB7_IN, PB6_IN, PB5_IN, PB4_IN, + PB3_IN, PB2_IN, PB1_IN, + /* Port C */ + PC8_IN, + PC7_IN, PC6_IN, PC5_IN, PC4_IN, + PC3_IN, PC2_IN, PC1_IN, PC0_IN, + /* Port D */ + PD15_IN, PD14_IN, PD13_IN, PD12_IN, + PD11_IN, PD10_IN, PD9_IN, PD8_IN, + PD7_IN, PD6_IN, PD5_IN, PD4_IN, + PD3_IN, PD2_IN, PD1_IN, PD0_IN, + /* Port E */ + PE7_IN, PE6_IN, PE5_IN, PE4_IN, + PE3_IN, PE2_IN, PE1_IN, PE0_IN, + /* Port F */ + PF23_IN, PF22_IN, PF21_IN, PF20_IN, + PF19_IN, PF18_IN, PF17_IN, PF16_IN, + PF15_IN, PF14_IN, PF13_IN, PF12_IN, + PF11_IN, PF10_IN, PF9_IN, PF8_IN, + PF7_IN, PF6_IN, PF5_IN, PF4_IN, + PF3_IN, PF2_IN, PF1_IN, PF0_IN, + /* Port G */ + PG27_IN, PG26_IN, PG25_IN, PG24_IN, + PG23_IN, PG22_IN, PG21_IN, PG20_IN, + PG19_IN, PG18_IN, PG17_IN, PG16_IN, + PG15_IN, PG14_IN, PG13_IN, PG12_IN, + PG11_IN, PG10_IN, PG9_IN, PG8_IN, + PG7_IN, PG6_IN, PG5_IN, PG4_IN, + PG3_IN, PG2_IN, PG1_IN, PG0_IN, + /* Port H - Port H does not have a Data Register */ + /* Port I - not on device */ + /* Port J */ + PJ31_IN, PJ30_IN, PJ29_IN, PJ28_IN, + PJ27_IN, PJ26_IN, PJ25_IN, PJ24_IN, + PJ23_IN, PJ22_IN, PJ21_IN, PJ20_IN, + PJ19_IN, PJ18_IN, PJ17_IN, PJ16_IN, + PJ15_IN, PJ14_IN, PJ13_IN, PJ12_IN, + PJ11_IN, PJ10_IN, PJ9_IN, PJ8_IN, + PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN, + PJ3_IN, PJ2_IN, PJ1_IN, PJ0_IN, + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + FORCE_OUT, + /* Port A */ + PA1_OUT, PA0_OUT, + /* Port B */ + PB22_OUT, PB21_OUT, PB20_OUT, + PB19_OUT, PB18_OUT, PB17_OUT, PB16_OUT, + PB15_OUT, PB14_OUT, PB13_OUT, PB12_OUT, + PB11_OUT, PB10_OUT, PB9_OUT, PB8_OUT, + PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT, + PB3_OUT, PB2_OUT, PB1_OUT, + /* Port C */ + PC8_OUT, + PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT, + PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT, + /* Port D */ + PD15_OUT, PD14_OUT, PD13_OUT, PD12_OUT, + PD11_OUT, PD10_OUT, PD9_OUT, PD8_OUT, + PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT, + PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT, + /* Port E */ + PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT, + PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT, + /* Port F */ + PF23_OUT, PF22_OUT, PF21_OUT, PF20_OUT, + PF19_OUT, PF18_OUT, PF17_OUT, PF16_OUT, + PF15_OUT, PF14_OUT, PF13_OUT, PF12_OUT, + PF11_OUT, PF10_OUT, PF9_OUT, PF8_OUT, + PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT, + PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT, + /* Port G */ + PG27_OUT, PG26_OUT, PG25_OUT, PG24_OUT, + PG23_OUT, PG22_OUT, PG21_OUT, PG20_OUT, + PG19_OUT, PG18_OUT, PG17_OUT, PG16_OUT, + PG15_OUT, PG14_OUT, PG13_OUT, PG12_OUT, + PG11_OUT, PG10_OUT, PG9_OUT, PG8_OUT, + PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT, + PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT, + /* Port H - Port H does not have a Data Register */ + /* Port I - not on device */ + /* Port J */ + PJ31_OUT, PJ30_OUT, PJ29_OUT, PJ28_OUT, + PJ27_OUT, PJ26_OUT, PJ25_OUT, PJ24_OUT, + PJ23_OUT, PJ22_OUT, PJ21_OUT, PJ20_OUT, + PJ19_OUT, PJ18_OUT, PJ17_OUT, PJ16_OUT, + PJ15_OUT, PJ14_OUT, PJ13_OUT, PJ12_OUT, + PJ11_OUT, PJ10_OUT, PJ9_OUT, PJ8_OUT, + PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT, + PJ3_OUT, PJ2_OUT, PJ1_OUT, PJ0_OUT, + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + /* Port A */ + PA1_IOR_IN, PA1_IOR_OUT, + PA0_IOR_IN, PA0_IOR_OUT, + + /* Port B */ + PB22_IOR_IN, PB22_IOR_OUT, + PB21_IOR_IN, PB21_IOR_OUT, + PB20_IOR_IN, PB20_IOR_OUT, + PB19_IOR_IN, PB19_IOR_OUT, + PB18_IOR_IN, PB18_IOR_OUT, + PB17_IOR_IN, PB17_IOR_OUT, + PB16_IOR_IN, PB16_IOR_OUT, + + PB15_IOR_IN, PB15_IOR_OUT, + PB14_IOR_IN, PB14_IOR_OUT, + PB13_IOR_IN, PB13_IOR_OUT, + PB12_IOR_IN, PB12_IOR_OUT, + PB11_IOR_IN, PB11_IOR_OUT, + PB10_IOR_IN, PB10_IOR_OUT, + PB9_IOR_IN, PB9_IOR_OUT, + PB8_IOR_IN, PB8_IOR_OUT, + + PB7_IOR_IN, PB7_IOR_OUT, + PB6_IOR_IN, PB6_IOR_OUT, + PB5_IOR_IN, PB5_IOR_OUT, + PB4_IOR_IN, PB4_IOR_OUT, + PB3_IOR_IN, PB3_IOR_OUT, + PB2_IOR_IN, PB2_IOR_OUT, + PB1_IOR_IN, PB1_IOR_OUT, + PB0_IOR_IN, PB0_IOR_OUT, + + PB22MD_000, PB22MD_001, PB22MD_010, PB22MD_011, + PB22MD_100, PB22MD_101, PB22MD_110, PB22MD_111, + PB21MD_00, PB21MD_01, PB21MD_10, PB21MD_11, + PB20MD_000, PB20MD_001, PB20MD_010, PB20MD_011, + PB20MD_100, PB20MD_101, PB20MD_110, PB20MD_111, + PB19MD_000, PB19MD_001, PB19MD_010, PB19MD_011, + PB19MD_100, PB19MD_101, PB19MD_110, PB19MD_111, + PB18MD_000, PB18MD_001, PB18MD_010, PB18MD_011, + PB18MD_100, PB18MD_101, PB18MD_110, PB18MD_111, + PB17MD_000, PB17MD_001, PB17MD_010, PB17MD_011, + PB17MD_100, PB17MD_101, PB17MD_110, PB17MD_111, + PB16MD_000, PB16MD_001, PB16MD_010, PB16MD_011, + PB16MD_100, PB16MD_101, PB16MD_110, PB16MD_111, + PB15MD_000, PB15MD_001, PB15MD_010, PB15MD_011, + PB15MD_100, PB15MD_101, PB15MD_110, PB15MD_111, + PB14MD_000, PB14MD_001, PB14MD_010, PB14MD_011, + PB14MD_100, PB14MD_101, PB14MD_110, PB14MD_111, + PB13MD_000, PB13MD_001, PB13MD_010, PB13MD_011, + PB13MD_100, PB13MD_101, PB13MD_110, PB13MD_111, + PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11, + + PB11MD_00, PB11MD_01, PB11MD_10, PB11MD_11, + PB10MD_00, PB10MD_01, PB10MD_10, PB10MD_11, + PB9MD_00, PB9MD_01, PB9MD_10, PB9MD_11, + PB8MD_00, PB8MD_01, PB8MD_10, PB8MD_11, + + PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11, + PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11, + PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11, + PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11, + + PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11, + PB2MD_00, PB2MD_01, PB2MD_10, PB2MD_11, + PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11, + + /* Port C */ + PC8_IOR_IN, PC8_IOR_OUT, + PC7_IOR_IN, PC7_IOR_OUT, + PC6_IOR_IN, PC6_IOR_OUT, + PC5_IOR_IN, PC5_IOR_OUT, + PC4_IOR_IN, PC4_IOR_OUT, + PC3_IOR_IN, PC3_IOR_OUT, + PC2_IOR_IN, PC2_IOR_OUT, + PC1_IOR_IN, PC1_IOR_OUT, + PC0_IOR_IN, PC0_IOR_OUT, + + PC8MD_000, PC8MD_001, PC8MD_010, PC8MD_011, + PC8MD_100, PC8MD_101, PC8MD_110, PC8MD_111, + PC7MD_000, PC7MD_001, PC7MD_010, PC7MD_011, + PC7MD_100, PC7MD_101, PC7MD_110, PC7MD_111, + PC6MD_000, PC6MD_001, PC6MD_010, PC6MD_011, + PC6MD_100, PC6MD_101, PC6MD_110, PC6MD_111, + PC5MD_000, PC5MD_001, PC5MD_010, PC5MD_011, + PC5MD_100, PC5MD_101, PC5MD_110, PC5MD_111, + PC4MD_00, PC4MD_01, PC4MD_10, PC4MD_11, + + PC3MD_00, PC3MD_01, PC3MD_10, PC3MD_11, + PC2MD_00, PC2MD_01, PC2MD_10, PC2MD_11, + PC1MD_0, PC1MD_1, + PC0MD_0, PC0MD_1, + + /* Port D */ + PD15_IOR_IN, PD15_IOR_OUT, + PD14_IOR_IN, PD14_IOR_OUT, + PD13_IOR_IN, PD13_IOR_OUT, + PD12_IOR_IN, PD12_IOR_OUT, + PD11_IOR_IN, PD11_IOR_OUT, + PD10_IOR_IN, PD10_IOR_OUT, + PD9_IOR_IN, PD9_IOR_OUT, + PD8_IOR_IN, PD8_IOR_OUT, + PD7_IOR_IN, PD7_IOR_OUT, + PD6_IOR_IN, PD6_IOR_OUT, + PD5_IOR_IN, PD5_IOR_OUT, + PD4_IOR_IN, PD4_IOR_OUT, + PD3_IOR_IN, PD3_IOR_OUT, + PD2_IOR_IN, PD2_IOR_OUT, + PD1_IOR_IN, PD1_IOR_OUT, + PD0_IOR_IN, PD0_IOR_OUT, + + PD15MD_00, PD15MD_01, PD15MD_10, PD15MD_11, + PD14MD_00, PD14MD_01, PD14MD_10, PD14MD_11, + PD13MD_00, PD13MD_01, PD13MD_10, PD13MD_11, + PD12MD_00, PD12MD_01, PD12MD_10, PD12MD_11, + + PD11MD_00, PD11MD_01, PD11MD_10, PD11MD_11, + PD10MD_00, PD10MD_01, PD10MD_10, PD10MD_11, + PD9MD_00, PD9MD_01, PD9MD_10, PD9MD_11, + PD8MD_00, PD8MD_01, PD8MD_10, PD8MD_11, + + PD7MD_00, PD7MD_01, PD7MD_10, PD7MD_11, + PD6MD_00, PD6MD_01, PD6MD_10, PD6MD_11, + PD5MD_00, PD5MD_01, PD5MD_10, PD5MD_11, + PD4MD_00, PD4MD_01, PD4MD_10, PD4MD_11, + + PD3MD_00, PD3MD_01, PD3MD_10, PD3MD_11, + PD2MD_00, PD2MD_01, PD2MD_10, PD2MD_11, + PD1MD_00, PD1MD_01, PD1MD_10, PD1MD_11, + PD0MD_00, PD0MD_01, PD0MD_10, PD0MD_11, + + /* Port E */ + PE7_IOR_IN, PE7_IOR_OUT, + PE6_IOR_IN, PE6_IOR_OUT, + PE5_IOR_IN, PE5_IOR_OUT, + PE4_IOR_IN, PE4_IOR_OUT, + PE3_IOR_IN, PE3_IOR_OUT, + PE2_IOR_IN, PE2_IOR_OUT, + PE1_IOR_IN, PE1_IOR_OUT, + PE0_IOR_IN, PE0_IOR_OUT, + + PE7MD_00, PE7MD_01, PE7MD_10, PE7MD_11, + PE6MD_00, PE6MD_01, PE6MD_10, PE6MD_11, + PE5MD_00, PE5MD_01, PE5MD_10, PE5MD_11, + PE4MD_00, PE4MD_01, PE4MD_10, PE4MD_11, + + PE3MD_000, PE3MD_001, PE3MD_010, PE3MD_011, + PE3MD_100, PE3MD_101, PE3MD_110, PE3MD_111, + PE2MD_000, PE2MD_001, PE2MD_010, PE2MD_011, + PE2MD_100, PE2MD_101, PE2MD_110, PE2MD_111, + PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011, + PE1MD_100, PE1MD_101, PE1MD_110, PE1MD_111, + PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, + + /* Port F */ + PF23_IOR_IN, PF23_IOR_OUT, + PF22_IOR_IN, PF22_IOR_OUT, + PF21_IOR_IN, PF21_IOR_OUT, + PF20_IOR_IN, PF20_IOR_OUT, + PF19_IOR_IN, PF19_IOR_OUT, + PF18_IOR_IN, PF18_IOR_OUT, + PF17_IOR_IN, PF17_IOR_OUT, + PF16_IOR_IN, PF16_IOR_OUT, + PF15_IOR_IN, PF15_IOR_OUT, + PF14_IOR_IN, PF14_IOR_OUT, + PF13_IOR_IN, PF13_IOR_OUT, + PF12_IOR_IN, PF12_IOR_OUT, + PF11_IOR_IN, PF11_IOR_OUT, + PF10_IOR_IN, PF10_IOR_OUT, + PF9_IOR_IN, PF9_IOR_OUT, + PF8_IOR_IN, PF8_IOR_OUT, + PF7_IOR_IN, PF7_IOR_OUT, + PF6_IOR_IN, PF6_IOR_OUT, + PF5_IOR_IN, PF5_IOR_OUT, + PF4_IOR_IN, PF4_IOR_OUT, + PF3_IOR_IN, PF3_IOR_OUT, + PF2_IOR_IN, PF2_IOR_OUT, + PF1_IOR_IN, PF1_IOR_OUT, + PF0_IOR_IN, PF0_IOR_OUT, + + PF23MD_000, PF23MD_001, PF23MD_010, PF23MD_011, + PF23MD_100, PF23MD_101, PF23MD_110, PF23MD_111, + PF22MD_000, PF22MD_001, PF22MD_010, PF22MD_011, + PF22MD_100, PF22MD_101, PF22MD_110, PF22MD_111, + PF21MD_000, PF21MD_001, PF21MD_010, PF21MD_011, + PF21MD_100, PF21MD_101, PF21MD_110, PF21MD_111, + PF20MD_000, PF20MD_001, PF20MD_010, PF20MD_011, + PF20MD_100, PF20MD_101, PF20MD_110, PF20MD_111, + + PF19MD_000, PF19MD_001, PF19MD_010, PF19MD_011, + PF19MD_100, PF19MD_101, PF19MD_110, PF19MD_111, + PF18MD_000, PF18MD_001, PF18MD_010, PF18MD_011, + PF18MD_100, PF18MD_101, PF18MD_110, PF18MD_111, + PF17MD_000, PF17MD_001, PF17MD_010, PF17MD_011, + PF17MD_100, PF17MD_101, PF17MD_110, PF17MD_111, + PF16MD_000, PF16MD_001, PF16MD_010, PF16MD_011, + PF16MD_100, PF16MD_101, PF16MD_110, PF16MD_111, + + PF15MD_000, PF15MD_001, PF15MD_010, PF15MD_011, + PF15MD_100, PF15MD_101, PF15MD_110, PF15MD_111, + PF14MD_000, PF14MD_001, PF14MD_010, PF14MD_011, + PF14MD_100, PF14MD_101, PF14MD_110, PF14MD_111, + PF13MD_000, PF13MD_001, PF13MD_010, PF13MD_011, + PF13MD_100, PF13MD_101, PF13MD_110, PF13MD_111, + PF12MD_000, PF12MD_001, PF12MD_010, PF12MD_011, + PF12MD_100, PF12MD_101, PF12MD_110, PF12MD_111, + + PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011, + PF11MD_100, PF11MD_101, PF11MD_110, PF11MD_111, + PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011, + PF10MD_100, PF10MD_101, PF10MD_110, PF10MD_111, + PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011, + PF9MD_100, PF9MD_101, PF9MD_110, PF9MD_111, + PF8MD_000, PF8MD_001, PF8MD_010, PF8MD_011, + PF8MD_100, PF8MD_101, PF8MD_110, PF8MD_111, + + PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011, + PF7MD_100, PF7MD_101, PF7MD_110, PF7MD_111, + PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011, + PF6MD_100, PF6MD_101, PF6MD_110, PF6MD_111, + PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011, + PF5MD_100, PF5MD_101, PF5MD_110, PF5MD_111, + PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011, + PF4MD_100, PF4MD_101, PF4MD_110, PF4MD_111, + + PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011, + PF3MD_100, PF3MD_101, PF3MD_110, PF3MD_111, + PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011, + PF2MD_100, PF2MD_101, PF2MD_110, PF2MD_111, + PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011, + PF1MD_100, PF1MD_101, PF1MD_110, PF1MD_111, + PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011, + PF0MD_100, PF0MD_101, PF0MD_110, PF0MD_111, + + /* Port G */ + PG27_IOR_IN, PG27_IOR_OUT, + PG26_IOR_IN, PG26_IOR_OUT, + PG25_IOR_IN, PG25_IOR_OUT, + PG24_IOR_IN, PG24_IOR_OUT, + PG23_IOR_IN, PG23_IOR_OUT, + PG22_IOR_IN, PG22_IOR_OUT, + PG21_IOR_IN, PG21_IOR_OUT, + PG20_IOR_IN, PG20_IOR_OUT, + PG19_IOR_IN, PG19_IOR_OUT, + PG18_IOR_IN, PG18_IOR_OUT, + PG17_IOR_IN, PG17_IOR_OUT, + PG16_IOR_IN, PG16_IOR_OUT, + PG15_IOR_IN, PG15_IOR_OUT, + PG14_IOR_IN, PG14_IOR_OUT, + PG13_IOR_IN, PG13_IOR_OUT, + PG12_IOR_IN, PG12_IOR_OUT, + PG11_IOR_IN, PG11_IOR_OUT, + PG10_IOR_IN, PG10_IOR_OUT, + PG9_IOR_IN, PG9_IOR_OUT, + PG8_IOR_IN, PG8_IOR_OUT, + PG7_IOR_IN, PG7_IOR_OUT, + PG6_IOR_IN, PG6_IOR_OUT, + PG5_IOR_IN, PG5_IOR_OUT, + PG4_IOR_IN, PG4_IOR_OUT, + PG3_IOR_IN, PG3_IOR_OUT, + PG2_IOR_IN, PG2_IOR_OUT, + PG1_IOR_IN, PG1_IOR_OUT, + PG0_IOR_IN, PG0_IOR_OUT, + + PG27MD_00, PG27MD_01, PG27MD_10, PG27MD_11, + PG26MD_00, PG26MD_01, PG26MD_10, PG26MD_11, + PG25MD_00, PG25MD_01, PG25MD_10, PG25MD_11, + PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, + + PG23MD_000, PG23MD_001, PG23MD_010, PG23MD_011, + PG23MD_100, PG23MD_101, PG23MD_110, PG23MD_111, + PG22MD_000, PG22MD_001, PG22MD_010, PG22MD_011, + PG22MD_100, PG22MD_101, PG22MD_110, PG22MD_111, + PG21MD_000, PG21MD_001, PG21MD_010, PG21MD_011, + PG21MD_100, PG21MD_101, PG21MD_110, PG21MD_111, + PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011, + PG20MD_100, PG20MD_101, PG20MD_110, PG20MD_111, + + PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011, + PG19MD_100, PG19MD_101, PG19MD_110, PG19MD_111, + PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011, + PG18MD_100, PG18MD_101, PG18MD_110, PG18MD_111, + PG17MD_00, PG17MD_01, PG17MD_10, PG17MD_11, + PG16MD_00, PG16MD_01, PG16MD_10, PG16MD_11, + + PG15MD_00, PG15MD_01, PG15MD_10, PG15MD_11, + PG14MD_00, PG14MD_01, PG14MD_10, PG14MD_11, + PG13MD_00, PG13MD_01, PG13MD_10, PG13MD_11, + PG12MD_00, PG12MD_01, PG12MD_10, PG12MD_11, + + PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011, + PG11MD_100, PG11MD_101, PG11MD_110, PG11MD_111, + PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011, + PG10MD_100, PG10MD_101, PG10MD_110, PG10MD_111, + PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011, + PG9MD_100, PG9MD_101, PG9MD_110, PG9MD_111, + PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011, + PG8MD_100, PG8MD_101, PG8MD_110, PG8MD_111, + + PG7MD_000, PG7MD_001, PG7MD_010, PG7MD_011, + PG7MD_100, PG7MD_101, PG7MD_110, PG7MD_111, + PG6MD_000, PG6MD_001, PG6MD_010, PG6MD_011, + PG6MD_100, PG6MD_101, PG6MD_110, PG6MD_111, + PG5MD_000, PG5MD_001, PG5MD_010, PG5MD_011, + PG5MD_100, PG5MD_101, PG5MD_110, PG5MD_111, + PG4MD_000, PG4MD_001, PG4MD_010, PG4MD_011, + PG4MD_100, PG4MD_101, PG4MD_110, PG4MD_111, + + PG3MD_000, PG3MD_001, PG3MD_010, PG3MD_011, + PG3MD_100, PG3MD_101, PG3MD_110, PG3MD_111, + PG2MD_000, PG2MD_001, PG2MD_010, PG2MD_011, + PG2MD_100, PG2MD_101, PG2MD_110, PG2MD_111, + PG1MD_000, PG1MD_001, PG1MD_010, PG1MD_011, + PG1MD_100, PG1MD_101, PG1MD_110, PG1MD_111, + PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011, + PG0MD_100, PG0MD_101, PG0MD_110, PG0MD_111, + + /* Port H */ + PH7MD_00, PH7MD_01, PH7MD_10, PH7MD_11, + PH6MD_00, PH6MD_01, PH6MD_10, PH6MD_11, + PH5MD_00, PH5MD_01, PH5MD_10, PH5MD_11, + PH4MD_00, PH4MD_01, PH4MD_10, PH4MD_11, + + PH3MD_00, PH3MD_01, PH3MD_10, PH3MD_11, + PH2MD_00, PH2MD_01, PH2MD_10, PH2MD_11, + PH1MD_00, PH1MD_01, PH1MD_10, PH1MD_11, + PH0MD_00, PH0MD_01, PH0MD_10, PH0MD_11, + + /* Port I - not on device */ + + /* Port J */ + PJ31_IOR_IN, PJ31_IOR_OUT, + PJ30_IOR_IN, PJ30_IOR_OUT, + PJ29_IOR_IN, PJ29_IOR_OUT, + PJ28_IOR_IN, PJ28_IOR_OUT, + PJ27_IOR_IN, PJ27_IOR_OUT, + PJ26_IOR_IN, PJ26_IOR_OUT, + PJ25_IOR_IN, PJ25_IOR_OUT, + PJ24_IOR_IN, PJ24_IOR_OUT, + PJ23_IOR_IN, PJ23_IOR_OUT, + PJ22_IOR_IN, PJ22_IOR_OUT, + PJ21_IOR_IN, PJ21_IOR_OUT, + PJ20_IOR_IN, PJ20_IOR_OUT, + PJ19_IOR_IN, PJ19_IOR_OUT, + PJ18_IOR_IN, PJ18_IOR_OUT, + PJ17_IOR_IN, PJ17_IOR_OUT, + PJ16_IOR_IN, PJ16_IOR_OUT, + PJ15_IOR_IN, PJ15_IOR_OUT, + PJ14_IOR_IN, PJ14_IOR_OUT, + PJ13_IOR_IN, PJ13_IOR_OUT, + PJ12_IOR_IN, PJ12_IOR_OUT, + PJ11_IOR_IN, PJ11_IOR_OUT, + PJ10_IOR_IN, PJ10_IOR_OUT, + PJ9_IOR_IN, PJ9_IOR_OUT, + PJ8_IOR_IN, PJ8_IOR_OUT, + PJ7_IOR_IN, PJ7_IOR_OUT, + PJ6_IOR_IN, PJ6_IOR_OUT, + PJ5_IOR_IN, PJ5_IOR_OUT, + PJ4_IOR_IN, PJ4_IOR_OUT, + PJ3_IOR_IN, PJ3_IOR_OUT, + PJ2_IOR_IN, PJ2_IOR_OUT, + PJ1_IOR_IN, PJ1_IOR_OUT, + PJ0_IOR_IN, PJ0_IOR_OUT, + + PJ31MD_0, PJ31MD_1, + PJ30MD_000, PJ30MD_001, PJ30MD_010, PJ30MD_011, + PJ30MD_100, PJ30MD_101, PJ30MD_110, PJ30MD_111, + PJ29MD_000, PJ29MD_001, PJ29MD_010, PJ29MD_011, + PJ29MD_100, PJ29MD_101, PJ29MD_110, PJ29MD_111, + PJ28MD_000, PJ28MD_001, PJ28MD_010, PJ28MD_011, + PJ28MD_100, PJ28MD_101, PJ28MD_110, PJ28MD_111, + + PJ27MD_000, PJ27MD_001, PJ27MD_010, PJ27MD_011, + PJ27MD_100, PJ27MD_101, PJ27MD_110, PJ27MD_111, + PJ26MD_000, PJ26MD_001, PJ26MD_010, PJ26MD_011, + PJ26MD_100, PJ26MD_101, PJ26MD_110, PJ26MD_111, + PJ25MD_000, PJ25MD_001, PJ25MD_010, PJ25MD_011, + PJ25MD_100, PJ25MD_101, PJ25MD_110, PJ25MD_111, + PJ24MD_000, PJ24MD_001, PJ24MD_010, PJ24MD_011, + PJ24MD_100, PJ24MD_101, PJ24MD_110, PJ24MD_111, + + PJ23MD_000, PJ23MD_001, PJ23MD_010, PJ23MD_011, + PJ23MD_100, PJ23MD_101, PJ23MD_110, PJ23MD_111, + PJ22MD_000, PJ22MD_001, PJ22MD_010, PJ22MD_011, + PJ22MD_100, PJ22MD_101, PJ22MD_110, PJ22MD_111, + PJ21MD_000, PJ21MD_001, PJ21MD_010, PJ21MD_011, + PJ21MD_100, PJ21MD_101, PJ21MD_110, PJ21MD_111, + PJ20MD_000, PJ20MD_001, PJ20MD_010, PJ20MD_011, + PJ20MD_100, PJ20MD_101, PJ20MD_110, PJ20MD_111, + + PJ19MD_000, PJ19MD_001, PJ19MD_010, PJ19MD_011, + PJ19MD_100, PJ19MD_101, PJ19MD_110, PJ19MD_111, + PJ18MD_000, PJ18MD_001, PJ18MD_010, PJ18MD_011, + PJ18MD_100, PJ18MD_101, PJ18MD_110, PJ18MD_111, + PJ17MD_000, PJ17MD_001, PJ17MD_010, PJ17MD_011, + PJ17MD_100, PJ17MD_101, PJ17MD_110, PJ17MD_111, + PJ16MD_000, PJ16MD_001, PJ16MD_010, PJ16MD_011, + PJ16MD_100, PJ16MD_101, PJ16MD_110, PJ16MD_111, + + PJ15MD_000, PJ15MD_001, PJ15MD_010, PJ15MD_011, + PJ15MD_100, PJ15MD_101, PJ15MD_110, PJ15MD_111, + PJ14MD_000, PJ14MD_001, PJ14MD_010, PJ14MD_011, + PJ14MD_100, PJ14MD_101, PJ14MD_110, PJ14MD_111, + PJ13MD_000, PJ13MD_001, PJ13MD_010, PJ13MD_011, + PJ13MD_100, PJ13MD_101, PJ13MD_110, PJ13MD_111, + PJ12MD_000, PJ12MD_001, PJ12MD_010, PJ12MD_011, + PJ12MD_100, PJ12MD_101, PJ12MD_110, PJ12MD_111, + + PJ11MD_000, PJ11MD_001, PJ11MD_010, PJ11MD_011, + PJ11MD_100, PJ11MD_101, PJ11MD_110, PJ11MD_111, + PJ10MD_000, PJ10MD_001, PJ10MD_010, PJ10MD_011, + PJ10MD_100, PJ10MD_101, PJ10MD_110, PJ10MD_111, + PJ9MD_000, PJ9MD_001, PJ9MD_010, PJ9MD_011, + PJ9MD_100, PJ9MD_101, PJ9MD_110, PJ9MD_111, + PJ8MD_000, PJ8MD_001, PJ8MD_010, PJ8MD_011, + PJ8MD_100, PJ8MD_101, PJ8MD_110, PJ8MD_111, + + PJ7MD_000, PJ7MD_001, PJ7MD_010, PJ7MD_011, + PJ7MD_100, PJ7MD_101, PJ7MD_110, PJ7MD_111, + PJ6MD_000, PJ6MD_001, PJ6MD_010, PJ6MD_011, + PJ6MD_100, PJ6MD_101, PJ6MD_110, PJ6MD_111, + PJ5MD_000, PJ5MD_001, PJ5MD_010, PJ5MD_011, + PJ5MD_100, PJ5MD_101, PJ5MD_110, PJ5MD_111, + PJ4MD_000, PJ4MD_001, PJ4MD_010, PJ4MD_011, + PJ4MD_100, PJ4MD_101, PJ4MD_110, PJ4MD_111, + + PJ3MD_000, PJ3MD_001, PJ3MD_010, PJ3MD_011, + PJ3MD_100, PJ3MD_101, PJ3MD_110, PJ3MD_111, + PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011, + PJ2MD_100, PJ2MD_101, PJ2MD_110, PJ2MD_111, + PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011, + PJ1MD_100, PJ1MD_101, PJ1MD_110, PJ1MD_111, + PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011, + PJ0MD_100, PJ0MD_101, PJ0MD_110, PJ0MD_111, + + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + /* Port H */ + PHAN7_MARK, PHAN6_MARK, PHAN5_MARK, PHAN4_MARK, + PHAN3_MARK, PHAN2_MARK, PHAN1_MARK, PHAN0_MARK, + + /* IRQs */ + IRQ7_PG_MARK, IRQ6_PG_MARK, IRQ5_PG_MARK, IRQ4_PG_MARK, + IRQ3_PG_MARK, IRQ2_PG_MARK, IRQ1_PG_MARK, IRQ0_PG_MARK, + IRQ7_PF_MARK, IRQ6_PF_MARK, IRQ5_PF_MARK, IRQ4_PF_MARK, + IRQ3_PJ_MARK, IRQ2_PJ_MARK, IRQ1_PJ_MARK, IRQ0_PJ_MARK, + IRQ1_PC_MARK, IRQ0_PC_MARK, + + PINT7_PG_MARK, PINT6_PG_MARK, PINT5_PG_MARK, PINT4_PG_MARK, + PINT3_PG_MARK, PINT2_PG_MARK, PINT1_PG_MARK, PINT0_PG_MARK, + PINT7_PH_MARK, PINT6_PH_MARK, PINT5_PH_MARK, PINT4_PH_MARK, + PINT3_PH_MARK, PINT2_PH_MARK, PINT1_PH_MARK, PINT0_PH_MARK, + PINT7_PJ_MARK, PINT6_PJ_MARK, PINT5_PJ_MARK, PINT4_PJ_MARK, + PINT3_PJ_MARK, PINT2_PJ_MARK, PINT1_PJ_MARK, PINT0_PJ_MARK, + + /* SD */ + SD_D0_MARK, SD_D1_MARK, SD_D2_MARK, SD_D3_MARK, + SD_WP_MARK, SD_CLK_MARK, SD_CMD_MARK, SD_CD_MARK, + + /* MMC */ + MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, + MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, + MMC_CLK_MARK, MMC_CMD_MARK, MMC_CD_MARK, + + /* PWM */ + PWM1A_MARK, PWM1B_MARK, PWM1C_MARK, PWM1D_MARK, + PWM1E_MARK, PWM1F_MARK, PWM1G_MARK, PWM1H_MARK, + PWM2A_MARK, PWM2B_MARK, PWM2C_MARK, PWM2D_MARK, + PWM2E_MARK, PWM2F_MARK, PWM2G_MARK, PWM2H_MARK, + + /* IEBus */ + IERXD_MARK, IETXD_MARK, + + /* WDT */ + WDTOVF_MARK, + + /* DMAC */ + TEND0_MARK, DACK0_MARK, DREQ0_MARK, + TEND1_MARK, DACK1_MARK, DREQ1_MARK, + + /* ADC */ + ADTRG_MARK, + + /* BSC */ + A25_MARK, A24_MARK, + A23_MARK, A22_MARK, A21_MARK, A20_MARK, + A19_MARK, A18_MARK, A17_MARK, A16_MARK, + A15_MARK, A14_MARK, A13_MARK, A12_MARK, + A11_MARK, A10_MARK, A9_MARK, A8_MARK, + A7_MARK, A6_MARK, A5_MARK, A4_MARK, + A3_MARK, A2_MARK, A1_MARK, A0_MARK, + D31_MARK, D30_MARK, D29_MARK, D28_MARK, + D27_MARK, D26_MARK, D25_MARK, D24_MARK, + D23_MARK, D22_MARK, D21_MARK, D20_MARK, + D19_MARK, D18_MARK, D17_MARK, D16_MARK, + D15_MARK, D14_MARK, D13_MARK, D12_MARK, + D11_MARK, D10_MARK, D9_MARK, D8_MARK, + D7_MARK, D6_MARK, D5_MARK, D4_MARK, + D3_MARK, D2_MARK, D1_MARK, D0_MARK, + BS_MARK, + CS4_MARK, CS3_MARK, CS2_MARK, CS1_MARK, CS0_MARK, + CS5CE1A_MARK, + CE2A_MARK, CE2B_MARK, + RD_MARK, RDWR_MARK, + WE3ICIOWRAHDQMUU_MARK, + WE2ICIORDDQMUL_MARK, + WE1DQMUWE_MARK, + WE0DQML_MARK, + RAS_MARK, CAS_MARK, CKE_MARK, + WAIT_MARK, BREQ_MARK, BACK_MARK, IOIS16_MARK, + + /* TMU */ + TIOC0A_MARK, TIOC0B_MARK, TIOC0C_MARK, TIOC0D_MARK, + TIOC1A_MARK, TIOC1B_MARK, + TIOC2A_MARK, TIOC2B_MARK, + TIOC3A_MARK, TIOC3B_MARK, TIOC3C_MARK, TIOC3D_MARK, + TIOC4A_MARK, TIOC4B_MARK, TIOC4C_MARK, TIOC4D_MARK, + TCLKA_MARK, TCLKB_MARK, TCLKC_MARK, TCLKD_MARK, + + /* SCIF */ + SCK0_MARK, RXD0_MARK, TXD0_MARK, + SCK1_MARK, RXD1_MARK, TXD1_MARK, RTS1_MARK, CTS1_MARK, + SCK2_MARK, RXD2_MARK, TXD2_MARK, + SCK3_MARK, RXD3_MARK, TXD3_MARK, + SCK4_MARK, RXD4_MARK, TXD4_MARK, + SCK5_MARK, RXD5_MARK, TXD5_MARK, RTS5_MARK, CTS5_MARK, + SCK6_MARK, RXD6_MARK, TXD6_MARK, + SCK7_MARK, RXD7_MARK, TXD7_MARK, RTS7_MARK, CTS7_MARK, + + /* RSPI */ + MISO0_PB20_MARK, MOSI0_PB19_MARK, SSL00_PB18_MARK, RSPCK0_PB17_MARK, + MISO0_PJ19_MARK, MOSI0_PJ18_MARK, SSL00_PJ17_MARK, RSPCK0_PJ16_MARK, + MISO1_MARK, MOSI1_MARK, SSL10_MARK, RSPCK1_MARK, + + /* IIC3 */ + SCL0_MARK, SDA0_MARK, + SCL1_MARK, SDA1_MARK, + SCL2_MARK, SDA2_MARK, + SCL3_MARK, SDA3_MARK, + + /* SSI */ + SSISCK0_MARK, SSIWS0_MARK, SSITXD0_MARK, SSIRXD0_MARK, + SSISCK1_MARK, SSIWS1_MARK, SSIDATA1_MARK, + SSISCK2_MARK, SSIWS2_MARK, SSIDATA2_MARK, + SSISCK3_MARK, SSIWS3_MARK, SSIDATA3_MARK, + SSISCK4_MARK, SSIWS4_MARK, SSIDATA4_MARK, + SSISCK5_MARK, SSIWS5_MARK, SSIDATA5_MARK, + AUDIO_CLK_MARK, + AUDIO_XOUT_MARK, + + /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */ + SIOFTXD_MARK, SIOFRXD_MARK, SIOFSYNC_MARK, SIOFSCK_MARK, + + /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */ + SPDIF_IN_MARK, SPDIF_OUT_MARK, + SPDIF_IN_PJ24_MARK, SPDIF_OUT_PJ25_MARK, + + /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ + FCE_MARK, + FRB_MARK, + + /* CAN */ + CRX0_MARK, CTX0_MARK, + CRX1_MARK, CTX1_MARK, + CRX2_MARK, CTX2_MARK, + CRX0CRX1_MARK, + CRX0CRX1CRX2_MARK, + CTX0CTX1CTX2_MARK, + CRX1_PJ22_MARK, CTX1_PJ23_MARK, + CRX2_PJ20_MARK, CTX2_PJ21_MARK, + CRX0CRX1_PJ22_MARK, + CRX0CRX1CRX2_PJ20_MARK, + + /* VDC */ + DV_CLK_MARK, + DV_VSYNC_MARK, DV_HSYNC_MARK, + DV_DATA23_MARK, DV_DATA22_MARK, DV_DATA21_MARK, DV_DATA20_MARK, + DV_DATA19_MARK, DV_DATA18_MARK, DV_DATA17_MARK, DV_DATA16_MARK, + DV_DATA15_MARK, DV_DATA14_MARK, DV_DATA13_MARK, DV_DATA12_MARK, + DV_DATA11_MARK, DV_DATA10_MARK, DV_DATA9_MARK, DV_DATA8_MARK, + DV_DATA7_MARK, DV_DATA6_MARK, DV_DATA5_MARK, DV_DATA4_MARK, + DV_DATA3_MARK, DV_DATA2_MARK, DV_DATA1_MARK, DV_DATA0_MARK, + LCD_CLK_MARK, LCD_EXTCLK_MARK, + LCD_VSYNC_MARK, LCD_HSYNC_MARK, LCD_DE_MARK, + LCD_DATA23_MARK, LCD_DATA22_MARK, LCD_DATA21_MARK, LCD_DATA20_MARK, + LCD_DATA19_MARK, LCD_DATA18_MARK, LCD_DATA17_MARK, LCD_DATA16_MARK, + LCD_DATA15_MARK, LCD_DATA14_MARK, LCD_DATA13_MARK, LCD_DATA12_MARK, + LCD_DATA11_MARK, LCD_DATA10_MARK, LCD_DATA9_MARK, LCD_DATA8_MARK, + LCD_DATA7_MARK, LCD_DATA6_MARK, LCD_DATA5_MARK, LCD_DATA4_MARK, + LCD_DATA3_MARK, LCD_DATA2_MARK, LCD_DATA1_MARK, LCD_DATA0_MARK, + LCD_TCON6_MARK, LCD_TCON5_MARK, LCD_TCON4_MARK, + LCD_TCON3_MARK, LCD_TCON2_MARK, LCD_TCON1_MARK, LCD_TCON0_MARK, + LCD_M_DISP_MARK, + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + + /* Port A */ + PINMUX_DATA(PA1_DATA, PA1_IN), + PINMUX_DATA(PA0_DATA, PA0_IN), + + /* Port B */ + PINMUX_DATA(PB22_DATA, PB22MD_000, PB22_IN, PB22_OUT), + PINMUX_DATA(A22_MARK, PB22MD_001), + PINMUX_DATA(CTX2_MARK, PB22MD_010), + PINMUX_DATA(IETXD_MARK, PB22MD_011), + PINMUX_DATA(CS4_MARK, PB22MD_100), + + PINMUX_DATA(PB21_DATA, PB21MD_00, PB21_IN, PB21_OUT), + PINMUX_DATA(A21_MARK, PB21MD_01), + PINMUX_DATA(CRX2_MARK, PB21MD_10), + PINMUX_DATA(IERXD_MARK, PB21MD_11), + + PINMUX_DATA(A20_MARK, PB20MD_001), + PINMUX_DATA(A19_MARK, PB19MD_001), + PINMUX_DATA(A18_MARK, PB18MD_001), + PINMUX_DATA(A17_MARK, PB17MD_001), + PINMUX_DATA(A16_MARK, PB16MD_001), + PINMUX_DATA(A15_MARK, PB15MD_001), + PINMUX_DATA(A14_MARK, PB14MD_001), + PINMUX_DATA(A13_MARK, PB13MD_001), + PINMUX_DATA(A12_MARK, PB12MD_01), + PINMUX_DATA(A11_MARK, PB11MD_01), + PINMUX_DATA(A10_MARK, PB10MD_01), + PINMUX_DATA(A9_MARK, PB9MD_01), + PINMUX_DATA(A8_MARK, PB8MD_01), + PINMUX_DATA(A7_MARK, PB7MD_01), + PINMUX_DATA(A6_MARK, PB6MD_01), + PINMUX_DATA(A5_MARK, PB5MD_01), + PINMUX_DATA(A4_MARK, PB4MD_01), + PINMUX_DATA(A3_MARK, PB3MD_01), + PINMUX_DATA(A2_MARK, PB2MD_01), + PINMUX_DATA(A1_MARK, PB1MD_01), + + /* Port C */ + PINMUX_DATA(PC8_DATA, PC8MD_000), + PINMUX_DATA(CS3_MARK, PC8MD_001), + PINMUX_DATA(TXD7_MARK, PC8MD_010), + PINMUX_DATA(CTX1_MARK, PC8MD_011), + + PINMUX_DATA(PC7_DATA, PC7MD_000), + PINMUX_DATA(CKE_MARK, PC7MD_001), + PINMUX_DATA(RXD7_MARK, PC7MD_010), + PINMUX_DATA(CRX1_MARK, PC7MD_011), + PINMUX_DATA(CRX0CRX1_MARK, PC7MD_100), + PINMUX_DATA(IRQ1_PC_MARK, PC7MD_101), + + PINMUX_DATA(PC6_DATA, PC6MD_000), + PINMUX_DATA(CAS_MARK, PC6MD_001), + PINMUX_DATA(SCK7_MARK, PC6MD_010), + PINMUX_DATA(CTX0_MARK, PC6MD_011), + + PINMUX_DATA(PC5_DATA, PC5MD_000), + PINMUX_DATA(RAS_MARK, PC5MD_001), + PINMUX_DATA(CRX0_MARK, PC5MD_011), + PINMUX_DATA(CTX0CTX1CTX2_MARK, PC5MD_100), + PINMUX_DATA(IRQ0_PC_MARK, PC5MD_101), + + PINMUX_DATA(PC4_DATA, PC4MD_00), + PINMUX_DATA(WE1DQMUWE_MARK, PC4MD_01), + PINMUX_DATA(TXD6_MARK, PC4MD_10), + + PINMUX_DATA(PC3_DATA, PC3MD_00), + PINMUX_DATA(WE0DQML_MARK, PC3MD_01), + PINMUX_DATA(RXD6_MARK, PC3MD_10), + + PINMUX_DATA(PC2_DATA, PC2MD_00), + PINMUX_DATA(RDWR_MARK, PC2MD_01), + PINMUX_DATA(SCK5_MARK, PC2MD_10), + + PINMUX_DATA(PC1_DATA, PC1MD_0), + PINMUX_DATA(RD_MARK, PC1MD_1), + + PINMUX_DATA(PC0_DATA, PC0MD_0), + PINMUX_DATA(CS0_MARK, PC0MD_1), + + /* Port D */ + PINMUX_DATA(D15_MARK, PD15MD_01), + PINMUX_DATA(D14_MARK, PD14MD_01), + + PINMUX_DATA(PD13_DATA, PD13MD_00), + PINMUX_DATA(D13_MARK, PD13MD_01), + PINMUX_DATA(PWM2F_MARK, PD13MD_10), + + PINMUX_DATA(PD12_DATA, PD12MD_00), + PINMUX_DATA(D12_MARK, PD12MD_01), + PINMUX_DATA(PWM2E_MARK, PD12MD_10), + + PINMUX_DATA(D11_MARK, PD11MD_01), + PINMUX_DATA(D10_MARK, PD10MD_01), + PINMUX_DATA(D9_MARK, PD9MD_01), + PINMUX_DATA(D8_MARK, PD8MD_01), + PINMUX_DATA(D7_MARK, PD7MD_01), + PINMUX_DATA(D6_MARK, PD6MD_01), + PINMUX_DATA(D5_MARK, PD5MD_01), + PINMUX_DATA(D4_MARK, PD4MD_01), + PINMUX_DATA(D3_MARK, PD3MD_01), + PINMUX_DATA(D2_MARK, PD2MD_01), + PINMUX_DATA(D1_MARK, PD1MD_01), + PINMUX_DATA(D0_MARK, PD0MD_01), + + /* Port E */ + PINMUX_DATA(PE7_DATA, PE7MD_00), + PINMUX_DATA(SDA3_MARK, PE7MD_01), + PINMUX_DATA(RXD7_MARK, PE7MD_10), + + PINMUX_DATA(PE6_DATA, PE6MD_00), + PINMUX_DATA(SCL3_MARK, PE6MD_01), + PINMUX_DATA(RXD6_MARK, PE6MD_10), + + PINMUX_DATA(PE5_DATA, PE5MD_00), + PINMUX_DATA(SDA2_MARK, PE5MD_01), + PINMUX_DATA(RXD5_MARK, PE5MD_10), + PINMUX_DATA(DV_HSYNC_MARK, PE5MD_11), + + PINMUX_DATA(PE4_DATA, PE4MD_00), + PINMUX_DATA(SCL2_MARK, PE4MD_01), + PINMUX_DATA(DV_VSYNC_MARK, PE4MD_11), + + PINMUX_DATA(PE3_DATA, PE3MD_000), + PINMUX_DATA(SDA1_MARK, PE3MD_001), + PINMUX_DATA(TCLKD_MARK, PE3MD_010), + PINMUX_DATA(ADTRG_MARK, PE3MD_011), + PINMUX_DATA(DV_HSYNC_MARK, PE3MD_100), + + PINMUX_DATA(PE2_DATA, PE2MD_000), + PINMUX_DATA(SCL1_MARK, PE2MD_001), + PINMUX_DATA(TCLKD_MARK, PE2MD_010), + PINMUX_DATA(IOIS16_MARK, PE2MD_011), + PINMUX_DATA(DV_VSYNC_MARK, PE2MD_100), + + PINMUX_DATA(PE1_DATA, PE1MD_000), + PINMUX_DATA(SDA0_MARK, PE1MD_001), + PINMUX_DATA(TCLKB_MARK, PE1MD_010), + PINMUX_DATA(AUDIO_CLK_MARK, PE1MD_010), + PINMUX_DATA(DV_CLK_MARK, PE1MD_100), + + PINMUX_DATA(PE0_DATA, PE0MD_00), + PINMUX_DATA(SCL0_MARK, PE0MD_01), + PINMUX_DATA(TCLKA_MARK, PE0MD_10), + PINMUX_DATA(LCD_EXTCLK_MARK, PE0MD_11), + + /* Port F */ + PINMUX_DATA(PF23_DATA, PF23MD_000), + PINMUX_DATA(SD_D2_MARK, PF23MD_001), + PINMUX_DATA(TXD3_MARK, PF23MD_100), + PINMUX_DATA(MMC_D2_MARK, PF23MD_101), + + PINMUX_DATA(PF22_DATA, PF22MD_000), + PINMUX_DATA(SD_D3_MARK, PF22MD_001), + PINMUX_DATA(RXD3_MARK, PF22MD_100), + PINMUX_DATA(MMC_D3_MARK, PF22MD_101), + + PINMUX_DATA(PF21_DATA, PF21MD_000), + PINMUX_DATA(SD_CMD_MARK, PF21MD_001), + PINMUX_DATA(SCK3_MARK, PF21MD_100), + PINMUX_DATA(MMC_CMD_MARK, PF21MD_101), + + PINMUX_DATA(PF20_DATA, PF20MD_000), + PINMUX_DATA(SD_CLK_MARK, PF20MD_001), + PINMUX_DATA(SSIDATA3_MARK, PF20MD_010), + PINMUX_DATA(MMC_CLK_MARK, PF20MD_101), + + PINMUX_DATA(PF19_DATA, PF19MD_000), + PINMUX_DATA(SD_D0_MARK, PF19MD_001), + PINMUX_DATA(SSIWS3_MARK, PF19MD_010), + PINMUX_DATA(IRQ7_PF_MARK, PF19MD_100), + PINMUX_DATA(MMC_D0_MARK, PF19MD_101), + + PINMUX_DATA(PF18_DATA, PF18MD_000), + PINMUX_DATA(SD_D1_MARK, PF18MD_001), + PINMUX_DATA(SSISCK3_MARK, PF18MD_010), + PINMUX_DATA(IRQ6_PF_MARK, PF18MD_100), + PINMUX_DATA(MMC_D1_MARK, PF18MD_101), + + PINMUX_DATA(PF17_DATA, PF17MD_000), + PINMUX_DATA(SD_WP_MARK, PF17MD_001), + PINMUX_DATA(FRB_MARK, PF17MD_011), + PINMUX_DATA(IRQ5_PF_MARK, PF17MD_100), + + PINMUX_DATA(PF16_DATA, PF16MD_000), + PINMUX_DATA(SD_CD_MARK, PF16MD_001), + PINMUX_DATA(FCE_MARK, PF16MD_011), + PINMUX_DATA(IRQ4_PF_MARK, PF16MD_100), + PINMUX_DATA(MMC_CD_MARK, PF16MD_101), + + PINMUX_DATA(PF15_DATA, PF15MD_000), + PINMUX_DATA(A0_MARK, PF15MD_001), + PINMUX_DATA(SSIDATA2_MARK, PF15MD_010), + PINMUX_DATA(WDTOVF_MARK, PF15MD_011), + PINMUX_DATA(TXD2_MARK, PF15MD_100), + + PINMUX_DATA(PF14_DATA, PF14MD_000), + PINMUX_DATA(A25_MARK, PF14MD_001), + PINMUX_DATA(SSIWS2_MARK, PF14MD_010), + PINMUX_DATA(RXD2_MARK, PF14MD_100), + + PINMUX_DATA(PF13_DATA, PF13MD_000), + PINMUX_DATA(A24_MARK, PF13MD_001), + PINMUX_DATA(SSISCK2_MARK, PF13MD_010), + PINMUX_DATA(SCK2_MARK, PF13MD_100), + + PINMUX_DATA(PF12_DATA, PF12MD_000), + PINMUX_DATA(SSIDATA1_MARK, PF12MD_010), + PINMUX_DATA(DV_DATA12_MARK, PF12MD_011), + PINMUX_DATA(TXD1_MARK, PF12MD_100), + PINMUX_DATA(MMC_D7_MARK, PF12MD_101), + + PINMUX_DATA(PF11_DATA, PF11MD_000), + PINMUX_DATA(SSIWS1_MARK, PF11MD_010), + PINMUX_DATA(DV_DATA2_MARK, PF11MD_011), + PINMUX_DATA(RXD1_MARK, PF11MD_100), + PINMUX_DATA(MMC_D6_MARK, PF11MD_101), + + PINMUX_DATA(PF10_DATA, PF10MD_000), + PINMUX_DATA(CS1_MARK, PF10MD_001), + PINMUX_DATA(SSISCK1_MARK, PF10MD_010), + PINMUX_DATA(DV_DATA1_MARK, PF10MD_011), + PINMUX_DATA(SCK1_MARK, PF10MD_100), + PINMUX_DATA(MMC_D5_MARK, PF10MD_101), + + PINMUX_DATA(PF9_DATA, PF9MD_000), + PINMUX_DATA(BS_MARK, PF9MD_001), + PINMUX_DATA(DV_DATA0_MARK, PF9MD_011), + PINMUX_DATA(SCK0_MARK, PF9MD_100), + PINMUX_DATA(MMC_D4_MARK, PF9MD_101), + PINMUX_DATA(RTS1_MARK, PF9MD_110), + + PINMUX_DATA(PF8_DATA, PF8MD_000), + PINMUX_DATA(A23_MARK, PF8MD_001), + PINMUX_DATA(TXD0_MARK, PF8MD_100), + + PINMUX_DATA(PF7_DATA, PF7MD_000), + PINMUX_DATA(SSIRXD0_MARK, PF7MD_010), + PINMUX_DATA(RXD0_MARK, PF7MD_100), + PINMUX_DATA(CTS1_MARK, PF7MD_110), + + PINMUX_DATA(PF6_DATA, PF6MD_000), + PINMUX_DATA(CE2A_MARK, PF6MD_001), + PINMUX_DATA(SSITXD0_MARK, PF6MD_010), + + PINMUX_DATA(PF5_DATA, PF5MD_000), + PINMUX_DATA(SSIWS0_MARK, PF5MD_010), + + PINMUX_DATA(PF4_DATA, PF4MD_000), + PINMUX_DATA(CS5CE1A_MARK, PF4MD_001), + PINMUX_DATA(SSISCK0_MARK, PF4MD_010), + + PINMUX_DATA(PF3_DATA, PF3MD_000), + PINMUX_DATA(CS2_MARK, PF3MD_001), + PINMUX_DATA(MISO1_MARK, PF3MD_011), + PINMUX_DATA(TIOC4D_MARK, PF3MD_100), + + PINMUX_DATA(PF2_DATA, PF2MD_000), + PINMUX_DATA(WAIT_MARK, PF2MD_001), + PINMUX_DATA(MOSI1_MARK, PF2MD_011), + PINMUX_DATA(TIOC4C_MARK, PF2MD_100), + PINMUX_DATA(TEND0_MARK, PF2MD_101), + + PINMUX_DATA(PF1_DATA, PF1MD_000), + PINMUX_DATA(BACK_MARK, PF1MD_001), + PINMUX_DATA(TIOC4B_MARK, PF1MD_100), + PINMUX_DATA(DACK0_MARK, PF1MD_101), + + PINMUX_DATA(PF0_DATA, PF0MD_000), + PINMUX_DATA(BREQ_MARK, PF0MD_001), + PINMUX_DATA(RSPCK1_MARK, PF0MD_011), + PINMUX_DATA(TIOC4A_MARK, PF0MD_100), + PINMUX_DATA(DREQ0_MARK, PF0MD_101), + + /* Port G */ + PINMUX_DATA(PG27_DATA, PG27MD_00), + PINMUX_DATA(LCD_TCON2_MARK, PG27MD_10), + PINMUX_DATA(LCD_EXTCLK_MARK, PG27MD_11), + + PINMUX_DATA(PG26_DATA, PG26MD_00), + PINMUX_DATA(LCD_TCON1_MARK, PG26MD_10), + + PINMUX_DATA(PG25_DATA, PG25MD_00), + PINMUX_DATA(LCD_TCON0_MARK, PG25MD_10), + + PINMUX_DATA(PG24_DATA, PG24MD_00), + PINMUX_DATA(LCD_CLK_MARK, PG24MD_10), + + PINMUX_DATA(PG23_DATA, PG23MD_000), + PINMUX_DATA(LCD_DATA23_MARK, PG23MD_010), + PINMUX_DATA(LCD_TCON6_MARK, PG23MD_011), + PINMUX_DATA(TXD5_MARK, PG23MD_100), + + PINMUX_DATA(PG22_DATA, PG22MD_000), + PINMUX_DATA(LCD_DATA22_MARK, PG22MD_010), + PINMUX_DATA(LCD_TCON5_MARK, PG22MD_011), + PINMUX_DATA(RXD5_MARK, PG22MD_100), + + PINMUX_DATA(PG21_DATA, PG21MD_000), + PINMUX_DATA(DV_DATA7_MARK, PG21MD_001), + PINMUX_DATA(LCD_DATA21_MARK, PG21MD_010), + PINMUX_DATA(LCD_TCON4_MARK, PG21MD_011), + PINMUX_DATA(TXD4_MARK, PG21MD_100), + + PINMUX_DATA(PG20_DATA, PG20MD_000), + PINMUX_DATA(DV_DATA6_MARK, PG20MD_001), + PINMUX_DATA(LCD_DATA20_MARK, PG21MD_010), + PINMUX_DATA(LCD_TCON3_MARK, PG20MD_011), + PINMUX_DATA(RXD4_MARK, PG20MD_100), + + PINMUX_DATA(PG19_DATA, PG19MD_000), + PINMUX_DATA(DV_DATA5_MARK, PG19MD_001), + PINMUX_DATA(LCD_DATA19_MARK, PG19MD_010), + PINMUX_DATA(SPDIF_OUT_MARK, PG19MD_011), + PINMUX_DATA(SCK5_MARK, PG19MD_100), + + PINMUX_DATA(PG18_DATA, PG18MD_000), + PINMUX_DATA(DV_DATA4_MARK, PG18MD_001), + PINMUX_DATA(LCD_DATA18_MARK, PG18MD_010), + PINMUX_DATA(SPDIF_IN_MARK, PG18MD_011), + PINMUX_DATA(SCK4_MARK, PG18MD_100), + +// TODO hardware manual has PG17 3 bits wide in reg picture and 2 bits in description +// we're going with 2 bits + PINMUX_DATA(PG17_DATA, PG17MD_00), + PINMUX_DATA(WE3ICIOWRAHDQMUU_MARK, PG17MD_01), + PINMUX_DATA(LCD_DATA17_MARK, PG17MD_10), + +// TODO hardware manual has PG16 3 bits wide in reg picture and 2 bits in description +// we're going with 2 bits + PINMUX_DATA(PG16_DATA, PG16MD_00), + PINMUX_DATA(WE2ICIORDDQMUL_MARK, PG16MD_01), + PINMUX_DATA(LCD_DATA16_MARK, PG16MD_10), + + PINMUX_DATA(PG15_DATA, PG15MD_00), + PINMUX_DATA(D31_MARK, PG15MD_01), + PINMUX_DATA(LCD_DATA15_MARK, PG15MD_10), + PINMUX_DATA(PINT7_PG_MARK, PG15MD_11), + + PINMUX_DATA(PG14_DATA, PG14MD_00), + PINMUX_DATA(D30_MARK, PG14MD_01), + PINMUX_DATA(LCD_DATA14_MARK, PG14MD_10), + PINMUX_DATA(PINT6_PG_MARK, PG14MD_11), + + PINMUX_DATA(PG13_DATA, PG13MD_00), + PINMUX_DATA(D29_MARK, PG13MD_01), + PINMUX_DATA(LCD_DATA13_MARK, PG13MD_10), + PINMUX_DATA(PINT5_PG_MARK, PG13MD_11), + + PINMUX_DATA(PG12_DATA, PG12MD_00), + PINMUX_DATA(D28_MARK, PG12MD_01), + PINMUX_DATA(LCD_DATA12_MARK, PG12MD_10), + PINMUX_DATA(PINT4_PG_MARK, PG12MD_11), + + PINMUX_DATA(PG11_DATA, PG11MD_000), + PINMUX_DATA(D27_MARK, PG11MD_001), + PINMUX_DATA(LCD_DATA11_MARK, PG11MD_010), + PINMUX_DATA(PINT3_PG_MARK, PG11MD_011), + PINMUX_DATA(TIOC3D_MARK, PG11MD_100), + + PINMUX_DATA(PG10_DATA, PG10MD_000), + PINMUX_DATA(D26_MARK, PG10MD_001), + PINMUX_DATA(LCD_DATA10_MARK, PG10MD_010), + PINMUX_DATA(PINT2_PG_MARK, PG10MD_011), + PINMUX_DATA(TIOC3C_MARK, PG10MD_100), + + PINMUX_DATA(PG9_DATA, PG9MD_000), + PINMUX_DATA(D25_MARK, PG9MD_001), + PINMUX_DATA(LCD_DATA9_MARK, PG9MD_010), + PINMUX_DATA(PINT1_PG_MARK, PG9MD_011), + PINMUX_DATA(TIOC3B_MARK, PG9MD_100), + + PINMUX_DATA(PG8_DATA, PG8MD_000), + PINMUX_DATA(D24_MARK, PG8MD_001), + PINMUX_DATA(LCD_DATA8_MARK, PG8MD_010), + PINMUX_DATA(PINT0_PG_MARK, PG8MD_011), + PINMUX_DATA(TIOC3A_MARK, PG8MD_100), + + PINMUX_DATA(PG7_DATA, PG7MD_000), + PINMUX_DATA(D23_MARK, PG7MD_001), + PINMUX_DATA(LCD_DATA7_MARK, PG7MD_010), + PINMUX_DATA(IRQ7_PG_MARK, PG7MD_011), + PINMUX_DATA(TIOC2B_MARK, PG7MD_100), + + PINMUX_DATA(PG6_DATA, PG6MD_000), + PINMUX_DATA(D22_MARK, PG6MD_001), + PINMUX_DATA(LCD_DATA6_MARK, PG6MD_010), + PINMUX_DATA(IRQ6_PG_MARK, PG6MD_011), + PINMUX_DATA(TIOC2A_MARK, PG6MD_100), + + PINMUX_DATA(PG5_DATA, PG5MD_000), + PINMUX_DATA(D21_MARK, PG5MD_001), + PINMUX_DATA(LCD_DATA5_MARK, PG5MD_010), + PINMUX_DATA(IRQ5_PG_MARK, PG5MD_011), + PINMUX_DATA(TIOC1B_MARK, PG5MD_100), + + PINMUX_DATA(PG4_DATA, PG4MD_000), + PINMUX_DATA(D20_MARK, PG4MD_001), + PINMUX_DATA(LCD_DATA4_MARK, PG4MD_010), + PINMUX_DATA(IRQ4_PG_MARK, PG4MD_011), + PINMUX_DATA(TIOC1A_MARK, PG4MD_100), + + PINMUX_DATA(PG3_DATA, PG3MD_000), + PINMUX_DATA(D19_MARK, PG3MD_001), + PINMUX_DATA(LCD_DATA3_MARK, PG3MD_010), + PINMUX_DATA(IRQ3_PG_MARK, PG3MD_011), + PINMUX_DATA(TIOC0D_MARK, PG3MD_100), + + PINMUX_DATA(PG2_DATA, PG2MD_000), + PINMUX_DATA(D18_MARK, PG2MD_001), + PINMUX_DATA(LCD_DATA2_MARK, PG2MD_010), + PINMUX_DATA(IRQ2_PG_MARK, PG2MD_011), + PINMUX_DATA(TIOC0C_MARK, PG2MD_100), + + PINMUX_DATA(PG1_DATA, PG1MD_000), + PINMUX_DATA(D17_MARK, PG1MD_001), + PINMUX_DATA(LCD_DATA1_MARK, PG1MD_010), + PINMUX_DATA(IRQ1_PG_MARK, PG1MD_011), + PINMUX_DATA(TIOC0B_MARK, PG1MD_100), + + PINMUX_DATA(PG0_DATA, PG0MD_000), + PINMUX_DATA(D16_MARK, PG0MD_001), + PINMUX_DATA(LCD_DATA0_MARK, PG0MD_010), + PINMUX_DATA(IRQ0_PG_MARK, PG0MD_011), + PINMUX_DATA(TIOC0A_MARK, PG0MD_100), + + /* Port H */ + PINMUX_DATA(PH7_DATA, PH7MD_00), + PINMUX_DATA(PHAN7_MARK, PH7MD_01), + PINMUX_DATA(PINT7_PH_MARK, PH7MD_10), + + PINMUX_DATA(PH6_DATA, PH6MD_00), + PINMUX_DATA(PHAN6_MARK, PH6MD_01), + PINMUX_DATA(PINT6_PH_MARK, PH6MD_10), + + PINMUX_DATA(PH5_DATA, PH5MD_00), + PINMUX_DATA(PHAN5_MARK, PH5MD_01), + PINMUX_DATA(PINT5_PH_MARK, PH5MD_10), + PINMUX_DATA(LCD_EXTCLK_MARK, PH5MD_11), + + PINMUX_DATA(PH4_DATA, PH4MD_00), + PINMUX_DATA(PHAN4_MARK, PH4MD_01), + PINMUX_DATA(PINT4_PH_MARK, PH4MD_10), + + PINMUX_DATA(PH3_DATA, PH3MD_00), + PINMUX_DATA(PHAN3_MARK, PH3MD_01), + PINMUX_DATA(PINT3_PH_MARK, PH3MD_10), + + PINMUX_DATA(PH2_DATA, PH2MD_00), + PINMUX_DATA(PHAN2_MARK, PH2MD_01), + PINMUX_DATA(PINT2_PH_MARK, PH2MD_10), + + PINMUX_DATA(PH1_DATA, PH1MD_00), + PINMUX_DATA(PHAN1_MARK, PH1MD_01), + PINMUX_DATA(PINT1_PH_MARK, PH1MD_10), + + PINMUX_DATA(PH0_DATA, PH0MD_00), + PINMUX_DATA(PHAN0_MARK, PH0MD_01), + PINMUX_DATA(PINT0_PH_MARK, PH0MD_10), + + /* Port I - not on device */ + + /* Port J */ + PINMUX_DATA(PJ31_DATA, PJ31MD_0), + PINMUX_DATA(DV_CLK_MARK, PJ31MD_1), + + PINMUX_DATA(PJ30_DATA, PJ30MD_000), + PINMUX_DATA(SSIDATA5_MARK, PJ30MD_010), + PINMUX_DATA(TIOC2B_MARK, PJ30MD_100), + PINMUX_DATA(IETXD_MARK, PJ30MD_101), + + PINMUX_DATA(PJ29_DATA, PJ29MD_000), + PINMUX_DATA(SSIWS5_MARK, PJ29MD_010), + PINMUX_DATA(TIOC2A_MARK, PJ29MD_100), + PINMUX_DATA(IERXD_MARK, PJ29MD_101), + + PINMUX_DATA(PJ28_DATA, PJ28MD_000), + PINMUX_DATA(SSISCK5_MARK, PJ28MD_010), + PINMUX_DATA(TIOC1B_MARK, PJ28MD_100), + PINMUX_DATA(RTS7_MARK, PJ28MD_101), + + PINMUX_DATA(PJ27_DATA, PJ27MD_000), + PINMUX_DATA(TIOC1A_MARK, PJ27MD_100), + PINMUX_DATA(CTS7_MARK, PJ27MD_101), + + PINMUX_DATA(PJ26_DATA, PJ26MD_000), + PINMUX_DATA(SSIDATA4_MARK, PJ26MD_010), + PINMUX_DATA(LCD_TCON5_MARK, PJ26MD_011), + PINMUX_DATA(TXD7_MARK, PJ26MD_101), + + PINMUX_DATA(PJ25_DATA, PJ25MD_000), + PINMUX_DATA(SSIWS4_MARK, PJ25MD_010), + PINMUX_DATA(LCD_TCON4_MARK, PJ25MD_011), + PINMUX_DATA(SPDIF_OUT_MARK, PJ25MD_100), + PINMUX_DATA(RXD7_MARK, PJ25MD_101), + + PINMUX_DATA(PJ24_DATA, PJ24MD_000), + PINMUX_DATA(SSISCK4_MARK, PJ24MD_010), + PINMUX_DATA(LCD_TCON3_MARK, PJ24MD_011), + PINMUX_DATA(SPDIF_IN_MARK, PJ24MD_100), + PINMUX_DATA(SCK7_MARK, PJ24MD_101), + + PINMUX_DATA(PJ23_DATA, PJ23MD_000), + PINMUX_DATA(DV_DATA23_MARK, PJ23MD_001), + PINMUX_DATA(LCD_DATA23_MARK, PJ23MD_010), + PINMUX_DATA(LCD_TCON6_MARK, PJ23MD_011), + PINMUX_DATA(IRQ3_PJ_MARK, PJ23MD_100), + PINMUX_DATA(CTX1_MARK, PJ23MD_101), + + PINMUX_DATA(PJ22_DATA, PJ22MD_000), + PINMUX_DATA(DV_DATA22_MARK, PJ22MD_001), + PINMUX_DATA(LCD_DATA22_MARK, PJ22MD_010), + PINMUX_DATA(LCD_TCON5_MARK, PJ22MD_011), + PINMUX_DATA(IRQ2_PJ_MARK, PJ22MD_100), + PINMUX_DATA(CRX1_MARK, PJ22MD_101), + PINMUX_DATA(CRX0CRX1_MARK, PJ22MD_110), + + PINMUX_DATA(PJ21_DATA, PJ21MD_000), + PINMUX_DATA(DV_DATA21_MARK, PJ21MD_001), + PINMUX_DATA(LCD_DATA21_MARK, PJ21MD_010), + PINMUX_DATA(LCD_TCON4_MARK, PJ21MD_011), + PINMUX_DATA(IRQ1_PJ_MARK, PJ21MD_100), + PINMUX_DATA(CTX2_MARK, PJ21MD_101), + + PINMUX_DATA(PJ20_DATA, PJ20MD_000), + PINMUX_DATA(DV_DATA20_MARK, PJ20MD_001), + PINMUX_DATA(LCD_DATA20_MARK, PJ20MD_010), + PINMUX_DATA(LCD_TCON3_MARK, PJ20MD_011), + PINMUX_DATA(IRQ0_PJ_MARK, PJ20MD_100), + PINMUX_DATA(CRX2_MARK, PJ20MD_101), + PINMUX_DATA(CRX0CRX1CRX2_PJ20_MARK, PJ20MD_110), + + PINMUX_DATA(PJ19_DATA, PJ19MD_000), + PINMUX_DATA(DV_DATA19_MARK, PJ19MD_001), + PINMUX_DATA(LCD_DATA19_MARK, PJ19MD_010), + PINMUX_DATA(MISO0_PJ19_MARK, PJ19MD_011), + PINMUX_DATA(TIOC0D_MARK, PJ19MD_100), + PINMUX_DATA(SIOFRXD_MARK, PJ19MD_101), + PINMUX_DATA(AUDIO_XOUT_MARK, PJ19MD_110), + + PINMUX_DATA(PJ18_DATA, PJ18MD_000), + PINMUX_DATA(DV_DATA18_MARK, PJ18MD_001), + PINMUX_DATA(LCD_DATA18_MARK, PJ18MD_010), + PINMUX_DATA(MOSI0_PJ18_MARK, PJ18MD_011), + PINMUX_DATA(TIOC0C_MARK, PJ18MD_100), + PINMUX_DATA(SIOFTXD_MARK, PJ18MD_101), + + PINMUX_DATA(PJ17_DATA, PJ17MD_000), + PINMUX_DATA(DV_DATA17_MARK, PJ17MD_001), + PINMUX_DATA(LCD_DATA17_MARK, PJ17MD_010), + PINMUX_DATA(SSL00_PJ17_MARK, PJ17MD_011), + PINMUX_DATA(TIOC0B_MARK, PJ17MD_100), + PINMUX_DATA(SIOFSYNC_MARK, PJ17MD_101), + + PINMUX_DATA(PJ16_DATA, PJ16MD_000), + PINMUX_DATA(DV_DATA16_MARK, PJ16MD_001), + PINMUX_DATA(LCD_DATA16_MARK, PJ16MD_010), + PINMUX_DATA(RSPCK0_PJ16_MARK, PJ16MD_011), + PINMUX_DATA(TIOC0A_MARK, PJ16MD_100), + PINMUX_DATA(SIOFSCK_MARK, PJ16MD_101), + + PINMUX_DATA(PJ15_DATA, PJ15MD_000), + PINMUX_DATA(DV_DATA15_MARK, PJ15MD_001), + PINMUX_DATA(LCD_DATA15_MARK, PJ15MD_010), + PINMUX_DATA(PINT7_PJ_MARK, PJ15MD_011), + PINMUX_DATA(PWM2H_MARK, PJ15MD_100), + PINMUX_DATA(TXD7_MARK, PJ15MD_101), + + PINMUX_DATA(PJ14_DATA, PJ14MD_000), + PINMUX_DATA(DV_DATA14_MARK, PJ14MD_001), + PINMUX_DATA(LCD_DATA14_MARK, PJ14MD_010), + PINMUX_DATA(PINT6_PJ_MARK, PJ14MD_011), + PINMUX_DATA(PWM2G_MARK, PJ14MD_100), + PINMUX_DATA(TXD6_MARK, PJ14MD_101), + + PINMUX_DATA(PJ13_DATA, PJ13MD_000), + PINMUX_DATA(DV_DATA13_MARK, PJ13MD_001), + PINMUX_DATA(LCD_DATA13_MARK, PJ13MD_010), + PINMUX_DATA(PINT5_PJ_MARK, PJ13MD_011), + PINMUX_DATA(PWM2F_MARK, PJ13MD_100), + PINMUX_DATA(TXD5_MARK, PJ13MD_101), + + PINMUX_DATA(PJ12_DATA, PJ12MD_000), + PINMUX_DATA(DV_DATA12_MARK, PJ12MD_001), + PINMUX_DATA(LCD_DATA12_MARK, PJ12MD_010), + PINMUX_DATA(PINT4_PJ_MARK, PJ12MD_011), + PINMUX_DATA(PWM2E_MARK, PJ12MD_100), + PINMUX_DATA(SCK7_MARK, PJ12MD_101), + + PINMUX_DATA(PJ11_DATA, PJ11MD_000), + PINMUX_DATA(DV_DATA11_MARK, PJ11MD_001), + PINMUX_DATA(LCD_DATA11_MARK, PJ11MD_010), + PINMUX_DATA(PINT3_PJ_MARK, PJ11MD_011), + PINMUX_DATA(PWM2D_MARK, PJ11MD_100), + PINMUX_DATA(SCK6_MARK, PJ11MD_101), + + PINMUX_DATA(PJ10_DATA, PJ10MD_000), + PINMUX_DATA(DV_DATA10_MARK, PJ10MD_001), + PINMUX_DATA(LCD_DATA10_MARK, PJ10MD_010), + PINMUX_DATA(PINT2_PJ_MARK, PJ10MD_011), + PINMUX_DATA(PWM2C_MARK, PJ10MD_100), + PINMUX_DATA(SCK5_MARK, PJ10MD_101), + + PINMUX_DATA(PJ9_DATA, PJ9MD_000), + PINMUX_DATA(DV_DATA9_MARK, PJ9MD_001), + PINMUX_DATA(LCD_DATA9_MARK, PJ9MD_010), + PINMUX_DATA(PINT1_PJ_MARK, PJ9MD_011), + PINMUX_DATA(PWM2B_MARK, PJ9MD_100), + PINMUX_DATA(RTS5_MARK, PJ9MD_101), + + PINMUX_DATA(PJ8_DATA, PJ8MD_000), + PINMUX_DATA(DV_DATA8_MARK, PJ8MD_001), + PINMUX_DATA(LCD_DATA8_MARK, PJ8MD_010), + PINMUX_DATA(PINT0_PJ_MARK, PJ8MD_011), + PINMUX_DATA(PWM2A_MARK, PJ8MD_100), + PINMUX_DATA(CTS5_MARK, PJ8MD_101), + + PINMUX_DATA(PJ7_DATA, PJ7MD_000), + PINMUX_DATA(DV_DATA7_MARK, PJ7MD_001), + PINMUX_DATA(LCD_DATA7_MARK, PJ7MD_010), + PINMUX_DATA(SD_D2_MARK, PJ7MD_011), + PINMUX_DATA(PWM1H_MARK, PJ7MD_100), + + PINMUX_DATA(PJ6_DATA, PJ6MD_000), + PINMUX_DATA(DV_DATA6_MARK, PJ6MD_001), + PINMUX_DATA(LCD_DATA6_MARK, PJ6MD_010), + PINMUX_DATA(SD_D3_MARK, PJ6MD_011), + PINMUX_DATA(PWM1G_MARK, PJ6MD_100), + + PINMUX_DATA(PJ5_DATA, PJ5MD_000), + PINMUX_DATA(DV_DATA5_MARK, PJ5MD_001), + PINMUX_DATA(LCD_DATA5_MARK, PJ5MD_010), + PINMUX_DATA(SD_CMD_MARK, PJ5MD_011), + PINMUX_DATA(PWM1F_MARK, PJ5MD_100), + + PINMUX_DATA(PJ4_DATA, PJ4MD_000), + PINMUX_DATA(DV_DATA4_MARK, PJ4MD_001), + PINMUX_DATA(LCD_DATA4_MARK, PJ4MD_010), + PINMUX_DATA(SD_CLK_MARK, PJ4MD_011), + PINMUX_DATA(PWM1E_MARK, PJ4MD_100), + + PINMUX_DATA(PJ3_DATA, PJ3MD_000), + PINMUX_DATA(DV_DATA3_MARK, PJ3MD_001), + PINMUX_DATA(LCD_DATA3_MARK, PJ3MD_010), + PINMUX_DATA(SD_D0_MARK, PJ3MD_011), + PINMUX_DATA(PWM1D_MARK, PJ3MD_100), + + PINMUX_DATA(PJ2_DATA, PJ2MD_000), + PINMUX_DATA(DV_DATA2_MARK, PJ2MD_001), + PINMUX_DATA(LCD_DATA2_MARK, PJ2MD_010), + PINMUX_DATA(SD_D1_MARK, PJ2MD_011), + PINMUX_DATA(PWM1C_MARK, PJ2MD_100), + + PINMUX_DATA(PJ1_DATA, PJ1MD_000), + PINMUX_DATA(DV_DATA1_MARK, PJ1MD_001), + PINMUX_DATA(LCD_DATA1_MARK, PJ1MD_010), + PINMUX_DATA(SD_WP_MARK, PJ1MD_011), + PINMUX_DATA(PWM1B_MARK, PJ1MD_100), + + PINMUX_DATA(PJ0_DATA, PJ0MD_000), + PINMUX_DATA(DV_DATA0_MARK, PJ0MD_001), + PINMUX_DATA(LCD_DATA0_MARK, PJ0MD_010), + PINMUX_DATA(SD_CD_MARK, PJ0MD_011), + PINMUX_DATA(PWM1A_MARK, PJ0MD_100), +}; + +static struct pinmux_gpio pinmux_gpios[] = { + /* Port A */ + PINMUX_GPIO(GPIO_PA1, PA1_DATA), + PINMUX_GPIO(GPIO_PA0, PA0_DATA), + + /* Port B */ + PINMUX_GPIO(GPIO_PB22, PB22_DATA), + PINMUX_GPIO(GPIO_PB21, PB21_DATA), + PINMUX_GPIO(GPIO_PB20, PB20_DATA), + PINMUX_GPIO(GPIO_PB19, PB19_DATA), + PINMUX_GPIO(GPIO_PB18, PB18_DATA), + PINMUX_GPIO(GPIO_PB17, PB17_DATA), + PINMUX_GPIO(GPIO_PB16, PB16_DATA), + PINMUX_GPIO(GPIO_PB15, PB15_DATA), + PINMUX_GPIO(GPIO_PB14, PB14_DATA), + PINMUX_GPIO(GPIO_PB13, PB13_DATA), + PINMUX_GPIO(GPIO_PB12, PB12_DATA), + PINMUX_GPIO(GPIO_PB11, PB11_DATA), + PINMUX_GPIO(GPIO_PB10, PB10_DATA), + PINMUX_GPIO(GPIO_PB9, PB9_DATA), + PINMUX_GPIO(GPIO_PB8, PB8_DATA), + PINMUX_GPIO(GPIO_PB7, PB7_DATA), + PINMUX_GPIO(GPIO_PB6, PB6_DATA), + PINMUX_GPIO(GPIO_PB5, PB5_DATA), + PINMUX_GPIO(GPIO_PB4, PB4_DATA), + PINMUX_GPIO(GPIO_PB3, PB3_DATA), + PINMUX_GPIO(GPIO_PB2, PB2_DATA), + PINMUX_GPIO(GPIO_PB1, PB1_DATA), + + /* Port C */ + PINMUX_GPIO(GPIO_PC8, PC8_DATA), + PINMUX_GPIO(GPIO_PC7, PC7_DATA), + PINMUX_GPIO(GPIO_PC6, PC6_DATA), + PINMUX_GPIO(GPIO_PC5, PC5_DATA), + PINMUX_GPIO(GPIO_PC4, PC4_DATA), + PINMUX_GPIO(GPIO_PC3, PC3_DATA), + PINMUX_GPIO(GPIO_PC2, PC2_DATA), + PINMUX_GPIO(GPIO_PC1, PC1_DATA), + PINMUX_GPIO(GPIO_PC0, PC0_DATA), + + /* Port D */ + PINMUX_GPIO(GPIO_PD15, PD15_DATA), + PINMUX_GPIO(GPIO_PD14, PD14_DATA), + PINMUX_GPIO(GPIO_PD13, PD13_DATA), + PINMUX_GPIO(GPIO_PD12, PD12_DATA), + PINMUX_GPIO(GPIO_PD11, PD11_DATA), + PINMUX_GPIO(GPIO_PD10, PD10_DATA), + PINMUX_GPIO(GPIO_PD9, PD9_DATA), + PINMUX_GPIO(GPIO_PD8, PD8_DATA), + PINMUX_GPIO(GPIO_PD7, PD7_DATA), + PINMUX_GPIO(GPIO_PD6, PD6_DATA), + PINMUX_GPIO(GPIO_PD5, PD5_DATA), + PINMUX_GPIO(GPIO_PD4, PD4_DATA), + PINMUX_GPIO(GPIO_PD3, PD3_DATA), + PINMUX_GPIO(GPIO_PD2, PD2_DATA), + PINMUX_GPIO(GPIO_PD1, PD1_DATA), + PINMUX_GPIO(GPIO_PD0, PD0_DATA), + + /* Port E */ + PINMUX_GPIO(GPIO_PE7, PE7_DATA), + PINMUX_GPIO(GPIO_PE6, PE6_DATA), + PINMUX_GPIO(GPIO_PE5, PE5_DATA), + PINMUX_GPIO(GPIO_PE4, PE4_DATA), + PINMUX_GPIO(GPIO_PE3, PE3_DATA), + PINMUX_GPIO(GPIO_PE2, PE2_DATA), + PINMUX_GPIO(GPIO_PE1, PE1_DATA), + PINMUX_GPIO(GPIO_PE0, PE0_DATA), + + /* Port F */ + PINMUX_GPIO(GPIO_PF23, PF23_DATA), + PINMUX_GPIO(GPIO_PF22, PF22_DATA), + PINMUX_GPIO(GPIO_PF21, PF21_DATA), + PINMUX_GPIO(GPIO_PF20, PF20_DATA), + PINMUX_GPIO(GPIO_PF19, PF19_DATA), + PINMUX_GPIO(GPIO_PF18, PF18_DATA), + PINMUX_GPIO(GPIO_PF17, PF17_DATA), + PINMUX_GPIO(GPIO_PF16, PF16_DATA), + PINMUX_GPIO(GPIO_PF15, PF15_DATA), + PINMUX_GPIO(GPIO_PF14, PF14_DATA), + PINMUX_GPIO(GPIO_PF13, PF13_DATA), + PINMUX_GPIO(GPIO_PF12, PF12_DATA), + PINMUX_GPIO(GPIO_PF11, PF11_DATA), + PINMUX_GPIO(GPIO_PF10, PF10_DATA), + PINMUX_GPIO(GPIO_PF9, PF9_DATA), + PINMUX_GPIO(GPIO_PF8, PF8_DATA), + PINMUX_GPIO(GPIO_PF7, PF7_DATA), + PINMUX_GPIO(GPIO_PF6, PF6_DATA), + PINMUX_GPIO(GPIO_PF5, PF5_DATA), + PINMUX_GPIO(GPIO_PF4, PF4_DATA), + PINMUX_GPIO(GPIO_PF3, PF3_DATA), + PINMUX_GPIO(GPIO_PF2, PF2_DATA), + PINMUX_GPIO(GPIO_PF1, PF1_DATA), + PINMUX_GPIO(GPIO_PF0, PF0_DATA), + + /* Port G */ + PINMUX_GPIO(GPIO_PG27, PG27_DATA), + PINMUX_GPIO(GPIO_PG26, PG26_DATA), + PINMUX_GPIO(GPIO_PG25, PG25_DATA), + PINMUX_GPIO(GPIO_PG24, PG24_DATA), + PINMUX_GPIO(GPIO_PG23, PG23_DATA), + PINMUX_GPIO(GPIO_PG22, PG22_DATA), + PINMUX_GPIO(GPIO_PG21, PG21_DATA), + PINMUX_GPIO(GPIO_PG20, PG20_DATA), + PINMUX_GPIO(GPIO_PG19, PG19_DATA), + PINMUX_GPIO(GPIO_PG18, PG18_DATA), + PINMUX_GPIO(GPIO_PG17, PG17_DATA), + PINMUX_GPIO(GPIO_PG16, PG16_DATA), + PINMUX_GPIO(GPIO_PG15, PG15_DATA), + PINMUX_GPIO(GPIO_PG14, PG14_DATA), + PINMUX_GPIO(GPIO_PG13, PG13_DATA), + PINMUX_GPIO(GPIO_PG12, PG12_DATA), + PINMUX_GPIO(GPIO_PG11, PG11_DATA), + PINMUX_GPIO(GPIO_PG10, PG10_DATA), + PINMUX_GPIO(GPIO_PG9, PG9_DATA), + PINMUX_GPIO(GPIO_PG8, PG8_DATA), + PINMUX_GPIO(GPIO_PG7, PG7_DATA), + PINMUX_GPIO(GPIO_PG6, PG6_DATA), + PINMUX_GPIO(GPIO_PG5, PG5_DATA), + PINMUX_GPIO(GPIO_PG4, PG4_DATA), + PINMUX_GPIO(GPIO_PG3, PG3_DATA), + PINMUX_GPIO(GPIO_PG2, PG2_DATA), + PINMUX_GPIO(GPIO_PG1, PG1_DATA), + PINMUX_GPIO(GPIO_PG0, PG0_DATA), + + /* Port H - Port H does not have a Data Register */ + + /* Port I - not on device */ + + /* Port J */ + PINMUX_GPIO(GPIO_PJ31, PJ31_DATA), + PINMUX_GPIO(GPIO_PJ30, PJ30_DATA), + PINMUX_GPIO(GPIO_PJ29, PJ29_DATA), + PINMUX_GPIO(GPIO_PJ28, PJ28_DATA), + PINMUX_GPIO(GPIO_PJ27, PJ27_DATA), + PINMUX_GPIO(GPIO_PJ26, PJ26_DATA), + PINMUX_GPIO(GPIO_PJ25, PJ25_DATA), + PINMUX_GPIO(GPIO_PJ24, PJ24_DATA), + PINMUX_GPIO(GPIO_PJ23, PJ23_DATA), + PINMUX_GPIO(GPIO_PJ22, PJ22_DATA), + PINMUX_GPIO(GPIO_PJ21, PJ21_DATA), + PINMUX_GPIO(GPIO_PJ20, PJ20_DATA), + PINMUX_GPIO(GPIO_PJ19, PJ19_DATA), + PINMUX_GPIO(GPIO_PJ18, PJ18_DATA), + PINMUX_GPIO(GPIO_PJ17, PJ17_DATA), + PINMUX_GPIO(GPIO_PJ16, PJ16_DATA), + PINMUX_GPIO(GPIO_PJ15, PJ15_DATA), + PINMUX_GPIO(GPIO_PJ14, PJ14_DATA), + PINMUX_GPIO(GPIO_PJ13, PJ13_DATA), + PINMUX_GPIO(GPIO_PJ12, PJ12_DATA), + PINMUX_GPIO(GPIO_PJ11, PJ11_DATA), + PINMUX_GPIO(GPIO_PJ10, PJ10_DATA), + PINMUX_GPIO(GPIO_PJ9, PJ9_DATA), + PINMUX_GPIO(GPIO_PJ8, PJ8_DATA), + PINMUX_GPIO(GPIO_PJ7, PJ7_DATA), + PINMUX_GPIO(GPIO_PJ6, PJ6_DATA), + PINMUX_GPIO(GPIO_PJ5, PJ5_DATA), + PINMUX_GPIO(GPIO_PJ4, PJ4_DATA), + PINMUX_GPIO(GPIO_PJ3, PJ3_DATA), + PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), + PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), + PINMUX_GPIO(GPIO_PJ0, PJ0_DATA), + + /* INTC */ + PINMUX_GPIO(GPIO_FN_IRQ7_PG, IRQ7_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6_PG, IRQ6_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5_PG, IRQ5_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4_PG, IRQ4_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_PG, IRQ1_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_PG, IRQ0_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ7_PF, IRQ7_PF_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6_PF, IRQ6_PF_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5_PF, IRQ5_PF_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4_PF, IRQ4_PF_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3_PJ, IRQ3_PJ_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2_PJ, IRQ2_PJ_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_PC, IRQ1_PC_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_PC, IRQ0_PC_MARK), + + PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT0_PG, PINT0_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT7_PH, PINT7_PH_MARK), + PINMUX_GPIO(GPIO_FN_PINT6_PH, PINT6_PH_MARK), + PINMUX_GPIO(GPIO_FN_PINT5_PH, PINT5_PH_MARK), + PINMUX_GPIO(GPIO_FN_PINT4_PH, PINT4_PH_MARK), + PINMUX_GPIO(GPIO_FN_PINT3_PH, PINT3_PH_MARK), + PINMUX_GPIO(GPIO_FN_PINT2_PH, PINT2_PH_MARK), + PINMUX_GPIO(GPIO_FN_PINT1_PH, PINT1_PH_MARK), + PINMUX_GPIO(GPIO_FN_PINT0_PH, PINT0_PH_MARK), + PINMUX_GPIO(GPIO_FN_PINT7_PJ, PINT7_PJ_MARK), + PINMUX_GPIO(GPIO_FN_PINT6_PJ, PINT6_PJ_MARK), + PINMUX_GPIO(GPIO_FN_PINT5_PJ, PINT5_PJ_MARK), + PINMUX_GPIO(GPIO_FN_PINT4_PJ, PINT4_PJ_MARK), + PINMUX_GPIO(GPIO_FN_PINT3_PJ, PINT3_PJ_MARK), + PINMUX_GPIO(GPIO_FN_PINT2_PJ, PINT2_PJ_MARK), + PINMUX_GPIO(GPIO_FN_PINT1_PJ, PINT1_PJ_MARK), + PINMUX_GPIO(GPIO_FN_PINT0_PJ, PINT0_PJ_MARK), + + /* WDT */ + PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), + + /* CAN */ + PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), + PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), + PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), + PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), + PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0CRX1_MARK), + PINMUX_GPIO(GPIO_FN_CRX0_CRX1_CRX2, CRX0CRX1CRX2_MARK), + + /* DMAC */ + PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), + PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), + PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + + /* ADC */ + PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), + + /* BSCh */ + PINMUX_GPIO(GPIO_FN_A25, A25_MARK), + PINMUX_GPIO(GPIO_FN_A24, A24_MARK), + PINMUX_GPIO(GPIO_FN_A23, A23_MARK), + PINMUX_GPIO(GPIO_FN_A22, A22_MARK), + PINMUX_GPIO(GPIO_FN_A21, A21_MARK), + PINMUX_GPIO(GPIO_FN_A20, A20_MARK), + PINMUX_GPIO(GPIO_FN_A19, A19_MARK), + PINMUX_GPIO(GPIO_FN_A18, A18_MARK), + PINMUX_GPIO(GPIO_FN_A17, A17_MARK), + PINMUX_GPIO(GPIO_FN_A16, A16_MARK), + PINMUX_GPIO(GPIO_FN_A15, A15_MARK), + PINMUX_GPIO(GPIO_FN_A14, A14_MARK), + PINMUX_GPIO(GPIO_FN_A13, A13_MARK), + PINMUX_GPIO(GPIO_FN_A12, A12_MARK), + PINMUX_GPIO(GPIO_FN_A11, A11_MARK), + PINMUX_GPIO(GPIO_FN_A10, A10_MARK), + PINMUX_GPIO(GPIO_FN_A9, A9_MARK), + PINMUX_GPIO(GPIO_FN_A8, A8_MARK), + PINMUX_GPIO(GPIO_FN_A7, A7_MARK), + PINMUX_GPIO(GPIO_FN_A6, A6_MARK), + PINMUX_GPIO(GPIO_FN_A5, A5_MARK), + PINMUX_GPIO(GPIO_FN_A4, A4_MARK), + PINMUX_GPIO(GPIO_FN_A3, A3_MARK), + PINMUX_GPIO(GPIO_FN_A2, A2_MARK), + PINMUX_GPIO(GPIO_FN_A1, A1_MARK), + PINMUX_GPIO(GPIO_FN_A0, A0_MARK), + + PINMUX_GPIO(GPIO_FN_D15, D15_MARK), + PINMUX_GPIO(GPIO_FN_D14, D14_MARK), + PINMUX_GPIO(GPIO_FN_D13, D13_MARK), + PINMUX_GPIO(GPIO_FN_D12, D12_MARK), + PINMUX_GPIO(GPIO_FN_D11, D11_MARK), + PINMUX_GPIO(GPIO_FN_D10, D10_MARK), + PINMUX_GPIO(GPIO_FN_D9, D9_MARK), + PINMUX_GPIO(GPIO_FN_D8, D8_MARK), + PINMUX_GPIO(GPIO_FN_D7, D7_MARK), + PINMUX_GPIO(GPIO_FN_D6, D6_MARK), + PINMUX_GPIO(GPIO_FN_D5, D5_MARK), + PINMUX_GPIO(GPIO_FN_D4, D4_MARK), + PINMUX_GPIO(GPIO_FN_D3, D3_MARK), + PINMUX_GPIO(GPIO_FN_D2, D2_MARK), + PINMUX_GPIO(GPIO_FN_D1, D1_MARK), + PINMUX_GPIO(GPIO_FN_D0, D0_MARK), + + PINMUX_GPIO(GPIO_FN_BS, BS_MARK), + PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), + PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), + PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), + PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), + PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), + PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK), + PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), + PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), + PINMUX_GPIO(GPIO_FN_RD, RD_MARK), + PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), + PINMUX_GPIO(GPIO_FN_WE3ICIOWRAHDQMUU, WE3ICIOWRAHDQMUU_MARK), + PINMUX_GPIO(GPIO_FN_WE2ICIORDDQMUL, WE2ICIORDDQMUL_MARK), + PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK), + PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK), + PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), + PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), + PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), + PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), + PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), + PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + + /* TMU */ + PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), + PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK), + PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK), + PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK), + PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK), + + /* SCIF */ + PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), + PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), + PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), + PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), + PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), + PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), + PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK), + PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK), + PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), + PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), + PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), + PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), + PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), + PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), + PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK), + PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), + PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), + PINMUX_GPIO(GPIO_FN_SCK5, SCK5_MARK), + PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK), + PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK), + PINMUX_GPIO(GPIO_FN_RTS5, RTS5_MARK), + PINMUX_GPIO(GPIO_FN_CTS5, CTS5_MARK), + PINMUX_GPIO(GPIO_FN_SCK6, SCK6_MARK), + PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK), + PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK), + PINMUX_GPIO(GPIO_FN_SCK7, SCK7_MARK), + PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK), + PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK), + PINMUX_GPIO(GPIO_FN_RTS7, RTS7_MARK), + PINMUX_GPIO(GPIO_FN_CTS7, CTS7_MARK), + + /* RSPI */ + PINMUX_GPIO(GPIO_FN_RSPCK0_PJ16, RSPCK0_PJ16_MARK), + PINMUX_GPIO(GPIO_FN_SSL00_PJ17, SSL00_PJ17_MARK), + PINMUX_GPIO(GPIO_FN_MOSI0_PJ18, MOSI0_PJ18_MARK), + PINMUX_GPIO(GPIO_FN_MISO0_PJ19, MISO0_PJ19_MARK), + PINMUX_GPIO(GPIO_FN_RSPCK0_PB17, RSPCK0_PB17_MARK), + PINMUX_GPIO(GPIO_FN_SSL00_PB18, SSL00_PB18_MARK), + PINMUX_GPIO(GPIO_FN_MOSI0_PB19, MOSI0_PB19_MARK), + PINMUX_GPIO(GPIO_FN_MISO0_PB20, MISO0_PB20_MARK), + PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK), + PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK), + PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK), + PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK), + + /* IIC3 */ + PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), + PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), + PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), + PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), + PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), + PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), + + /* SSI */ + PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), + PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK), + PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), + PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), + PINMUX_GPIO(GPIO_FN_AUDIO_XOUT, AUDIO_XOUT_MARK), + + /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */ + PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK), + PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK), + + /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */ + PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK), + PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK), + + /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ + PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), + PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), + + /* VDC3 */ + PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), + PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), + PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), + + PINMUX_GPIO(GPIO_FN_DV_DATA23, DV_DATA23_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA22, DV_DATA22_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA21, DV_DATA21_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA20, DV_DATA20_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA19, DV_DATA19_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA18, DV_DATA18_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA17, DV_DATA17_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA16, DV_DATA16_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA15, DV_DATA15_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA14, DV_DATA14_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA13, DV_DATA13_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA12, DV_DATA12_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA11, DV_DATA11_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA10, DV_DATA10_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA9, DV_DATA9_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA8, DV_DATA8_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK), + + PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), + PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK), + PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK), + PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK), + + PINMUX_GPIO(GPIO_FN_LCD_DATA23, LCD_DATA23_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA22, LCD_DATA22_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA21, LCD_DATA21_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA20, LCD_DATA20_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA19, LCD_DATA19_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA18, LCD_DATA18_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA17, LCD_DATA17_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA16, LCD_DATA16_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), + + PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + /* "name" addr register_size Field_Width */ + /* where Field_Width is 1 for single mode registers or 4 for upto 16 + /* mode registers and modes are described in assending order [0..16] */ + + { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, PA1_IN, PA1_OUT, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, PA0_IN, PA0_OUT } + }, + { PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PB22MD_000, PB22MD_001, PB22MD_010, PB22MD_011, + PB22MD_100, PB22MD_101, PB22MD_110, PB22MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PB21MD_00, PB21MD_01, PB21MD_10, PB21MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PB20MD_000, PB20MD_001, PB20MD_010, PB20MD_011, + PB20MD_100, PB20MD_101, PB20MD_110, PB20MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4) { + PB19MD_000, PB19MD_001, PB19MD_010, PB19MD_011, + PB19MD_100, PB19MD_101, PB19MD_110, PB19MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PB18MD_000, PB18MD_001, PB18MD_010, PB18MD_011, + PB18MD_100, PB18MD_101, PB18MD_110, PB18MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PB17MD_000, PB17MD_001, PB17MD_010, PB17MD_011, + PB17MD_100, PB17MD_101, PB17MD_110, PB17MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PB16MD_000, PB16MD_001, PB16MD_010, PB16MD_011, + PB16MD_100, PB16MD_101, PB16MD_110, PB16MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4) { + PB15MD_000, PB15MD_001, PB15MD_010, PB15MD_011, + PB15MD_100, PB15MD_101, PB15MD_110, PB15MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PB14MD_000, PB14MD_001, PB14MD_010, PB14MD_011, + PB14MD_100, PB14MD_101, PB14MD_110, PB14MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PB13MD_000, PB13MD_001, PB13MD_010, PB13MD_011, + PB13MD_100, PB13MD_101, PB13MD_110, PB13MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4) { + PB11MD_00, PB11MD_01, PB11MD_10, PB11MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PB10MD_00, PB10MD_01, PB10MD_10, PB10MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PB9MD_00, PB9MD_01, PB9MD_10, PB9MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PB8MD_00, PB8MD_01, PB8MD_10, PB8MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4) { + PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4) { + PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PB2MD_00, PB2MD_01, PB2MD_10, PB2MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, + PB22_IN, PB22_OUT, + PB21_IN, PB21_OUT, + PB20_IN, PB20_OUT, + PB19_IN, PB19_OUT, + PB18_IN, PB18_OUT, + PB17_IN, PB17_OUT, + PB16_IN, PB16_OUT } + }, + { PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1) { + PB15_IN, PB15_OUT, + PB14_IN, PB14_OUT, + PB13_IN, PB13_OUT, + PB12_IN, PB12_OUT, + PB11_IN, PB11_OUT, + PB10_IN, PB10_OUT, + PB9_IN, PB9_OUT, + PB8_IN, PB8_OUT, + PB7_IN, PB7_OUT, + PB6_IN, PB6_OUT, + PB5_IN, PB5_OUT, + PB4_IN, PB4_OUT, + PB3_IN, PB3_OUT, + PB2_IN, PB2_OUT, + PB1_IN, PB1_OUT, + 0, 0 } + }, + + { PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PC8MD_000, PC8MD_001, PC8MD_010, PC8MD_011, + PC8MD_100, PC8MD_101, PC8MD_110, PC8MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PCCR1", 0xfffe384c, 16, 4) { + PC7MD_000, PC7MD_001, PC7MD_010, PC7MD_011, + PC7MD_100, PC7MD_101, PC7MD_110, PC7MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PC6MD_000, PC6MD_001, PC6MD_010, PC6MD_011, + PC6MD_100, PC6MD_101, PC6MD_110, PC6MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PC5MD_000, PC5MD_001, PC5MD_010, PC5MD_011, + PC5MD_100, PC5MD_101, PC5MD_110, PC5MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PC4MD_00, PC4MD_01, PC4MD_10, PC4MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PCCR0", 0xfffe384e, 16, 4) { + PC3MD_00, PC3MD_01, PC3MD_10, PC3MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PC2MD_00, PC2MD_01, PC2MD_10, PC2MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PC1MD_0, PC1MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PC0MD_0, PC0MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + PC8_IN, PC8_OUT, + PC7_IN, PC7_OUT, + PC6_IN, PC6_OUT, + PC5_IN, PC5_OUT, + PC4_IN, PC4_OUT, + PC3_IN, PC3_OUT, + PC2_IN, PC2_OUT, + PC1_IN, PC1_OUT, + PC0_IN, PC0_OUT } + }, + + { PINMUX_CFG_REG("PDCR3", 0xfffe3868, 16, 4) { + PD15MD_00, PD15MD_01, PD15MD_10, PD15MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD14MD_00, PD14MD_01, PD14MD_10, PD14MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD13MD_00, PD13MD_01, PD13MD_10, PD13MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD12MD_00, PD12MD_01, PD12MD_10, PD12MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PDCR2", 0xfffe386a, 16, 4) { + PD11MD_00, PD11MD_01, PD11MD_10, PD11MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD10MD_00, PD10MD_01, PD10MD_10, PD10MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD9MD_00, PD9MD_01, PD9MD_10, PD9MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD8MD_00, PD8MD_01, PD8MD_10, PD8MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PDCR1", 0xfffe386c, 16, 4) { + PD7MD_00, PD7MD_01, PD7MD_10, PD7MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD6MD_00, PD6MD_01, PD6MD_10, PD6MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD5MD_00, PD5MD_01, PD5MD_10, PD5MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD4MD_00, PD4MD_01, PD4MD_10, PD4MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PDCR0", 0xfffe386e, 16, 4) { + PD3MD_00, PD3MD_01, PD3MD_10, PD3MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD2MD_00, PD2MD_01, PD2MD_10, PD2MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD1MD_00, PD1MD_01, PD1MD_10, PD1MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD0MD_00, PD0MD_01, PD0MD_10, PD0MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PDIOR0", 0xfffe3872, 16, 1) { + PD15_IN, PD15_OUT, + PD14_IN, PD14_OUT, + PD13_IN, PD13_OUT, + PD12_IN, PD12_OUT, + PD11_IN, PD11_OUT, + PD10_IN, PD10_OUT, + PD9_IN, PD9_OUT, + PD8_IN, PD8_OUT, + PD7_IN, PD7_OUT, + PD6_IN, PD6_OUT, + PD5_IN, PD5_OUT, + PD4_IN, PD4_OUT, + PD3_IN, PD3_OUT, + PD2_IN, PD2_OUT, + PD1_IN, PD1_OUT, + PD0_IN, PD0_OUT } + }, + + { PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4) { + PE7MD_00, PE7MD_01, PE7MD_10, PE7MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PE6MD_00, PE6MD_01, PE6MD_10, PE6MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PE5MD_00, PE5MD_01, PE5MD_10, PE5MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PE4MD_00, PE4MD_01, PE4MD_10, PE4MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PECR0", 0xfffe388e, 16, 4) { + PE3MD_000, PE3MD_001, PE3MD_010, PE3MD_011, + PE3MD_100, PE3MD_101, PE3MD_110, PE3MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PE2MD_000, PE2MD_001, PE2MD_010, PE2MD_011, + PE2MD_100, PE2MD_101, PE2MD_110, PE2MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011, + PE1MD_100, PE1MD_101, PE1MD_110, PE1MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PE7_IN, PE7_OUT, + PE6_IN, PE6_OUT, + PE5_IN, PE5_OUT, + PE4_IN, PE4_OUT, + PE3_IN, PE3_OUT, + PE2_IN, PE2_OUT, + PE1_IN, PE1_OUT, + PE0_IN, PE0_OUT } + }, + + { PINMUX_CFG_REG("PFCR6", 0xfffe38a2, 16, 4) { + PF23MD_000, PF23MD_001, PF23MD_010, PF23MD_011, + PF23MD_100, PF23MD_101, PF23MD_110, PF23MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PF22MD_000, PF22MD_001, PF22MD_010, PF22MD_011, + PF22MD_100, PF22MD_101, PF22MD_110, PF22MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PF21MD_000, PF21MD_001, PF21MD_010, PF21MD_011, + PF21MD_100, PF21MD_101, PF21MD_110, PF21MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PF20MD_000, PF20MD_001, PF20MD_010, PF20MD_011, + PF20MD_100, PF20MD_101, PF20MD_110, PF20MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PFCR5", 0xfffe38a4, 16, 4) { + PF19MD_000, PF19MD_001, PF19MD_010, PF19MD_011, + PF19MD_100, PF19MD_101, PF19MD_110, PF19MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PF18MD_000, PF18MD_001, PF18MD_010, PF18MD_011, + PF18MD_100, PF18MD_101, PF18MD_110, PF18MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PF17MD_000, PF17MD_001, PF17MD_010, PF17MD_011, + PF17MD_100, PF17MD_101, PF17MD_110, PF17MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PF16MD_000, PF16MD_001, PF16MD_010, PF16MD_011, + PF16MD_100, PF16MD_101, PF16MD_110, PF16MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PFCR4", 0xfffe38a6, 16, 4) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF15MD_000, PF15MD_001, PF15MD_010, PF15MD_011, + PF15MD_100, PF15MD_101, PF15MD_110, PF15MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF14MD_000, PF14MD_001, PF14MD_010, PF14MD_011, + PF14MD_100, PF14MD_101, PF14MD_110, PF14MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PF13MD_000, PF13MD_001, PF13MD_010, PF13MD_011, + PF13MD_100, PF13MD_101, PF13MD_110, PF13MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PF12MD_000, PF12MD_001, PF12MD_010, PF12MD_011, + PF12MD_100, PF12MD_101, PF12MD_110, PF12MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PFCR2", 0xfffe38aa, 16, 4) { + PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011, + PF11MD_100, PF11MD_101, PF11MD_110, PF11MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011, + PF10MD_100, PF10MD_101, PF10MD_110, PF10MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011, + PF9MD_100, PF9MD_101, PF9MD_110, PF9MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PF8MD_000, PF8MD_001, PF8MD_010, PF8MD_011, + PF8MD_100, PF8MD_101, PF8MD_110, PF8MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PFCR1", 0xfffe38ac, 16, 4) { + PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011, + PF7MD_100, PF7MD_101, PF7MD_110, PF7MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011, + PF6MD_100, PF6MD_101, PF6MD_110, PF6MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011, + PF5MD_100, PF5MD_101, PF5MD_110, PF5MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011, + PF4MD_100, PF4MD_101, PF4MD_110, PF4MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PFCR0", 0xfffe38ae, 16, 4) { + PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011, + PF3MD_100, PF3MD_101, PF3MD_110, PF3MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011, + PF2MD_100, PF2MD_101, PF2MD_110, PF2MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011, + PF1MD_100, PF1MD_101, PF1MD_110, PF1MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011, + PF0MD_100, PF0MD_101, PF0MD_110, PF0MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PFIOR1", 0xfffe38b0, 16, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + PF23_IN, PF23_OUT, + PF22_IN, PF22_OUT, + PF21_IN, PF21_OUT, + PF20_IN, PF20_OUT, + PF19_IN, PF19_OUT, + PF18_IN, PF18_OUT, + PF17_IN, PF17_OUT, + PF16_IN, PF16_OUT } + }, + { PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1) { + PF15_IN, PF15_OUT, + PF14_IN, PF14_OUT, + PF13_IN, PF13_OUT, + PF12_IN, PF12_OUT, + PF11_IN, PF11_OUT, + PF10_IN, PF10_OUT, + PF9_IN, PF9_OUT, + PF8_IN, PF8_OUT, + PF7_IN, PF7_OUT, + PF6_IN, PF6_OUT, + PF5_IN, PF5_OUT, + PF4_IN, PF4_OUT, + PF3_IN, PF3_OUT, + PF2_IN, PF2_OUT, + PF1_IN, PF1_OUT, + PF0_IN, PF0_OUT } + }, + + { PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4) { + PG27MD_00, PG27MD_01, PG27MD_10, PG27MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG26MD_00, PG26MD_01, PG26MD_10, PG26MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG25MD_00, PG25MD_01, PG25MD_10, PG25MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PGCR5", 0xfffe38c4, 16, 4) { + PG23MD_000, PG23MD_001, PG23MD_010, PG23MD_011, + PG23MD_100, PG23MD_101, PG23MD_110, PG23MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG22MD_000, PG22MD_001, PG22MD_010, PG22MD_011, + PG22MD_100, PG22MD_101, PG22MD_110, PG22MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG21MD_000, PG21MD_001, PG21MD_010, PG21MD_011, + PG21MD_100, PG21MD_101, PG21MD_110, PG21MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011, + PG20MD_100, PG20MD_101, PG20MD_110, PG20MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PGCR4", 0xfffe38c6, 16, 4) { + PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011, + PG19MD_100, PG19MD_101, PG19MD_110, PG19MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011, + PG18MD_100, PG18MD_101, PG18MD_110, PG18MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG17MD_00, PG17MD_01, PG17MD_10, PG17MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG16MD_00, PG16MD_01, PG16MD_10, PG16MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PGCR3", 0xfffe38c8, 16, 4) { + PG15MD_00, PG15MD_01, PG15MD_10, PG15MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG14MD_00, PG14MD_01, PG14MD_10, PG14MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG13MD_00, PG13MD_01, PG13MD_10, PG13MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG12MD_00, PG12MD_01, PG12MD_10, PG12MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PGCR2", 0xfffe38ca, 16, 4) { + PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011, + PG11MD_100, PG11MD_101, PG11MD_110, PG11MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011, + PG10MD_100, PG10MD_101, PG10MD_110, PG10MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011, + PG9MD_100, PG9MD_101, PG9MD_110, PG9MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011, + PG8MD_100, PG8MD_101, PG8MD_110, PG8MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PGCR1", 0xfffe38cc, 16, 4) { + PG7MD_000, PG7MD_001, PG7MD_010, PG7MD_011, + PG7MD_100, PG7MD_101, PG7MD_110, PG7MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG6MD_000, PG6MD_001, PG6MD_010, PG6MD_011, + PG6MD_100, PG6MD_101, PG6MD_110, PG6MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG5MD_000, PG5MD_001, PG5MD_010, PG5MD_011, + PG5MD_100, PG5MD_101, PG5MD_110, PG5MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG4MD_000, PG4MD_001, PG4MD_010, PG4MD_011, + PG4MD_100, PG4MD_101, PG4MD_110, PG4MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4) { + PG3MD_000, PG3MD_001, PG3MD_010, PG3MD_011, + PG3MD_100, PG3MD_101, PG3MD_110, PG3MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG2MD_000, PG2MD_001, PG2MD_010, PG2MD_011, + PG2MD_100, PG2MD_101, PG2MD_110, PG2MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG1MD_000, PG1MD_001, PG1MD_010, PG1MD_011, + PG1MD_100, PG1MD_101, PG1MD_110, PG1MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011, + PG0MD_100, PG0MD_101, PG0MD_110, PG0MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, + PG27_IN, PG27_OUT, + PG26_IN, PG26_OUT, + PG25_IN, PG25_OUT, + PG24_IN, PG24_OUT, + PG23_IN, PG23_OUT, + PG22_IN, PG22_OUT, + PG21_IN, PG21_OUT, + PG20_IN, PG20_OUT, + PG19_IN, PG19_OUT, + PG18_IN, PG18_OUT, + PG17_IN, PG17_OUT, + PG16_IN, PG16_OUT } + }, + { PINMUX_CFG_REG("PGIOR0", 0xfffe38d2, 16, 1) { + PG15_IN, PG15_OUT, + PG14_IN, PG14_OUT, + PG13_IN, PG13_OUT, + PG12_IN, PG12_OUT, + PG11_IN, PG11_OUT, + PG10_IN, PG10_OUT, + PG9_IN, PG9_OUT, + PG8_IN, PG8_OUT, + PG7_IN, PG7_OUT, + PG6_IN, PG6_OUT, + PG5_IN, PG5_OUT, + PG4_IN, PG4_OUT, + PG3_IN, PG3_OUT, + PG2_IN, PG2_OUT, + PG1_IN, PG1_OUT, + PG0_IN, PG0_OUT } + }, + + { PINMUX_CFG_REG("PHCR1", 0xfffe38ec, 16, 4) { + PH7MD_00, PH7MD_01, PH7MD_10, PH7MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PH6MD_00, PH6MD_01, PH6MD_10, PH6MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PH5MD_00, PH5MD_01, PH5MD_10, PH5MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PH4MD_00, PH4MD_01, PH4MD_10, PH4MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PHCR0", 0xfffe38ee, 16, 4) { + PH3MD_00, PH3MD_01, PH3MD_10, PH3MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PH2MD_00, PH2MD_01, PH2MD_10, PH2MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PH1MD_00, PH1MD_01, PH1MD_10, PH1MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PH0MD_00, PH0MD_01, PH0MD_10, PH0MD_11, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PJCR7", 0xfffe3900, 16, 4) { + PJ31MD_0, PJ31MD_1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ30MD_000, PJ30MD_001, PJ30MD_010, PJ30MD_011, + PJ30MD_100, PJ30MD_101, PJ30MD_110, PJ30MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ29MD_000, PJ29MD_001, PJ29MD_010, PJ29MD_011, + PJ29MD_100, PJ29MD_101, PJ29MD_110, PJ29MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ28MD_000, PJ28MD_001, PJ28MD_010, PJ28MD_011, + PJ28MD_100, PJ28MD_101, PJ28MD_110, PJ28MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PJCR6", 0xfffe3902, 16, 4) { + PJ27MD_000, PJ27MD_001, PJ27MD_010, PJ27MD_011, + PJ27MD_100, PJ27MD_101, PJ27MD_110, PJ27MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ26MD_000, PJ26MD_001, PJ26MD_010, PJ26MD_011, + PJ26MD_100, PJ26MD_101, PJ26MD_110, PJ26MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ25MD_000, PJ25MD_001, PJ25MD_010, PJ25MD_011, + PJ25MD_100, PJ25MD_101, PJ25MD_110, PJ25MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ24MD_000, PJ24MD_001, PJ24MD_010, PJ24MD_011, + PJ24MD_100, PJ24MD_101, PJ24MD_110, PJ24MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PJCR5", 0xfffe3904, 16, 4) { + PJ23MD_000, PJ23MD_001, PJ23MD_010, PJ23MD_011, + PJ23MD_100, PJ23MD_101, PJ23MD_110, PJ23MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ22MD_000, PJ22MD_001, PJ22MD_010, PJ22MD_011, + PJ22MD_100, PJ22MD_101, PJ22MD_110, PJ22MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ21MD_000, PJ21MD_001, PJ21MD_010, PJ21MD_011, + PJ21MD_100, PJ21MD_101, PJ21MD_110, PJ21MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ20MD_000, PJ20MD_001, PJ20MD_010, PJ20MD_011, + PJ20MD_100, PJ20MD_101, PJ20MD_110, PJ20MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PJCR4", 0xfffe3906, 16, 4) { + PJ19MD_000, PJ19MD_001, PJ19MD_010, PJ19MD_011, + PJ19MD_100, PJ19MD_101, PJ19MD_110, PJ19MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ18MD_000, PJ18MD_001, PJ18MD_010, PJ18MD_011, + PJ18MD_100, PJ18MD_101, PJ18MD_110, PJ18MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ17MD_000, PJ17MD_001, PJ17MD_010, PJ17MD_011, + PJ17MD_100, PJ17MD_101, PJ17MD_110, PJ17MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ16MD_000, PJ16MD_001, PJ16MD_010, PJ16MD_011, + PJ16MD_100, PJ16MD_101, PJ16MD_110, PJ16MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PJCR3", 0xfffe3908, 16, 4) { + PJ15MD_000, PJ15MD_001, PJ15MD_010, PJ15MD_011, + PJ15MD_100, PJ15MD_101, PJ15MD_110, PJ15MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ14MD_000, PJ14MD_001, PJ14MD_010, PJ14MD_011, + PJ14MD_100, PJ14MD_101, PJ14MD_110, PJ14MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ13MD_000, PJ13MD_001, PJ13MD_010, PJ13MD_011, + PJ13MD_100, PJ13MD_101, PJ13MD_110, PJ13MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ12MD_000, PJ12MD_001, PJ12MD_010, PJ12MD_011, + PJ12MD_100, PJ12MD_101, PJ12MD_110, PJ12MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PJCR2", 0xfffe390a, 16, 4) { + PJ11MD_000, PJ11MD_001, PJ11MD_010, PJ11MD_011, + PJ11MD_100, PJ11MD_101, PJ11MD_110, PJ11MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ10MD_000, PJ10MD_001, PJ10MD_010, PJ10MD_011, + PJ10MD_100, PJ10MD_101, PJ10MD_110, PJ10MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ9MD_000, PJ9MD_001, PJ9MD_010, PJ9MD_011, + PJ9MD_100, PJ9MD_101, PJ9MD_110, PJ9MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ8MD_000, PJ8MD_001, PJ8MD_010, PJ8MD_011, + PJ8MD_100, PJ8MD_101, PJ8MD_110, PJ8MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PJCR1", 0xfffe390c, 16, 4) { + PJ7MD_000, PJ7MD_001, PJ7MD_010, PJ7MD_011, + PJ7MD_100, PJ7MD_101, PJ7MD_110, PJ7MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ6MD_000, PJ6MD_001, PJ6MD_010, PJ6MD_011, + PJ6MD_100, PJ6MD_101, PJ6MD_110, PJ6MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ5MD_000, PJ5MD_001, PJ5MD_010, PJ5MD_011, + PJ5MD_100, PJ5MD_101, PJ5MD_110, PJ5MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ4MD_000, PJ4MD_001, PJ4MD_010, PJ4MD_011, + PJ4MD_100, PJ4MD_101, PJ4MD_110, PJ4MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PJCR0", 0xfffe390e, 16, 4) { + PJ3MD_000, PJ3MD_001, PJ3MD_010, PJ3MD_011, + PJ3MD_100, PJ3MD_101, PJ3MD_110, PJ3MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011, + PJ2MD_100, PJ2MD_101, PJ2MD_110, PJ2MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011, + PJ1MD_100, PJ1MD_101, PJ1MD_110, PJ1MD_111, + 0, 0, 0, 0, 0, 0, 0, 0, + + PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011, + PJ0MD_100, PJ0MD_101, PJ0MD_110, PJ0MD_111, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + { PINMUX_CFG_REG("PJIOR1", 0xfffe3910, 16, 1) { + PJ31_IN, PJ31_OUT, + PJ30_IN, PJ30_OUT, + PJ29_IN, PJ29_OUT, + PJ28_IN, PJ28_OUT, + PJ27_IN, PJ27_OUT, + PJ26_IN, PJ26_OUT, + PJ25_IN, PJ25_OUT, + PJ24_IN, PJ24_OUT, + PJ23_IN, PJ23_OUT, + PJ22_IN, PJ22_OUT, + PJ21_IN, PJ21_OUT, + PJ20_IN, PJ20_OUT, + PJ19_IN, PJ19_OUT, + PJ18_IN, PJ18_OUT, + PJ17_IN, PJ17_OUT, + PJ16_IN, PJ16_OUT } + }, + { PINMUX_CFG_REG("PJIOR0", 0xfffe3912, 16, 1) { + PJ15_IN, PJ15_OUT, + PJ14_IN, PJ14_OUT, + PJ13_IN, PJ13_OUT, + PJ12_IN, PJ12_OUT, + PJ11_IN, PJ11_OUT, + PJ10_IN, PJ10_OUT, + PJ9_IN, PJ9_OUT, + PJ8_IN, PJ8_OUT, + PJ7_IN, PJ7_OUT, + PJ6_IN, PJ6_OUT, + PJ5_IN, PJ5_OUT, + PJ4_IN, PJ4_OUT, + PJ3_IN, PJ3_OUT, + PJ2_IN, PJ2_OUT, + PJ1_IN, PJ1_OUT, + PJ0_IN, PJ0_OUT } + }, + + {} +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) { + 0, 0, 0, 0, 0, 0, 0, PA1_DATA, + 0, 0, 0, 0, 0, 0, 0, PA0_DATA } + }, + + { PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, PB22_DATA, PB21_DATA, PB20_DATA, + PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA } + }, + { PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16) { + PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA, + PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA, + PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, + PB3_DATA, PB2_DATA, PB1_DATA, 0 } + }, + + { PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16) { + 0, 0, 0, 0, + 0, 0, 0, PC8_DATA, + PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, + PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA } + }, + + { PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16) { + PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA, + PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA, + PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, + PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA } + }, + + { PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16) { + 0, 0, 0, 0, 0, 0, 0, 0, + PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA, + PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA } + }, + + { PINMUX_DATA_REG("PFDR1", 0xfffe38b4, 16) { + 0, 0, 0, 0, 0, 0, 0, 0, + PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA, + PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA } + }, + { PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16) { + PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA, + PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA, + PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, + PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA } + }, + + { PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16) { + 0, 0, 0, 0, + PG27_DATA, PG26_DATA, PG25_DATA, PG24_DATA, + PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA, + PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA } + }, + { PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16) { + PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA, + PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA, + PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, + PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA } + }, + + { PINMUX_DATA_REG("PJDR1", 0xfffe3914, 16) { + PJ31_DATA, PJ30_DATA, PJ29_DATA, PJ28_DATA, + PJ27_DATA, PJ26_DATA, PJ25_DATA, PJ24_DATA, + PJ23_DATA, PJ22_DATA, PJ21_DATA, PJ20_DATA, + PJ19_DATA, PJ18_DATA, PJ17_DATA, PJ16_DATA } + }, + { PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16) { + PJ15_DATA, PJ14_DATA, PJ13_DATA, PJ12_DATA, + PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA, + PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, + PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA } + }, + + { } +}; + +static struct pinmux_info sh7269_pinmux_info = { + .name = "sh7269_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PA1, + .last_gpio = GPIO_FN_LCD_M_DISP, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +static int __init plat_pinmux_setup(void) +{ + return register_pinmux(&sh7269_pinmux_info); +} +arch_initcall(plat_pinmux_setup); -- cgit v0.10.2 From c4f10e5cd79ce09ef94be0924395c62350bf262d Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 10 May 2012 17:23:58 +0900 Subject: sh: Fix up comment noise in sh7269 pinmux code. The build complains about a /* nested within a comment block, so just tidy up the formatting. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c index 9f0109f..f25127c 100644 --- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c +++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c @@ -1907,8 +1907,9 @@ static struct pinmux_gpio pinmux_gpios[] = { static struct pinmux_cfg_reg pinmux_config_regs[] = { /* "name" addr register_size Field_Width */ + /* where Field_Width is 1 for single mode registers or 4 for upto 16 - /* mode registers and modes are described in assending order [0..16] */ + mode registers and modes are described in assending order [0..16] */ { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) { 0, 0, 0, 0, 0, 0, 0, 0, -- cgit v0.10.2 From dbdb4e9f3fd4914caba6f102e62eef23920ab1f4 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 14 May 2012 10:27:34 +0900 Subject: sh: Tidy up and generalize page fault error paths. This follows the x86 changes for tidying up the page fault error paths. We'll build on top of this for _32/_64 unification. Signed-off-by: Paul Mundt diff --git a/arch/sh/include/asm/kdebug.h b/arch/sh/include/asm/kdebug.h index 5f6d2e9..a6201f1 100644 --- a/arch/sh/include/asm/kdebug.h +++ b/arch/sh/include/asm/kdebug.h @@ -10,4 +10,6 @@ enum die_val { DIE_SSTEP, }; +extern void printk_address(unsigned long address, int reliable); + #endif /* __ASM_SH_KDEBUG_H */ diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c index 8ce856d..889e83b 100644 --- a/arch/sh/mm/fault_32.c +++ b/arch/sh/mm/fault_32.c @@ -2,7 +2,7 @@ * Page fault handler for SH with an MMU. * * Copyright (C) 1999 Niibe Yutaka - * Copyright (C) 2003 - 2009 Paul Mundt + * Copyright (C) 2003 - 2012 Paul Mundt * * Based on linux/arch/i386/mm/fault.c: * Copyright (C) 1995 Linus Torvalds @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -35,6 +36,20 @@ static inline int notify_page_fault(struct pt_regs *regs, int trap) return ret; } +static void +force_sig_info_fault(int si_signo, int si_code, unsigned long address, + struct task_struct *tsk) +{ + siginfo_t info; + + info.si_signo = si_signo; + info.si_errno = 0; + info.si_code = si_code; + info.si_addr = (void __user *)address; + + force_sig_info(si_signo, &info, tsk); +} + /* * This is useful to dump out the page tables associated with * 'addr' in mm 'mm'. @@ -176,6 +191,185 @@ static noinline int vmalloc_fault(unsigned long address) return 0; } +static void +show_fault_oops(struct pt_regs *regs, unsigned long address) +{ + if (!oops_may_print()) + return; + + printk(KERN_ALERT "BUG: unable to handle kernel "); + if (address < PAGE_SIZE) + printk(KERN_CONT "NULL pointer dereference"); + else + printk(KERN_CONT "paging request"); + + printk(KERN_CONT " at %08lx\n", address); + printk(KERN_ALERT "PC:"); + printk_address(regs->pc, 1); + + show_pte(NULL, address); +} + +static noinline void +no_context(struct pt_regs *regs, unsigned long writeaccess, + unsigned long address) +{ + /* Are we prepared to handle this kernel fault? */ + if (fixup_exception(regs)) + return; + + if (handle_trapped_io(regs, address)) + return; + + /* + * Oops. The kernel tried to access some bad page. We'll have to + * terminate things with extreme prejudice. + */ + bust_spinlocks(1); + + show_fault_oops(regs, address); + + die("Oops", regs, writeaccess); + bust_spinlocks(0); + do_exit(SIGKILL); +} + +static void +__bad_area_nosemaphore(struct pt_regs *regs, unsigned long writeaccess, + unsigned long address, int si_code) +{ + struct task_struct *tsk = current; + + /* User mode accesses just cause a SIGSEGV */ + if (user_mode(regs)) { + /* + * It's possible to have interrupts off here: + */ + local_irq_enable(); + + force_sig_info_fault(SIGSEGV, si_code, address, tsk); + + return; + } + + no_context(regs, writeaccess, address); +} + +static noinline void +bad_area_nosemaphore(struct pt_regs *regs, unsigned long writeaccess, + unsigned long address) +{ + __bad_area_nosemaphore(regs, writeaccess, address, SEGV_MAPERR); +} + +static void +__bad_area(struct pt_regs *regs, unsigned long writeaccess, + unsigned long address, int si_code) +{ + struct mm_struct *mm = current->mm; + + /* + * Something tried to access memory that isn't in our memory map.. + * Fix it, but check if it's kernel or user first.. + */ + up_read(&mm->mmap_sem); + + __bad_area_nosemaphore(regs, writeaccess, address, si_code); +} + +static noinline void +bad_area(struct pt_regs *regs, unsigned long writeaccess, unsigned long address) +{ + __bad_area(regs, writeaccess, address, SEGV_MAPERR); +} + +static noinline void +bad_area_access_error(struct pt_regs *regs, unsigned long writeaccess, + unsigned long address) +{ + __bad_area(regs, writeaccess, address, SEGV_ACCERR); +} + +static void out_of_memory(void) +{ + /* + * We ran out of memory, call the OOM killer, and return the userspace + * (which will retry the fault, or kill us if we got oom-killed): + */ + up_read(¤t->mm->mmap_sem); + + pagefault_out_of_memory(); +} + +static void +do_sigbus(struct pt_regs *regs, unsigned long writeaccess, unsigned long address) +{ + struct task_struct *tsk = current; + struct mm_struct *mm = tsk->mm; + + up_read(&mm->mmap_sem); + + /* Kernel mode? Handle exceptions or die: */ + if (!user_mode(regs)) + no_context(regs, writeaccess, address); + + force_sig_info_fault(SIGBUS, BUS_ADRERR, address, tsk); +} + +static noinline int +mm_fault_error(struct pt_regs *regs, unsigned long writeaccess, + unsigned long address, unsigned int fault) +{ + /* + * Pagefault was interrupted by SIGKILL. We have no reason to + * continue pagefault. + */ + if (fatal_signal_pending(current)) { + if (!(fault & VM_FAULT_RETRY)) + up_read(¤t->mm->mmap_sem); + if (!user_mode(regs)) + no_context(regs, writeaccess, address); + return 1; + } + + if (!(fault & VM_FAULT_ERROR)) + return 0; + + if (fault & VM_FAULT_OOM) { + /* Kernel mode? Handle exceptions or die: */ + if (!user_mode(regs)) { + up_read(¤t->mm->mmap_sem); + no_context(regs, writeaccess, address); + return 1; + } + + out_of_memory(); + } else { + if (fault & VM_FAULT_SIGBUS) + do_sigbus(regs, writeaccess, address); + else + BUG(); + } + + return 1; +} + +static inline int access_error(int write, struct vm_area_struct *vma) +{ + if (write) { + /* write, present and write, not present: */ + if (unlikely(!(vma->vm_flags & VM_WRITE))) + return 1; + return 0; + } + + /* read, not present: */ + if (unlikely(!(vma->vm_flags & (VM_READ | VM_EXEC | VM_WRITE)))) + return 1; + + return 0; +} + static int fault_in_kernel_space(unsigned long address) { return address >= TASK_SIZE; @@ -194,15 +388,12 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, struct task_struct *tsk; struct mm_struct *mm; struct vm_area_struct * vma; - int si_code; int fault; - siginfo_t info; unsigned int flags = (FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE | (writeaccess ? FAULT_FLAG_WRITE : 0)); tsk = current; mm = tsk->mm; - si_code = SEGV_MAPERR; vec = lookup_exception_vector(); /* @@ -220,7 +411,8 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, if (notify_page_fault(regs, vec)) return; - goto bad_area_nosemaphore; + bad_area_nosemaphore(regs, writeaccess, address); + return; } if (unlikely(notify_page_fault(regs, vec))) @@ -236,34 +428,38 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, * If we're in an interrupt, have no user context or are running * in an atomic region then we must not take the fault: */ - if (in_atomic() || !mm) - goto no_context; + if (unlikely(in_atomic() || !mm)) { + bad_area_nosemaphore(regs, writeaccess, address); + return; + } retry: down_read(&mm->mmap_sem); vma = find_vma(mm, address); - if (!vma) - goto bad_area; - if (vma->vm_start <= address) + if (unlikely(!vma)) { + bad_area(regs, writeaccess, address); + return; + } + if (likely(vma->vm_start <= address)) goto good_area; - if (!(vma->vm_flags & VM_GROWSDOWN)) - goto bad_area; - if (expand_stack(vma, address)) - goto bad_area; + if (unlikely(!(vma->vm_flags & VM_GROWSDOWN))) { + bad_area(regs, writeaccess, address); + return; + } + if (unlikely(expand_stack(vma, address))) { + bad_area(regs, writeaccess, address); + return; + } /* * Ok, we have a good vm_area for this memory access, so * we can handle it.. */ good_area: - si_code = SEGV_ACCERR; - if (writeaccess) { - if (!(vma->vm_flags & VM_WRITE)) - goto bad_area; - } else { - if (!(vma->vm_flags & (VM_READ | VM_EXEC | VM_WRITE))) - goto bad_area; + if (unlikely(access_error(writeaccess, vma))) { + bad_area_access_error(regs, writeaccess, address); + return; } /* @@ -273,16 +469,9 @@ good_area: */ fault = handle_mm_fault(mm, vma, address, flags); - if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) - return; - - if (unlikely(fault & VM_FAULT_ERROR)) { - if (fault & VM_FAULT_OOM) - goto out_of_memory; - else if (fault & VM_FAULT_SIGBUS) - goto do_sigbus; - BUG(); - } + if (unlikely(fault & (VM_FAULT_RETRY | VM_FAULT_ERROR))) + if (mm_fault_error(regs, writeaccess, address, fault)) + return; if (flags & FAULT_FLAG_ALLOW_RETRY) { if (fault & VM_FAULT_MAJOR) { @@ -307,80 +496,6 @@ good_area: } up_read(&mm->mmap_sem); - return; - - /* - * Something tried to access memory that isn't in our memory map.. - * Fix it, but check if it's kernel or user first.. - */ -bad_area: - up_read(&mm->mmap_sem); - -bad_area_nosemaphore: - if (user_mode(regs)) { - info.si_signo = SIGSEGV; - info.si_errno = 0; - info.si_code = si_code; - info.si_addr = (void *) address; - force_sig_info(SIGSEGV, &info, tsk); - return; - } - -no_context: - /* Are we prepared to handle this kernel fault? */ - if (fixup_exception(regs)) - return; - - if (handle_trapped_io(regs, address)) - return; -/* - * Oops. The kernel tried to access some bad page. We'll have to - * terminate things with extreme prejudice. - * - */ - - bust_spinlocks(1); - - if (oops_may_print()) { - printk(KERN_ALERT - "Unable to handle kernel %s at virtual address %08lx\n", - (address < PAGE_SIZE) ? "NULL pointer dereference" : - "paging request", address); - - show_pte(mm, address); - } - - die("Oops", regs, writeaccess); - bust_spinlocks(0); - do_exit(SIGKILL); - -/* - * We ran out of memory, or some other thing happened to us that made - * us unable to handle the page fault gracefully. - */ -out_of_memory: - up_read(&mm->mmap_sem); - if (!user_mode(regs)) - goto no_context; - pagefault_out_of_memory(); - return; - -do_sigbus: - up_read(&mm->mmap_sem); - - /* - * Send a sigbus, regardless of whether we were in kernel - * or user mode. - */ - info.si_signo = SIGBUS; - info.si_errno = 0; - info.si_code = BUS_ADRERR; - info.si_addr = (void *)address; - force_sig_info(SIGBUS, &info, tsk); - - /* Kernel mode? Handle exceptions or die */ - if (!user_mode(regs)) - goto no_context; } /* -- cgit v0.10.2 From f007688a50cf5724049a4a5f17023fcdb0966b54 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 14 May 2012 13:04:08 +0900 Subject: sh64: Provide EXPEVT helper. We need a lookup_exception_vector() helper for sh64 in order to use the common page fault code. Signed-off-by: Paul Mundt diff --git a/arch/sh/include/asm/traps_64.h b/arch/sh/include/asm/traps_64.h index c52d7f9..ef5eff9 100644 --- a/arch/sh/include/asm/traps_64.h +++ b/arch/sh/include/asm/traps_64.h @@ -10,8 +10,22 @@ #ifndef __ASM_SH_TRAPS_64_H #define __ASM_SH_TRAPS_64_H +#include + extern void phys_stext(void); +#define lookup_exception_vector() \ +({ \ + unsigned long _vec; \ + \ + __asm__ __volatile__ ( \ + "getcon " __EXPEVT ", %0\n\t" \ + : "=r" (_vec) \ + ); \ + \ + _vec; \ +}) + static inline void trigger_address_error(void) { phys_stext(); -- cgit v0.10.2 From 5a1dc78a38bfb04159a08cd493e5b3d844939e6c Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 14 May 2012 14:57:28 +0900 Subject: sh: Support thread fault code encoding. This provides a simple interface modelled after sparc64/m32r to encode the error code in the upper byte of thread_info for finer-grained handling in the page fault path. Signed-off-by: Paul Mundt diff --git a/arch/sh/include/asm/thread_info.h b/arch/sh/include/asm/thread_info.h index 20ee40a..25a13e5 100644 --- a/arch/sh/include/asm/thread_info.h +++ b/arch/sh/include/asm/thread_info.h @@ -10,8 +10,18 @@ * - Incorporating suggestions made by Linus Torvalds and Dave Miller */ #ifdef __KERNEL__ + #include +/* + * Page fault error code bits + */ +#define FAULT_CODE_WRITE (1 << 0) /* write access */ +#define FAULT_CODE_INITIAL (1 << 1) /* initial page write */ +#define FAULT_CODE_ITLB (1 << 2) /* ITLB miss */ +#define FAULT_CODE_PROT (1 << 3) /* protection fault */ +#define FAULT_CODE_USER (1 << 4) /* user-mode access */ + #ifndef __ASSEMBLY__ #include @@ -107,10 +117,13 @@ extern void init_thread_xstate(void); #endif /* __ASSEMBLY__ */ /* - * thread information flags - * - these are process state flags that various assembly files may need to access - * - pending work-to-be-done flags are in LSW - * - other flags in MSW + * Thread information flags + * + * - Limited to 24 bits, upper byte used for fault code encoding. + * + * - _TIF_ALLWORK_MASK and _TIF_WORK_MASK need to fit within 2 bytes, or + * we blow the tst immediate size constraints and need to fix up + * arch/sh/kernel/entry-common.S. */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ #define TIF_SIGPENDING 1 /* signal pending */ @@ -133,12 +146,6 @@ extern void init_thread_xstate(void); #define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT) #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) -/* - * _TIF_ALLWORK_MASK and _TIF_WORK_MASK need to fit within 2 bytes, or we - * blow the tst immediate size constraints and need to fix up - * arch/sh/kernel/entry-common.S. - */ - /* work to do in syscall trace */ #define _TIF_WORK_SYSCALL_MASK (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \ _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \ @@ -165,6 +172,7 @@ extern void init_thread_xstate(void); #define TS_USEDFPU 0x0002 /* FPU used by this task this quantum */ #ifndef __ASSEMBLY__ + #define HAVE_SET_RESTORE_SIGMASK 1 static inline void set_restore_sigmask(void) { @@ -172,6 +180,24 @@ static inline void set_restore_sigmask(void) ti->status |= TS_RESTORE_SIGMASK; set_bit(TIF_SIGPENDING, (unsigned long *)&ti->flags); } + +#define TI_FLAG_FAULT_CODE_SHIFT 24 + +/* + * Additional thread flag encoding + */ +static inline void set_thread_fault_code(unsigned int val) +{ + struct thread_info *ti = current_thread_info(); + ti->flags = (ti->flags & (~0 >> (32 - TI_FLAG_FAULT_CODE_SHIFT))) + | (val << TI_FLAG_FAULT_CODE_SHIFT); +} + +static inline unsigned int get_thread_fault_code(void) +{ + struct thread_info *ti = current_thread_info(); + return ti->flags >> TI_FLAG_FAULT_CODE_SHIFT; +} #endif /* !__ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S index f6a389c..262db6e 100644 --- a/arch/sh/kernel/cpu/sh3/entry.S +++ b/arch/sh/kernel/cpu/sh3/entry.S @@ -2,7 +2,7 @@ * arch/sh/kernel/cpu/sh3/entry.S * * Copyright (C) 1999, 2000, 2002 Niibe Yutaka - * Copyright (C) 2003 - 2006 Paul Mundt + * Copyright (C) 2003 - 2012 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -17,6 +17,7 @@ #include #include #include +#include ! NOTE: ! GNU as (as of 2.9.1) changes bf/s into bt/s and bra, when the address @@ -114,22 +115,22 @@ ENTRY(tlb_miss_load) .align 2 ENTRY(tlb_miss_store) bra call_handle_tlbmiss - mov #1, r5 + mov #FAULT_CODE_WRITE, r5 .align 2 ENTRY(initial_page_write) bra call_handle_tlbmiss - mov #2, r5 + mov #FAULT_CODE_INITIAL, r5 .align 2 ENTRY(tlb_protection_violation_load) bra call_do_page_fault - mov #0, r5 + mov #FAULT_CODE_PROT, r5 .align 2 ENTRY(tlb_protection_violation_store) bra call_do_page_fault - mov #1, r5 + mov #(FAULT_CODE_PROT | FAULT_CODE_WRITE), r5 call_handle_tlbmiss: mov.l 1f, r0 diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c index 889e83b..a469b95 100644 --- a/arch/sh/mm/fault_32.c +++ b/arch/sh/mm/fault_32.c @@ -211,7 +211,7 @@ show_fault_oops(struct pt_regs *regs, unsigned long address) } static noinline void -no_context(struct pt_regs *regs, unsigned long writeaccess, +no_context(struct pt_regs *regs, unsigned long error_code, unsigned long address) { /* Are we prepared to handle this kernel fault? */ @@ -229,13 +229,13 @@ no_context(struct pt_regs *regs, unsigned long writeaccess, show_fault_oops(regs, address); - die("Oops", regs, writeaccess); + die("Oops", regs, error_code); bust_spinlocks(0); do_exit(SIGKILL); } static void -__bad_area_nosemaphore(struct pt_regs *regs, unsigned long writeaccess, +__bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code, unsigned long address, int si_code) { struct task_struct *tsk = current; @@ -252,18 +252,18 @@ __bad_area_nosemaphore(struct pt_regs *regs, unsigned long writeaccess, return; } - no_context(regs, writeaccess, address); + no_context(regs, error_code, address); } static noinline void -bad_area_nosemaphore(struct pt_regs *regs, unsigned long writeaccess, +bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code, unsigned long address) { - __bad_area_nosemaphore(regs, writeaccess, address, SEGV_MAPERR); + __bad_area_nosemaphore(regs, error_code, address, SEGV_MAPERR); } static void -__bad_area(struct pt_regs *regs, unsigned long writeaccess, +__bad_area(struct pt_regs *regs, unsigned long error_code, unsigned long address, int si_code) { struct mm_struct *mm = current->mm; @@ -274,20 +274,20 @@ __bad_area(struct pt_regs *regs, unsigned long writeaccess, */ up_read(&mm->mmap_sem); - __bad_area_nosemaphore(regs, writeaccess, address, si_code); + __bad_area_nosemaphore(regs, error_code, address, si_code); } static noinline void -bad_area(struct pt_regs *regs, unsigned long writeaccess, unsigned long address) +bad_area(struct pt_regs *regs, unsigned long error_code, unsigned long address) { - __bad_area(regs, writeaccess, address, SEGV_MAPERR); + __bad_area(regs, error_code, address, SEGV_MAPERR); } static noinline void -bad_area_access_error(struct pt_regs *regs, unsigned long writeaccess, +bad_area_access_error(struct pt_regs *regs, unsigned long error_code, unsigned long address) { - __bad_area(regs, writeaccess, address, SEGV_ACCERR); + __bad_area(regs, error_code, address, SEGV_ACCERR); } static void out_of_memory(void) @@ -302,7 +302,7 @@ static void out_of_memory(void) } static void -do_sigbus(struct pt_regs *regs, unsigned long writeaccess, unsigned long address) +do_sigbus(struct pt_regs *regs, unsigned long error_code, unsigned long address) { struct task_struct *tsk = current; struct mm_struct *mm = tsk->mm; @@ -311,13 +311,13 @@ do_sigbus(struct pt_regs *regs, unsigned long writeaccess, unsigned long address /* Kernel mode? Handle exceptions or die: */ if (!user_mode(regs)) - no_context(regs, writeaccess, address); + no_context(regs, error_code, address); force_sig_info_fault(SIGBUS, BUS_ADRERR, address, tsk); } static noinline int -mm_fault_error(struct pt_regs *regs, unsigned long writeaccess, +mm_fault_error(struct pt_regs *regs, unsigned long error_code, unsigned long address, unsigned int fault) { /* @@ -328,7 +328,7 @@ mm_fault_error(struct pt_regs *regs, unsigned long writeaccess, if (!(fault & VM_FAULT_RETRY)) up_read(¤t->mm->mmap_sem); if (!user_mode(regs)) - no_context(regs, writeaccess, address); + no_context(regs, error_code, address); return 1; } @@ -339,14 +339,14 @@ mm_fault_error(struct pt_regs *regs, unsigned long writeaccess, /* Kernel mode? Handle exceptions or die: */ if (!user_mode(regs)) { up_read(¤t->mm->mmap_sem); - no_context(regs, writeaccess, address); + no_context(regs, error_code, address); return 1; } out_of_memory(); } else { if (fault & VM_FAULT_SIGBUS) - do_sigbus(regs, writeaccess, address); + do_sigbus(regs, error_code, address); else BUG(); } @@ -381,7 +381,7 @@ static int fault_in_kernel_space(unsigned long address) * routines. */ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, - unsigned long writeaccess, + unsigned long error_code, unsigned long address) { unsigned long vec; @@ -389,8 +389,9 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, struct mm_struct *mm; struct vm_area_struct * vma; int fault; + int write = error_code & FAULT_CODE_WRITE; unsigned int flags = (FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE | - (writeaccess ? FAULT_FLAG_WRITE : 0)); + (write ? FAULT_FLAG_WRITE : 0)); tsk = current; mm = tsk->mm; @@ -411,7 +412,7 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, if (notify_page_fault(regs, vec)) return; - bad_area_nosemaphore(regs, writeaccess, address); + bad_area_nosemaphore(regs, error_code, address); return; } @@ -429,7 +430,7 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, * in an atomic region then we must not take the fault: */ if (unlikely(in_atomic() || !mm)) { - bad_area_nosemaphore(regs, writeaccess, address); + bad_area_nosemaphore(regs, error_code, address); return; } @@ -438,17 +439,17 @@ retry: vma = find_vma(mm, address); if (unlikely(!vma)) { - bad_area(regs, writeaccess, address); + bad_area(regs, error_code, address); return; } if (likely(vma->vm_start <= address)) goto good_area; if (unlikely(!(vma->vm_flags & VM_GROWSDOWN))) { - bad_area(regs, writeaccess, address); + bad_area(regs, error_code, address); return; } if (unlikely(expand_stack(vma, address))) { - bad_area(regs, writeaccess, address); + bad_area(regs, error_code, address); return; } @@ -457,11 +458,13 @@ retry: * we can handle it.. */ good_area: - if (unlikely(access_error(writeaccess, vma))) { - bad_area_access_error(regs, writeaccess, address); + if (unlikely(access_error(error_code, vma))) { + bad_area_access_error(regs, error_code, address); return; } + set_thread_fault_code(error_code); + /* * If for any reason at all we couldn't handle the fault, * make sure we exit gracefully rather than endlessly redo @@ -470,7 +473,7 @@ good_area: fault = handle_mm_fault(mm, vma, address, flags); if (unlikely(fault & (VM_FAULT_RETRY | VM_FAULT_ERROR))) - if (mm_fault_error(regs, writeaccess, address, fault)) + if (mm_fault_error(regs, error_code, address, fault)) return; if (flags & FAULT_FLAG_ALLOW_RETRY) { @@ -502,7 +505,7 @@ good_area: * Called with interrupts disabled. */ asmlinkage int __kprobes -handle_tlbmiss(struct pt_regs *regs, unsigned long writeaccess, +handle_tlbmiss(struct pt_regs *regs, unsigned long error_code, unsigned long address) { pgd_t *pgd; @@ -535,10 +538,10 @@ handle_tlbmiss(struct pt_regs *regs, unsigned long writeaccess, entry = *pte; if (unlikely(pte_none(entry) || pte_not_present(entry))) return 1; - if (unlikely(writeaccess && !pte_write(entry))) + if (unlikely(error_code && !pte_write(entry))) return 1; - if (writeaccess) + if (error_code) entry = pte_mkdirty(entry); entry = pte_mkyoung(entry); @@ -550,10 +553,11 @@ handle_tlbmiss(struct pt_regs *regs, unsigned long writeaccess, * the case of an initial page write exception, so we need to * flush it in order to avoid potential TLB entry duplication. */ - if (writeaccess == 2) + if (error_code == FAULT_CODE_INITIAL) local_flush_tlb_one(get_asid(), address & PAGE_MASK); #endif + set_thread_fault_code(error_code); update_mmu_cache(NULL, address, pte); return 0; -- cgit v0.10.2 From 9a7b7739f9dba4014fc93531e4c2b6efac41b0a7 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 14 May 2012 15:07:52 +0900 Subject: sh64: Utilize thread fault code encoding. This plugs in fault code encoding for the sh64 page fault, too. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh5/entry.S b/arch/sh/kernel/cpu/sh5/entry.S index 6b80295..de60dc8 100644 --- a/arch/sh/kernel/cpu/sh5/entry.S +++ b/arch/sh/kernel/cpu/sh5/entry.S @@ -1079,9 +1079,8 @@ restore_all: * * Kernel TLB fault handlers will get a slightly different interface. * (r2) struct pt_regs *, original register's frame pointer - * (r3) writeaccess, whether it's a store fault as opposed to load fault - * (r4) execaccess, whether it's a ITLB fault as opposed to DTLB fault - * (r5) Effective Address of fault + * (r3) page fault error code (see asm/thread_info.h) + * (r4) Effective Address of fault * (LINK) return address * (SP) = r2 * @@ -1092,26 +1091,25 @@ restore_all: tlb_miss_load: or SP, ZERO, r2 or ZERO, ZERO, r3 /* Read */ - or ZERO, ZERO, r4 /* Data */ - getcon TEA, r5 + getcon TEA, r4 pta call_do_page_fault, tr0 beq ZERO, ZERO, tr0 tlb_miss_store: or SP, ZERO, r2 - movi 1, r3 /* Write */ - or ZERO, ZERO, r4 /* Data */ - getcon TEA, r5 + movi FAULT_CODE_WRITE, r3 /* Write */ + getcon TEA, r4 pta call_do_page_fault, tr0 beq ZERO, ZERO, tr0 itlb_miss_or_IRQ: pta its_IRQ, tr0 beqi/u r4, EVENT_INTERRUPT, tr0 + + /* ITLB miss */ or SP, ZERO, r2 - or ZERO, ZERO, r3 /* Read */ - movi 1, r4 /* Text */ - getcon TEA, r5 + movi FAULT_CODE_ITLB, r3 + getcon TEA, r4 /* Fall through */ call_do_page_fault: diff --git a/arch/sh/mm/tlbflush_64.c b/arch/sh/mm/tlbflush_64.c index be01f92..99c5833 100644 --- a/arch/sh/mm/tlbflush_64.c +++ b/arch/sh/mm/tlbflush_64.c @@ -61,15 +61,17 @@ static pte_t *lookup_pte(struct mm_struct *mm, unsigned long address) * and the problem, and then passes it off to one of the appropriate * routines. */ -asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long writeaccess, - unsigned long textaccess, unsigned long address) +asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code, + unsigned long address) { struct task_struct *tsk; struct mm_struct *mm; struct vm_area_struct * vma; const struct exception_table_entry *fixup; + int write = error_code & FAULT_CODE_WRITE; + int textaccess = error_code & FAULT_CODE_ITLB; unsigned int flags = (FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE | - (writeaccess ? FAULT_FLAG_WRITE : 0)); + (write ? FAULT_FLAG_WRITE : 0)); pte_t *pte; int fault; @@ -122,7 +124,7 @@ good_area: if (!(vma->vm_flags & VM_EXEC)) goto bad_area; } else { - if (writeaccess) { + if (write) { if (!(vma->vm_flags & VM_WRITE)) goto bad_area; } else { @@ -239,7 +241,7 @@ no_context: printk(KERN_ALERT "Unable to handle kernel paging request"); printk(" at virtual address %08lx\n", address); printk(KERN_ALERT "pc = %08Lx%08Lx\n", regs->pc >> 32, regs->pc & 0xffffffff); - die("Oops", regs, writeaccess); + die("Oops", regs, error_code); do_exit(SIGKILL); /* -- cgit v0.10.2 From 20e7c297efeca0861adcca073a0d283da659834b Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 14 May 2012 15:11:35 +0900 Subject: sh: Ensure fixmap and store queue space can co-exist. At the moment the top of the fixmap space is calculated from P4SEG, which places it at the end of the store queue space when that API is enabled. Make sure we use P3_ADDR_MAX here instead to find the proper address limit. With this done, it's also possible to switch to the generic vmalloc address range check now that VMALLOC_START/END encapsulate the translatable areas that we care about. Signed-off-by: Paul Mundt diff --git a/arch/sh/include/asm/fixmap.h b/arch/sh/include/asm/fixmap.h index bd7e79a..5f1ca55 100644 --- a/arch/sh/include/asm/fixmap.h +++ b/arch/sh/include/asm/fixmap.h @@ -94,7 +94,7 @@ extern void __clear_fixmap(enum fixed_addresses idx, pgprot_t flags); * at the top of mem.. */ #ifdef CONFIG_SUPERH32 -#define FIXADDR_TOP (P4SEG - PAGE_SIZE) +#define FIXADDR_TOP (P3_ADDR_MAX - PAGE_SIZE) #else #define FIXADDR_TOP (0xff000000 - PAGE_SIZE) #endif diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c index a469b95..39e291c 100644 --- a/arch/sh/mm/fault_32.c +++ b/arch/sh/mm/fault_32.c @@ -168,8 +168,8 @@ static noinline int vmalloc_fault(unsigned long address) pmd_t *pmd_k; pte_t *pte_k; - /* Make sure we are in vmalloc/module/P3 area: */ - if (!(address >= P3SEG && address < P3_ADDR_MAX)) + /* Make sure we are in vmalloc/module area: */ + if (!is_vmalloc_addr((void *)address)) return -1; /* -- cgit v0.10.2 From e45af0e083dfc5d49dbad6965b9eeb3ac0072d82 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 14 May 2012 15:16:11 +0900 Subject: sh64: Kill off unused fixed I/O mapping window. This was reworked some time ago to go through fixmaps instead, leaving the range itself unused. As such, kill off the remaining references and hand over the remaining space for fixmaps directly. This also makes it possible to simplify the vmalloc fault case as we no longer have to care about the special section. Signed-off-by: Paul Mundt diff --git a/arch/sh/include/asm/fixmap.h b/arch/sh/include/asm/fixmap.h index 5f1ca55..41cda12 100644 --- a/arch/sh/include/asm/fixmap.h +++ b/arch/sh/include/asm/fixmap.h @@ -96,7 +96,7 @@ extern void __clear_fixmap(enum fixed_addresses idx, pgprot_t flags); #ifdef CONFIG_SUPERH32 #define FIXADDR_TOP (P3_ADDR_MAX - PAGE_SIZE) #else -#define FIXADDR_TOP (0xff000000 - PAGE_SIZE) +#define FIXADDR_TOP ((unsigned long)(-PAGE_SIZE)) #endif #define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) diff --git a/arch/sh/include/asm/pgtable_64.h b/arch/sh/include/asm/pgtable_64.h index 42cb9dd..dda8c82 100644 --- a/arch/sh/include/asm/pgtable_64.h +++ b/arch/sh/include/asm/pgtable_64.h @@ -87,9 +87,6 @@ static __inline__ void set_pte(pte_t *pteptr, pte_t pteval) #define pte_unmap(pte) do { } while (0) #ifndef __ASSEMBLY__ -#define IOBASE_VADDR 0xff000000 -#define IOBASE_END 0xffffffff - /* * PTEL coherent flags. * See Chapter 17 ST50 CPU Core Volume 1, Architecture. diff --git a/arch/sh/mm/fault_64.c b/arch/sh/mm/fault_64.c index 44a3410..33a9219 100644 --- a/arch/sh/mm/fault_64.c +++ b/arch/sh/mm/fault_64.c @@ -246,8 +246,7 @@ asmlinkage int do_fast_page_fault(unsigned long long ssr_md, tsk = current; mm = tsk->mm; - if ((address >= VMALLOC_START && address < VMALLOC_END) || - (address >= IOBASE_VADDR && address < IOBASE_END)) { + if ((address >= VMALLOC_START && address < VMALLOC_END)) { if (ssr_md) /* * Process-contexts can never have this address -- cgit v0.10.2 From 28080329ede3e4110bb14306b4529a5b9a2ce163 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 14 May 2012 15:33:28 +0900 Subject: sh: Enable shared page fault handler for _32/_64. This moves the now generic _32 page fault handling code to a shared place and adapts the _64 implementation to make use of it. Signed-off-by: Paul Mundt diff --git a/arch/sh/mm/Makefile b/arch/sh/mm/Makefile index 2228c8c..ba81910 100644 --- a/arch/sh/mm/Makefile +++ b/arch/sh/mm/Makefile @@ -15,8 +15,8 @@ cacheops-$(CONFIG_CPU_SHX3) += cache-shx3.o obj-y += $(cacheops-y) mmu-y := nommu.o extable_32.o -mmu-$(CONFIG_MMU) := extable_$(BITS).o fault_$(BITS).o gup.o \ - ioremap.o kmap.o pgtable.o tlbflush_$(BITS).o +mmu-$(CONFIG_MMU) := extable_$(BITS).o fault.o gup.o ioremap.o kmap.o \ + pgtable.o tlbex_$(BITS).o tlbflush_$(BITS).o obj-y += $(mmu-y) diff --git a/arch/sh/mm/fault.c b/arch/sh/mm/fault.c new file mode 100644 index 0000000..16799f9 --- /dev/null +++ b/arch/sh/mm/fault.c @@ -0,0 +1,508 @@ +/* + * Page fault handler for SH with an MMU. + * + * Copyright (C) 1999 Niibe Yutaka + * Copyright (C) 2003 - 2012 Paul Mundt + * + * Based on linux/arch/i386/mm/fault.c: + * Copyright (C) 1995 Linus Torvalds + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static inline int notify_page_fault(struct pt_regs *regs, int trap) +{ + int ret = 0; + + if (kprobes_built_in() && !user_mode(regs)) { + preempt_disable(); + if (kprobe_running() && kprobe_fault_handler(regs, trap)) + ret = 1; + preempt_enable(); + } + + return ret; +} + +static void +force_sig_info_fault(int si_signo, int si_code, unsigned long address, + struct task_struct *tsk) +{ + siginfo_t info; + + info.si_signo = si_signo; + info.si_errno = 0; + info.si_code = si_code; + info.si_addr = (void __user *)address; + + force_sig_info(si_signo, &info, tsk); +} + +/* + * This is useful to dump out the page tables associated with + * 'addr' in mm 'mm'. + */ +static void show_pte(struct mm_struct *mm, unsigned long addr) +{ + pgd_t *pgd; + + if (mm) + pgd = mm->pgd; + else + pgd = get_TTB(); + + printk(KERN_ALERT "pgd = %p\n", pgd); + pgd += pgd_index(addr); + printk(KERN_ALERT "[%08lx] *pgd=%0*Lx", addr, + (u32)(sizeof(*pgd) * 2), (u64)pgd_val(*pgd)); + + do { + pud_t *pud; + pmd_t *pmd; + pte_t *pte; + + if (pgd_none(*pgd)) + break; + + if (pgd_bad(*pgd)) { + printk("(bad)"); + break; + } + + pud = pud_offset(pgd, addr); + if (PTRS_PER_PUD != 1) + printk(", *pud=%0*Lx", (u32)(sizeof(*pud) * 2), + (u64)pud_val(*pud)); + + if (pud_none(*pud)) + break; + + if (pud_bad(*pud)) { + printk("(bad)"); + break; + } + + pmd = pmd_offset(pud, addr); + if (PTRS_PER_PMD != 1) + printk(", *pmd=%0*Lx", (u32)(sizeof(*pmd) * 2), + (u64)pmd_val(*pmd)); + + if (pmd_none(*pmd)) + break; + + if (pmd_bad(*pmd)) { + printk("(bad)"); + break; + } + + /* We must not map this if we have highmem enabled */ + if (PageHighMem(pfn_to_page(pmd_val(*pmd) >> PAGE_SHIFT))) + break; + + pte = pte_offset_kernel(pmd, addr); + printk(", *pte=%0*Lx", (u32)(sizeof(*pte) * 2), + (u64)pte_val(*pte)); + } while (0); + + printk("\n"); +} + +static inline pmd_t *vmalloc_sync_one(pgd_t *pgd, unsigned long address) +{ + unsigned index = pgd_index(address); + pgd_t *pgd_k; + pud_t *pud, *pud_k; + pmd_t *pmd, *pmd_k; + + pgd += index; + pgd_k = init_mm.pgd + index; + + if (!pgd_present(*pgd_k)) + return NULL; + + pud = pud_offset(pgd, address); + pud_k = pud_offset(pgd_k, address); + if (!pud_present(*pud_k)) + return NULL; + + if (!pud_present(*pud)) + set_pud(pud, *pud_k); + + pmd = pmd_offset(pud, address); + pmd_k = pmd_offset(pud_k, address); + if (!pmd_present(*pmd_k)) + return NULL; + + if (!pmd_present(*pmd)) + set_pmd(pmd, *pmd_k); + else { + /* + * The page tables are fully synchronised so there must + * be another reason for the fault. Return NULL here to + * signal that we have not taken care of the fault. + */ + BUG_ON(pmd_page(*pmd) != pmd_page(*pmd_k)); + return NULL; + } + + return pmd_k; +} + +/* + * Handle a fault on the vmalloc or module mapping area + */ +static noinline int vmalloc_fault(unsigned long address) +{ + pgd_t *pgd_k; + pmd_t *pmd_k; + pte_t *pte_k; + + /* Make sure we are in vmalloc/module area: */ + if (!is_vmalloc_addr((void *)address)) + return -1; + + /* + * Synchronize this task's top level page-table + * with the 'reference' page table. + * + * Do _not_ use "current" here. We might be inside + * an interrupt in the middle of a task switch.. + */ + pgd_k = get_TTB(); + pmd_k = vmalloc_sync_one(pgd_k, address); + if (!pmd_k) + return -1; + + pte_k = pte_offset_kernel(pmd_k, address); + if (!pte_present(*pte_k)) + return -1; + + return 0; +} + +static void +show_fault_oops(struct pt_regs *regs, unsigned long address) +{ + if (!oops_may_print()) + return; + + printk(KERN_ALERT "BUG: unable to handle kernel "); + if (address < PAGE_SIZE) + printk(KERN_CONT "NULL pointer dereference"); + else + printk(KERN_CONT "paging request"); + + printk(KERN_CONT " at %08lx\n", address); + printk(KERN_ALERT "PC:"); + printk_address(regs->pc, 1); + + show_pte(NULL, address); +} + +static noinline void +no_context(struct pt_regs *regs, unsigned long error_code, + unsigned long address) +{ + /* Are we prepared to handle this kernel fault? */ + if (fixup_exception(regs)) + return; + + if (handle_trapped_io(regs, address)) + return; + + /* + * Oops. The kernel tried to access some bad page. We'll have to + * terminate things with extreme prejudice. + */ + bust_spinlocks(1); + + show_fault_oops(regs, address); + + die("Oops", regs, error_code); + bust_spinlocks(0); + do_exit(SIGKILL); +} + +static void +__bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code, + unsigned long address, int si_code) +{ + struct task_struct *tsk = current; + + /* User mode accesses just cause a SIGSEGV */ + if (user_mode(regs)) { + /* + * It's possible to have interrupts off here: + */ + local_irq_enable(); + + force_sig_info_fault(SIGSEGV, si_code, address, tsk); + + return; + } + + no_context(regs, error_code, address); +} + +static noinline void +bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code, + unsigned long address) +{ + __bad_area_nosemaphore(regs, error_code, address, SEGV_MAPERR); +} + +static void +__bad_area(struct pt_regs *regs, unsigned long error_code, + unsigned long address, int si_code) +{ + struct mm_struct *mm = current->mm; + + /* + * Something tried to access memory that isn't in our memory map.. + * Fix it, but check if it's kernel or user first.. + */ + up_read(&mm->mmap_sem); + + __bad_area_nosemaphore(regs, error_code, address, si_code); +} + +static noinline void +bad_area(struct pt_regs *regs, unsigned long error_code, unsigned long address) +{ + __bad_area(regs, error_code, address, SEGV_MAPERR); +} + +static noinline void +bad_area_access_error(struct pt_regs *regs, unsigned long error_code, + unsigned long address) +{ + __bad_area(regs, error_code, address, SEGV_ACCERR); +} + +static void out_of_memory(void) +{ + /* + * We ran out of memory, call the OOM killer, and return the userspace + * (which will retry the fault, or kill us if we got oom-killed): + */ + up_read(¤t->mm->mmap_sem); + + pagefault_out_of_memory(); +} + +static void +do_sigbus(struct pt_regs *regs, unsigned long error_code, unsigned long address) +{ + struct task_struct *tsk = current; + struct mm_struct *mm = tsk->mm; + + up_read(&mm->mmap_sem); + + /* Kernel mode? Handle exceptions or die: */ + if (!user_mode(regs)) + no_context(regs, error_code, address); + + force_sig_info_fault(SIGBUS, BUS_ADRERR, address, tsk); +} + +static noinline int +mm_fault_error(struct pt_regs *regs, unsigned long error_code, + unsigned long address, unsigned int fault) +{ + /* + * Pagefault was interrupted by SIGKILL. We have no reason to + * continue pagefault. + */ + if (fatal_signal_pending(current)) { + if (!(fault & VM_FAULT_RETRY)) + up_read(¤t->mm->mmap_sem); + if (!user_mode(regs)) + no_context(regs, error_code, address); + return 1; + } + + if (!(fault & VM_FAULT_ERROR)) + return 0; + + if (fault & VM_FAULT_OOM) { + /* Kernel mode? Handle exceptions or die: */ + if (!user_mode(regs)) { + up_read(¤t->mm->mmap_sem); + no_context(regs, error_code, address); + return 1; + } + + out_of_memory(); + } else { + if (fault & VM_FAULT_SIGBUS) + do_sigbus(regs, error_code, address); + else + BUG(); + } + + return 1; +} + +static inline int access_error(int error_code, struct vm_area_struct *vma) +{ + if (error_code & FAULT_CODE_WRITE) { + /* write, present and write, not present: */ + if (unlikely(!(vma->vm_flags & VM_WRITE))) + return 1; + return 0; + } + + /* ITLB miss on NX page */ + if (unlikely((error_code & FAULT_CODE_ITLB) && + !(vma->vm_flags & VM_EXEC))) + return 1; + + /* read, not present: */ + if (unlikely(!(vma->vm_flags & (VM_READ | VM_EXEC | VM_WRITE)))) + return 1; + + return 0; +} + +static int fault_in_kernel_space(unsigned long address) +{ + return address >= TASK_SIZE; +} + +/* + * This routine handles page faults. It determines the address, + * and the problem, and then passes it off to one of the appropriate + * routines. + */ +asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, + unsigned long error_code, + unsigned long address) +{ + unsigned long vec; + struct task_struct *tsk; + struct mm_struct *mm; + struct vm_area_struct * vma; + int fault; + int write = error_code & FAULT_CODE_WRITE; + unsigned int flags = (FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE | + (write ? FAULT_FLAG_WRITE : 0)); + + tsk = current; + mm = tsk->mm; + vec = lookup_exception_vector(); + + /* + * We fault-in kernel-space virtual memory on-demand. The + * 'reference' page table is init_mm.pgd. + * + * NOTE! We MUST NOT take any locks for this case. We may + * be in an interrupt or a critical region, and should + * only copy the information from the master page table, + * nothing more. + */ + if (unlikely(fault_in_kernel_space(address))) { + if (vmalloc_fault(address) >= 0) + return; + if (notify_page_fault(regs, vec)) + return; + + bad_area_nosemaphore(regs, error_code, address); + return; + } + + if (unlikely(notify_page_fault(regs, vec))) + return; + + /* Only enable interrupts if they were on before the fault */ + if ((regs->sr & SR_IMASK) != SR_IMASK) + local_irq_enable(); + + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address); + + /* + * If we're in an interrupt, have no user context or are running + * in an atomic region then we must not take the fault: + */ + if (unlikely(in_atomic() || !mm)) { + bad_area_nosemaphore(regs, error_code, address); + return; + } + +retry: + down_read(&mm->mmap_sem); + + vma = find_vma(mm, address); + if (unlikely(!vma)) { + bad_area(regs, error_code, address); + return; + } + if (likely(vma->vm_start <= address)) + goto good_area; + if (unlikely(!(vma->vm_flags & VM_GROWSDOWN))) { + bad_area(regs, error_code, address); + return; + } + if (unlikely(expand_stack(vma, address))) { + bad_area(regs, error_code, address); + return; + } + + /* + * Ok, we have a good vm_area for this memory access, so + * we can handle it.. + */ +good_area: + if (unlikely(access_error(error_code, vma))) { + bad_area_access_error(regs, error_code, address); + return; + } + + set_thread_fault_code(error_code); + + /* + * If for any reason at all we couldn't handle the fault, + * make sure we exit gracefully rather than endlessly redo + * the fault. + */ + fault = handle_mm_fault(mm, vma, address, flags); + + if (unlikely(fault & (VM_FAULT_RETRY | VM_FAULT_ERROR))) + if (mm_fault_error(regs, error_code, address, fault)) + return; + + if (flags & FAULT_FLAG_ALLOW_RETRY) { + if (fault & VM_FAULT_MAJOR) { + tsk->maj_flt++; + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, + regs, address); + } else { + tsk->min_flt++; + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, + regs, address); + } + if (fault & VM_FAULT_RETRY) { + flags &= ~FAULT_FLAG_ALLOW_RETRY; + + /* + * No need to up_read(&mm->mmap_sem) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ + goto retry; + } + } + + up_read(&mm->mmap_sem); +} diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c deleted file mode 100644 index 39e291c..0000000 --- a/arch/sh/mm/fault_32.c +++ /dev/null @@ -1,564 +0,0 @@ -/* - * Page fault handler for SH with an MMU. - * - * Copyright (C) 1999 Niibe Yutaka - * Copyright (C) 2003 - 2012 Paul Mundt - * - * Based on linux/arch/i386/mm/fault.c: - * Copyright (C) 1995 Linus Torvalds - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static inline int notify_page_fault(struct pt_regs *regs, int trap) -{ - int ret = 0; - - if (kprobes_built_in() && !user_mode(regs)) { - preempt_disable(); - if (kprobe_running() && kprobe_fault_handler(regs, trap)) - ret = 1; - preempt_enable(); - } - - return ret; -} - -static void -force_sig_info_fault(int si_signo, int si_code, unsigned long address, - struct task_struct *tsk) -{ - siginfo_t info; - - info.si_signo = si_signo; - info.si_errno = 0; - info.si_code = si_code; - info.si_addr = (void __user *)address; - - force_sig_info(si_signo, &info, tsk); -} - -/* - * This is useful to dump out the page tables associated with - * 'addr' in mm 'mm'. - */ -static void show_pte(struct mm_struct *mm, unsigned long addr) -{ - pgd_t *pgd; - - if (mm) - pgd = mm->pgd; - else - pgd = get_TTB(); - - printk(KERN_ALERT "pgd = %p\n", pgd); - pgd += pgd_index(addr); - printk(KERN_ALERT "[%08lx] *pgd=%0*Lx", addr, - sizeof(*pgd) * 2, (u64)pgd_val(*pgd)); - - do { - pud_t *pud; - pmd_t *pmd; - pte_t *pte; - - if (pgd_none(*pgd)) - break; - - if (pgd_bad(*pgd)) { - printk("(bad)"); - break; - } - - pud = pud_offset(pgd, addr); - if (PTRS_PER_PUD != 1) - printk(", *pud=%0*Lx", sizeof(*pud) * 2, - (u64)pud_val(*pud)); - - if (pud_none(*pud)) - break; - - if (pud_bad(*pud)) { - printk("(bad)"); - break; - } - - pmd = pmd_offset(pud, addr); - if (PTRS_PER_PMD != 1) - printk(", *pmd=%0*Lx", sizeof(*pmd) * 2, - (u64)pmd_val(*pmd)); - - if (pmd_none(*pmd)) - break; - - if (pmd_bad(*pmd)) { - printk("(bad)"); - break; - } - - /* We must not map this if we have highmem enabled */ - if (PageHighMem(pfn_to_page(pmd_val(*pmd) >> PAGE_SHIFT))) - break; - - pte = pte_offset_kernel(pmd, addr); - printk(", *pte=%0*Lx", sizeof(*pte) * 2, (u64)pte_val(*pte)); - } while (0); - - printk("\n"); -} - -static inline pmd_t *vmalloc_sync_one(pgd_t *pgd, unsigned long address) -{ - unsigned index = pgd_index(address); - pgd_t *pgd_k; - pud_t *pud, *pud_k; - pmd_t *pmd, *pmd_k; - - pgd += index; - pgd_k = init_mm.pgd + index; - - if (!pgd_present(*pgd_k)) - return NULL; - - pud = pud_offset(pgd, address); - pud_k = pud_offset(pgd_k, address); - if (!pud_present(*pud_k)) - return NULL; - - if (!pud_present(*pud)) - set_pud(pud, *pud_k); - - pmd = pmd_offset(pud, address); - pmd_k = pmd_offset(pud_k, address); - if (!pmd_present(*pmd_k)) - return NULL; - - if (!pmd_present(*pmd)) - set_pmd(pmd, *pmd_k); - else { - /* - * The page tables are fully synchronised so there must - * be another reason for the fault. Return NULL here to - * signal that we have not taken care of the fault. - */ - BUG_ON(pmd_page(*pmd) != pmd_page(*pmd_k)); - return NULL; - } - - return pmd_k; -} - -/* - * Handle a fault on the vmalloc or module mapping area - */ -static noinline int vmalloc_fault(unsigned long address) -{ - pgd_t *pgd_k; - pmd_t *pmd_k; - pte_t *pte_k; - - /* Make sure we are in vmalloc/module area: */ - if (!is_vmalloc_addr((void *)address)) - return -1; - - /* - * Synchronize this task's top level page-table - * with the 'reference' page table. - * - * Do _not_ use "current" here. We might be inside - * an interrupt in the middle of a task switch.. - */ - pgd_k = get_TTB(); - pmd_k = vmalloc_sync_one(pgd_k, address); - if (!pmd_k) - return -1; - - pte_k = pte_offset_kernel(pmd_k, address); - if (!pte_present(*pte_k)) - return -1; - - return 0; -} - -static void -show_fault_oops(struct pt_regs *regs, unsigned long address) -{ - if (!oops_may_print()) - return; - - printk(KERN_ALERT "BUG: unable to handle kernel "); - if (address < PAGE_SIZE) - printk(KERN_CONT "NULL pointer dereference"); - else - printk(KERN_CONT "paging request"); - - printk(KERN_CONT " at %08lx\n", address); - printk(KERN_ALERT "PC:"); - printk_address(regs->pc, 1); - - show_pte(NULL, address); -} - -static noinline void -no_context(struct pt_regs *regs, unsigned long error_code, - unsigned long address) -{ - /* Are we prepared to handle this kernel fault? */ - if (fixup_exception(regs)) - return; - - if (handle_trapped_io(regs, address)) - return; - - /* - * Oops. The kernel tried to access some bad page. We'll have to - * terminate things with extreme prejudice. - */ - bust_spinlocks(1); - - show_fault_oops(regs, address); - - die("Oops", regs, error_code); - bust_spinlocks(0); - do_exit(SIGKILL); -} - -static void -__bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code, - unsigned long address, int si_code) -{ - struct task_struct *tsk = current; - - /* User mode accesses just cause a SIGSEGV */ - if (user_mode(regs)) { - /* - * It's possible to have interrupts off here: - */ - local_irq_enable(); - - force_sig_info_fault(SIGSEGV, si_code, address, tsk); - - return; - } - - no_context(regs, error_code, address); -} - -static noinline void -bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code, - unsigned long address) -{ - __bad_area_nosemaphore(regs, error_code, address, SEGV_MAPERR); -} - -static void -__bad_area(struct pt_regs *regs, unsigned long error_code, - unsigned long address, int si_code) -{ - struct mm_struct *mm = current->mm; - - /* - * Something tried to access memory that isn't in our memory map.. - * Fix it, but check if it's kernel or user first.. - */ - up_read(&mm->mmap_sem); - - __bad_area_nosemaphore(regs, error_code, address, si_code); -} - -static noinline void -bad_area(struct pt_regs *regs, unsigned long error_code, unsigned long address) -{ - __bad_area(regs, error_code, address, SEGV_MAPERR); -} - -static noinline void -bad_area_access_error(struct pt_regs *regs, unsigned long error_code, - unsigned long address) -{ - __bad_area(regs, error_code, address, SEGV_ACCERR); -} - -static void out_of_memory(void) -{ - /* - * We ran out of memory, call the OOM killer, and return the userspace - * (which will retry the fault, or kill us if we got oom-killed): - */ - up_read(¤t->mm->mmap_sem); - - pagefault_out_of_memory(); -} - -static void -do_sigbus(struct pt_regs *regs, unsigned long error_code, unsigned long address) -{ - struct task_struct *tsk = current; - struct mm_struct *mm = tsk->mm; - - up_read(&mm->mmap_sem); - - /* Kernel mode? Handle exceptions or die: */ - if (!user_mode(regs)) - no_context(regs, error_code, address); - - force_sig_info_fault(SIGBUS, BUS_ADRERR, address, tsk); -} - -static noinline int -mm_fault_error(struct pt_regs *regs, unsigned long error_code, - unsigned long address, unsigned int fault) -{ - /* - * Pagefault was interrupted by SIGKILL. We have no reason to - * continue pagefault. - */ - if (fatal_signal_pending(current)) { - if (!(fault & VM_FAULT_RETRY)) - up_read(¤t->mm->mmap_sem); - if (!user_mode(regs)) - no_context(regs, error_code, address); - return 1; - } - - if (!(fault & VM_FAULT_ERROR)) - return 0; - - if (fault & VM_FAULT_OOM) { - /* Kernel mode? Handle exceptions or die: */ - if (!user_mode(regs)) { - up_read(¤t->mm->mmap_sem); - no_context(regs, error_code, address); - return 1; - } - - out_of_memory(); - } else { - if (fault & VM_FAULT_SIGBUS) - do_sigbus(regs, error_code, address); - else - BUG(); - } - - return 1; -} - -static inline int access_error(int write, struct vm_area_struct *vma) -{ - if (write) { - /* write, present and write, not present: */ - if (unlikely(!(vma->vm_flags & VM_WRITE))) - return 1; - return 0; - } - - /* read, not present: */ - if (unlikely(!(vma->vm_flags & (VM_READ | VM_EXEC | VM_WRITE)))) - return 1; - - return 0; -} - -static int fault_in_kernel_space(unsigned long address) -{ - return address >= TASK_SIZE; -} - -/* - * This routine handles page faults. It determines the address, - * and the problem, and then passes it off to one of the appropriate - * routines. - */ -asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, - unsigned long error_code, - unsigned long address) -{ - unsigned long vec; - struct task_struct *tsk; - struct mm_struct *mm; - struct vm_area_struct * vma; - int fault; - int write = error_code & FAULT_CODE_WRITE; - unsigned int flags = (FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE | - (write ? FAULT_FLAG_WRITE : 0)); - - tsk = current; - mm = tsk->mm; - vec = lookup_exception_vector(); - - /* - * We fault-in kernel-space virtual memory on-demand. The - * 'reference' page table is init_mm.pgd. - * - * NOTE! We MUST NOT take any locks for this case. We may - * be in an interrupt or a critical region, and should - * only copy the information from the master page table, - * nothing more. - */ - if (unlikely(fault_in_kernel_space(address))) { - if (vmalloc_fault(address) >= 0) - return; - if (notify_page_fault(regs, vec)) - return; - - bad_area_nosemaphore(regs, error_code, address); - return; - } - - if (unlikely(notify_page_fault(regs, vec))) - return; - - /* Only enable interrupts if they were on before the fault */ - if ((regs->sr & SR_IMASK) != SR_IMASK) - local_irq_enable(); - - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address); - - /* - * If we're in an interrupt, have no user context or are running - * in an atomic region then we must not take the fault: - */ - if (unlikely(in_atomic() || !mm)) { - bad_area_nosemaphore(regs, error_code, address); - return; - } - -retry: - down_read(&mm->mmap_sem); - - vma = find_vma(mm, address); - if (unlikely(!vma)) { - bad_area(regs, error_code, address); - return; - } - if (likely(vma->vm_start <= address)) - goto good_area; - if (unlikely(!(vma->vm_flags & VM_GROWSDOWN))) { - bad_area(regs, error_code, address); - return; - } - if (unlikely(expand_stack(vma, address))) { - bad_area(regs, error_code, address); - return; - } - - /* - * Ok, we have a good vm_area for this memory access, so - * we can handle it.. - */ -good_area: - if (unlikely(access_error(error_code, vma))) { - bad_area_access_error(regs, error_code, address); - return; - } - - set_thread_fault_code(error_code); - - /* - * If for any reason at all we couldn't handle the fault, - * make sure we exit gracefully rather than endlessly redo - * the fault. - */ - fault = handle_mm_fault(mm, vma, address, flags); - - if (unlikely(fault & (VM_FAULT_RETRY | VM_FAULT_ERROR))) - if (mm_fault_error(regs, error_code, address, fault)) - return; - - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_MAJOR) { - tsk->maj_flt++; - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, - regs, address); - } else { - tsk->min_flt++; - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, - regs, address); - } - if (fault & VM_FAULT_RETRY) { - flags &= ~FAULT_FLAG_ALLOW_RETRY; - - /* - * No need to up_read(&mm->mmap_sem) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ - goto retry; - } - } - - up_read(&mm->mmap_sem); -} - -/* - * Called with interrupts disabled. - */ -asmlinkage int __kprobes -handle_tlbmiss(struct pt_regs *regs, unsigned long error_code, - unsigned long address) -{ - pgd_t *pgd; - pud_t *pud; - pmd_t *pmd; - pte_t *pte; - pte_t entry; - - /* - * We don't take page faults for P1, P2, and parts of P4, these - * are always mapped, whether it be due to legacy behaviour in - * 29-bit mode, or due to PMB configuration in 32-bit mode. - */ - if (address >= P3SEG && address < P3_ADDR_MAX) { - pgd = pgd_offset_k(address); - } else { - if (unlikely(address >= TASK_SIZE || !current->mm)) - return 1; - - pgd = pgd_offset(current->mm, address); - } - - pud = pud_offset(pgd, address); - if (pud_none_or_clear_bad(pud)) - return 1; - pmd = pmd_offset(pud, address); - if (pmd_none_or_clear_bad(pmd)) - return 1; - pte = pte_offset_kernel(pmd, address); - entry = *pte; - if (unlikely(pte_none(entry) || pte_not_present(entry))) - return 1; - if (unlikely(error_code && !pte_write(entry))) - return 1; - - if (error_code) - entry = pte_mkdirty(entry); - entry = pte_mkyoung(entry); - - set_pte(pte, entry); - -#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SMP) - /* - * SH-4 does not set MMUCR.RC to the corresponding TLB entry in - * the case of an initial page write exception, so we need to - * flush it in order to avoid potential TLB entry duplication. - */ - if (error_code == FAULT_CODE_INITIAL) - local_flush_tlb_one(get_asid(), address & PAGE_MASK); -#endif - - set_thread_fault_code(error_code); - update_mmu_cache(NULL, address, pte); - - return 0; -} diff --git a/arch/sh/mm/fault_64.c b/arch/sh/mm/fault_64.c deleted file mode 100644 index 33a9219..0000000 --- a/arch/sh/mm/fault_64.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - * The SH64 TLB miss. - * - * Original code from fault.c - * Copyright (C) 2000, 2001 Paolo Alberelli - * - * Fast PTE->TLB refill path - * Copyright (C) 2003 Richard.Curnow@superh.com - * - * IMPORTANT NOTES : - * The do_fast_page_fault function is called from a context in entry.S - * where very few registers have been saved. In particular, the code in - * this file must be compiled not to use ANY caller-save registers that - * are not part of the restricted save set. Also, it means that code in - * this file must not make calls to functions elsewhere in the kernel, or - * else the excepting context will see corruption in its caller-save - * registers. Plus, the entry.S save area is non-reentrant, so this code - * has to run with SR.BL==1, i.e. no interrupts taken inside it and panic - * on any exception. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Callable from fault.c, so not static */ -inline void __do_tlb_refill(unsigned long address, - unsigned long long is_text_not_data, pte_t *pte) -{ - unsigned long long ptel; - unsigned long long pteh=0; - struct tlb_info *tlbp; - unsigned long long next; - - /* Get PTEL first */ - ptel = pte_val(*pte); - - /* - * Set PTEH register - */ - pteh = neff_sign_extend(address & MMU_VPN_MASK); - - /* Set the ASID. */ - pteh |= get_asid() << PTEH_ASID_SHIFT; - pteh |= PTEH_VALID; - - /* Set PTEL register, set_pte has performed the sign extension */ - ptel &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */ - - tlbp = is_text_not_data ? &(cpu_data->itlb) : &(cpu_data->dtlb); - next = tlbp->next; - __flush_tlb_slot(next); - asm volatile ("putcfg %0,1,%2\n\n\t" - "putcfg %0,0,%1\n" - : : "r" (next), "r" (pteh), "r" (ptel) ); - - next += TLB_STEP; - if (next > tlbp->last) next = tlbp->first; - tlbp->next = next; - -} - -static int handle_vmalloc_fault(struct mm_struct *mm, - unsigned long protection_flags, - unsigned long long textaccess, - unsigned long address) -{ - pgd_t *dir; - pud_t *pud; - pmd_t *pmd; - static pte_t *pte; - pte_t entry; - - dir = pgd_offset_k(address); - - pud = pud_offset(dir, address); - if (pud_none_or_clear_bad(pud)) - return 0; - - pmd = pmd_offset(pud, address); - if (pmd_none_or_clear_bad(pmd)) - return 0; - - pte = pte_offset_kernel(pmd, address); - entry = *pte; - - if (pte_none(entry) || !pte_present(entry)) - return 0; - if ((pte_val(entry) & protection_flags) != protection_flags) - return 0; - - __do_tlb_refill(address, textaccess, pte); - - return 1; -} - -static int handle_tlbmiss(struct mm_struct *mm, - unsigned long long protection_flags, - unsigned long long textaccess, - unsigned long address) -{ - pgd_t *dir; - pud_t *pud; - pmd_t *pmd; - pte_t *pte; - pte_t entry; - - /* NB. The PGD currently only contains a single entry - there is no - page table tree stored for the top half of the address space since - virtual pages in that region should never be mapped in user mode. - (In kernel mode, the only things in that region are the 512Mb super - page (locked in), and vmalloc (modules) + I/O device pages (handled - by handle_vmalloc_fault), so no PGD for the upper half is required - by kernel mode either). - - See how mm->pgd is allocated and initialised in pgd_alloc to see why - the next test is necessary. - RPC */ - if (address >= (unsigned long) TASK_SIZE) - /* upper half - never has page table entries. */ - return 0; - - dir = pgd_offset(mm, address); - if (pgd_none(*dir) || !pgd_present(*dir)) - return 0; - if (!pgd_present(*dir)) - return 0; - - pud = pud_offset(dir, address); - if (pud_none(*pud) || !pud_present(*pud)) - return 0; - - pmd = pmd_offset(pud, address); - if (pmd_none(*pmd) || !pmd_present(*pmd)) - return 0; - - pte = pte_offset_kernel(pmd, address); - entry = *pte; - - if (pte_none(entry) || !pte_present(entry)) - return 0; - - /* - * If the page doesn't have sufficient protection bits set to - * service the kind of fault being handled, there's not much - * point doing the TLB refill. Punt the fault to the general - * handler. - */ - if ((pte_val(entry) & protection_flags) != protection_flags) - return 0; - - __do_tlb_refill(address, textaccess, pte); - - return 1; -} - -/* - * Put all this information into one structure so that everything is just - * arithmetic relative to a single base address. This reduces the number - * of movi/shori pairs needed just to load addresses of static data. - */ -struct expevt_lookup { - unsigned short protection_flags[8]; - unsigned char is_text_access[8]; - unsigned char is_write_access[8]; -}; - -#define PRU (1<<9) -#define PRW (1<<8) -#define PRX (1<<7) -#define PRR (1<<6) - -#define DIRTY (_PAGE_DIRTY | _PAGE_ACCESSED) -#define YOUNG (_PAGE_ACCESSED) - -/* Sized as 8 rather than 4 to allow checking the PTE's PRU bit against whether - the fault happened in user mode or privileged mode. */ -static struct expevt_lookup expevt_lookup_table = { - .protection_flags = {PRX, PRX, 0, 0, PRR, PRR, PRW, PRW}, - .is_text_access = {1, 1, 0, 0, 0, 0, 0, 0} -}; - -/* - This routine handles page faults that can be serviced just by refilling a - TLB entry from an existing page table entry. (This case represents a very - large majority of page faults.) Return 1 if the fault was successfully - handled. Return 0 if the fault could not be handled. (This leads into the - general fault handling in fault.c which deals with mapping file-backed - pages, stack growth, segmentation faults, swapping etc etc) - */ -asmlinkage int do_fast_page_fault(unsigned long long ssr_md, - unsigned long long expevt, - unsigned long address) -{ - struct task_struct *tsk; - struct mm_struct *mm; - unsigned long long textaccess; - unsigned long long protection_flags; - unsigned long long index; - unsigned long long expevt4; - - /* The next few lines implement a way of hashing EXPEVT into a - * small array index which can be used to lookup parameters - * specific to the type of TLBMISS being handled. - * - * Note: - * ITLBMISS has EXPEVT==0xa40 - * RTLBMISS has EXPEVT==0x040 - * WTLBMISS has EXPEVT==0x060 - */ - expevt4 = (expevt >> 4); - /* TODO : xor ssr_md into this expression too. Then we can check - * that PRU is set when it needs to be. */ - index = expevt4 ^ (expevt4 >> 5); - index &= 7; - protection_flags = expevt_lookup_table.protection_flags[index]; - textaccess = expevt_lookup_table.is_text_access[index]; - - /* SIM - * Note this is now called with interrupts still disabled - * This is to cope with being called for a missing IO port - * address with interrupts disabled. This should be fixed as - * soon as we have a better 'fast path' miss handler. - * - * Plus take care how you try and debug this stuff. - * For example, writing debug data to a port which you - * have just faulted on is not going to work. - */ - - tsk = current; - mm = tsk->mm; - - if ((address >= VMALLOC_START && address < VMALLOC_END)) { - if (ssr_md) - /* - * Process-contexts can never have this address - * range mapped - */ - if (handle_vmalloc_fault(mm, protection_flags, - textaccess, address)) - return 1; - } else if (!in_interrupt() && mm) { - if (handle_tlbmiss(mm, protection_flags, textaccess, address)) - return 1; - } - - return 0; -} diff --git a/arch/sh/mm/tlbex_32.c b/arch/sh/mm/tlbex_32.c new file mode 100644 index 0000000..382262d --- /dev/null +++ b/arch/sh/mm/tlbex_32.c @@ -0,0 +1,78 @@ +/* + * TLB miss handler for SH with an MMU. + * + * Copyright (C) 1999 Niibe Yutaka + * Copyright (C) 2003 - 2012 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include + +/* + * Called with interrupts disabled. + */ +asmlinkage int __kprobes +handle_tlbmiss(struct pt_regs *regs, unsigned long error_code, + unsigned long address) +{ + pgd_t *pgd; + pud_t *pud; + pmd_t *pmd; + pte_t *pte; + pte_t entry; + + /* + * We don't take page faults for P1, P2, and parts of P4, these + * are always mapped, whether it be due to legacy behaviour in + * 29-bit mode, or due to PMB configuration in 32-bit mode. + */ + if (address >= P3SEG && address < P3_ADDR_MAX) { + pgd = pgd_offset_k(address); + } else { + if (unlikely(address >= TASK_SIZE || !current->mm)) + return 1; + + pgd = pgd_offset(current->mm, address); + } + + pud = pud_offset(pgd, address); + if (pud_none_or_clear_bad(pud)) + return 1; + pmd = pmd_offset(pud, address); + if (pmd_none_or_clear_bad(pmd)) + return 1; + pte = pte_offset_kernel(pmd, address); + entry = *pte; + if (unlikely(pte_none(entry) || pte_not_present(entry))) + return 1; + if (unlikely(error_code && !pte_write(entry))) + return 1; + + if (error_code) + entry = pte_mkdirty(entry); + entry = pte_mkyoung(entry); + + set_pte(pte, entry); + +#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SMP) + /* + * SH-4 does not set MMUCR.RC to the corresponding TLB entry in + * the case of an initial page write exception, so we need to + * flush it in order to avoid potential TLB entry duplication. + */ + if (error_code == FAULT_CODE_INITIAL) + local_flush_tlb_one(get_asid(), address & PAGE_MASK); +#endif + + set_thread_fault_code(error_code); + update_mmu_cache(NULL, address, pte); + + return 0; +} diff --git a/arch/sh/mm/tlbex_64.c b/arch/sh/mm/tlbex_64.c new file mode 100644 index 0000000..d15b994 --- /dev/null +++ b/arch/sh/mm/tlbex_64.c @@ -0,0 +1,264 @@ +/* + * The SH64 TLB miss. + * + * Original code from fault.c + * Copyright (C) 2000, 2001 Paolo Alberelli + * + * Fast PTE->TLB refill path + * Copyright (C) 2003 Richard.Curnow@superh.com + * + * IMPORTANT NOTES : + * The do_fast_page_fault function is called from a context in entry.S + * where very few registers have been saved. In particular, the code in + * this file must be compiled not to use ANY caller-save registers that + * are not part of the restricted save set. Also, it means that code in + * this file must not make calls to functions elsewhere in the kernel, or + * else the excepting context will see corruption in its caller-save + * registers. Plus, the entry.S save area is non-reentrant, so this code + * has to run with SR.BL==1, i.e. no interrupts taken inside it and panic + * on any exception. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Callable from fault.c, so not static */ +inline void __do_tlb_refill(unsigned long address, + unsigned long long is_text_not_data, pte_t *pte) +{ + unsigned long long ptel; + unsigned long long pteh=0; + struct tlb_info *tlbp; + unsigned long long next; + + /* Get PTEL first */ + ptel = pte_val(*pte); + + /* + * Set PTEH register + */ + pteh = neff_sign_extend(address & MMU_VPN_MASK); + + /* Set the ASID. */ + pteh |= get_asid() << PTEH_ASID_SHIFT; + pteh |= PTEH_VALID; + + /* Set PTEL register, set_pte has performed the sign extension */ + ptel &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */ + + tlbp = is_text_not_data ? &(cpu_data->itlb) : &(cpu_data->dtlb); + next = tlbp->next; + __flush_tlb_slot(next); + asm volatile ("putcfg %0,1,%2\n\n\t" + "putcfg %0,0,%1\n" + : : "r" (next), "r" (pteh), "r" (ptel) ); + + next += TLB_STEP; + if (next > tlbp->last) next = tlbp->first; + tlbp->next = next; + +} + +static int handle_vmalloc_fault(struct mm_struct *mm, + unsigned long protection_flags, + unsigned long long textaccess, + unsigned long address) +{ + pgd_t *dir; + pud_t *pud; + pmd_t *pmd; + static pte_t *pte; + pte_t entry; + + dir = pgd_offset_k(address); + + pud = pud_offset(dir, address); + if (pud_none_or_clear_bad(pud)) + return 0; + + pmd = pmd_offset(pud, address); + if (pmd_none_or_clear_bad(pmd)) + return 0; + + pte = pte_offset_kernel(pmd, address); + entry = *pte; + + if (pte_none(entry) || !pte_present(entry)) + return 0; + if ((pte_val(entry) & protection_flags) != protection_flags) + return 0; + + __do_tlb_refill(address, textaccess, pte); + + return 1; +} + +static int handle_tlbmiss(struct mm_struct *mm, + unsigned long long protection_flags, + unsigned long long textaccess, + unsigned long address) +{ + pgd_t *dir; + pud_t *pud; + pmd_t *pmd; + pte_t *pte; + pte_t entry; + + /* NB. The PGD currently only contains a single entry - there is no + page table tree stored for the top half of the address space since + virtual pages in that region should never be mapped in user mode. + (In kernel mode, the only things in that region are the 512Mb super + page (locked in), and vmalloc (modules) + I/O device pages (handled + by handle_vmalloc_fault), so no PGD for the upper half is required + by kernel mode either). + + See how mm->pgd is allocated and initialised in pgd_alloc to see why + the next test is necessary. - RPC */ + if (address >= (unsigned long) TASK_SIZE) + /* upper half - never has page table entries. */ + return 0; + + dir = pgd_offset(mm, address); + if (pgd_none(*dir) || !pgd_present(*dir)) + return 0; + if (!pgd_present(*dir)) + return 0; + + pud = pud_offset(dir, address); + if (pud_none(*pud) || !pud_present(*pud)) + return 0; + + pmd = pmd_offset(pud, address); + if (pmd_none(*pmd) || !pmd_present(*pmd)) + return 0; + + pte = pte_offset_kernel(pmd, address); + entry = *pte; + + if (pte_none(entry) || !pte_present(entry)) + return 0; + + /* + * If the page doesn't have sufficient protection bits set to + * service the kind of fault being handled, there's not much + * point doing the TLB refill. Punt the fault to the general + * handler. + */ + if ((pte_val(entry) & protection_flags) != protection_flags) + return 0; + + __do_tlb_refill(address, textaccess, pte); + + return 1; +} + +/* + * Put all this information into one structure so that everything is just + * arithmetic relative to a single base address. This reduces the number + * of movi/shori pairs needed just to load addresses of static data. + */ +struct expevt_lookup { + unsigned short protection_flags[8]; + unsigned char is_text_access[8]; + unsigned char is_write_access[8]; +}; + +#define PRU (1<<9) +#define PRW (1<<8) +#define PRX (1<<7) +#define PRR (1<<6) + +#define DIRTY (_PAGE_DIRTY | _PAGE_ACCESSED) +#define YOUNG (_PAGE_ACCESSED) + +/* Sized as 8 rather than 4 to allow checking the PTE's PRU bit against whether + the fault happened in user mode or privileged mode. */ +static struct expevt_lookup expevt_lookup_table = { + .protection_flags = {PRX, PRX, 0, 0, PRR, PRR, PRW, PRW}, + .is_text_access = {1, 1, 0, 0, 0, 0, 0, 0} +}; + +/* + This routine handles page faults that can be serviced just by refilling a + TLB entry from an existing page table entry. (This case represents a very + large majority of page faults.) Return 1 if the fault was successfully + handled. Return 0 if the fault could not be handled. (This leads into the + general fault handling in fault.c which deals with mapping file-backed + pages, stack growth, segmentation faults, swapping etc etc) + */ +asmlinkage int do_fast_page_fault(unsigned long long ssr_md, + unsigned long long expevt, + unsigned long address) +{ + struct task_struct *tsk; + struct mm_struct *mm; + unsigned long long textaccess; + unsigned long long protection_flags; + unsigned long long index; + unsigned long long expevt4; + + /* The next few lines implement a way of hashing EXPEVT into a + * small array index which can be used to lookup parameters + * specific to the type of TLBMISS being handled. + * + * Note: + * ITLBMISS has EXPEVT==0xa40 + * RTLBMISS has EXPEVT==0x040 + * WTLBMISS has EXPEVT==0x060 + */ + expevt4 = (expevt >> 4); + /* TODO : xor ssr_md into this expression too. Then we can check + * that PRU is set when it needs to be. */ + index = expevt4 ^ (expevt4 >> 5); + index &= 7; + protection_flags = expevt_lookup_table.protection_flags[index]; + textaccess = expevt_lookup_table.is_text_access[index]; + + /* SIM + * Note this is now called with interrupts still disabled + * This is to cope with being called for a missing IO port + * address with interrupts disabled. This should be fixed as + * soon as we have a better 'fast path' miss handler. + * + * Plus take care how you try and debug this stuff. + * For example, writing debug data to a port which you + * have just faulted on is not going to work. + */ + + tsk = current; + mm = tsk->mm; + + if (is_vmalloc_addr((void *)address)) { + if (ssr_md) + /* + * Process-contexts can never have this address + * range mapped + */ + if (handle_vmalloc_fault(mm, protection_flags, + textaccess, address)) + return 1; + } else if (!in_interrupt() && mm) { + if (handle_tlbmiss(mm, protection_flags, textaccess, address)) + return 1; + } + + return 0; +} diff --git a/arch/sh/mm/tlbflush_64.c b/arch/sh/mm/tlbflush_64.c index 99c5833..908167b 100644 --- a/arch/sh/mm/tlbflush_64.c +++ b/arch/sh/mm/tlbflush_64.c @@ -28,249 +28,6 @@ #include #include -static pte_t *lookup_pte(struct mm_struct *mm, unsigned long address) -{ - pgd_t *dir; - pud_t *pud; - pmd_t *pmd; - pte_t *pte; - pte_t entry; - - dir = pgd_offset(mm, address); - if (pgd_none(*dir)) - return NULL; - - pud = pud_offset(dir, address); - if (pud_none(*pud)) - return NULL; - - pmd = pmd_offset(pud, address); - if (pmd_none(*pmd)) - return NULL; - - pte = pte_offset_kernel(pmd, address); - entry = *pte; - if (pte_none(entry) || !pte_present(entry)) - return NULL; - - return pte; -} - -/* - * This routine handles page faults. It determines the address, - * and the problem, and then passes it off to one of the appropriate - * routines. - */ -asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code, - unsigned long address) -{ - struct task_struct *tsk; - struct mm_struct *mm; - struct vm_area_struct * vma; - const struct exception_table_entry *fixup; - int write = error_code & FAULT_CODE_WRITE; - int textaccess = error_code & FAULT_CODE_ITLB; - unsigned int flags = (FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE | - (write ? FAULT_FLAG_WRITE : 0)); - pte_t *pte; - int fault; - - /* SIM - * Note this is now called with interrupts still disabled - * This is to cope with being called for a missing IO port - * address with interrupts disabled. This should be fixed as - * soon as we have a better 'fast path' miss handler. - * - * Plus take care how you try and debug this stuff. - * For example, writing debug data to a port which you - * have just faulted on is not going to work. - */ - - tsk = current; - mm = tsk->mm; - - /* Not an IO address, so reenable interrupts */ - local_irq_enable(); - - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address); - - /* - * If we're in an interrupt or have no user - * context, we must not take the fault.. - */ - if (in_atomic() || !mm) - goto no_context; - -retry: - /* TLB misses upon some cache flushes get done under cli() */ - down_read(&mm->mmap_sem); - - vma = find_vma(mm, address); - if (!vma) - goto bad_area; - if (vma->vm_start <= address) - goto good_area; - if (!(vma->vm_flags & VM_GROWSDOWN)) - goto bad_area; - if (expand_stack(vma, address)) - goto bad_area; - -/* - * Ok, we have a good vm_area for this memory access, so - * we can handle it.. - */ -good_area: - if (textaccess) { - if (!(vma->vm_flags & VM_EXEC)) - goto bad_area; - } else { - if (write) { - if (!(vma->vm_flags & VM_WRITE)) - goto bad_area; - } else { - if (!(vma->vm_flags & VM_READ)) - goto bad_area; - } - } - - /* - * If for any reason at all we couldn't handle the fault, - * make sure we exit gracefully rather than endlessly redo - * the fault. - */ - fault = handle_mm_fault(mm, vma, address, flags); - - if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) - return; - - if (unlikely(fault & VM_FAULT_ERROR)) { - if (fault & VM_FAULT_OOM) - goto out_of_memory; - else if (fault & VM_FAULT_SIGBUS) - goto do_sigbus; - BUG(); - } - - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_MAJOR) { - tsk->maj_flt++; - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, - regs, address); - } else { - tsk->min_flt++; - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, - regs, address); - } - - if (fault & VM_FAULT_RETRY) { - flags &= ~FAULT_FLAG_ALLOW_RETRY; - - /* - * No need to up_read(&mm->mmap_sem) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ - goto retry; - } - } - - /* If we get here, the page fault has been handled. Do the TLB refill - now from the newly-setup PTE, to avoid having to fault again right - away on the same instruction. */ - pte = lookup_pte (mm, address); - if (!pte) { - /* From empirical evidence, we can get here, due to - !pte_present(pte). (e.g. if a swap-in occurs, and the page - is swapped back out again before the process that wanted it - gets rescheduled?) */ - goto no_pte; - } - - __do_tlb_refill(address, textaccess, pte); - -no_pte: - - up_read(&mm->mmap_sem); - return; - -/* - * Something tried to access memory that isn't in our memory map.. - * Fix it, but check if it's kernel or user first.. - */ -bad_area: - up_read(&mm->mmap_sem); - - if (user_mode(regs)) { - static int count=0; - siginfo_t info; - if (count < 4) { - /* This is really to help debug faults when starting - * usermode, so only need a few */ - count++; - printk("user mode bad_area address=%08lx pid=%d (%s) pc=%08lx\n", - address, task_pid_nr(current), current->comm, - (unsigned long) regs->pc); - } - if (is_global_init(tsk)) { - panic("INIT had user mode bad_area\n"); - } - tsk->thread.address = address; - info.si_signo = SIGSEGV; - info.si_errno = 0; - info.si_addr = (void *) address; - force_sig_info(SIGSEGV, &info, tsk); - return; - } - -no_context: - /* Are we prepared to handle this kernel fault? */ - fixup = search_exception_tables(regs->pc); - if (fixup) { - regs->pc = fixup->fixup; - return; - } - -/* - * Oops. The kernel tried to access some bad page. We'll have to - * terminate things with extreme prejudice. - * - */ - if (address < PAGE_SIZE) - printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference"); - else - printk(KERN_ALERT "Unable to handle kernel paging request"); - printk(" at virtual address %08lx\n", address); - printk(KERN_ALERT "pc = %08Lx%08Lx\n", regs->pc >> 32, regs->pc & 0xffffffff); - die("Oops", regs, error_code); - do_exit(SIGKILL); - -/* - * We ran out of memory, or some other thing happened to us that made - * us unable to handle the page fault gracefully. - */ -out_of_memory: - up_read(&mm->mmap_sem); - if (!user_mode(regs)) - goto no_context; - pagefault_out_of_memory(); - return; - -do_sigbus: - printk("fault:Do sigbus\n"); - up_read(&mm->mmap_sem); - - /* - * Send a sigbus, regardless of whether we were in kernel - * or user mode. - */ - tsk->thread.address = address; - force_sig(SIGBUS, tsk); - - /* Kernel mode? Handle exceptions or die */ - if (!user_mode(regs)) - goto no_context; -} - void local_flush_tlb_one(unsigned long asid, unsigned long page) { unsigned long long match, pteh=0, lpage; -- cgit v0.10.2 From c06fd28387a3da2cc4763f7f471f735ccdd61b88 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 14 May 2012 15:52:28 +0900 Subject: sh64: Migrate to __update_tlb() API. Now that we have a method for finding out if we're handling an ITLB fault or not without passing it all the way down the chain, it's possible to use the __update_tlb() interface in place of a special __do_tlb_refill(). Signed-off-by: Paul Mundt diff --git a/arch/sh/mm/tlb-sh5.c b/arch/sh/mm/tlb-sh5.c index f27dbe1..3aea25d 100644 --- a/arch/sh/mm/tlb-sh5.c +++ b/arch/sh/mm/tlb-sh5.c @@ -182,3 +182,43 @@ void tlb_unwire_entry(void) local_irq_restore(flags); } + +void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) +{ + unsigned long long ptel; + unsigned long long pteh=0; + struct tlb_info *tlbp; + unsigned long long next; + unsigned int fault_code = get_thread_fault_code(); + + /* Get PTEL first */ + ptel = pte.pte_low; + + /* + * Set PTEH register + */ + pteh = neff_sign_extend(address & MMU_VPN_MASK); + + /* Set the ASID. */ + pteh |= get_asid() << PTEH_ASID_SHIFT; + pteh |= PTEH_VALID; + + /* Set PTEL register, set_pte has performed the sign extension */ + ptel &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */ + + if (fault_code & FAULT_CODE_ITLB) + tlbp = &cpu_data->itlb; + else + tlbp = &cpu_data->dtlb; + + next = tlbp->next; + __flush_tlb_slot(next); + asm volatile ("putcfg %0,1,%2\n\n\t" + "putcfg %0,0,%1\n" + : : "r" (next), "r" (pteh), "r" (ptel) ); + + next += TLB_STEP; + if (next > tlbp->last) + next = tlbp->first; + tlbp->next = next; +} diff --git a/arch/sh/mm/tlbex_64.c b/arch/sh/mm/tlbex_64.c index d15b994..98b6427 100644 --- a/arch/sh/mm/tlbex_64.c +++ b/arch/sh/mm/tlbex_64.c @@ -38,54 +38,15 @@ #include #include #include -#include - -/* Callable from fault.c, so not static */ -inline void __do_tlb_refill(unsigned long address, - unsigned long long is_text_not_data, pte_t *pte) -{ - unsigned long long ptel; - unsigned long long pteh=0; - struct tlb_info *tlbp; - unsigned long long next; - - /* Get PTEL first */ - ptel = pte_val(*pte); - - /* - * Set PTEH register - */ - pteh = neff_sign_extend(address & MMU_VPN_MASK); - - /* Set the ASID. */ - pteh |= get_asid() << PTEH_ASID_SHIFT; - pteh |= PTEH_VALID; - - /* Set PTEL register, set_pte has performed the sign extension */ - ptel &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */ - - tlbp = is_text_not_data ? &(cpu_data->itlb) : &(cpu_data->dtlb); - next = tlbp->next; - __flush_tlb_slot(next); - asm volatile ("putcfg %0,1,%2\n\n\t" - "putcfg %0,0,%1\n" - : : "r" (next), "r" (pteh), "r" (ptel) ); - - next += TLB_STEP; - if (next > tlbp->last) next = tlbp->first; - tlbp->next = next; - -} static int handle_vmalloc_fault(struct mm_struct *mm, unsigned long protection_flags, - unsigned long long textaccess, unsigned long address) { pgd_t *dir; pud_t *pud; pmd_t *pmd; - static pte_t *pte; + pte_t *pte; pte_t entry; dir = pgd_offset_k(address); @@ -106,14 +67,13 @@ static int handle_vmalloc_fault(struct mm_struct *mm, if ((pte_val(entry) & protection_flags) != protection_flags) return 0; - __do_tlb_refill(address, textaccess, pte); + update_mmu_cache(NULL, address, pte); return 1; } static int handle_tlbmiss(struct mm_struct *mm, unsigned long long protection_flags, - unsigned long long textaccess, unsigned long address) { pgd_t *dir; @@ -165,7 +125,7 @@ static int handle_tlbmiss(struct mm_struct *mm, if ((pte_val(entry) & protection_flags) != protection_flags) return 0; - __do_tlb_refill(address, textaccess, pte); + update_mmu_cache(NULL, address, pte); return 1; } @@ -210,7 +170,6 @@ asmlinkage int do_fast_page_fault(unsigned long long ssr_md, { struct task_struct *tsk; struct mm_struct *mm; - unsigned long long textaccess; unsigned long long protection_flags; unsigned long long index; unsigned long long expevt4; @@ -229,8 +188,11 @@ asmlinkage int do_fast_page_fault(unsigned long long ssr_md, * that PRU is set when it needs to be. */ index = expevt4 ^ (expevt4 >> 5); index &= 7; + protection_flags = expevt_lookup_table.protection_flags[index]; - textaccess = expevt_lookup_table.is_text_access[index]; + + if (expevt_lookup_table.is_text_access[index]) + set_thread_fault_code(FAULT_CODE_ITLB); /* SIM * Note this is now called with interrupts still disabled @@ -252,11 +214,10 @@ asmlinkage int do_fast_page_fault(unsigned long long ssr_md, * Process-contexts can never have this address * range mapped */ - if (handle_vmalloc_fault(mm, protection_flags, - textaccess, address)) + if (handle_vmalloc_fault(mm, protection_flags, address)) return 1; } else if (!in_interrupt() && mm) { - if (handle_tlbmiss(mm, protection_flags, textaccess, address)) + if (handle_tlbmiss(mm, protection_flags, address)) return 1; } diff --git a/arch/sh/mm/tlbflush_64.c b/arch/sh/mm/tlbflush_64.c index 908167b..f33fdd2 100644 --- a/arch/sh/mm/tlbflush_64.c +++ b/arch/sh/mm/tlbflush_64.c @@ -170,7 +170,3 @@ void __flush_tlb_global(void) { flush_tlb_all(); } - -void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) -{ -} -- cgit v0.10.2 From 4de5185629f44942f60e2fd536709ef31bd5a9c1 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 14 May 2012 16:44:45 +0900 Subject: sh64: Invert page fault fast-path error path values. This brings the sh64 version in line with the sh32 one with regards to how errors are handled. Base work for further unification of the implementations. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh5/entry.S b/arch/sh/kernel/cpu/sh5/entry.S index de60dc8..ff1f0e6 100644 --- a/arch/sh/kernel/cpu/sh5/entry.S +++ b/arch/sh/kernel/cpu/sh5/entry.S @@ -335,7 +335,7 @@ tlb_miss: /* If the fast path handler fixed the fault, just drop through quickly to the restore code right away to return to the excepting context. */ - beqi/u r2, 0, tr1 + bnei/u r2, 0, tr1 fast_tlb_miss_restore: ld.q SP, SAVED_TR0, r2 diff --git a/arch/sh/mm/tlbex_64.c b/arch/sh/mm/tlbex_64.c index 98b6427..59cb058 100644 --- a/arch/sh/mm/tlbex_64.c +++ b/arch/sh/mm/tlbex_64.c @@ -53,23 +53,23 @@ static int handle_vmalloc_fault(struct mm_struct *mm, pud = pud_offset(dir, address); if (pud_none_or_clear_bad(pud)) - return 0; + return 1; pmd = pmd_offset(pud, address); if (pmd_none_or_clear_bad(pmd)) - return 0; + return 1; pte = pte_offset_kernel(pmd, address); entry = *pte; if (pte_none(entry) || !pte_present(entry)) - return 0; + return 1; if ((pte_val(entry) & protection_flags) != protection_flags) - return 0; + return 1; update_mmu_cache(NULL, address, pte); - return 1; + return 0; } static int handle_tlbmiss(struct mm_struct *mm, @@ -94,27 +94,27 @@ static int handle_tlbmiss(struct mm_struct *mm, the next test is necessary. - RPC */ if (address >= (unsigned long) TASK_SIZE) /* upper half - never has page table entries. */ - return 0; + return 1; dir = pgd_offset(mm, address); if (pgd_none(*dir) || !pgd_present(*dir)) - return 0; + return 1; if (!pgd_present(*dir)) - return 0; + return 1; pud = pud_offset(dir, address); if (pud_none(*pud) || !pud_present(*pud)) - return 0; + return 1; pmd = pmd_offset(pud, address); if (pmd_none(*pmd) || !pmd_present(*pmd)) - return 0; + return 1; pte = pte_offset_kernel(pmd, address); entry = *pte; if (pte_none(entry) || !pte_present(entry)) - return 0; + return 1; /* * If the page doesn't have sufficient protection bits set to @@ -123,11 +123,11 @@ static int handle_tlbmiss(struct mm_struct *mm, * handler. */ if ((pte_val(entry) & protection_flags) != protection_flags) - return 0; + return 1; update_mmu_cache(NULL, address, pte); - return 1; + return 0; } /* @@ -214,12 +214,12 @@ asmlinkage int do_fast_page_fault(unsigned long long ssr_md, * Process-contexts can never have this address * range mapped */ - if (handle_vmalloc_fault(mm, protection_flags, address)) - return 1; + if (handle_vmalloc_fault(mm, protection_flags, address) == 0) + return 0; } else if (!in_interrupt() && mm) { - if (handle_tlbmiss(mm, protection_flags, address)) - return 1; + if (handle_tlbmiss(mm, protection_flags, address) == 0) + return 0; } - return 0; + return 1; } -- cgit v0.10.2 From 2ec08e141f88328e8a4d24590e9a2406633a0898 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 14 May 2012 16:46:07 +0900 Subject: sh64: Fix up caller-save register settings for fast-path. Now that the fast-path handler has been moved, we also need to update the Makefile to ensure that the same restrictions for caller-save registers are observed. Signed-off-by: Paul Mundt diff --git a/arch/sh/mm/Makefile b/arch/sh/mm/Makefile index ba81910..cee6b99 100644 --- a/arch/sh/mm/Makefile +++ b/arch/sh/mm/Makefile @@ -44,7 +44,7 @@ obj-$(CONFIG_HAVE_SRAM_POOL) += sram.o GCOV_PROFILE_pmb.o := n -# Special flags for fault_64.o. This puts restrictions on the number of +# Special flags for tlbex_64.o. This puts restrictions on the number of # caller-save registers that the compiler can target when building this file. # This is required because the code is called from a context in entry.S where # very few registers have been saved in the exception handler (for speed @@ -59,7 +59,7 @@ GCOV_PROFILE_pmb.o := n # The resources not listed below are callee save, i.e. the compiler is free to # use any of them and will spill them to the stack itself. -CFLAGS_fault_64.o += -ffixed-r7 \ +CFLAGS_tlbex_64.o += -ffixed-r7 \ -ffixed-r8 -ffixed-r9 -ffixed-r10 -ffixed-r11 -ffixed-r12 \ -ffixed-r13 -ffixed-r14 -ffixed-r16 -ffixed-r17 -ffixed-r19 \ -ffixed-r20 -ffixed-r21 -ffixed-r22 -ffixed-r23 \ -- cgit v0.10.2 From 392c3822a6fc247c0708c9e52c0818d1fbc9d7d7 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 14 May 2012 17:24:21 +0900 Subject: sh64: Tidy up and consolidate the TLB miss fast path. This unifies the fast-path TLB miss handler, allowing for further cleanup and eventual utilization of a shared _32/_64 handler. Signed-off-by: Paul Mundt diff --git a/arch/sh/mm/tlbex_64.c b/arch/sh/mm/tlbex_64.c index 59cb058..24dd4ab 100644 --- a/arch/sh/mm/tlbex_64.c +++ b/arch/sh/mm/tlbex_64.c @@ -33,76 +33,32 @@ #include #include #include +#include #include #include #include #include #include -static int handle_vmalloc_fault(struct mm_struct *mm, - unsigned long protection_flags, - unsigned long address) -{ - pgd_t *dir; - pud_t *pud; - pmd_t *pmd; - pte_t *pte; - pte_t entry; - - dir = pgd_offset_k(address); - - pud = pud_offset(dir, address); - if (pud_none_or_clear_bad(pud)) - return 1; - - pmd = pmd_offset(pud, address); - if (pmd_none_or_clear_bad(pmd)) - return 1; - - pte = pte_offset_kernel(pmd, address); - entry = *pte; - - if (pte_none(entry) || !pte_present(entry)) - return 1; - if ((pte_val(entry) & protection_flags) != protection_flags) - return 1; - - update_mmu_cache(NULL, address, pte); - - return 0; -} - -static int handle_tlbmiss(struct mm_struct *mm, - unsigned long long protection_flags, +static int handle_tlbmiss(unsigned long long protection_flags, unsigned long address) { - pgd_t *dir; + pgd_t *pgd; pud_t *pud; pmd_t *pmd; pte_t *pte; pte_t entry; - /* NB. The PGD currently only contains a single entry - there is no - page table tree stored for the top half of the address space since - virtual pages in that region should never be mapped in user mode. - (In kernel mode, the only things in that region are the 512Mb super - page (locked in), and vmalloc (modules) + I/O device pages (handled - by handle_vmalloc_fault), so no PGD for the upper half is required - by kernel mode either). - - See how mm->pgd is allocated and initialised in pgd_alloc to see why - the next test is necessary. - RPC */ - if (address >= (unsigned long) TASK_SIZE) - /* upper half - never has page table entries. */ - return 1; + if (is_vmalloc_addr((void *)address)) { + pgd = pgd_offset_k(address); + } else { + if (unlikely(address >= TASK_SIZE || !current->mm)) + return 1; - dir = pgd_offset(mm, address); - if (pgd_none(*dir) || !pgd_present(*dir)) - return 1; - if (!pgd_present(*dir)) - return 1; + pgd = pgd_offset(current->mm, address); + } - pud = pud_offset(dir, address); + pud = pud_offset(pgd, address); if (pud_none(*pud) || !pud_present(*pud)) return 1; @@ -112,7 +68,6 @@ static int handle_tlbmiss(struct mm_struct *mm, pte = pte_offset_kernel(pmd, address); entry = *pte; - if (pte_none(entry) || !pte_present(entry)) return 1; @@ -146,9 +101,6 @@ struct expevt_lookup { #define PRX (1<<7) #define PRR (1<<6) -#define DIRTY (_PAGE_DIRTY | _PAGE_ACCESSED) -#define YOUNG (_PAGE_ACCESSED) - /* Sized as 8 rather than 4 to allow checking the PTE's PRU bit against whether the fault happened in user mode or privileged mode. */ static struct expevt_lookup expevt_lookup_table = { @@ -164,12 +116,10 @@ static struct expevt_lookup expevt_lookup_table = { general fault handling in fault.c which deals with mapping file-backed pages, stack growth, segmentation faults, swapping etc etc) */ -asmlinkage int do_fast_page_fault(unsigned long long ssr_md, - unsigned long long expevt, - unsigned long address) +asmlinkage int __kprobes +do_fast_page_fault(unsigned long long ssr_md, unsigned long long expevt, + unsigned long address) { - struct task_struct *tsk; - struct mm_struct *mm; unsigned long long protection_flags; unsigned long long index; unsigned long long expevt4; @@ -194,32 +144,5 @@ asmlinkage int do_fast_page_fault(unsigned long long ssr_md, if (expevt_lookup_table.is_text_access[index]) set_thread_fault_code(FAULT_CODE_ITLB); - /* SIM - * Note this is now called with interrupts still disabled - * This is to cope with being called for a missing IO port - * address with interrupts disabled. This should be fixed as - * soon as we have a better 'fast path' miss handler. - * - * Plus take care how you try and debug this stuff. - * For example, writing debug data to a port which you - * have just faulted on is not going to work. - */ - - tsk = current; - mm = tsk->mm; - - if (is_vmalloc_addr((void *)address)) { - if (ssr_md) - /* - * Process-contexts can never have this address - * range mapped - */ - if (handle_vmalloc_fault(mm, protection_flags, address) == 0) - return 0; - } else if (!in_interrupt() && mm) { - if (handle_tlbmiss(mm, protection_flags, address) == 0) - return 0; - } - - return 1; + return handle_tlbmiss(protection_flags, address); } -- cgit v0.10.2 From fd37e75ed56e3f9ddde15c57a9cbde8256221404 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 14 May 2012 17:46:49 +0900 Subject: sh64: Set additional fault code values. The SSR.MD status amongst other things are already made available, which can be used for encoding a more precise fault code value. Signed-off-by: Paul Mundt diff --git a/arch/sh/mm/tlbex_64.c b/arch/sh/mm/tlbex_64.c index 24dd4ab..8557548 100644 --- a/arch/sh/mm/tlbex_64.c +++ b/arch/sh/mm/tlbex_64.c @@ -108,6 +108,17 @@ static struct expevt_lookup expevt_lookup_table = { .is_text_access = {1, 1, 0, 0, 0, 0, 0, 0} }; +static inline unsigned int +expevt_to_fault_code(unsigned long expevt) +{ + if (expevt == 0xa40) + return FAULT_CODE_ITLB; + else if (expevt == 0x060) + return FAULT_CODE_WRITE; + + return 0; +} + /* This routine handles page faults that can be serviced just by refilling a TLB entry from an existing page table entry. (This case represents a very @@ -123,6 +134,7 @@ do_fast_page_fault(unsigned long long ssr_md, unsigned long long expevt, unsigned long long protection_flags; unsigned long long index; unsigned long long expevt4; + unsigned int fault_code; /* The next few lines implement a way of hashing EXPEVT into a * small array index which can be used to lookup parameters @@ -139,10 +151,16 @@ do_fast_page_fault(unsigned long long ssr_md, unsigned long long expevt, index = expevt4 ^ (expevt4 >> 5); index &= 7; + fault_code = expevt_to_fault_code(expevt); + protection_flags = expevt_lookup_table.protection_flags[index]; if (expevt_lookup_table.is_text_access[index]) - set_thread_fault_code(FAULT_CODE_ITLB); + fault_code |= FAULT_CODE_ITLB; + if (!ssr_md) + fault_code |= FAULT_CODE_USER; + + set_thread_fault_code(fault_code); return handle_tlbmiss(protection_flags, address); } -- cgit v0.10.2 From 00d6025e58c6e3b229e28cab721c568af5b1ae05 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 15 May 2012 10:26:11 +0900 Subject: sh: Fix mistake of the member variable of plat_sci_port for SH7343 The current code was going to initialize irq of plat_sci_port. Not irq, irqs is right. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c index 476f474..5773643 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c @@ -56,7 +56,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irq = SCIx_IRQ_MUXED(evt2irq(0xC40)), + .irqs = SCIx_IRQ_MUXED(evt2irq(0xC40)), }; static struct platform_device scif2_device = { -- cgit v0.10.2 From e55387e9bfd24b6e415f27ab90ca1702f47304aa Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 12:29:22 +0900 Subject: sh: sh7786 evt2irq migration. This migrates SH7786 to evt2irq() backed hwirq lookup rather than using an open-coded calculation. This will make it possible to reposition the vector base at a later point in time. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c index 599022d..2e6952f 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c @@ -32,7 +32,10 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 40, 41, 43, 42 }, + .irqs = { evt2irq(0x700), + evt2irq(0x720), + evt2irq(0x760), + evt2irq(0x740) }, .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -53,7 +56,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 44, 44, 44, 44 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -71,7 +74,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 50, 50, 50, 50 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x840)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -89,7 +92,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 51, 51, 51, 51 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x860)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -107,7 +110,7 @@ static struct plat_sci_port scif4_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 52, 52, 52, 52 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -125,7 +128,7 @@ static struct plat_sci_port scif5_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 53, 53, 53, 53 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x8a0)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -150,7 +153,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 16, + .start = evt2irq(0x400), .flags = IORESOURCE_IRQ, }, }; @@ -178,7 +181,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 17, + .start = evt2irq(0x420), .flags = IORESOURCE_IRQ, }, }; @@ -205,7 +208,7 @@ static struct resource tmu2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 18, + .start = evt2irq(0x440), .flags = IORESOURCE_IRQ, }, }; @@ -232,7 +235,7 @@ static struct resource tmu3_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 20, + .start = evt2irq(0x480), .flags = IORESOURCE_IRQ, }, }; @@ -259,7 +262,7 @@ static struct resource tmu4_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 21, + .start = evt2irq(0x4a0), .flags = IORESOURCE_IRQ, }, }; @@ -286,7 +289,7 @@ static struct resource tmu5_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 22, + .start = evt2irq(0x4c0), .flags = IORESOURCE_IRQ, }, }; @@ -313,7 +316,7 @@ static struct resource tmu6_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 45, + .start = evt2irq(0x7a0), .flags = IORESOURCE_IRQ, }, }; @@ -340,7 +343,7 @@ static struct resource tmu7_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 45, + .start = evt2irq(0x7a0), .flags = IORESOURCE_IRQ, }, }; @@ -367,7 +370,7 @@ static struct resource tmu8_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 45, + .start = evt2irq(0x7a0), .flags = IORESOURCE_IRQ, }, }; @@ -394,7 +397,7 @@ static struct resource tmu9_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 46, + .start = evt2irq(0x7c0), .flags = IORESOURCE_IRQ, }, }; @@ -421,7 +424,7 @@ static struct resource tmu10_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 46, + .start = evt2irq(0x7c0), .flags = IORESOURCE_IRQ, }, }; @@ -448,7 +451,7 @@ static struct resource tmu11_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 46, + .start = evt2irq(0x7c0), .flags = IORESOURCE_IRQ, }, }; @@ -550,8 +553,8 @@ static struct resource usb_ehci_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 77, - .end = 77, + .start = evt2irq(0xba0), + .end = evt2irq(0xba0), .flags = IORESOURCE_IRQ, }, }; @@ -574,8 +577,8 @@ static struct resource usb_ohci_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 77, - .end = 77, + .start = evt2irq(0xba0), + .end = evt2irq(0xba0), .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From de410b5369e29085f60ddf39e4da5bb9d1a8e99e Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 12:38:12 +0900 Subject: sh: sh7343 evt2irq migration. Migrate SH7343 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c index 1b88483..b91ea83 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c @@ -13,6 +13,7 @@ #include #include #include +#include #include /* Serial */ @@ -22,7 +23,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), }; static struct platform_device scif0_device = { @@ -39,7 +40,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 81, 81, 81, 81 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), }; static struct platform_device scif1_device = { @@ -56,7 +57,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 82, 82, 82, 82 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), }; static struct platform_device scif2_device = { @@ -73,7 +74,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 83, 83, 83, 83 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xc60)), }; static struct platform_device scif3_device = { @@ -92,8 +93,8 @@ static struct resource iic0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 96, - .end = 99, + .start = evt2irq(0xe00), + .end = evt2irq(0xe60), .flags = IORESOURCE_IRQ, }, }; @@ -113,8 +114,8 @@ static struct resource iic1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 44, - .end = 47, + .start = evt2irq(0x780), + .end = evt2irq(0x7e0), .flags = IORESOURCE_IRQ, }, }; @@ -129,7 +130,7 @@ static struct platform_device iic1_device = { static struct uio_info vpu_platform_data = { .name = "VPU4", .version = "0", - .irq = 60, + .irq = evt2irq(0x980), }; static struct resource vpu_resources[] = { @@ -157,7 +158,7 @@ static struct platform_device vpu_device = { static struct uio_info veu_platform_data = { .name = "VEU", .version = "0", - .irq = 54, + .irq = evt2irq(0x8c0), }; static struct resource veu_resources[] = { @@ -185,7 +186,7 @@ static struct platform_device veu_device = { static struct uio_info jpu_platform_data = { .name = "JPU", .version = "0", - .irq = 27, + .irq = evt2irq(0x560), }; static struct resource jpu_resources[] = { @@ -224,7 +225,7 @@ static struct resource cmt_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 104, + .start = evt2irq(0xf00), .flags = IORESOURCE_IRQ, }, }; @@ -252,7 +253,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 16, + .start = evt2irq(0x400), .flags = IORESOURCE_IRQ, }, }; @@ -280,7 +281,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 17, + .start = evt2irq(0x420), .flags = IORESOURCE_IRQ, }, }; @@ -307,7 +308,7 @@ static struct resource tmu2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 18, + .start = evt2irq(0x440), .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From 58749400c540f11e3146c6e4f87215e44c58589b Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 12:43:11 +0900 Subject: sh: sh7366 evt2irq migration. Migrate SH7366 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c index 8777386..0bd09d5 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -25,7 +26,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), }; static struct platform_device scif0_device = { @@ -44,8 +45,8 @@ static struct resource iic_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 96, - .end = 99, + .start = evt2irq(0xe00), + .end = evt2irq(0xe60), .flags = IORESOURCE_IRQ, }, }; @@ -68,8 +69,8 @@ static struct resource usb_host_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 65, - .end = 65, + .start = evt2irq(0xa20), + .end = evt2irq(0xa20), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, }, }; @@ -89,7 +90,7 @@ static struct platform_device usb_host_device = { static struct uio_info vpu_platform_data = { .name = "VPU5", .version = "0", - .irq = 60, + .irq = evt2irq(0x980), }; static struct resource vpu_resources[] = { @@ -117,7 +118,7 @@ static struct platform_device vpu_device = { static struct uio_info veu0_platform_data = { .name = "VEU", .version = "0", - .irq = 54, + .irq = evt2irq(0x8c0), }; static struct resource veu0_resources[] = { @@ -145,7 +146,7 @@ static struct platform_device veu0_device = { static struct uio_info veu1_platform_data = { .name = "VEU", .version = "0", - .irq = 27, + .irq = evt2irq(0x560), }; static struct resource veu1_resources[] = { @@ -184,7 +185,7 @@ static struct resource cmt_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 104, + .start = evt2irq(0xf00), .flags = IORESOURCE_IRQ, }, }; @@ -240,7 +241,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 17, + .start = evt2irq(0x420), .flags = IORESOURCE_IRQ, }, }; @@ -267,7 +268,7 @@ static struct resource tmu2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 18, + .start = evt2irq(0x440), .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From 29b53e375b7e7ca148cc6faab523a5bb920af833 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 12:49:38 +0900 Subject: sh: sh7722 evt2irq migration. Migrate SH7722 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index 8420d4b..0f5a219 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -147,20 +148,20 @@ static struct resource sh7722_dmae_resources[] = { }, { .name = "error_irq", - .start = 78, - .end = 78, + .start = evt2irq(0xbc0), + .end = evt2irq(0xbc0), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 0-3 */ - .start = 48, - .end = 51, + .start = evt2irq(0x800), + .end = evt2irq(0x860), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 4-5 */ - .start = 76, - .end = 77, + .start = evt2irq(0xb80), + .end = evt2irq(0xba0), .flags = IORESOURCE_IRQ, }, }; @@ -182,7 +183,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), .ops = &sh7722_sci_port_ops, .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; @@ -201,7 +202,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 81, 81, 81, 81 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), .ops = &sh7722_sci_port_ops, .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; @@ -220,7 +221,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 82, 82, 82, 82 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), .ops = &sh7722_sci_port_ops, .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; @@ -241,17 +242,17 @@ static struct resource rtc_resources[] = { }, [1] = { /* Period IRQ */ - .start = 45, + .start = evt2irq(0x7a0), .flags = IORESOURCE_IRQ, }, [2] = { /* Carry IRQ */ - .start = 46, + .start = evt2irq(0x7c0), .flags = IORESOURCE_IRQ, }, [3] = { /* Alarm IRQ */ - .start = 44, + .start = evt2irq(0x780), .flags = IORESOURCE_IRQ, }, }; @@ -275,8 +276,8 @@ static struct resource usbf_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 65, - .end = 65, + .start = evt2irq(0xa20), + .end = evt2irq(0xa20), .flags = IORESOURCE_IRQ, }, }; @@ -301,8 +302,8 @@ static struct resource iic_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 96, - .end = 99, + .start = evt2irq(0xe00), + .end = evt2irq(0xe60), .flags = IORESOURCE_IRQ, }, }; @@ -317,7 +318,7 @@ static struct platform_device iic_device = { static struct uio_info vpu_platform_data = { .name = "VPU4", .version = "0", - .irq = 60, + .irq = evt2irq(0x980), }; static struct resource vpu_resources[] = { @@ -345,7 +346,7 @@ static struct platform_device vpu_device = { static struct uio_info veu_platform_data = { .name = "VEU", .version = "0", - .irq = 54, + .irq = evt2irq(0x8c0), }; static struct resource veu_resources[] = { @@ -373,7 +374,7 @@ static struct platform_device veu_device = { static struct uio_info jpu_platform_data = { .name = "JPU", .version = "0", - .irq = 27, + .irq = evt2irq(0x560), }; static struct resource jpu_resources[] = { @@ -412,7 +413,7 @@ static struct resource cmt_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 104, + .start = evt2irq(0xf00), .flags = IORESOURCE_IRQ, }, }; @@ -440,7 +441,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 16, + .start = evt2irq(0x400), .flags = IORESOURCE_IRQ, }, }; @@ -468,7 +469,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 17, + .start = evt2irq(0x420), .flags = IORESOURCE_IRQ, }, }; @@ -525,7 +526,7 @@ static struct resource siu_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 108, + .start = evt2irq(0xf80), .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From 933b954386dd6c8d04a0a406827e8c3febc619a5 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 12:57:59 +0900 Subject: sh: sh7723 evt2irq migration. Migrate SH7723 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index a188c9e..28d6fd8 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -28,7 +29,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; @@ -47,7 +48,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 81, 81, 81, 81 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; @@ -66,7 +67,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 82, 82, 82, 82 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; @@ -85,7 +86,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_3, .type = PORT_SCIFA, - .irqs = { 56, 56, 56, 56 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), }; static struct platform_device scif3_device = { @@ -103,7 +104,7 @@ static struct plat_sci_port scif4_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_3, .type = PORT_SCIFA, - .irqs = { 88, 88, 88, 88 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)), }; static struct platform_device scif4_device = { @@ -121,7 +122,7 @@ static struct plat_sci_port scif5_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_3, .type = PORT_SCIFA, - .irqs = { 109, 109, 109, 109 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)), }; static struct platform_device scif5_device = { @@ -135,7 +136,7 @@ static struct platform_device scif5_device = { static struct uio_info vpu_platform_data = { .name = "VPU5", .version = "0", - .irq = 60, + .irq = evt2irq(0x980), }; static struct resource vpu_resources[] = { @@ -163,7 +164,7 @@ static struct platform_device vpu_device = { static struct uio_info veu0_platform_data = { .name = "VEU2H", .version = "0", - .irq = 54, + .irq = evt2irq(0x8c0), }; static struct resource veu0_resources[] = { @@ -191,7 +192,7 @@ static struct platform_device veu0_device = { static struct uio_info veu1_platform_data = { .name = "VEU2H", .version = "0", - .irq = 27, + .irq = evt2irq(0x560), }; static struct resource veu1_resources[] = { @@ -230,7 +231,7 @@ static struct resource cmt_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 104, + .start = evt2irq(0xf00), .flags = IORESOURCE_IRQ, }, }; @@ -258,7 +259,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 16, + .start = evt2irq(0x400), .flags = IORESOURCE_IRQ, }, }; @@ -286,7 +287,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 17, + .start = evt2irq(0x420), .flags = IORESOURCE_IRQ, }, }; @@ -313,7 +314,7 @@ static struct resource tmu2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 18, + .start = evt2irq(0x440), .flags = IORESOURCE_IRQ, }, }; @@ -340,7 +341,7 @@ static struct resource tmu3_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 57, + .start = evt2irq(0x920), .flags = IORESOURCE_IRQ, }, }; @@ -367,7 +368,7 @@ static struct resource tmu4_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 58, + .start = evt2irq(0x940), .flags = IORESOURCE_IRQ, }, }; @@ -394,7 +395,7 @@ static struct resource tmu5_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 57, + .start = evt2irq(0x920), .flags = IORESOURCE_IRQ, }, }; @@ -417,17 +418,17 @@ static struct resource rtc_resources[] = { }, [1] = { /* Period IRQ */ - .start = 69, + .start = evt2irq(0xaa0), .flags = IORESOURCE_IRQ, }, [2] = { /* Carry IRQ */ - .start = 70, + .start = evt2irq(0xac0), .flags = IORESOURCE_IRQ, }, [3] = { /* Alarm IRQ */ - .start = 68, + .start = evt2irq(0xa80), .flags = IORESOURCE_IRQ, }, }; @@ -450,8 +451,8 @@ static struct resource sh7723_usb_host_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 65, - .end = 65, + .start = evt2irq(0xa20), + .end = evt2irq(0xa20), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, }, }; @@ -476,8 +477,8 @@ static struct resource iic_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 96, - .end = 99, + .start = evt2irq(0xe00), + .end = evt2irq(0xe60), .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From 16e9515358b28c787a057dfe010e797a9067294a Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 13:12:24 +0900 Subject: sh: sh7724 evt2irq migration. Migrate SH7724 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index 4c671cf..26b74c2 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -215,20 +216,20 @@ static struct resource sh7724_dmae0_resources[] = { }, { .name = "error_irq", - .start = 78, - .end = 78, + .start = evt2irq(0xbc0), + .end = evt2irq(0xbc0), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 0-3 */ - .start = 48, - .end = 51, + .start = evt2irq(0x800), + .end = evt2irq(0x860), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 4-5 */ - .start = 76, - .end = 77, + .start = evt2irq(0xb80), + .end = evt2irq(0xba0), .flags = IORESOURCE_IRQ, }, }; @@ -249,20 +250,20 @@ static struct resource sh7724_dmae1_resources[] = { }, { .name = "error_irq", - .start = 74, - .end = 74, + .start = evt2irq(0xb40), + .end = evt2irq(0xb40), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 0-3 */ - .start = 40, - .end = 43, + .start = evt2irq(0x700), + .end = evt2irq(0x760), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 4-5 */ - .start = 72, - .end = 73, + .start = evt2irq(0xb00), + .end = evt2irq(0xb20), .flags = IORESOURCE_IRQ, }, }; @@ -295,7 +296,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; @@ -314,7 +315,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 81, 81, 81, 81 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; @@ -333,7 +334,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 82, 82, 82, 82 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; @@ -352,7 +353,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_3, .type = PORT_SCIFA, - .irqs = { 56, 56, 56, 56 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), }; static struct platform_device scif3_device = { @@ -370,7 +371,7 @@ static struct plat_sci_port scif4_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_3, .type = PORT_SCIFA, - .irqs = { 88, 88, 88, 88 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)), }; static struct platform_device scif4_device = { @@ -388,7 +389,7 @@ static struct plat_sci_port scif5_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_3, .type = PORT_SCIFA, - .irqs = { 109, 109, 109, 109 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)), }; static struct platform_device scif5_device = { @@ -408,17 +409,17 @@ static struct resource rtc_resources[] = { }, [1] = { /* Period IRQ */ - .start = 69, + .start = evt2irq(0xaa0), .flags = IORESOURCE_IRQ, }, [2] = { /* Carry IRQ */ - .start = 70, + .start = evt2irq(0xac0), .flags = IORESOURCE_IRQ, }, [3] = { /* Alarm IRQ */ - .start = 68, + .start = evt2irq(0xa80), .flags = IORESOURCE_IRQ, }, }; @@ -439,8 +440,8 @@ static struct resource iic0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 96, - .end = 99, + .start = evt2irq(0xe00), + .end = evt2irq(0xe60), .flags = IORESOURCE_IRQ, }, }; @@ -461,8 +462,8 @@ static struct resource iic1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 92, - .end = 95, + .start = evt2irq(0xd80), + .end = evt2irq(0xde0), .flags = IORESOURCE_IRQ, }, }; @@ -478,7 +479,7 @@ static struct platform_device iic1_device = { static struct uio_info vpu_platform_data = { .name = "VPU5F", .version = "0", - .irq = 60, + .irq = evt2irq(0x980), }; static struct resource vpu_resources[] = { @@ -507,7 +508,7 @@ static struct platform_device vpu_device = { static struct uio_info veu0_platform_data = { .name = "VEU3F0", .version = "0", - .irq = 83, + .irq = evt2irq(0xc60), }; static struct resource veu0_resources[] = { @@ -536,7 +537,7 @@ static struct platform_device veu0_device = { static struct uio_info veu1_platform_data = { .name = "VEU3F1", .version = "0", - .irq = 54, + .irq = evt2irq(0x8c0), }; static struct resource veu1_resources[] = { @@ -633,7 +634,7 @@ static struct resource cmt_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 104, + .start = evt2irq(0xf00), .flags = IORESOURCE_IRQ, }, }; @@ -661,7 +662,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 16, + .start = evt2irq(0x400), .flags = IORESOURCE_IRQ, }, }; @@ -689,7 +690,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 17, + .start = evt2irq(0x420), .flags = IORESOURCE_IRQ, }, }; @@ -716,7 +717,7 @@ static struct resource tmu2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 18, + .start = evt2irq(0x440), .flags = IORESOURCE_IRQ, }, }; @@ -744,7 +745,7 @@ static struct resource tmu3_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 57, + .start = evt2irq(0x920), .flags = IORESOURCE_IRQ, }, }; @@ -771,7 +772,7 @@ static struct resource tmu4_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 58, + .start = evt2irq(0x940), .flags = IORESOURCE_IRQ, }, }; @@ -798,7 +799,7 @@ static struct resource tmu5_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 57, + .start = evt2irq(0x920), .flags = IORESOURCE_IRQ, }, }; @@ -817,7 +818,7 @@ static struct platform_device tmu5_device = { static struct uio_info jpu_platform_data = { .name = "JPU", .version = "0", - .irq = 27, + .irq = evt2irq(0x560), }; static struct resource jpu_resources[] = { @@ -846,7 +847,7 @@ static struct platform_device jpu_device = { static struct uio_info spu0_platform_data = { .name = "SPU2DSP0", .version = "0", - .irq = 86, + .irq = evt2irq(0xcc0), }; static struct resource spu0_resources[] = { @@ -875,7 +876,7 @@ static struct platform_device spu0_device = { static struct uio_info spu1_platform_data = { .name = "SPU2DSP1", .version = "0", - .irq = 87, + .irq = evt2irq(0xce0), }; static struct resource spu1_resources[] = { -- cgit v0.10.2 From f5bccdc09a259a121965cc1c9d1f8349452e1244 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 13:24:34 +0900 Subject: sh: sh7757 evt2irq migration. Migrate SH7757 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c index c8836cf..2096308 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c @@ -18,7 +18,7 @@ #include #include #include - +#include #include #include @@ -28,7 +28,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 40, 40, 40, 40 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), }; static struct platform_device scif2_device = { @@ -45,7 +45,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 76, 76, 76, 76 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), }; static struct platform_device scif3_device = { @@ -86,7 +86,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 28, + .start = evt2irq(0x580), .flags = IORESOURCE_IRQ, }, }; @@ -114,7 +114,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 29, + .start = evt2irq(0x5a0), .flags = IORESOURCE_IRQ, }, }; @@ -136,7 +136,7 @@ static struct resource spi0_resources[] = { .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, }, [1] = { - .start = 86, + .start = evt2irq(0xcc0), .flags = IORESOURCE_IRQ, }, }; @@ -466,8 +466,8 @@ static struct resource sh7757_dmae0_resources[] = { }, { .name = "error_irq", - .start = 34, - .end = 34, + .start = evt2irq(0x640), + .end = evt2irq(0x640), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, }, }; @@ -488,56 +488,56 @@ static struct resource sh7757_dmae1_resources[] = { }, { .name = "error_irq", - .start = 34, - .end = 34, + .start = evt2irq(0x640), + .end = evt2irq(0x640), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, }, { /* IRQ for channels 4 */ - .start = 46, - .end = 46, + .start = evt2irq(0x7c0), + .end = evt2irq(0x7c0), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, }, { /* IRQ for channels 5 */ - .start = 46, - .end = 46, + .start = evt2irq(0x7c0), + .end = evt2irq(0x7c0), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, }, { /* IRQ for channels 6 */ - .start = 88, - .end = 88, + .start = evt2irq(0xd00), + .end = evt2irq(0xd00), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, }, { /* IRQ for channels 7 */ - .start = 88, - .end = 88, + .start = evt2irq(0xd00), + .end = evt2irq(0xd00), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, }, { /* IRQ for channels 8 */ - .start = 88, - .end = 88, + .start = evt2irq(0xd00), + .end = evt2irq(0xd00), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, }, { /* IRQ for channels 9 */ - .start = 88, - .end = 88, + .start = evt2irq(0xd00), + .end = evt2irq(0xd00), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, }, { /* IRQ for channels 10 */ - .start = 88, - .end = 88, + .start = evt2irq(0xd00), + .end = evt2irq(0xd00), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, }, { /* IRQ for channels 11 */ - .start = 88, - .end = 88, + .start = evt2irq(0xd00), + .end = evt2irq(0xd00), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, }, }; @@ -558,20 +558,20 @@ static struct resource sh7757_dmae2_resources[] = { }, { .name = "error_irq", - .start = 323, - .end = 323, + .start = evt2irq(0x2a60), + .end = evt2irq(0x2a60), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 12 to 16 */ - .start = 272, - .end = 276, + .start = evt2irq(0x2400), + .end = evt2irq(0x2480), .flags = IORESOURCE_IRQ, }, { /* IRQ for channel 17 */ - .start = 279, - .end = 279, + .start = evt2irq(0x24e0), + .end = evt2irq(0x24e0), .flags = IORESOURCE_IRQ, }, }; @@ -592,20 +592,20 @@ static struct resource sh7757_dmae3_resources[] = { }, { .name = "error_irq", - .start = 324, - .end = 324, + .start = evt2irq(0x2a80), + .end = evt2irq(0x2a80), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 18 to 22 */ - .start = 280, - .end = 284, + .start = evt2irq(0x2500), + .end = evt2irq(0x2580), .flags = IORESOURCE_IRQ, }, { /* IRQ for channel 23 */ - .start = 288, - .end = 288, + .start = evt2irq(0x2600), + .end = evt2irq(0x2600), .flags = IORESOURCE_IRQ, }, }; @@ -668,7 +668,7 @@ static struct resource spi1_resources[] = { .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, }, { - .start = 54, + .start = evt2irq(0x8c0), .flags = IORESOURCE_IRQ, }, }; @@ -687,7 +687,7 @@ static struct resource rspi_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = 220, + .start = evt2irq(0x1d80), .flags = IORESOURCE_IRQ, }, }; @@ -706,8 +706,8 @@ static struct resource usb_ehci_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 57, - .end = 57, + .start = evt2irq(0x920), + .end = evt2irq(0x920), .flags = IORESOURCE_IRQ, }, }; @@ -730,8 +730,8 @@ static struct resource usb_ohci_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 57, - .end = 57, + .start = evt2irq(0x920), + .end = evt2irq(0x920), .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From ea3235d96297e7e99deec8419bd9568606d89996 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 13:46:34 +0900 Subject: sh: sh7763 evt2irq migration. Migrate SH7763 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c index 0011351..bd0a8fb 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -22,7 +23,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 40, 40, 40, 40 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -40,7 +41,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 76, 76, 76, 76 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -58,7 +59,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 104, 104, 104, 104 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xf00)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -78,7 +79,7 @@ static struct resource rtc_resources[] = { }, [1] = { /* Shared Period/Carry/Alarm IRQ */ - .start = 20, + .start = evt2irq(0x480), .flags = IORESOURCE_IRQ, }, }; @@ -97,13 +98,14 @@ static struct resource usb_ohci_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 83, - .end = 83, + .start = evt2irq(0xc60), + .end = evt2irq(0xc60), .flags = IORESOURCE_IRQ, }, }; static u64 usb_ohci_dma_mask = 0xffffffffUL; + static struct platform_device usb_ohci_device = { .name = "sh_ohci", .id = -1, @@ -122,8 +124,8 @@ static struct resource usbf_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 84, - .end = 84, + .start = evt2irq(0xc80), + .end = evt2irq(0xc80), .flags = IORESOURCE_IRQ, }, }; @@ -152,7 +154,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 28, + .start = evt2irq(0x580), .flags = IORESOURCE_IRQ, }, }; @@ -180,7 +182,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 29, + .start = evt2irq(0x5a0), .flags = IORESOURCE_IRQ, }, }; @@ -207,7 +209,7 @@ static struct resource tmu2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 30, + .start = evt2irq(0x5c0), .flags = IORESOURCE_IRQ, }, }; @@ -234,7 +236,7 @@ static struct resource tmu3_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 96, + .start = evt2irq(0xe00), .flags = IORESOURCE_IRQ, }, }; @@ -261,7 +263,7 @@ static struct resource tmu4_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 97, + .start = evt2irq(0xe20), .flags = IORESOURCE_IRQ, }, }; @@ -288,7 +290,7 @@ static struct resource tmu5_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 98, + .start = evt2irq(0xe40), .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From f454314cff21155192d7358a9e890d7834078094 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 13:52:22 +0900 Subject: sh: sh7770 evt2irq migration. Migrate SH7770 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c index 2c6aa22..256ea7a 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c @@ -12,6 +12,7 @@ #include #include #include +#include #include static struct plat_sci_port scif0_platform_data = { @@ -20,7 +21,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 61, 61, 61, 61 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)), }; static struct platform_device scif0_device = { @@ -37,7 +38,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 62, 62, 62, 62 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)), }; static struct platform_device scif1_device = { @@ -54,7 +55,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 63, 63, 63, 63 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)), }; static struct platform_device scif2_device = { @@ -71,7 +72,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 64, 64, 64, 64 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xa00)), }; static struct platform_device scif3_device = { @@ -88,7 +89,7 @@ static struct plat_sci_port scif4_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 65, 65, 65, 65 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xa20)), }; static struct platform_device scif4_device = { @@ -105,7 +106,7 @@ static struct plat_sci_port scif5_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 66, 66, 66, 66 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xa40)), }; static struct platform_device scif5_device = { @@ -122,7 +123,7 @@ static struct plat_sci_port scif6_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 67, 67, 67, 67 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xa60)), }; static struct platform_device scif6_device = { @@ -139,7 +140,7 @@ static struct plat_sci_port scif7_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 68, 68, 68, 68 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xa80)), }; static struct platform_device scif7_device = { @@ -156,7 +157,7 @@ static struct plat_sci_port scif8_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 69, 69, 69, 69 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xaa0)), }; static struct platform_device scif8_device = { @@ -173,7 +174,7 @@ static struct plat_sci_port scif9_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 70, 70, 70, 70 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xac0)), }; static struct platform_device scif9_device = { @@ -197,7 +198,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 16, + .start = evt2irq(0x400), .flags = IORESOURCE_IRQ, }, }; @@ -225,7 +226,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 17, + .start = evt2irq(0x420), .flags = IORESOURCE_IRQ, }, }; @@ -252,7 +253,7 @@ static struct resource tmu2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 18, + .start = evt2irq(0x440), .flags = IORESOURCE_IRQ, }, }; @@ -279,7 +280,7 @@ static struct resource tmu3_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 19, + .start = evt2irq(0x460), .flags = IORESOURCE_IRQ, }, }; @@ -306,7 +307,7 @@ static struct resource tmu4_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 20, + .start = evt2irq(0x480), .flags = IORESOURCE_IRQ, }, }; @@ -333,7 +334,7 @@ static struct resource tmu5_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 21, + .start = evt2irq(0x4a0), .flags = IORESOURCE_IRQ, }, }; @@ -360,7 +361,7 @@ static struct resource tmu6_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 22, + .start = evt2irq(0x4c0), .flags = IORESOURCE_IRQ, }, }; @@ -387,7 +388,7 @@ static struct resource tmu7_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 23, + .start = evt2irq(0x4e0), .flags = IORESOURCE_IRQ, }, }; @@ -414,7 +415,7 @@ static struct resource tmu8_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 24, + .start = evt2irq(0x500), .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From 89ed34f34842fc4ed766a93838302f613d5f4801 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 13:59:18 +0900 Subject: sh: sh7780 evt2irq migration. Migrate SH7780 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c index d431b00..de45b704 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c @@ -14,6 +14,7 @@ #include #include #include +#include #include static struct plat_sci_port scif0_platform_data = { @@ -22,7 +23,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 40, 40, 40, 40 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -40,7 +41,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 76, 76, 76, 76 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -65,7 +66,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 28, + .start = evt2irq(0x580), .flags = IORESOURCE_IRQ, }, }; @@ -93,7 +94,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 29, + .start = evt2irq(0x5a0), .flags = IORESOURCE_IRQ, }, }; @@ -120,7 +121,7 @@ static struct resource tmu2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 30, + .start = evt2irq(0x5c0), .flags = IORESOURCE_IRQ, }, }; @@ -147,7 +148,7 @@ static struct resource tmu3_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 96, + .start = evt2irq(0xe00), .flags = IORESOURCE_IRQ, }, }; @@ -174,7 +175,7 @@ static struct resource tmu4_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 97, + .start = evt2irq(0xe20), .flags = IORESOURCE_IRQ, }, }; @@ -201,7 +202,7 @@ static struct resource tmu5_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 98, + .start = evt2irq(0xe40), .flags = IORESOURCE_IRQ, }, }; @@ -224,7 +225,7 @@ static struct resource rtc_resources[] = { }, [1] = { /* Shared Period/Carry/Alarm IRQ */ - .start = 20, + .start = evt2irq(0x480), .flags = IORESOURCE_IRQ, }, }; @@ -321,10 +322,13 @@ static struct resource sh7780_dmae0_resources[] = { .flags = IORESOURCE_MEM, }, { - /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */ + /* + * Real DMA error vector is 0x6c0, and channel + * vectors are 0x640-0x6a0, 0x780-0x7a0 + */ .name = "error_irq", - .start = 34, - .end = 34, + .start = evt2irq(0x640), + .end = evt2irq(0x640), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, }, }; @@ -338,10 +342,13 @@ static struct resource sh7780_dmae1_resources[] = { }, /* DMAC1 has no DMARS */ { - /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */ + /* + * Real DMA error vector is 0x6c0, and channel + * vectors are 0x7c0-0x7e0, 0xd80-0xde0 + */ .name = "error_irq", - .start = 46, - .end = 46, + .start = evt2irq(0x7c0), + .end = evt2irq(0x7c0), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, }, }; -- cgit v0.10.2 From ddb3208497599764cd7209b4c1b7e2a607689a6b Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 14:04:49 +0900 Subject: sh: sh7785 evt2irq migration. Migrate SH7785 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c index 81588ef..0968ecb 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -24,7 +25,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 40, 40, 40, 40 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -42,7 +43,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 44, 44, 44, 44 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -60,7 +61,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 60, 60, 60, 60 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x980)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -78,7 +79,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 61, 61, 61, 61 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -96,7 +97,7 @@ static struct plat_sci_port scif4_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 62, 62, 62, 62 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -114,7 +115,7 @@ static struct plat_sci_port scif5_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { 63, 63, 63, 63 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -139,7 +140,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 28, + .start = evt2irq(0x580), .flags = IORESOURCE_IRQ, }, }; @@ -167,7 +168,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 29, + .start = evt2irq(0x5a0), .flags = IORESOURCE_IRQ, }, }; @@ -194,7 +195,7 @@ static struct resource tmu2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 30, + .start = evt2irq(0x5c0), .flags = IORESOURCE_IRQ, }, }; @@ -221,7 +222,7 @@ static struct resource tmu3_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 96, + .start = evt2irq(0xe00), .flags = IORESOURCE_IRQ, }, }; @@ -248,7 +249,7 @@ static struct resource tmu4_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 97, + .start = evt2irq(0xe20), .flags = IORESOURCE_IRQ, }, }; @@ -275,7 +276,7 @@ static struct resource tmu5_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 98, + .start = evt2irq(0xe40), .flags = IORESOURCE_IRQ, }, }; @@ -375,10 +376,13 @@ static struct resource sh7785_dmae0_resources[] = { .flags = IORESOURCE_MEM, }, { - /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */ + /* + * Real DMA error vector is 0x6e0, and channel + * vectors are 0x620-0x6c0 + */ .name = "error_irq", - .start = 33, - .end = 33, + .start = evt2irq(0x620), + .end = evt2irq(0x620), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, }, }; @@ -392,10 +396,13 @@ static struct resource sh7785_dmae1_resources[] = { }, /* DMAC1 has no DMARS */ { - /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */ + /* + * Real DMA error vector is 0x940, and channel + * vectors are 0x880-0x920 + */ .name = "error_irq", - .start = 52, - .end = 52, + .start = evt2irq(0x880), + .end = evt2irq(0x880), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, }, }; -- cgit v0.10.2 From d8be10bbf3ba7eb4f1a9e609813fcbf916472e2f Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 14:11:22 +0900 Subject: sh: sh-x3 evt2irq migration. Migrate SH-X3 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c index bb20880..7ca7dd2 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -32,7 +33,10 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 40, 41, 43, 42 }, + .irqs = { evt2irq(0x700), + evt2irq(0x720), + evt2irq(0x760), + evt2irq(0x740) }, }; static struct platform_device scif0_device = { @@ -49,7 +53,10 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 44, 45, 47, 46 }, + .irqs = { evt2irq(0x780), + evt2irq(0x7a0), + evt2irq(0x7e0), + evt2irq(0x7c0) }, }; static struct platform_device scif1_device = { @@ -66,7 +73,10 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 52, 53, 55, 54 }, + .irqs = { evt2irq(0x880), + evt2irq(0x8a0), + evt2irq(0x8e0), + evt2irq(0x8c0) }, }; static struct platform_device scif2_device = { @@ -90,7 +100,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 16, + .start = evt2irq(0x400), .flags = IORESOURCE_IRQ, }, }; @@ -118,7 +128,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 17, + .start = evt2irq(0x420), .flags = IORESOURCE_IRQ, }, }; @@ -145,7 +155,7 @@ static struct resource tmu2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 18, + .start = evt2irq(0x440), .flags = IORESOURCE_IRQ, }, }; @@ -172,7 +182,7 @@ static struct resource tmu3_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 19, + .start = evt2irq(0x460), .flags = IORESOURCE_IRQ, }, }; @@ -199,7 +209,7 @@ static struct resource tmu4_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 20, + .start = evt2irq(0x480), .flags = IORESOURCE_IRQ, }, }; @@ -226,7 +236,7 @@ static struct resource tmu5_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 21, + .start = evt2irq(0x4a0), .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From 054f0378a5ed2f8bd99f87846f0464e2440108d4 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 14:15:11 +0900 Subject: sh: sh4-202 evt2irq migration. Migrate SH4-202 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c index 5b28331..2a5320a 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c @@ -13,6 +13,7 @@ #include #include #include +#include #include static struct plat_sci_port scif0_platform_data = { @@ -21,7 +22,10 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 40, 41, 43, 42 }, + .irqs = { evt2irq(0x700), + evt2irq(0x720), + evt2irq(0x760), + evt2irq(0x740) }, }; static struct platform_device scif0_device = { @@ -45,7 +49,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 16, + .start = evt2irq(0x400), .flags = IORESOURCE_IRQ, }, }; @@ -73,7 +77,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 17, + .start = evt2irq(0x420), .flags = IORESOURCE_IRQ, }, }; @@ -100,7 +104,7 @@ static struct resource tmu2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 18, + .start = evt2irq(0x440), .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From 20688c3093caf5d3b1ebf36819b1d6b3247a811d Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 14:18:35 +0900 Subject: sh: sh7750 evt2irq migration. Migrate SH7750 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c index 98cc0c7..04a4551 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -24,7 +25,7 @@ static struct resource rtc_resources[] = { }, [1] = { /* Shared Period/Carry/Alarm IRQ */ - .start = 20, + .start = evt2irq(0x480), .flags = IORESOURCE_IRQ, }, }; @@ -43,7 +44,7 @@ static struct plat_sci_port sci_platform_data = { .scscr = SCSCR_TE | SCSCR_RE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCI, - .irqs = { 23, 23, 23, 0 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x4e0)), .regshift = 2, }; @@ -61,7 +62,7 @@ static struct plat_sci_port scif_platform_data = { .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 40, 40, 40, 40 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), }; static struct platform_device scif_device = { @@ -85,7 +86,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 16, + .start = evt2irq(0x400), .flags = IORESOURCE_IRQ, }, }; @@ -113,7 +114,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 17, + .start = evt2irq(0x420), .flags = IORESOURCE_IRQ, }, }; @@ -140,7 +141,7 @@ static struct resource tmu2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 18, + .start = evt2irq(0x440), .flags = IORESOURCE_IRQ, }, }; @@ -172,7 +173,7 @@ static struct resource tmu3_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 72, + .start = evt2irq(0xb00), .flags = IORESOURCE_IRQ, }, }; @@ -199,7 +200,7 @@ static struct resource tmu4_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 76, + .start = evt2irq(0xb80), .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From 79ce21a64bee65434a311d68b8962c9dd6408842 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 14:28:11 +0900 Subject: sh: sh7760 evt2irq migration. Migrate SH7760 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c index c0b4c77..98e075a 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -132,7 +133,10 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 52, 53, 55, 54 }, + .irqs = { evt2irq(0x880), + evt2irq(0x8a0), + evt2irq(0x8e0), + evt2irq(0x8c0) }, .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -150,7 +154,10 @@ static struct plat_sci_port scif1_platform_data = { .type = PORT_SCIF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, - .irqs = { 72, 73, 75, 74 }, + .irqs = { evt2irq(0xb00), + evt2irq(0xb20), + evt2irq(0xb60), + evt2irq(0xb40) }, .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -168,7 +175,10 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 76, 77, 79, 78 }, + .irqs = { evt2irq(0xb80), + evt2irq(0xba0), + evt2irq(0xbe0), + evt2irq(0xbc0) }, .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; @@ -186,7 +196,9 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCI, - .irqs = { 80, 81, 82, 0 }, + .irqs = { evt2irq(0xc00), + evt2irq(0xc20), + evt2irq(0xc40), }, .regshift = 2, }; @@ -211,7 +223,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 16, + .start = evt2irq(0x400), .flags = IORESOURCE_IRQ, }, }; @@ -239,7 +251,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 17, + .start = evt2irq(0x420), .flags = IORESOURCE_IRQ, }, }; @@ -266,7 +278,7 @@ static struct resource tmu2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 18, + .start = evt2irq(0x440), .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From e91b2a40a1a440a80a073d952de421ae7d188802 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 14:31:11 +0900 Subject: sh: sh7705 evt2irq migration. Migrate SH7705 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c index 2309618..03e4c96 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -75,7 +76,7 @@ static struct plat_sci_port scif0_platform_data = { SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIF, - .irqs = { 56, 56, 56 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), .ops = &sh770x_sci_port_ops, .regtype = SCIx_SH7705_SCIF_REGTYPE, }; @@ -94,7 +95,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIF, - .irqs = { 52, 52, 52 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), .ops = &sh770x_sci_port_ops, .regtype = SCIx_SH7705_SCIF_REGTYPE, }; @@ -114,7 +115,7 @@ static struct resource rtc_resources[] = { .flags = IORESOURCE_IO, }, [1] = { - .start = 20, + .start = evt2irq(0x480), .flags = IORESOURCE_IRQ, }, }; @@ -146,7 +147,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 16, + .start = evt2irq(0x400), .flags = IORESOURCE_IRQ, }, }; @@ -174,7 +175,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 17, + .start = evt2irq(0x420), .flags = IORESOURCE_IRQ, }, }; @@ -201,7 +202,7 @@ static struct resource tmu2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 18, + .start = evt2irq(0x440), .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From a9302a64d440ff60c917b33fe47dbeab2e3e7e94 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 14:34:48 +0900 Subject: sh: sh7706/sh7707/sh7709/sh7709 evt2irq migration. Migrate SH770x to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c index 3f3d5fe..ba26cd9 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c @@ -19,6 +19,7 @@ #include #include #include +#include #include enum { @@ -95,7 +96,7 @@ static struct resource rtc_resources[] = { .flags = IORESOURCE_IO, }, [1] = { - .start = 20, + .start = evt2irq(0x480), .flags = IORESOURCE_IRQ, }, }; @@ -114,7 +115,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_TE | SCSCR_RE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCI, - .irqs = { 23, 23, 23, 0 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x4e0)), .ops = &sh770x_sci_port_ops, .regshift = 1, }; @@ -135,7 +136,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_TE | SCSCR_RE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 56, 56, 56, 56 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), .ops = &sh770x_sci_port_ops, .regtype = SCIx_SH3_SCIF_REGTYPE, }; @@ -157,7 +158,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_TE | SCSCR_RE, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_IRDA, - .irqs = { 52, 52, 52, 52 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), .ops = &sh770x_sci_port_ops, .regshift = 1, }; @@ -184,7 +185,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 16, + .start = evt2irq(0x400), .flags = IORESOURCE_IRQ, }, }; @@ -212,7 +213,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 17, + .start = evt2irq(0x420), .flags = IORESOURCE_IRQ, }, }; @@ -239,7 +240,7 @@ static struct resource tmu2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 18, + .start = evt2irq(0x440), .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From 5d0af7696869cb52d63b849fabc1087f16c0092e Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 14:37:51 +0900 Subject: sh: sh7710/sh7712 evt2irq migration. Migrate SH7710/SH7712 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c index 78f6b01..93c9c5e 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c @@ -14,6 +14,7 @@ #include #include #include +#include #include enum { @@ -77,7 +78,7 @@ static struct resource rtc_resources[] = { .flags = IORESOURCE_IO, }, [1] = { - .start = 20, + .start = evt2irq(0x480), .flags = IORESOURCE_IRQ, }, }; @@ -103,7 +104,7 @@ static struct plat_sci_port scif0_platform_data = { SCSCR_CKE1 | SCSCR_CKE0, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 52, 52, 52, 52 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), }; static struct platform_device scif0_device = { @@ -121,7 +122,7 @@ static struct plat_sci_port scif1_platform_data = { SCSCR_CKE1 | SCSCR_CKE0, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 56, 56, 56, 56 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), }; static struct platform_device scif1_device = { @@ -145,7 +146,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 16, + .start = evt2irq(0x400), .flags = IORESOURCE_IRQ, }, }; @@ -173,7 +174,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 17, + .start = evt2irq(0x420), .flags = IORESOURCE_IRQ, }, }; @@ -200,7 +201,7 @@ static struct resource tmu2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 18, + .start = evt2irq(0x440), .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From 85ee6b06cc3a42f0381455ea4d1da0bdded41bee Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 14:41:00 +0900 Subject: sh: sh7720 evt2irq migration. Migrate SH7720 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c index 9492034..0c2f1b2 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -30,7 +31,7 @@ static struct resource rtc_resources[] = { }, [1] = { /* Shared Period/Carry/Alarm IRQ */ - .start = 20, + .start = evt2irq(0x480), .flags = IORESOURCE_IRQ, }, }; @@ -55,7 +56,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), .ops = &sh7720_sci_port_ops, .regtype = SCIx_SH7705_SCIF_REGTYPE, }; @@ -74,7 +75,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIF, - .irqs = { 81, 81, 81, 81 }, + .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), .ops = &sh7720_sci_port_ops, .regtype = SCIx_SH7705_SCIF_REGTYPE, }; @@ -94,13 +95,14 @@ static struct resource usb_ohci_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 67, - .end = 67, + .start = evt2irq(0xa60), + .end = evt2irq(0xa60), .flags = IORESOURCE_IRQ, }, }; static u64 usb_ohci_dma_mask = 0xffffffffUL; + static struct platform_device usb_ohci_device = { .name = "sh_ohci", .id = -1, @@ -121,8 +123,8 @@ static struct resource usbf_resources[] = { }, [1] = { .name = "sh_udc", - .start = 65, - .end = 65, + .start = evt2irq(0xa20), + .end = evt2irq(0xa20), .flags = IORESOURCE_IRQ, }, }; @@ -152,7 +154,7 @@ static struct resource cmt0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 104, + .start = evt2irq(0xf00), .flags = IORESOURCE_IRQ, }, }; @@ -179,7 +181,7 @@ static struct resource cmt1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 104, + .start = evt2irq(0xf00), .flags = IORESOURCE_IRQ, }, }; @@ -206,7 +208,7 @@ static struct resource cmt2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 104, + .start = evt2irq(0xf00), .flags = IORESOURCE_IRQ, }, }; @@ -233,7 +235,7 @@ static struct resource cmt3_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 104, + .start = evt2irq(0xf00), .flags = IORESOURCE_IRQ, }, }; @@ -260,7 +262,7 @@ static struct resource cmt4_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 104, + .start = evt2irq(0xf00), .flags = IORESOURCE_IRQ, }, }; @@ -288,7 +290,7 @@ static struct resource tmu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 16, + .start = evt2irq(0x400), .flags = IORESOURCE_IRQ, }, }; @@ -316,7 +318,7 @@ static struct resource tmu1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 17, + .start = evt2irq(0x420), .flags = IORESOURCE_IRQ, }, }; @@ -343,7 +345,7 @@ static struct resource tmu2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 18, + .start = evt2irq(0x440), .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From 0fa4c3912cd8e257a4648d6982f0bfe1a48bd8c2 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 14:48:53 +0900 Subject: sh: edosk7705 evt2irq migration. Migrate edosk7705 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/boards/board-edosk7705.c b/arch/sh/boards/board-edosk7705.c index 541d8a2..0a531a1 100644 --- a/arch/sh/boards/board-edosk7705.c +++ b/arch/sh/boards/board-edosk7705.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -20,7 +21,7 @@ #define SMC_IO_OFFSET 0x300 #define SMC_IOADDR (SMC_IOBASE + SMC_IO_OFFSET) -#define ETHERNET_IRQ 0x09 +#define ETHERNET_IRQ evt2irq(0x320) static void __init sh_edosk7705_init_irq(void) { -- cgit v0.10.2 From 03c5713c96755c6ade73feb27558d214a3e0e546 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 14:52:31 +0900 Subject: sh: edosk7760 evt2irq migration. Migrate edosk7760 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/boards/board-edosk7760.c b/arch/sh/boards/board-edosk7760.c index e9656a2..d4871d2 100644 --- a/arch/sh/boards/board-edosk7760.c +++ b/arch/sh/boards/board-edosk7760.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -40,8 +41,6 @@ #define SMC_IO_OFFSET 0x300 #define SMC_IOADDR (SMC_IOBASE + SMC_IO_OFFSET) -#define ETHERNET_IRQ 5 - /* NOR flash */ static struct mtd_partition edosk7760_nor_flash_partitions[] = { { @@ -99,8 +98,8 @@ static struct resource sh7760_i2c1_res[] = { .end = SH7760_I2C1_MMIOEND, .flags = IORESOURCE_MEM, },{ - .start = SH7760_I2C1_IRQ, - .end = SH7760_I2C1_IRQ, + .start = evt2irq(0x9e0), + .end = evt2irq(0x9e0), .flags = IORESOURCE_IRQ, }, }; @@ -122,8 +121,8 @@ static struct resource sh7760_i2c0_res[] = { .end = SH7760_I2C0_MMIOEND, .flags = IORESOURCE_MEM, }, { - .start = SH7760_I2C0_IRQ, - .end = SH7760_I2C0_IRQ, + .start = evt2irq(0x9c0), + .end = evt2irq(0x9c0), .flags = IORESOURCE_IRQ, }, }; @@ -150,8 +149,8 @@ static struct resource smc91x_res[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = ETHERNET_IRQ, - .end = ETHERNET_IRQ, + .start = evt2irq(0x2a0), + .end = evt2irq(0x2a0), .flags = IORESOURCE_IRQ , } }; diff --git a/arch/sh/include/asm/i2c-sh7760.h b/arch/sh/include/asm/i2c-sh7760.h index 2418211..69fee12 100644 --- a/arch/sh/include/asm/i2c-sh7760.h +++ b/arch/sh/include/asm/i2c-sh7760.h @@ -9,11 +9,9 @@ #define SH7760_I2C0_MMIO 0xFE140000 #define SH7760_I2C0_MMIOEND 0xFE14003B -#define SH7760_I2C0_IRQ 62 #define SH7760_I2C1_MMIO 0xFE150000 #define SH7760_I2C1_MMIOEND 0xFE15003B -#define SH7760_I2C1_IRQ 63 struct sh7760_i2c_platdata { unsigned int speed_khz; -- cgit v0.10.2 From d5d7e78368cb04b2ee3dc2c0e5f2ea97a345d4d6 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 14:57:21 +0900 Subject: sh: espt evt2irq migration. Migrate espt to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/boards/board-espt.c b/arch/sh/boards/board-espt.c index b3ae9d3..6cba0a7 100644 --- a/arch/sh/boards/board-espt.c +++ b/arch/sh/boards/board-espt.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -71,7 +72,7 @@ static struct resource sh_eth_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = 57, /* irq number */ + .start = evt2irq(0x920), /* irq number */ .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From 7b56934ce26841587f3cd2843a6f0b918070e5b7 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 14:58:03 +0900 Subject: sh: magicpanelr2 evt2irq migration. Migrate magicpanelr2 to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/boards/board-magicpanelr2.c b/arch/sh/boards/board-magicpanelr2.c index b2ca1d9..90568f9 100644 --- a/arch/sh/boards/board-magicpanelr2.c +++ b/arch/sh/boards/board-magicpanelr2.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -245,8 +246,8 @@ static struct resource smsc911x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 35, - .end = 35, + .start = evt2irq(0x660), + .end = evt2irq(0x660), .flags = IORESOURCE_IRQ, }, }; @@ -358,17 +359,17 @@ static void __init init_mpr2_IRQ(void) { plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */ - irq_set_irq_type(32, IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */ - irq_set_irq_type(33, IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */ - irq_set_irq_type(34, IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */ - irq_set_irq_type(35, IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */ - irq_set_irq_type(36, IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */ - irq_set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */ - - intc_set_priority(32, 13); /* IRQ0 CAN1 */ - intc_set_priority(33, 13); /* IRQ0 CAN2 */ - intc_set_priority(34, 13); /* IRQ0 CAN3 */ - intc_set_priority(35, 6); /* IRQ3 SMSC9115 */ + irq_set_irq_type(evt2irq(0x600), IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */ + irq_set_irq_type(evt2irq(0x620), IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */ + irq_set_irq_type(evt2irq(0x640), IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */ + irq_set_irq_type(evt2irq(0x660), IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */ + irq_set_irq_type(evt2irq(0x680), IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */ + irq_set_irq_type(evt2irq(0x6a0), IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */ + + intc_set_priority(evt2irq(0x600), 13); /* IRQ0 CAN1 */ + intc_set_priority(evt2irq(0x620), 13); /* IRQ0 CAN2 */ + intc_set_priority(evt2irq(0x640), 13); /* IRQ0 CAN3 */ + intc_set_priority(evt2irq(0x660), 6); /* IRQ3 SMSC9115 */ } /* -- cgit v0.10.2 From a7734e51077e3eb3943887d15bb5c49063738263 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 15:18:10 +0900 Subject: sh: sh7757lcr evt2irq migration. Migrate sh7757lcr to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/boards/board-sh7757lcr.c b/arch/sh/boards/board-sh7757lcr.c index 24b1ee4..5087f8b 100644 --- a/arch/sh/boards/board-sh7757lcr.c +++ b/arch/sh/boards/board-sh7757lcr.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -65,8 +66,8 @@ static struct resource sh_eth0_resources[] = { .end = 0xfef001ff, .flags = IORESOURCE_MEM, }, { - .start = 84, - .end = 84, + .start = evt2irq(0xc80), + .end = evt2irq(0xc80), .flags = IORESOURCE_IRQ, }, }; @@ -94,8 +95,8 @@ static struct resource sh_eth1_resources[] = { .end = 0xfef009ff, .flags = IORESOURCE_MEM, }, { - .start = 84, - .end = 84, + .start = evt2irq(0xc80), + .end = evt2irq(0xc80), .flags = IORESOURCE_IRQ, }, }; @@ -139,8 +140,8 @@ static struct resource sh_eth_giga0_resources[] = { .end = 0xfee01fff, .flags = IORESOURCE_MEM, }, { - .start = 315, - .end = 315, + .start = evt2irq(0x2960), + .end = evt2irq(0x2960), .flags = IORESOURCE_IRQ, }, }; @@ -174,8 +175,8 @@ static struct resource sh_eth_giga1_resources[] = { .end = 0xfee01fff, .flags = IORESOURCE_MEM, }, { - .start = 316, - .end = 316, + .start = evt2irq(0x2980), + .end = evt2irq(0x2980), .flags = IORESOURCE_IRQ, }, }; @@ -206,11 +207,11 @@ static struct resource sh_mmcif_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 211, + .start = evt2irq(0x1c60), .flags = IORESOURCE_IRQ, }, [2] = { - .start = 212, + .start = evt2irq(0x1c80), .flags = IORESOURCE_IRQ, }, }; @@ -248,7 +249,7 @@ static struct resource sdhi_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 20, + .start = evt2irq(0x480), .flags = IORESOURCE_IRQ, }, }; @@ -284,8 +285,8 @@ static struct resource usb0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 50, - .end = 50, + .start = evt2irq(0x840), + .end = evt2irq(0x840), .flags = IORESOURCE_IRQ, }, }; -- cgit v0.10.2 From b894701e7c472dbc6267bdde68bd6d35266b8dfc Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 18 May 2012 15:34:49 +0900 Subject: sh: mach-se evt2irq migration. Migrate Solution Engine boards to evt2irq backed hwirq lookups. Signed-off-by: Paul Mundt diff --git a/arch/sh/boards/mach-se/7722/setup.c b/arch/sh/boards/mach-se/7722/setup.c index e1963fe..8f7f055 100644 --- a/arch/sh/boards/mach-se/7722/setup.c +++ b/arch/sh/boards/mach-se/7722/setup.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -114,7 +115,7 @@ static struct resource sh_keysc_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 79, + .start = evt2irq(0xbe0), .flags = IORESOURCE_IRQ, }, }; diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c index c540b16..479cdf8 100644 --- a/arch/sh/boards/mach-se/7724/setup.c +++ b/arch/sh/boards/mach-se/7724/setup.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include