From f6db7029bb266fafe7679792514c1f26556fd61e Mon Sep 17 00:00:00 2001 From: Yunzhi Li Date: Fri, 12 Dec 2014 23:12:21 +0800 Subject: ARM: dts: rockchip: add rk3288 usb PHY This patch adds a device_node for RK3288 SoC usb phy. It also defines the phy to be used by three usb controllers: usb_host0/1 and usb_otg. Signed-off-by: Yunzhi Li Tested-by: Doug Anderson Reviewed-by: Doug Anderson Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index d771f68..2c29a3e 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -419,6 +419,8 @@ interrupts = ; clocks = <&cru HCLK_USBHOST0>; clock-names = "usbhost"; + phys = <&usbphy1>; + phy-names = "usb"; status = "disabled"; }; @@ -431,6 +433,8 @@ interrupts = ; clocks = <&cru HCLK_USBHOST1>; clock-names = "otg"; + phys = <&usbphy2>; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -441,6 +445,8 @@ interrupts = ; clocks = <&cru HCLK_OTG0>; clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -697,6 +703,35 @@ interrupts = ; }; + usbphy: phy { + compatible = "rockchip,rk3288-usb-phy"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy0 { + #phy-cells = <0>; + reg = <0x320>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + }; + + usbphy1: usb-phy1 { + #phy-cells = <0>; + reg = <0x334>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + }; + + usbphy2: usb-phy2 { + #phy-cells = <0>; + reg = <0x348>; + clocks = <&cru SCLK_OTGPHY2>; + clock-names = "phyclk"; + }; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3288-pinctrl"; rockchip,grf = <&grf>; -- cgit v0.10.2 From e537c9ccfab694281de8b6966bfa14e8d2bd9a69 Mon Sep 17 00:00:00 2001 From: Yunzhi Li Date: Fri, 12 Dec 2014 23:17:02 +0800 Subject: ARM: dts: rockchip: Enable usb PHY on rk3288-evb board Enable usb PHY for all usb ports on rk3288-evb. Signed-off-by: Yunzhi Li Reviewed-by: Doug Anderson Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 5e895a5..287a162 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -238,6 +238,10 @@ }; }; +&usbphy { + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; }; -- cgit v0.10.2 From 055b0c6753f315ad6922b86bdfa352733de5f674 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 19 Feb 2015 22:46:45 +0100 Subject: ARM: dts: rockchip: enable usbphy on rk3288-firefly Enable the usb phys on the firefly board. Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index e6f873a..b9dda41 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -459,6 +459,10 @@ status = "okay"; }; +&usbphy { + status = "okay"; +}; + &usb_host1 { pinctrl-names = "default"; pinctrl-0 = <&usbhub_rst>; -- cgit v0.10.2 From f36abc869886ac91f88c72d21835497686228558 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 20 Feb 2015 01:31:57 +0100 Subject: ARM: dts: rockchip: enable gmac on rk3288-firefly This was left out of the original firefly board definition due to the ethernet support going completely through the network tree, making the underlying nodes unavailable. Now that everything is present enable the gmac on the firefly. Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index b9dda41..b54dd78 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -179,6 +179,22 @@ status = "okay"; }; +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "ok"; +}; + &hdmi { ddc-i2c-bus = <&i2c5>; status = "okay"; -- cgit v0.10.2 From b757258a5e47a4d46dd1ea03cbbe1f10122b9e39 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 29 Jan 2015 12:36:28 +0100 Subject: ARM: mvebu: Use macros for interrupt flags on Armada 38x sdhci node Instead of hardcoding the values of the interrupt flags, use the macros provided by and for the Armada 38x SDHCI node. Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 1dff30a..efff46b 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -549,7 +549,7 @@ sdhci@d8000 { compatible = "marvell,armada-380-sdhci"; reg = <0xd8000 0x1000>, <0xdc000 0x100>; - interrupts = <0 25 0x4>; + interrupts = ; clocks = <&gateclk 17>; mrvl,clk-delay-cycles = <0x1F>; status = "disabled"; -- cgit v0.10.2 From ddbdc5790fb9274a5aeed49081152842d17b0932 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 29 Jan 2015 12:36:29 +0100 Subject: ARM: mvebu: Update the SDHCI node on Armada 38x The binding of the armada-380-sdhci has been extended with a new register in order to be able to use the SDR50 and DDR50 mode. This commit add the resource associated to this new register for the Armada 38x. Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index efff46b..cb30fb8 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -548,7 +548,10 @@ sdhci@d8000 { compatible = "marvell,armada-380-sdhci"; - reg = <0xd8000 0x1000>, <0xdc000 0x100>; + reg-names = "sdhci", "mbus", "conf-sdio3"; + reg = <0xd8000 0x1000>, + <0xdc000 0x100>, + <0x18454 0x4>; interrupts = ; clocks = <&gateclk 17>; mrvl,clk-delay-cycles = <0x1F>; -- cgit v0.10.2 From 444fdf947de3bf5ac6b6ac033eb9d877a4b7e90d Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 29 Jan 2015 12:36:30 +0100 Subject: ARM: mvebu: Add Device Tree description of SDHCI for Armada 388 RD The Device Tree description of SDHCI on Armada 388 RD board was missing. This commit adds the node for it. Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts index d99baac..1ecf511 100644 --- a/arch/arm/boot/dts/armada-388-rd.dts +++ b/arch/arm/boot/dts/armada-388-rd.dts @@ -85,6 +85,16 @@ clock-frequency = <100000>; }; + sdhci@d8000 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; + broken-cd; + no-1-8-v; + wp-inverted; + bus-width = <8>; + status = "okay"; + }; + serial@12000 { status = "okay"; }; -- cgit v0.10.2 From fe7c20fa689d3b9230be0b552f667c043d11ed75 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 21 Jan 2015 17:17:39 +0100 Subject: ARM: shmobile: r8a7740 dtsi: add remaining DIV6 clocks This adds the remaining DIV6 clocks and all possible parents for the SUB clock. Signed-off-by: Ulrich Hecht Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 8a09260..83c1c3c 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -431,6 +431,18 @@ clock-frequency = <27000000>; clock-output-names = "dv"; }; + fmsick_clk: fmsick_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "fmsick"; + }; + fmsock_clk: fmsock_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "fmsock"; + }; fsiack_clk: fsiack_clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -459,13 +471,78 @@ }; /* Variable factor clocks (DIV6) */ + vclk1_clk: vclk1_clk@e6150008 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150008 4>; + clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, + <&cpg_clocks R8A7740_CLK_USB24S>, + <&extal1_div2_clk>, <&extalr_clk>, <0>, + <0>; + #clock-cells = <0>; + clock-output-names = "vclk1"; + }; + vclk2_clk: vclk2_clk@e615000c { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe615000c 4>; + clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, + <&cpg_clocks R8A7740_CLK_USB24S>, + <&extal1_div2_clk>, <&extalr_clk>, <0>, + <0>; + #clock-cells = <0>; + clock-output-names = "vclk2"; + }; + fmsi_clk: fmsi_clk@e6150010 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150010 4>; + clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "fmsi"; + }; + fmso_clk: fmso_clk@e6150014 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150014 4>; + clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "fmso"; + }; + fsia_clk: fsia_clk@e6150018 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150018 4>; + clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "fsia"; + }; sub_clk: sub_clk@e6150080 { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150080 4>; - clocks = <&pllc1_div2_clk>; + clocks = <&pllc1_div2_clk>, + <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; #clock-cells = <0>; clock-output-names = "sub"; }; + spu_clk: spu_clk@e6150084 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150084 4>; + clocks = <&pllc1_div2_clk>, + <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "spu"; + }; + vou_clk: vou_clk@e6150088 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150088 4>; + clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>, + <0>; + #clock-cells = <0>; + clock-output-names = "vou"; + }; + stpro_clk: stpro_clk@e615009c { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe615009c 4>; + clocks = <&cpg_clocks R8A7740_CLK_PLLC0>; + #clock-cells = <0>; + clock-output-names = "stpro"; + }; /* Fixed factor clocks */ pllc1_div2_clk: pllc1_div2_clk { -- cgit v0.10.2 From 48bdf06dd975fb01e54e0b0406de720ebeeb55c7 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 6 Jan 2015 20:42:04 +0100 Subject: ARM: shmobile: sh73a0 dtsi: Set control-parent for all irqpin nodes The sh73a0 INTC can't mask interrupts properly most likely due to a hardware bug. Set the control-parent property to delegate masking to the parent interrupt controller. Signed-off-by: Laurent Pinchart Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 2dfd5b4..0767087 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -94,6 +94,7 @@ 0 6 IRQ_TYPE_LEVEL_HIGH 0 7 IRQ_TYPE_LEVEL_HIGH 0 8 IRQ_TYPE_LEVEL_HIGH>; + control-parent; }; irqpin1: irqpin@e6900004 { @@ -133,6 +134,7 @@ 0 22 IRQ_TYPE_LEVEL_HIGH 0 23 IRQ_TYPE_LEVEL_HIGH 0 24 IRQ_TYPE_LEVEL_HIGH>; + control-parent; }; irqpin3: irqpin@e690000c { @@ -152,6 +154,7 @@ 0 30 IRQ_TYPE_LEVEL_HIGH 0 31 IRQ_TYPE_LEVEL_HIGH 0 32 IRQ_TYPE_LEVEL_HIGH>; + control-parent; }; i2c0: i2c@e6820000 { -- cgit v0.10.2 From 5c9e276095a9607f530f94e219daf2996b1360fa Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 6 Jan 2015 20:42:05 +0100 Subject: ARM: shmobile: kzm9g-reference dts: Sort i2c0 children by unit address While at it rename the ak4648 node to "codec" to describe the device's function instead of its model, and move its device-specific property after its generic properties. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 6d32c87..0134d53 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -188,6 +188,13 @@ &i2c0 { status = "okay"; + + ak4648: codec@12 { + compatible = "asahi-kasei,ak4648"; + reg = <0x12>; + #sound-dai-cells = <0>; + }; + as3711@40 { compatible = "ams,as3711"; reg = <0x40>; @@ -258,12 +265,6 @@ }; }; }; - - ak4648: ak4648@12 { - #sound-dai-cells = <0>; - compatible = "asahi-kasei,ak4648"; - reg = <0x12>; - }; }; &i2c3 { -- cgit v0.10.2 From 56b7271c9dbf029d288e4fbcae72e405e56ae856 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 6 Jan 2015 20:42:06 +0100 Subject: ARM: shmobile: kzm9g-reference dts: Add ak8975 magnetometer node Add a DT node for the AK8975 magnetometer sensor, which is connected to i2c0. Signed-off-by: Geert Uytterhoeven Specify the device interrupt to avoid polling for end of conversion. While at it rename the DT node to compass@c to describe the device's function instead of its model. Signed-off-by: Laurent Pinchart Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 0134d53..873b415 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -189,6 +189,13 @@ &i2c0 { status = "okay"; + compass@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + interrupt-parent = <&irqpin3>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + }; + ak4648: codec@12 { compatible = "asahi-kasei,ak4648"; reg = <0x12>; -- cgit v0.10.2 From 4bd1dd503aa2a6cfeb18a48d1da01662dd5124e1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 6 Jan 2015 20:42:07 +0100 Subject: ARM: shmobile: kzm9g-reference dts: Add adxl345 accelerometer node Add a DT node for the ADXL345 three-axis digital accelerometer sensor, which is connected to i2c0. As trivial i2c devices are matched against the first compatible entry only, compatibility is declared with "adi,adxl34x" only for now. Signed-off-by: Geert Uytterhoeven The device needs an interrupt to operate properly. Specify the two interrupts used on the board. While at it rename the DT node to accelerometer@1d to describe the device's function instead of its model. Signed-off-by: Laurent Pinchart Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 873b415..fd16998 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -202,6 +202,14 @@ #sound-dai-cells = <0>; }; + accelerometer@1d { + compatible = "adi,adxl34x"; + reg = <0x1d>; + interrupt-parent = <&irqpin3>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <3 IRQ_TYPE_LEVEL_HIGH>; + }; + as3711@40 { compatible = "ams,as3711"; reg = <0x40>; -- cgit v0.10.2 From 070048dc8879499533f587b8ebdb990f5a29d08b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 6 Jan 2015 20:42:08 +0100 Subject: ARM: shmobile: kzm9g-reference dts: Add r2025sd rtc node Add a DT node for the R2025D real-time clock, which is connected to i2c0. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index fd16998..e3723be 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -210,6 +210,11 @@ <3 IRQ_TYPE_LEVEL_HIGH>; }; + rtc@32 { + compatible = "ricoh,r2025sd"; + reg = <0x32>; + }; + as3711@40 { compatible = "ams,as3711"; reg = <0x40>; -- cgit v0.10.2 From 8ac627fa8ef0f98f914690515aa3bf376d7a880d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 6 Jan 2015 20:42:09 +0100 Subject: ARM: shmobile: kzm9g-reference dts: Add st1232 touchscreen node Enable the kzm9g touchscreen controller in the board's DT file. Signed-off-by: Laurent Pinchart Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index e3723be..0156fc8 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -287,6 +287,17 @@ }; }; +&i2c1 { + status = "okay"; + + touchscreen@55 { + compatible = "sitronix,st1232"; + reg = <0x55>; + interrupt-parent = <&irqpin1>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + }; +}; + &i2c3 { pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; -- cgit v0.10.2 From 56a215d66b1eee870a6b90a8c245dfc3e503a137 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 6 Jan 2015 20:56:05 +0100 Subject: ARM: shmobile: sh73a0 dtsi: Add missing INTCA0 clock for irqpin module This clock drives the irqpin controller modules. Before, it was assumed enabled by the bootloader or reset state. By making it available to the driver, we make sure it gets enabled when needed, and allow it to be managed by system or runtime PM. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 0767087..08f736d 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -94,6 +94,7 @@ 0 6 IRQ_TYPE_LEVEL_HIGH 0 7 IRQ_TYPE_LEVEL_HIGH 0 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; control-parent; }; @@ -114,6 +115,7 @@ 0 14 IRQ_TYPE_LEVEL_HIGH 0 15 IRQ_TYPE_LEVEL_HIGH 0 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; control-parent; }; @@ -134,6 +136,7 @@ 0 22 IRQ_TYPE_LEVEL_HIGH 0 23 IRQ_TYPE_LEVEL_HIGH 0 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; control-parent; }; @@ -154,6 +157,7 @@ 0 30 IRQ_TYPE_LEVEL_HIGH 0 31 IRQ_TYPE_LEVEL_HIGH 0 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; control-parent; }; @@ -698,5 +702,16 @@ clock-output-names = "iic3", "iic4", "keysc"; }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe6150144 4>, <0xe615003c 4>; + clocks = <&cpg_clocks SH73A0_CLK_HP>; + #clock-cells = <1>; + clock-indices = < + SH73A0_CLK_INTCA0 + >; + clock-output-names = + "intca0"; + }; }; }; diff --git a/include/dt-bindings/clock/sh73a0-clock.h b/include/dt-bindings/clock/sh73a0-clock.h index 1dd3eb2..5336956 100644 --- a/include/dt-bindings/clock/sh73a0-clock.h +++ b/include/dt-bindings/clock/sh73a0-clock.h @@ -76,4 +76,7 @@ #define SH73A0_CLK_IIC4 10 #define SH73A0_CLK_KEYSC 3 +/* MSTP5 */ +#define SH73A0_CLK_INTCA0 8 + #endif -- cgit v0.10.2 From 09940bf079454a17c0bc298a4ca3678ce530b858 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Tue, 6 Jan 2015 20:56:06 +0100 Subject: ARM: shmobile: sh73a0 dtsi: Add selectable sources to DIV6 clocks Specifies clock sources and register bits. Signed-off-by: Ulrich Hecht [geert: Drop renesas,src-shift/renesas,src-width, pad to 4 or 8 parents] Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 08f736d..ab319b7 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -433,133 +433,159 @@ vclk1_clk: vclk1_clk@e6150008 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150008 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, + <0>; #clock-cells = <0>; clock-output-names = "vclk1"; }; vclk2_clk: vclk2_clk@e615000c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615000c 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, + <0>; #clock-cells = <0>; clock-output-names = "vclk2"; }; vclk3_clk: vclk3_clk@e615001c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615001c 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, + <0>; #clock-cells = <0>; clock-output-names = "vclk3"; }; zb_clk: zb_clk@e6150010 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150010 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; clock-output-names = "zb"; }; flctl_clk: flctl_clk@e6150014 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150014 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; clock-output-names = "flctlck"; }; sdhi0_clk: sdhi0_clk@e6150074 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150074 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&pll1_div13_clk>, <0>; #clock-cells = <0>; clock-output-names = "sdhi0ck"; }; sdhi1_clk: sdhi1_clk@e6150078 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150078 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&pll1_div13_clk>, <0>; #clock-cells = <0>; clock-output-names = "sdhi1ck"; }; sdhi2_clk: sdhi2_clk@e615007c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615007c 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&pll1_div13_clk>, <0>; #clock-cells = <0>; clock-output-names = "sdhi2ck"; }; fsia_clk: fsia_clk@e6150018 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150018 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&fsiack_clk>, <&fsiack_clk>; #clock-cells = <0>; clock-output-names = "fsia"; }; fsib_clk: fsib_clk@e6150090 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150090 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&fsibck_clk>, <&fsibck_clk>; #clock-cells = <0>; clock-output-names = "fsib"; }; sub_clk: sub_clk@e6150080 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150080 4>; - clocks = <&extal2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; clock-output-names = "sub"; }; spua_clk: spua_clk@e6150084 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150084 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; clock-output-names = "spua"; }; spuv_clk: spuv_clk@e6150094 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150094 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; clock-output-names = "spuv"; }; msu_clk: msu_clk@e6150088 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150088 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; clock-output-names = "msu"; }; hsi_clk: hsi_clk@e615008c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615008c 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&pll1_div7_clk>, <0>; #clock-cells = <0>; clock-output-names = "hsi"; }; mfg1_clk: mfg1_clk@e6150098 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150098 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; clock-output-names = "mfg1"; }; mfg2_clk: mfg2_clk@e615009c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615009c 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; clock-output-names = "mfg2"; }; dsit_clk: dsit_clk@e6150060 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150060 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; clock-output-names = "dsit"; }; dsi0p_clk: dsi0p_clk@e6150064 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150064 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>, + <&extcki_clk>, <0>, <0>, <0>; #clock-cells = <0>; clock-output-names = "dsi0pck"; }; -- cgit v0.10.2 From 89ebd5459c3c43536f3dbec19216e97179647673 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 6 Jan 2015 20:17:38 +0100 Subject: ARM: shmobile: kzm9g dts: Declare the full 512 MiB of RAM Traditionally, the first 16 MiB of RAM was reserved for the RT processor. However, this is incompatible with CONFIG_AUTO_ZRELADDR=y, which requires that the start address of physical memory is a multiple of 128 MiB. As CONFIG_AUTO_ZRELADDR=y is enabled for multi-platform kernels, declare RAM to start at 0x40000000. While at it, reclaim the last 8 MiB of RAM, too, so the full 512 MiB is available. Note that kzm9g_defconfig still has CONFIG_MEMORY_START=0x41000000 and CONFIG_MEMORY_SIZE=0x1f000000, so before the advent of DT we scribbled over the last 8 MiB, too. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts index 27c5f42..e7dae01 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts @@ -21,6 +21,6 @@ memory { device_type = "memory"; - reg = <0x41000000 0x1e800000>; + reg = <0x40000000 0x20000000>; }; }; -- cgit v0.10.2 From 3ce1bc08efdd1c1dfba123e802604c0e853ae5db Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 6 Jan 2015 20:17:39 +0100 Subject: ARM: shmobile: kzm9g-reference dts: Declare the full 512 MiB of RAM Traditionally, the first 16 MiB of RAM was reserved for the RT processor. However, this is incompatible with CONFIG_AUTO_ZRELADDR=y, which requires that the start address of physical memory is a multiple of 128 MiB. As CONFIG_AUTO_ZRELADDR=y is enabled for multi-platform kernels, declare RAM to start at 0x40000000. While at it, reclaim the last 8 MiB of RAM, too, so the full 512 MiB is available. Note that kzm9g_defconfig still has CONFIG_MEMORY_START=0x41000000 and CONFIG_MEMORY_SIZE=0x1f000000, so before the advent of DT we scribbled over the last 8 MiB, too. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 0156fc8..bf365f7 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -45,7 +45,7 @@ memory { device_type = "memory"; - reg = <0x41000000 0x1e800000>; + reg = <0x40000000 0x20000000>; }; reg_1p8v: regulator@0 { -- cgit v0.10.2 From bd8474853f9de32a963fb06569552833f756b63d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 27 Jan 2015 19:12:17 +0200 Subject: ARM: shmobile: r8a7794: Add DMAC devices to DT Instantiate the two system DMA controllers in the r8a7794 device tree. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 8f78da5..7474535 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -107,6 +107,66 @@ <0 17 IRQ_TYPE_LEVEL_HIGH>; }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH + 0 200 IRQ_TYPE_LEVEL_HIGH + 0 201 IRQ_TYPE_LEVEL_HIGH + 0 202 IRQ_TYPE_LEVEL_HIGH + 0 203 IRQ_TYPE_LEVEL_HIGH + 0 204 IRQ_TYPE_LEVEL_HIGH + 0 205 IRQ_TYPE_LEVEL_HIGH + 0 206 IRQ_TYPE_LEVEL_HIGH + 0 207 IRQ_TYPE_LEVEL_HIGH + 0 208 IRQ_TYPE_LEVEL_HIGH + 0 209 IRQ_TYPE_LEVEL_HIGH + 0 210 IRQ_TYPE_LEVEL_HIGH + 0 211 IRQ_TYPE_LEVEL_HIGH + 0 212 IRQ_TYPE_LEVEL_HIGH + 0 213 IRQ_TYPE_LEVEL_HIGH + 0 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH + 0 216 IRQ_TYPE_LEVEL_HIGH + 0 217 IRQ_TYPE_LEVEL_HIGH + 0 218 IRQ_TYPE_LEVEL_HIGH + 0 219 IRQ_TYPE_LEVEL_HIGH + 0 308 IRQ_TYPE_LEVEL_HIGH + 0 309 IRQ_TYPE_LEVEL_HIGH + 0 310 IRQ_TYPE_LEVEL_HIGH + 0 311 IRQ_TYPE_LEVEL_HIGH + 0 312 IRQ_TYPE_LEVEL_HIGH + 0 313 IRQ_TYPE_LEVEL_HIGH + 0 314 IRQ_TYPE_LEVEL_HIGH + 0 315 IRQ_TYPE_LEVEL_HIGH + 0 316 IRQ_TYPE_LEVEL_HIGH + 0 317 IRQ_TYPE_LEVEL_HIGH + 0 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <15>; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7794", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; -- cgit v0.10.2 From 70496727c08262c69cbeac10dfefada745b46869 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 27 Jan 2015 11:13:23 +0200 Subject: ARM: shmobile: r8a7790: Add IPMMU DT nodes Add the six IPMMU instances found in the r8a7790 to DT with a disabled status. Signed-off-by: Laurent Pinchart Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 4b38fc9..24de994 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1465,4 +1465,55 @@ ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; }; }; }; + + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>, + <0 224 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, + <0 199 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, + <0 221 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xffc80000 0 0x1000>; + interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; }; -- cgit v0.10.2 From f1951852ed17684f6033e96a9faf3dbe67c163ae Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 27 Jan 2015 11:13:24 +0200 Subject: ARM: shmobile: r8a7791: Add IPMMU DT nodes Add the seven IPMMU instances found in the r8a7791 to DT with a disabled status. Signed-off-by: Laurent Pinchart Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index e35812a..43fb58a 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1384,6 +1384,66 @@ status = "disabled"; }; + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>, + <0 224 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, + <0 199 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, + <0 221 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xffc80000 0 0x1000>; + interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_gp: mmu@e62a0000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>, + <0 261 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + rcar_sound: rcar_sound@ec500000 { /* * #sound-dai-cells is required -- cgit v0.10.2 From 1cb2794f608244312515ac41e82378cb2d58d74e Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 27 Jan 2015 11:13:25 +0200 Subject: ARM: shmobile: r8a7794: Add IPMMU DT nodes Add the six IPMMU instances found in the r8a7794 to DT with a disabled status. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 7474535..6f70bc4 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -645,4 +645,54 @@ clock-output-names = "scifa3", "scifa4", "scifa5"; }; }; + + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>, + <0 224 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, + <0 199 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + }; + + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, + <0 221 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + }; + + ipmmu_gp: mmu@e62a0000 { + compatible = "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>, + <0 261 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; }; -- cgit v0.10.2 From 82818d3482badfa88f66b3abbac838daf7e35b97 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 27 Jan 2015 10:45:55 +0200 Subject: ARM: shmobile: r8a7794: Add ethernet controller to device tree Add a DT node for the on-SoC ethernet controller device. Signed-off-by: Laurent Pinchart Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 6f70bc4..63b918b 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -329,6 +329,17 @@ status = "disabled"; }; + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7794"; + reg = <0 0xee700000 0 0x400>; + interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7794_CLK_ETHER>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; -- cgit v0.10.2 From a895b7cda38cd2fa155be22b531d164f17ec84ec Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 27 Jan 2015 10:45:56 +0200 Subject: ARM: shmobile: r8a7794: alt: Enable ethernet controller Enable the ethernet controller for the Alt board. Pin muxing entries are currently left out as r8a7794 pin control support isn't available yet. We thus rely on the boot loader to configure ethernet pins for now. Signed-off-by: Laurent Pinchart Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 0d848e6..25bf434 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -43,6 +43,19 @@ status = "okay"; }; +ðer { + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +}; + &scif2 { status = "okay"; }; -- cgit v0.10.2 From 5e7e155483dfbf590be9b05e53ae954dced73253 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 5 Jan 2015 09:40:49 +0900 Subject: ARM: shmobile: r8a7794: Correct SDHI clock base address, labels and output-names * Correct base address of SD3 div6 clk. * Update div6 clock node labels There appears to have been some inconsistency and confusion here as on the r8a7790 these clocks are referred to as SD(HI)1 and SD(HI)2 while on the r8a7791 and r8a7794 they are referred to as SD(HI)2 and SD(HI)3. This has no run-time affect as the clock nodes are not currently used. Fixes: 8e181633e6ca96049 ("ARM: shmobile: r8a7794: Add SDHI clocks to device tree") Reported-by: Sergei Shtylyov Reported-by: Geert Uytterhoeven Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 63b918b..fff9497 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -365,19 +365,19 @@ "lb", "qspi", "sdh", "sd0", "z"; }; /* Variable factor clocks */ - sd1_clk: sd2_clk@e6150078 { + sd2_clk: sd2_clk@e6150078 { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd1"; + clock-output-names = "sd2"; }; - sd2_clk: sd3_clk@e615007c { + sd3_clk: sd3_clk@e615026c { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615007c 0 4>; + reg = <0 0xe615026c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd2"; + clock-output-names = "sd3"; }; mmc0_clk: mmc0_clk@e6150240 { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; @@ -589,7 +589,7 @@ mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7794_CLK_SD0>, + clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; clock-indices = < -- cgit v0.10.2 From 2ea0d4ec39ac837e34c07b4783a7c900940e6eaf Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 29 Jan 2015 10:41:24 +0900 Subject: ARM: shmobile: r8a7791: Correct SDHI clock labels and output-names There appears to have been some inconsistency and confusion here as on the r8a7790 these clocks are referred to as SD(HI)1 and SD(HI)2 while on the r8a7791 and r8a7794 they are referred to as SD(HI)2 and SD(HI)3. Fixes: 59e79895b95892863 ("ARM: shmobile: r8a7791: Add clocks") Reported-by: Geert Uytterhoeven Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 43fb58a..afba8af 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -874,19 +874,19 @@ }; /* Variable factor clocks */ - sd1_clk: sd2_clk@e6150078 { + sd2_clk: sd2_clk@e6150078 { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd1"; + clock-output-names = "sd2"; }; - sd2_clk: sd3_clk@e615026c { + sd3_clk: sd3_clk@e615026c { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615026c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd2"; + clock-output-names = "sd3"; }; mmc0_clk: mmc0_clk@e6150240 { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; @@ -1107,7 +1107,7 @@ mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, + clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; -- cgit v0.10.2 From 83a0731b39f3bc2421960e6169f8440ca673a20f Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 11 Dec 2014 01:42:12 +0200 Subject: ARM: shmobile: koelsch: Add DU HDMI output support Add DT nodes for the ADV7511 HDMI encoder and its HDMI output connector and configure the DISP pin group that drives the HDMI transmitter DE pin. Signed-off-by: Laurent Pinchart Acked-by: Simon Horman Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index a3c2780..624bb2c 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -258,6 +258,17 @@ system-clock-frequency = <11289600>; }; }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; }; &du { @@ -266,6 +277,11 @@ status = "okay"; ports { + port@0 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; port@1 { lvds_connector: endpoint { }; @@ -284,7 +300,7 @@ }; du_pins: du { - renesas,groups = "du_rgb666", "du_sync", "du_clk_out_0"; + renesas,groups = "du_rgb666", "du_sync", "du_disp", "du_clk_out_0"; renesas,function = "du"; }; @@ -506,6 +522,38 @@ }; }; + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio3>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + eeprom@50 { compatible = "renesas,24c02"; reg = <0x50>; -- cgit v0.10.2 From 1d66f72d2c79b76b7353ea4e42f33521fa839f81 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 3 Feb 2015 15:57:41 +0100 Subject: ARM: shmobile: r8a7790: smp: remap whole apmu region Documentation says the last register is at 0x184 (CAxCPUCMCR), so use proper length. Current APMU code accesses CAxCPUnCR which is currently outside of the remapped area. Signed-off-by: Wolfram Sang Signed-off-by: Simon Horman diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c index 9c3da13..a5bef87 100644 --- a/arch/arm/mach-shmobile/smp-r8a7790.c +++ b/arch/arm/mach-shmobile/smp-r8a7790.c @@ -37,11 +37,11 @@ static struct rcar_sysc_ch r8a7790_ca7_scu = { static struct rcar_apmu_config r8a7790_apmu_config[] = { { - .iomem = DEFINE_RES_MEM(0xe6152000, 0x88), + .iomem = DEFINE_RES_MEM(0xe6152000, 0x188), .cpus = { 0, 1, 2, 3 }, }, { - .iomem = DEFINE_RES_MEM(0xe6151000, 0x88), + .iomem = DEFINE_RES_MEM(0xe6151000, 0x188), .cpus = { 0x100, 0x0101, 0x102, 0x103 }, } }; -- cgit v0.10.2 From 98f60f8600694ce05c0cba34acce4d77acaea4f9 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 3 Feb 2015 15:57:42 +0100 Subject: ARM: shmobile: r8a7791: smp: remap whole apmu region Documentation says the last register is at 0x184 (CAxCPUCMCR), so use proper length. Current APMU code accesses CAxCPUnCR which is currently outside of the remapped area. Signed-off-by: Wolfram Sang Signed-off-by: Simon Horman diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c index 7e49e0a..de1d92d 100644 --- a/arch/arm/mach-shmobile/smp-r8a7791.c +++ b/arch/arm/mach-shmobile/smp-r8a7791.c @@ -27,7 +27,7 @@ static struct rcar_apmu_config r8a7791_apmu_config[] = { { - .iomem = DEFINE_RES_MEM(0xe6152000, 0x88), + .iomem = DEFINE_RES_MEM(0xe6152000, 0x188), .cpus = { 0, 1 }, } }; -- cgit v0.10.2 From e7cdf791dbc456329703424822e85eeb31fc1a54 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Tue, 17 Feb 2015 14:31:54 +0100 Subject: ARM: shmobile: emev2 dtsi: Add PFC information MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With this information all GPIOs can make use of the PFC functionality. Signed-off-by: Niklas Söderlund Acked-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index cc7bfe0..bb45694 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -169,12 +169,18 @@ clock-names = "sclk"; }; + pfc: pfc@e0140200 { + compatible = "renesas,pfc-emev2"; + reg = <0xe0140200 0x100>; + }; + gpio0: gpio@e0050000 { compatible = "renesas,em-gio"; reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>, <0 68 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; + gpio-ranges = <&pfc 0 0 32>; #gpio-cells = <2>; ngpios = <32>; interrupt-controller; @@ -186,6 +192,7 @@ interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>, <0 70 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; + gpio-ranges = <&pfc 0 32 32>; #gpio-cells = <2>; ngpios = <32>; interrupt-controller; @@ -197,6 +204,7 @@ interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>, <0 72 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; + gpio-ranges = <&pfc 0 64 32>; #gpio-cells = <2>; ngpios = <32>; interrupt-controller; @@ -208,6 +216,7 @@ interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>, <0 74 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; + gpio-ranges = <&pfc 0 96 32>; #gpio-cells = <2>; ngpios = <32>; interrupt-controller; @@ -219,6 +228,7 @@ interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>, <0 76 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; + gpio-ranges = <&pfc 0 128 31>; #gpio-cells = <2>; ngpios = <31>; interrupt-controller; -- cgit v0.10.2 From 4a5fcc685a84751bbec5653e942fb3d61470a66c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Tue, 17 Feb 2015 14:31:55 +0100 Subject: ARM: shmobile: emev2-kzm9d dts: Add PFC information for uart1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Configure the pinmux on kzm9d to use the serial connector for uart1. Signed-off-by: Niklas Söderlund Acked-by: Linus Walleij Acked-by: Laurent Pinchart Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index 667d323..1944627 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -94,3 +94,16 @@ vdd33a-supply = <®_3p3v>; }; }; + +&pfc { + uart1_pins: uart@e1030000 { + renesas,groups = "uart1_ctrl", "uart1_data"; + renesas,function = "uart1"; + }; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; -- cgit v0.10.2 From 41650f406cdc4a420d5c08e1b407f6420323a04b Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 6 Jan 2015 00:33:25 +0300 Subject: ARM: shmobile: r8a7790: add CAN clocks The R-Car CAN controllers can derive the CAN bus clock not only from their peripheral clock input (clkp1) but also from the other internal clock (clkp2) and external clock fed on CAN_CLK pin. Describe those clocks in the device tree, along with the USB_EXTAL clock from which clkp2 is derived. Signed-off-by: Sergei Shtylyov Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 24de994..e872854 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -838,16 +838,34 @@ clock-output-names = "audio_clk_c"; }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "usb_extal"; + }; + + /* External CAN clock */ + can_clk: can_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + clock-output-names = "can_clk"; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7790-cpg-clocks", "renesas,rcar-gen2-cpg-clocks"; reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; + clocks = <&extal_clk &usb_extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", - "z"; + "z", "rcan"; }; /* Variable factor clocks */ diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h index 9194027..ffa8c11 100644 --- a/include/dt-bindings/clock/r8a7790-clock.h +++ b/include/dt-bindings/clock/r8a7790-clock.h @@ -21,6 +21,7 @@ #define R8A7790_CLK_SD0 7 #define R8A7790_CLK_SD1 8 #define R8A7790_CLK_Z 9 +#define R8A7790_CLK_RCAN 10 /* MSTP0 */ #define R8A7790_CLK_MSIOF0 0 -- cgit v0.10.2 From 6a7742b4eea5de4af68bb62c20ca56e38b8e5b8b Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 6 Jan 2015 00:34:42 +0300 Subject: ARM: shmobile: r8a7790: add CAN DT support Define the generic R8A7790 parts of the CAN0/1 device nodes. Signed-off-by: Sergei Shtylyov Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index e872854..cd7fc05 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -792,6 +792,26 @@ }; }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7790"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7790_CLK_RCAN0>, + <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7790"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7790_CLK_RCAN1>, + <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; -- cgit v0.10.2 From b324252cc18d52d5752942a8574c22229153c58f Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 6 Jan 2015 01:24:08 +0300 Subject: ARM: shmobile: r8a7791: add CAN clocks The R-Car CAN controllers can derive the CAN bus clock not only from their peripheral clock input (clkp1) but also from the other internal clock (clkp2) and external clock fed on CAN_CLK pin. Describe those clocks in the device tree, along with the USB_EXTAL clock from which clkp2 is derived. Signed-off-by: Sergei Shtylyov Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index afba8af..1ebffef 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -862,15 +862,34 @@ status = "disabled"; }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "usb_extal"; + }; + + /* External CAN clock */ + can_clk: can_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + clock-output-names = "can_clk"; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7791-cpg-clocks", "renesas,rcar-gen2-cpg-clocks"; reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; + clocks = <&extal_clk &usb_extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "z"; + "lb", "qspi", "sdh", "sd0", "z", + "rcan"; }; /* Variable factor clocks */ diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h index f096f3f..a45a363 100644 --- a/include/dt-bindings/clock/r8a7791-clock.h +++ b/include/dt-bindings/clock/r8a7791-clock.h @@ -20,6 +20,7 @@ #define R8A7791_CLK_SDH 6 #define R8A7791_CLK_SD0 7 #define R8A7791_CLK_Z 8 +#define R8A7791_CLK_RCAN 9 /* MSTP0 */ #define R8A7791_CLK_MSIOF0 0 -- cgit v0.10.2 From 3cf0188461def8f732fefce3975cab0189220574 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 6 Jan 2015 01:25:25 +0300 Subject: ARM: shmobile: r8a7791: add CAN DT support Define the generic R8A7791 parts of the CAN0/1 device nodes. Signed-off-by: Sergei Shtylyov Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 1ebffef..ff49b95 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -816,6 +816,26 @@ }; }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7791"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, + <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7791"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_RCAN1>, + <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; -- cgit v0.10.2 From 457acc4a6ce8fe821aed4f254e72a76c88673712 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 6 Jan 2015 01:26:45 +0300 Subject: ARM: shmobile: henninger: add CAN0 DT support Define the Henninger board dependent part of the CAN0 device node. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts index d2ebf11..e33e404 100644 --- a/arch/arm/boot/dts/r8a7791-henninger.dts +++ b/arch/arm/boot/dts/r8a7791-henninger.dts @@ -141,6 +141,11 @@ renesas,groups = "vin0_data8", "vin0_clk"; renesas,function = "vin0"; }; + + can0_pins: can0 { + renesas,groups = "can0_data"; + renesas,function = "can0"; + }; }; &scif0 { @@ -307,3 +312,9 @@ }; }; }; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; -- cgit v0.10.2 From ae65a8ae4c25c7ea01204c9d033cd47da3000cf8 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 30 Dec 2014 23:20:34 +0300 Subject: ARM: shmobile: r8a7791: add ADSP clocks Add the ADSP clocks to the CPG and MSTP5 nodes of the R8A7791 device tree. Based on the original patch by Konstantin Kozhevnikov . Signed-off-by: Sergei Shtylyov Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index ff49b95..1e593a2 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -909,7 +909,7 @@ #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "z", - "rcan"; + "rcan", "adsp"; }; /* Variable factor clocks */ @@ -1164,13 +1164,16 @@ mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>; + clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>, + <&extal_clk>, <&p_clk>; #clock-cells = <1>; clock-indices = < R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 - R8A7791_CLK_THERMAL R8A7791_CLK_PWM + R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL + R8A7791_CLK_PWM >; - clock-output-names = "audmac0", "audmac1", "thermal", "pwm"; + clock-output-names = "audmac0", "audmac1", "adsp_mod", + "thermal", "pwm"; }; mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h index a45a363..8fc5dc8 100644 --- a/include/dt-bindings/clock/r8a7791-clock.h +++ b/include/dt-bindings/clock/r8a7791-clock.h @@ -21,6 +21,7 @@ #define R8A7791_CLK_SD0 7 #define R8A7791_CLK_Z 8 #define R8A7791_CLK_RCAN 9 +#define R8A7791_CLK_ADSP 10 /* MSTP0 */ #define R8A7791_CLK_MSIOF0 0 @@ -72,6 +73,7 @@ /* MSTP5 */ #define R8A7791_CLK_AUDIO_DMAC1 1 #define R8A7791_CLK_AUDIO_DMAC0 2 +#define R8A7791_CLK_ADSP_MOD 6 #define R8A7791_CLK_THERMAL 22 #define R8A7791_CLK_PWM 23 -- cgit v0.10.2 From 3453ca9e4f51a0e6865d303f4e428cb6f630594f Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 30 Dec 2014 23:21:45 +0300 Subject: ARM: shmobile: r8a7790: add ADSP clocks Add the ADSP clocks to the CPG and MSTP5 nodes of the R8A7790 device tree. Based on the original patch by Konstantin Kozhevnikov . Signed-off-by: Sergei Shtylyov Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index cd7fc05..c6c0a0c 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -885,7 +885,7 @@ #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", - "z", "rcan"; + "z", "rcan", "adsp"; }; /* Variable factor clocks */ @@ -1159,13 +1159,16 @@ mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>; + clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>, + <&extal_clk>, <&p_clk>; #clock-cells = <1>; clock-indices = < R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1 - R8A7790_CLK_THERMAL R8A7790_CLK_PWM + R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL + R8A7790_CLK_PWM >; - clock-output-names = "audmac0", "audmac1", "thermal", "pwm"; + clock-output-names = "audmac0", "audmac1", "adsp_mod", + "thermal", "pwm"; }; mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h index ffa8c11..3f2c6b1 100644 --- a/include/dt-bindings/clock/r8a7790-clock.h +++ b/include/dt-bindings/clock/r8a7790-clock.h @@ -22,6 +22,7 @@ #define R8A7790_CLK_SD1 8 #define R8A7790_CLK_Z 9 #define R8A7790_CLK_RCAN 10 +#define R8A7790_CLK_ADSP 11 /* MSTP0 */ #define R8A7790_CLK_MSIOF0 0 @@ -81,6 +82,7 @@ /* MSTP5 */ #define R8A7790_CLK_AUDIO_DMAC1 1 #define R8A7790_CLK_AUDIO_DMAC0 2 +#define R8A7790_CLK_ADSP_MOD 6 #define R8A7790_CLK_THERMAL 22 #define R8A7790_CLK_PWM 23 -- cgit v0.10.2 From b8e8ea127d00f1b0c18d8c1ae1b8388e190d5052 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sun, 22 Feb 2015 01:26:37 +0300 Subject: ARM: shmobile: r8a7794: add SDHI DT support Define the generic R8A7794 parts of the SDHI[012] device nodes. Based on the orginal patch by Shinobu Uehara . Signed-off-by: Sergei Shtylyov Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index fff9497..7a3ffa5 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -340,6 +340,30 @@ status = "disabled"; }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7794"; + reg = <0 0xee100000 0 0x200>; + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; + status = "disabled"; + }; + + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7794"; + reg = <0 0xee140000 0 0x100>; + interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; + status = "disabled"; + }; + + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7794"; + reg = <0 0xee160000 0 0x100>; + interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; -- cgit v0.10.2 From 941fe36b4071ddfd6c793bfaeed1d051175d4d80 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 24 Feb 2015 02:20:03 +0000 Subject: ARM: shmobile: r8a7790: Reference DMA channels in SDHI DT nodes Add references to the transmit and receive DMA channels in the four SDHI nodes. Signed-off-by: Laurent Pinchart Acked-by: Geert Uytterhoeven Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index c6c0a0c..5ce3564 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -496,6 +496,8 @@ reg = <0 0xee100000 0 0x200>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; + dmas = <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -504,6 +506,8 @@ reg = <0 0xee120000 0 0x200>; interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; + dmas = <&dmac1 0xc9>, <&dmac1 0xca>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -512,6 +516,8 @@ reg = <0 0xee140000 0 0x100>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; + dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -520,6 +526,8 @@ reg = <0 0xee160000 0 0x100>; interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; + dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx"; status = "disabled"; }; -- cgit v0.10.2 From ae67fa2f8b29aa0bb443ee213991f4b712d58faa Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 24 Feb 2015 02:20:19 +0000 Subject: ARM: shmobile: r8a7791: Reference DMA channels in SDHI DT nodes Add references to the transmit and receive DMA channels in the three SDHI nodes. Signed-off-by: Laurent Pinchart Acked-by: Geert Uytterhoeven Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 1e593a2..32f0506 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -485,6 +485,8 @@ reg = <0 0xee100000 0 0x200>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; + dmas = <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -493,6 +495,8 @@ reg = <0 0xee140000 0 0x100>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; + dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -501,6 +505,8 @@ reg = <0 0xee160000 0 0x100>; interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; + dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx"; status = "disabled"; }; -- cgit v0.10.2 From 66f47ed0e86d823b57ff9ab39ab18640fa053155 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 24 Feb 2015 02:20:37 +0000 Subject: ARM: shmobile: r8a7790: tidyup SDHI register size on DTSI r8a7790 SDHI ch0/ch1 has SD_DMACR which is located in 0x324. This patch updates register size Signed-off-by: Kuninori Morimoto Acked-by: Laurent Pinchart Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 5ce3564..31569ac 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -493,7 +493,7 @@ sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7790"; - reg = <0 0xee100000 0 0x200>; + reg = <0 0xee100000 0 0x328>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; dmas = <&dmac1 0xcd>, <&dmac1 0xce>; @@ -503,7 +503,7 @@ sdhi1: sd@ee120000 { compatible = "renesas,sdhi-r8a7790"; - reg = <0 0xee120000 0 0x200>; + reg = <0 0xee120000 0 0x328>; interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; dmas = <&dmac1 0xc9>, <&dmac1 0xca>; -- cgit v0.10.2 From e849b0650d4375996bfb7df70a641e2ad45a425f Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 24 Feb 2015 02:20:52 +0000 Subject: ARM: shmobile: r8a7791: tidyup SDHI register size on DTSI r8a7791 SDHI ch0/ch1 has SD_DMACR which is located in 0x324. This patch updates register size Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 32f0506..fbb33bb 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -482,7 +482,7 @@ sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7791"; - reg = <0 0xee100000 0 0x200>; + reg = <0 0xee100000 0 0x328>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; dmas = <&dmac1 0xcd>, <&dmac1 0xce>; -- cgit v0.10.2 From b621f6d458e9d6315205d5667b9eb5592ef0433c Mon Sep 17 00:00:00 2001 From: Kazuya Mizuguchi Date: Thu, 19 Feb 2015 10:42:55 -0500 Subject: ARM: shmobile: r8a7790: Fix HSUSB clock to hp_clk from mp_clk HSUSB uses hp_clk rather than mp_clk for H/W register access. Signed-off-by: Kazuya Mizuguchi Signed-off-by: Yoshihiro Kaneko [horms: updated changelog] Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 31569ac..b320252 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1,6 +1,7 @@ /* * Device Tree Source for the r8a7790 SoC * + * Copyright (C) 2015 Renesas Electronics Corporation * Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2014 Cogent Embedded Inc. * @@ -1181,7 +1182,7 @@ mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, + clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>; #clock-cells = <1>; -- cgit v0.10.2 From 118e4e6a716836378f89b66609ad50f79fd74f33 Mon Sep 17 00:00:00 2001 From: Kazuya Mizuguchi Date: Thu, 19 Feb 2015 10:43:10 -0500 Subject: ARM: shmobile: r8a7791: Fix HSUSB clock to hp_clk from mp_clk HSUSB uses hp_clk rather than mp_clk for H/W register access. Signed-off-by: Kazuya Mizuguchi Signed-off-by: Yoshihiro Kaneko [horms: updated changelog] Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index fbb33bb..de42fc5 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for the r8a7791 SoC * - * Copyright (C) 2013-2014 Renesas Electronics Corporation + * Copyright (C) 2013-2015 Renesas Electronics Corporation * Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2014 Cogent Embedded Inc. * @@ -1184,7 +1184,7 @@ mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, + clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>; #clock-cells = <1>; -- cgit v0.10.2 From fd25cdd15b7f9d1dbddb03e44b82c48d69f24200 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 11 Dec 2014 01:42:11 +0200 Subject: ARM: shmobile: lager: Add DU HDMI output support Add DT nodes for the ADV7511 HDMI encoder and its HDMI output connector. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 0c3b678..631b3f5 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -222,6 +222,17 @@ }; }; }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; }; &du { @@ -235,6 +246,11 @@ remote-endpoint = <&adv7123_in>; }; }; + port@1 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; port@2 { lvds_connector: endpoint { }; @@ -506,6 +522,38 @@ }; }; }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; }; &iic3 { -- cgit v0.10.2 From b07a27696bda1d23036b3b018bfd799f93f4e8f0 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 5 Feb 2015 00:22:02 +0900 Subject: ARM: dts: Enable wifi power-on for exynos5250-snow The Snow board has a MMC/SDIO wifi chip that is always powered but it needs a power sequence involving a reset (active low) and an enable (active high) pins. Both pins are marked as active low since the MMC simple power sequence driver asserts the pins prior to the card power up procedure and de-asserts the pins after the card has been powered. So the reset line will be left de-asserted and the enable pin will be left asserted. The chip also needs an external 32kHz reference clock to be operational that is by the MAX77686 PMIC clock. Add a simple MMC power sequence provider for the wifi MMC/SDIO slot. Signed-off-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index b9aeec4..b787120 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -229,6 +229,14 @@ power-supply = <&fet6>; backlight = <&backlight>; }; + + mmc3_pwrseq: mmc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpx0 2 GPIO_ACTIVE_LOW>, /* WIFI_RSTn */ + <&gpx0 1 GPIO_ACTIVE_LOW>; /* WIFI_EN */ + clocks = <&max77686 MAX77686_CLK_PMIC>; + clock-names = "ext_clock"; + }; }; &dp { @@ -536,12 +544,27 @@ samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; + pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4 &wifi_en &wifi_rst>; bus-width = <4>; cap-sd-highspeed; + mmc-pwrseq = <&mmc3_pwrseq>; }; &pinctrl_0 { + wifi_en: wifi-en { + samsung,pins = "gpx0-1"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + wifi_rst: wifi-rst { + samsung,pins = "gpx0-2"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + power_key_irq: power-key-irq { samsung,pins = "gpx1-3"; samsung,pin-function = <0xf>; -- cgit v0.10.2 From d0cf8bc7296f2ec7b27aa09cc358f393777075b4 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 5 Feb 2015 00:22:02 +0900 Subject: ARM: dts: Add cap-sdio-irq to wifi mmc node for exynos5250-snow Enabling SDIO IRQ signalling for the wifi MMC/SDIO slot doubles the transmission transfer rate. Signed-off-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index b787120..909edc3 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -539,6 +539,7 @@ status = "okay"; num-slots = <1>; broken-cd; + cap-sdio-irq; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; -- cgit v0.10.2 From b174e79ef518622a29ddf26923efaa5b90e2b973 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Date: Thu, 5 Feb 2015 00:29:06 +0900 Subject: ARM: dts: represent bridge and panel connection for exynos5250-snow Define videoports and use endpoints to describe the connection between the encoder, bridge and the panel, instead of using phandles. Signed-off-by: Ajay Kumar Acked-by: Inki Dae Tested-by: Rahul Sharma Tested-by: Javier Martinez Canillas Tested-by: Gustavo Padovan Tested-by: Sjoerd Simons Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 909edc3..5be966d 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -183,7 +183,20 @@ powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>; edid-emulation = <5>; - panel = <&panel>; + + ports { + port@0 { + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + + port@1 { + bridge_in: endpoint { + remote-endpoint = <&dp_out>; + }; + }; + }; }; }; @@ -228,6 +241,12 @@ compatible = "auo,b116xw03"; power-supply = <&fet6>; backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; }; mmc3_pwrseq: mmc3_pwrseq { @@ -250,7 +269,14 @@ samsung,link-rate = <0x0a>; samsung,lane-count = <2>; samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>; - bridge = <&ptn3460>; + + ports { + port@0 { + dp_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; }; &ehci { -- cgit v0.10.2 From e07eb1ec8df413f187ff5066af5feb94917cb567 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Date: Thu, 5 Feb 2015 00:29:56 +0900 Subject: ARM: dts: represent bridge and panel connection for exynos5420-peach-pit Define videoports and use endpoints to describe the connection between the encoder, bridge and the panel, instead of using phandles. Signed-off-by: Ajay Kumar Acked-by: Inki Dae Tested-by: Rahul Sharma Tested-by: Javier Martinez Canillas Tested-by: Gustavo Padovan Tested-by: Sjoerd Simons Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index c47bb70..ec86d95 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -118,6 +118,12 @@ compatible = "auo,b116xw03"; power-supply = <&tps65090_fet6>; backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; }; }; @@ -137,7 +143,14 @@ samsung,link-rate = <0x06>; samsung,lane-count = <2>; samsung,hpd-gpio = <&gpx2 6 0>; - bridge = <&ps8625>; + + ports { + port@0 { + dp_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; }; &fimd { @@ -595,8 +608,22 @@ sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>; lane-count = <2>; - panel = <&panel>; use-external-pwm; + + ports { + port@0 { + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + + port@1 { + bridge_in: endpoint { + remote-endpoint = <&dp_out>; + }; + }; + }; + }; }; -- cgit v0.10.2 From 225da7e65a03d7b730ccb201f8acb6afde5eb40b Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 5 Feb 2015 00:35:58 +0900 Subject: ARM: dts: add eMMC reset line for exynos4412-odroid-common This patch adds reset-gpios property to the eMMC slot, so the MMC driver is able to properly reset eMMC card on system restart and thus fixes system hang on software reboot. Signed-off-by: Marek Szyprowski Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index de80b5b..3c5a7ab 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -75,10 +75,18 @@ }; }; + emmc_pwrseq: pwrseq { + pinctrl-0 = <&sd1_cd>; + pinctrl-names = "default"; + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpk1 2 1>; + }; + mmc@12550000 { pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; pinctrl-names = "default"; vmmc-supply = <&ldo20_reg &buck8_reg>; + mmc-pwrseq = <&emmc_pwrseq>; status = "okay"; num-slots = <1>; @@ -413,6 +421,12 @@ }; }; +/* RSTN signal for eMMC */ +&sd1_cd { + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; +}; + &pinctrl_1 { gpio_power_key: power_key { samsung,pins = "gpx1-3"; -- cgit v0.10.2 From 1056a273ec2ce4446e38598c08ef782bbfe9bdc3 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 5 Feb 2015 00:35:58 +0900 Subject: ARM: dts: add eMMC reset line for exynos5422-odroidxu3 This patch adds reset-gpios property to the eMMC slot, so the MMC driver is able to properly reset eMMC card on system restart and thus fixes system hang on software reboot. Signed-off-by: Marek Szyprowski Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index a519c86..790fb4c 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -264,6 +264,13 @@ }; }; + emmc_pwrseq: pwrseq { + pinctrl-0 = <&emmc_nrst_pin>; + pinctrl-names = "default"; + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpd1 0 1>; + }; + i2c_2: i2c@12C80000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; @@ -298,6 +305,7 @@ &mmc_0 { status = "okay"; + mmc-pwrseq = <&emmc_pwrseq>; broken-cd; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; @@ -330,6 +338,15 @@ }; }; +&pinctrl_1 { + emmc_nrst_pin: emmc-nrst { + samsung,pins = "gpd1-0"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + &usbdrd_dwc3_0 { dr_mode = "host"; }; -- cgit v0.10.2 From 4824140f4bd1caaf900215aabe27e4bdd1677704 Mon Sep 17 00:00:00 2001 From: Imre Kaloz Date: Mon, 16 Feb 2015 13:31:04 +0100 Subject: ARM: mvebu: add Linksys WRT1900AC (Mamba) support The Linksys WRT1900AC (Mamba) is a router that has - 2 mini-PCIe slots with Marvell 88W8864 radios - 1 USB 3.0 port - 1 USB 2.0/eSATAp port - 2 Ethernet interfaces connected to a 88E6172 switch (1x WAN + 4x LAN) - 128MB NAND flash - 256MB RAM gregory.clement@free-electrons.com: - add ARM to the title - fix the reference to CONFIG_DEBUG_MVEBU_UART0_ALTERNATE - fix the unbalanced comment for the syscfg partition Signed-off-by: Imre Kaloz Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a1c776b..0d9710b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -629,6 +629,7 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-db.dtb \ armada-xp-gp.dtb \ armada-xp-lenovo-ix4-300d.dtb \ + armada-xp-linksys-mamba.dtb \ armada-xp-matrix.dtb \ armada-xp-netgear-rn2120.dtb \ armada-xp-openblocks-ax3-4.dtb \ diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts new file mode 100644 index 0000000..485a6eb --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts @@ -0,0 +1,348 @@ +/* + * Device Tree file for the Linksys WRT1900AC (Mamba). + * + * Note: this board is shipped with a new generation boot loader that + * remaps internal registers at 0xf1000000. Therefore, if earlyprintk + * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option should be + * used. + * + * Copyright (C) 2014 Imre Kaloz + * + * Based on armada-xp-axpwifiap.dts: + * + * Copyright (C) 2013 Marvell + * + * Thomas Petazzoni + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include +#include +#include "armada-xp-mv78230.dtsi" + +/ { + model = "Linksys WRT1900AC"; + compatible = "linksys,mamba", "marvell,armadaxp-mv78230", + "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */ + }; + + soc { + ranges = ; + + pcie-controller { + status = "okay"; + + /* Etron EJ168 USB 3.0 controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* First mini-PCIe port */ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + + /* Second mini-PCIe port */ + pcie@3,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; + }; + + internal-regs { + + /* J10: VCC, NC, RX, NC, TX, GND */ + serial@12000 { + status = "okay"; + }; + + sata@a0000 { + nr-ports = <1>; + status = "okay"; + }; + + ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + /* USB part of the eSATA/USB 2.0 port */ + usb@50000 { + status = "okay"; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + + tlc59116@68 { + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <2>; + compatible = "ti,tlc59116"; + reg = <0x68>; + + wan_amber@0 { + label = "mamba:amber:wan"; + reg = <0x0>; + }; + + wan_white@1 { + label = "mamba:white:wan"; + reg = <0x1>; + }; + + wlan_2g@2 { + label = "mamba:white:wlan_2g"; + reg = <0x2>; + }; + + wlan_5g@3 { + label = "mamba:white:wlan_5g"; + reg = <0x3>; + }; + + esata@4 { + label = "mamba:white:esata"; + reg = <0x4>; + }; + + usb2@5 { + label = "mamba:white:usb2"; + reg = <0x5>; + }; + + usb3_1@6 { + label = "mamba:white:usb3_1"; + reg = <0x6>; + }; + + usb3_2@7 { + label = "mamba:white:usb3_2"; + reg = <0x7>; + }; + + wps_white@8 { + label = "mamba:white:wps"; + reg = <0x8>; + }; + + wps_amber@9 { + label = "mamba:amber:wps"; + reg = <0x9>; + }; + }; + }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; /* 1MB */ + read-only; + }; + + partition@100000 { + label = "u_env"; + reg = <0x100000 0x40000>; /* 256KB */ + }; + + partition@140000 { + label = "s_env"; + reg = <0x140000 0x40000>; /* 256KB */ + }; + + partition@900000 { + label = "devinfo"; + reg = <0x900000 0x100000>; /* 1MB */ + read-only; + }; + + /* kernel1 overlaps with rootfs1 by design */ + partition@a00000 { + label = "kernel1"; + reg = <0xa00000 0x2800000>; /* 40MB */ + }; + + partition@d00000 { + label = "rootfs1"; + reg = <0xd00000 0x2500000>; /* 37MB */ + }; + + /* kernel2 overlaps with rootfs2 by design */ + partition@3200000 { + label = "kernel2"; + reg = <0x3200000 0x2800000>; /* 40MB */ + }; + + partition@3500000 { + label = "rootfs2"; + reg = <0x3500000 0x2500000>; /* 37MB */ + }; + + /* + * 38MB, last MB is for the BBT, not writable + */ + partition@5a00000 { + label = "syscfg"; + reg = <0x5a00000 0x2600000>; + }; + + /* + * Unused area between "s_env" and "devinfo". + * Moved here because otherwise the renumbered + * partitions would break the bootloader + * supplied bootargs + */ + partition@180000 { + label = "unused_area"; + reg = <0x180000 0x780000>; /* 7.5MB */ + }; + }; + + spi0: spi@10600 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "everspin,mr25h256"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <40000000>; + }; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&keys_pin>; + pinctrl-names = "default"; + + button@1 { + label = "WPS"; + linux,code = ; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + }; + + button@2 { + label = "Factory Reset Button"; + linux,code = ; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&power_led_pin>; + pinctrl-names = "default"; + + power { + label = "mamba:white:power"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + gpio_fan { + /* SUNON HA4010V4-0000-C99 */ + compatible = "gpio-fan"; + gpios = <&gpio0 24 0>; + + gpio-fan,speed-map = <0 0 + 4500 1>; + }; +}; + +&pinctrl { + + keys_pin: keys-pin { + marvell,pins = "mpp32", "mpp33"; + marvell,function = "gpio"; + }; + + power_led_pin: power-led-pin { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + gpio_fan_pin: gpio-fan-pin { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; +}; -- cgit v0.10.2 From a74cd13b807029397f7232449df929bac11fb228 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Tue, 17 Feb 2015 19:52:04 +0100 Subject: ARM: dts: dove: Fix uart[23] reg property Fix Dove's register addresses of uart2 and uart3 nodes that seem to be broken since ages due to a copy-and-paste error. Cc: # 3.7+ Signed-off-by: Sebastian Hesselbarth Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index a5441d5..3cc8b83 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -154,7 +154,7 @@ uart2: serial@12200 { compatible = "ns16550a"; - reg = <0x12000 0x100>; + reg = <0x12200 0x100>; reg-shift = <2>; interrupts = <9>; clocks = <&core_clk 0>; @@ -163,7 +163,7 @@ uart3: serial@12300 { compatible = "ns16550a"; - reg = <0x12100 0x100>; + reg = <0x12300 0x100>; reg-shift = <2>; interrupts = <10>; clocks = <&core_clk 0>; -- cgit v0.10.2 From eb472c4cdd5a798dd096095435cf1f5e16464ef8 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Tue, 17 Feb 2015 19:52:05 +0100 Subject: ARM: dts: dove: Always include gpio and interrupt-controller headers We want to enforce the use of named flags in GPIO and interrupt specifiers, include the corresponding headers to Dove's SoC dtsi. Signed-off-by: Sebastian Hesselbarth Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 3cc8b83..cae8654 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -1,5 +1,8 @@ /include/ "skeleton.dtsi" +#include +#include + #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { -- cgit v0.10.2 From 83ce82eeff06098eb14d2ece35e73c4b3d55770d Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Tue, 17 Feb 2015 19:52:06 +0100 Subject: ARM: dts: dove: Add node labels for PCIe ports 0 and 1 Add pcie[01] node labels to allow to reference them easily from board level. Signed-off-by: Sebastian Hesselbarth Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index cae8654..81209bd 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -64,7 +64,7 @@ 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ - pcie-port@0 { + pcie0: pcie-port@0 { device_type = "pci"; status = "disabled"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; @@ -82,7 +82,7 @@ interrupt-map = <0 0 0 0 &intc 16>; }; - pcie-port@1 { + pcie1: pcie-port@1 { device_type = "pci"; status = "disabled"; assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; -- cgit v0.10.2 From af6ad88acbd66ddfe31066ebcf1e02f848ec406c Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Fri, 27 Feb 2015 06:08:51 +0900 Subject: ARM: dts: Mux XMMCnDATA[0] pad correctly for Exynos5420 boards The Exynos5420 SoC has 3 sets of 8 pads used as data lines for the 3 MMC/SD/SDIO slots. These needs to be muxed as SD_n_DATA instead of a GPIO or external interrupt to allow the MMC controller to communicate with the attached cards or SDIO devices. Which data lines needs to be muxed as SD_n_DATA depends on the bus width used for data transfer: * bus-width = <1> needs SD_n_DATA[0] * bus-width = <4> needs SD_n_DATA[0-3] * bus-width = <8> needs SD_n_DATA[0-7] The Exynos5250-pinctrl.dtsi file that defines the groups of pins has SD_n_DATA[0] muxed for both sdn_bus1 and sdn_bus4 so just one of them needs to be included in the device node's pinctrl property. But Exynos5420-pinctrl has a different definition and only includes SD_n_DATA[1-3] for sdn_bus4. So for a bus-width = <4>, both sdn_bus1 and sdn_bus4 have to be in the dev pinctrl to mux all the needed pads. It seems all Exynos5420 boards had just cargo cult the pinctrl lines assuming that sdn_bus4 also included SD_n_DATA[0] and it only works because the bootloader muxes the pads correctly. But that is not the case for the devices not used by the bootloader such as WiFi modules. Add sdn_bus1 too in the nodes pinctrl to not rely on the bootloader. Suggested-by: Doug Anderson Signed-off-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index db2c1c4..b82b6fa 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -55,7 +55,7 @@ samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; vmmc-supply = <&ldo10_reg>; bus-width = <8>; cap-mmc-highspeed; @@ -68,7 +68,7 @@ samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; vmmc-supply = <&ldo19_reg>; vqmmc-supply = <&ldo13_reg>; bus-width = <4>; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index ec86d95..c4db5ae 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -687,7 +687,7 @@ samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; bus-width = <8>; }; @@ -701,7 +701,7 @@ samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; bus-width = <4>; }; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 8be3d7b..7a56852 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -81,7 +81,7 @@ samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; bus-width = <8>; cap-mmc-highspeed; }; @@ -93,7 +93,7 @@ samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index 790fb4c..edc25cf 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -312,7 +312,7 @@ samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; bus-width = <8>; cap-mmc-highspeed; }; @@ -324,7 +324,7 @@ samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; }; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 06737c6..ca73fb2 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -649,7 +649,7 @@ samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; bus-width = <8>; }; @@ -663,7 +663,7 @@ samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; bus-width = <4>; }; -- cgit v0.10.2 From 3cb18180e8e06dea06cd2b601895f42beaf00052 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Fri, 27 Feb 2015 06:08:51 +0900 Subject: ARM: dts: Add WiFi module support for Peach boards Peach Pit and Pi boards have a WiFi module that is always powered but needs toggling an enable pin and ungating a 32kHz reference clock as part of their power sequencing. Add a dev node for the SDIO slot and a MMC power sequence provider. Signed-off-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index c4db5ae..80db913 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -125,6 +125,13 @@ }; }; }; + + mmc1_pwrseq: mmc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ + clocks = <&max77802 MAX77802_CLK_32K_CP>; + clock-names = "ext_clock"; + }; }; &adc { @@ -691,6 +698,25 @@ bus-width = <8>; }; +&mmc_1 { + status = "okay"; + num-slots = <1>; + broken-cd; + cap-sdio-irq; + card-detect-delay = <200>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>, + <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>; + bus-width = <4>; + cap-sd-highspeed; + mmc-pwrseq = <&mmc1_pwrseq>; + vqmmc-supply = <&buck10_reg>; +}; + &mmc_2 { status = "okay"; num-slots = <1>; @@ -710,6 +736,13 @@ pinctrl-names = "default"; pinctrl-0 = <&mask_tpm_reset>; + wifi_en: wifi-en { + samsung,pins = "gpx0-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + max98090_irq: max98090-irq { samsung,pins = "gpx0-2"; samsung,pin-function = <0>; @@ -797,6 +830,29 @@ }; }; +&pinctrl_1 { + /* Adjust WiFi drive strengths lower for EMI */ + sd1_clk: sd1-clk { + samsung,pin-drv = <2>; + }; + + sd1_cmd: sd1-cmd { + samsung,pin-drv = <2>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pin-drv = <2>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pin-drv = <2>; + }; + + sd1_bus8: sd1-bus-width8 { + samsung,pin-drv = <2>; + }; +}; + &pinctrl_2 { pmic_dvs_2: pmic-dvs-2 { samsung,pins = "gpj4-2"; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index ca73fb2..9db2b59 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -119,6 +119,13 @@ power-supply = <&tps65090_fet6>; backlight = <&backlight>; }; + + mmc1_pwrseq: mmc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ + clocks = <&max77802 MAX77802_CLK_32K_CP>; + clock-names = "ext_clock"; + }; }; &adc { @@ -653,6 +660,25 @@ bus-width = <8>; }; +&mmc_1 { + status = "okay"; + num-slots = <1>; + broken-cd; + cap-sdio-irq; + card-detect-delay = <200>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>, + <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>; + bus-width = <4>; + cap-sd-highspeed; + mmc-pwrseq = <&mmc1_pwrseq>; + vqmmc-supply = <&buck10_reg>; +}; + &mmc_2 { status = "okay"; num-slots = <1>; @@ -672,6 +698,13 @@ pinctrl-names = "default"; pinctrl-0 = <&mask_tpm_reset>; + wifi_en: wifi-en { + samsung,pins = "gpx0-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + max98091_irq: max98091-irq { samsung,pins = "gpx0-2"; samsung,pin-function = <0>; @@ -759,6 +792,29 @@ }; }; +&pinctrl_1 { + /* Adjust WiFi drive strengths lower for EMI */ + sd1_clk: sd1-clk { + samsung,pin-drv = <2>; + }; + + sd1_cmd: sd1-cmd { + samsung,pin-drv = <2>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pin-drv = <2>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pin-drv = <2>; + }; + + sd1_bus8: sd1-bus-width8 { + samsung,pin-drv = <2>; + }; +}; + &pinctrl_2 { pmic_dvs_2: pmic-dvs-2 { samsung,pins = "gpj4-2"; -- cgit v0.10.2 From 2fad972d45c4b758763beef2860c83c2ab7ed573 Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Fri, 27 Feb 2015 06:08:52 +0900 Subject: ARM: dts: Add mclk entry for Peach boards On Peach Pit and Pi boards, the Exynos SoC XCLKOUT pin provides master clock (mclk) to the codec. So make it a clock consumer. Signed-off-by: Tushar Behera Signed-off-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 80db913..d0ee55f 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -601,6 +601,8 @@ interrupt-parent = <&gpx0>; pinctrl-names = "default"; pinctrl-0 = <&max98090_irq>; + clocks = <&pmu_system_controller 0>; + clock-names = "mclk"; }; light-sensor@44 { diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 9db2b59..7ea1d66 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -588,6 +588,8 @@ interrupt-parent = <&gpx0>; pinctrl-names = "default"; pinctrl-0 = <&max98091_irq>; + clocks = <&pmu_system_controller 0>; + clock-names = "mclk"; }; light-sensor@44 { -- cgit v0.10.2 From ca50ee8f6f7c25d3de7d5da4e7a164e21f08c828 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 26 Feb 2015 11:46:29 +0100 Subject: ARM: shmobile: ape6evm dts: Fix polarity of LEDs While the LEDs on r8a73a4/ape6evm are tied to VSUPPLY, they're driven by an N-channel MOSFET. Hence the GPIO signal should be active high. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index 0d50bef..e8f3f38 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -95,27 +95,27 @@ leds { compatible = "gpio-leds"; led1 { - gpios = <&pfc 28 GPIO_ACTIVE_LOW>; + gpios = <&pfc 28 GPIO_ACTIVE_HIGH>; label = "GNSS_EN"; }; led2 { - gpios = <&pfc 126 GPIO_ACTIVE_LOW>; + gpios = <&pfc 126 GPIO_ACTIVE_HIGH>; label = "NFC_NRST"; }; led3 { - gpios = <&pfc 132 GPIO_ACTIVE_LOW>; + gpios = <&pfc 132 GPIO_ACTIVE_HIGH>; label = "GNSS_NRST"; }; led4 { - gpios = <&pfc 232 GPIO_ACTIVE_LOW>; + gpios = <&pfc 232 GPIO_ACTIVE_HIGH>; label = "BT_WAKEUP"; }; led5 { - gpios = <&pfc 250 GPIO_ACTIVE_LOW>; + gpios = <&pfc 250 GPIO_ACTIVE_HIGH>; label = "STROBE"; }; led6 { - gpios = <&pfc 288 GPIO_ACTIVE_LOW>; + gpios = <&pfc 288 GPIO_ACTIVE_HIGH>; label = "BBRESETOUT"; }; }; -- cgit v0.10.2 From 665d79aa47cb3983b1fd14cd7c42eead5324c24e Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 26 Feb 2015 11:21:21 +0200 Subject: ARM: shmobile: marzen: Add DU external pixel clock to DT Declare the fixed 65MHz pixel clock connected to the DU clock input. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index e83d40e..540756c 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -122,6 +122,12 @@ }; }; }; + + x3_clk: x3-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <65000000>; + }; }; &du { @@ -129,6 +135,9 @@ pinctrl-names = "default"; status = "okay"; + clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>; + clock-names = "du", "dclkin.0"; + ports { port@0 { endpoint { -- cgit v0.10.2 From cd21cb46e14aae3a5d4f044c07f2c1f9d89fcd1a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 26 Feb 2015 11:21:23 +0200 Subject: ARM: shmobile: koelsch: Add DU external pixel clocks to DT Declare the fixed 148.5MHz pixel clocks connected to the DU clock inputs. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 624bb2c..75fa985 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -269,6 +269,18 @@ }; }; }; + + x2_clk: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; + + x13_clk: x13-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; }; &du { @@ -276,6 +288,13 @@ pinctrl-names = "default"; status = "okay"; + clocks = <&mstp7_clks R8A7791_CLK_DU0>, + <&mstp7_clks R8A7791_CLK_DU1>, + <&mstp7_clks R8A7791_CLK_LVDS0>, + <&x13_clk>, <&x2_clk>; + clock-names = "du.0", "du.1", "lvds.0", + "dclkin.0", "dclkin.1"; + ports { port@0 { endpoint { -- cgit v0.10.2 From 26c00ab4aae2d29b6c724a9c23d5f6cba2b20e41 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 26 Feb 2015 11:21:22 +0200 Subject: ARM: shmobile: lager: Add DU external pixel clocks to DT Declare the fixed 148.5MHz pixel clocks connected to the DU clock inputs. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 631b3f5..329bb99 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -233,6 +233,18 @@ }; }; }; + + x2_clk: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; + + x13_clk: x13-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; }; &du { @@ -240,6 +252,15 @@ pinctrl-names = "default"; status = "okay"; + clocks = <&mstp7_clks R8A7790_CLK_DU0>, + <&mstp7_clks R8A7790_CLK_DU1>, + <&mstp7_clks R8A7790_CLK_DU2>, + <&mstp7_clks R8A7790_CLK_LVDS0>, + <&mstp7_clks R8A7790_CLK_LVDS1>, + <&x13_clk>, <&x2_clk>; + clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", + "dclkin.0", "dclkin.1"; + ports { port@0 { endpoint { -- cgit v0.10.2 From 1fc580158714b19fbc3a592a126c58e06728763d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 26 Feb 2015 16:08:33 +0200 Subject: ARM: shmobile: r8a7794: alt: Fix ethernet controller PHY IRQ line The PHY IRQ line is connected to external IRQ8, not IRQ0. Fix DT accordingly. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 25bf434..928cfa6 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -51,7 +51,7 @@ phy1: ethernet-phy@1 { reg = <1>; interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; }; }; -- cgit v0.10.2 From 75a499a651bb5838320a7e2542ed6f8181e60976 Mon Sep 17 00:00:00 2001 From: Ryo Kataoka Date: Thu, 19 Feb 2015 22:29:06 +0900 Subject: ARM: shmobile: r8a7791: Fix IPMMU-GP clock to device tree Signed-off-by: Ryo Kataoka Signed-off-by: Yoshihiro Kaneko Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index de42fc5..e899f79 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1202,7 +1202,7 @@ mstp8_clks: mstp8_clks@e6150990 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zg_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>, + clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; clock-indices = < -- cgit v0.10.2 From 03bb95124e100ecccd62604f3261584c6977f1e5 Mon Sep 17 00:00:00 2001 From: Beniamino Galvani Date: Sun, 1 Mar 2015 20:39:51 +0100 Subject: ARM: dts: meson: add node for SPIFC This adds a node for the SPI Flash Controller to the Amlogic Meson DTS. Signed-off-by: Beniamino Galvani Signed-off-by: Carlo Caione Acked-by: Mark Brown diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index b67ede5..43b7896 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -150,5 +150,14 @@ interrupts = <0 15 1>; status = "disabled"; }; + + spifc: spi@c1108c80 { + compatible = "amlogic,meson6-spifc"; + reg = <0xc1108c80 0x80>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk81>; + status = "disabled"; + }; }; }; /* end of / */ -- cgit v0.10.2 From 2345d5058344b0dcd02bb602d64e796fcdbc8f34 Mon Sep 17 00:00:00 2001 From: Beniamino Galvani Date: Sun, 1 Mar 2015 20:45:37 +0100 Subject: ARM: dts: meson: enable Ethernet controller Add a node for the Ethernet controller to Meson DTS file and enable it on the Geniatech ATV1200 board. Signed-off-by: Beniamino Galvani Signed-off-by: Carlo Caione diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 43b7896..5484413 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -159,5 +159,16 @@ clocks = <&clk81>; status = "disabled"; }; + + ethmac: ethernet@c9410000 { + compatible = "amlogic,meson6-dwmac", "snps,dwmac"; + reg = <0xc9410000 0x10000 + 0xc1108108 0x4>; + interrupts = <0 8 1>; + interrupt-names = "macirq"; + clocks = <&clk81>; + clock-names = "stmmaceth"; + status = "disabled"; + }; }; }; /* end of / */ diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts index d7d351a..1237faa 100644 --- a/arch/arm/boot/dts/meson6-atv1200.dts +++ b/arch/arm/boot/dts/meson6-atv1200.dts @@ -64,3 +64,7 @@ &uart_AO { status = "okay"; }; + +ðmac { + status = "okay"; +}; -- cgit v0.10.2 From d9fea88c4f8ded4355018625f2c886c3c7c9b63d Mon Sep 17 00:00:00 2001 From: Beniamino Galvani Date: Sat, 17 Jan 2015 19:15:16 +0100 Subject: ARM: dts: meson8: add pinctrl node Add pinctrl node to the DTSI file for meson8 and sub-nodes for some standard mux configurations. Signed-off-by: Beniamino Galvani Signed-off-by: Carlo Caione diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 1f442a7..a2ddcb8 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -43,6 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include /include/ "meson.dtsi" / { @@ -89,4 +90,71 @@ compatible = "fixed-clock"; clock-frequency = <141666666>; }; + + pinctrl: pinctrl@c1109880 { + compatible = "amlogic,meson8-pinctrl"; + reg = <0xc1109880 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio: banks@c11080b0 { + reg = <0xc11080b0 0x28>, + <0xc11080e8 0x18>, + <0xc1108120 0x18>, + <0xc1108030 0x30>; + reg-names = "mux", "pull", "pull-enable", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio_ao: ao-bank@c1108030 { + reg = <0xc8100014 0x4>, + <0xc810002c 0x4>, + <0xc8100024 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + uart_ao_a_pins: uart_ao_a { + mux { + groups = "uart_tx_ao_a", "uart_rx_ao_a"; + function = "uart_ao"; + }; + }; + + i2c_ao_pins: i2c_mst_ao { + mux { + groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; + function = "i2c_mst_ao"; + }; + }; + + spi_nor_pins: nor { + mux { + groups = "nor_d", "nor_q", "nor_c", "nor_cs"; + function = "nor"; + }; + }; + + ir_recv_pins: remote { + mux { + groups = "remote_input"; + function = "remote"; + }; + }; + + eth_pins: ethernet { + mux { + groups = "eth_tx_clk_50m", "eth_tx_en", + "eth_txd1", "eth_txd0", + "eth_rx_clk_in", "eth_rx_dv", + "eth_rxd1", "eth_rxd0", "eth_mdio", + "eth_mdc"; + function = "ethernet"; + }; + }; + }; + }; /* end of / */ -- cgit v0.10.2 From b3e67c9112f6268045f78a61274fda2c7250c5c9 Mon Sep 17 00:00:00 2001 From: Beniamino Galvani Date: Sun, 1 Mar 2015 19:19:26 +0100 Subject: ARM: dts: meson: add DTS file for MINIX NEO-X8 Add a DTS file for MINIX NEO-X8, a Meson8-based digital media player. Signed-off-by: Beniamino Galvani Signed-off-by: Carlo Caione diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a1c776b..bcde192 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -199,6 +199,8 @@ dtb-$(CONFIG_ARCH_LPC32XX) += \ ea3250.dtb phy3250.dtb dtb-$(CONFIG_MACH_MESON6) += \ meson6-atv1200.dtb +dtb-$(CONFIG_MACH_MESON8) += \ + meson8-minix-neo-x8.dtb dtb-$(CONFIG_ARCH_MMP) += \ pxa168-aspenite.dtb \ pxa910-dkb.dtb \ diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/meson8-minix-neo-x8.dts new file mode 100644 index 0000000..4f536bb --- /dev/null +++ b/arch/arm/boot/dts/meson8-minix-neo-x8.dts @@ -0,0 +1,128 @@ +/* + * Copyright 2014 Beniamino Galvani + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include +#include "meson8.dtsi" + +/ { + model = "MINIX NEO-X8"; + compatible = "minix,neo-x8", "amlogic,meson8"; + + aliases { + serial0 = &uart_AO; + }; + + memory { + reg = <0x40000000 0x80000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + + blue { + label = "x8:blue:power"; + gpios = <&gpio_ao GPIO_TEST_N GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&i2c_AO { + status = "okay"; + pinctrl-0 = <&i2c_ao_pins>; + pinctrl-names = "default"; + + pmic@32 { + compatible = "ricoh,rn5t618"; + reg = <0x32>; + + regulators { + }; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&spifc { + status = "okay"; + pinctrl-0 = <&spi_nor_pins>; + pinctrl-names = "default"; + + spi-flash@0 { + compatible = "mxicy,mx25l1606e"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <30000000>; + + partition@0 { + label = "boot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "env"; + reg = <0x100000 0x10000>; + }; + }; +}; + +&ir_receiver { + status = "okay"; + pinctrl-0 = <&ir_recv_pins>; + pinctrl-names = "default"; +}; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_pins>; + pnictrl-names = "default"; +}; -- cgit v0.10.2 From 96c110aaa7a9db17d5893a6416def2233ba769fb Mon Sep 17 00:00:00 2001 From: Jonathan Richardson Date: Mon, 2 Mar 2015 14:41:10 -0800 Subject: ARM: dts: Enable Broadcom Cygnus BCM958305K DT file to enable the Wireless Audio reference design based on the BCM58305. Reviewed-by: Ray Jui Reviewed-by: Scott Branden Tested-by: Scott Branden Signed-off-by: Jonathan Richardson Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a1c776b..2604d7c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -65,7 +65,8 @@ dtb-$(CONFIG_ARCH_BCM_63XX) += \ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ bcm911360_entphn.dtb \ bcm911360k.dtb \ - bcm958300k.dtb + bcm958300k.dtb \ + bcm958305k.dtb dtb-$(CONFIG_ARCH_BCM_MOBILE) += \ bcm28155-ap.dtb \ bcm21664-garnet.dtb diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts new file mode 100644 index 0000000..56b429a --- /dev/null +++ b/arch/arm/boot/dts/bcm958305k.dts @@ -0,0 +1,53 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-cygnus.dtsi" + +/ { + model = "Cygnus Wireless Audio (BCM958305K)"; + compatible = "brcm,bcm58305", "brcm,cygnus"; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = &uart3; + bootargs = "console=ttyS0,115200"; + }; + + uart3: serial@18023000 { + status = "okay"; + }; +}; -- cgit v0.10.2 From 1a1b9d2571fb521985616573bfa6bdb5f80c8b32 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Tue, 17 Feb 2015 19:52:07 +0100 Subject: ARM: dts: dove: Add some more common pinctrl settings This add common pinctrl settings for pcie[01]_clkreq, spi1, i2c[23], and internal i2c mux. These settings have either one or two options only, so put them into the SoC dtsi instead of repeating them on board level. Signed-off-by: Sebastian Hesselbarth Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 81209bd..9ad8295 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -451,6 +451,11 @@ marvell,function = "gpio"; }; + pmx_pcie1_clkreq: pmx-pcie1-clkreq { + marvell,pins = "mpp9"; + marvell,function = "pex1"; + }; + pmx_gpio_10: pmx-gpio-10 { marvell,pins = "mpp10"; marvell,function = "gpio"; @@ -461,6 +466,11 @@ marvell,function = "gpio"; }; + pmx_pcie0_clkreq: pmx-pcie0-clkreq { + marvell,pins = "mpp11"; + marvell,function = "pex0"; + }; + pmx_gpio_12: pmx-gpio-12 { marvell,pins = "mpp12"; marvell,function = "gpio"; @@ -566,6 +576,18 @@ marvell,function = "gpio"; }; + pmx_spi1_4_7: pmx-spi1-4-7 { + marvell,pins = "mpp4", "mpp5", + "mpp6", "mpp7"; + marvell,function = "spi1"; + }; + + pmx_spi1_20_23: pmx-spi1-20-23 { + marvell,pins = "mpp20", "mpp21", + "mpp22", "mpp23"; + marvell,function = "spi1"; + }; + pmx_uart1: pmx-uart1 { marvell,pins = "mpp_uart1"; marvell,function = "uart1"; @@ -585,6 +607,36 @@ marvell,pins = "mpp_nand"; marvell,function = "gpo"; }; + + pmx_i2c1: pmx-i2c1 { + marvell,pins = "mpp17", "mpp19"; + marvell,function = "twsi"; + }; + + pmx_i2c2: pmx-i2c2 { + marvell,pins = "mpp_audio1"; + marvell,function = "twsi"; + }; + + pmx_ssp_i2c2: pmx-ssp-i2c2 { + marvell,pins = "mpp_audio1"; + marvell,function = "ssp/twsi"; + }; + + pmx_i2cmux_0: pmx-i2cmux-0 { + marvell,pins = "twsi"; + marvell,function = "twsi-opt1"; + }; + + pmx_i2cmux_1: pmx-i2cmux-1 { + marvell,pins = "twsi"; + marvell,function = "twsi-opt2"; + }; + + pmx_i2cmux_2: pmx-i2cmux-2 { + marvell,pins = "twsi"; + marvell,function = "twsi-opt3"; + }; }; core_clk: core-clocks@d0214 { -- cgit v0.10.2 From 1d7b0839941c6ee883c001716611949448f20a79 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 26 Feb 2015 10:51:17 +0100 Subject: ARM: mvebu: Fix MPIC unit address The unit-address is supposed to be equal the first reg address, which is not the case for the MPIC, that uses the mbus-controller one. Fix this. Signed-off-by: Maxime Ripard Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index cb30fb8..a7f2c7b 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -368,7 +368,7 @@ reg = <0x20000 0x100>, <0x20180 0x20>; }; - mpic: interrupt-controller@20000 { + mpic: interrupt-controller@20a00 { compatible = "marvell,mpic"; reg = <0x20a00 0x2d0>, <0x21070 0x58>; #interrupt-cells = <1>; -- cgit v0.10.2 From ef34481712067205ca3a9ca52c8484550702b4e2 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Wed, 25 Feb 2015 19:00:19 +0100 Subject: ARM: Kirkwood: enable GPIO fan alarm support for 2Big Network v2 On the LaCie 2Big Network v2 (net2big_v2) board, the fan alarm is not wired to the I2C fan controller but to a separe GPIO. This GPIO can be controlled by using the gpio-fan driver. This patch adds the gpio-fan alarm description in the net2big_v2 DTS. Signed-off-by: Simon Guinot Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/kirkwood-net2big.dts b/arch/arm/boot/dts/kirkwood-net2big.dts index 53dc37a..13a4477 100644 --- a/arch/arm/boot/dts/kirkwood-net2big.dts +++ b/arch/arm/boot/dts/kirkwood-net2big.dts @@ -27,6 +27,11 @@ device_type = "memory"; reg = <0x00000000 0x10000000>; }; + + fan { + compatible = "gpio-fan"; + alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; }; ®ulators { -- cgit v0.10.2 From 924361249de339123e15d78c1d95dd450a6e3f03 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 28 Feb 2015 21:20:48 +0100 Subject: ARM: ARMADA XP: WRT1900AC: Add support for the Ethernet switch Add a DSA section to the DT blob representing the Ethernet switch. Signed-off-by: Andrew Lunn Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts index 485a6eb..a2cf215 100644 --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts @@ -327,6 +327,51 @@ gpio-fan,speed-map = <0 0 4500 1>; }; + + dsa@0 { + compatible = "marvell,dsa"; + #address-cells = <2>; + #size-cells = <0>; + + dsa,ethernet = <ð0>; + dsa,mii-bus = <&mdio>; + + switch@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0>; /* MDIO address 0, switch 0 in tree */ + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@4 { + reg = <4>; + label = "internet"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + }; + }; + }; }; &pinctrl { -- cgit v0.10.2 From 2a2dbd8b411028151a8adb09db3395a95769b4bb Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 3 Mar 2015 11:16:45 +0100 Subject: ARM: mvebu: a385-db-ap: Enable the NAND The Armada 385 Access Point Development Board has a 1GB NAND SLC chip from Micron as its main storage. Enable it. Signed-off-by: Maxime Ripard Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts index 57b9119..9e33f7d 100644 --- a/arch/arm/boot/dts/armada-385-db-ap.dts +++ b/arch/arm/boot/dts/armada-385-db-ap.dts @@ -150,6 +150,19 @@ phy = <&phy0>; phy-mode = "rgmii-id"; }; + + nfc: flash@d0000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <1>; + + num-cs = <1>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + }; }; pcie-controller { -- cgit v0.10.2 From a165c3b63b6f24fdc47c270db5f8b1a48b69c1b6 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 3 Mar 2015 15:40:57 +0100 Subject: ARM: mvebu: fix usb@ unit address on Armada 38x to match register address On Marvell Armada 38x, the USB2 controller registers are at 0x58000, so the corresponding Device Tree node should have a unit address of 58000, and not 50000. We were using 50000 due to an incorrect copy/pastebin of Armada 370/XP code. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts index 16512ef..af6c74e 100644 --- a/arch/arm/boot/dts/armada-388-db.dts +++ b/arch/arm/boot/dts/armada-388-db.dts @@ -99,7 +99,7 @@ phy-mode = "rgmii-id"; }; - usb@50000 { + usb@58000 { status = "ok"; }; diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts index 590b383..3ff0573 100644 --- a/arch/arm/boot/dts/armada-388-gp.dts +++ b/arch/arm/boot/dts/armada-388-gp.dts @@ -135,7 +135,7 @@ }; /* CON4 */ - usb@50000 { + usb@58000 { vcc-supply = <®_usb2_0_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index a7f2c7b..1db118b 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -435,7 +435,7 @@ status = "disabled"; }; - usb@50000 { + usb@58000 { compatible = "marvell,orion-ehci"; reg = <0x58000 0x500>; interrupts = ; -- cgit v0.10.2 From 8a48dccb8350ad6c1f91b9f8306e555cd38b25e8 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 3 Mar 2015 15:40:58 +0100 Subject: ARM: mvebu: add missing UART labels on Armada 38x The Armada 38x had a label for UART0, but not UART1. This commit fixes that. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 1db118b..2fedfc7 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -216,7 +216,7 @@ status = "disabled"; }; - serial@12100 { + uart1: serial@12100 { compatible = "snps,dw-apb-uart"; reg = <0x12100 0x100>; reg-shift = <2>; -- cgit v0.10.2 From 43e58e90f8f9c69a453b9889f66e4562eb99b32b Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 3 Mar 2015 15:40:59 +0100 Subject: ARM: mvebu: add UART labels to Armada 375 This commit adds the standard uart0 and uart1 DT labels to the Device Tree description of the Marvell Armada 375 SoC. Signed-off-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index ba3c57e..6307e80 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -276,7 +276,7 @@ status = "disabled"; }; - serial@12000 { + uart0: serial@12000 { compatible = "snps,dw-apb-uart"; reg = <0x12000 0x100>; reg-shift = <2>; @@ -286,7 +286,7 @@ status = "disabled"; }; - serial@12100 { + uart1: serial@12100 { compatible = "snps,dw-apb-uart"; reg = <0x12100 0x100>; reg-shift = <2>; -- cgit v0.10.2 From 9574b2fb1cf7f6bab48714f5cf9e5382b8ca1685 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 3 Mar 2015 15:41:00 +0100 Subject: ARM: mvebu: remove aliases for Ethernet devices on Armada 370/375/38x/XP Having aliases for Ethernet devices is useless, since the networking subsystem unfortunately doesn't care about aliases to name network interfaces. Note that the 'aliases' nodes in armada-370-xp.dtsi and armada-xp.dtsi become empty, but that we keep it as is since a followup patch will re-add some aliases to it. Signed-off-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 8a322ad..d36b1e5 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -59,8 +59,6 @@ compatible = "marvell,armada-370-xp"; aliases { - eth0 = ð0; - eth1 = ð1; }; cpus { diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 6307e80..0d02251 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -60,8 +60,6 @@ gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; - ethernet0 = ð0; - ethernet1 = ð1; }; clocks { diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 2fedfc7..f74bb01 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -59,9 +59,6 @@ aliases { gpio0 = &gpio0; gpio1 = &gpio1; - ethernet0 = ð0; - ethernet1 = ð1; - ethernet2 = ð2; }; soc { diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 4a7cbed..8479fdc 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -57,7 +57,6 @@ gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; - eth3 = ð3; }; cpus { diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 36ce63a..661d54c 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -57,7 +57,6 @@ gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; - eth3 = ð3; }; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 8291723..975ae64 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -57,7 +57,6 @@ compatible = "marvell,armadaxp", "marvell,armada-370-xp"; aliases { - eth2 = ð2; }; soc { -- cgit v0.10.2 From bf6acf1657ab906531549d3e8fbe9027d90e4c86 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 3 Mar 2015 15:41:01 +0100 Subject: ARM: mvebu: add serial port aliases on Armada 370/375/38x/XP This commit adds 'serialX' aliases for the various serial ports on Armada 370, 375, 38x and XP platforms. It will allow the usage of the stdout-path property. Signed-off-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index d36b1e5..1058cf6 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -59,6 +59,8 @@ compatible = "marvell,armada-370-xp"; aliases { + serial0 = &uart0; + serial1 = &uart1; }; cpus { diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 0d02251..6420693 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -60,6 +60,8 @@ gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; + serial0 = &uart0; + serial1 = &uart1; }; clocks { diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index f74bb01..1a2dc37 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -59,6 +59,8 @@ aliases { gpio0 = &gpio0; gpio1 = &gpio1; + serial0 = &uart0; + serial1 = &uart1; }; soc { diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 975ae64..bbabee5 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -57,6 +57,8 @@ compatible = "marvell,armadaxp", "marvell,armada-370-xp"; aliases { + serial2 = &uart2; + serial3 = &uart3; }; soc { -- cgit v0.10.2 From 9552203cb08b9802e17f19bd5c786d6a2281a04a Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 3 Mar 2015 15:41:02 +0100 Subject: ARM: mvebu: use stdout-path in all armada-*.dts This commit adds the stdout-path property in /chosen for all Armada boards that were not yet carrying this property, and gets rid of /chosen/bootargs which becomes unneeded: earlyprintk should not be used by default, and the console= parameter is replaced by the /chosen/stdout-path property. Signed-off-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index e993c46..485ecf8 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -55,7 +55,7 @@ compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index b10ceb4..0f40d5d 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -51,7 +51,7 @@ compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index 3f8cc38..a312078 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -53,7 +53,7 @@ compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index 99eb8a0..00540f2 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -53,7 +53,7 @@ compatible = "netgear,readynas-104", "marvell,armada370", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 6ae36a3..19475e6 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -64,7 +64,7 @@ compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts index 59f74e6..b42b767 100644 --- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts +++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts @@ -67,8 +67,7 @@ "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts index 0440891..4eabc9c 100644 --- a/arch/arm/boot/dts/armada-375-db.dts +++ b/arch/arm/boot/dts/armada-375-db.dts @@ -55,7 +55,7 @@ compatible = "marvell,a375-db", "marvell,armada375"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts index 9e33f7d..d6b0f7d 100644 --- a/arch/arm/boot/dts/armada-385-db-ap.dts +++ b/arch/arm/boot/dts/armada-385-db-ap.dts @@ -49,8 +49,7 @@ compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x"; chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart1; + stdout-path = "serial1:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts index af6c74e..51d1623 100644 --- a/arch/arm/boot/dts/armada-388-db.dts +++ b/arch/arm/boot/dts/armada-388-db.dts @@ -54,7 +54,7 @@ "marvell,armada385", "marvell,armada380"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts index 3ff0573..78514ab 100644 --- a/arch/arm/boot/dts/armada-388-gp.dts +++ b/arch/arm/boot/dts/armada-388-gp.dts @@ -48,8 +48,7 @@ compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380"; chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts index 1ecf511..1dc6e23 100644 --- a/arch/arm/boot/dts/armada-388-rd.dts +++ b/arch/arm/boot/dts/armada-388-rd.dts @@ -55,7 +55,7 @@ "marvell,armada385","marvell,armada380"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts index c1fbab2..dfd782b 100644 --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts @@ -59,7 +59,7 @@ compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index 48bdafe..1037824 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -64,7 +64,7 @@ compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 206aebb..565227e 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -65,7 +65,7 @@ compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts index 5fb3c8b..06a6a6c 100644 --- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts +++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts @@ -54,8 +54,7 @@ "marvell,armadaxp", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts index 56f958e..f894bc8 100644 --- a/arch/arm/boot/dts/armada-xp-matrix.dts +++ b/arch/arm/boot/dts/armada-xp-matrix.dts @@ -52,7 +52,7 @@ compatible = "marvell,axp-matrix", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts index 99cb9a8..1516fc2 100644 --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts @@ -53,7 +53,7 @@ compatible = "netgear,readynas-2120", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 0c76d9f..e3b08fb 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -54,7 +54,7 @@ compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts index e9fb225..6063428 100644 --- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts +++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts @@ -67,8 +67,7 @@ "marvell,armadaxp", "marvell,armada-370-xp"; chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; memory { -- cgit v0.10.2 From 24c2573bdb9203259a822a4e3ed90795b273d3ab Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 3 Mar 2015 15:41:03 +0100 Subject: ARM: mvebu: fix unit address of MPIC nodes The Device Tree nodes describing the MPIC nodes on Armada 370, 375, 38x and XP had a unit address that did not match the first reg property, as suggested by the ePAPR. This commit fixes that. [gregory.clement@free-electrons.com: removed the armada-38x part, as it was already applied by a previous patch] Signed-off-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 1058cf6..7b3393e 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -223,7 +223,7 @@ <0x20250 0x8>; }; - mpic: interrupt-controller@20000 { + mpic: interrupt-controller@20a00 { compatible = "marvell,mpic"; #interrupt-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 27397f1..50f259b 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -232,7 +232,7 @@ reg = <0x18330 0x4>; }; - interrupt-controller@20000 { + interrupt-controller@20a00 { reg = <0x20a00 0x1d0>, <0x21870 0x58>; }; diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 6420693..c6fedf2 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -394,7 +394,7 @@ reg = <0x20000 0x100>, <0x20180 0x20>; }; - mpic: interrupt-controller@20000 { + mpic: interrupt-controller@20a00 { compatible = "marvell,mpic"; reg = <0x20a00 0x2d0>, <0x21070 0x58>; #interrupt-cells = <1>; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index bbabee5..ff47345 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -154,7 +154,7 @@ clocks = <&coreclk 1>; }; - interrupt-controller@20000 { + interrupt-controller@20a00 { reg = <0x20a00 0x2d0>, <0x21070 0x58>; }; -- cgit v0.10.2 From 538da83ddbeaa422a48e9bd0a12a0bc246c567f4 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 3 Mar 2015 15:41:12 +0100 Subject: ARM: mvebu: add Device Tree files for Armada 39x SoC and board This commit adds the Device Tree files for the Armada 39x family of processors, as well as one Armada 398 Development Board. Like for other Marvell EBU families, a common armada-39x.dtsi contains the description of the common features of all Armada 39x SoCs, while armada-390.dtsi and armada-398.dtsi respectively describe the specificities of those SoCs. Finally, an armada-398-db.dts file is added to describe the Armada 398 Development Board itself. So far, the following features are supported: * SMP: dual Cortex-A9 * Basic ARM IPs: SCU, timer, GIC, L2 cache * Basic Marvell IPs: pin-muxing, clocks, system controller, MBus controller, MPIC interrupt controller, timer, CPU reset for SMP, PMSU. * I2C * SPI * SDHCI * XOR * NAND * UART * PCIe Additional features will be supported in the future. Signed-off-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0d9710b..b9c3f8c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -624,6 +624,8 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \ armada-388-db.dtb \ armada-388-gp.dtb \ armada-388-rd.dtb +dtb-$(CONFIG_MACH_ARMADA_39X) += \ + armada-398-db.dtb dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-axpwifiap.dtb \ armada-xp-db.dtb \ diff --git a/arch/arm/boot/dts/armada-390.dtsi b/arch/arm/boot/dts/armada-390.dtsi new file mode 100644 index 0000000..094e39c --- /dev/null +++ b/arch/arm/boot/dts/armada-390.dtsi @@ -0,0 +1,57 @@ +/* + * Device Tree Include file for Marvell Armada 390 SoC. + * + * Copyright (C) 2015 Marvell + * + * Thomas Petazzoni + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "armada-39x.dtsi" + +/ { + soc { + internal-regs { + pinctrl@18000 { + compatible = "marvell,mv88f6920-pinctrl"; + reg = <0x18000 0x20>; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/armada-398-db.dts new file mode 100644 index 0000000..bbf8375 --- /dev/null +++ b/arch/arm/boot/dts/armada-398-db.dts @@ -0,0 +1,153 @@ +/* + * Device Tree Include file for Marvell Armada 398 Development Board + * + * Copyright (C) 2015 Marvell + * + * Thomas Petazzoni + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-398.dtsi" + +/ { + model = "Marvell Armada 398 Development Board"; + compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2 GB */ + }; + + soc { + ranges = ; + + internal-regs { + spi@10680 { + status = "okay"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "n25q128a13"; + reg = <0>; + spi-max-frequency = <108000000>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x400000>; + }; + + partition@400000 { + label = "Filesystem"; + reg = <0x400000 0x1000000>; + }; + }; + }; + + i2c@11000 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = <100000>; + }; + + serial@12000 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + serial@12100 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + flash@d0000 { + status = "okay"; + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; + }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + + pcie@2,0 { + status = "okay"; + }; + + pcie@3,0 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-398.dtsi b/arch/arm/boot/dts/armada-398.dtsi new file mode 100644 index 0000000..fdc2591 --- /dev/null +++ b/arch/arm/boot/dts/armada-398.dtsi @@ -0,0 +1,60 @@ +/* + * Device Tree Include file for Marvell Armada 398 SoC. + * + * Copyright (C) 2015 Marvell + * + * Thomas Petazzoni + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "armada-39x.dtsi" + +/ { + compatible = "marvell,armada398", "marvell,armada390"; + + soc { + internal-regs { + pinctrl@18000 { + compatible = "marvell,mv88f6928-pinctrl"; + reg = <0x18000 0x20>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi new file mode 100644 index 0000000..0e85fc1 --- /dev/null +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -0,0 +1,508 @@ +/* + * Device Tree Include file for Marvell Armada 39x family of SoCs. + * + * Copyright (C) 2015 Marvell + * + * Thomas Petazzoni + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton.dtsi" +#include +#include + +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + +/ { + model = "Marvell Armada 39x family SoC"; + compatible = "marvell,armada390"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,armada-390-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + soc { + compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus", + "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + controller = <&mbusc>; + interrupt-parent = <&gic>; + pcie-mem-aperture = <0xe0000000 0x8000000>; + pcie-io-aperture = <0xe8000000 0x100000>; + + bootrom { + compatible = "marvell,bootrom"; + reg = ; + }; + + internal-regs { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + + L2: cache-controller@8000 { + compatible = "arm,pl310-cache"; + reg = <0x8000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + scu@c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xc000 0x100>; + }; + + timer@c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xc600 0x20>; + interrupts = ; + clocks = <&coreclk 2>; + }; + + gic: interrupt-controller@d000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + interrupt-controller; + reg = <0xd000 0x1000>, + <0xc100 0x100>; + }; + + spi0: spi@10600 { + compatible = "marvell,orion-spi"; + reg = <0x10600 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + compatible = "marvell,orion-spi"; + reg = <0x10680 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c2: i2c@11200 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11200 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c3: i2c@11300 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11300 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart1: serial@12100 { + compatible = "snps,dw-apb-uart"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart2: serial@12200 { + compatible = "snps,dw-apb-uart"; + reg = <0x12200 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart3: serial@12300 { + compatible = "snps,dw-apb-uart"; + reg = <0x12300 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + pinctrl@18000 { + i2c0_pins: i2c0-pins { + marvell,pins = "mpp2", "mpp3"; + marvell,function = "i2c0"; + }; + + uart0_pins: uart0-pins { + marvell,pins = "mpp0", "mpp1"; + marvell,function = "ua0"; + }; + + uart1_pins: uart1-pins { + marvell,pins = "mpp19", "mpp20"; + marvell,function = "ua1"; + }; + + spi1_pins: spi1-pins { + marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59"; + marvell,function = "spi1"; + }; + + nand_pins: nand-pins { + marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", + "mpp38", "mpp28", "mpp40", "mpp42", + "mpp35", "mpp36", "mpp25", "mpp30", + "mpp32"; + marvell,function = "dev"; + }; + }; + + system-controller@18200 { + compatible = "marvell,armada-390-system-controller", + "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x100>; + }; + + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-390-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + + coreclk: mvebu-sar@18600 { + compatible = "marvell,armada-390-core-clock"; + reg = <0x18600 0x04>; + #clock-cells = <1>; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; + }; + + mpic: interrupt-controller@20a00 { + compatible = "marvell,mpic"; + reg = <0x20a00 0x2d0>, <0x21070 0x58>; + #interrupt-cells = <1>; + #size-cells = <1>; + interrupt-controller; + msi-controller; + interrupts = ; + }; + + timer@20300 { + compatible = "marvell,armada-380-timer", + "marvell,armada-xp-timer"; + reg = <0x20300 0x30>, <0x21040 0x30>; + interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <&mpic 5>, + <&mpic 6>; + clocks = <&coreclk 2>, <&coreclk 5>; + clock-names = "nbclk", "fixed"; + }; + + cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x10>; + }; + + pmsu@22000 { + compatible = "marvell,armada-390-pmsu", + "marvell,armada-380-pmsu"; + reg = <0x22000 0x1000>; + }; + + xor@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60a00 0x100>; + clocks = <&gateclk 22>; + status = "okay"; + + xor00 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gateclk 28>; + status = "okay"; + + xor10 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + flash@d0000 { + compatible = "marvell,armada370-nand"; + reg = <0xd0000 0x54>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = ; + clocks = <&coredivclk 0>; + status = "disabled"; + }; + + sdhci@d8000 { + compatible = "marvell,armada-380-sdhci"; + reg = <0xd8000 0x1000>, <0xdc000 0x100>; + interrupts = ; + clocks = <&gateclk 17>; + mrvl,clk-delay-cycles = <0x1F>; + status = "disabled"; + }; + + coredivclk: clock@e4250 { + compatible = "marvell,armada-390-corediv-clock", + "marvell,armada-380-corediv-clock"; + reg = <0xe4250 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; + }; + + pcie-controller { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; + + /* + * This port can be either x4 or x1. When + * configured in x4 by the bootloader, then + * pcie@4,0 is not available. + */ + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + /* x1 port */ + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + /* x1 port */ + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + /* + * x1 port only available when pcie@1,0 is + * configured as a x1 port + */ + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + }; + }; + + clocks { + /* 2 GHz fixed main PLL */ + mainpll: mainpll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + }; +}; -- cgit v0.10.2 From 7f9acb109318ddf8bf5139804b065f137cbf8b47 Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Thu, 12 Feb 2015 16:06:23 +0800 Subject: ARM: at91: at91sam9x5/dts: add ISI dt support, include isi node, pinctrls Add a new file: at91sam9x5_isi.dtsi, which includes ISI node and pinctrls. Signed-off-by: Josh Wu Acked-by: Boris Brezillon Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi index 17b8799..a7da0dd 100644 --- a/arch/arm/boot/dts/at91sam9g25.dtsi +++ b/arch/arm/boot/dts/at91sam9g25.dtsi @@ -7,6 +7,7 @@ */ #include "at91sam9x5.dtsi" +#include "at91sam9x5_isi.dtsi" #include "at91sam9x5_usart3.dtsi" #include "at91sam9x5_macb0.dtsi" diff --git a/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/at91sam9x5_isi.dtsi index 98bc877..8fc45ca 100644 --- a/arch/arm/boot/dts/at91sam9x5_isi.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_isi.dtsi @@ -13,6 +13,37 @@ / { ahb { apb { + pinctrl@fffff400 { + isi { + pinctrl_isi_data_0_7: isi-0-data-0-7 { + atmel,pins = + ; /* ISI_VSYNC, conflicts with LCDDAT13 */ + }; + + pinctrl_isi_data_8_9: isi-0-data-8-9 { + atmel,pins = + ; /* ISI_D9, conflicts with LCDDAT9 */ + }; + + pinctrl_isi_data_10_11: isi-0-data-10-11 { + atmel,pins = + ; /* ISI_D11, conflicts with LCDDAT11 */ + }; + }; + }; + pmc: pmc@fffffc00 { periphck { isi_clk: isi_clk { @@ -21,6 +52,21 @@ }; }; }; + + isi: isi@f8048000 { + compatible = "atmel,at91sam9g45-isi"; + reg = <0xf8048000 0x4000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi_data_0_7>; + clocks = <&isi_clk>; + clock-names = "isi_clk"; + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; }; }; -- cgit v0.10.2 From 436ea603c3779699f50ee0ff61c4d733496c2560 Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Thu, 12 Feb 2015 16:06:24 +0800 Subject: ARM: at91: at91sam9x5ek/dts: add ov2640 support Add the camera sensor ov2640 dt support. And connect sensor to isi node as well. Signed-off-by: Josh Wu Acked-by: Boris Brezillon Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi index bd16bd3..cc83a37 100644 --- a/arch/arm/boot/dts/at91sam9x5ek.dtsi +++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi @@ -59,6 +59,16 @@ status = "okay"; }; + isi: isi@f8048000 { + status = "disabled"; + port { + isi_0: endpoint@0 { + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + }; + }; + }; + i2c0: i2c@f8010000 { status = "okay"; @@ -66,9 +76,47 @@ compatible = "wm8731"; reg = <0x1a>; }; + + ov2640: camera@0x30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; + resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>; + clocks = <&pck0>; + clock-names = "xvclk"; + assigned-clocks = <&pck0>; + assigned-clock-rates = <25000000>; + status = "disabled"; + + port { + ov2640_0: endpoint { + remote-endpoint = <&isi_0>; + bus-width = <8>; + }; + }; + }; }; pinctrl@fffff400 { + camera_sensor { + pinctrl_pck0_as_isi_mck: pck0_as_isi_mck-0 { + atmel,pins = + ; /* ISI_MCK */ + }; + + pinctrl_sensor_power: sensor_power-0 { + atmel,pins = + ; + }; + + pinctrl_sensor_reset: sensor_reset-0 { + atmel,pins = + ; + }; + }; + mmc0 { pinctrl_board_mmc0: mmc0-board { atmel,pins = -- cgit v0.10.2 From 3978d6b05ff39821890f0322782322f242350c1f Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Thu, 12 Feb 2015 16:06:25 +0800 Subject: ARM: at91: at91sam9g25ek/dts: enable ISI and ov2640 Enable ISI and ov2640 for at91sam9g25ek board. Meantime, we need to disable the mmc1 and spi0 as they have pin conflict with ISI. Signed-off-by: Josh Wu Acked-by: Boris Brezillon Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts index 1e4c49c..707fd4e 100644 --- a/arch/arm/boot/dts/at91sam9g25ek.dts +++ b/arch/arm/boot/dts/at91sam9g25ek.dts @@ -16,10 +16,28 @@ ahb { apb { + spi0: spi@f0000000 { + status = "disabled"; + }; + + mmc1: mmc@f000c000 { + status = "disabled"; + }; + + i2c0: i2c@f8010000 { + ov2640: camera@0x30 { + status = "okay"; + }; + }; + macb0: ethernet@f802c000 { phy-mode = "rmii"; status = "okay"; }; + + isi: isi@f8048000 { + status = "okay"; + }; }; }; }; -- cgit v0.10.2 From 13f7ad3dc6dbb09ae232647058f18dedd69fce47 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Tue, 10 Feb 2015 09:55:34 +0800 Subject: ARM: at91/dt: at91sam9n12: add udp device node Add usb device node for at91sam9n12. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 0c53a375..9648430 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -912,6 +912,15 @@ clocks = <&pwm_clk>; status = "disabled"; }; + + usb1: gadget@f803c000 { + compatible = "atmel,at91sam9260-udc"; + reg = <0xf803c000 0x4000>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udphs_clk>, <&udpck>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; }; nand0: nand@40000000 { -- cgit v0.10.2 From cf05ea713144fe08d1207846fb592ff0985040c6 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Tue, 10 Feb 2015 09:55:35 +0800 Subject: ARM: at91/dt: at91sam9n12ek: enable udp Enable usb device port on at91sam9n12ek board. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 9575c0d..6123109 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -108,6 +108,13 @@ ; }; }; + + usb1 { + pinctrl_usb1_vbus_sense: usb1_vbus_sense { + atmel,pins = + ; /* PB16 gpio usb vbus sense, no pull up and deglitch */ + }; + }; }; spi0: spi@f0000000 { @@ -120,6 +127,13 @@ }; }; + usb1: gadget@f803c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus_sense>; + atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + watchdog@fffffe40 { status = "okay"; }; -- cgit v0.10.2 From 8dafaa1f28e9113c19ead7d7e118669aace538af Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 4 Mar 2015 17:56:03 +0100 Subject: ARM: at91/dt/trivial: correct file headers for SAMA5D3 SoC peripherals File name had at91 prefix, which is not the case anymore for SAMA5D3. AT91SAM9x5 was mentioned instead of SAMA5D3 SoC. Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi index eaf4145..c5a3772 100644 --- a/arch/arm/boot/dts/sama5d3_can.dtsi +++ b/arch/arm/boot/dts/sama5d3_can.dtsi @@ -1,5 +1,5 @@ /* - * at91sama5d3_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with * CAN support * * Copyright (C) 2013 Boris BREZILLON diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi index fe2af92..ca4094d 100644 --- a/arch/arm/boot/dts/sama5d3_emac.dtsi +++ b/arch/arm/boot/dts/sama5d3_emac.dtsi @@ -1,5 +1,5 @@ /* - * at91sama5d3_emac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * sama5d3_emac.dtsi - Device Tree Include file for SAMA5D3 SoC with * Ethernet. * * Copyright (C) 2013 Boris BREZILLON diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi index de5ed59..23f225f 100644 --- a/arch/arm/boot/dts/sama5d3_gmac.dtsi +++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi @@ -1,5 +1,5 @@ /* - * at91sama5d3_gmac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * sama5d3_gmac.dtsi - Device Tree Include file for SAMA5D3 SoC with * Gigabit Ethernet. * * Copyright (C) 2013 Boris BREZILLON diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi index 85d3027..8aeff6c 100644 --- a/arch/arm/boot/dts/sama5d3_lcd.dtsi +++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi @@ -1,5 +1,5 @@ /* - * at91sama5d3_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with * LCD support * * Copyright (C) 2013 Boris BREZILLON diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi index 1b02208..026b252 100644 --- a/arch/arm/boot/dts/sama5d3_mci2.dtsi +++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi @@ -1,5 +1,5 @@ /* - * at91sama5d3_mci2.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * sama5d3_mci2.dtsi - Device Tree Include file for SAMA5D3 SoC with * 3 MMC ports * * Copyright (C) 2013 Boris BREZILLON diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi index 0284845..f7fa58f 100644 --- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi +++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi @@ -1,5 +1,5 @@ /* - * at91sama5d3_tcb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * sama5d3_tcb1.dtsi - Device Tree Include file for SAMA5D3 SoC with * 2 TC blocks. * * Copyright (C) 2013 Boris BREZILLON diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi index 7a8d4c6..2511d74 100644 --- a/arch/arm/boot/dts/sama5d3_uart.dtsi +++ b/arch/arm/boot/dts/sama5d3_uart.dtsi @@ -1,5 +1,5 @@ /* - * at91sama5d3_uart.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with * UART support * * Copyright (C) 2013 Boris BREZILLON -- cgit v0.10.2 From 6d39bb019f5ac1e48d8bdc4e88cef290a14058a5 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Wed, 13 Aug 2014 12:58:21 +0800 Subject: ARM: at91/dt: at91-sama5d3_xplained: add gpio-key pinctrl property Signed-off-by: Wenyou Yang Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index fec1fca..225c63d 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -188,6 +188,11 @@ ; }; + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + ; + }; + pinctrl_mmc0_cd: mmc0_cd { atmel,pins = ; @@ -276,6 +281,9 @@ gpio_keys { compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + bp3 { label = "PB_USER"; gpios = <&pioE 29 GPIO_ACTIVE_LOW>; -- cgit v0.10.2 From 4f74a4a642eb48e6638fb709039638881f6cf9ed Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 4 Mar 2015 18:31:03 +0100 Subject: ARM: at91/dt: gpio-keys: address-cells and size-cells properties are not needed Gpio-keys nodes are not using the "reg" property in their sub nodes. So, there is no need to define #address-cells and #size-cells properties in gpio-keys nodes: we remove them in these new boards. Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index 9198b71..61f537a 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -244,8 +244,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio>; diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts index 9089c7c..d9a9aca 100644 --- a/arch/arm/boot/dts/sama5d35ek.dts +++ b/arch/arm/boot/dts/sama5d35ek.dts @@ -44,8 +44,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pb_user1 { label = "pb_user1"; -- cgit v0.10.2 From 4cc7cdf35c5f8022fde2d5046a79b52967e390f5 Mon Sep 17 00:00:00 2001 From: Philip Attfield Date: Fri, 6 Feb 2015 14:52:56 +0100 Subject: ARM: at91/dt: add i2c1 declaration to sama5d4 Add alias, node declaration and pinctrl for i2c1 (aka: twi1). Signed-off-by: Philip Attfield Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 97d5b97..2f4cf5a 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -67,6 +67,7 @@ tcb0 = &tcb0; tcb1 = &tcb1; i2c0 = &i2c0; + i2c1 = &i2c1; i2c2 = &i2c2; }; cpus { @@ -839,6 +840,25 @@ status = "disabled"; }; + i2c1: i2c@f8018000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8018000 0x4000>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(4)>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(5)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi1_clk>; + status = "disabled"; + }; + tcb0: timer@f801c000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf801c000 0x100>; @@ -1190,6 +1210,14 @@ }; }; + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + ; /* TWCK1, conflicts with UART0 TX and DIBN */ + }; + }; + i2c2 { pinctrl_i2c2: i2c2-0 { atmel,pins = -- cgit v0.10.2 From 1bc54652767637d1be3515129777b83abc997fcc Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Mon, 9 Feb 2015 17:40:20 +0800 Subject: ARM: at91/dt: sama5d4ek: add leds in DT node Add the leds DT node in the dts file. In the leds, d10 is set as heartbeat led. Signed-off-by: Josh Wu Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index 61f537a..fbd1ed2 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -255,4 +255,26 @@ gpio-key,wakeup; }; }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + d8 { + label = "d8"; + /* PE28, conflicts with usart4 rts pin */ + gpios = <&pioE 28 GPIO_ACTIVE_LOW>; + }; + + d9 { + label = "d9"; + gpios = <&pioE 9 GPIO_ACTIVE_HIGH>; + }; + + d10 { + label = "d10"; + gpios = <&pioE 8 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; }; -- cgit v0.10.2 From 9917defd8c3928eb89729d1457d9bc438263a3a1 Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Wed, 4 Mar 2015 10:51:47 +0800 Subject: ARM: at91/dt: sama5d4: add #{address, size}_cells properties for macb0 macb0 DT node can have phy child nodes, so add the #{address, size}_cells for macb0 node. Signed-off-by: Josh Wu Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 2f4cf5a..f6f2af3 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -873,6 +873,8 @@ interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_rmii>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&macb0_clk>, <&macb0_clk>; clock-names = "hclk", "pclk"; status = "disabled"; -- cgit v0.10.2 From 38153a017896f3a23fa8b4eb41241a8681fc8d6b Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Wed, 4 Mar 2015 10:51:48 +0800 Subject: ARM: at91/dt: sama5d4: add dts for sama5d4 xplained board Add at91 sama5d4 xplained board support. Signed-off-by: Josh Wu Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a1c776b..0fc67d7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -42,6 +42,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ sama5d34ek.dtb \ sama5d35ek.dtb \ sama5d36ek.dtb \ + at91-sama5d4_xplained.dtb \ at91-sama5d4ek.dtb dtb-$(CONFIG_ARCH_ATLAS6) += \ atlas6-evb.dtb diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts new file mode 100644 index 0000000..772dc98 --- /dev/null +++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts @@ -0,0 +1,237 @@ +/* + * at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board + * + * Copyright (C) 2015 Atmel, + * 2015 Josh Wu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; +#include "sama5d4.dtsi" + +/ { + model = "Atmel SAMA5D4 Xplained"; + compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5"; + + chosen { + bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk"; + }; + + memory { + reg = <0x20000000 0x20000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + spi0: spi@f8010000 { + cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; + status = "okay"; + m25p80@0 { + compatible = "atmel,at25df321a"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + macb0: ethernet@f8020000 { + phy-mode = "rmii"; + status = "okay"; + + phy0: ethernet-phy@1 { + interrupt-parent = <&pioE>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + reg = <1>; + }; + }; + + mmc1: mmc@fc000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 3 0>; + }; + }; + + usart3: serial@fc00c000 { + status = "okay"; + }; + + usart4: serial@fc010000 { + status = "okay"; + }; + + adc0: adc@fc034000 { + atmel,adc-vref = <3300>; + status = "okay"; + }; + + watchdog@fc068640 { + status = "okay"; + }; + + pinctrl@fc06a000 { + board { + pinctrl_mmc1_cd: mmc1_cd { + atmel,pins = + ; + }; + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + ; + }; + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + ; + }; + }; + }; + }; + + usb0: gadget@00400000 { + atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@00500000 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioE 11 GPIO_ACTIVE_HIGH + &pioE 14 GPIO_ACTIVE_HIGH + >; + status = "okay"; + }; + + usb2: ehci@00600000 { + status = "okay"; + }; + + nand0: nand@80000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + atmel,has-pmecc; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + pb_user1 { + label = "pb_user1"; + gpios = <&pioE 8 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; + gpio-key,wakeup; + }; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + d8 { + label = "d8"; + gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + d10 { + label = "d10"; + gpios = <&pioE 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; -- cgit v0.10.2 From df99d08ccd1db44bba746fea31de8e7bfb08c6d6 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 26 Feb 2015 16:05:14 +0100 Subject: ARM: at91/dt: sama5d4 xplained: add i2c0 Add i2c0 aka twi0 on sama5d4 xplained board. Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts index 772dc98..c740e1a 100644 --- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts @@ -88,6 +88,10 @@ }; }; + i2c0: i2c@f8014000 { + status = "okay"; + }; + macb0: ethernet@f8020000 { phy-mode = "rmii"; status = "okay"; -- cgit v0.10.2 From 0697edd7b7c57b533f286e2101699af9ec59564d Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 2 Feb 2015 14:51:44 +0800 Subject: ARM: at91: dt: sama5d4: add ssc nodes Add SSC 0 and 1 nodes. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index f6f2af3..5661b90 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -64,6 +64,8 @@ gpio2 = &pioC; gpio3 = &pioD; gpio4 = &pioE; + ssc0 = &ssc0; + ssc1 = &ssc1; tcb0 = &tcb0; tcb1 = &tcb1; i2c0 = &i2c0; @@ -801,6 +803,24 @@ clock-names = "mci_clk"; }; + ssc0: ssc@f8008000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf8008000 0x4000>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(26))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(27))>; + dma-names = "tx", "rx"; + clocks = <&ssc0_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + spi0: spi@f8010000 { #address-cells = <1>; #size-cells = <0>; @@ -975,6 +995,24 @@ status = "disabled"; }; + ssc1: ssc@fc014000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xfc014000 0x4000>; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(28))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(29))>; + dma-names = "tx", "rx"; + clocks = <&ssc1_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + tcb1: timer@fc020000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xfc020000 0x100>; @@ -1311,6 +1349,38 @@ }; }; + ssc0 { + pinctrl_ssc0_tx: ssc0_tx { + atmel,pins = + ; /* TD0 */ + }; + + pinctrl_ssc0_rx: ssc0_rx { + atmel,pins = + ; /* RD0 */ + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx { + atmel,pins = + ; /* TD1 */ + }; + + pinctrl_ssc1_rx: ssc1_rx { + atmel,pins = + ; /* RD1 */ + }; + }; + usart2 { pinctrl_usart2: usart2-0 { atmel,pins = -- cgit v0.10.2 From 06981c51f82464f946cea6843fd17cacfd4c59a6 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 2 Feb 2015 14:51:45 +0800 Subject: ARM: at91: dt: sama5d4ek: enable ssc0 Enable SSC0 node, which will be used for audio. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index fbd1ed2..e8e2016 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -115,6 +115,10 @@ }; }; + ssc0: ssc@f8008000 { + status = "okay"; + }; + spi0: spi@f8010000 { cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; status = "okay"; -- cgit v0.10.2 From 5afd9451cf6c20e8bbd0dc5713141295a1d8f38c Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 2 Feb 2015 14:51:46 +0800 Subject: ARM: at91: dt: sama5d4ek: add and enable wm8904 Add wm8904 codec node and enable it. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index e8e2016..957e66b 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -131,6 +131,13 @@ i2c0: i2c@f8014000 { status = "okay"; + + wm8904: codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&pck2>; + clock-names = "mclk"; + }; }; macb0: ethernet@f8020000 { -- cgit v0.10.2 From 15ff964dd45877278aaae20c00ef5977138976c8 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 2 Feb 2015 14:51:47 +0800 Subject: ARM: at91: dt: sama5d4ek: enable audio Enable audio support for sama5d4ek board. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index 957e66b..89ef4a5 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -182,6 +182,10 @@ atmel,pins = ; }; + pinctrl_pck2_as_audio_mck: pck2_as_audio_mck { + atmel,pins = + ; + }; pinctrl_usba_vbus: usba_vbus { atmel,pins = ; @@ -288,4 +292,20 @@ linux,default-trigger = "heartbeat"; }; }; + + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck2_as_audio_mck>; + + atmel,model = "wm8904 @ SAMA5D4EK"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN1L", "Line In Jack", + "IN1R", "Line In Jack"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + }; }; -- cgit v0.10.2 From 83906783b7663b9245ea6d668c8af4b4697f463b Mon Sep 17 00:00:00 2001 From: Leilei Zhao Date: Fri, 9 Jan 2015 16:58:57 +0100 Subject: ARM: at91/dt: sama5d4: add aes, sha and tdes nodes Signed-off-by: Leilei Zhao Signed-off-by: Ludovic Desroches Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 5661b90..93dc4e3 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -1068,6 +1068,46 @@ }; }; + aes@fc044000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xfc044000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(41)>, + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(40)>; + dma-names = "tx", "rx"; + clocks = <&aes_clk>; + clock-names = "aes_clk"; + status = "disabled"; + }; + + tdes@fc04c000 { + compatible = "atmel,at91sam9g46-tdes"; + reg = <0xfc04c000 0x100>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(42)>, + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(43)>; + dma-names = "tx", "rx"; + clocks = <&tdes_clk>; + clock-names = "tdes_clk"; + status = "disabled"; + }; + + sha@fc050000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xfc050000 0x100>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(44)>; + dma-names = "tx"; + clocks = <&sha_clk>; + clock-names = "sha_clk"; + status = "disabled"; + }; + rstc@fc068600 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfc068600 0x10>; -- cgit v0.10.2 From 0a5c5f84a51450c8772f4212d85262ddb8f75b14 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Fri, 9 Jan 2015 17:11:05 +0100 Subject: ARM: at91/dt: sama5d4: add pwm0 device node Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 93dc4e3..3041baa 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -64,6 +64,7 @@ gpio2 = &pioC; gpio3 = &pioD; gpio4 = &pioE; + pwm0 = &pwm0; ssc0 = &ssc0; ssc1 = &ssc1; tcb0 = &tcb0; @@ -821,6 +822,15 @@ status = "disabled"; }; + pwm0: pwm@f800c000 { + compatible = "atmel,sama5d3-pwm"; + reg = <0xf800c000 0x300>; + interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pwm_clk>; + status = "disabled"; + }; + spi0: spi@f8010000 { #address-cells = <1>; #size-cells = <0>; -- cgit v0.10.2 From 35762a624f82dbea7c62177bf3ef0cde0d0f84bc Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Fri, 23 Jan 2015 16:38:03 +0800 Subject: ARM: at91/dt: sama5d4: add ISI dt support Add ISI dt node and pinctrl settings in sama5d4.dtsi. Signed-off-by: Josh Wu [nicolas.ferre@atmel.com: sort nodes in order. remove useless comments] Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 3041baa..63eb7a2 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -323,6 +323,21 @@ clock-names = "dma_clk"; }; + isi: isi@f0008000 { + compatible = "atmel,at91sam9g45-isi"; + reg = <0xf0008000 0x4000>; + interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi_data_0_7>; + clocks = <&isi_clk>; + clock-names = "isi_clk"; + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + ramc0: ramc@f0010000 { compatible = "atmel,sama5d3-ddramc"; reg = <0xf0010000 0x200>; @@ -1316,6 +1331,33 @@ }; }; + isi { + pinctrl_isi_data_0_7: isi-0-data-0-7 { + atmel,pins = + ; /* ISI_HSYNC */ + }; + pinctrl_isi_data_8_9: isi-0-data-8-9 { + atmel,pins = + ; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */ + }; + pinctrl_isi_data_10_11: isi-0-data-10-11 { + atmel,pins = + ; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */ + }; + }; + macb0 { pinctrl_macb0_rmii: macb0_rmii-0 { atmel,pins = -- cgit v0.10.2 From d55ce8d818a992cef7de014ed1b86108cf3f27a4 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sun, 1 Mar 2015 17:28:24 +0800 Subject: dt-bindings: add root compatible property for PopMetal board PopMetal board is a rk3288 based board made by ChipSpark, this add root compatible property for it Signed-off-by: Andy Yan Signed-off-by: Heiko Stuebner diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 6809e4e..60d4a1e 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -22,3 +22,7 @@ Rockchip platforms device tree bindings - compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; or - compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288"; + +- ChipSPARK PopMetal-RK3288 board: + Required root node properties: + - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; -- cgit v0.10.2 From c38e1328ceadc0b345ddd914c13ac1abfb048209 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sun, 1 Mar 2015 17:32:33 +0800 Subject: ARM: dts: add rk3288 PopMetal board PopMetal is a rockchip rk3288 based board made by ChipSpark, which has many interface such as VGA,HDMI,usb,ir,sdcad and lots of sensors such as gyroscope(L3G4200D),accelerometer(mma8452), compass(AK8963C). This patch add a basic support for this board, which make the board boot into a initramfs shell with sdcard,hdmi and all sensors enabled Signed-off-by: Andy Yan Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts new file mode 100644 index 0000000..d081f0e --- /dev/null +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -0,0 +1,447 @@ +/* + * Copyright (c) 2014, 2015 Andy Yan + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "rk3288.dtsi" + +/ { + model = "PopMetal-RK3288"; + compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; + + memory{ + reg = <0 0x80000000>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + button@0 { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + }; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; /* wp not hooked up */ + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio4 7 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "ok"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_18>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc_io>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_lan: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_lan"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc18_lcd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + ldo5: LDO_REG5 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "ldo5"; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_codec: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_codec"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_wl: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_wl"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_lcd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + ak8963: ak8963@0d { + compatible = "asahi-kasei,ak8975"; + reg = <0x0d>; + interrupt-parent = <&gpio8>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&comp_int>; + }; + + l3g4200d: l3g4200d@68 { + compatible = "st,l3g4200d-gyro"; + st,drdy-int-pin = <2>; + reg = <0x6b>; + }; + + mma8452: mma8452@1d { + compatible = "fsl,mma8452"; + reg = <0x1d>; + interrupt-parent = <&gpio8>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&gsensor_int>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&pinctrl { + ak8963 { + comp_int: comp-int { + rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + ir { + ir_int: ir-int { + rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + mma8452 { + gsensor_int: gsensor-int { + rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = ; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; -- cgit v0.10.2 From 66c9270b6898de629ab2a7428e56993800ea9a6c Mon Sep 17 00:00:00 2001 From: Daniel Tang Date: Mon, 9 Feb 2015 19:41:57 +1100 Subject: devicetree: Add TI-NSPIRE USB OTG support to device tree Signed-off-by: Daniel Tang Signed-off-by: Arnd Bergmann diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi index 9565199..4907c50 100644 --- a/arch/arm/boot/dts/nspire-classic.dtsi +++ b/arch/arm/boot/dts/nspire-classic.dtsi @@ -51,6 +51,11 @@ compatible = "lsi,nspire-classic-ahb-divider"; }; + +&vbus_reg { + gpio = <&gpio 5 0>; +}; + / { memory { device_type = "memory"; diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts index 375b924..08e0b81 100644 --- a/arch/arm/boot/dts/nspire-cx.dts +++ b/arch/arm/boot/dts/nspire-cx.dts @@ -69,6 +69,10 @@ 0x0709001d 0x070a0033 >; }; +&vbus_reg { + gpio = <&gpio 2 0>; +}; + / { model = "TI-NSPIRE CX"; compatible = "ti,nspire-cx"; diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index a22ffe6..390c91a 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -54,6 +54,20 @@ clocks = <&ahb_clk>; }; + usb_phy: usb_phy { + compatible = "usb-nop-xceiv"; + }; + + vbus_reg: vbus_reg { + compatible = "regulator-fixed"; + + regulator-name = "USB VBUS output"; + regulator-type = "voltage"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; @@ -65,8 +79,12 @@ }; usb0: usb@B0000000 { + compatible = "lsi,zevio-usb"; reg = <0xB0000000 0x1000>; interrupts = <8>; + + usb-phy = <&usb_phy>; + vbus-supply = <&vbus_reg>; }; usb1: usb@B4000000 { @@ -105,8 +123,11 @@ ranges; gpio: gpio@90000000 { + compatible = "lsi,zevio-gpio"; reg = <0x90000000 0x1000>; interrupts = <7>; + gpio-controller; + #gpio-cells = <2>; }; fast_timer: timer@90010000 { -- cgit v0.10.2 From e6f219b8ec5e4227c8b87b758afb48ed102b4210 Mon Sep 17 00:00:00 2001 From: Hongzhou Yang Date: Wed, 21 Jan 2015 13:28:17 +0800 Subject: ARM: dts: mt8135: Add pinctrl/GPIO/EINT node for mt8135. Add pinctrl,GPIO and EINT node to mt8135.dtsi. Signed-off-by: Hongzhou Yang Acked-by: Linus Walleij Singed-off-by: Matthias Brugger diff --git a/arch/arm/boot/dts/mt8135-pinfunc.h b/arch/arm/boot/dts/mt8135-pinfunc.h new file mode 100644 index 0000000..5a60987 --- /dev/null +++ b/arch/arm/boot/dts/mt8135-pinfunc.h @@ -0,0 +1,1302 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DTS_MT8135_PINFUNC_H +#define __DTS_MT8135_PINFUNC_H + +#include + +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(0) | 1) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MTK_PIN_NO(0) | 2) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MTK_PIN_NO(0) | 3) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_DAC_DAT_OUT (MTK_PIN_NO(0) | 4) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_PCM1_DO (MTK_PIN_NO(0) | 5) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_SPI1_MO (MTK_PIN_NO(0) | 6) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_NALE (MTK_PIN_NO(0) | 7) + +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(1) | 1) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_EINT48 (MTK_PIN_NO(1) | 2) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_I2SIN_WS (MTK_PIN_NO(1) | 3) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_DAC_WS (MTK_PIN_NO(1) | 4) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_PCM1_WS (MTK_PIN_NO(1) | 5) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_SPI1_CSN (MTK_PIN_NO(1) | 6) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_NCLE (MTK_PIN_NO(1) | 7) + +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(2) | 1) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_EINT47 (MTK_PIN_NO(2) | 2) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_I2SIN_CK (MTK_PIN_NO(2) | 3) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_DAC_CK (MTK_PIN_NO(2) | 4) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_PCM1_CK (MTK_PIN_NO(2) | 5) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_SPI1_CLK (MTK_PIN_NO(2) | 6) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(2) | 7) + +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(3) | 1) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_EINT46 (MTK_PIN_NO(3) | 2) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_A_FUNC_CK (MTK_PIN_NO(3) | 3) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_LSCE1B_2X (MTK_PIN_NO(3) | 6) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_NLD5 (MTK_PIN_NO(3) | 7) + +#define MT8135_PIN_4_MSDC0_CMD__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(4) | 1) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_EINT41 (MTK_PIN_NO(4) | 2) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_A_FUNC_DOUT_0 (MTK_PIN_NO(4) | 3) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_USB_TEST_IO_0 (MTK_PIN_NO(4) | 5) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_LRSTB_2X (MTK_PIN_NO(4) | 6) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_NRNB (MTK_PIN_NO(4) | 7) + +#define MT8135_PIN_5_MSDC0_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(5) | 1) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_EINT40 (MTK_PIN_NO(5) | 2) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_A_FUNC_DOUT_1 (MTK_PIN_NO(5) | 3) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_USB_TEST_IO_1 (MTK_PIN_NO(5) | 5) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_LPTE (MTK_PIN_NO(5) | 6) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_NREB (MTK_PIN_NO(5) | 7) + +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(6) | 1) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_EINT45 (MTK_PIN_NO(6) | 2) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_A_FUNC_DOUT_2 (MTK_PIN_NO(6) | 3) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_USB_TEST_IO_2 (MTK_PIN_NO(6) | 5) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_LSCE0B_2X (MTK_PIN_NO(6) | 6) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_NLD7 (MTK_PIN_NO(6) | 7) + +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(7) | 1) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_EINT44 (MTK_PIN_NO(7) | 2) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_A_FUNC_DOUT_3 (MTK_PIN_NO(7) | 3) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_USB_TEST_IO_3 (MTK_PIN_NO(7) | 5) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_LSA0_2X (MTK_PIN_NO(7) | 6) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_NLD14 (MTK_PIN_NO(7) | 7) + +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(8) | 1) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_EINT43 (MTK_PIN_NO(8) | 2) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_USB_TEST_IO_4 (MTK_PIN_NO(8) | 5) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_LSCK_2X (MTK_PIN_NO(8) | 6) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_NLD11 (MTK_PIN_NO(8) | 7) + +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(9) | 1) +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_EINT42 (MTK_PIN_NO(9) | 2) +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_USB_TEST_IO_5 (MTK_PIN_NO(9) | 5) +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_LSDA_2X (MTK_PIN_NO(9) | 6) + +#define MT8135_PIN_10_NCEB0__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT8135_PIN_10_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(10) | 1) +#define MT8135_PIN_10_NCEB0__FUNC_EINT139 (MTK_PIN_NO(10) | 2) +#define MT8135_PIN_10_NCEB0__FUNC_TESTA_OUT4 (MTK_PIN_NO(10) | 7) + +#define MT8135_PIN_11_NCEB1__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT8135_PIN_11_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(11) | 1) +#define MT8135_PIN_11_NCEB1__FUNC_EINT140 (MTK_PIN_NO(11) | 2) +#define MT8135_PIN_11_NCEB1__FUNC_USB_DRVVBUS (MTK_PIN_NO(11) | 6) +#define MT8135_PIN_11_NCEB1__FUNC_TESTA_OUT5 (MTK_PIN_NO(11) | 7) + +#define MT8135_PIN_12_NRNB__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT8135_PIN_12_NRNB__FUNC_NRNB (MTK_PIN_NO(12) | 1) +#define MT8135_PIN_12_NRNB__FUNC_EINT141 (MTK_PIN_NO(12) | 2) +#define MT8135_PIN_12_NRNB__FUNC_A_FUNC_DOUT_4 (MTK_PIN_NO(12) | 3) +#define MT8135_PIN_12_NRNB__FUNC_TESTA_OUT6 (MTK_PIN_NO(12) | 7) + +#define MT8135_PIN_13_NCLE__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT8135_PIN_13_NCLE__FUNC_NCLE (MTK_PIN_NO(13) | 1) +#define MT8135_PIN_13_NCLE__FUNC_EINT142 (MTK_PIN_NO(13) | 2) +#define MT8135_PIN_13_NCLE__FUNC_A_FUNC_DOUT_5 (MTK_PIN_NO(13) | 3) +#define MT8135_PIN_13_NCLE__FUNC_CM2PDN_1X (MTK_PIN_NO(13) | 4) +#define MT8135_PIN_13_NCLE__FUNC_NALE (MTK_PIN_NO(13) | 6) +#define MT8135_PIN_13_NCLE__FUNC_TESTA_OUT7 (MTK_PIN_NO(13) | 7) + +#define MT8135_PIN_14_NALE__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT8135_PIN_14_NALE__FUNC_NALE (MTK_PIN_NO(14) | 1) +#define MT8135_PIN_14_NALE__FUNC_EINT143 (MTK_PIN_NO(14) | 2) +#define MT8135_PIN_14_NALE__FUNC_A_FUNC_DOUT_6 (MTK_PIN_NO(14) | 3) +#define MT8135_PIN_14_NALE__FUNC_CM2MCLK_1X (MTK_PIN_NO(14) | 4) +#define MT8135_PIN_14_NALE__FUNC_IRDA_RXD (MTK_PIN_NO(14) | 5) +#define MT8135_PIN_14_NALE__FUNC_NCLE (MTK_PIN_NO(14) | 6) +#define MT8135_PIN_14_NALE__FUNC_TESTA_OUT8 (MTK_PIN_NO(14) | 7) + +#define MT8135_PIN_15_NREB__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT8135_PIN_15_NREB__FUNC_NREB (MTK_PIN_NO(15) | 1) +#define MT8135_PIN_15_NREB__FUNC_EINT144 (MTK_PIN_NO(15) | 2) +#define MT8135_PIN_15_NREB__FUNC_A_FUNC_DOUT_7 (MTK_PIN_NO(15) | 3) +#define MT8135_PIN_15_NREB__FUNC_CM2RST_1X (MTK_PIN_NO(15) | 4) +#define MT8135_PIN_15_NREB__FUNC_IRDA_TXD (MTK_PIN_NO(15) | 5) +#define MT8135_PIN_15_NREB__FUNC_TESTA_OUT9 (MTK_PIN_NO(15) | 7) + +#define MT8135_PIN_16_NWEB__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT8135_PIN_16_NWEB__FUNC_NWEB (MTK_PIN_NO(16) | 1) +#define MT8135_PIN_16_NWEB__FUNC_EINT145 (MTK_PIN_NO(16) | 2) +#define MT8135_PIN_16_NWEB__FUNC_A_FUNC_DIN_0 (MTK_PIN_NO(16) | 3) +#define MT8135_PIN_16_NWEB__FUNC_CM2PCLK_1X (MTK_PIN_NO(16) | 4) +#define MT8135_PIN_16_NWEB__FUNC_IRDA_PDN (MTK_PIN_NO(16) | 5) +#define MT8135_PIN_16_NWEB__FUNC_TESTA_OUT10 (MTK_PIN_NO(16) | 7) + +#define MT8135_PIN_17_NLD0__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT8135_PIN_17_NLD0__FUNC_NLD0 (MTK_PIN_NO(17) | 1) +#define MT8135_PIN_17_NLD0__FUNC_EINT146 (MTK_PIN_NO(17) | 2) +#define MT8135_PIN_17_NLD0__FUNC_A_FUNC_DIN_1 (MTK_PIN_NO(17) | 3) +#define MT8135_PIN_17_NLD0__FUNC_CM2DAT_1X_0 (MTK_PIN_NO(17) | 4) +#define MT8135_PIN_17_NLD0__FUNC_I2SIN_CK (MTK_PIN_NO(17) | 5) +#define MT8135_PIN_17_NLD0__FUNC_DAC_CK (MTK_PIN_NO(17) | 6) +#define MT8135_PIN_17_NLD0__FUNC_TESTA_OUT11 (MTK_PIN_NO(17) | 7) + +#define MT8135_PIN_18_NLD1__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT8135_PIN_18_NLD1__FUNC_NLD1 (MTK_PIN_NO(18) | 1) +#define MT8135_PIN_18_NLD1__FUNC_EINT147 (MTK_PIN_NO(18) | 2) +#define MT8135_PIN_18_NLD1__FUNC_A_FUNC_DIN_2 (MTK_PIN_NO(18) | 3) +#define MT8135_PIN_18_NLD1__FUNC_CM2DAT_1X_1 (MTK_PIN_NO(18) | 4) +#define MT8135_PIN_18_NLD1__FUNC_I2SIN_WS (MTK_PIN_NO(18) | 5) +#define MT8135_PIN_18_NLD1__FUNC_DAC_WS (MTK_PIN_NO(18) | 6) +#define MT8135_PIN_18_NLD1__FUNC_TESTA_OUT12 (MTK_PIN_NO(18) | 7) + +#define MT8135_PIN_19_NLD2__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT8135_PIN_19_NLD2__FUNC_NLD2 (MTK_PIN_NO(19) | 1) +#define MT8135_PIN_19_NLD2__FUNC_EINT148 (MTK_PIN_NO(19) | 2) +#define MT8135_PIN_19_NLD2__FUNC_A_FUNC_DIN_3 (MTK_PIN_NO(19) | 3) +#define MT8135_PIN_19_NLD2__FUNC_CM2DAT_1X_2 (MTK_PIN_NO(19) | 4) +#define MT8135_PIN_19_NLD2__FUNC_I2SOUT_DAT (MTK_PIN_NO(19) | 5) +#define MT8135_PIN_19_NLD2__FUNC_DAC_DAT_OUT (MTK_PIN_NO(19) | 6) +#define MT8135_PIN_19_NLD2__FUNC_TESTA_OUT13 (MTK_PIN_NO(19) | 7) + +#define MT8135_PIN_20_NLD3__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT8135_PIN_20_NLD3__FUNC_NLD3 (MTK_PIN_NO(20) | 1) +#define MT8135_PIN_20_NLD3__FUNC_EINT149 (MTK_PIN_NO(20) | 2) +#define MT8135_PIN_20_NLD3__FUNC_A_FUNC_DIN_4 (MTK_PIN_NO(20) | 3) +#define MT8135_PIN_20_NLD3__FUNC_CM2DAT_1X_3 (MTK_PIN_NO(20) | 4) +#define MT8135_PIN_20_NLD3__FUNC_TESTA_OUT14 (MTK_PIN_NO(20) | 7) + +#define MT8135_PIN_21_NLD4__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT8135_PIN_21_NLD4__FUNC_NLD4 (MTK_PIN_NO(21) | 1) +#define MT8135_PIN_21_NLD4__FUNC_EINT150 (MTK_PIN_NO(21) | 2) +#define MT8135_PIN_21_NLD4__FUNC_A_FUNC_DIN_5 (MTK_PIN_NO(21) | 3) +#define MT8135_PIN_21_NLD4__FUNC_CM2DAT_1X_4 (MTK_PIN_NO(21) | 4) +#define MT8135_PIN_21_NLD4__FUNC_TESTA_OUT15 (MTK_PIN_NO(21) | 7) + +#define MT8135_PIN_22_NLD5__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT8135_PIN_22_NLD5__FUNC_NLD5 (MTK_PIN_NO(22) | 1) +#define MT8135_PIN_22_NLD5__FUNC_EINT151 (MTK_PIN_NO(22) | 2) +#define MT8135_PIN_22_NLD5__FUNC_A_FUNC_DIN_6 (MTK_PIN_NO(22) | 3) +#define MT8135_PIN_22_NLD5__FUNC_CM2DAT_1X_5 (MTK_PIN_NO(22) | 4) +#define MT8135_PIN_22_NLD5__FUNC_TESTA_OUT16 (MTK_PIN_NO(22) | 7) + +#define MT8135_PIN_23_NLD6__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT8135_PIN_23_NLD6__FUNC_NLD6 (MTK_PIN_NO(23) | 1) +#define MT8135_PIN_23_NLD6__FUNC_EINT152 (MTK_PIN_NO(23) | 2) +#define MT8135_PIN_23_NLD6__FUNC_A_FUNC_DIN_7 (MTK_PIN_NO(23) | 3) +#define MT8135_PIN_23_NLD6__FUNC_CM2DAT_1X_6 (MTK_PIN_NO(23) | 4) +#define MT8135_PIN_23_NLD6__FUNC_TESTA_OUT17 (MTK_PIN_NO(23) | 7) + +#define MT8135_PIN_24_NLD7__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT8135_PIN_24_NLD7__FUNC_NLD7 (MTK_PIN_NO(24) | 1) +#define MT8135_PIN_24_NLD7__FUNC_EINT153 (MTK_PIN_NO(24) | 2) +#define MT8135_PIN_24_NLD7__FUNC_A_FUNC_DIN_8 (MTK_PIN_NO(24) | 3) +#define MT8135_PIN_24_NLD7__FUNC_CM2DAT_1X_7 (MTK_PIN_NO(24) | 4) +#define MT8135_PIN_24_NLD7__FUNC_TESTA_OUT18 (MTK_PIN_NO(24) | 7) + +#define MT8135_PIN_25_NLD8__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT8135_PIN_25_NLD8__FUNC_NLD8 (MTK_PIN_NO(25) | 1) +#define MT8135_PIN_25_NLD8__FUNC_EINT154 (MTK_PIN_NO(25) | 2) +#define MT8135_PIN_25_NLD8__FUNC_CM2DAT_1X_8 (MTK_PIN_NO(25) | 4) + +#define MT8135_PIN_26_NLD9__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT8135_PIN_26_NLD9__FUNC_NLD9 (MTK_PIN_NO(26) | 1) +#define MT8135_PIN_26_NLD9__FUNC_EINT155 (MTK_PIN_NO(26) | 2) +#define MT8135_PIN_26_NLD9__FUNC_CM2DAT_1X_9 (MTK_PIN_NO(26) | 4) +#define MT8135_PIN_26_NLD9__FUNC_PWM1 (MTK_PIN_NO(26) | 5) + +#define MT8135_PIN_27_NLD10__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT8135_PIN_27_NLD10__FUNC_NLD10 (MTK_PIN_NO(27) | 1) +#define MT8135_PIN_27_NLD10__FUNC_EINT156 (MTK_PIN_NO(27) | 2) +#define MT8135_PIN_27_NLD10__FUNC_CM2VSYNC_1X (MTK_PIN_NO(27) | 4) +#define MT8135_PIN_27_NLD10__FUNC_PWM2 (MTK_PIN_NO(27) | 5) + +#define MT8135_PIN_28_NLD11__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT8135_PIN_28_NLD11__FUNC_NLD11 (MTK_PIN_NO(28) | 1) +#define MT8135_PIN_28_NLD11__FUNC_EINT157 (MTK_PIN_NO(28) | 2) +#define MT8135_PIN_28_NLD11__FUNC_CM2HSYNC_1X (MTK_PIN_NO(28) | 4) +#define MT8135_PIN_28_NLD11__FUNC_PWM3 (MTK_PIN_NO(28) | 5) + +#define MT8135_PIN_29_NLD12__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT8135_PIN_29_NLD12__FUNC_NLD12 (MTK_PIN_NO(29) | 1) +#define MT8135_PIN_29_NLD12__FUNC_EINT158 (MTK_PIN_NO(29) | 2) +#define MT8135_PIN_29_NLD12__FUNC_I2SIN_CK (MTK_PIN_NO(29) | 3) +#define MT8135_PIN_29_NLD12__FUNC_DAC_CK (MTK_PIN_NO(29) | 4) +#define MT8135_PIN_29_NLD12__FUNC_PCM1_CK (MTK_PIN_NO(29) | 5) + +#define MT8135_PIN_30_NLD13__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT8135_PIN_30_NLD13__FUNC_NLD13 (MTK_PIN_NO(30) | 1) +#define MT8135_PIN_30_NLD13__FUNC_EINT159 (MTK_PIN_NO(30) | 2) +#define MT8135_PIN_30_NLD13__FUNC_I2SIN_WS (MTK_PIN_NO(30) | 3) +#define MT8135_PIN_30_NLD13__FUNC_DAC_WS (MTK_PIN_NO(30) | 4) +#define MT8135_PIN_30_NLD13__FUNC_PCM1_WS (MTK_PIN_NO(30) | 5) + +#define MT8135_PIN_31_NLD14__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT8135_PIN_31_NLD14__FUNC_NLD14 (MTK_PIN_NO(31) | 1) +#define MT8135_PIN_31_NLD14__FUNC_EINT160 (MTK_PIN_NO(31) | 2) +#define MT8135_PIN_31_NLD14__FUNC_I2SOUT_DAT (MTK_PIN_NO(31) | 3) +#define MT8135_PIN_31_NLD14__FUNC_DAC_DAT_OUT (MTK_PIN_NO(31) | 4) +#define MT8135_PIN_31_NLD14__FUNC_PCM1_DO (MTK_PIN_NO(31) | 5) + +#define MT8135_PIN_32_NLD15__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT8135_PIN_32_NLD15__FUNC_NLD15 (MTK_PIN_NO(32) | 1) +#define MT8135_PIN_32_NLD15__FUNC_EINT161 (MTK_PIN_NO(32) | 2) +#define MT8135_PIN_32_NLD15__FUNC_DISP_PWM (MTK_PIN_NO(32) | 3) +#define MT8135_PIN_32_NLD15__FUNC_PWM4 (MTK_PIN_NO(32) | 4) +#define MT8135_PIN_32_NLD15__FUNC_PCM1_DI (MTK_PIN_NO(32) | 5) + +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(33) | 1) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_EINT50 (MTK_PIN_NO(33) | 2) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_I2SIN_DAT (MTK_PIN_NO(33) | 3) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_PCM1_DI (MTK_PIN_NO(33) | 5) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_SPI1_MI (MTK_PIN_NO(33) | 6) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_NLD10 (MTK_PIN_NO(33) | 7) + +#define MT8135_PIN_34_IDDIG__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT8135_PIN_34_IDDIG__FUNC_IDDIG (MTK_PIN_NO(34) | 1) +#define MT8135_PIN_34_IDDIG__FUNC_EINT34 (MTK_PIN_NO(34) | 2) + +#define MT8135_PIN_35_SCL3__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT8135_PIN_35_SCL3__FUNC_SCL3 (MTK_PIN_NO(35) | 1) +#define MT8135_PIN_35_SCL3__FUNC_EINT96 (MTK_PIN_NO(35) | 2) +#define MT8135_PIN_35_SCL3__FUNC_CLKM6 (MTK_PIN_NO(35) | 3) +#define MT8135_PIN_35_SCL3__FUNC_PWM6 (MTK_PIN_NO(35) | 4) + +#define MT8135_PIN_36_SDA3__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT8135_PIN_36_SDA3__FUNC_SDA3 (MTK_PIN_NO(36) | 1) +#define MT8135_PIN_36_SDA3__FUNC_EINT97 (MTK_PIN_NO(36) | 2) + +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(37) | 1) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_ADC_CK (MTK_PIN_NO(37) | 2) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_HDMI_SDATA0 (MTK_PIN_NO(37) | 3) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_EINT19 (MTK_PIN_NO(37) | 4) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_USB_TEST_IO_6 (MTK_PIN_NO(37) | 5) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_TESTA_OUT19 (MTK_PIN_NO(37) | 7) + +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(38) | 1) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_ADC_WS (MTK_PIN_NO(38) | 2) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(38) | 3) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_EINT21 (MTK_PIN_NO(38) | 4) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_USB_TEST_IO_7 (MTK_PIN_NO(38) | 5) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_TESTA_OUT20 (MTK_PIN_NO(38) | 7) + +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(39) | 1) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_ADC_DAT_IN (MTK_PIN_NO(39) | 2) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(39) | 3) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_EINT20 (MTK_PIN_NO(39) | 4) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_USB_TEST_IO_8 (MTK_PIN_NO(39) | 5) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_TESTA_OUT21 (MTK_PIN_NO(39) | 7) + +#define MT8135_PIN_40_DAC_CLK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT8135_PIN_40_DAC_CLK__FUNC_DAC_CK (MTK_PIN_NO(40) | 1) +#define MT8135_PIN_40_DAC_CLK__FUNC_EINT22 (MTK_PIN_NO(40) | 2) +#define MT8135_PIN_40_DAC_CLK__FUNC_HDMI_SDATA1 (MTK_PIN_NO(40) | 3) +#define MT8135_PIN_40_DAC_CLK__FUNC_USB_TEST_IO_9 (MTK_PIN_NO(40) | 5) +#define MT8135_PIN_40_DAC_CLK__FUNC_TESTA_OUT22 (MTK_PIN_NO(40) | 7) + +#define MT8135_PIN_41_DAC_WS__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT8135_PIN_41_DAC_WS__FUNC_DAC_WS (MTK_PIN_NO(41) | 1) +#define MT8135_PIN_41_DAC_WS__FUNC_EINT24 (MTK_PIN_NO(41) | 2) +#define MT8135_PIN_41_DAC_WS__FUNC_HDMI_SDATA2 (MTK_PIN_NO(41) | 3) +#define MT8135_PIN_41_DAC_WS__FUNC_USB_TEST_IO_10 (MTK_PIN_NO(41) | 5) +#define MT8135_PIN_41_DAC_WS__FUNC_TESTA_OUT23 (MTK_PIN_NO(41) | 7) + +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(42) | 1) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_EINT23 (MTK_PIN_NO(42) | 2) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_HDMI_SDATA3 (MTK_PIN_NO(42) | 3) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_USB_TEST_IO_11 (MTK_PIN_NO(42) | 5) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_TESTA_OUT24 (MTK_PIN_NO(42) | 7) + +#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(43) | 1) +#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_EINT29 (MTK_PIN_NO(43) | 2) + +#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(44) | 1) +#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_EINT28 (MTK_PIN_NO(44) | 2) + +#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(45) | 1) +#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_EINT27 (MTK_PIN_NO(45) | 2) + +#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(46) | 1) +#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_EINT26 (MTK_PIN_NO(46) | 2) + +#define MT8135_PIN_47_PWRAP_EVENT__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT8135_PIN_47_PWRAP_EVENT__FUNC_PWRAP_EVENT_IN (MTK_PIN_NO(47) | 1) +#define MT8135_PIN_47_PWRAP_EVENT__FUNC_EINT25 (MTK_PIN_NO(47) | 2) +#define MT8135_PIN_47_PWRAP_EVENT__FUNC_TESTA_OUT2 (MTK_PIN_NO(47) | 7) + +#define MT8135_PIN_48_RTC32K_CK__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT8135_PIN_48_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(48) | 1) + +#define MT8135_PIN_49_WATCHDOG__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT8135_PIN_49_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(49) | 1) +#define MT8135_PIN_49_WATCHDOG__FUNC_EINT36 (MTK_PIN_NO(49) | 2) + +#define MT8135_PIN_50_SRCLKENA__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT8135_PIN_50_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(50) | 1) +#define MT8135_PIN_50_SRCLKENA__FUNC_EINT38 (MTK_PIN_NO(50) | 2) + +#define MT8135_PIN_51_SRCVOLTEN__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT8135_PIN_51_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(51) | 1) +#define MT8135_PIN_51_SRCVOLTEN__FUNC_EINT37 (MTK_PIN_NO(51) | 2) + +#define MT8135_PIN_52_EINT0__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT8135_PIN_52_EINT0__FUNC_EINT0 (MTK_PIN_NO(52) | 1) +#define MT8135_PIN_52_EINT0__FUNC_PWM1 (MTK_PIN_NO(52) | 2) +#define MT8135_PIN_52_EINT0__FUNC_CLKM0 (MTK_PIN_NO(52) | 3) +#define MT8135_PIN_52_EINT0__FUNC_SPDIF_OUT (MTK_PIN_NO(52) | 4) +#define MT8135_PIN_52_EINT0__FUNC_USB_TEST_IO_12 (MTK_PIN_NO(52) | 5) +#define MT8135_PIN_52_EINT0__FUNC_USB_SCL (MTK_PIN_NO(52) | 7) + +#define MT8135_PIN_53_URXD2__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT8135_PIN_53_URXD2__FUNC_URXD2 (MTK_PIN_NO(53) | 1) +#define MT8135_PIN_53_URXD2__FUNC_EINT83 (MTK_PIN_NO(53) | 2) +#define MT8135_PIN_53_URXD2__FUNC_HDMI_LRCK (MTK_PIN_NO(53) | 4) +#define MT8135_PIN_53_URXD2__FUNC_CLKM3 (MTK_PIN_NO(53) | 5) +#define MT8135_PIN_53_URXD2__FUNC_UTXD2 (MTK_PIN_NO(53) | 7) + +#define MT8135_PIN_54_UTXD2__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT8135_PIN_54_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(54) | 1) +#define MT8135_PIN_54_UTXD2__FUNC_EINT82 (MTK_PIN_NO(54) | 2) +#define MT8135_PIN_54_UTXD2__FUNC_HDMI_BCK_OUT (MTK_PIN_NO(54) | 4) +#define MT8135_PIN_54_UTXD2__FUNC_CLKM2 (MTK_PIN_NO(54) | 5) +#define MT8135_PIN_54_UTXD2__FUNC_URXD2 (MTK_PIN_NO(54) | 7) + +#define MT8135_PIN_55_UCTS2__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT8135_PIN_55_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(55) | 1) +#define MT8135_PIN_55_UCTS2__FUNC_EINT84 (MTK_PIN_NO(55) | 2) +#define MT8135_PIN_55_UCTS2__FUNC_PWM1 (MTK_PIN_NO(55) | 5) +#define MT8135_PIN_55_UCTS2__FUNC_URTS2 (MTK_PIN_NO(55) | 7) + +#define MT8135_PIN_56_URTS2__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT8135_PIN_56_URTS2__FUNC_URTS2 (MTK_PIN_NO(56) | 1) +#define MT8135_PIN_56_URTS2__FUNC_EINT85 (MTK_PIN_NO(56) | 2) +#define MT8135_PIN_56_URTS2__FUNC_PWM2 (MTK_PIN_NO(56) | 5) +#define MT8135_PIN_56_URTS2__FUNC_UCTS2 (MTK_PIN_NO(56) | 7) + +#define MT8135_PIN_57_JTCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT8135_PIN_57_JTCK__FUNC_JTCK (MTK_PIN_NO(57) | 1) +#define MT8135_PIN_57_JTCK__FUNC_EINT188 (MTK_PIN_NO(57) | 2) +#define MT8135_PIN_57_JTCK__FUNC_DSP1_ICK (MTK_PIN_NO(57) | 3) + +#define MT8135_PIN_58_JTDO__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT8135_PIN_58_JTDO__FUNC_JTDO (MTK_PIN_NO(58) | 1) +#define MT8135_PIN_58_JTDO__FUNC_EINT190 (MTK_PIN_NO(58) | 2) +#define MT8135_PIN_58_JTDO__FUNC_DSP2_IMS (MTK_PIN_NO(58) | 3) + +#define MT8135_PIN_59_JTRST_B__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT8135_PIN_59_JTRST_B__FUNC_JTRST_B (MTK_PIN_NO(59) | 1) +#define MT8135_PIN_59_JTRST_B__FUNC_EINT0 (MTK_PIN_NO(59) | 2) +#define MT8135_PIN_59_JTRST_B__FUNC_DSP2_ICK (MTK_PIN_NO(59) | 3) + +#define MT8135_PIN_60_JTDI__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT8135_PIN_60_JTDI__FUNC_JTDI (MTK_PIN_NO(60) | 1) +#define MT8135_PIN_60_JTDI__FUNC_EINT189 (MTK_PIN_NO(60) | 2) +#define MT8135_PIN_60_JTDI__FUNC_DSP1_IMS (MTK_PIN_NO(60) | 3) + +#define MT8135_PIN_61_JRTCK__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT8135_PIN_61_JRTCK__FUNC_JRTCK (MTK_PIN_NO(61) | 1) +#define MT8135_PIN_61_JRTCK__FUNC_EINT187 (MTK_PIN_NO(61) | 2) +#define MT8135_PIN_61_JRTCK__FUNC_DSP1_ID (MTK_PIN_NO(61) | 3) + +#define MT8135_PIN_62_JTMS__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT8135_PIN_62_JTMS__FUNC_JTMS (MTK_PIN_NO(62) | 1) +#define MT8135_PIN_62_JTMS__FUNC_EINT191 (MTK_PIN_NO(62) | 2) +#define MT8135_PIN_62_JTMS__FUNC_DSP2_ID (MTK_PIN_NO(62) | 3) + +#define MT8135_PIN_63_MSDC1_INSI__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_MSDC1_INSI (MTK_PIN_NO(63) | 1) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_SCL5 (MTK_PIN_NO(63) | 3) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_PWM6 (MTK_PIN_NO(63) | 4) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_CLKM5 (MTK_PIN_NO(63) | 5) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_TESTB_OUT6 (MTK_PIN_NO(63) | 7) + +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_MSDC1_SDWPI (MTK_PIN_NO(64) | 1) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_EINT58 (MTK_PIN_NO(64) | 2) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_SDA5 (MTK_PIN_NO(64) | 3) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_PWM7 (MTK_PIN_NO(64) | 4) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_CLKM6 (MTK_PIN_NO(64) | 5) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_TESTB_OUT7 (MTK_PIN_NO(64) | 7) + +#define MT8135_PIN_65_MSDC2_INSI__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT8135_PIN_65_MSDC2_INSI__FUNC_MSDC2_INSI (MTK_PIN_NO(65) | 1) +#define MT8135_PIN_65_MSDC2_INSI__FUNC_USB_TEST_IO_27 (MTK_PIN_NO(65) | 5) +#define MT8135_PIN_65_MSDC2_INSI__FUNC_TESTA_OUT3 (MTK_PIN_NO(65) | 7) + +#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_MSDC2_SDWPI (MTK_PIN_NO(66) | 1) +#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_EINT66 (MTK_PIN_NO(66) | 2) +#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_USB_TEST_IO_28 (MTK_PIN_NO(66) | 5) + +#define MT8135_PIN_67_URXD4__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT8135_PIN_67_URXD4__FUNC_URXD4 (MTK_PIN_NO(67) | 1) +#define MT8135_PIN_67_URXD4__FUNC_EINT89 (MTK_PIN_NO(67) | 2) +#define MT8135_PIN_67_URXD4__FUNC_URXD1 (MTK_PIN_NO(67) | 3) +#define MT8135_PIN_67_URXD4__FUNC_UTXD4 (MTK_PIN_NO(67) | 6) +#define MT8135_PIN_67_URXD4__FUNC_TESTB_OUT10 (MTK_PIN_NO(67) | 7) + +#define MT8135_PIN_68_UTXD4__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT8135_PIN_68_UTXD4__FUNC_UTXD4 (MTK_PIN_NO(68) | 1) +#define MT8135_PIN_68_UTXD4__FUNC_EINT88 (MTK_PIN_NO(68) | 2) +#define MT8135_PIN_68_UTXD4__FUNC_UTXD1 (MTK_PIN_NO(68) | 3) +#define MT8135_PIN_68_UTXD4__FUNC_URXD4 (MTK_PIN_NO(68) | 6) +#define MT8135_PIN_68_UTXD4__FUNC_TESTB_OUT11 (MTK_PIN_NO(68) | 7) + +#define MT8135_PIN_69_URXD1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT8135_PIN_69_URXD1__FUNC_URXD1 (MTK_PIN_NO(69) | 1) +#define MT8135_PIN_69_URXD1__FUNC_EINT79 (MTK_PIN_NO(69) | 2) +#define MT8135_PIN_69_URXD1__FUNC_URXD4 (MTK_PIN_NO(69) | 3) +#define MT8135_PIN_69_URXD1__FUNC_UTXD1 (MTK_PIN_NO(69) | 6) +#define MT8135_PIN_69_URXD1__FUNC_TESTB_OUT24 (MTK_PIN_NO(69) | 7) + +#define MT8135_PIN_70_UTXD1__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT8135_PIN_70_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(70) | 1) +#define MT8135_PIN_70_UTXD1__FUNC_EINT78 (MTK_PIN_NO(70) | 2) +#define MT8135_PIN_70_UTXD1__FUNC_UTXD4 (MTK_PIN_NO(70) | 3) +#define MT8135_PIN_70_UTXD1__FUNC_URXD1 (MTK_PIN_NO(70) | 6) +#define MT8135_PIN_70_UTXD1__FUNC_TESTB_OUT25 (MTK_PIN_NO(70) | 7) + +#define MT8135_PIN_71_UCTS1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT8135_PIN_71_UCTS1__FUNC_UCTS1 (MTK_PIN_NO(71) | 1) +#define MT8135_PIN_71_UCTS1__FUNC_EINT80 (MTK_PIN_NO(71) | 2) +#define MT8135_PIN_71_UCTS1__FUNC_CLKM0 (MTK_PIN_NO(71) | 5) +#define MT8135_PIN_71_UCTS1__FUNC_URTS1 (MTK_PIN_NO(71) | 6) +#define MT8135_PIN_71_UCTS1__FUNC_TESTB_OUT31 (MTK_PIN_NO(71) | 7) + +#define MT8135_PIN_72_URTS1__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT8135_PIN_72_URTS1__FUNC_URTS1 (MTK_PIN_NO(72) | 1) +#define MT8135_PIN_72_URTS1__FUNC_EINT81 (MTK_PIN_NO(72) | 2) +#define MT8135_PIN_72_URTS1__FUNC_CLKM1 (MTK_PIN_NO(72) | 5) +#define MT8135_PIN_72_URTS1__FUNC_UCTS1 (MTK_PIN_NO(72) | 6) +#define MT8135_PIN_72_URTS1__FUNC_TESTB_OUT21 (MTK_PIN_NO(72) | 7) + +#define MT8135_PIN_73_PWM1__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT8135_PIN_73_PWM1__FUNC_PWM1 (MTK_PIN_NO(73) | 1) +#define MT8135_PIN_73_PWM1__FUNC_EINT73 (MTK_PIN_NO(73) | 2) +#define MT8135_PIN_73_PWM1__FUNC_USB_DRVVBUS (MTK_PIN_NO(73) | 5) +#define MT8135_PIN_73_PWM1__FUNC_DISP_PWM (MTK_PIN_NO(73) | 6) +#define MT8135_PIN_73_PWM1__FUNC_TESTB_OUT8 (MTK_PIN_NO(73) | 7) + +#define MT8135_PIN_74_PWM2__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define MT8135_PIN_74_PWM2__FUNC_PWM2 (MTK_PIN_NO(74) | 1) +#define MT8135_PIN_74_PWM2__FUNC_EINT74 (MTK_PIN_NO(74) | 2) +#define MT8135_PIN_74_PWM2__FUNC_DPI33_CK (MTK_PIN_NO(74) | 3) +#define MT8135_PIN_74_PWM2__FUNC_PWM5 (MTK_PIN_NO(74) | 4) +#define MT8135_PIN_74_PWM2__FUNC_URXD2 (MTK_PIN_NO(74) | 5) +#define MT8135_PIN_74_PWM2__FUNC_DISP_PWM (MTK_PIN_NO(74) | 6) +#define MT8135_PIN_74_PWM2__FUNC_TESTB_OUT9 (MTK_PIN_NO(74) | 7) + +#define MT8135_PIN_75_PWM3__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define MT8135_PIN_75_PWM3__FUNC_PWM3 (MTK_PIN_NO(75) | 1) +#define MT8135_PIN_75_PWM3__FUNC_EINT75 (MTK_PIN_NO(75) | 2) +#define MT8135_PIN_75_PWM3__FUNC_DPI33_D0 (MTK_PIN_NO(75) | 3) +#define MT8135_PIN_75_PWM3__FUNC_PWM6 (MTK_PIN_NO(75) | 4) +#define MT8135_PIN_75_PWM3__FUNC_UTXD2 (MTK_PIN_NO(75) | 5) +#define MT8135_PIN_75_PWM3__FUNC_DISP_PWM (MTK_PIN_NO(75) | 6) +#define MT8135_PIN_75_PWM3__FUNC_TESTB_OUT12 (MTK_PIN_NO(75) | 7) + +#define MT8135_PIN_76_PWM4__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define MT8135_PIN_76_PWM4__FUNC_PWM4 (MTK_PIN_NO(76) | 1) +#define MT8135_PIN_76_PWM4__FUNC_EINT76 (MTK_PIN_NO(76) | 2) +#define MT8135_PIN_76_PWM4__FUNC_DPI33_D1 (MTK_PIN_NO(76) | 3) +#define MT8135_PIN_76_PWM4__FUNC_PWM7 (MTK_PIN_NO(76) | 4) +#define MT8135_PIN_76_PWM4__FUNC_DISP_PWM (MTK_PIN_NO(76) | 6) +#define MT8135_PIN_76_PWM4__FUNC_TESTB_OUT13 (MTK_PIN_NO(76) | 7) + +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(77) | 1) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_EINT63 (MTK_PIN_NO(77) | 2) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DSP2_IMS (MTK_PIN_NO(77) | 4) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DPI33_D6 (MTK_PIN_NO(77) | 6) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_TESTA_OUT25 (MTK_PIN_NO(77) | 7) + +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(78) | 1) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_EINT64 (MTK_PIN_NO(78) | 2) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DSP2_ID (MTK_PIN_NO(78) | 4) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DPI33_D7 (MTK_PIN_NO(78) | 6) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_TESTA_OUT26 (MTK_PIN_NO(78) | 7) + +#define MT8135_PIN_79_MSDC2_CMD__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(79) | 1) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_EINT60 (MTK_PIN_NO(79) | 2) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_DSP1_IMS (MTK_PIN_NO(79) | 4) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_PCM1_WS (MTK_PIN_NO(79) | 5) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_DPI33_D3 (MTK_PIN_NO(79) | 6) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_TESTA_OUT0 (MTK_PIN_NO(79) | 7) + +#define MT8135_PIN_80_MSDC2_CLK__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(80) | 1) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_EINT59 (MTK_PIN_NO(80) | 2) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_DSP1_ICK (MTK_PIN_NO(80) | 4) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_PCM1_CK (MTK_PIN_NO(80) | 5) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_DPI33_D2 (MTK_PIN_NO(80) | 6) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_TESTA_OUT1 (MTK_PIN_NO(80) | 7) + +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(81) | 1) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_EINT62 (MTK_PIN_NO(81) | 2) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DSP2_ICK (MTK_PIN_NO(81) | 4) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_PCM1_DO (MTK_PIN_NO(81) | 5) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DPI33_D5 (MTK_PIN_NO(81) | 6) + +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_EINT61 (MTK_PIN_NO(82) | 2) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DSP1_ID (MTK_PIN_NO(82) | 4) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_PCM1_DI (MTK_PIN_NO(82) | 5) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DPI33_D4 (MTK_PIN_NO(82) | 6) + +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(83) | 1) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_EINT53 (MTK_PIN_NO(83) | 2) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_SCL1 (MTK_PIN_NO(83) | 3) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_PWM2 (MTK_PIN_NO(83) | 4) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_CLKM1 (MTK_PIN_NO(83) | 5) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_TESTB_OUT2 (MTK_PIN_NO(83) | 7) + +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(84) | 1) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_EINT54 (MTK_PIN_NO(84) | 2) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_SDA1 (MTK_PIN_NO(84) | 3) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_PWM3 (MTK_PIN_NO(84) | 4) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_CLKM2 (MTK_PIN_NO(84) | 5) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_TESTB_OUT3 (MTK_PIN_NO(84) | 7) + +#define MT8135_PIN_85_MSDC1_CMD__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(85) | 1) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_EINT52 (MTK_PIN_NO(85) | 2) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_SDA0 (MTK_PIN_NO(85) | 3) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_PWM1 (MTK_PIN_NO(85) | 4) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_CLKM0 (MTK_PIN_NO(85) | 5) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_TESTB_OUT1 (MTK_PIN_NO(85) | 7) + +#define MT8135_PIN_86_MSDC1_CLK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(86) | 1) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_EINT51 (MTK_PIN_NO(86) | 2) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_SCL0 (MTK_PIN_NO(86) | 3) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_DISP_PWM (MTK_PIN_NO(86) | 4) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_TESTB_OUT0 (MTK_PIN_NO(86) | 7) + +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(87) | 1) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_EINT55 (MTK_PIN_NO(87) | 2) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_SCL4 (MTK_PIN_NO(87) | 3) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_PWM4 (MTK_PIN_NO(87) | 4) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_CLKM3 (MTK_PIN_NO(87) | 5) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_TESTB_OUT4 (MTK_PIN_NO(87) | 7) + +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(88) | 1) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_EINT56 (MTK_PIN_NO(88) | 2) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_SDA4 (MTK_PIN_NO(88) | 3) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_PWM5 (MTK_PIN_NO(88) | 4) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_CLKM4 (MTK_PIN_NO(88) | 5) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_TESTB_OUT5 (MTK_PIN_NO(88) | 7) + +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_MSDC4_DAT0 (MTK_PIN_NO(89) | 1) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EINT133 (MTK_PIN_NO(89) | 2) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(89) | 4) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_USB_DRVVBUS (MTK_PIN_NO(89) | 5) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_A_FUNC_DIN_9 (MTK_PIN_NO(89) | 6) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_LPTE (MTK_PIN_NO(89) | 7) + +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_MSDC4_DAT1 (MTK_PIN_NO(90) | 1) +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_EINT134 (MTK_PIN_NO(90) | 2) +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_A_FUNC_DIN_10 (MTK_PIN_NO(90) | 6) +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_LRSTB_1X (MTK_PIN_NO(90) | 7) + +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_MSDC4_DAT5 (MTK_PIN_NO(91) | 1) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_EINT136 (MTK_PIN_NO(91) | 2) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_I2SIN_WS (MTK_PIN_NO(91) | 3) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_DAC_WS (MTK_PIN_NO(91) | 4) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_PCM1_WS (MTK_PIN_NO(91) | 5) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_A_FUNC_DIN_11 (MTK_PIN_NO(91) | 6) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_SPI1_CSN (MTK_PIN_NO(91) | 7) + +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_MSDC4_DAT6 (MTK_PIN_NO(92) | 1) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_EINT137 (MTK_PIN_NO(92) | 2) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_I2SOUT_DAT (MTK_PIN_NO(92) | 3) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_DAC_DAT_OUT (MTK_PIN_NO(92) | 4) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_PCM1_DO (MTK_PIN_NO(92) | 5) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_A_FUNC_DIN_12 (MTK_PIN_NO(92) | 6) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_SPI1_MO (MTK_PIN_NO(92) | 7) + +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_MSDC4_DAT7 (MTK_PIN_NO(93) | 1) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_EINT138 (MTK_PIN_NO(93) | 2) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_I2SIN_DAT (MTK_PIN_NO(93) | 3) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_PCM1_DI (MTK_PIN_NO(93) | 5) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_A_FUNC_DIN_13 (MTK_PIN_NO(93) | 6) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_SPI1_MI (MTK_PIN_NO(93) | 7) + +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_MSDC4_DAT4 (MTK_PIN_NO(94) | 1) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_EINT135 (MTK_PIN_NO(94) | 2) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_I2SIN_CK (MTK_PIN_NO(94) | 3) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_DAC_CK (MTK_PIN_NO(94) | 4) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_PCM1_CK (MTK_PIN_NO(94) | 5) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_A_FUNC_DIN_14 (MTK_PIN_NO(94) | 6) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_SPI1_CLK (MTK_PIN_NO(94) | 7) + +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_MSDC4_DAT2 (MTK_PIN_NO(95) | 1) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_EINT131 (MTK_PIN_NO(95) | 2) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_I2SIN_WS (MTK_PIN_NO(95) | 3) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_CM2PDN_2X (MTK_PIN_NO(95) | 4) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_DAC_WS (MTK_PIN_NO(95) | 5) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_PCM1_WS (MTK_PIN_NO(95) | 6) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_LSCE0B_1X (MTK_PIN_NO(95) | 7) + +#define MT8135_PIN_96_MSDC4_CLK__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_MSDC4_CLK (MTK_PIN_NO(96) | 1) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_EINT129 (MTK_PIN_NO(96) | 2) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_DPI1_CK_2X (MTK_PIN_NO(96) | 3) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_CM2PCLK_2X (MTK_PIN_NO(96) | 4) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_PWM4 (MTK_PIN_NO(96) | 5) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_PCM1_DI (MTK_PIN_NO(96) | 6) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_LSCK_1X (MTK_PIN_NO(96) | 7) + +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_MSDC4_DAT3 (MTK_PIN_NO(97) | 1) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_EINT132 (MTK_PIN_NO(97) | 2) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_I2SOUT_DAT (MTK_PIN_NO(97) | 3) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_CM2RST_2X (MTK_PIN_NO(97) | 4) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_DAC_DAT_OUT (MTK_PIN_NO(97) | 5) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_PCM1_DO (MTK_PIN_NO(97) | 6) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_LSCE1B_1X (MTK_PIN_NO(97) | 7) + +#define MT8135_PIN_98_MSDC4_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_MSDC4_CMD (MTK_PIN_NO(98) | 1) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_EINT128 (MTK_PIN_NO(98) | 2) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_DPI1_DE_2X (MTK_PIN_NO(98) | 3) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_PWM3 (MTK_PIN_NO(98) | 5) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_LSDA_1X (MTK_PIN_NO(98) | 7) + +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_MSDC4_RSTB (MTK_PIN_NO(99) | 1) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_EINT130 (MTK_PIN_NO(99) | 2) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_I2SIN_CK (MTK_PIN_NO(99) | 3) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_CM2MCLK_2X (MTK_PIN_NO(99) | 4) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_DAC_CK (MTK_PIN_NO(99) | 5) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_PCM1_CK (MTK_PIN_NO(99) | 6) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_LSA0_1X (MTK_PIN_NO(99) | 7) + +#define MT8135_PIN_100_SDA0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT8135_PIN_100_SDA0__FUNC_SDA0 (MTK_PIN_NO(100) | 1) +#define MT8135_PIN_100_SDA0__FUNC_EINT91 (MTK_PIN_NO(100) | 2) +#define MT8135_PIN_100_SDA0__FUNC_CLKM1 (MTK_PIN_NO(100) | 3) +#define MT8135_PIN_100_SDA0__FUNC_PWM1 (MTK_PIN_NO(100) | 4) +#define MT8135_PIN_100_SDA0__FUNC_A_FUNC_DIN_15 (MTK_PIN_NO(100) | 7) + +#define MT8135_PIN_101_SCL0__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT8135_PIN_101_SCL0__FUNC_SCL0 (MTK_PIN_NO(101) | 1) +#define MT8135_PIN_101_SCL0__FUNC_EINT90 (MTK_PIN_NO(101) | 2) +#define MT8135_PIN_101_SCL0__FUNC_CLKM0 (MTK_PIN_NO(101) | 3) +#define MT8135_PIN_101_SCL0__FUNC_DISP_PWM (MTK_PIN_NO(101) | 4) +#define MT8135_PIN_101_SCL0__FUNC_A_FUNC_DIN_16 (MTK_PIN_NO(101) | 7) + +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_EINT10 (MTK_PIN_NO(102) | 1) +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_USB_TEST_IO_16 (MTK_PIN_NO(102) | 5) +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_TESTB_OUT16 (MTK_PIN_NO(102) | 6) +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_A_FUNC_DIN_17 (MTK_PIN_NO(102) | 7) + +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_EINT11 (MTK_PIN_NO(103) | 1) +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_USB_TEST_IO_17 (MTK_PIN_NO(103) | 5) +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_TESTB_OUT17 (MTK_PIN_NO(103) | 6) +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_A_FUNC_DIN_18 (MTK_PIN_NO(103) | 7) + +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_EINT16 (MTK_PIN_NO(104) | 1) +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_USB_TEST_IO_18 (MTK_PIN_NO(104) | 5) +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_TESTB_OUT18 (MTK_PIN_NO(104) | 6) +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_A_FUNC_DIN_19 (MTK_PIN_NO(104) | 7) + +#define MT8135_PIN_105_I2S_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT8135_PIN_105_I2S_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(105) | 1) +#define MT8135_PIN_105_I2S_CLK__FUNC_EINT10 (MTK_PIN_NO(105) | 2) +#define MT8135_PIN_105_I2S_CLK__FUNC_DAC_CK (MTK_PIN_NO(105) | 3) +#define MT8135_PIN_105_I2S_CLK__FUNC_PCM1_CK (MTK_PIN_NO(105) | 4) +#define MT8135_PIN_105_I2S_CLK__FUNC_USB_TEST_IO_19 (MTK_PIN_NO(105) | 5) +#define MT8135_PIN_105_I2S_CLK__FUNC_TESTB_OUT19 (MTK_PIN_NO(105) | 6) +#define MT8135_PIN_105_I2S_CLK__FUNC_A_FUNC_DIN_20 (MTK_PIN_NO(105) | 7) + +#define MT8135_PIN_106_I2S_WS__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT8135_PIN_106_I2S_WS__FUNC_I2SIN_WS (MTK_PIN_NO(106) | 1) +#define MT8135_PIN_106_I2S_WS__FUNC_EINT13 (MTK_PIN_NO(106) | 2) +#define MT8135_PIN_106_I2S_WS__FUNC_DAC_WS (MTK_PIN_NO(106) | 3) +#define MT8135_PIN_106_I2S_WS__FUNC_PCM1_WS (MTK_PIN_NO(106) | 4) +#define MT8135_PIN_106_I2S_WS__FUNC_USB_TEST_IO_20 (MTK_PIN_NO(106) | 5) +#define MT8135_PIN_106_I2S_WS__FUNC_TESTB_OUT20 (MTK_PIN_NO(106) | 6) +#define MT8135_PIN_106_I2S_WS__FUNC_A_FUNC_DIN_21 (MTK_PIN_NO(106) | 7) + +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_I2SIN_DAT (MTK_PIN_NO(107) | 1) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_EINT11 (MTK_PIN_NO(107) | 2) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_PCM1_DI (MTK_PIN_NO(107) | 4) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_USB_TEST_IO_21 (MTK_PIN_NO(107) | 5) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_TESTB_OUT22 (MTK_PIN_NO(107) | 6) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_A_FUNC_DIN_22 (MTK_PIN_NO(107) | 7) + +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_I2SOUT_DAT (MTK_PIN_NO(108) | 1) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_EINT12 (MTK_PIN_NO(108) | 2) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(108) | 3) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_PCM1_DO (MTK_PIN_NO(108) | 4) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_USB_TEST_IO_22 (MTK_PIN_NO(108) | 5) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_TESTB_OUT23 (MTK_PIN_NO(108) | 6) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_A_FUNC_DIN_23 (MTK_PIN_NO(108) | 7) + +#define MT8135_PIN_109_EINT5__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT8135_PIN_109_EINT5__FUNC_EINT5 (MTK_PIN_NO(109) | 1) +#define MT8135_PIN_109_EINT5__FUNC_PWM5 (MTK_PIN_NO(109) | 2) +#define MT8135_PIN_109_EINT5__FUNC_CLKM3 (MTK_PIN_NO(109) | 3) +#define MT8135_PIN_109_EINT5__FUNC_GPU_JTRSTB (MTK_PIN_NO(109) | 4) +#define MT8135_PIN_109_EINT5__FUNC_USB_TEST_IO_23 (MTK_PIN_NO(109) | 5) +#define MT8135_PIN_109_EINT5__FUNC_TESTB_OUT26 (MTK_PIN_NO(109) | 6) +#define MT8135_PIN_109_EINT5__FUNC_A_FUNC_DIN_24 (MTK_PIN_NO(109) | 7) + +#define MT8135_PIN_110_EINT6__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT8135_PIN_110_EINT6__FUNC_EINT6 (MTK_PIN_NO(110) | 1) +#define MT8135_PIN_110_EINT6__FUNC_PWM6 (MTK_PIN_NO(110) | 2) +#define MT8135_PIN_110_EINT6__FUNC_CLKM4 (MTK_PIN_NO(110) | 3) +#define MT8135_PIN_110_EINT6__FUNC_GPU_JTMS (MTK_PIN_NO(110) | 4) +#define MT8135_PIN_110_EINT6__FUNC_USB_TEST_IO_24 (MTK_PIN_NO(110) | 5) +#define MT8135_PIN_110_EINT6__FUNC_TESTB_OUT27 (MTK_PIN_NO(110) | 6) +#define MT8135_PIN_110_EINT6__FUNC_A_FUNC_DIN_25 (MTK_PIN_NO(110) | 7) + +#define MT8135_PIN_111_EINT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT8135_PIN_111_EINT7__FUNC_EINT7 (MTK_PIN_NO(111) | 1) +#define MT8135_PIN_111_EINT7__FUNC_PWM7 (MTK_PIN_NO(111) | 2) +#define MT8135_PIN_111_EINT7__FUNC_CLKM5 (MTK_PIN_NO(111) | 3) +#define MT8135_PIN_111_EINT7__FUNC_GPU_JTDO (MTK_PIN_NO(111) | 4) +#define MT8135_PIN_111_EINT7__FUNC_USB_TEST_IO_25 (MTK_PIN_NO(111) | 5) +#define MT8135_PIN_111_EINT7__FUNC_TESTB_OUT28 (MTK_PIN_NO(111) | 6) +#define MT8135_PIN_111_EINT7__FUNC_A_FUNC_DIN_26 (MTK_PIN_NO(111) | 7) + +#define MT8135_PIN_112_EINT8__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT8135_PIN_112_EINT8__FUNC_EINT8 (MTK_PIN_NO(112) | 1) +#define MT8135_PIN_112_EINT8__FUNC_DISP_PWM (MTK_PIN_NO(112) | 2) +#define MT8135_PIN_112_EINT8__FUNC_CLKM6 (MTK_PIN_NO(112) | 3) +#define MT8135_PIN_112_EINT8__FUNC_GPU_JTDI (MTK_PIN_NO(112) | 4) +#define MT8135_PIN_112_EINT8__FUNC_USB_TEST_IO_26 (MTK_PIN_NO(112) | 5) +#define MT8135_PIN_112_EINT8__FUNC_TESTB_OUT29 (MTK_PIN_NO(112) | 6) +#define MT8135_PIN_112_EINT8__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(112) | 7) + +#define MT8135_PIN_113_EINT9__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT8135_PIN_113_EINT9__FUNC_EINT9 (MTK_PIN_NO(113) | 1) +#define MT8135_PIN_113_EINT9__FUNC_GPU_JTCK (MTK_PIN_NO(113) | 4) +#define MT8135_PIN_113_EINT9__FUNC_USB_DRVVBUS (MTK_PIN_NO(113) | 5) +#define MT8135_PIN_113_EINT9__FUNC_TESTB_OUT30 (MTK_PIN_NO(113) | 6) +#define MT8135_PIN_113_EINT9__FUNC_A_FUNC_DIN_27 (MTK_PIN_NO(113) | 7) + +#define MT8135_PIN_114_LPCE1B__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT8135_PIN_114_LPCE1B__FUNC_LPCE1B (MTK_PIN_NO(114) | 1) +#define MT8135_PIN_114_LPCE1B__FUNC_EINT127 (MTK_PIN_NO(114) | 2) +#define MT8135_PIN_114_LPCE1B__FUNC_PWM2 (MTK_PIN_NO(114) | 5) +#define MT8135_PIN_114_LPCE1B__FUNC_TESTB_OUT14 (MTK_PIN_NO(114) | 6) +#define MT8135_PIN_114_LPCE1B__FUNC_A_FUNC_DIN_28 (MTK_PIN_NO(114) | 7) + +#define MT8135_PIN_115_LPCE0B__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT8135_PIN_115_LPCE0B__FUNC_LPCE0B (MTK_PIN_NO(115) | 1) +#define MT8135_PIN_115_LPCE0B__FUNC_EINT126 (MTK_PIN_NO(115) | 2) +#define MT8135_PIN_115_LPCE0B__FUNC_PWM1 (MTK_PIN_NO(115) | 5) +#define MT8135_PIN_115_LPCE0B__FUNC_TESTB_OUT15 (MTK_PIN_NO(115) | 6) +#define MT8135_PIN_115_LPCE0B__FUNC_A_FUNC_DIN_29 (MTK_PIN_NO(115) | 7) + +#define MT8135_PIN_116_DISP_PWM__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT8135_PIN_116_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(116) | 1) +#define MT8135_PIN_116_DISP_PWM__FUNC_EINT77 (MTK_PIN_NO(116) | 2) +#define MT8135_PIN_116_DISP_PWM__FUNC_LSDI (MTK_PIN_NO(116) | 3) +#define MT8135_PIN_116_DISP_PWM__FUNC_PWM1 (MTK_PIN_NO(116) | 4) +#define MT8135_PIN_116_DISP_PWM__FUNC_PWM2 (MTK_PIN_NO(116) | 5) +#define MT8135_PIN_116_DISP_PWM__FUNC_PWM3 (MTK_PIN_NO(116) | 7) + +#define MT8135_PIN_117_EINT1__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT8135_PIN_117_EINT1__FUNC_EINT1 (MTK_PIN_NO(117) | 1) +#define MT8135_PIN_117_EINT1__FUNC_PWM2 (MTK_PIN_NO(117) | 2) +#define MT8135_PIN_117_EINT1__FUNC_CLKM1 (MTK_PIN_NO(117) | 3) +#define MT8135_PIN_117_EINT1__FUNC_USB_TEST_IO_13 (MTK_PIN_NO(117) | 5) +#define MT8135_PIN_117_EINT1__FUNC_USB_SDA (MTK_PIN_NO(117) | 7) + +#define MT8135_PIN_118_EINT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT8135_PIN_118_EINT2__FUNC_EINT2 (MTK_PIN_NO(118) | 1) +#define MT8135_PIN_118_EINT2__FUNC_PWM3 (MTK_PIN_NO(118) | 2) +#define MT8135_PIN_118_EINT2__FUNC_CLKM2 (MTK_PIN_NO(118) | 3) +#define MT8135_PIN_118_EINT2__FUNC_USB_TEST_IO_14 (MTK_PIN_NO(118) | 5) +#define MT8135_PIN_118_EINT2__FUNC_SRCLKENAI2 (MTK_PIN_NO(118) | 6) +#define MT8135_PIN_118_EINT2__FUNC_A_FUNC_DIN_30 (MTK_PIN_NO(118) | 7) + +#define MT8135_PIN_119_EINT3__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT8135_PIN_119_EINT3__FUNC_EINT3 (MTK_PIN_NO(119) | 1) +#define MT8135_PIN_119_EINT3__FUNC_USB_TEST_IO_15 (MTK_PIN_NO(119) | 5) +#define MT8135_PIN_119_EINT3__FUNC_SRCLKENAI1 (MTK_PIN_NO(119) | 6) +#define MT8135_PIN_119_EINT3__FUNC_EXT_26M_CK (MTK_PIN_NO(119) | 7) + +#define MT8135_PIN_120_EINT4__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT8135_PIN_120_EINT4__FUNC_EINT4 (MTK_PIN_NO(120) | 1) +#define MT8135_PIN_120_EINT4__FUNC_PWM4 (MTK_PIN_NO(120) | 2) +#define MT8135_PIN_120_EINT4__FUNC_USB_DRVVBUS (MTK_PIN_NO(120) | 5) +#define MT8135_PIN_120_EINT4__FUNC_A_FUNC_DIN_31 (MTK_PIN_NO(120) | 7) + +#define MT8135_PIN_121_DPIDE__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT8135_PIN_121_DPIDE__FUNC_DPI0_DE (MTK_PIN_NO(121) | 1) +#define MT8135_PIN_121_DPIDE__FUNC_EINT100 (MTK_PIN_NO(121) | 2) +#define MT8135_PIN_121_DPIDE__FUNC_I2SOUT_DAT (MTK_PIN_NO(121) | 3) +#define MT8135_PIN_121_DPIDE__FUNC_DAC_DAT_OUT (MTK_PIN_NO(121) | 4) +#define MT8135_PIN_121_DPIDE__FUNC_PCM1_DO (MTK_PIN_NO(121) | 5) +#define MT8135_PIN_121_DPIDE__FUNC_IRDA_TXD (MTK_PIN_NO(121) | 6) + +#define MT8135_PIN_122_DPICK__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT8135_PIN_122_DPICK__FUNC_DPI0_CK (MTK_PIN_NO(122) | 1) +#define MT8135_PIN_122_DPICK__FUNC_EINT101 (MTK_PIN_NO(122) | 2) +#define MT8135_PIN_122_DPICK__FUNC_I2SIN_DAT (MTK_PIN_NO(122) | 3) +#define MT8135_PIN_122_DPICK__FUNC_PCM1_DI (MTK_PIN_NO(122) | 5) +#define MT8135_PIN_122_DPICK__FUNC_IRDA_PDN (MTK_PIN_NO(122) | 6) + +#define MT8135_PIN_123_DPIG4__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT8135_PIN_123_DPIG4__FUNC_DPI0_G4 (MTK_PIN_NO(123) | 1) +#define MT8135_PIN_123_DPIG4__FUNC_EINT114 (MTK_PIN_NO(123) | 2) +#define MT8135_PIN_123_DPIG4__FUNC_CM2DAT_2X_0 (MTK_PIN_NO(123) | 4) +#define MT8135_PIN_123_DPIG4__FUNC_DSP2_ID (MTK_PIN_NO(123) | 5) + +#define MT8135_PIN_124_DPIG5__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT8135_PIN_124_DPIG5__FUNC_DPI0_G5 (MTK_PIN_NO(124) | 1) +#define MT8135_PIN_124_DPIG5__FUNC_EINT115 (MTK_PIN_NO(124) | 2) +#define MT8135_PIN_124_DPIG5__FUNC_CM2DAT_2X_1 (MTK_PIN_NO(124) | 4) +#define MT8135_PIN_124_DPIG5__FUNC_DSP2_ICK (MTK_PIN_NO(124) | 5) + +#define MT8135_PIN_125_DPIR3__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define MT8135_PIN_125_DPIR3__FUNC_DPI0_R3 (MTK_PIN_NO(125) | 1) +#define MT8135_PIN_125_DPIR3__FUNC_EINT121 (MTK_PIN_NO(125) | 2) +#define MT8135_PIN_125_DPIR3__FUNC_CM2DAT_2X_7 (MTK_PIN_NO(125) | 4) + +#define MT8135_PIN_126_DPIG1__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define MT8135_PIN_126_DPIG1__FUNC_DPI0_G1 (MTK_PIN_NO(126) | 1) +#define MT8135_PIN_126_DPIG1__FUNC_EINT111 (MTK_PIN_NO(126) | 2) +#define MT8135_PIN_126_DPIG1__FUNC_DSP1_ICK (MTK_PIN_NO(126) | 5) + +#define MT8135_PIN_127_DPIVSYNC__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define MT8135_PIN_127_DPIVSYNC__FUNC_DPI0_VSYNC (MTK_PIN_NO(127) | 1) +#define MT8135_PIN_127_DPIVSYNC__FUNC_EINT98 (MTK_PIN_NO(127) | 2) +#define MT8135_PIN_127_DPIVSYNC__FUNC_I2SIN_CK (MTK_PIN_NO(127) | 3) +#define MT8135_PIN_127_DPIVSYNC__FUNC_DAC_CK (MTK_PIN_NO(127) | 4) +#define MT8135_PIN_127_DPIVSYNC__FUNC_PCM1_CK (MTK_PIN_NO(127) | 5) + +#define MT8135_PIN_128_DPIHSYNC__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define MT8135_PIN_128_DPIHSYNC__FUNC_DPI0_HSYNC (MTK_PIN_NO(128) | 1) +#define MT8135_PIN_128_DPIHSYNC__FUNC_EINT99 (MTK_PIN_NO(128) | 2) +#define MT8135_PIN_128_DPIHSYNC__FUNC_I2SIN_WS (MTK_PIN_NO(128) | 3) +#define MT8135_PIN_128_DPIHSYNC__FUNC_DAC_WS (MTK_PIN_NO(128) | 4) +#define MT8135_PIN_128_DPIHSYNC__FUNC_PCM1_WS (MTK_PIN_NO(128) | 5) +#define MT8135_PIN_128_DPIHSYNC__FUNC_IRDA_RXD (MTK_PIN_NO(128) | 6) + +#define MT8135_PIN_129_DPIB0__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define MT8135_PIN_129_DPIB0__FUNC_DPI0_B0 (MTK_PIN_NO(129) | 1) +#define MT8135_PIN_129_DPIB0__FUNC_EINT102 (MTK_PIN_NO(129) | 2) +#define MT8135_PIN_129_DPIB0__FUNC_SCL0 (MTK_PIN_NO(129) | 4) +#define MT8135_PIN_129_DPIB0__FUNC_DISP_PWM (MTK_PIN_NO(129) | 5) + +#define MT8135_PIN_130_DPIB1__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define MT8135_PIN_130_DPIB1__FUNC_DPI0_B1 (MTK_PIN_NO(130) | 1) +#define MT8135_PIN_130_DPIB1__FUNC_EINT103 (MTK_PIN_NO(130) | 2) +#define MT8135_PIN_130_DPIB1__FUNC_CLKM0 (MTK_PIN_NO(130) | 3) +#define MT8135_PIN_130_DPIB1__FUNC_SDA0 (MTK_PIN_NO(130) | 4) +#define MT8135_PIN_130_DPIB1__FUNC_PWM1 (MTK_PIN_NO(130) | 5) + +#define MT8135_PIN_131_DPIB2__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define MT8135_PIN_131_DPIB2__FUNC_DPI0_B2 (MTK_PIN_NO(131) | 1) +#define MT8135_PIN_131_DPIB2__FUNC_EINT104 (MTK_PIN_NO(131) | 2) +#define MT8135_PIN_131_DPIB2__FUNC_CLKM1 (MTK_PIN_NO(131) | 3) +#define MT8135_PIN_131_DPIB2__FUNC_SCL1 (MTK_PIN_NO(131) | 4) +#define MT8135_PIN_131_DPIB2__FUNC_PWM2 (MTK_PIN_NO(131) | 5) + +#define MT8135_PIN_132_DPIB3__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define MT8135_PIN_132_DPIB3__FUNC_DPI0_B3 (MTK_PIN_NO(132) | 1) +#define MT8135_PIN_132_DPIB3__FUNC_EINT105 (MTK_PIN_NO(132) | 2) +#define MT8135_PIN_132_DPIB3__FUNC_CLKM2 (MTK_PIN_NO(132) | 3) +#define MT8135_PIN_132_DPIB3__FUNC_SDA1 (MTK_PIN_NO(132) | 4) +#define MT8135_PIN_132_DPIB3__FUNC_PWM3 (MTK_PIN_NO(132) | 5) + +#define MT8135_PIN_133_DPIB4__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define MT8135_PIN_133_DPIB4__FUNC_DPI0_B4 (MTK_PIN_NO(133) | 1) +#define MT8135_PIN_133_DPIB4__FUNC_EINT106 (MTK_PIN_NO(133) | 2) +#define MT8135_PIN_133_DPIB4__FUNC_CLKM3 (MTK_PIN_NO(133) | 3) +#define MT8135_PIN_133_DPIB4__FUNC_SCL2 (MTK_PIN_NO(133) | 4) +#define MT8135_PIN_133_DPIB4__FUNC_PWM4 (MTK_PIN_NO(133) | 5) + +#define MT8135_PIN_134_DPIB5__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define MT8135_PIN_134_DPIB5__FUNC_DPI0_B5 (MTK_PIN_NO(134) | 1) +#define MT8135_PIN_134_DPIB5__FUNC_EINT107 (MTK_PIN_NO(134) | 2) +#define MT8135_PIN_134_DPIB5__FUNC_CLKM4 (MTK_PIN_NO(134) | 3) +#define MT8135_PIN_134_DPIB5__FUNC_SDA2 (MTK_PIN_NO(134) | 4) +#define MT8135_PIN_134_DPIB5__FUNC_PWM5 (MTK_PIN_NO(134) | 5) + +#define MT8135_PIN_135_DPIB6__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define MT8135_PIN_135_DPIB6__FUNC_DPI0_B6 (MTK_PIN_NO(135) | 1) +#define MT8135_PIN_135_DPIB6__FUNC_EINT108 (MTK_PIN_NO(135) | 2) +#define MT8135_PIN_135_DPIB6__FUNC_CLKM5 (MTK_PIN_NO(135) | 3) +#define MT8135_PIN_135_DPIB6__FUNC_SCL3 (MTK_PIN_NO(135) | 4) +#define MT8135_PIN_135_DPIB6__FUNC_PWM6 (MTK_PIN_NO(135) | 5) + +#define MT8135_PIN_136_DPIB7__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define MT8135_PIN_136_DPIB7__FUNC_DPI0_B7 (MTK_PIN_NO(136) | 1) +#define MT8135_PIN_136_DPIB7__FUNC_EINT109 (MTK_PIN_NO(136) | 2) +#define MT8135_PIN_136_DPIB7__FUNC_CLKM6 (MTK_PIN_NO(136) | 3) +#define MT8135_PIN_136_DPIB7__FUNC_SDA3 (MTK_PIN_NO(136) | 4) +#define MT8135_PIN_136_DPIB7__FUNC_PWM7 (MTK_PIN_NO(136) | 5) + +#define MT8135_PIN_137_DPIG0__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define MT8135_PIN_137_DPIG0__FUNC_DPI0_G0 (MTK_PIN_NO(137) | 1) +#define MT8135_PIN_137_DPIG0__FUNC_EINT110 (MTK_PIN_NO(137) | 2) +#define MT8135_PIN_137_DPIG0__FUNC_DSP1_ID (MTK_PIN_NO(137) | 5) + +#define MT8135_PIN_138_DPIG2__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define MT8135_PIN_138_DPIG2__FUNC_DPI0_G2 (MTK_PIN_NO(138) | 1) +#define MT8135_PIN_138_DPIG2__FUNC_EINT112 (MTK_PIN_NO(138) | 2) +#define MT8135_PIN_138_DPIG2__FUNC_DSP1_IMS (MTK_PIN_NO(138) | 5) + +#define MT8135_PIN_139_DPIG3__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define MT8135_PIN_139_DPIG3__FUNC_DPI0_G3 (MTK_PIN_NO(139) | 1) +#define MT8135_PIN_139_DPIG3__FUNC_EINT113 (MTK_PIN_NO(139) | 2) +#define MT8135_PIN_139_DPIG3__FUNC_DSP2_IMS (MTK_PIN_NO(139) | 5) + +#define MT8135_PIN_140_DPIG6__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define MT8135_PIN_140_DPIG6__FUNC_DPI0_G6 (MTK_PIN_NO(140) | 1) +#define MT8135_PIN_140_DPIG6__FUNC_EINT116 (MTK_PIN_NO(140) | 2) +#define MT8135_PIN_140_DPIG6__FUNC_CM2DAT_2X_2 (MTK_PIN_NO(140) | 4) + +#define MT8135_PIN_141_DPIG7__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define MT8135_PIN_141_DPIG7__FUNC_DPI0_G7 (MTK_PIN_NO(141) | 1) +#define MT8135_PIN_141_DPIG7__FUNC_EINT117 (MTK_PIN_NO(141) | 2) +#define MT8135_PIN_141_DPIG7__FUNC_CM2DAT_2X_3 (MTK_PIN_NO(141) | 4) + +#define MT8135_PIN_142_DPIR0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define MT8135_PIN_142_DPIR0__FUNC_DPI0_R0 (MTK_PIN_NO(142) | 1) +#define MT8135_PIN_142_DPIR0__FUNC_EINT118 (MTK_PIN_NO(142) | 2) +#define MT8135_PIN_142_DPIR0__FUNC_CM2DAT_2X_4 (MTK_PIN_NO(142) | 4) + +#define MT8135_PIN_143_DPIR1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define MT8135_PIN_143_DPIR1__FUNC_DPI0_R1 (MTK_PIN_NO(143) | 1) +#define MT8135_PIN_143_DPIR1__FUNC_EINT119 (MTK_PIN_NO(143) | 2) +#define MT8135_PIN_143_DPIR1__FUNC_CM2DAT_2X_5 (MTK_PIN_NO(143) | 4) + +#define MT8135_PIN_144_DPIR2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define MT8135_PIN_144_DPIR2__FUNC_DPI0_R2 (MTK_PIN_NO(144) | 1) +#define MT8135_PIN_144_DPIR2__FUNC_EINT120 (MTK_PIN_NO(144) | 2) +#define MT8135_PIN_144_DPIR2__FUNC_CM2DAT_2X_6 (MTK_PIN_NO(144) | 4) + +#define MT8135_PIN_145_DPIR4__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define MT8135_PIN_145_DPIR4__FUNC_DPI0_R4 (MTK_PIN_NO(145) | 1) +#define MT8135_PIN_145_DPIR4__FUNC_EINT122 (MTK_PIN_NO(145) | 2) +#define MT8135_PIN_145_DPIR4__FUNC_CM2DAT_2X_8 (MTK_PIN_NO(145) | 4) + +#define MT8135_PIN_146_DPIR5__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define MT8135_PIN_146_DPIR5__FUNC_DPI0_R5 (MTK_PIN_NO(146) | 1) +#define MT8135_PIN_146_DPIR5__FUNC_EINT123 (MTK_PIN_NO(146) | 2) +#define MT8135_PIN_146_DPIR5__FUNC_CM2DAT_2X_9 (MTK_PIN_NO(146) | 4) + +#define MT8135_PIN_147_DPIR6__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define MT8135_PIN_147_DPIR6__FUNC_DPI0_R6 (MTK_PIN_NO(147) | 1) +#define MT8135_PIN_147_DPIR6__FUNC_EINT124 (MTK_PIN_NO(147) | 2) +#define MT8135_PIN_147_DPIR6__FUNC_CM2VSYNC_2X (MTK_PIN_NO(147) | 4) + +#define MT8135_PIN_148_DPIR7__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define MT8135_PIN_148_DPIR7__FUNC_DPI0_R7 (MTK_PIN_NO(148) | 1) +#define MT8135_PIN_148_DPIR7__FUNC_EINT125 (MTK_PIN_NO(148) | 2) +#define MT8135_PIN_148_DPIR7__FUNC_CM2HSYNC_2X (MTK_PIN_NO(148) | 4) + +#define MT8135_PIN_149_TDN3__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define MT8135_PIN_149_TDN3__FUNC_EINT36 (MTK_PIN_NO(149) | 2) + +#define MT8135_PIN_150_TDP3__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define MT8135_PIN_150_TDP3__FUNC_EINT35 (MTK_PIN_NO(150) | 2) + +#define MT8135_PIN_151_TDN2__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define MT8135_PIN_151_TDN2__FUNC_EINT169 (MTK_PIN_NO(151) | 2) + +#define MT8135_PIN_152_TDP2__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define MT8135_PIN_152_TDP2__FUNC_EINT168 (MTK_PIN_NO(152) | 2) + +#define MT8135_PIN_153_TCN__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define MT8135_PIN_153_TCN__FUNC_EINT163 (MTK_PIN_NO(153) | 2) + +#define MT8135_PIN_154_TCP__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define MT8135_PIN_154_TCP__FUNC_EINT162 (MTK_PIN_NO(154) | 2) + +#define MT8135_PIN_155_TDN1__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define MT8135_PIN_155_TDN1__FUNC_EINT167 (MTK_PIN_NO(155) | 2) + +#define MT8135_PIN_156_TDP1__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define MT8135_PIN_156_TDP1__FUNC_EINT166 (MTK_PIN_NO(156) | 2) + +#define MT8135_PIN_157_TDN0__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define MT8135_PIN_157_TDN0__FUNC_EINT165 (MTK_PIN_NO(157) | 2) + +#define MT8135_PIN_158_TDP0__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define MT8135_PIN_158_TDP0__FUNC_EINT164 (MTK_PIN_NO(158) | 2) + +#define MT8135_PIN_159_RDN3__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define MT8135_PIN_159_RDN3__FUNC_EINT18 (MTK_PIN_NO(159) | 2) + +#define MT8135_PIN_160_RDP3__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define MT8135_PIN_160_RDP3__FUNC_EINT30 (MTK_PIN_NO(160) | 2) + +#define MT8135_PIN_161_RDN2__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define MT8135_PIN_161_RDN2__FUNC_EINT31 (MTK_PIN_NO(161) | 2) + +#define MT8135_PIN_162_RDP2__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define MT8135_PIN_162_RDP2__FUNC_EINT32 (MTK_PIN_NO(162) | 2) + +#define MT8135_PIN_163_RCN__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define MT8135_PIN_163_RCN__FUNC_EINT33 (MTK_PIN_NO(163) | 2) + +#define MT8135_PIN_164_RCP__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define MT8135_PIN_164_RCP__FUNC_EINT39 (MTK_PIN_NO(164) | 2) + +#define MT8135_PIN_165_RDN1__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) + +#define MT8135_PIN_166_RDP1__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) + +#define MT8135_PIN_167_RDN0__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) + +#define MT8135_PIN_168_RDP0__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) + +#define MT8135_PIN_169_RDN1_A__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define MT8135_PIN_169_RDN1_A__FUNC_CMDAT6 (MTK_PIN_NO(169) | 1) +#define MT8135_PIN_169_RDN1_A__FUNC_EINT175 (MTK_PIN_NO(169) | 2) + +#define MT8135_PIN_170_RDP1_A__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define MT8135_PIN_170_RDP1_A__FUNC_CMDAT7 (MTK_PIN_NO(170) | 1) +#define MT8135_PIN_170_RDP1_A__FUNC_EINT174 (MTK_PIN_NO(170) | 2) + +#define MT8135_PIN_171_RCN_A__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define MT8135_PIN_171_RCN_A__FUNC_CMDAT8 (MTK_PIN_NO(171) | 1) +#define MT8135_PIN_171_RCN_A__FUNC_EINT171 (MTK_PIN_NO(171) | 2) + +#define MT8135_PIN_172_RCP_A__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define MT8135_PIN_172_RCP_A__FUNC_CMDAT9 (MTK_PIN_NO(172) | 1) +#define MT8135_PIN_172_RCP_A__FUNC_EINT170 (MTK_PIN_NO(172) | 2) + +#define MT8135_PIN_173_RDN0_A__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define MT8135_PIN_173_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(173) | 1) +#define MT8135_PIN_173_RDN0_A__FUNC_EINT173 (MTK_PIN_NO(173) | 2) + +#define MT8135_PIN_174_RDP0_A__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define MT8135_PIN_174_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(174) | 1) +#define MT8135_PIN_174_RDP0_A__FUNC_EINT172 (MTK_PIN_NO(174) | 2) + +#define MT8135_PIN_175_RDN1_B__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define MT8135_PIN_175_RDN1_B__FUNC_CMDAT2 (MTK_PIN_NO(175) | 1) +#define MT8135_PIN_175_RDN1_B__FUNC_EINT181 (MTK_PIN_NO(175) | 2) +#define MT8135_PIN_175_RDN1_B__FUNC_CMCSD2 (MTK_PIN_NO(175) | 3) + +#define MT8135_PIN_176_RDP1_B__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define MT8135_PIN_176_RDP1_B__FUNC_CMDAT3 (MTK_PIN_NO(176) | 1) +#define MT8135_PIN_176_RDP1_B__FUNC_EINT180 (MTK_PIN_NO(176) | 2) +#define MT8135_PIN_176_RDP1_B__FUNC_CMCSD3 (MTK_PIN_NO(176) | 3) + +#define MT8135_PIN_177_RCN_B__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define MT8135_PIN_177_RCN_B__FUNC_CMDAT4 (MTK_PIN_NO(177) | 1) +#define MT8135_PIN_177_RCN_B__FUNC_EINT177 (MTK_PIN_NO(177) | 2) + +#define MT8135_PIN_178_RCP_B__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define MT8135_PIN_178_RCP_B__FUNC_CMDAT5 (MTK_PIN_NO(178) | 1) +#define MT8135_PIN_178_RCP_B__FUNC_EINT176 (MTK_PIN_NO(178) | 2) + +#define MT8135_PIN_179_RDN0_B__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define MT8135_PIN_179_RDN0_B__FUNC_CMDAT0 (MTK_PIN_NO(179) | 1) +#define MT8135_PIN_179_RDN0_B__FUNC_EINT179 (MTK_PIN_NO(179) | 2) +#define MT8135_PIN_179_RDN0_B__FUNC_CMCSD0 (MTK_PIN_NO(179) | 3) + +#define MT8135_PIN_180_RDP0_B__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define MT8135_PIN_180_RDP0_B__FUNC_CMDAT1 (MTK_PIN_NO(180) | 1) +#define MT8135_PIN_180_RDP0_B__FUNC_EINT178 (MTK_PIN_NO(180) | 2) +#define MT8135_PIN_180_RDP0_B__FUNC_CMCSD1 (MTK_PIN_NO(180) | 3) + +#define MT8135_PIN_181_CMPCLK__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define MT8135_PIN_181_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(181) | 1) +#define MT8135_PIN_181_CMPCLK__FUNC_EINT182 (MTK_PIN_NO(181) | 2) +#define MT8135_PIN_181_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(181) | 3) +#define MT8135_PIN_181_CMPCLK__FUNC_CM2MCLK_4X (MTK_PIN_NO(181) | 4) +#define MT8135_PIN_181_CMPCLK__FUNC_TS_AUXADC_SEL_3 (MTK_PIN_NO(181) | 5) +#define MT8135_PIN_181_CMPCLK__FUNC_VENC_TEST_CK (MTK_PIN_NO(181) | 6) +#define MT8135_PIN_181_CMPCLK__FUNC_TESTA_OUT27 (MTK_PIN_NO(181) | 7) + +#define MT8135_PIN_182_CMMCLK__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define MT8135_PIN_182_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(182) | 1) +#define MT8135_PIN_182_CMMCLK__FUNC_EINT183 (MTK_PIN_NO(182) | 2) +#define MT8135_PIN_182_CMMCLK__FUNC_TS_AUXADC_SEL_2 (MTK_PIN_NO(182) | 5) +#define MT8135_PIN_182_CMMCLK__FUNC_TESTA_OUT28 (MTK_PIN_NO(182) | 7) + +#define MT8135_PIN_183_CMRST__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define MT8135_PIN_183_CMRST__FUNC_CMRST (MTK_PIN_NO(183) | 1) +#define MT8135_PIN_183_CMRST__FUNC_EINT185 (MTK_PIN_NO(183) | 2) +#define MT8135_PIN_183_CMRST__FUNC_TS_AUXADC_SEL_1 (MTK_PIN_NO(183) | 5) +#define MT8135_PIN_183_CMRST__FUNC_TESTA_OUT30 (MTK_PIN_NO(183) | 7) + +#define MT8135_PIN_184_CMPDN__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define MT8135_PIN_184_CMPDN__FUNC_CMPDN (MTK_PIN_NO(184) | 1) +#define MT8135_PIN_184_CMPDN__FUNC_EINT184 (MTK_PIN_NO(184) | 2) +#define MT8135_PIN_184_CMPDN__FUNC_TS_AUXADC_SEL_0 (MTK_PIN_NO(184) | 5) +#define MT8135_PIN_184_CMPDN__FUNC_TESTA_OUT29 (MTK_PIN_NO(184) | 7) + +#define MT8135_PIN_185_CMFLASH__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define MT8135_PIN_185_CMFLASH__FUNC_CMFLASH (MTK_PIN_NO(185) | 1) +#define MT8135_PIN_185_CMFLASH__FUNC_EINT186 (MTK_PIN_NO(185) | 2) +#define MT8135_PIN_185_CMFLASH__FUNC_CM2MCLK_3X (MTK_PIN_NO(185) | 3) +#define MT8135_PIN_185_CMFLASH__FUNC_MFG_TEST_CK_1 (MTK_PIN_NO(185) | 6) +#define MT8135_PIN_185_CMFLASH__FUNC_TESTA_OUT31 (MTK_PIN_NO(185) | 7) + +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_MRG_I2S_P_CLK (MTK_PIN_NO(186) | 1) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_EINT14 (MTK_PIN_NO(186) | 2) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(186) | 3) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_PCM0_CK (MTK_PIN_NO(186) | 4) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_DSP2_ICK (MTK_PIN_NO(186) | 5) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_IMG_TEST_CK (MTK_PIN_NO(186) | 6) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_USB_SCL (MTK_PIN_NO(186) | 7) + +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_MRG_I2S_SYNC (MTK_PIN_NO(187) | 1) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_EINT16 (MTK_PIN_NO(187) | 2) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_I2SIN_WS (MTK_PIN_NO(187) | 3) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_PCM0_WS (MTK_PIN_NO(187) | 4) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_DISP_TEST_CK (MTK_PIN_NO(187) | 6) + +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MRG_I2S_PCM_RX (MTK_PIN_NO(188) | 1) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_EINT15 (MTK_PIN_NO(188) | 2) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_I2SIN_DAT (MTK_PIN_NO(188) | 3) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_PCM0_DI (MTK_PIN_NO(188) | 4) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_DSP2_ID (MTK_PIN_NO(188) | 5) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MFG_TEST_CK (MTK_PIN_NO(188) | 6) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_USB_SDA (MTK_PIN_NO(188) | 7) + +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_MRG_I2S_PCM_TX (MTK_PIN_NO(189) | 1) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_EINT17 (MTK_PIN_NO(189) | 2) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_I2SOUT_DAT (MTK_PIN_NO(189) | 3) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_PCM0_DO (MTK_PIN_NO(189) | 4) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_VDEC_TEST_CK (MTK_PIN_NO(189) | 6) + +#define MT8135_PIN_190_SRCLKENAI__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define MT8135_PIN_190_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(190) | 1) + +#define MT8135_PIN_191_URXD3__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define MT8135_PIN_191_URXD3__FUNC_URXD3 (MTK_PIN_NO(191) | 1) +#define MT8135_PIN_191_URXD3__FUNC_EINT87 (MTK_PIN_NO(191) | 2) +#define MT8135_PIN_191_URXD3__FUNC_UTXD3 (MTK_PIN_NO(191) | 3) +#define MT8135_PIN_191_URXD3__FUNC_TS_AUX_ST (MTK_PIN_NO(191) | 5) +#define MT8135_PIN_191_URXD3__FUNC_PWM4 (MTK_PIN_NO(191) | 6) + +#define MT8135_PIN_192_UTXD3__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define MT8135_PIN_192_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(192) | 1) +#define MT8135_PIN_192_UTXD3__FUNC_EINT86 (MTK_PIN_NO(192) | 2) +#define MT8135_PIN_192_UTXD3__FUNC_URXD3 (MTK_PIN_NO(192) | 3) +#define MT8135_PIN_192_UTXD3__FUNC_TS_AUX_CS_B (MTK_PIN_NO(192) | 5) +#define MT8135_PIN_192_UTXD3__FUNC_PWM3 (MTK_PIN_NO(192) | 6) + +#define MT8135_PIN_193_SDA2__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define MT8135_PIN_193_SDA2__FUNC_SDA2 (MTK_PIN_NO(193) | 1) +#define MT8135_PIN_193_SDA2__FUNC_EINT95 (MTK_PIN_NO(193) | 2) +#define MT8135_PIN_193_SDA2__FUNC_CLKM5 (MTK_PIN_NO(193) | 3) +#define MT8135_PIN_193_SDA2__FUNC_PWM5 (MTK_PIN_NO(193) | 4) +#define MT8135_PIN_193_SDA2__FUNC_TS_AUX_PWDB (MTK_PIN_NO(193) | 5) + +#define MT8135_PIN_194_SCL2__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define MT8135_PIN_194_SCL2__FUNC_SCL2 (MTK_PIN_NO(194) | 1) +#define MT8135_PIN_194_SCL2__FUNC_EINT94 (MTK_PIN_NO(194) | 2) +#define MT8135_PIN_194_SCL2__FUNC_CLKM4 (MTK_PIN_NO(194) | 3) +#define MT8135_PIN_194_SCL2__FUNC_PWM4 (MTK_PIN_NO(194) | 4) +#define MT8135_PIN_194_SCL2__FUNC_TS_AUXADC_TEST_CK (MTK_PIN_NO(194) | 5) + +#define MT8135_PIN_195_SDA1__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define MT8135_PIN_195_SDA1__FUNC_SDA1 (MTK_PIN_NO(195) | 1) +#define MT8135_PIN_195_SDA1__FUNC_EINT93 (MTK_PIN_NO(195) | 2) +#define MT8135_PIN_195_SDA1__FUNC_CLKM3 (MTK_PIN_NO(195) | 3) +#define MT8135_PIN_195_SDA1__FUNC_PWM3 (MTK_PIN_NO(195) | 4) +#define MT8135_PIN_195_SDA1__FUNC_TS_AUX_SCLK_PWDB (MTK_PIN_NO(195) | 5) + +#define MT8135_PIN_196_SCL1__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define MT8135_PIN_196_SCL1__FUNC_SCL1 (MTK_PIN_NO(196) | 1) +#define MT8135_PIN_196_SCL1__FUNC_EINT92 (MTK_PIN_NO(196) | 2) +#define MT8135_PIN_196_SCL1__FUNC_CLKM2 (MTK_PIN_NO(196) | 3) +#define MT8135_PIN_196_SCL1__FUNC_PWM2 (MTK_PIN_NO(196) | 4) +#define MT8135_PIN_196_SCL1__FUNC_TS_AUX_DIN (MTK_PIN_NO(196) | 5) + +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(197) | 1) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_EINT71 (MTK_PIN_NO(197) | 2) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_SCL6 (MTK_PIN_NO(197) | 3) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_PWM5 (MTK_PIN_NO(197) | 4) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_CLKM4 (MTK_PIN_NO(197) | 5) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MFG_TEST_CK_2 (MTK_PIN_NO(197) | 6) + +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(198) | 1) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_EINT72 (MTK_PIN_NO(198) | 2) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_SDA6 (MTK_PIN_NO(198) | 3) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_PWM6 (MTK_PIN_NO(198) | 4) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_CLKM5 (MTK_PIN_NO(198) | 5) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MFG_TEST_CK_3 (MTK_PIN_NO(198) | 6) + +#define MT8135_PIN_199_MSDC3_CMD__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(199) | 1) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_EINT68 (MTK_PIN_NO(199) | 2) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_SDA2 (MTK_PIN_NO(199) | 3) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_PWM2 (MTK_PIN_NO(199) | 4) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_CLKM1 (MTK_PIN_NO(199) | 5) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_MFG_TEST_CK_4 (MTK_PIN_NO(199) | 6) + +#define MT8135_PIN_200_MSDC3_CLK__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(200) | 1) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_EINT67 (MTK_PIN_NO(200) | 2) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_SCL2 (MTK_PIN_NO(200) | 3) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_PWM1 (MTK_PIN_NO(200) | 4) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_CLKM0 (MTK_PIN_NO(200) | 5) + +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(201) | 1) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_EINT70 (MTK_PIN_NO(201) | 2) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_SDA3 (MTK_PIN_NO(201) | 3) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_PWM4 (MTK_PIN_NO(201) | 4) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_CLKM3 (MTK_PIN_NO(201) | 5) + +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(202) | 1) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_EINT69 (MTK_PIN_NO(202) | 2) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_SCL3 (MTK_PIN_NO(202) | 3) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_PWM3 (MTK_PIN_NO(202) | 4) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_CLKM2 (MTK_PIN_NO(202) | 5) + +#endif /* __DTS_MT8135_PINFUNC_H */ diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi index a161e99..a069afd 100644 --- a/arch/arm/boot/dts/mt8135.dtsi +++ b/arch/arm/boot/dts/mt8135.dtsi @@ -15,6 +15,7 @@ #include #include #include "skeleton64.dtsi" +#include "mt8135-pinfunc.h" / { compatible = "mediatek,mt8135"; @@ -101,6 +102,30 @@ compatible = "simple-bus"; ranges; + syscfg_pctl_a: syscfg_pctl_a@10005000 { + compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + syscfg_pctl_b: syscfg_pctl_b@1020C000 { + compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; + reg = <0 0x1020C000 0 0x1000>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8135-pinctrl"; + reg = <0 0x1000B000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + ; + }; + timer: timer@10008000 { compatible = "mediatek,mt8135-timer", "mediatek,mt6577-timer"; -- cgit v0.10.2 From a104662052b5863663d11895667f0f8a755cd826 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 27 Feb 2015 18:48:38 +0100 Subject: ARM: shmobile: ape6evm dts: Enable pull-up for GPIO switches The switches on r8a73a4/ape6evm do not have pull-up registers. The schematics say: "Need to use APE6 internal PullUp", hence enable pull-up using pinctrl. Without this, the switches don't really work, as the GPIO inputs are more likely to pick up ghost signals through capacitive coupling than actual keypresses. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index e8f3f38..9734dd7 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -123,6 +123,9 @@ keyboard { compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&keyboard_pins>; + zero-key { gpios = <&pfc 324 GPIO_ACTIVE_LOW>; linux,code = ; @@ -208,6 +211,12 @@ renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; renesas,function = "sdhi1"; }; + + keyboard_pins: keyboard { + renesas,pins = "PORT324", "PORT325", "PORT326", "PORT327", + "PORT328", "PORT329"; + bias-pull-up; + }; }; &mmcif0 { -- cgit v0.10.2 From 90ca409a1e6b9b72d1b6ae716cd7a63335fd0e87 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 27 Feb 2015 18:48:39 +0100 Subject: ARM: shmobile: ape6evm dts: Configure the custom switch as wake-up source Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index 9734dd7..d1b6a07 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -130,6 +130,7 @@ gpios = <&pfc 324 GPIO_ACTIVE_LOW>; linux,code = ; label = "S16"; + gpio-key,wakeup; }; menu-key { -- cgit v0.10.2 From 4076b521cb50c411467c4ba65f82ef0079823357 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 18 Feb 2015 12:25:42 +0100 Subject: ARM: BCM5301X: Add DT for Netgear R8000 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: RafaÅ‚ MiÅ‚ecki Reported-by: Ian Kent Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 2604d7c..c6e0a4c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -59,7 +59,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4708-netgear-r6300-v2.dtb \ bcm47081-asus-rt-n18u.dtb \ bcm47081-buffalo-wzr-600dhp2.dtb \ - bcm47081-buffalo-wzr-900dhp.dtb + bcm47081-buffalo-wzr-900dhp.dtb \ + bcm4709-netgear-r8000.dtb dtb-$(CONFIG_ARCH_BCM_63XX) += \ bcm963138dvt.dtb dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts new file mode 100644 index 0000000..ea26dd3 --- /dev/null +++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts @@ -0,0 +1,77 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Netgear R8000 + * + * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" + +/ { + compatible = "netgear,r8000", "brcm,bcm4709", "brcm,bcm4708"; + model = "Netgear R8000 (BCM4709)"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + power0 { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + power1 { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + 5ghz-1 { + label = "bcm53xx:white:5ghz-1"; + gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + 2ghz { + label = "bcm53xx:white:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + }; + }; +}; -- cgit v0.10.2 From 7875b470c9d80dff2d58ae9692adb3a2b5814a89 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 20 Feb 2015 11:22:05 +0100 Subject: ARM: BCM5301X: Fix default state of power LEDs on Netgear R6250 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We want green LED to be enabled by default. Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts index f18c9d9..2ed9e57 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts @@ -45,13 +45,13 @@ power0 { label = "bcm53xx:green:power"; gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; + linux,default-trigger = "default-on"; }; power1 { label = "bcm53xx:amber:power"; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; + linux,default-trigger = "default-off"; }; usb { -- cgit v0.10.2 From 776920e16a74b0009765d84b6c267fe820966307 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 7 Mar 2015 15:14:59 +0100 Subject: ARM: dts: rockchip: add input supplies for the act8846 on Radxa Rock On the Radxa Rock board most supplies come from the static 5v vsys supply, but the inl1-supply comes from the REG4 of the act8846 itself. Model this dependency using the added supply-handling to make sure the supplying regulator gets handled correctly and not accidentially turned off. Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 9a09579..bdf8570 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -103,6 +103,14 @@ regulator-always-on; regulator-boot-on; }; + + vsys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; }; &emac { @@ -148,6 +156,14 @@ pinctrl-names = "default"; pinctrl-0 = <&act8846_dvs0_ctl>; + vp1-supply = <&vsys>; + vp2-supply = <&vsys>; + vp3-supply = <&vsys>; + vp4-supply = <&vsys>; + inl1-supply = <&vcc_io>; + inl2-supply = <&vsys>; + inl3-supply = <&vsys>; + regulators { vcc_ddr: REG1 { regulator-name = "VCC_DDR"; -- cgit v0.10.2 From e6a4e5d50b3eea42220e50d64006fe5baacf654c Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Mon, 9 Mar 2015 13:44:58 -0700 Subject: ARM: dts: enable IOMUX for Broadcom Cygnus This enables the IOMUX support for Broadcom Cygnus SoC Signed-off-by: Ray Jui Tested-by: Dmitry Torokhov Acked-by: Linus Walleij Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index ff5fb6a..1cbae6a 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -54,6 +54,12 @@ /include/ "bcm-cygnus-clock.dtsi" + pinctrl: pinctrl@0x0301d0c8 { + compatible = "brcm,cygnus-pinmux"; + reg = <0x0301d0c8 0x30>, + <0x0301d24c 0x2c>; + }; + amba { #address-cells = <1>; #size-cells = <1>; -- cgit v0.10.2 From 5fa4b29c71b204b7258a8130020d574e033f4015 Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Mon, 9 Mar 2015 13:45:01 -0700 Subject: ARM: dts: enable GPIO for Broadcom Cygnus This enables all 3 GPIO controllers including the ASIU GPIO, the chipcommonG GPIO, and the ALWAYS-ON GPIO, for Broadcom Cygnus SoC Signed-off-by: Ray Jui Reviewed-by: Scott Branden Tested-by: Dmitry Torokhov Acked-by: Linus Walleij Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 1cbae6a..63b7fed 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -60,6 +60,36 @@ <0x0301d24c 0x2c>; }; + gpio_crmu: gpio@03024800 { + compatible = "brcm,cygnus-crmu-gpio"; + reg = <0x03024800 0x50>, + <0x03024008 0x18>; + #gpio-cells = <2>; + gpio-controller; + }; + + gpio_ccm: gpio@1800a000 { + compatible = "brcm,cygnus-ccm-gpio"; + reg = <0x1800a000 0x50>, + <0x0301d164 0x20>; + #gpio-cells = <2>; + gpio-controller; + interrupts = ; + interrupt-controller; + }; + + gpio_asiu: gpio@180a5000 { + compatible = "brcm,cygnus-asiu-gpio"; + reg = <0x180a5000 0x668>; + #gpio-cells = <2>; + gpio-controller; + + pinmux = <&pinctrl>; + + interrupt-controller; + interrupts = ; + }; + amba { #address-cells = <1>; #size-cells = <1>; -- cgit v0.10.2 From 90c6e608e737e387e88aa789c7b4e1f6dfdc4822 Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Mon, 9 Mar 2015 13:45:02 -0700 Subject: ARM: dts: cygnus: enable GPIO based hook detection This enables GPIO based phone hook detection for Broadcom BCM911360 phone factor board (bcm911360_entphn) Signed-off-by: Ray Jui Acked-by: Linus Walleij Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts index d2ee952..7db4843 100644 --- a/arch/arm/boot/dts/bcm911360_entphn.dts +++ b/arch/arm/boot/dts/bcm911360_entphn.dts @@ -33,6 +33,7 @@ /dts-v1/; #include "bcm-cygnus.dtsi" +#include "dt-bindings/input/input.h" / { model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)"; @@ -50,4 +51,16 @@ uart3: serial@18023000 { status = "okay"; }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + hook { + label = "HOOK"; + linux,code = ; + gpios = <&gpio_asiu 48 0>; + }; + }; }; -- cgit v0.10.2 From 46a158f2ce965940f68ccb07ac8127e1091bebe8 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 10 Mar 2015 01:39:01 +0000 Subject: ARM: shmobile: r8a7790: add reg-names for sound Rensas R-Car sound driver supports reg-names. Let's use it. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index b320252..2041ec7 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1461,6 +1461,8 @@ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ <0 0xec541000 0 0x1280>; /* SSI */ + reg-names = "scu", "adg", "ssiu", "ssi"; + clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>, <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>, -- cgit v0.10.2 From d88a6a2a2184b0f58c42dfda77fdda87ab28b6aa Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 10 Mar 2015 01:39:18 +0000 Subject: ARM: shmobile: r8a7791: add reg-names for sound Rensas R-Car sound driver supports reg-names. Let's use it. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index e899f79..8631e02 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1504,6 +1504,8 @@ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ <0 0xec541000 0 0x1280>; /* SSI */ + reg-names = "scu", "adg", "ssiu", "ssi"; + clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>, <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>, -- cgit v0.10.2 From 0c60267702244b8a6e62743a8e13a07823efbf6d Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 10 Mar 2015 01:39:39 +0000 Subject: ARM: shmobile: r8a7790: enable Audio DMAC peri peri via sound driver Audio DMAC peri peri is no longer DMAEngine. it is supported by sound driver. this patch enable it. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 2041ec7..48d11e0e 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -370,13 +370,6 @@ dma-channels = <13>; }; - audmapp: dma-controller@ec740000 { - compatible = "renesas,rcar-audmapp"; - #dma-cells = <1>; - - reg = <0 0xec740000 0 0x200>; - }; - i2c0: i2c@e6508000 { #address-cells = <1>; #size-cells = <0>; @@ -1460,8 +1453,9 @@ reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x1280>; /* SSI */ - reg-names = "scu", "adg", "ssiu", "ssi"; + <0 0xec541000 0 0x1280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>, -- cgit v0.10.2 From d73a5013ed61bc605374f72ce879a358feba7f3e Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 10 Mar 2015 01:39:55 +0000 Subject: ARM: shmobile: r8a7791: enable Audio DMAC peri peri via sound driver Audio DMAC peri peri is no longer DMAEngine. it is supported by sound driver. this patch enable it. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 8631e02..a697b94 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -357,13 +357,6 @@ dma-channels = <13>; }; - audmapp: dma-controller@ec740000 { - compatible = "renesas,rcar-audmapp"; - #dma-cells = <1>; - - reg = <0 0xec740000 0 0x200>; - }; - /* The memory map in the User's Manual maps the cores to bus numbers */ i2c0: i2c@e6508000 { #address-cells = <1>; @@ -1503,8 +1496,9 @@ reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x1280>; /* SSI */ - reg-names = "scu", "adg", "ssiu", "ssi"; + <0 0xec541000 0 0x1280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>, -- cgit v0.10.2 From 118a509374f7791feee309946abccf2ce5609f16 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 10 Mar 2015 01:40:13 +0000 Subject: ARM: shmobile: r8a7790: sound enables Audio DMAC entry on DTSI This patch adds Audio DMAC (= rcar-dmac) entry for sound Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 48d11e0e..4bb2f4c 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1481,34 +1481,120 @@ status = "disabled"; rcar_sound,dvc { - dvc0: dvc@0 { }; - dvc1: dvc@1 { }; + dvc0: dvc@0 { + dmas = <&audma0 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc@1 { + dmas = <&audma0 0xbe>; + dma-names = "tx"; + }; }; rcar_sound,src { - src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; }; - src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; }; - src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; }; - src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; }; - src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; }; - src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; }; - src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; }; - src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; }; - src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; }; - src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; }; + src0: src@0 { + interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src@1 { + interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src@2 { + interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src@3 { + interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src@4 { + interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src@5 { + interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src@6 { + interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src@7 { + interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src@8 { + interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src@9 { + interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; }; rcar_sound,ssi { - ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; }; - ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; }; - ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; }; - ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; }; - ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; }; - ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; }; - ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; }; - ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; }; - ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; }; - ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; }; + ssi0: ssi@0 { + interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi@1 { + interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi@2 { + interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi@3 { + interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi@4 { + interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi@5 { + interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi@6 { + interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi@7 { + interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi@8 { + interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi@9 { + interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; }; }; -- cgit v0.10.2 From 63573339e7698503bfeaef3bb0c444ffc98e45a0 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 10 Mar 2015 01:40:27 +0000 Subject: ARM: shmobile: r8a7791: sound enables Audio DMAC entry on DTSI This patch adds Audio DMAC (= rcar-dmac) entry for sound Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index a697b94..4696062 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1524,34 +1524,120 @@ status = "disabled"; rcar_sound,dvc { - dvc0: dvc@0 { }; - dvc1: dvc@1 { }; + dvc0: dvc@0 { + dmas = <&audma0 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc@1 { + dmas = <&audma0 0xbe>; + dma-names = "tx"; + }; }; rcar_sound,src { - src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; }; - src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; }; - src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; }; - src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; }; - src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; }; - src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; }; - src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; }; - src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; }; - src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; }; - src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; }; + src0: src@0 { + interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src@1 { + interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src@2 { + interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src@3 { + interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src@4 { + interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src@5 { + interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src@6 { + interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src@7 { + interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src@8 { + interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src@9 { + interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; }; rcar_sound,ssi { - ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; }; - ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; }; - ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; }; - ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; }; - ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; }; - ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; }; - ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; }; - ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; }; - ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; }; - ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; }; + ssi0: ssi@0 { + interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi@1 { + interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi@2 { + interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi@3 { + interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi@4 { + interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi@5 { + interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi@6 { + interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi@7 { + interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi@8 { + interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi@9 { + interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; }; }; }; -- cgit v0.10.2 From 0c2d652f0bd9fdfe367eca4ebf56ad354bf3b153 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Sun, 1 Mar 2015 21:51:40 +0100 Subject: ARM: Kirkwood: add DT description for nas2big This patch adds the DT description for the LaCie "2Big NAS" (nas2big). This NAS is an hardware upgrade of the 2Big Network v2. Chipset and device list: - CPU Marvell 88F6282 1600Mhz - SDRAM memory, 256MB DDR3 (2x128MB x8) 533Mhz - 1 Ethernet Gigabit port (PHY Marvell 88E1518) - Flash memory, NAND 256MB TSOP48 - I2C EEPROM, 512 bytes (AT24 type) - PCIe SATA controller JMicron JMB360 (eSATA) - I2C fan controller GMT G762 (with a separate alarm GPIO) - 1 USB2 host port - 1 push button - 1 power switch - 2 SATA LEDs (bi-color, blue and red) - 1 power LED (bi-color, blue and red) - CPLD for LEDs and start-up management (Altera Max EMP3064) Signed-off-by: Simon Guinot Acked-by: Andrew Lunn Signed-off-by: Gregory CLEMENT diff --git a/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt b/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt index 925ecbf..4f40ff3 100644 --- a/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt +++ b/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt @@ -42,6 +42,7 @@ board. Currently known boards are: "lacie,cloudbox" "lacie,inetspace_v2" "lacie,laplug" +"lacie,nas2big" "lacie,netspace_lite_v2" "lacie,netspace_max_v2" "lacie,netspace_mini_v2" diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b9c3f8c..b2e51fe 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -165,6 +165,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-lsxhl.dtb \ kirkwood-mplcec4.dtb \ kirkwood-mv88f6281gtw-ge.dtb \ + kirkwood-nas2big.dtb \ kirkwood-net2big.dtb \ kirkwood-net5big.dtb \ kirkwood-netgear_readynas_duo_v2.dtb \ diff --git a/arch/arm/boot/dts/kirkwood-nas2big.dts b/arch/arm/boot/dts/kirkwood-nas2big.dts new file mode 100644 index 0000000..7427ec5 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-nas2big.dts @@ -0,0 +1,143 @@ +/* + * Device Tree file for LaCie 2Big NAS + * + * Copyright (C) 2015 Seagate + * + * Author: Simon Guinot + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +/dts-v1/; + +#include "kirkwood-netxbig.dtsi" + +/ { + model = "LaCie 2Big NAS"; + compatible = "lacie,nas2big", "lacie,netxbig", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + mbus { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + rtc@10300 { + /* The on-chip RTC is not powered (no supercap). */ + status = "disabled"; + }; + spi@10600 { + /* + * A NAND flash is used instead of an SPI flash for + * the other netxbig-compatible boards. + */ + status = "disabled"; + }; + }; + + fan { + /* + * An I2C fan controller (GMT G762) is used but alarm is + * wired to a separate GPIO. + */ + compatible = "gpio-fan"; + alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; + + regulators: regulators { + status = "okay"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; + }; + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; + + /* + * An external I2C RTC (Dallas DS1337S+) is used. This allows + * to power-up the board on an RTC alarm. The external RTC can + * be kept powered, even when the SoC is off. + */ + rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + interrupts = <43>; + }; + g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; + }; +}; + +&nand { + chip-delay = <50>; + status = "okay"; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x1000000>; + }; + + partition@1100000 { + label = "root"; + reg = <0x1100000 0x8000000>; + }; + + partition@9100000 { + label = "unused"; + reg = <0x9100000 0x6f00000>; + }; +}; -- cgit v0.10.2 From 91d5cb737287642b75e47790a28a43cd0efd80cb Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 7 Mar 2015 23:18:12 +0100 Subject: ARM: dts: rockchip: complete rk3288-evb pmic supplies This adds the static vcc_sys regulator to the rk3288-evb, the missing rk808 supplies from it and all the supplies of the act8846 evb-variant. Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts index d7b8bbc..1687e83 100644 --- a/arch/arm/boot/dts/rk3288-evb-act8846.dts +++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts @@ -33,6 +33,7 @@ regulator-max-microvolt = <1350000>; regulator-always-on; regulator-boot-on; + vin-supply = <&vcc_sys>; }; vdd_gpu: syr828@41 { @@ -43,6 +44,7 @@ regulator-min-microvolt = <850000>; regulator-max-microvolt = <1350000>; regulator-always-on; + vin-supply = <&vcc_sys>; }; hym8563@51 { @@ -64,6 +66,14 @@ reg = <0x5a>; status = "okay"; + vp1-supply = <&vcc_sys>; + vp2-supply = <&vcc_sys>; + vp3-supply = <&vcc_sys>; + vp4-supply = <&vcc_sys>; + inl1-supply = <&vcc_io>; + inl2-supply = <&vcc_sys>; + inl3-supply = <&vcc_20>; + regulators { vcc_ddr: REG1 { regulator-name = "VCC_DDR"; diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts index a1c294b..f62ea78 100644 --- a/arch/arm/boot/dts/rk3288-evb-rk808.dts +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts @@ -43,9 +43,16 @@ #clock-cells = <1>; clock-output-names = "xin32k", "rk808-clkout2"; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; vcc8-supply = <&vcc_18>; vcc9-supply = <&vcc_io>; vcc10-supply = <&vcc_io>; + vcc11-supply = <&vcc_sys>; vcc12-supply = <&vcc_io>; vddio-supply = <&vccio_pmu>; diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 287a162..4a45751 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -103,6 +103,15 @@ regulator-always-on; regulator-boot-on; }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; }; &emmc { -- cgit v0.10.2 From cd590b50a9367b52520f6866b27f72317bb1a07e Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Wed, 11 Mar 2015 11:06:09 -0700 Subject: ARM: dts: enable PCIe support for Cygnus Add PCIe device nodes in bcm-cygnus.dtsi but keep them disabled there. Only enable them for bcm958300k where PCIe interfaces are populated Signed-off-by: Ray Jui Reviewed-by: Scott Branden Acked-by: Arnd Bergmann Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 63b7fed..7b52c33 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -126,6 +126,48 @@ status = "disabled"; }; + pcie0: pcie@18012000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18012000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; + + linux,pci-domain = <0>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x28000000 0 0x00010000 + 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; + + status = "disabled"; + }; + + pcie1: pcie@18013000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18013000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; + + linux,pci-domain = <1>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x48000000 0 0x00010000 + 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; + + status = "disabled"; + }; + uart0: serial@18020000 { compatible = "snps,dw-apb-uart"; reg = <0x18020000 0x100>; diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts index f1bb36f..c9eb856 100644 --- a/arch/arm/boot/dts/bcm958300k.dts +++ b/arch/arm/boot/dts/bcm958300k.dts @@ -47,6 +47,14 @@ bootargs = "console=ttyS0,115200"; }; + pcie0: pcie@18012000 { + status = "okay"; + }; + + pcie1: pcie@18013000 { + status = "okay"; + }; + uart3: serial@18023000 { status = "okay"; }; -- cgit v0.10.2 From 841990b6b3e2cfc0b51a5efb4c2fed6693cfafee Mon Sep 17 00:00:00 2001 From: Tsahee Zidenberg Date: Thu, 12 Mar 2015 13:53:12 +0200 Subject: ARM: dts: Alpine platform devicetree This patch introduces devicetree for the Alpine platform, and for a development board based on the same platform. Signed-off-by: Barak Wasserstrom Signed-off-by: Tsahee Zidenberg Acked-by: Arnd Bergmann Signed-off-by: Arnd Bergmann diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 491a3c1..4e1b387 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1,5 +1,7 @@ ifeq ($(CONFIG_OF),y) +dtb-$(CONFIG_ARCH_ALPINE) += \ + alpine_db.dtb dtb-$(CONFIG_MACH_ASM9260) += \ alphascale-asm9260-devkit.dtb # Keep at91 dtb files sorted alphabetically for each SoC diff --git a/arch/arm/boot/dts/alpine-db.dts b/arch/arm/boot/dts/alpine-db.dts new file mode 100644 index 0000000..dfb5a08 --- /dev/null +++ b/arch/arm/boot/dts/alpine-db.dts @@ -0,0 +1,35 @@ +/* + * Copyright 2015 Annapurna Labs Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * Alternatively, redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "alpine.dtsi" + +/ { + model = "Annapurna Labs Alpine Dev Board"; + /* no need for anything outside SOC */ +}; + diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi new file mode 100644 index 0000000..519f58c --- /dev/null +++ b/arch/arm/boot/dts/alpine.dtsi @@ -0,0 +1,141 @@ +/* + * Copyright 2015 Annapurna Labs Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * Alternatively, redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include "skeleton64.dtsi" + +/ { + /* SOC compatibility */ + compatible = "al,alpine"; + + /* CPU Configuration */ + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "al,alpine-smp"; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + clock-frequency = <0>; /* Filled by loader */ + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + clock-frequency = <0>; /* Filled by loader */ + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + clock-frequency = <0>; /* Filled by loader */ + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + clock-frequency = <0>; /* Filled by loader */ + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + arch-timer { + compatible = "arm,cortex-a15-timer", + "arm,armv7-timer"; + interrupts = + , + , + , + ; + clock-frequency = <0>; /* Filled by loader */ + }; + + /* Interrupt Controller */ + gic: gic@fb001000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfb001000 0x0 0x1000>, + <0x0 0xfb002000 0x0 0x2000>, + <0x0 0xfb004000 0x0 0x1000>, + <0x0 0xfb006000 0x0 0x2000>; + interrupts = + ; + }; + + /* CPU Resume registers */ + cpu-resume@fbff5ec0 { + compatible = "al,alpine-cpu-resume"; + reg = <0x0 0xfbff5ec0 0x0 0x30>; + }; + + /* North Bridge Service Registers */ + sysfabric-service@fb070000 { + compatible = "al,alpine-sysfabric-service", "syscon"; + reg = <0x0 0xfb070000 0x0 0x10000>; + }; + + /* Performance Monitor Unit */ + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = , + , + , + ; + }; + + uart0:uart@fd883000 { + compatible = "ns16550a"; + reg = <0x0 0xfd883000 0x0 0x1000>; + clock-frequency = <0>; /* Filled by loader */ + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart1:uart@0xfd884000 { + compatible = "ns16550a"; + reg = <0x0 0xfd884000 0x0 0x1000>; + clock-frequency = <0>; /* Filled by loader */ + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + }; +}; -- cgit v0.10.2 From 1b3a62ae9c06aa015397984eaa0be531fc6675eb Mon Sep 17 00:00:00 2001 From: Rostislav Lisovy Date: Mon, 9 Feb 2015 15:48:03 +0100 Subject: ARM: dts: Add vendor prefix for Grinn Grinn is a company located in Poland, Europe producing System on Modules. Webpage: http://www.grinn-global.com/ Signed-off-by: Rostislav Lisovy Signed-off-by: Tony Lindgren diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 389ca13..f6a9f25 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -77,6 +77,7 @@ giantplus Giantplus Technology Co., Ltd. globalscale Globalscale Technologies, Inc. gmt Global Mixed-mode Technology, Inc. google Google, Inc. +grinn Grinn gumstix Gumstix, Inc. gw Gateworks Corporation hannstar HannStar Display Corporation -- cgit v0.10.2 From 11d938d494890f09cf22252615cd2d0f2332f429 Mon Sep 17 00:00:00 2001 From: Rostislav Lisovy Date: Mon, 9 Feb 2015 15:48:04 +0100 Subject: ARM: dts: am335x: Add DTS for ChiliSOM module Since this is a SOM (System on Module) that will be part of another embedded board (and can't really exist on its own) define it as a "dtsi" that will be included in the Device tree describing the whole system later on. Hardware specification: * AM335x SoC * up to 512 MB RAM * NAND Flash (8x interface, cs0) * UART0 * PMIC * I2C0 (for PMIC) * 1x Ethernet MAC Signed-off-by: Rostislav Lisovy [tony@atomide.com: updated nand io size to be just 4] Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/am335x-chilisom.dtsi new file mode 100644 index 0000000..7e9a34d --- /dev/null +++ b/arch/arm/boot/dts/am335x-chilisom.dtsi @@ -0,0 +1,239 @@ +/* + * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ + * Author: Rostislav Lisovy + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "am33xx.dtsi" + +/ { + model = "Grinn AM335x ChiliSOM"; + compatible = "grinn,am335x-chilisom", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ + 0x110 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + 0x13c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + 0x140 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* mdio_data.mdio_data */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) + /* mdio_clk.mdio_clk */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + nandflash_pins: nandflash_pins { + pinctrl-single,pins = < + 0x00 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + 0x04 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + 0x08 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + 0x0c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + + 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + 0x7c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + 0x90 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + 0x9c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + +}; + +/include/ "tps65217.dtsi" + +&tps { + regulators { + dcdc1_reg: regulator@0 { + regulator-name = "vdds_dpr"; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-name = "vio,vrtc,vdds"; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-name = "vdd_3v3aux"; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-name = "vdd_1v8"; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-name = "vdd_3v3d"; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +/* Ethernet MAC */ +&mac { + slaves = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +/* NAND Flash */ +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins>; + ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */ + nand@0,0 { + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + }; +}; -- cgit v0.10.2 From 5b5e49af054a315bda68fec3eb935637aa72be31 Mon Sep 17 00:00:00 2001 From: Rostislav Lisovy Date: Mon, 9 Feb 2015 15:48:05 +0100 Subject: ARM: dts: am335x: Add Chiliboard DTS Chiliboard uses ChiliSOM as its base. Hardware specification: * ChiliSOM (am335x, PMIC, DRAM, NAND) * Ethernet PHY (id 0) * USB host (usb1) * microSD slot * 2x GPIO LED Signed-off-by: Rostislav Lisovy Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a1c776b..b316b38 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -401,7 +401,8 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-evmsk.dtb \ am335x-nano.dtb \ am335x-pepper.dtb \ - am335x-lxm.dtb + am335x-lxm.dtb \ + am335x-chiliboard.dtb dtb-$(CONFIG_ARCH_OMAP4) += \ omap4-duovero-parlor.dtb \ omap4-panda.dtb \ diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts new file mode 100644 index 0000000..310da20 --- /dev/null +++ b/arch/arm/boot/dts/am335x-chiliboard.dts @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ + * Author: Rostislav Lisovy + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; +#include "am335x-chilisom.dtsi" + +/ { + model = "AM335x Chiliboard"; + compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom", + "ti,am33xx"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_gpio_pins>; + + led0 { + label = "led0"; + gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "heartbeat"; + }; + + led1 { + label = "led1"; + gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; +}; + +&am33xx_pinmux { + usb1_drvvbus: usb1_drvvbus { + pinctrl-single,pins = < + 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ + >; + }; + + sd_pins: pinmux_sd_card { + pinctrl-single,pins = < + 0xf0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + 0xf4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + 0xf8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + 0xfc (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + led_gpio_pins: led_gpio_pins { + pinctrl-single,pins = < + 0x1e4 (PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */ + 0x1e8 (PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */ + >; + }; +}; + +&ldo4_reg { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +/* Ethernet */ +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rmii"; +}; + +&phy_sel { + rmii-clock-ext; +}; + +/* USB */ +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_drvvbus>; + + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +/* microSD */ +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&sd_pins>; + vmmc-supply = <&ldo4_reg>; + bus-width = <0x4>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; -- cgit v0.10.2 From 49d094570c59ba9e60efacd5b08a248ab9f6d59a Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Thu, 19 Feb 2015 13:57:38 -0600 Subject: ARM: dts: am437x-idk: enable i2c2 i2c2 goes to an expansion connector which we want to use. Signed-off-by: Felipe Balbi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index 0198f5a..37834427 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -133,6 +133,20 @@ >; }; + i2c2_pins_default: i2c2_pins_default { + pinctrl-single,pins = < + 0x1e8 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */ + 0x1ec (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */ + >; + }; + + i2c2_pins_sleep: i2c2_pins_sleep { + pinctrl-single,pins = < + 0x1e8 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x1ec (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + mmc1_pins_default: pinmux_mmc1_pins_default { pinctrl-single,pins = < 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ @@ -263,6 +277,14 @@ }; }; +&i2c2 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_default>; + pinctrl-1 = <&i2c2_pins_sleep>; + clock-frequency = <100000>; +}; + &epwmss0 { status = "okay"; }; -- cgit v0.10.2 From 5c8a521d447682037221535bd898a9d182d25c7d Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Thu, 26 Feb 2015 10:38:45 -0500 Subject: Documentation: DT: omap_serial: document missing properties and add an example The omap_serial.txt binding documentation lacks a number of properties that are used in DTS files for platforms incorporating this peripheral. Fix this by documenting the missing required and optional fields and add an example. Signed-off-by: Matt Porter Signed-off-by: Tony Lindgren diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt index 342eedd..54c2a15 100644 --- a/Documentation/devicetree/bindings/serial/omap_serial.txt +++ b/Documentation/devicetree/bindings/serial/omap_serial.txt @@ -4,7 +4,27 @@ Required properties: - compatible : should be "ti,omap2-uart" for OMAP2 controllers - compatible : should be "ti,omap3-uart" for OMAP3 controllers - compatible : should be "ti,omap4-uart" for OMAP4 controllers +- reg : address and length of the register space +- interrupts or interrupts-extended : Should contain the uart interrupt + specifier or both the interrupt + controller phandle and interrupt + specifier. - ti,hwmods : Must be "uart", n being the instance number (1-based) Optional properties: - clock-frequency : frequency of the clock input to the UART +- dmas : DMA specifier, consisting of a phandle to the DMA controller + node and a DMA channel number. +- dma-names : "rx" for receive channel, "tx" for transmit channel. + +Example: + + uart4: serial@49042000 { + compatible = "ti,omap3-uart"; + reg = <0x49042000 0x400>; + interrupts = <80>; + dmas = <&sdma 81 &sdma 82>; + dma-names = "tx", "rx"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; -- cgit v0.10.2 From a7390ebe457ec5a90ce7da9ae652ebdbda94b926 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 26 Feb 2015 15:39:23 +0200 Subject: ARM: dts: dra7xx-clocks: Add gate clock for CLKOUT2 To be able to control the gate for the clkout2 clock output. Signed-off-by: Peter Ujfalusi Signed-off-by: Jyri Sarha Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 4bdcbd6..2a9994f 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1421,6 +1421,14 @@ ti,dividers = <1>, <8>; }; + clkout2_clk: clkout2_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkoutmux2_clk_mux>; + ti,bit-shift = <8>; + reg = <0x06b0>; + }; + l3init_960m_gfclk: l3init_960m_gfclk { #clock-cells = <0>; compatible = "ti,gate-clock"; -- cgit v0.10.2 From 771048f59d068f0baf22fef7f952e8d4cca158af Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Fri, 27 Feb 2015 22:26:37 +0100 Subject: ARM: dts: omap3-pandora: add common device tree This device tree allows to boot, supports the panel, framebuffer, touch screen, as well as some more peripherals. Since there is a OMAP3530 based 600 MHz variant and a DM3730 based 1 GHz variant we must include this common device tree code in one of two CPU specific device trees. Signed-off-by: H. Nikolaus Schaller Signed-off-by: Marek Belisko Tested-by: Grazvydas Ignotas Reviewed-by: Grazvydas Ignotas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi new file mode 100644 index 0000000..782ab1f --- /dev/null +++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi @@ -0,0 +1,640 @@ +/* + * Copyright (C) 2015 + * Nikolaus Schaller + * + * Common device tree include for OpenPandora devices. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +/ { + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + aliases { + display0 = &lcd; + }; + + tv: connector@1 { + compatible = "connector-analog-tv"; + label = "tv"; + + port { + tv_connector_in: endpoint { + remote-endpoint = <&venc_out>; + }; + }; + }; + + gpio-leds { + + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led@1 { + label = "pandora::sd1"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* GPIO_128 */ + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@2 { + label = "pandora::sd2"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* GPIO_129 */ + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led@3 { + label = "pandora::bluetooth"; + gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; /* GPIO_158 */ + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led@4 { + label = "pandora::wifi"; + gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; /* GPIO_159 */ + linux,default-trigger = "mmc2"; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + + up-button { + label = "up"; + linux,code = ; + gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* GPIO_110 */ + gpio-key,wakeup; + }; + + down-button { + label = "down"; + linux,code = ; + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* GPIO_103 */ + gpio-key,wakeup; + }; + + left-button { + label = "left"; + linux,code = ; + gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; /* GPIO_96 */ + gpio-key,wakeup; + }; + + right-button { + label = "right"; + linux,code = ; + gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; /* GPIO_98 */ + gpio-key,wakeup; + }; + + pageup-button { + label = "game 1"; + linux,code = ; + gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* GPIO_109 */ + gpio-key,wakeup; + }; + + pagedown-button { + label = "game 3"; + linux,code = ; + gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* GPIO_106 */ + gpio-key,wakeup; + }; + + home-button { + label = "game 4"; + linux,code = ; + gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* GPIO_101 */ + gpio-key,wakeup; + }; + + end-button { + label = "game 2"; + linux,code = ; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* GPIO_111 */ + gpio-key,wakeup; + }; + + right-shift { + label = "l"; + linux,code = ; + gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* GPIO_102 */ + gpio-key,wakeup; + }; + + kp-plus { + label = "l2"; + linux,code = ; + gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; /* GPIO_97 */ + gpio-key,wakeup; + }; + + right-ctrl { + label = "r"; + linux,code = ; + gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* GPIO_105 */ + gpio-key,wakeup; + }; + + kp-minus { + label = "r2"; + linux,code = ; + gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* GPIO_107 */ + gpio-key,wakeup; + }; + + left-ctrl { + label = "ctrl"; + linux,code = ; + gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* GPIO_104 */ + gpio-key,wakeup; + }; + + menu { + label = "menu"; + linux,code = ; + gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; /* GPIO_99 */ + gpio-key,wakeup; + }; + + hold { + label = "hold"; + linux,code = ; + gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* GPIO_176 */ + gpio-key,wakeup; + }; + + left-alt { + label = "alt"; + linux,code = ; + gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; /* GPIO_100 */ + gpio-key,wakeup; + }; + + lid { + label = "lid"; + linux,code = <0x00>; /* SW_LID lid shut */ + linux,input-type = <0x05>; /* EV_SW */ + gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; /* GPIO_108 */ + }; + }; +}; + +&omap3_pmx_core { + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dirdat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dirdat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dircmd */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ + >; + }; + + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* GPIO_157 = lcd reset */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + led_pins: pinmux_leds_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2154, PIN_OUTPUT | MUX_MODE4) /* GPIO_128 */ + OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* GPIO_129 */ + OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE4) /* GPIO_158 */ + OMAP3_CORE1_IOPAD(0x2192, PIN_OUTPUT | MUX_MODE4) /* GPIO_159 */ + >; + }; + + button_pins: pinmux_button_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE4) /* GPIO_96 */ + OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE4) /* GPIO_97 */ + OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* GPIO_98 */ + OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE4) /* GPIO_99 */ + OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE4) /* GPIO_100 */ + OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* GPIO_101 */ + OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4) /* GPIO_102 */ + OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE4) /* GPIO_103 */ + OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE4) /* GPIO_104 */ + OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE4) /* GPIO_105 */ + OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE4) /* GPIO_106 */ + OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE4) /* GPIO_107 */ + OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE4) /* GPIO_108 */ + OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* GPIO_109 */ + OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT | MUX_MODE4) /* GPIO_110 */ + OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* GPIO_111 */ + OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* GPIO_176 */ + >; + }; + + penirq_pins: pinmux_penirq_pins { + pinctrl-single,pins = < + /* here we could enable to wakeup the cpu from suspend by a pen touch */ + OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE4) /* GPIO_94 */ + >; + }; + +}; + +&omap3_pmx_core2 { + /* define in CPU specific file that includes this one + * use either OMAP3430_CORE2_IOPAD() or OMAP3630_CORE2_IOPAD() + */ +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + twl_power: power { + compatible = "ti,twl4030-power-reset"; + ti,use_poweroff; + }; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + + codec { + ti,ramp_delay_value = <3>; + }; + }; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&twl_keypad { + keypad,num-rows = <8>; + keypad,num-columns = <6>; + linux,keymap = < + MATRIX_KEY(0, 0, KEY_9) + MATRIX_KEY(0, 1, KEY_8) + MATRIX_KEY(0, 2, KEY_I) + MATRIX_KEY(0, 3, KEY_J) + MATRIX_KEY(0, 4, KEY_N) + MATRIX_KEY(0, 5, KEY_M) + MATRIX_KEY(1, 0, KEY_0) + MATRIX_KEY(1, 1, KEY_7) + MATRIX_KEY(1, 2, KEY_U) + MATRIX_KEY(1, 3, KEY_H) + MATRIX_KEY(1, 4, KEY_B) + MATRIX_KEY(1, 5, KEY_SPACE) + MATRIX_KEY(2, 0, KEY_BACKSPACE) + MATRIX_KEY(2, 1, KEY_6) + MATRIX_KEY(2, 2, KEY_Y) + MATRIX_KEY(2, 3, KEY_G) + MATRIX_KEY(2, 4, KEY_V) + MATRIX_KEY(2, 5, KEY_FN) + MATRIX_KEY(3, 0, KEY_O) + MATRIX_KEY(3, 1, KEY_5) + MATRIX_KEY(3, 2, KEY_T) + MATRIX_KEY(3, 3, KEY_F) + MATRIX_KEY(3, 4, KEY_C) + MATRIX_KEY(4, 0, KEY_P) + MATRIX_KEY(4, 1, KEY_4) + MATRIX_KEY(4, 2, KEY_R) + MATRIX_KEY(4, 3, KEY_D) + MATRIX_KEY(4, 4, KEY_X) + MATRIX_KEY(5, 0, KEY_K) + MATRIX_KEY(5, 1, KEY_3) + MATRIX_KEY(5, 2, KEY_E) + MATRIX_KEY(5, 3, KEY_S) + MATRIX_KEY(5, 4, KEY_Z) + MATRIX_KEY(6, 0, KEY_L) + MATRIX_KEY(6, 1, KEY_2) + MATRIX_KEY(6, 2, KEY_W) + MATRIX_KEY(6, 3, KEY_A) + MATRIX_KEY(6, 4, KEY_RIGHTBRACE) + MATRIX_KEY(7, 0, KEY_ENTER) + MATRIX_KEY(7, 1, KEY_1) + MATRIX_KEY(7, 2, KEY_Q) + MATRIX_KEY(7, 3, KEY_LEFTSHIFT) + MATRIX_KEY(7, 4, KEY_LEFTBRACE ) + >; +}; + +/* backup battery charger */ +&charger { + ti,bb-uvolt = <3200000>; + ti,bb-uamp = <150>; +}; + +/* MMC2 */ +&vmmc2 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <3150000>; +}; + +/* LCD */ +&vaux1 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; + +/* USB Host PHY */ +&vaux2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +/* available on expansion connector */ +&vaux3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +/* ADS7846 and nubs */ +&vaux4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +/* power audio DAC and LID sensor */ +&vsim { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; +}; + +&i2c2 { + clock-frequency = <100000>; + /* no clients so we should disable clock */ +}; + +&i2c3 { + clock-frequency = <100000>; + + bq27500@55 { + compatible = "ti,bq27500"; + reg = <0x55>; + }; + +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc1>; + bus-width = <4>; + cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; /* GPIO_126 */ +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&vmmc2>; + bus-width = <4>; + cd-gpios = <&twl_gpio 1 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* GPIO_127 */ +}; + +/* bluetooth*/ +&uart1 { +}; + +/* spare (expansion connector) */ +&uart2 { +}; + +/* console (expansion connector) */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +}; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + nand-bus-width = <16>; + ti,nand-ecc-opt = "sw"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,device-width = <2>; + + #address-cells = <1>; + #size-cells = <1>; + + /* u-boot uses mtdparts=nand:512k(xloader),1920k(uboot),128k(uboot-env),10m(boot),-(rootfs) */ + + x-loader@0 { + label = "xloader"; + reg = <0 0x80000>; + }; + + bootloaders@80000 { + label = "uboot"; + reg = <0x80000 0x1e0000>; + }; + + bootloaders_env@260000 { + label = "uboot-env"; + reg = <0x260000 0x20000>; + }; + + kernel@280000 { + label = "boot"; + reg = <0x280000 0xa00000>; + }; + + filesystem@680000 { + label = "rootfs"; + reg = <0xc80000 0>; /* 0 = MTDPART_SIZ_FULL */ + }; + }; +}; + +&mcspi1 { + tsc2046@0 { + reg = <0>; /* CS0 */ + compatible = "ti,tsc2046"; + spi-max-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&penirq_pins>; + interrupt-parent = <&gpio3>; + interrupts = <30 0>; /* GPIO_94 */ + pendown-gpio = <&gpio3 30 0>; + vcc-supply = <&vaux4>; + + ti,x-min = /bits/ 16 <0>; + ti,x-max = /bits/ 16 <8000>; + ti,y-min = /bits/ 16 <0>; + ti,y-max = /bits/ 16 <4800>; + ti,x-plate-ohms = /bits/ 16 <40>; + ti,pressure-max = /bits/ 16 <255>; + + linux,wakeup; + }; + + lcd: lcd@1 { + reg = <1>; /* CS1 */ + compatible = "omapdss,tpo,td043mtea1"; + spi-max-frequency = <100000>; + spi-cpol; + spi-cpha; + + label = "lcd"; + reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; /* GPIO_157 */ + vcc-supply = <&vaux1>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + +}; + +/* n/a - used as GPIOs */ +&mcbsp1 { +}; + +/* audio DAC */ +&mcbsp2 { +}; + +/* bluetooth */ +&mcbsp3 { +}; + +/* to twl4030*/ +&mcbsp4 { +}; + +&venc { + status = "ok"; + + vdda-supply = <&vdac>; + + port { + venc_out: endpoint { + remote-endpoint = <&tv_connector_in>; + ti,channels = <2>; + }; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = < &dss_dpi_pins >; + + status = "ok"; + vdds_dsi-supply = <&vpll2>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; -- cgit v0.10.2 From b715da74deafb5f5a324001e9520b948f8c2795c Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Fri, 27 Feb 2015 22:26:38 +0100 Subject: ARM: dts: omap3-pandora: add OMAP3530 600 MHz version Added Pandora Rebirth model which is based on Pandora Classic with 512 MiB DDR-333 SDRAM memory. Signed-off-by: H. Nikolaus Schaller Tested-by: Grazvydas Ignotas Reviewed-by: Grazvydas Ignotas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b316b38..c650509 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -386,6 +386,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \ omap3-overo-storm-tobi.dtb \ omap3-overo-summit.dtb \ omap3-overo-tobi.dtb \ + omap3-pandora-600mhz.dtb \ omap3-sbc-t3517.dtb \ omap3-sbc-t3530.dtb \ omap3-sbc-t3730.dtb \ diff --git a/arch/arm/boot/dts/omap3-pandora-600mhz.dts b/arch/arm/boot/dts/omap3-pandora-600mhz.dts new file mode 100644 index 0000000..fb803a7 --- /dev/null +++ b/arch/arm/boot/dts/omap3-pandora-600mhz.dts @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2015 + * Nikolaus Schaller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * device tree for OpenPandora with OMAP3530 + */ + +/dts-v1/; + +#include "omap34xx.dtsi" +#include "omap3-pandora-common.dtsi" + +/ { + model = "Pandora Handheld Console"; + + compatible = "ti,omap3"; +}; + +&omap3_pmx_core2 { + + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + &control_pins + >; + + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; + + mmc3_pins: pinmux_mmc3_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ + OMAP3430_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ + OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ + OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ + OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ + OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ + >; + }; + + control_pins: pinmux_control_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ + OMAP3430_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ + OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 = RESET_USB_HOST */ + OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4) /* etk_d7.gpio_21 = WIFI IRQ */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 = MSECURE */ + OMAP3430_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4) /* etk_d9.gpio_23 = WIFI_POWER */ + >; + }; +}; -- cgit v0.10.2 From 9ccd0106c9dbcb7b6328680f4375f885f0efaca8 Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Fri, 27 Feb 2015 22:26:39 +0100 Subject: ARM: dts: omap3-pandora: add DM3730 1 GHz version Added Pandora 1 GHz model which is based on Classic/Rebirth with following changes: - upgraded cpu to dm3730 runs on 1GHz - 512 MiB DDR-333 SDRAM @ 200 MHz Signed-off-by: H. Nikolaus Schaller Tested-by: Grazvydas Ignotas Reviewed-by: Grazvydas Ignotas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c650509..a533f72 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -387,6 +387,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \ omap3-overo-summit.dtb \ omap3-overo-tobi.dtb \ omap3-pandora-600mhz.dtb \ + omap3-pandora-1ghz.dtb \ omap3-sbc-t3517.dtb \ omap3-sbc-t3530.dtb \ omap3-sbc-t3730.dtb \ diff --git a/arch/arm/boot/dts/omap3-pandora-1ghz.dts b/arch/arm/boot/dts/omap3-pandora-1ghz.dts new file mode 100644 index 0000000..9619a28 --- /dev/null +++ b/arch/arm/boot/dts/omap3-pandora-1ghz.dts @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2015 + * Nikolaus Schaller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * device tree for OpenPandora 1GHz with DM3730 + */ + +/dts-v1/; + +#include "omap36xx.dtsi" +#include "omap3-pandora-common.dtsi" + +/ { + model = "Pandora Handheld Console 1GHz"; + + compatible = "ti,omap36xx", "ti,omap3"; +}; + +&omap3_pmx_core2 { + + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + &control_pins + >; + + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; + + mmc3_pins: pinmux_mmc3_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ + OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ + OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ + OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ + OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ + OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ + >; + }; + + control_pins: pinmux_control_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ + OMAP3630_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ + OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 = RESET_USB_HOST */ + OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4) /* etk_d7.gpio_21 = WIFI IRQ */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 = MSECURE */ + OMAP3630_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4) /* etk_d9.gpio_23 = WIFI_POWER */ + OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT | MUX_MODE4) /* reserved.gpio_127 = MMC2_WP */ + OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 = MMC1_WP */ + OMAP3_WKUP_IOPAD(0x2a58, PIN_OUTPUT | MUX_MODE4) /* reserved.gpio_128 = LED_MMC1 */ + OMAP3_WKUP_IOPAD(0x2a5a, PIN_OUTPUT | MUX_MODE4) /* reserved.gpio_129 = LED_MMC2 */ + + >; + }; +}; -- cgit v0.10.2 From a895b8a0d1e474dcfce3680d8f66cc08056acc1c Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Mon, 2 Mar 2015 16:19:34 +0530 Subject: ARM: dts: AM4372: update hdq compatible property This patch updates hdq node compatible property to "ti,am4372-hdq". Signed-off-by: Vignesh R Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 1943fc3..ae0e8c1 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -884,7 +884,7 @@ }; hdq: hdq@48347000 { - compatible = "ti,am43xx-hdq"; + compatible = "ti,am4372-hdq"; reg = <0x48347000 0x1000>; interrupts = ; clocks = <&func_12m_clk>; -- cgit v0.10.2 From d37530a0fc13b860f3b4ef88fbddff69fac52fc0 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Fri, 6 Mar 2015 17:10:05 +0200 Subject: ARM: dts: omap3-beagle: Add NAND device The beagle board contains a 16-bit NAND device connected to chip select 0 of the GPMC controller. Signed-off-by: Roger Quadros Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index c792391..bf28502 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -379,3 +379,55 @@ }; }; }; + +&gpmc { + status = "ok"; + ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */ + + /* Chip select 0 */ + nand@0,0 { + reg = <0 0 4>; /* NAND I/O window, 4 bytes */ + interrupts = <20>; + ti,nand-ecc-opt = "ham1"; + nand-bus-width = <16>; + #address-cells = <1>; + #size-cells = <1>; + + gpmc,device-width = <2>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <36>; + gpmc,cs-wr-off-ns = <36>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <24>; + gpmc,adv-wr-off-ns = <36>; + gpmc,oe-on-ns = <6>; + gpmc,oe-off-ns = <48>; + gpmc,we-on-ns = <6>; + gpmc,we-off-ns = <30>; + gpmc,rd-cycle-ns = <72>; + gpmc,wr-cycle-ns = <72>; + gpmc,access-ns = <54>; + gpmc,wr-access-ns = <30>; + + partition@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + partition@80000 { + label = "U-Boot"; + reg = <0x80000 0x1e0000>; + }; + partition@1c0000 { + label = "U-Boot Env"; + reg = <0x260000 0x20000>; + }; + partition@280000 { + label = "Kernel"; + reg = <0x280000 0x400000>; + }; + partition@780000 { + label = "Filesystem"; + reg = <0x680000 0xf980000>; + }; + }; +}; -- cgit v0.10.2 From 3eb78ea8411e3877ace2af700c9a90847d1a397e Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Fri, 13 Mar 2015 21:40:36 +0100 Subject: ARM: dts: omap3: Remove all references to ti,codec property ti,codec property is not used (parsed) in omap-twl4030 driver. The ti,twl4030-audio which ti,codec points by phandle is mfd driver and device for ASoC codec is created w/o DT compatible string. Removing all references in DT files. Signed-off-by: Marek Belisko Acked-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 25f7b0a..da1464b 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -60,7 +60,6 @@ ti,model = "omap3beagle"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; gpio_keys { diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index bf28502..28f99a1 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -71,7 +71,6 @@ ti,model = "omap3beagle"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; gpio_keys { diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi index d9e92b6..046cd77 100644 --- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi +++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi @@ -16,7 +16,6 @@ ti,model = "cm-t35"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; }; diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts index 169037e..134d3f2 100644 --- a/arch/arm/boot/dts/omap3-devkit8000.dts +++ b/arch/arm/boot/dts/omap3-devkit8000.dts @@ -48,7 +48,6 @@ ti,model = "devkit8000"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; ti,audio-routing = "Ext Spk", "PREDRIVEL", "Ext Spk", "PREDRIVER", diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index fb3a696..b9f6881 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -46,7 +46,6 @@ ti,model = "gta04"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; spi_lcd { diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index 8a63ad2..d5e5cd4 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi @@ -22,7 +22,6 @@ compatible = "ti,omap-twl4030"; ti,model = "igep2"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; vdd33: regulator-vdd33 { diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi index e81fb65..e631333 100644 --- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi +++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi @@ -38,7 +38,6 @@ ti,model = "lilly-a83x"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; reg_vcc3: vcc3 { diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi index d36bf02..18e1649 100644 --- a/arch/arm/boot/dts/omap3-overo-base.dtsi +++ b/arch/arm/boot/dts/omap3-overo-base.dtsi @@ -27,7 +27,6 @@ ti,model = "overo"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; /* HS USB Port 2 Power */ diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi index e89820a..b3b24a5 100644 --- a/arch/arm/boot/dts/omap3-tao3530.dtsi +++ b/arch/arm/boot/dts/omap3-tao3530.dtsi @@ -45,7 +45,6 @@ /* McBSP2 is used for onboard sound, same as on beagle */ ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; /* Regulator to enable/switch the vcc of the Wifi module */ -- cgit v0.10.2 From 624ce7616d90337738dfd24c8e6ff7adf0060ad7 Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Fri, 13 Mar 2015 21:40:37 +0100 Subject: Documentation: omap-twl4030: Move ti,codec property to optional ti,codec property is not used in omap-twl4030 driver in linux kernel but we keep it as optional property, so that the existing dtbs do not become noncompliant after the change on other OS. Signed-off-by: Marek Belisko Acked-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/Documentation/devicetree/bindings/sound/omap-twl4030.txt b/Documentation/devicetree/bindings/sound/omap-twl4030.txt index 1ab6bc8..f6a715e 100644 --- a/Documentation/devicetree/bindings/sound/omap-twl4030.txt +++ b/Documentation/devicetree/bindings/sound/omap-twl4030.txt @@ -4,9 +4,9 @@ Required properties: - compatible: "ti,omap-twl4030" - ti,model: Name of the sound card (for example "omap3beagle") - ti,mcbsp: phandle for the McBSP node -- ti,codec: phandle for the twl4030 audio node Optional properties: +- ti,codec: phandle for the twl4030 audio node - ti,mcbsp-voice: phandle for the McBSP node connected to the voice port of twl - ti, jack-det-gpio: Jack detect GPIO - ti,audio-routing: List of connections between audio components. @@ -59,5 +59,4 @@ sound { ti,model = "omap3beagle"; ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; }; -- cgit v0.10.2 From 38b1565ca77f411c85427988fa30c3482d5d7e68 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 16 Mar 2015 12:20:37 -0500 Subject: ARM: dts: DRA7: Remove ti,timer-dsp and ti,timer-pwm properties Remove the 'ti,timer-dsp' and 'ti,timer-pwm' properties from the timer nodes that still have them. This seems to be copied from OMAP5, on which only certain timers are capable of providing PWM functionality or be able to interrupt the DSP. All the GPTimers On DRA7 are capable of PWM and interrupting any core (due to the presence of Crossbar). These properties were used by the driver to add capabilities to each timer, and support requesting timers by capability. In the DT world, we expect any users of timers to use phandles to the respective timer, and use the omap_dm_timer_request_by_node() API. The API to request using capabilities, omap_dm_timer_request_by_cap() API should be deprecated eventually. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 127608d..eea4a54 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -658,7 +658,6 @@ reg = <0x48820000 0x80>; interrupts = ; ti,hwmods = "timer5"; - ti,timer-dsp; }; timer6: timer@48822000 { @@ -666,8 +665,6 @@ reg = <0x48822000 0x80>; interrupts = ; ti,hwmods = "timer6"; - ti,timer-dsp; - ti,timer-pwm; }; timer7: timer@48824000 { @@ -675,7 +672,6 @@ reg = <0x48824000 0x80>; interrupts = ; ti,hwmods = "timer7"; - ti,timer-dsp; }; timer8: timer@48826000 { @@ -683,8 +679,6 @@ reg = <0x48826000 0x80>; interrupts = ; ti,hwmods = "timer8"; - ti,timer-dsp; - ti,timer-pwm; }; timer9: timer@4803e000 { @@ -706,7 +700,6 @@ reg = <0x48088000 0x80>; interrupts = ; ti,hwmods = "timer11"; - ti,timer-pwm; }; timer13: timer@48828000 { -- cgit v0.10.2 From ac434806f233e43c50afee0e42c88e6e7842572f Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 26 Feb 2015 15:40:39 +0200 Subject: ARM: dts: am57xx-beagle-x15: Do not include the atl header AM57xx does not have ATL block integrated. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts index 6463f9e..c1d82e8 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15.dts +++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts @@ -8,7 +8,6 @@ /dts-v1/; #include "dra74x.dtsi" -#include #include #include -- cgit v0.10.2 From a87cd07b88b4797d50d11fa1089705a284ae087f Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 3 Mar 2015 11:43:17 +0100 Subject: ARM: mvebu: Enable Performance Monitor Unit on Armada XP/370 SoCs The Armada 370 and XP SoCs have Cortex-A9 compatible CPUs, and with a Performance Monitoring Unit. Enable it so that we can have hardware-assisted perf support. Signed-off-by: Maxime Ripard Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 7b3393e..ec96f0b 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -73,6 +73,11 @@ }; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&mpic 3>; + }; + soc { #address-cells = <2>; #size-cells = <1>; -- cgit v0.10.2 From 7f592c39d4975d9e6d3d0ebcf39695a487a6dc4e Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Tue, 3 Mar 2015 11:43:18 +0100 Subject: ARM: mvebu: Enable Performance Monitor Unit on Armada 375 SoC The Armada 375 SoC has a Cortex-A9 CPU, and so the PMU is available to be used. This commit enables it in the devicetree. Signed-off-by: Ezequiel Garcia Signed-off-by: Maxime Ripard Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index c6fedf2..c675257 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -96,6 +96,11 @@ }; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&mpic 3>; + }; + soc { compatible = "marvell,armada375-mbus", "simple-bus"; #address-cells = <2>; -- cgit v0.10.2 From 754c4b1b2bddc6881889be9b4aa549d1647ef9ca Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Tue, 3 Mar 2015 11:43:19 +0100 Subject: ARM: mvebu: Enable Performance Monitor Unit on Armada 380/385 SoC The Armada 380 and 385 SoCs have a Cortex-A9 CPU, so the PMU is available to be used. This commit enables it in the devicetree. Signed-off-by: Ezequiel Garcia Signed-off-by: Maxime Ripard Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 1a2dc37..ed2dd8b 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -63,6 +63,11 @@ serial1 = &uart1; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&mpic 3>; + }; + soc { compatible = "marvell,armada380-mbus", "simple-bus"; #address-cells = <2>; -- cgit v0.10.2 From 52005dece52703e18af4611e9c15f9d923c737ea Mon Sep 17 00:00:00 2001 From: Beata Michalska Date: Wed, 18 Mar 2015 00:21:46 +0900 Subject: ARM: dts: Add assigned clock parents to CMU node for exynos3250 Use assigned-clocks/assigned-clock-parents properties for CMU clock controller DT node to secure proper clock setup: switching the two muxes to root oscillator clock is not only required for proper powering down the ISP power domain, but it also reduces the risk of accessing the ISP CMU registers while the ISP power domain remains turned off (i.e. through the common clock framework by clk_summary) Signed-off-by: Beata Michalska Acked-by: Kyungmin Park Acked-by: Sylwester Nawrocki Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 277b48b..6d6118e 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -172,6 +172,10 @@ compatible = "samsung,exynos3250-cmu"; reg = <0x10030000 0x20000>; #clock-cells = <1>; + assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>, + <&cmu CLK_MOUT_ACLK_266_SUB>; + assigned-clock-parents = <&cmu CLK_FIN_PLL>, + <&cmu CLK_FIN_PLL>; }; cmu_dmc: clock-controller@105C0000 { -- cgit v0.10.2 From 1d1b00aae0bc0b0aba7844099149170744fc1b30 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 18 Mar 2015 00:31:22 +0900 Subject: ARM: dts: Define stdout-path property for Peach boards The kernel can use as the default console a serial port if is defined as stdout device in the Device Tree. This allows a board to be booted without the need of having a console parameter in the kernel command line. Signed-off-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index d0ee55f..3f4e2fe 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -43,6 +43,10 @@ pinctrl-names = "default"; }; + chosen { + stdout-path = "serial3:115200n8"; + }; + fixed-rate-clocks { oscclk { compatible = "samsung,exynos5420-oscclk"; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 7ea1d66..c833bac 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -42,6 +42,10 @@ pinctrl-names = "default"; }; + chosen { + stdout-path = "serial3:115200n8"; + }; + fixed-rate-clocks { oscclk { compatible = "samsung,exynos5420-oscclk"; -- cgit v0.10.2 From 038e4096054c90f78a9d14eca41b715154341d13 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 18 Mar 2015 00:31:27 +0900 Subject: ARM: dts: Define stdout-path property for exynos5250-snow The kernel can use as the default console a serial port if is defined as stdout device in the Device Tree. This allows a board to be booted without the need of having a console parameter in the kernel command line. Currently the Snow DTS has a bootargs in the /chosen node and this is kept since users that don't have a serial console on this board might be using it to have the boot log shown in the display. This will have more precedence than the stdout-path but it's fine since is only used when CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is enabled. Signed-off-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 5be966d..2657e84 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -29,6 +29,7 @@ chosen { bootargs = "console=tty1"; + stdout-path = "serial3:115200n8"; }; gpio-keys { -- cgit v0.10.2 From 46a0b9ff21d3c409a65d285e8a7a39f07f495706 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 18 Mar 2015 00:31:33 +0900 Subject: ARM: dts: Define stdout-path property for exynos5250-spring The kernel can use as the default console a serial port if is defined as stdout device in the Device Tree. This allows a board to be booted without the need of having a console parameter in the kernel command line. Currently the Spring DTS has bootargs in the /chosen node and this is kept since users that don't have a serial console on this board might be using it to have the boot log shown in the display. This will have more precedence than the stdout-path but it's fine since is only used when CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is enabled. Signed-off-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index f027754..b9ec763 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -25,6 +25,7 @@ chosen { bootargs = "console=tty1"; + stdout-path = "serial3:115200n8"; }; gpio-keys { -- cgit v0.10.2 From 472c95a6e352413af068b42ab0db2b2e23c20756 Mon Sep 17 00:00:00 2001 From: Andrzej Hajda Date: Wed, 18 Mar 2015 02:14:07 +0900 Subject: dt-bindings: add asynchronous bridge clock for exynos The patch adds bindings for clocks required by async-bridges present in the particular power domain. Signed-off-by: Andrzej Hajda Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt index f4445e5..c47e79b 100644 --- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt +++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt @@ -22,6 +22,9 @@ Optional Properties: - pclkN, clkN: Pairs of parent of input clock and input clock to the devices in this power domain. Maximum of 4 pairs (N = 0 to 3) are supported currently. + - asbN: Clocks required by asynchronous bridges (ASB) present in + the power domain. These clock should be enabled during power + domain on/off operations. Node of a device using power domains must have a power-domains property defined with a phandle to respective power domain. -- cgit v0.10.2 From ffb8b1ee9a704229f0b6753970ae09dc4d6863d9 Mon Sep 17 00:00:00 2001 From: Andrzej Hajda Date: Wed, 18 Mar 2015 02:14:07 +0900 Subject: ARM: dts: add async-bridge clocks to disp1 power domain for exynos5420 FIMD and MIXER IPs in disp1 power domain have async-bridges (to GSCALER), therefore their clocks should be enabled during power domain switch. Signed-off-by: Andrzej Hajda Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Reviewed-by: Sylwester Nawrocki Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 9dc2e97..ac0fc09 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -283,9 +283,11 @@ <&clock CLK_MOUT_SW_ACLK300>, <&clock CLK_MOUT_USER_ACLK300_DISP1>, <&clock CLK_MOUT_SW_ACLK400>, - <&clock CLK_MOUT_USER_ACLK400_DISP1>; + <&clock CLK_MOUT_USER_ACLK400_DISP1>, + <&clock CLK_FIMD1>, <&clock CLK_MIXER>; clock-names = "oscclk", "pclk0", "clk0", - "pclk1", "clk1", "pclk2", "clk2"; + "pclk1", "clk1", "pclk2", "clk2", + "asb0", "asb1"; }; pinctrl_0: pinctrl@13400000 { -- cgit v0.10.2 From fa87bd4360ab4244467571f4235ccb2b362fea24 Mon Sep 17 00:00:00 2001 From: Andrzej Hajda Date: Wed, 18 Mar 2015 02:14:07 +0900 Subject: ARM: dts: add async-bridge clocks to gsc power domain for exynos5420 Both GSCALER IPs in gsc power domain have async-bridges (to FIMD and MIXER), therefore their clocks should be enabled during power domain switch. Signed-off-by: Andrzej Hajda Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index ac0fc09..d4d643e 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -251,6 +251,8 @@ compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; #power-domain-cells = <0>; + clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; + clock-names = "asb0", "asb1"; }; isp_pd: power-domain@10044020 { -- cgit v0.10.2 From a7b0aa1932b1cdffe4aa901f562309d5fb5e8c4b Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 17 Mar 2015 11:43:51 +0200 Subject: ARM: dts: dra7x-evm: beagle-x15: Fix USB Peripheral Now that we have EXTCON_USB_GPIO queued for v4.1, revert commit addfcde7c485 ("ARM: dts: dra7x-evm: beagle-x15: Fix USB Host") On these EVMs, the USB cable state has to be determined via the ID pin tied to a GPIO line. We use the gpio-usb-extcon driver to read the ID pin and the extcon framework to forward the USB cable state information to the USB driver so the controller can be configured in the right mode (host/peripheral). Gets USB peripheral mode to work on this EVM. Reviewed-by: Felipe Balbi Signed-off-by: Roger Quadros diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts index c1d82e8..41642fe 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15.dts +++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts @@ -548,6 +548,14 @@ pinctrl-0 = <&usb1_pins>; }; +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + &usb2 { dr_mode = "peripheral"; }; diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 3290a96..746cddb 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -543,6 +543,14 @@ }; }; +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + &usb1 { dr_mode = "peripheral"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index e0264d0..4d87117 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -380,6 +380,14 @@ phy-supply = <&ldo4_reg>; }; +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + &usb1 { dr_mode = "peripheral"; pinctrl-names = "default"; -- cgit v0.10.2 From 7776ab70d75ff9857343e44e428744d81c30ce1b Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 19 Jan 2015 14:01:14 +0100 Subject: ARM: mvebu: armada-385-ap: Enable USB3 port The Armada 385 AP board has a USB3 port exposed that uses a GPIO to drive the VBUS line. Enable the needed drivers to support this. Signed-off-by: Maxime Ripard Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts index d6b0f7d..7219ac3 100644 --- a/arch/arm/boot/dts/armada-385-db-ap.dts +++ b/arch/arm/boot/dts/armada-385-db-ap.dts @@ -125,6 +125,13 @@ status = "okay"; }; + pinctrl@18000 { + xhci0_vbus_pins: xhci0-vbus-pins { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + }; + ethernet@30000 { status = "okay"; phy = <&phy2>; @@ -162,6 +169,11 @@ marvell,nand-enable-arbiter; nand-on-flash-bbt; }; + + usb3@f0000 { + status = "okay"; + usb-phy = <&usb3_phy>; + }; }; pcie-controller { @@ -187,4 +199,20 @@ }; }; }; + + usb3_phy: usb3_phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <®_xhci0_vbus>; + }; + + reg_xhci0_vbus: xhci0-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&xhci0_vbus_pins>; + regulator-name = "xhci0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; }; -- cgit v0.10.2 From b7f01842bcbbf8aaf26c9f9bd413774114fa83c9 Mon Sep 17 00:00:00 2001 From: Nadav Haklai Date: Tue, 17 Mar 2015 13:53:34 +0100 Subject: ARM: mvebu: clk: remove cpuclk resources overlapping coredivclk registers on Armada XP The resources of the cpuclk node are overlapping the one from coredivclk node. It was not noticed until now because the driver did a simple of_iomap and not a request_mem_region. This patch fixes it. [gregory.clement@free-electrons.com: add commit log and port to 4.0-rc] Signed-off-by: Nadav Haklai Signed-off-by: Gregory CLEMENT Reviewed-by: Thomas Petazzoni diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index ff47345..448af33 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -150,7 +150,7 @@ cpuclk: clock-complex@18700 { #clock-cells = <1>; compatible = "marvell,armada-xp-cpu-clock"; - reg = <0x18700 0xA0>, <0x1c054 0x10>; + reg = <0x18700 0x24>, <0x1c054 0x10>; clocks = <&coreclk 1>; }; -- cgit v0.10.2 From 292a3546b9eb20bf5a292f4e55dd1a027424669f Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 17 Mar 2015 17:33:54 +0100 Subject: ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level For L2 cache controller node, cache-level property is mandatory. Let's add it to Armada 370 and Armada XP device tree. Signed-off-by: Gregory CLEMENT Reviewed-by: Thomas Petazzoni diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 50f259b..00b50db5 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -129,6 +129,7 @@ compatible = "marvell,aurora-outer-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; + cache-level = <2>; cache-unified; wt-override; }; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 448af33..013d63f 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -79,6 +79,7 @@ compatible = "marvell,aurora-system-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; + cache-level = <2>; cache-unified; wt-override; }; -- cgit v0.10.2 From 3438bd2e7b00b047ea243272dc368fef89e90080 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 19 Mar 2015 09:14:35 -0700 Subject: ARM: dts: Fix typo for dm816x usb0_pins Commit a54879a00859 ("ARM: dts: Fix USB dts configuration for dm816x") attempted to fix the USB features introduced by commit 7800064ba507 ("ARM: dts: Add basic dm816x device tree configuration") but obviously I did not read the dmesg as more USB issues still keep trickling in. It should be usb1_pins instead not usb0_pins for the second interface to avoid warnings from pinctrl framework. Cc: Brian Hutchinson Cc: Felipe Balbi Cc: Matthijs van Duin Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts index d3a29c1..c8dff38 100644 --- a/arch/arm/boot/dts/dm8168-evm.dts +++ b/arch/arm/boot/dts/dm8168-evm.dts @@ -38,13 +38,13 @@ usb0_pins: pinmux_usb0_pins { pinctrl-single,pins = < - DM816X_IOPAD(0x0d00, MUX_MODE0) /* USB0_DRVVBUS */ + DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB0_DRVVBUS */ >; }; - usb1_pins: pinmux_usb0_pins { + usb1_pins: pinmux_usb1_pins { pinctrl-single,pins = < - DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB1_DRVVBUS */ + DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */ >; }; }; -- cgit v0.10.2 From de1a12216af0a46f878b9860fedadc985a7d71f3 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 19 Mar 2015 09:14:36 -0700 Subject: ARM: dts: Add cppi41 support for dm816x MUSB Looks like we have cppi41 on dm816x just like on am335x. Cc: Bin Liu Cc: Brian Hutchinson Cc: Felipe Balbi Cc: Matthijs van Duin Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index 3c97b5f..90c8207 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -386,6 +386,29 @@ mentor,num-eps = <16>; mentor,ram-bits = <12>; mentor,power = <500>; + + dmas = <&cppi41dma 0 0 &cppi41dma 1 0 + &cppi41dma 2 0 &cppi41dma 3 0 + &cppi41dma 4 0 &cppi41dma 5 0 + &cppi41dma 6 0 &cppi41dma 7 0 + &cppi41dma 8 0 &cppi41dma 9 0 + &cppi41dma 10 0 &cppi41dma 11 0 + &cppi41dma 12 0 &cppi41dma 13 0 + &cppi41dma 14 0 &cppi41dma 0 1 + &cppi41dma 1 1 &cppi41dma 2 1 + &cppi41dma 3 1 &cppi41dma 4 1 + &cppi41dma 5 1 &cppi41dma 6 1 + &cppi41dma 7 1 &cppi41dma 8 1 + &cppi41dma 9 1 &cppi41dma 10 1 + &cppi41dma 11 1 &cppi41dma 12 1 + &cppi41dma 13 1 &cppi41dma 14 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; }; usb1: usb@47401800 { @@ -403,6 +426,43 @@ mentor,num-eps = <16>; mentor,ram-bits = <12>; mentor,power = <500>; + + dmas = <&cppi41dma 15 0 &cppi41dma 16 0 + &cppi41dma 17 0 &cppi41dma 18 0 + &cppi41dma 19 0 &cppi41dma 20 0 + &cppi41dma 21 0 &cppi41dma 22 0 + &cppi41dma 23 0 &cppi41dma 24 0 + &cppi41dma 25 0 &cppi41dma 26 0 + &cppi41dma 27 0 &cppi41dma 28 0 + &cppi41dma 29 0 &cppi41dma 15 1 + &cppi41dma 16 1 &cppi41dma 17 1 + &cppi41dma 18 1 &cppi41dma 19 1 + &cppi41dma 20 1 &cppi41dma 21 1 + &cppi41dma 22 1 &cppi41dma 23 1 + &cppi41dma 24 1 &cppi41dma 25 1 + &cppi41dma 26 1 &cppi41dma 27 1 + &cppi41dma 28 1 &cppi41dma 29 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; + }; + + cppi41dma: dma-controller@47402000 { + compatible = "ti,am3359-cppi41"; + reg = <0x47400000 0x1000 + 0x47402000 0x1000 + 0x47403000 0x1000 + 0x47404000 0x4000>; + reg-names = "glue", "controller", "scheduler", "queuemgr"; + interrupts = <17>; + interrupt-names = "glue"; + #dma-cells = <2>; + #dma-channels = <30>; + #dma-requests = <256>; }; }; -- cgit v0.10.2 From a710d10d021735cc68be9609fe0fefe4c63938ae Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 19 Mar 2015 09:14:36 -0700 Subject: ARM: dts: Remove PIN_INPUT for dm816x McSPI On dm816x we have no PIN_INPUT vs PIN_OUTPUT configuration, there are just pulls. Let's remove the bogus flags. Cc: Brian Hutchinson Cc: Matthijs van Duin Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts index c8dff38..dee39c3 100644 --- a/arch/arm/boot/dts/dm8168-evm.dts +++ b/arch/arm/boot/dts/dm8168-evm.dts @@ -29,10 +29,10 @@ &dm816x_pinmux { mcspi1_pins: pinmux_mcspi1_pins { pinctrl-single,pins = < - DM816X_IOPAD(0x0a94, PIN_INPUT | MUX_MODE0) /* SPI_SCLK */ - DM816X_IOPAD(0x0a98, PIN_OUTPUT | MUX_MODE0) /* SPI_SCS0 */ - DM816X_IOPAD(0x0aa8, PIN_INPUT | MUX_MODE0) /* SPI_D0 */ - DM816X_IOPAD(0x0aac, PIN_INPUT | MUX_MODE0) /* SPI_D1 */ + DM816X_IOPAD(0x0a94, MUX_MODE0) /* SPI_SCLK */ + DM816X_IOPAD(0x0a98, MUX_MODE0) /* SPI_SCS0 */ + DM816X_IOPAD(0x0aa8, MUX_MODE0) /* SPI_D0 */ + DM816X_IOPAD(0x0aac, MUX_MODE0) /* SPI_D1 */ >; }; -- cgit v0.10.2 From a494e32d3a4fc8852da78b8fc8392aab77f998ba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 26 Feb 2015 14:49:57 +0100 Subject: ARM: dts: n9/n950: Enable omap crypto support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Harmattan system on Nokia N9 and N950 devices uses omap crypto support. Bootloader on those devices is known that it enables HW crypto support. This patch just include omap36xx.dtsi directly, so aes and sham is enabled. Signed-off-by: Pali Rohár Acked-by: Pavel Machek Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index c41db94..800b379 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ -#include "omap36xx-hs.dtsi" +#include "omap36xx.dtsi" / { cpus { -- cgit v0.10.2 From 69540a7c277d96382257216436f41abc040cc878 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 26 Feb 2015 14:49:58 +0100 Subject: ARM: dts: n900: Enable omap sham and include directly omap34xx.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch moves content of file omap34xx-hs.dtsi into omap3-n900.dts and enable omap sham support (omap HW support for SHA + MD5). After testing both omap hwmod and omap-sham.ko drivers it looks like signed Nokia X-Loader enable L3 firewall for omap sham. There is no kernel crash with both official bootloader and crypto enable bootloader. So we can safely enable sham code. Signed-off-by: Pali Rohár Acked-by: Pavel Machek Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index db80f9d..bbea307 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -9,9 +9,23 @@ /dts-v1/; -#include "omap34xx-hs.dtsi" +#include "omap34xx.dtsi" #include +/* + * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall + * for omap AES HW crypto support. When linux kernel try to access memory of AES + * blocks then kernel receive "Unhandled fault: external abort on non-linefetch" + * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no + * crash anymore) omap AES support will be disabled for all Nokia N900 devices. + * There is "unofficial" version of bootloader which enables AES in L3 firewall + * but it is not widely used and to prevent kernel crash rather AES is disabled. + * There is also no runtime detection code if AES is disabled in L3 firewall... + */ +&aes { + status = "disabled"; +}; + / { model = "Nokia N900"; compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3"; -- cgit v0.10.2 From a27c6f3ced3b8cbc8e31189eeffbd0f2f2e2dbc5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 26 Feb 2015 14:49:59 +0100 Subject: ARM: dts: omap3-tao3530: Include directly omap34xx.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch just move content of file omap34xx-hs.dtsi into omap3-tao3530.dts. There is no code change, patch is just preparation for removing -hs file. Signed-off-by: Pali Rohár Acked-by: Pavel Machek Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi index b3b24a5..7bd8d9a 100644 --- a/arch/arm/boot/dts/omap3-tao3530.dtsi +++ b/arch/arm/boot/dts/omap3-tao3530.dtsi @@ -8,7 +8,16 @@ */ /dts-v1/; -#include "omap34xx-hs.dtsi" +#include "omap34xx.dtsi" + +/* Secure omaps have some devices inaccessible depending on the firmware */ +&aes { + status = "disabled"; +}; + +&sham { + status = "disabled"; +}; / { cpus { -- cgit v0.10.2 From e36fcd13c26c360a8ea81910c87eea1e77c6187e Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Wed, 18 Mar 2015 17:31:31 -0700 Subject: ARM: dts: brcmstb: un-hexify clock frequency This value makes much more sense in decimal. Signed-off-by: Brian Norris Acked-by: Gregory Fong Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi index 0ca0f4e..b183dc9 100644 --- a/arch/arm/boot/dts/bcm7445.dtsi +++ b/arch/arm/boot/dts/bcm7445.dtsi @@ -76,7 +76,7 @@ reg-shift = <2>; reg-io-width = <4>; interrupts = ; - clock-frequency = <0x4d3f640>; + clock-frequency = <81000000>; }; sun_top_ctrl: syscon@404000 { -- cgit v0.10.2 From d1f2e5a135a6c0fd422398612aeab260cef28e82 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 26 Feb 2015 14:50:00 +0100 Subject: ARM: dts: Remove files omap34xx-hs.dtsi and omap36xx-hs.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These files are not used by any DTS file anymore. Signed-off-by: Pali Rohár Acked-by: Pavel Machek Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap34xx-hs.dtsi b/arch/arm/boot/dts/omap34xx-hs.dtsi deleted file mode 100644 index 1ff6264..0000000 --- a/arch/arm/boot/dts/omap34xx-hs.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -/* Disabled modules for secure omaps */ - -#include "omap34xx.dtsi" - -/* Secure omaps have some devices inaccessible depending on the firmware */ -&aes { - status = "disabled"; -}; - -&sham { - status = "disabled"; -}; - -&timer12 { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/omap36xx-hs.dtsi b/arch/arm/boot/dts/omap36xx-hs.dtsi deleted file mode 100644 index 2c7febb..0000000 --- a/arch/arm/boot/dts/omap36xx-hs.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -/* Disabled modules for secure omaps */ - -#include "omap36xx.dtsi" - -/* Secure omaps have some devices inaccessible depending on the firmware */ -&aes { - status = "disabled"; -}; - -&sham { - status = "disabled"; -}; - -&timer12 { - status = "disabled"; -}; -- cgit v0.10.2 From 0c02acec74b655fe44b698d293f6f2a9600c4a8b Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Wed, 18 Mar 2015 17:31:32 -0700 Subject: ARM: dts: brcmstb: add IRQ0 controller This L2 controller handles multiplexing a few different interrupts. We also need it for configuring the interrupt forwarding masks for the UART. With this, we can *now* boot BCM7445 to a prompt using the upstream kernel + DTB. Signed-off-by: Brian Norris Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi index b183dc9..9eaeac8 100644 --- a/arch/arm/boot/dts/bcm7445.dtsi +++ b/arch/arm/boot/dts/bcm7445.dtsi @@ -96,6 +96,18 @@ "syscon"; reg = <0x452000 0x100>; }; + + irq0_intc: interrupt-controller@f040a780 { + compatible = "brcm,bcm7120-l2-intc"; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + reg = <0x40a780 0x8>; + interrupt-controller; + interrupts = , + ; + brcm,int-map-mask = <0x25c>, <0x7000000>; + brcm,int-fwd-mask = <0x70000>; + }; }; smpboot { -- cgit v0.10.2 From 7eec52db361a6ae6fbbd86c2299718586866b664 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Thu, 19 Mar 2015 01:50:22 +0200 Subject: Documentation: DT: Add bindings for omap3isp Signed-off-by: Sakari Ailus Acked-by: Laurent Pinchart Signed-off-by: Tony Lindgren diff --git a/Documentation/devicetree/bindings/media/ti,omap3isp.txt b/Documentation/devicetree/bindings/media/ti,omap3isp.txt new file mode 100644 index 0000000..ac23de8 --- /dev/null +++ b/Documentation/devicetree/bindings/media/ti,omap3isp.txt @@ -0,0 +1,71 @@ +OMAP 3 ISP Device Tree bindings +=============================== + +The DT definitions can be found in include/dt-bindings/media/omap3-isp.h. + +Required properties +=================== + +compatible : must contain "ti,omap3-isp" + +reg : the two registers sets (physical address and length) for the + ISP. The first set contains the core ISP registers up to + the end of the SBL block. The second set contains the + CSI PHYs and receivers registers. +interrupts : the ISP interrupt specifier +iommus : phandle and IOMMU specifier for the IOMMU that serves the ISP +syscon : the phandle and register offset to the Complex I/O or CSI-PHY + register +ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430) + 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630) +#clock-cells : Must be 1 --- the ISP provides two external clocks, + cam_xclka and cam_xclkb, at indices 0 and 1, + respectively. Please find more information on common + clock bindings in ../clock/clock-bindings.txt. + +Port nodes (optional) +--------------------- + +More documentation on these bindings is available in +video-interfaces.txt in the same directory. + +reg : The interface: + 0 - parallel (CCDC) + 1 - CSIPHY1 -- CSI2C / CCP2B on 3630; + CSI1 -- CSIb on 3430 + 2 - CSIPHY2 -- CSI2A / CCP2B on 3630; + CSI2 -- CSIa on 3430 + +Optional properties +=================== + +vdd-csiphy1-supply : voltage supply of the CSI-2 PHY 1 +vdd-csiphy2-supply : voltage supply of the CSI-2 PHY 2 + +Endpoint nodes +-------------- + +lane-polarities : lane polarity (required on CSI-2) + 0 -- not inverted; 1 -- inverted +data-lanes : an array of data lanes from 1 to 3. The length can + be either 1 or 2. (required on CSI-2) +clock-lanes : the clock lane (from 1 to 3). (required on CSI-2) + + +Example +======= + + isp@480bc000 { + compatible = "ti,omap3-isp"; + reg = <0x480bc000 0x12fc + 0x480bd800 0x0600>; + interrupts = <24>; + iommus = <&mmu_isp>; + syscon = <&scm_conf 0x2f0>; + ti,phy-type = ; + #clock-cells = <1>; + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index eaf9996..6a271a6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7077,6 +7077,7 @@ OMAP IMAGING SUBSYSTEM (OMAP3 ISP and OMAP4 ISS) M: Laurent Pinchart L: linux-media@vger.kernel.org S: Maintained +F: Documentation/devicetree/bindings/media/ti,omap3isp.txt F: drivers/media/platform/omap3isp/ F: drivers/staging/media/omap4iss/ diff --git a/include/dt-bindings/media/omap3-isp.h b/include/dt-bindings/media/omap3-isp.h new file mode 100644 index 0000000..b18c60e --- /dev/null +++ b/include/dt-bindings/media/omap3-isp.h @@ -0,0 +1,22 @@ +/* + * include/dt-bindings/media/omap3-isp.h + * + * Copyright (C) 2015 Sakari Ailus + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#ifndef __DT_BINDINGS_OMAP3_ISP_H__ +#define __DT_BINDINGS_OMAP3_ISP_H__ + +#define OMAP3ISP_PHY_TYPE_COMPLEX_IO 0 +#define OMAP3ISP_PHY_TYPE_CSIPHY 1 + +#endif /* __DT_BINDINGS_OMAP3_ISP_H__ */ -- cgit v0.10.2 From e52117638b79e0ae65b5acd4bf65971cc0e8be9f Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Thu, 19 Mar 2015 01:50:23 +0200 Subject: ARM: dts: omap3: Add DT entries for OMAP 3 ISP The resources the ISP needs are slightly different on 3[45]xx and 3[67]xx. Especially the phy-type property is different. Signed-off-by: Sakari Ailus Acked-by: Laurent Pinchart [tony@atomide.com: use omap3_scm_general instead of scm_conf for now] Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index 3819c1e..7bc8c0f 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -8,6 +8,8 @@ * kind, whether express or implied. */ +#include + #include "omap3.dtsi" / { @@ -37,6 +39,21 @@ pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xff1f>; }; + + isp: isp@480bc000 { + compatible = "ti,omap3-isp"; + reg = <0x480bc000 0x12fc + 0x480bd800 0x017c>; + interrupts = <24>; + iommus = <&mmu_isp>; + syscon = <&omap3_scm_general 0xdc>; + ti,phy-type = ; + #clock-cells = <1>; + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 541704a..3502fe0 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -8,6 +8,8 @@ * kind, whether express or implied. */ +#include + #include "omap3.dtsi" / { @@ -69,6 +71,21 @@ pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xff1f>; }; + + isp: isp@480bc000 { + compatible = "ti,omap3-isp"; + reg = <0x480bc000 0x12fc + 0x480bd800 0x0600>; + interrupts = <24>; + iommus = <&mmu_isp>; + syscon = <&omap3_scm_general 0x2f0>; + ti,phy-type = ; + #clock-cells = <1>; + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; }; -- cgit v0.10.2 From 80a41581369c48a1af8ff086fdcaef0a9c3dd40c Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Thu, 19 Mar 2015 01:50:24 +0200 Subject: ARM: dts: n950, n9: Add primary camera support Add support for the primary camera of the Nokia N950 and N9. Signed-off-by: Sakari Ailus Acked-by: Laurent Pinchart Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts index 9938b5d..f2e2139 100644 --- a/arch/arm/boot/dts/omap3-n9.dts +++ b/arch/arm/boot/dts/omap3-n9.dts @@ -16,3 +16,40 @@ model = "Nokia N9"; compatible = "nokia,omap3-n9", "ti,omap36xx", "ti,omap3"; }; + +&i2c2 { + smia_1: camera@10 { + compatible = "nokia,smia"; + reg = <0x10>; + /* No reset gpio */ + vana-supply = <&vaux3>; + clocks = <&isp 0>; + clock-frequency = <9600000>; + nokia,nvm-size = <(16 * 64)>; + port { + smia_1_1: endpoint { + link-frequencies = /bits/ 64 <199200000 210000000 499200000>; + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&csi2a_ep>; + }; + }; + }; +}; + +&isp { + vdd-csiphy1-supply = <&vaux2>; + vdd-csiphy2-supply = <&vaux2>; + ports { + port@2 { + reg = <2>; + csi2a_ep: endpoint { + remote-endpoint = <&smia_1_1>; + clock-lanes = <2>; + data-lanes = <1 3>; + crc = <1>; + lane-polarities = <1 1 1>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts index 261c558..0885b34 100644 --- a/arch/arm/boot/dts/omap3-n950.dts +++ b/arch/arm/boot/dts/omap3-n950.dts @@ -16,3 +16,40 @@ model = "Nokia N950"; compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3"; }; + +&i2c2 { + smia_1: camera@10 { + compatible = "nokia,smia"; + reg = <0x10>; + /* No reset gpio */ + vana-supply = <&vaux3>; + clocks = <&isp 0>; + clock-frequency = <9600000>; + nokia,nvm-size = <(16 * 64)>; + port { + smia_1_1: endpoint { + link-frequencies = /bits/ 64 <210000000 333600000 398400000>; + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&csi2a_ep>; + }; + }; + }; +}; + +&isp { + vdd-csiphy1-supply = <&vaux2>; + vdd-csiphy2-supply = <&vaux2>; + ports { + port@2 { + reg = <2>; + csi2a_ep: endpoint { + remote-endpoint = <&smia_1_1>; + clock-lanes = <2>; + data-lanes = <3 1>; + crc = <1>; + lane-polarities = <1 1 1>; + }; + }; + }; +}; -- cgit v0.10.2 From 10709c0858d89716b10b7bbf6d825044f2f59602 Mon Sep 17 00:00:00 2001 From: Mark Jackson Date: Thu, 19 Mar 2015 15:07:43 +0000 Subject: ARM: dts: Update Nanobone dts file Update dts file to reflect:- * new flash memory layout * add missing phy-mode property * dual_emac now just a boolean * rename mcp to microchip * update gpio definition Signed-off-by: Mark Jackson Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts index a346645..5ed4ca6 100644 --- a/arch/arm/boot/dts/am335x-nano.dts +++ b/arch/arm/boot/dts/am335x-nano.dts @@ -213,7 +213,9 @@ pinctrl-0 = <&i2c0_pins>; gpio@20 { - compatible = "mcp,mcp23017"; + compatible = "microchip,mcp23017"; + gpio-controller; + #gpio-cells = <2>; reg = <0x20>; }; @@ -222,7 +224,7 @@ }; eeprom@53 { - compatible = "mcp,24c02"; + compatible = "microchip,24c02"; reg = <0x53>; pagesize = <8>; }; @@ -297,8 +299,8 @@ | |-->0x004FFFFF-> Kernel end | |-->0x00500000-> File system start | | - | |-->0x014FFFFF-> File system end - | |-->0x01500000-> User data start + | |-->0x01FFFFFF-> File system end + | |-->0x02000000-> User data start | | | |-->0x03FFFFFF-> User data end | |-->0x04000000-> Data storage start @@ -327,12 +329,12 @@ partition@4 { label = "rootfs"; - reg = <0x00500000 0x01000000>; /* 16MB */ + reg = <0x00500000 0x01b00000>; /* 27MB */ }; partition@5 { label = "user"; - reg = <0x01500000 0x02b00000>; /* 43MB */ + reg = <0x02000000 0x02000000>; /* 32MB */ }; partition@6 { @@ -343,7 +345,7 @@ }; &mac { - dual_emac = <1>; + dual_emac; status = "okay"; }; @@ -353,11 +355,13 @@ &cpsw_emac0 { phy_id = <&davinci_mdio>, <0>; + phy-mode = "mii"; dual_emac_res_vlan = <1>; }; &cpsw_emac1 { phy_id = <&davinci_mdio>, <1>; + phy-mode = "mii"; dual_emac_res_vlan = <2>; }; -- cgit v0.10.2 From 6f921fab5844941f7605b7f1a265f5fc7fe969a7 Mon Sep 17 00:00:00 2001 From: Luciano Coelho Date: Wed, 18 Mar 2015 18:38:25 +0200 Subject: wlcore: set irq_trigger in board files instead of hiding behind a quirk The platform_quirk element in the platform data was used to change the way the IRQ is triggered. When set, the EDGE_IRQ quirk would change the irqflags used and treat edge trigger differently from the rest. Instead of hiding this irq flag setting behind the quirk, have the board files set the irq_trigger explicitly. This will allow us to use standard irq DT definitions later on. Signed-off-by: Luciano Coelho [Eliad - rebase, add irq_trigger field and pass it, update board file changes] Signed-off-by: Eliad Peller Tested-by: Nikita Kiryanov Acked-by: Kalle Valo Acked-by: Sekhar Nori Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 6b5a97d..916589c 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -1385,8 +1385,8 @@ static const short da850_wl12xx_pins[] __initconst = { static struct wl12xx_platform_data da850_wl12xx_wlan_data __initdata = { .irq = -1, + .irq_trigger = IRQ_TYPE_EDGE_RISING, .board_ref_clock = WL12XX_REFCLOCK_38, - .platform_quirks = WL12XX_PLATFORM_QUIRK_EDGE_IRQ, }; static __init int da850_wl12xx_init(void) diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index e642b07..e86fb0d 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -48,6 +48,7 @@ static void __init __used legacy_init_wl12xx(unsigned ref_clock, wl12xx.board_ref_clock = ref_clock; wl12xx.board_tcxo_clock = tcxo_clock; wl12xx.irq = gpio_to_irq(gpio); + wl12xx.irq_trigger = IRQ_TYPE_LEVEL_HIGH; res = wl12xx_set_platform_data(&wl12xx); if (res) { diff --git a/drivers/net/wireless/ti/wlcore/debugfs.c b/drivers/net/wireless/ti/wlcore/debugfs.c index 68f3bf2..eb43f94 100644 --- a/drivers/net/wireless/ti/wlcore/debugfs.c +++ b/drivers/net/wireless/ti/wlcore/debugfs.c @@ -502,7 +502,7 @@ static ssize_t driver_state_read(struct file *file, char __user *user_buf, DRIVER_STATE_PRINT_HEX(irq); /* TODO: ref_clock and tcxo_clock were moved to wl12xx priv */ DRIVER_STATE_PRINT_HEX(hw_pg_ver); - DRIVER_STATE_PRINT_HEX(platform_quirks); + DRIVER_STATE_PRINT_HEX(irq_flags); DRIVER_STATE_PRINT_HEX(chip.id); DRIVER_STATE_PRINT_STR(chip.fw_ver_str); DRIVER_STATE_PRINT_STR(chip.phy_fw_ver_str); diff --git a/drivers/net/wireless/ti/wlcore/main.c b/drivers/net/wireless/ti/wlcore/main.c index 1e13699..67518f6 100644 --- a/drivers/net/wireless/ti/wlcore/main.c +++ b/drivers/net/wireless/ti/wlcore/main.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "wlcore.h" #include "debug.h" @@ -538,7 +539,7 @@ static int wlcore_irq_locked(struct wl1271 *wl) * In case edge triggered interrupt must be used, we cannot iterate * more than once without introducing race conditions with the hardirq. */ - if (wl->platform_quirks & WL12XX_PLATFORM_QUIRK_EDGE_IRQ) + if (wl->irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) loopcount = 1; wl1271_debug(DEBUG_IRQ, "IRQ work"); @@ -6249,7 +6250,6 @@ struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size, wl->ap_ps_map = 0; wl->ap_fw_ps_map = 0; wl->quirks = 0; - wl->platform_quirks = 0; wl->system_hlid = WL12XX_SYSTEM_HLID; wl->active_sta_count = 0; wl->active_link_count = 0; @@ -6391,7 +6391,8 @@ static void wlcore_nvs_cb(const struct firmware *fw, void *context) struct platform_device *pdev = wl->pdev; struct wlcore_platdev_data *pdev_data = dev_get_platdata(&pdev->dev); struct wl12xx_platform_data *pdata = pdev_data->pdata; - unsigned long irqflags; + struct resource *res; + int ret; irq_handler_t hardirq_fn = NULL; @@ -6418,19 +6419,23 @@ static void wlcore_nvs_cb(const struct firmware *fw, void *context) /* adjust some runtime configuration parameters */ wlcore_adjust_conf(wl); - wl->irq = platform_get_irq(pdev, 0); - wl->platform_quirks = pdata->platform_quirks; + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + wl1271_error("Could not get IRQ resource"); + goto out_free_nvs; + } + + wl->irq = res->start; + wl->irq_flags = res->flags & IRQF_TRIGGER_MASK; wl->if_ops = pdev_data->if_ops; - if (wl->platform_quirks & WL12XX_PLATFORM_QUIRK_EDGE_IRQ) { - irqflags = IRQF_TRIGGER_RISING; + if (wl->irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) hardirq_fn = wlcore_hardirq; - } else { - irqflags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT; - } + else + wl->irq_flags |= IRQF_ONESHOT; ret = request_threaded_irq(wl->irq, hardirq_fn, wlcore_irq, - irqflags, pdev->name, wl); + wl->irq_flags, pdev->name, wl); if (ret < 0) { wl1271_error("request_irq() failed: %d", ret); goto out_free_nvs; diff --git a/drivers/net/wireless/ti/wlcore/sdio.c b/drivers/net/wireless/ti/wlcore/sdio.c index d3dd7bf..2bce00a 100644 --- a/drivers/net/wireless/ti/wlcore/sdio.c +++ b/drivers/net/wireless/ti/wlcore/sdio.c @@ -287,7 +287,7 @@ static int wl1271_probe(struct sdio_func *func, memset(res, 0x00, sizeof(res)); res[0].start = pdev_data.pdata->irq; - res[0].flags = IORESOURCE_IRQ; + res[0].flags = IORESOURCE_IRQ | pdev_data.pdata->irq_trigger; res[0].name = "irq"; ret = platform_device_add_resources(glue->core, res, ARRAY_SIZE(res)); diff --git a/drivers/net/wireless/ti/wlcore/wlcore.h b/drivers/net/wireless/ti/wlcore/wlcore.h index d599c86..7f363fa 100644 --- a/drivers/net/wireless/ti/wlcore/wlcore.h +++ b/drivers/net/wireless/ti/wlcore/wlcore.h @@ -197,6 +197,8 @@ struct wl1271 { int irq; + int irq_flags; + spinlock_t wl_lock; enum wlcore_state state; @@ -404,9 +406,6 @@ struct wl1271 { /* Quirks of specific hardware revisions */ unsigned int quirks; - /* Platform limitations */ - unsigned int platform_quirks; - /* number of currently active RX BA sessions */ int ba_rx_session_count; diff --git a/include/linux/wl12xx.h b/include/linux/wl12xx.h index a9c723b..3876b67 100644 --- a/include/linux/wl12xx.h +++ b/include/linux/wl12xx.h @@ -57,15 +57,12 @@ struct wl1251_platform_data { struct wl12xx_platform_data { int irq; + u32 irq_trigger; int board_ref_clock; int board_tcxo_clock; - unsigned long platform_quirks; bool pwr_in_suspend; }; -/* Platform does not support level trigger interrupts */ -#define WL12XX_PLATFORM_QUIRK_EDGE_IRQ BIT(0) - #ifdef CONFIG_WILINK_PLATFORM_DATA int wl12xx_set_platform_data(const struct wl12xx_platform_data *data); -- cgit v0.10.2 From 4518996f90b1c2e04dfa15137dcafe59a47b59f7 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 5 Mar 2015 08:35:38 +0100 Subject: DT: video: atmel_lcdc: Add example of fixed framebuffer memory This drivers allows a fixed framebuffer memory to be set by an additional IORESOURCE_MEM resource. Thus add an example to the DT documentation. Signed-off-by: Alexander Stein Signed-off-by: Nicolas Ferre diff --git a/Documentation/devicetree/bindings/video/atmel,lcdc.txt b/Documentation/devicetree/bindings/video/atmel,lcdc.txt index f059dd0..ecb8da0 100644 --- a/Documentation/devicetree/bindings/video/atmel,lcdc.txt +++ b/Documentation/devicetree/bindings/video/atmel,lcdc.txt @@ -10,7 +10,9 @@ Required properties: "atmel,at91sam9g45es-lcdc" , "atmel,at91sam9rl-lcdc" , "atmel,at32ap-lcdc" -- reg : Should contain 1 register ranges(address and length) +- reg : Should contain 1 register ranges(address and length). + Can contain an additional register range(address and length) + for fixed framebuffer memory. Useful for dedicated memories. - interrupts : framebuffer controller interrupt - display: a phandle pointing to the display node @@ -38,6 +40,14 @@ Example: }; +Example for fixed framebuffer memory: + + fb0: fb@0x00500000 { + compatible = "atmel,at91sam9263-lcdc"; + reg = <0x00700000 0x1000 0x70000000 0x200000>; + [...] + }; + Atmel LCDC Display ----------------------------------------------------- Required properties (as per of_videomode_helper): -- cgit v0.10.2 From 5934973ddaf01beda9a0ce4f5efa7506ca8f8cb4 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 19 Mar 2015 17:23:13 +0100 Subject: ARM: at91/dt: at91sam9x5cm: enable RTC Enable RTC for all the at91sam9x5 CPU Modules: this will enable it for all the EK boards. Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi index 229d6c2..26112eb 100644 --- a/arch/arm/boot/dts/at91sam9x5cm.dtsi +++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi @@ -42,6 +42,10 @@ }; }; }; + + rtc@fffffeb0 { + status = "okay"; + }; }; nand0: nand@40000000 { -- cgit v0.10.2 From 87003229119ee1e18660d6be6209f44167ba6c6e Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 19 Mar 2015 17:41:41 +0100 Subject: ARM: at91/dt: at91sam9n12ek: enable RTC Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 6123109..6e067c8 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -137,6 +137,10 @@ watchdog@fffffe40 { status = "okay"; }; + + rtc@fffffeb0 { + status = "okay"; + }; }; nand0: nand@40000000 { -- cgit v0.10.2 From 42be876539299cab8cf7324db7332cd680fdd4b5 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Mon, 7 Jul 2014 18:31:49 +0200 Subject: ARM: at91/dt: split sama5d3 lcd pin definitions to match RGB mode configs The HLCDC (HLCD Controller) IP supports 4 different output mode (RGB444, RGB565, RGB666 and RGB888) and the pin muxing will depend on the chosen RGB mode. Split pin definitions to be able to set pin config according to the selected mode. Signed-off-by: Boris Brezillon Tested-by: Anthony Harivel Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi index 8aeff6c..9006e21 100644 --- a/arch/arm/boot/dts/sama5d3_lcd.dtsi +++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi @@ -15,38 +15,103 @@ apb { pinctrl@fffff200 { lcd { - pinctrl_lcd: lcd-0 { + pinctrl_lcd_base: lcd-base-0 { atmel,pins = - ; /* PE28 periph C LCDD23 pin */ + ; /* LCDPCK */ + }; + + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = ; /* LCDPWM */ + }; + + pinctrl_lcd_rgb444: lcd-rgb-0 { + atmel,pins = + ; /* LCDD11 pin */ + }; + + pinctrl_lcd_rgb565: lcd-rgb-1 { + atmel,pins = + ; /* LCDD15 pin */ + }; + + pinctrl_lcd_rgb666: lcd-rgb-2 { + atmel,pins = + ; /* LCDD17 pin */ + }; + + pinctrl_lcd_rgb888: lcd-rgb-3 { + atmel,pins = + ; /* LCDD23 pin */ }; }; }; -- cgit v0.10.2 From ee839fdd9ff14fc94e8092aa6f35572b6f760e09 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Fri, 4 Jul 2014 16:43:53 +0200 Subject: ARM: at91/dt: add alternative pin muxing for sama5d3 lcd pins Define alternative pin muxing for the LCDC pins. Signed-off-by: Boris Brezillon Tested-by: Anthony Harivel Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi index 9006e21..4903885 100644 --- a/arch/arm/boot/dts/sama5d3_lcd.dtsi +++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi @@ -82,6 +82,28 @@ AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ + AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD17 pin */ + }; + + pinctrl_lcd_rgb666_alt: lcd-rgb-2-alt { + atmel,pins = + ; /* LCDD17 pin */ }; @@ -104,6 +126,34 @@ AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ + AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ + AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ + AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ + AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ + AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ + }; + + pinctrl_lcd_rgb888_alt: lcd-rgb-3-alt { + atmel,pins = + Date: Mon, 7 Jul 2014 18:32:24 +0200 Subject: ARM: at91/dt: define the HLCDC node available on sama5d3 SoCs Define the HLCDC (HLCD Controller) IP available on some sama5d3 SoCs (i.e. sama5d31, sama5d33, sama5d34 and sama5d36) in sama5d3 dtsi file. Signed-off-by: Boris Brezillon Tested-by: Anthony Harivel Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi index 4903885..be7cfef 100644 --- a/arch/arm/boot/dts/sama5d3_lcd.dtsi +++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi @@ -13,6 +13,34 @@ / { ahb { apb { + hlcdc: hlcdc@f0030000 { + compatible = "atmel,sama5d3-hlcdc"; + reg = <0xf0030000 0x2000>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + pinctrl@fffff200 { lcd { pinctrl_lcd_base: lcd-base-0 { -- cgit v0.10.2 From f1ea096c78db038e947b6a5393467d4f065e1669 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 27 Nov 2013 15:30:05 +0100 Subject: ARM: at91/dt: sama5d3: add uart0 Signed-off-by: Nicolas Ferre Signed-off-by: Ludovic Desroches diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index e30fee2..1477e97 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -26,6 +26,7 @@ serial2 = &usart1; serial3 = &usart2; serial4 = &usart3; + serial5 = &uart0; gpio0 = &pioA; gpio1 = &pioB; gpio2 = &pioC; @@ -206,6 +207,17 @@ status = "disabled"; }; + uart0: serial@f0024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf0024000 0x100>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + pwm0: pwm@f002c000 { compatible = "atmel,sama5d3-pwm"; reg = <0xf002c000 0x300>; @@ -764,6 +776,14 @@ }; }; + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + ; /* conflicts with ISI_PCK */ + }; + }; + usart0 { pinctrl_usart0: usart0-0 { atmel,pins = @@ -1098,6 +1118,12 @@ atmel,clk-output-range = <0 66000000>; }; + uart0_clk: uart0_clk { + #clock-cells = <0>; + reg = <16>; + atmel,clk-output-range = <0 66000000>; + }; + twi0_clk: twi0_clk { reg = <18>; #clock-cells = <0>; -- cgit v0.10.2 From 3c309ab8fa896ba74959c8a0523aee6c25b3b80f Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 11 Feb 2015 17:49:02 +0100 Subject: ARM: at91/dt: sama5d3: add uart1 pinctrl definition Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 1477e97..7de02f1 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -784,6 +784,14 @@ }; }; + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + ; /* conflicts with TWCK0, ISI_HSYNC */ + }; + }; + usart0 { pinctrl_usart0: usart0-0 { atmel,pins = -- cgit v0.10.2 From c5900a9edf3e21595a012116ab738d4758ce9912 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Fri, 1 Aug 2014 09:42:18 +0200 Subject: ARM: at91/dt: sama5d4: add lcdc pin definitions Add LCDC pin definitions. Signed-off-by: Boris Brezillon Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 63eb7a2..3d91ca3 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -1358,6 +1358,101 @@ }; }; + lcd { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + ; /* LCDPCK */ + }; + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = ; /* LCDPWM */ + }; + pinctrl_lcd_rgb444: lcd-rgb-0 { + atmel,pins = + ; /* LCDD11 pin */ + }; + pinctrl_lcd_rgb565: lcd-rgb-1 { + atmel,pins = + ; /* LCDD15 pin */ + }; + pinctrl_lcd_rgb666: lcd-rgb-2 { + atmel,pins = + ; /* LCDD17 pin */ + }; + pinctrl_lcd_rgb888: lcd-rgb-3 { + atmel,pins = + ; /* LCDD23 pin */ + }; + }; + macb0 { pinctrl_macb0_rmii: macb0_rmii-0 { atmel,pins = -- cgit v0.10.2 From 7e60dd30656771ed7f33aae796f791586a1fb356 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Fri, 1 Aug 2014 09:43:11 +0200 Subject: ARM: at91/dt: sama5d4: add hlcdc node Add HLCDC node. Signed-off-by: Boris Brezillon Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 3d91ca3..f525e7b 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -314,6 +314,34 @@ #size-cells = <1>; ranges; + hlcdc: hlcdc@f0000000 { + compatible = "atmel,sama5d4-hlcdc"; + reg = <0xf0000000 0x4000>; + interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + dma1: dma-controller@f0004000 { compatible = "atmel,sama5d4-dma"; reg = <0xf0004000 0x200>; -- cgit v0.10.2 From e9b93cf5d1dd8c37a82007fca6e54bff83eb503c Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Fri, 20 Feb 2015 15:07:18 +0100 Subject: ARM: at91/dt: sama5d4: fix LCD pins for RGB666 format The color arrangement for SAMA5D4 in RGB 666 takes the most significant bits of each color line groups. Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index f525e7b..7847e9a 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -1433,24 +1433,24 @@ }; pinctrl_lcd_rgb666: lcd-rgb-2 { atmel,pins = - ; /* LCDD17 pin */ + AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ + AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ + AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ + AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ }; pinctrl_lcd_rgb888: lcd-rgb-3 { atmel,pins = -- cgit v0.10.2 From 3c42ae3645a7fd2605453de9947629fb7b26c95f Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 25 Feb 2015 19:04:05 +0100 Subject: ARM: at91/dt: sama5d4: add rgb777 LCD line configuration For the SAMA5D4 SoC, some LCD lines are in conflict with useful peripherals. Remove these lines and the lowest significant bit of a 24 bit LCD. It gives us a RGB 777 configuration. Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 7847e9a..5cccbc9 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -1452,7 +1452,34 @@ AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ }; - pinctrl_lcd_rgb888: lcd-rgb-3 { + pinctrl_lcd_rgb777: lcd-rgb-3 { + atmel,pins = + /* LCDDAT0 conflicts with TMS */ + ; /* LCDD23 pin */ + }; + pinctrl_lcd_rgb888: lcd-rgb-4 { atmel,pins = Date: Tue, 17 Feb 2015 11:57:45 -0700 Subject: ARM: tegra: Import latest Jetson TK1 pinmux syseng has revamped the Jetson TK1 pinmux spreadsheet, basing the content completely on correct configuration for the board/schematic, rather than the previous version which was based on the bare minimum changes relative to another reference board. This content comes from Jetson_TK1_customer_pinmux.xlsm (v09) downloaded from https://developer.nvidia.com/hardware-design-and-development. Signed-off-by: Stephen Warren Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index dbfaba0..528768a 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -60,35 +60,35 @@ nvidia,pins = "clk_32k_out_pa0"; nvidia,function = "soc"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; uart3_cts_n_pa1 { nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap2_fs_pa2 { nvidia,pins = "dap2_fs_pa2"; nvidia,function = "i2s1"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; dap2_sclk_pa3 { nvidia,pins = "dap2_sclk_pa3"; nvidia,function = "i2s1"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; dap2_din_pa4 { nvidia,pins = "dap2_din_pa4"; nvidia,function = "i2s1"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; dap2_dout_pa5 { @@ -96,14 +96,14 @@ nvidia,function = "i2s1"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; sdmmc3_clk_pa6 { nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; sdmmc3_cmd_pa7 { nvidia,pins = "sdmmc3_cmd_pa7"; @@ -116,14 +116,14 @@ nvidia,pins = "pb0"; nvidia,function = "uartd"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pb1 { nvidia,pins = "pb1"; nvidia,function = "uartd"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; sdmmc3_dat3_pb4 { @@ -156,9 +156,9 @@ }; uart3_rts_n_pc0 { nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; uart2_txd_pc2 { @@ -172,7 +172,7 @@ nvidia,pins = "uart2_rxd_pc3"; nvidia,function = "irda"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; gen1_i2c_scl_pc4 { @@ -194,44 +194,39 @@ pc7 { nvidia,pins = "pc7"; nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pg0 { nvidia,pins = "pg0"; - nvidia,function = "rsvd1"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pg1 { nvidia,pins = "pg1"; - nvidia,function = "rsvd1"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pg2 { nvidia,pins = "pg2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pg3 { nvidia,pins = "pg3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pg4 { nvidia,pins = "pg4"; - nvidia,function = "spi4"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pg5 { nvidia,pins = "pg5"; @@ -251,7 +246,7 @@ nvidia,pins = "pg7"; nvidia,function = "spi4"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; ph0 { @@ -270,7 +265,6 @@ }; ph2 { nvidia,pins = "ph2"; - nvidia,function = "gmi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -278,57 +272,53 @@ ph3 { nvidia,pins = "ph3"; nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; ph4 { nvidia,pins = "ph4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; ph5 { nvidia,pins = "ph5"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; ph6 { nvidia,pins = "ph6"; nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; ph7 { nvidia,pins = "ph7"; - nvidia,function = "gmi"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; pi0 { nvidia,pins = "pi0"; - nvidia,function = "rsvd1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pi1 { nvidia,pins = "pi1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; pi2 { nvidia,pins = "pi2"; nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pi3 { @@ -341,22 +331,21 @@ pi4 { nvidia,pins = "pi4"; nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pi5 { nvidia,pins = "pi5"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pi6 { nvidia,pins = "pi6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pi7 { @@ -368,23 +357,22 @@ }; pj0 { nvidia,pins = "pj0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pj2 { nvidia,pins = "pj2"; nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; uart2_cts_n_pj5 { nvidia,pins = "uart2_cts_n_pj5"; nvidia,function = "uartb"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; uart2_rts_n_pj6 { @@ -403,35 +391,32 @@ }; pk0 { nvidia,pins = "pk0"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pk1 { nvidia,pins = "pk1"; - nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pk2 { nvidia,pins = "pk2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pk3 { nvidia,pins = "pk3"; nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pk4 { nvidia,pins = "pk4"; - nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -439,13 +424,12 @@ spdif_out_pk5 { nvidia,pins = "spdif_out_pk5"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; spdif_in_pk6 { nvidia,pins = "spdif_in_pk6"; - nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -459,17 +443,17 @@ }; dap1_fs_pn0 { nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "i2s0"; + nvidia,function = "rsvd4"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap1_din_pn1 { nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; + nvidia,function = "rsvd4"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap1_dout_pn2 { nvidia,pins = "dap1_dout_pn2"; @@ -480,108 +464,104 @@ }; dap1_sclk_pn3 { nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "i2s0"; + nvidia,function = "rsvd4"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; usb_vbus_en0_pn4 { nvidia,pins = "usb_vbus_en0_pn4"; nvidia,function = "usb"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,open-drain = ; + nvidia,open-drain = ; }; usb_vbus_en1_pn5 { nvidia,pins = "usb_vbus_en1_pn5"; nvidia,function = "usb"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,open-drain = ; + nvidia,open-drain = ; }; hdmi_int_pn7 { nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; nvidia,rcv-sel = ; }; ulpi_data7_po0 { nvidia,pins = "ulpi_data7_po0"; nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; ulpi_data0_po1 { nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; ulpi_data1_po2 { nvidia,pins = "ulpi_data1_po2"; nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; ulpi_data2_po3 { nvidia,pins = "ulpi_data2_po3"; nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; ulpi_data3_po4 { nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; ulpi_data4_po5 { nvidia,pins = "ulpi_data4_po5"; nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; ulpi_data5_po6 { nvidia,pins = "ulpi_data5_po6"; nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; ulpi_data6_po7 { nvidia,pins = "ulpi_data6_po7"; nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap3_fs_pp0 { nvidia,pins = "dap3_fs_pp0"; nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; dap3_din_pp1 { nvidia,pins = "dap3_din_pp1"; nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; dap3_dout_pp2 { nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -595,91 +575,87 @@ }; dap4_fs_pp4 { nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "i2s3"; + nvidia,function = "rsvd4"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap4_din_pp5 { nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; + nvidia,function = "rsvd3"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap4_dout_pp6 { nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "i2s3"; + nvidia,function = "rsvd4"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap4_sclk_pp7 { nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "i2s3"; + nvidia,function = "rsvd3"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_col0_pq0 { nvidia,pins = "kb_col0_pq0"; - nvidia,function = "rsvd2"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_col1_pq1 { nvidia,pins = "kb_col1_pq1"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_col2_pq2 { nvidia,pins = "kb_col2_pq2"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_col3_pq3 { nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; kb_col4_pq4 { nvidia,pins = "kb_col4_pq4"; nvidia,function = "sdmmc3"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_col5_pq5 { nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_col6_pq6 { nvidia,pins = "kb_col6_pq6"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_col7_pq7 { nvidia,pins = "kb_col7_pq7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_row0_pr0 { nvidia,pins = "kb_row0_pr0"; - nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -687,121 +663,115 @@ kb_row1_pr1 { nvidia,pins = "kb_row1_pr1"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row2_pr2 { nvidia,pins = "kb_row2_pr2"; - nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; kb_row3_pr3 { nvidia,pins = "kb_row3_pr3"; - nvidia,function = "sys"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row4_pr4 { nvidia,pins = "kb_row4_pr4"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row5_pr5 { nvidia,pins = "kb_row5_pr5"; nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row6_pr6 { nvidia,pins = "kb_row6_pr6"; nvidia,function = "displaya_alt"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row7_pr7 { nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row8_ps0 { nvidia,pins = "kb_row8_ps0"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_row9_ps1 { nvidia,pins = "kb_row9_ps1"; - nvidia,function = "rsvd2"; + nvidia,function = "uarta"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; kb_row10_ps2 { nvidia,pins = "kb_row10_ps2"; - nvidia,function = "rsvd2"; + nvidia,function = "uarta"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row11_ps3 { nvidia,pins = "kb_row11_ps3"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row12_ps4 { nvidia,pins = "kb_row12_ps4"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row13_ps5 { nvidia,pins = "kb_row13_ps5"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_row14_ps6 { nvidia,pins = "kb_row14_ps6"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row15_ps7 { nvidia,pins = "kb_row15_ps7"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; kb_row16_pt0 { nvidia,pins = "kb_row16_pt0"; - nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; kb_row17_pt1 { nvidia,pins = "kb_row17_pt1"; - nvidia,function = "rsvd2"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gen2_i2c_scl_pt5 { nvidia,pins = "gen2_i2c_scl_pt5"; @@ -828,72 +798,63 @@ }; pu0 { nvidia,pins = "pu0"; - nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; pu1 { nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pu2 { nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pu3 { nvidia,pins = "pu3"; - nvidia,function = "gmi"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; pu4 { nvidia,pins = "pu4"; - nvidia,function = "gmi"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; pu5 { nvidia,pins = "pu5"; - nvidia,function = "gmi"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pu6 { nvidia,pins = "pu6"; - nvidia,function = "rsvd3"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pv0 { nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pv1 { nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; sdmmc3_cd_n_pv2 { nvidia,pins = "sdmmc3_cd_n_pv2"; nvidia,function = "sdmmc3"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; sdmmc1_wp_n_pv3 { @@ -922,16 +883,16 @@ gpio_w2_aud_pw2 { nvidia,pins = "gpio_w2_aud_pw2"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gpio_w3_aud_pw3 { nvidia,pins = "gpio_w3_aud_pw3"; nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap_mclk1_pw4 { nvidia,pins = "dap_mclk1_pw4"; @@ -949,17 +910,17 @@ }; uart3_txd_pw6 { nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; uart3_rxd_pw7 { nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dvfs_pwm_px0 { nvidia,pins = "dvfs_pwm_px0"; @@ -970,10 +931,9 @@ }; gpio_x1_aud_px1 { nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd2"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dvfs_clk_px2 { nvidia,pins = "dvfs_clk_px2"; @@ -985,34 +945,32 @@ gpio_x3_aud_px3 { nvidia,pins = "gpio_x3_aud_px3"; nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gpio_x4_aud_px4 { nvidia,pins = "gpio_x4_aud_px4"; - nvidia,function = "gmi"; nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gpio_x5_aud_px5 { nvidia,pins = "gpio_x5_aud_px5"; nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gpio_x6_aud_px6 { nvidia,pins = "gpio_x6_aud_px6"; nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gpio_x7_aud_px7 { nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "rsvd1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1027,8 +985,8 @@ ulpi_dir_py1 { nvidia,pins = "ulpi_dir_py1"; nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; ulpi_nxt_py2 { @@ -1048,44 +1006,44 @@ sdmmc1_dat3_py4 { nvidia,pins = "sdmmc1_dat3_py4"; nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc1_dat2_py5 { nvidia,pins = "sdmmc1_dat2_py5"; nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc1_dat1_py6 { nvidia,pins = "sdmmc1_dat1_py6"; nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc1_dat0_py7 { nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc1_clk_pz0 { nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc1_cmd_pz1 { nvidia,pins = "sdmmc1_cmd_pz1"; nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pwr_i2c_scl_pz6 { nvidia,pins = "pwr_i2c_scl_pz6"; @@ -1184,7 +1142,6 @@ }; pbb3 { nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1198,21 +1155,18 @@ }; pbb5 { nvidia,pins = "pbb5"; - nvidia,function = "rsvd3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pbb6 { nvidia,pins = "pbb6"; - nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pbb7 { nvidia,pins = "pbb7"; - nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1226,15 +1180,13 @@ }; pcc1 { nvidia,pins = "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; pcc2 { nvidia,pins = "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; @@ -1248,8 +1200,8 @@ clk2_req_pcc5 { nvidia,pins = "clk2_req_pcc5"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pex_l0_rst_n_pdd1 { @@ -1262,15 +1214,15 @@ pex_l0_clkreq_n_pdd2 { nvidia,pins = "pex_l0_clkreq_n_pdd2"; nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pex_wake_n_pdd3 { nvidia,pins = "pex_wake_n_pdd3"; nvidia,function = "pe"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; pex_l1_rst_n_pdd5 { @@ -1283,8 +1235,8 @@ pex_l1_clkreq_n_pdd6 { nvidia,pins = "pex_l1_clkreq_n_pdd6"; nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; clk3_out_pee0 { @@ -1297,13 +1249,12 @@ clk3_req_pee1 { nvidia,pins = "clk3_req_pee1"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; dap_mclk1_req_pee2 { nvidia,pins = "dap_mclk1_req_pee2"; - nvidia,function = "sata"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1314,7 +1265,7 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,open-drain = ; + nvidia,open-drain = ; }; sdmmc3_clk_lb_out_pee4 { nvidia,pins = "sdmmc3_clk_lb_out_pee4"; @@ -1333,24 +1284,24 @@ dp_hpd_pff0 { nvidia,pins = "dp_hpd_pff0"; nvidia,function = "dp"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; usb_vbus_en2_pff1 { nvidia,pins = "usb_vbus_en2_pff1"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; }; pff2 { nvidia,pins = "pff2"; nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; nvidia,open-drain = ; }; core_pwr_req { @@ -1362,7 +1313,7 @@ }; cpu_pwr_req { nvidia,pins = "cpu_pwr_req"; - nvidia,function = "rsvd2"; + nvidia,function = "cpu"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1371,7 +1322,7 @@ nvidia,pins = "pwr_int_n"; nvidia,function = "pmi"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; reset_out_n { @@ -1379,7 +1330,7 @@ nvidia,function = "reset_out_n"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; owr { nvidia,pins = "owr"; @@ -1391,9 +1342,9 @@ }; clk_32k_in { nvidia,pins = "clk_32k_in"; - nvidia,function = "rsvd2"; + nvidia,function = "clk"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; jtag_rtck { -- cgit v0.10.2 From 3d03203a323b629866e732672237fbb8074d1df6 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 5 Jan 2015 22:57:46 +0100 Subject: ARM: tegra: Use generated pinmux for Beaver board Replace the current incomplete pinmux setup with a proper one generated using the tegra pinmux scripts. Signed-off-by: Lucas Stach Acked-by: Stephen Warren Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 6b157ee..3dede39 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -62,71 +62,1652 @@ pinctrl-0 = <&state_default>; state_default: pinmux { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pclk_pb3 { + nvidia,pins = "lcd_pclk_pb3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pwr1_pc1 { + nvidia,pins = "lcd_pwr1_pc1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat5_pd0 { + nvidia,pins = "sdmmc3_dat5_pd0"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat4_pd1 { + nvidia,pins = "sdmmc3_dat4_pd1"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat6_pd3 { + nvidia,pins = "sdmmc3_dat6_pd3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat7_pd4 { + nvidia,pins = "sdmmc3_dat7_pd4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_hsync_pd7 { + nvidia,pins = "vi_hsync_pd7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d0_pe0 { + nvidia,pins = "lcd_d0_pe0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d1_pe1 { + nvidia,pins = "lcd_d1_pe1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d2_pe2 { + nvidia,pins = "lcd_d2_pe2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d3_pe3 { + nvidia,pins = "lcd_d3_pe3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d4_pe4 { + nvidia,pins = "lcd_d4_pe4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d5_pe5 { + nvidia,pins = "lcd_d5_pe5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d6_pe6 { + nvidia,pins = "lcd_d6_pe6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d7_pe7 { + nvidia,pins = "lcd_d7_pe7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d8_pf0 { + nvidia,pins = "lcd_d8_pf0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d9_pf1 { + nvidia,pins = "lcd_d9_pf1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d10_pf2 { + nvidia,pins = "lcd_d10_pf2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d11_pf3 { + nvidia,pins = "lcd_d11_pf3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d12_pf4 { + nvidia,pins = "lcd_d12_pf4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d13_pf5 { + nvidia,pins = "lcd_d13_pf5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d14_pf6 { + nvidia,pins = "lcd_d14_pf6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d15_pf7 { + nvidia,pins = "lcd_d15_pf7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad1_pg1 { + nvidia,pins = "gmi_ad1_pg1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad3_pg3 { + nvidia,pins = "gmi_ad3_pg3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad4_pg4 { + nvidia,pins = "gmi_ad4_pg4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad5_pg5 { + nvidia,pins = "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad6_pg6 { + nvidia,pins = "gmi_ad6_pg6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad7_pg7 { + nvidia,pins = "gmi_ad7_pg7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad11_ph3 { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad14_ph6 { + nvidia,pins = "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_wr_n_pi0 { + nvidia,pins = "gmi_wr_n_pi0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_oe_n_pi1 { + nvidia,pins = "gmi_oe_n_pi1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_dqs_pi2 { + nvidia,pins = "gmi_dqs_pi2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs7_n_pi6 { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_wait_pi7 { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_de_pj1 { + nvidia,pins = "lcd_de_pj1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_hsync_pj3 { + nvidia,pins = "lcd_hsync_pj3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_vsync_pj4 { + nvidia,pins = "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_adv_n_pk0 { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_clk_pk1 { + nvidia,pins = "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs2_n_pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d2_pl0 { + nvidia,pins = "vi_d2_pl0"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d3_pl1 { + nvidia,pins = "vi_d3_pl1"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d5_pl3 { + nvidia,pins = "vi_d5_pl3"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d7_pl5 { + nvidia,pins = "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d9_pl7 { + nvidia,pins = "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d16_pm0 { + nvidia,pins = "lcd_d16_pm0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d17_pm1 { + nvidia,pins = "lcd_d17_pm1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d18_pm2 { + nvidia,pins = "lcd_d18_pm2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d19_pm3 { + nvidia,pins = "lcd_d19_pm3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d20_pm4 { + nvidia,pins = "lcd_d20_pm4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d21_pm5 { + nvidia,pins = "lcd_d21_pm5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d22_pm6 { + nvidia,pins = "lcd_d22_pm6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d23_pm7 { + nvidia,pins = "lcd_d23_pm7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_sdout_pn5 { + nvidia,pins = "lcd_sdout_pn5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_dc0_pn6 { + nvidia,pins = "lcd_dc0_pn6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d11_pt3 { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d0_pt4 { + nvidia,pins = "vi_d0_pt4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + crt_vsync_pv7 { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_cs1_n_pw0 { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_m1_pw1 { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_cs0_n_px6 { + nvidia,pins = "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; sdmmc1_clk_pz0 { nvidia,pins = "sdmmc1_clk_pz0"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; + nvidia,pins = "sdmmc1_cmd_pz1"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; + lcd_sdin_pz2 { + nvidia,pins = "lcd_sdin_pz2"; + nvidia,function = "displaya"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; + lcd_wr_n_pz3 { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; + lcd_sck_pz4 { + nvidia,pins = "lcd_sck_pz4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; }; sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; + nvidia,pins = "sdmmc4_dat0_paa0"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5"; - nvidia,function = "i2s1"; + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l2_clkreq_n_pcc7 { + nvidia,pins = "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_prsnt_n_pdd0 { + nvidia,pins = "pex_l0_prsnt_n_pdd0"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "pcie"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pex_l1_prsnt_n_pdd4 { - nvidia,pins = "pex_l1_prsnt_n_pdd4", - "pex_l1_clkreq_n_pdd6"; + nvidia,pins = "pex_l1_prsnt_n_pdd4"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "pcie"; nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l2_prsnt_n_pdd7 { + nvidia,pins = "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdio3 { nvidia,pins = "drive_sdio3"; -- cgit v0.10.2 From 412e575dec93b91a2a1ee30ee47b7ddb742679a0 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Wed, 18 Mar 2015 10:52:16 +0100 Subject: ARM: tegra: Change model of sound card in Nyan Big Change it from "Acer Chromebook 13" to GoogleNyanBig so it's unique and identifiable. With this change the card id exposed to userspace becomes GoogleNyanBig instead of the current A13. Signed-off-by: Tomeu Vizoso Acked-by: Stephen Warren Reviewed-by: Alexandre Courbot Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts index 004e8e4..e167df2 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big.dts +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -1110,7 +1110,7 @@ sound { compatible = "nvidia,tegra-audio-max98090-nyan-big", "nvidia,tegra-audio-max98090"; - nvidia,model = "Acer Chromebook 13"; + nvidia,model = "GoogleNyanBig"; nvidia,audio-routing = "Headphones", "HPR", -- cgit v0.10.2 From 53d02858bce5eadd3882dcb83441b01d3511f486 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Wed, 18 Mar 2015 10:52:17 +0100 Subject: ARM: tegra: Move generic parts out of the nyan-big DT In preparation for adding the DT for the nyan-blaze board. Signed-off-by: Tomeu Vizoso Acked-by: Stephen Warren Reviewed-by: Alexandre Courbot Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts index e167df2..3995630 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big.dts +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -1,46 +1,27 @@ /dts-v1/; -#include -#include "tegra124.dtsi" +#include "tegra124-nyan.dtsi" / { model = "Acer Chromebook 13 CB5-311"; compatible = "google,nyan-big", "nvidia,tegra124"; - aliases { - rtc0 = "/i2c@0,7000d000/pmic@40"; - rtc1 = "/rtc@0,7000e000"; - serial0 = &uarta; - }; + panel: panel { + compatible = "auo,b133xtn01"; - memory { - reg = <0x0 0x80000000 0x0 0x80000000>; + backlight = <&backlight>; + ddc-i2c-bus = <&dpaux>; }; - host1x@0,50000000 { - hdmi@0,54280000 { - status = "okay"; - - vdd-supply = <&vdd_3v3_hdmi>; - pll-supply = <&vdd_hdmi_pll>; - hdmi-supply = <&vdd_5v0_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - - sor@0,54540000 { - status = "okay"; - - nvidia,dpaux = <&dpaux>; - nvidia,panel = <&panel>; - }; + sdhci@0,700b0400 { /* SD Card on this bus */ + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + }; - dpaux@0,545c0000 { - vdd-supply = <&vdd_3v3_panel>; - status = "okay"; - }; + sound { + compatible = "nvidia,tegra-audio-max98090-nyan-big", + "nvidia,tegra-audio-max98090-nyan", + "nvidia,tegra-audio-max98090"; + nvidia,model = "GoogleNyanBig"; }; pinmux@0,70000868 { @@ -492,648 +473,4 @@ }; }; }; - - serial@0,70006000 { - /* Debug connector on the bottom of the board near SD card. */ - status = "okay"; - }; - - pwm@0,7000a000 { - status = "okay"; - }; - - i2c@0,7000c000 { - status = "okay"; - clock-frequency = <100000>; - - acodec: audio-codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - interrupt-parent = <&gpio>; - interrupts = ; - - #thermal-sensor-cells = <1>; - }; - }; - - i2c@0,7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@0,7000c500 { - status = "okay"; - clock-frequency = <400000>; - - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - }; - }; - - hdmi_ddc: i2c@0,7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@0,7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - - ams,system-power-controller; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - bias-pull-down; - }; - - gpio1 { - pins = "gpio1"; - function = "gpio"; - bias-pull-up; - }; - - gpio2_4_7 { - pins = "gpio2", "gpio4", "gpio7"; - function = "gpio"; - bias-pull-up; - }; - - gpio3_6 { - pins = "gpio3", "gpio6"; - bias-high-impedance; - }; - - gpio5 { - pins = "gpio5"; - function = "clk32k-out"; - bias-pull-down; - }; - }; - - regulators { - vsup-sd2-supply = <&vdd_5v0_sys>; - vsup-sd3-supply = <&vdd_5v0_sys>; - vsup-sd4-supply = <&vdd_5v0_sys>; - vsup-sd5-supply = <&vdd_5v0_sys>; - vin-ldo0-supply = <&vdd_1v35_lp0>; - vin-ldo1-6-supply = <&vdd_3v3_run>; - vin-ldo2-5-7-supply = <&vddio_1v8>; - vin-ldo3-4-supply = <&vdd_3v3_sys>; - vin-ldo9-10-supply = <&vdd_5v0_sys>; - vin-ldo11-supply = <&vdd_3v3_run>; - - sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <4000000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - vdd_1v35_lp0: sd2 { - regulator-name = "+1.35V_LP0(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = "+1.35V_LP0(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v05_run: sd4 { - regulator-name = "+1.05V_RUN"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddio_1v8: sd5 { - regulator-name = "+1.8V_VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo0 { - regulator-name = "+1.05V_RUN_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; - ams,ext-control = <1>; - }; - - ldo1 { - regulator-name = "+1.8V_RUN_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2 { - regulator-name = "+1.2V_GEN_AVDD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3 { - regulator-name = "+1.00V_LP0_VDD_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - ams,enable-tracking; - }; - - vdd_run_cam: ldo4 { - regulator-name = "+3.3V_RUN_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5 { - regulator-name = "+1.2V_RUN_CAM_FRONT"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vddio_sdmmc3: ldo6 { - regulator-name = "+VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "+1.05V_RUN_CAM_REAR"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo9 { - regulator-name = "+2.8V_RUN_TOUCH"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10 { - regulator-name = "+2.8V_RUN_CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo11 { - regulator-name = "+1.8V_RUN_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - }; - - spi@0,7000d400 { - status = "okay"; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - spi-max-frequency = <3000000>; - interrupt-parent = <&gpio>; - interrupts = ; - reg = <0>; - - google,cros-ec-spi-msg-delay = <2000>; - - i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - - google,remote-bus = <0>; - - charger: bq24735@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - interrupt-parent = <&gpio>; - interrupts = ; - ti,ac-detect-gpios = <&gpio - TEGRA_GPIO(J, 0) - GPIO_ACTIVE_HIGH>; - }; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <10>; - power-supplies = <&charger>; - }; - }; - }; - }; - - spi@0,7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - - flash@0 { - compatible = "winbond,w25q32dw"; - reg = <0>; - }; - }; - - pmc@0,7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - hda@0,70030000 { - status = "okay"; - }; - - sdhci@0,700b0000 { /* WiFi/BT on this bus */ - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - no-1-8-v; - non-removable; - }; - - sdhci@0,700b0400 { /* SD Card on this bus */ - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - bus-width = <4>; - no-1-8-v; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - sdhci@0,700b0600 { /* eMMC on this bus */ - status = "okay"; - bus-width = <8>; - no-1-8-v; - non-removable; - }; - - ahub@0,70300000 { - i2s@0,70301100 { - status = "okay"; - }; - }; - - usb@0,7d000000 { /* Rear external USB port. */ - status = "okay"; - }; - - usb-phy@0,7d000000 { - status = "okay"; - vbus-supply = <&vdd_usb1_vbus>; - }; - - usb@0,7d004000 { /* Internal webcam. */ - status = "okay"; - }; - - usb-phy@0,7d004000 { - status = "okay"; - vbus-supply = <&vdd_run_cam>; - }; - - usb@0,7d008000 { /* Left external USB port. */ - status = "okay"; - }; - - usb-phy@0,7d008000 { - status = "okay"; - vbus-supply = <&vdd_usb3_vbus>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_led>; - pwms = <&pwm 1 1000000>; - - default-brightness-level = <224>; - brightness-levels = - < 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - 256>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - lid { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; - linux,input-type = <5>; - linux,code = ; - debounce-interval = <1>; - gpio-key,wakeup; - }; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <30>; - gpio-key,wakeup; - }; - }; - - panel: panel { - compatible = "auo,b133xtn01"; - - backlight = <&backlight>; - ddc-i2c-bus = <&dpaux>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_led: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "+VDD_LED"; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; - - vdd_5v0_ts: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "+5V_VDD_TS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb3_vbus: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+5V_USB_SS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_3v3_panel: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "+3.3V_PANEL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_3v3_lp0: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * TODO: find a way to wire this up with the USB EHCI - * controllers so that it can be enabled on demand. - */ - regulator-always-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi_pll: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; - - vdd_5v0_hdmi: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-max98090-nyan-big", - "nvidia,tegra-audio-max98090"; - nvidia,model = "GoogleNyanBig"; - - nvidia,audio-routing = - "Headphones", "HPR", - "Headphones", "HPL", - "Speakers", "SPKR", - "Speakers", "SPKL", - "Mic Jack", "MICBIAS", - "DMICL", "Int Mic", - "DMICR", "Int Mic", - "IN34", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&acodec>; - - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; - nvidia,mic-det-gpios = - <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; - }; }; - -#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi new file mode 100644 index 0000000..c0ee53f --- /dev/null +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -0,0 +1,672 @@ +#include +#include "tegra124.dtsi" + +/ { + aliases { + rtc0 = "/i2c@0,7000d000/pmic@40"; + rtc1 = "/rtc@0,7000e000"; + serial0 = &uarta; + }; + + memory { + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + host1x@0,50000000 { + hdmi@0,54280000 { + status = "okay"; + + vdd-supply = <&vdd_3v3_hdmi>; + pll-supply = <&vdd_hdmi_pll>; + hdmi-supply = <&vdd_5v0_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + + sor@0,54540000 { + status = "okay"; + + nvidia,dpaux = <&dpaux>; + nvidia,panel = <&panel>; + }; + + dpaux@0,545c0000 { + vdd-supply = <&vdd_3v3_panel>; + status = "okay"; + }; + }; + + serial@0,70006000 { + /* Debug connector on the bottom of the board near SD card. */ + status = "okay"; + }; + + pwm@0,7000a000 { + status = "okay"; + }; + + i2c@0,7000c000 { + status = "okay"; + clock-frequency = <100000>; + + acodec: audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpio>; + interrupts = ; + }; + + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + }; + + i2c@0,7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@0,7000c500 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; + }; + + hdmi_ddc: i2c@0,7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + ams,system-power-controller; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + bias-pull-down; + }; + + gpio1 { + pins = "gpio1"; + function = "gpio"; + bias-pull-up; + }; + + gpio2_4_7 { + pins = "gpio2", "gpio4", "gpio7"; + function = "gpio"; + bias-pull-up; + }; + + gpio3_6 { + pins = "gpio3", "gpio6"; + bias-high-impedance; + }; + + gpio5 { + pins = "gpio5"; + function = "clk32k-out"; + bias-pull-down; + }; + }; + + regulators { + vsup-sd2-supply = <&vdd_5v0_sys>; + vsup-sd3-supply = <&vdd_5v0_sys>; + vsup-sd4-supply = <&vdd_5v0_sys>; + vsup-sd5-supply = <&vdd_5v0_sys>; + vin-ldo0-supply = <&vdd_1v35_lp0>; + vin-ldo1-6-supply = <&vdd_3v3_run>; + vin-ldo2-5-7-supply = <&vddio_1v8>; + vin-ldo3-4-supply = <&vdd_3v3_sys>; + vin-ldo9-10-supply = <&vdd_5v0_sys>; + vin-ldo11-supply = <&vdd_3v3_run>; + + sd0 { + regulator-name = "+VDD_CPU_AP"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <2>; + }; + + sd1 { + regulator-name = "+VDD_CORE"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <4000000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <1>; + }; + + vdd_1v35_lp0: sd2 { + regulator-name = "+1.35V_LP0(sd2)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = "+1.35V_LP0(sd3)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v05_run: sd4 { + regulator-name = "+1.05V_RUN"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddio_1v8: sd5 { + regulator-name = "+1.8V_VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + sd6 { + regulator-name = "+VDD_GPU_AP"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo0 { + regulator-name = "+1.05V_RUN_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,ext-control = <1>; + }; + + ldo1 { + regulator-name = "+1.8V_RUN_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2 { + regulator-name = "+1.2V_GEN_AVDD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "+1.00V_LP0_VDD_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + vdd_run_cam: ldo4 { + regulator-name = "+3.3V_RUN_CAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo5 { + regulator-name = "+1.2V_RUN_CAM_FRONT"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vddio_sdmmc3: ldo6 { + regulator-name = "+VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "+1.05V_RUN_CAM_REAR"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo9 { + regulator-name = "+2.8V_RUN_TOUCH"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo10 { + regulator-name = "+2.8V_RUN_CAM_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo11 { + regulator-name = "+1.8V_RUN_VPP_FUSE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; + + spi@0,7000d400 { + status = "okay"; + + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; + spi-max-frequency = <3000000>; + interrupt-parent = <&gpio>; + interrupts = ; + reg = <0>; + + google,cros-ec-spi-msg-delay = <2000>; + + i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + + google,remote-bus = <0>; + + charger: bq24735@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + interrupt-parent = <&gpio>; + interrupts = ; + ti,ac-detect-gpios = <&gpio + TEGRA_GPIO(J, 0) + GPIO_ACTIVE_HIGH>; + }; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + power-supplies = <&charger>; + }; + }; + }; + }; + + spi@0,7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + flash@0 { + compatible = "winbond,w25q32dw"; + reg = <0>; + }; + }; + + pmc@0,7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + hda@0,70030000 { + status = "okay"; + }; + + sdhci@0,700b0000 { /* WiFi/BT on this bus */ + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + no-1-8-v; + non-removable; + }; + + sdhci@0,700b0400 { /* SD Card on this bus */ + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + no-1-8-v; + vqmmc-supply = <&vddio_sdmmc3>; + }; + + sdhci@0,700b0600 { /* eMMC on this bus */ + status = "okay"; + bus-width = <8>; + no-1-8-v; + non-removable; + }; + + ahub@0,70300000 { + i2s@0,70301100 { + status = "okay"; + }; + }; + + usb@0,7d000000 { /* Rear external USB port. */ + status = "okay"; + }; + + usb-phy@0,7d000000 { + status = "okay"; + vbus-supply = <&vdd_usb1_vbus>; + }; + + usb@0,7d004000 { /* Internal webcam. */ + status = "okay"; + }; + + usb-phy@0,7d004000 { + status = "okay"; + vbus-supply = <&vdd_run_cam>; + }; + + usb@0,7d008000 { /* Left external USB port. */ + status = "okay"; + }; + + usb-phy@0,7d008000 { + status = "okay"; + vbus-supply = <&vdd_usb3_vbus>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_led>; + pwms = <&pwm 1 1000000>; + + default-brightness-level = <224>; + brightness-levels = + < 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + 256>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + lid { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; + linux,input-type = <5>; + linux,code = ; + debounce-interval = <1>; + gpio-key,wakeup; + }; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <30>; + gpio-key,wakeup; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_mux: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_run: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_hdmi: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_led: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "+VDD_LED"; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; + + vdd_5v0_ts: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "+5V_VDD_TS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb1_vbus: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb3_vbus: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "+5V_USB_SS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_3v3_panel: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "+3.3V_PANEL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_3v3_lp0: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* + * TODO: find a way to wire this up with the USB EHCI + * controllers so that it can be enabled on demand. + */ + regulator-always-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_hdmi_pll: regulator@11 { + compatible = "regulator-fixed"; + reg = <11>; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; + + vdd_5v0_hdmi: regulator@12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + }; + + sound { + nvidia,audio-routing = + "Headphones", "HPR", + "Headphones", "HPL", + "Speakers", "SPKR", + "Speakers", "SPKL", + "Mic Jack", "MICBIAS", + "DMICL", "Int Mic", + "DMICR", "Int Mic", + "IN34", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&acodec>; + + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; + nvidia,mic-det-gpios = + <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; + }; +}; + +#include "cros-ec-keyboard.dtsi" -- cgit v0.10.2 From 59fe02cb079f2a521cf25724c9194e3db6a52bfe Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Wed, 18 Mar 2015 10:52:19 +0100 Subject: ARM: tegra: Add DTS for the nyan-blaze board It's commercial name is HP Chromebook 14 and is substantially similar to the Acer Chromebook 13 (nyan-big). Signed-off-by: Tomeu Vizoso Acked-by: Stephen Warren Reviewed-by: Alexandre Courbot Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a1c776b..0af5d29 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -577,6 +577,7 @@ dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ + tegra124-nyan-blaze.dtb \ tegra124-venice2.dtb dtb-$(CONFIG_ARCH_U300) += \ ste-u300.dtb diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts new file mode 100644 index 0000000..e6e6b80 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts @@ -0,0 +1,1332 @@ +/dts-v1/; + +#include "tegra124-nyan.dtsi" + +/ { + model = "HP Chromebook 14"; + compatible = "google,nyan-blaze", "google,nyan", "nvidia,tegra124"; + + panel: panel { + compatible = "samsung,ltn140at29-301"; + + backlight = <&backlight>; + ddc-i2c-bus = <&dpaux>; + }; + + sound { + compatible = "nvidia,tegra-audio-max98090-nyan-blaze", + "nvidia,tegra-audio-max98090-nyan", + "nvidia,tegra-audio-max98090"; + nvidia,model = "GoogleNyanBlaze"; + }; + + pinmux@0,70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_default>; + + pinmux_default: common { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pb0 { + nvidia,pins = "pb0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pb1 { + nvidia,pins = "pb1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pc7 { + nvidia,pins = "pc7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg0 { + nvidia,pins = "pg0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg1 { + nvidia,pins = "pg1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg2 { + nvidia,pins = "pg2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg3 { + nvidia,pins = "pg3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg4 { + nvidia,pins = "pg4"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg5 { + nvidia,pins = "pg5"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg6 { + nvidia,pins = "pg6"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph0 { + nvidia,pins = "ph0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph2 { + nvidia,pins = "ph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph3 { + nvidia,pins = "ph3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph4 { + nvidia,pins = "ph4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph5 { + nvidia,pins = "ph5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph6 { + nvidia,pins = "ph6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph7 { + nvidia,pins = "ph7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi0 { + nvidia,pins = "pi0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi1 { + nvidia,pins = "pi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi2 { + nvidia,pins = "pi2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi3 { + nvidia,pins = "pi3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi4 { + nvidia,pins = "pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi5 { + nvidia,pins = "pi5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi6 { + nvidia,pins = "pi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi7 { + nvidia,pins = "pi7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj0 { + nvidia,pins = "pj0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj2 { + nvidia,pins = "pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj7 { + nvidia,pins = "pj7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk0 { + nvidia,pins = "pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk1 { + nvidia,pins = "pk1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk2 { + nvidia,pins = "pk2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk3 { + nvidia,pins = "pk3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk4 { + nvidia,pins = "pk4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk7 { + nvidia,pins = "pk7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + usb_vbus_en1_pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row16_pt0 { + nvidia,pins = "kb_row16_pt0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row17_pt1 { + nvidia,pins = "kb_row17_pt1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cd_n_pv2 { + nvidia,pins = "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_wp_n_pv3 { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + gpio_w2_aud_pw2 { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_w3_aud_pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x1_aud_px1 { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_clk_px2 { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x3_aud_px3 { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x4_aud_px4 { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x5_aud_px5 { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x6_aud_px6 { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x7_aud_px7 { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_req_pee2 { + nvidia,pins = "dap_mclk1_req_pee2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc3_clk_lb_out_pee4 { + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_lb_in_pee5 { + nvidia,pins = "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dp_hpd_pff0 { + nvidia,pins = "dp_hpd_pff0"; + nvidia,function = "dp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en2_pff1 { + nvidia,pins = "usb_vbus_en2_pff1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pff2 { + nvidia,pins = "pff2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; +}; -- cgit v0.10.2 From a0b9c1cb1636543b659e019a59c048bb911c80e2 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Wed, 18 Mar 2015 10:52:20 +0100 Subject: ARM: tegra: Add node for trackpad in Nyan boards The Nyan boards have a eKTH3000 from Elan as their trackpad, connected through I2C. Signed-off-by: Tomeu Vizoso Acked-by: Stephen Warren Reviewed-by: Alexandre Courbot Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index c0ee53f..579b0b9 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -71,6 +71,14 @@ i2c@0,7000c400 { status = "okay"; clock-frequency = <100000>; + + trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupt-parent = <&gpio>; + interrupts = ; + wakeup-source; + }; }; i2c@0,7000c500 { -- cgit v0.10.2 From 1d1690b85726540c3d2bf0907ce4b30bfec42dc1 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Wed, 18 Mar 2015 10:52:21 +0100 Subject: ARM: tegra: Use pwrseq-simple for the wifi in Nyan The Nyan boards have a Marvell 88w8897 wifi card connected through SDIO that needs the reset line to be asserted before mmc power up and deasserted afterwards. This patch also adds references to the power supplies of the card so that the regulators are enabled when it's probed. Signed-off-by: Tomeu Vizoso Acked-by: Stephen Warren Reviewed-by: Alexandre Courbot Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 579b0b9..d3a95f9 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -207,7 +207,6 @@ regulator-name = "+1.8V_VDDIO"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-boot-on; regulator-always-on; }; @@ -364,12 +363,20 @@ status = "okay"; }; + sdhci0_pwrseq: sdhci0_pwrseq { + compatible = "mmc-pwrseq-simple"; + + reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; + }; + sdhci@0,700b0000 { /* WiFi/BT on this bus */ status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; bus-width = <4>; no-1-8-v; non-removable; + mmc-pwrseq = <&sdhci0_pwrseq>; + vmmc-supply = <&vdd_3v3_lp0>; + vqmmc-supply = <&vddio_1v8>; }; sdhci@0,700b0400 { /* SD Card on this bus */ -- cgit v0.10.2 From 33b274ba10888627f826c9afc26f44f3ed8ec2b4 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Wed, 18 Mar 2015 10:52:22 +0100 Subject: ARM: tegra: Use generated pinmux data for Nyan Big Google has submitted a board config for the pinmux programming of the Nyan Big board. Use the whole of it as it's generated to make it easier to update as the configuration gets fixed in the future. Signed-off-by: Tomeu Vizoso Acked-by: Stephen Warren Reviewed-by: Alexandre Courbot Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts index 3995630..d34661b 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big.dts +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -29,448 +29,1308 @@ pinctrl-0 = <&pinmux_default>; pinmux_default: common { - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,enable-input = ; + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; nvidia,pull = ; nvidia,tristate = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3"; - nvidia,function = "i2s1"; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0", - "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,enable-input = ; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_nxt_py2", - "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,enable-input = ; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; nvidia,pull = ; nvidia,tristate = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,enable-input = ; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; nvidia,pull = ; nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; }; - pg4 { - nvidia,pins = "pg4", - "pg5", - "pg6", - "pi3"; - nvidia,function = "spi4"; - nvidia,enable-input = ; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; nvidia,pull = ; nvidia,tristate = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,enable-input = ; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - pk0 { - nvidia,pins = "pk0", - "kb_row15_ps7", - "clk_32k_out_pa0"; - nvidia,function = "soc"; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; + pb0 { + nvidia,pins = "pb0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; + pb1 { + nvidia,pins = "pb1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; nvidia,function = "sdmmc3"; - nvidia,enable-input = ; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "kb_col4_pq4", - "sdmmc3_clk_lb_out_pee4", - "sdmmc3_clk_lb_in_pee5", - "sdmmc3_cd_n_pv2"; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; nvidia,function = "sdmmc3"; - nvidia,enable-input = ; nvidia,pull = ; nvidia,tristate = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = ; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,enable-input = ; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,enable-input = ; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; }; gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5", - "gen1_i2c_scl_pc4"; + nvidia,pins = "gen1_i2c_sda_pc5"; nvidia,function = "i2c1"; - nvidia,enable-input = ; nvidia,pull = ; nvidia,tristate = ; - nvidia,lock = ; + nvidia,enable-input = ; nvidia,open-drain = ; }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,enable-input = ; + pc7 { + nvidia,pins = "pc7"; nvidia,pull = ; nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; nvidia,enable-input = ; - nvidia,pull = ; + }; + pg0 { + nvidia,pins = "pg0"; + nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; + pg1 { + nvidia,pins = "pg1"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; + }; + pg2 { + nvidia,pins = "pg2"; nvidia,pull = ; nvidia,tristate = ; - nvidia,lock = ; - nvidia,rcv-sel = ; + nvidia,enable-input = ; }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; + pg3 { + nvidia,pins = "pg3"; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; + pg4 { + nvidia,pins = "pg4"; + nvidia,function = "spi4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4", - "usb_vbus_en1_pn5"; - nvidia,function = "usb"; - nvidia,enable-input = ; + pg5 { + nvidia,pins = "pg5"; + nvidia,function = "spi4"; nvidia,pull = ; nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; + nvidia,enable-input = ; }; - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <22>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <2>; - nvidia,pull-up-strength = <1>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - nvidia,drive-type = <1>; - }; - codec_irq_l { - nvidia,pins = "ph4"; - nvidia,function = "gmi"; + pg6 { + nvidia,pins = "pg6"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - lcd_bl_en { - nvidia,pins = "ph2"; + ph0 { + nvidia,pins = "ph0"; nvidia,function = "gmi"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; nvidia,enable-input = ; }; - touch_irq_l { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; - tpm_davint_l { - nvidia,pins = "ph6"; - nvidia,function = "gmi"; + ph2 { + nvidia,pins = "ph2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ts_irq_l { - nvidia,pins = "pk2"; + ph3 { + nvidia,pins = "ph3"; nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph4 { + nvidia,pins = "ph4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ts_reset_l { - nvidia,pins = "pk4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; + ph5 { + nvidia,pins = "ph5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; - ts_shdn_l { - nvidia,pins = "pk1"; - nvidia,function = "gmi"; - nvidia,pull = ; + ph6 { + nvidia,pins = "ph6"; + nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; ph7 { nvidia,pins = "ph7"; - nvidia,function = "gmi"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; - kb_col0_ap { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; + pi0 { + nvidia,pins = "pi0"; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - lid_open { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "rsvd3"; - nvidia,pull = ; + pi1 { + nvidia,pins = "pi1"; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - en_vdd_sd { - nvidia,pins = "kb_row0_pr0"; + pi2 { + nvidia,pins = "pi2"; nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi3 { + nvidia,pins = "pi3"; + nvidia,function = "spi4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ac_ok { - nvidia,pins = "pj0"; + pi4 { + nvidia,pins = "pi4"; nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi5 { + nvidia,pins = "pi5"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; - sensor_irq_l { + pi6 { nvidia,pins = "pi6"; - nvidia,function = "gmi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - wifi_en { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "rsvd4"; + pi7 { + nvidia,pins = "pi7"; nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; - en_vdd_bl { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; + pj0 { + nvidia,pins = "pj0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj2 { + nvidia,pins = "pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; - en_vdd_hdmi { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj7 { + nvidia,pins = "pj7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk0 { + nvidia,pins = "pk0"; + nvidia,function = "rsvd1"; nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk1 { + nvidia,pins = "pk1"; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - soc_warm_reset_l { - nvidia,pins = "pi5"; + pk2 { + nvidia,pins = "pk2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk3 { + nvidia,pins = "pk3"; nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk4 { + nvidia,pins = "pk4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - hp_det_l { - nvidia,pins = "pi7"; - nvidia,function = "rsvd1"; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk7 { + nvidia,pins = "pk7"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - mic_det_l { - nvidia,pins = "kb_row7_pr7"; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + usb_vbus_en1_pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row16_pt0 { + nvidia,pins = "kb_row16_pt0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row17_pt1 { + nvidia,pins = "kb_row17_pt1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cd_n_pv2 { + nvidia,pins = "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_wp_n_pv3 { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + gpio_w2_aud_pw2 { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_w3_aud_pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x1_aud_px1 { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_clk_px2 { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x3_aud_px3 { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x4_aud_px4 { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x5_aud_px5 { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x6_aud_px6 { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x7_aud_px7 { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_req_pee2 { + nvidia,pins = "dap_mclk1_req_pee2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc3_clk_lb_out_pee4 { + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_lb_in_pee5 { + nvidia,pins = "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dp_hpd_pff0 { + nvidia,pins = "dp_hpd_pff0"; + nvidia,function = "dp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en2_pff1 { + nvidia,pins = "usb_vbus_en2_pff1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pff2 { + nvidia,pins = "pff2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; }; }; }; -- cgit v0.10.2 From 97e147e86b87bb2ab8be46c5e388c8058eda56d6 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Wed, 18 Mar 2015 10:52:23 +0100 Subject: ARM: tegra: nyan: Set maximum frequency for SPI flash Otherwise the SPI core will refuse to register the device. Signed-off-by: Tomeu Vizoso Acked-by: Stephen Warren Reviewed-by: Alexandre Courbot Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index d3a95f9..9b3fca8 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -344,6 +344,7 @@ flash@0 { compatible = "winbond,w25q32dw"; + spi-max-frequency = <25000000>; reg = <0>; }; }; -- cgit v0.10.2 From 1755de860b0f000d262d6ea326a14afa036b654d Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Wed, 18 Mar 2015 10:52:26 +0100 Subject: ARM: tegra: nyan: Add gpio-restart node The Nyan Chromebooks have a GPIO line dedicated to restarting the system. Using this line will make sure that the TPM is restarted as well. Signed-off-by: Tomeu Vizoso Acked-by: Stephen Warren Reviewed-by: Alexandre Courbot Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 9b3fca8..0b130cb 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -683,6 +683,12 @@ nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + priority = <200>; + }; }; #include "cros-ec-keyboard.dtsi" -- cgit v0.10.2 From 160b2dd712ee4621617fbd3eb7d8e28375ecdba0 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Wed, 18 Mar 2015 10:52:27 +0100 Subject: ARM: tegra: nyan: The WiFi card is kept powered during suspend Even if the host controller doesn't have power during suspend, the card is kept powered. Signed-off-by: Tomeu Vizoso Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 0b130cb..a9aec23 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -378,6 +378,7 @@ mmc-pwrseq = <&sdhci0_pwrseq>; vmmc-supply = <&vdd_3v3_lp0>; vqmmc-supply = <&vddio_1v8>; + keep-power-in-suspend; }; sdhci@0,700b0400 { /* SD Card on this bus */ -- cgit v0.10.2 From 44486b48b066330e0ed0a66478cc49f5975ec6c1 Mon Sep 17 00:00:00 2001 From: Luciano Coelho Date: Wed, 18 Mar 2015 18:38:26 +0200 Subject: wl12xx: use frequency instead of enumerations for pdata clocks Instead of defining an enumeration with the FW specific values for the different clock rates, use the actual frequency instead. Also add a boolean to specify whether the clock is XTAL or not. Change all board files to reflect this. Signed-off-by: Luciano Coelho [Eliad - small fixes, update board file changes] Signed-off-by: Eliad Peller Tested-by: Nikita Kiryanov Acked-by: Kalle Valo Acked-by: Sekhar Nori Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 916589c..853b941 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -1386,7 +1386,8 @@ static const short da850_wl12xx_pins[] __initconst = { static struct wl12xx_platform_data da850_wl12xx_wlan_data __initdata = { .irq = -1, .irq_trigger = IRQ_TYPE_EDGE_RISING, - .board_ref_clock = WL12XX_REFCLOCK_38, + .ref_clock_freq = 38400000, + .ref_clock_xtal = false, }; static __init int da850_wl12xx_init(void) diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index e86fb0d..cebdf8d 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -39,14 +39,14 @@ static struct twl4030_gpio_platform_data twl_gpio_auxdata; static struct wl12xx_platform_data wl12xx __initdata; -static void __init __used legacy_init_wl12xx(unsigned ref_clock, - unsigned tcxo_clock, +static void __init __used legacy_init_wl12xx(u32 ref_clock_freq, + u32 tcxo_clock_freq, int gpio) { int res; - wl12xx.board_ref_clock = ref_clock; - wl12xx.board_tcxo_clock = tcxo_clock; + wl12xx.ref_clock_freq = ref_clock_freq; + wl12xx.tcxo_clock_freq = tcxo_clock_freq; wl12xx.irq = gpio_to_irq(gpio); wl12xx.irq_trigger = IRQ_TYPE_LEVEL_HIGH; @@ -57,8 +57,8 @@ static void __init __used legacy_init_wl12xx(unsigned ref_clock, } } #else -static inline void legacy_init_wl12xx(unsigned ref_clock, - unsigned tcxo_clock, +static inline void legacy_init_wl12xx(u32 ref_clock_freq, + u32 tcxo_clock_freq, int gpio) { } @@ -130,7 +130,7 @@ static void __init omap3_sbc_t3730_twl_init(void) static void __init omap3_sbc_t3730_legacy_init(void) { omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub"); - legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 136); + legacy_init_wl12xx(38400000, 0, 136); } static void __init omap3_sbc_t3530_legacy_init(void) @@ -175,12 +175,12 @@ static void __init omap3_igep0030_rev_g_legacy_init(void) static void __init omap3_evm_legacy_init(void) { hsmmc2_internal_input_clk(); - legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 149); + legacy_init_wl12xx(38400000, 0, 149); } static void __init omap3_zoom_legacy_init(void) { - legacy_init_wl12xx(WL12XX_REFCLOCK_26, 0, 162); + legacy_init_wl12xx(26000000, 0, 162); } static void am35xx_enable_emac_int(void) @@ -247,7 +247,7 @@ static void __init omap3_sbc_t3517_legacy_init(void) am35xx_emac_reset(); hsmmc2_internal_input_clk(); omap3_sbc_t3517_wifi_init(); - legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 145); + legacy_init_wl12xx(38400000, 0, 145); } static void __init am3517_evm_legacy_init(void) @@ -292,18 +292,17 @@ static void __init omap3_tao3530_legacy_init(void) #ifdef CONFIG_ARCH_OMAP4 static void __init omap4_sdp_legacy_init(void) { - legacy_init_wl12xx(WL12XX_REFCLOCK_26, - WL12XX_TCXOCLOCK_26, 53); + legacy_init_wl12xx(26000000, 26000000, 53); } static void __init omap4_panda_legacy_init(void) { - legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 53); + legacy_init_wl12xx(38400000, 0, 53); } static void __init var_som_om44_legacy_init(void) { - legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 41); + legacy_init_wl12xx(38400000, 0, 41); } #endif @@ -318,7 +317,7 @@ static struct iommu_platform_data omap4_iommu_pdata = { #ifdef CONFIG_SOC_AM33XX static void __init am335x_evmsk_legacy_init(void) { - legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 31); + legacy_init_wl12xx(38400000, 0, 31); } #endif diff --git a/drivers/net/wireless/ti/wl12xx/main.c b/drivers/net/wireless/ti/wl12xx/main.c index 144d1f8..b3f751f 100644 --- a/drivers/net/wireless/ti/wl12xx/main.c +++ b/drivers/net/wireless/ti/wl12xx/main.c @@ -1770,6 +1770,40 @@ wl12xx_iface_combinations[] = { }, }; +static const struct wl12xx_clock wl12xx_refclock_table[] = { + { 19200000, false, WL12XX_REFCLOCK_19 }, + { 26000000, false, WL12XX_REFCLOCK_26 }, + { 26000000, true, WL12XX_REFCLOCK_26_XTAL }, + { 38400000, false, WL12XX_REFCLOCK_38 }, + { 38400000, true, WL12XX_REFCLOCK_38_XTAL }, + { 52000000, false, WL12XX_REFCLOCK_52 }, + { 0, false, 0 } +}; + +static const struct wl12xx_clock wl12xx_tcxoclock_table[] = { + { 16368000, true, WL12XX_TCXOCLOCK_16_368 }, + { 16800000, true, WL12XX_TCXOCLOCK_16_8 }, + { 19200000, true, WL12XX_TCXOCLOCK_19_2 }, + { 26000000, true, WL12XX_TCXOCLOCK_26 }, + { 32736000, true, WL12XX_TCXOCLOCK_32_736 }, + { 33600000, true, WL12XX_TCXOCLOCK_33_6 }, + { 38400000, true, WL12XX_TCXOCLOCK_38_4 }, + { 52000000, true, WL12XX_TCXOCLOCK_52 }, + { 0, false, 0 } +}; + +static int wl12xx_get_clock_idx(const struct wl12xx_clock *table, + u32 freq, bool xtal) +{ + int i; + + for (i = 0; table[i].freq != 0; i++) + if ((table[i].freq == freq) && (table[i].xtal == xtal)) + return table[i].hw_idx; + + return -EINVAL; +} + static int wl12xx_setup(struct wl1271 *wl) { struct wl12xx_priv *priv = wl->priv; @@ -1799,7 +1833,17 @@ static int wl12xx_setup(struct wl1271 *wl) wl12xx_conf_init(wl); if (!fref_param) { - priv->ref_clock = pdata->board_ref_clock; + priv->ref_clock = wl12xx_get_clock_idx(wl12xx_refclock_table, + pdata->ref_clock_freq, + pdata->ref_clock_xtal); + if (priv->ref_clock < 0) { + wl1271_error("Invalid ref_clock frequency (%d Hz, %s)", + pdata->ref_clock_freq, + pdata->ref_clock_xtal ? + "XTAL" : "not XTAL"); + + return priv->ref_clock; + } } else { if (!strcmp(fref_param, "19.2")) priv->ref_clock = WL12XX_REFCLOCK_19; @@ -1817,9 +1861,17 @@ static int wl12xx_setup(struct wl1271 *wl) wl1271_error("Invalid fref parameter %s", fref_param); } - if (!tcxo_param) { - priv->tcxo_clock = pdata->board_tcxo_clock; - } else { + if (!tcxo_param && pdata->tcxo_clock_freq) { + priv->tcxo_clock = wl12xx_get_clock_idx(wl12xx_tcxoclock_table, + pdata->tcxo_clock_freq, + true); + if (priv->tcxo_clock < 0) { + wl1271_error("Invalid tcxo_clock frequency (%d Hz)", + pdata->tcxo_clock_freq); + + return priv->tcxo_clock; + } + } else if (tcxo_param) { if (!strcmp(tcxo_param, "19.2")) priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2; else if (!strcmp(tcxo_param, "26")) diff --git a/drivers/net/wireless/ti/wl12xx/wl12xx.h b/drivers/net/wireless/ti/wl12xx/wl12xx.h index 75c9265..5952e99a 100644 --- a/drivers/net/wireless/ti/wl12xx/wl12xx.h +++ b/drivers/net/wireless/ti/wl12xx/wl12xx.h @@ -82,6 +82,34 @@ struct wl12xx_priv { struct wl127x_rx_mem_pool_addr *rx_mem_addr; }; +/* Reference clock values */ +enum { + WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */ + WL12XX_REFCLOCK_26 = 1, /* 26 MHz */ + WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */ + WL12XX_REFCLOCK_52 = 3, /* 52 MHz */ + WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */ + WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */ +}; + +/* TCXO clock values */ +enum { + WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */ + WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */ + WL12XX_TCXOCLOCK_38_4 = 2, /* 38.4MHz */ + WL12XX_TCXOCLOCK_52 = 3, /* 52 MHz */ + WL12XX_TCXOCLOCK_16_368 = 4, /* 16.368 MHz */ + WL12XX_TCXOCLOCK_32_736 = 5, /* 32.736 MHz */ + WL12XX_TCXOCLOCK_16_8 = 6, /* 16.8 MHz */ + WL12XX_TCXOCLOCK_33_6 = 7, /* 33.6 MHz */ +}; + +struct wl12xx_clock { + u32 freq; + bool xtal; + u8 hw_idx; +}; + struct wl12xx_fw_packet_counters { /* Cumulative counter of released packets per AC */ u8 tx_released_pkts[NUM_TX_QUEUES]; diff --git a/include/linux/wl12xx.h b/include/linux/wl12xx.h index 3876b67..eea1e6d 100644 --- a/include/linux/wl12xx.h +++ b/include/linux/wl12xx.h @@ -26,28 +26,6 @@ #include -/* Reference clock values */ -enum { - WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */ - WL12XX_REFCLOCK_26 = 1, /* 26 MHz */ - WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */ - WL12XX_REFCLOCK_52 = 3, /* 52 MHz */ - WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */ - WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */ -}; - -/* TCXO clock values */ -enum { - WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */ - WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */ - WL12XX_TCXOCLOCK_38_4 = 2, /* 38.4MHz */ - WL12XX_TCXOCLOCK_52 = 3, /* 52 MHz */ - WL12XX_TCXOCLOCK_16_368 = 4, /* 16.368 MHz */ - WL12XX_TCXOCLOCK_32_736 = 5, /* 32.736 MHz */ - WL12XX_TCXOCLOCK_16_8 = 6, /* 16.8 MHz */ - WL12XX_TCXOCLOCK_33_6 = 7, /* 33.6 MHz */ -}; - struct wl1251_platform_data { int power_gpio; /* SDIO only: IRQ number if WLAN_IRQ line is used, 0 for SDIO IRQs */ @@ -58,8 +36,9 @@ struct wl1251_platform_data { struct wl12xx_platform_data { int irq; u32 irq_trigger; - int board_ref_clock; - int board_tcxo_clock; + bool ref_clock_xtal; /* specify whether the clock is XTAL or not */ + u32 ref_clock_freq; /* in Hertz */ + u32 tcxo_clock_freq; /* in Hertz, tcxo is always XTAL */ bool pwr_in_suspend; }; -- cgit v0.10.2 From d96c8b77407de054e7a485bdef793ed5be827df4 Mon Sep 17 00:00:00 2001 From: Eliad Peller Date: Wed, 18 Mar 2015 18:38:27 +0200 Subject: dt: bindings: add TI's wilink wireless device Add device tree binding documentation for TI's wilink (wl12xx and wl18xx) wlan chip. Signed-off-by: Eliad Peller Tested-by: Nikita Kiryanov Acked-by: Kalle Valo Signed-off-by: Tony Lindgren diff --git a/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt b/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt new file mode 100644 index 0000000..2a3d90d --- /dev/null +++ b/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt @@ -0,0 +1,47 @@ +TI Wilink 6/7/8 (wl12xx/wl18xx) SDIO devices + +This node provides properties for controlling the wilink wireless device. The +node is expected to be specified as a child node to the SDIO controller that +connects the device to the system. + +Required properties: + - compatible: should be one of the following: + * "ti,wl1271" + * "ti,wl1273" + * "ti,wl1281" + * "ti,wl1283" + * "ti,wl1801" + * "ti,wl1805" + * "ti,wl1807" + * "ti,wl1831" + * "ti,wl1835" + * "ti,wl1837" + - interrupts : specifies attributes for the out-of-band interrupt. + +Optional properties: + - interrupt-parent : the phandle for the interrupt controller to which the + device interrupts are connected. + - ref-clock-frequency : ref clock frequency in Hz + - tcxo-clock-frequency : tcxo clock frequency in Hz + +Note: the *-clock-frequency properties assume internal clocks. In case of external +clock, new bindings (for parsing the clock nodes) have to be added. + +Example: + +&mmc3 { + status = "okay"; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio0>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + }; +}; -- cgit v0.10.2 From 5ea5c518ccaba0de97efb71c3bccbcdee681c2e6 Mon Sep 17 00:00:00 2001 From: Eliad Peller Date: Wed, 18 Mar 2015 18:38:28 +0200 Subject: wlcore: add device-tree support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When running with device-tree, we no longer have a board file that can set up the platform data for wlcore. Allow this data to be passed from DT. Signed-off-by: Ido Yariv Signed-off-by: Eliad Peller Tested-by: Sébastien Szymanski Tested-by: Nikita Kiryanov Acked-by: Kalle Valo Signed-off-by: Tony Lindgren diff --git a/drivers/net/wireless/ti/wlcore/sdio.c b/drivers/net/wireless/ti/wlcore/sdio.c index 2bce00a..b55dc0e 100644 --- a/drivers/net/wireless/ti/wlcore/sdio.c +++ b/drivers/net/wireless/ti/wlcore/sdio.c @@ -34,6 +34,8 @@ #include #include #include +#include +#include #include "wlcore.h" #include "wl12xx_80211.h" @@ -214,6 +216,82 @@ static struct wl1271_if_operations sdio_ops = { .set_block_size = wl1271_sdio_set_block_size, }; +#ifdef CONFIG_OF +static const struct of_device_id wlcore_sdio_of_match_table[] = { + { .compatible = "ti,wl1271" }, + { .compatible = "ti,wl1273" }, + { .compatible = "ti,wl1281" }, + { .compatible = "ti,wl1283" }, + { .compatible = "ti,wl1801" }, + { .compatible = "ti,wl1805" }, + { .compatible = "ti,wl1807" }, + { .compatible = "ti,wl1831" }, + { .compatible = "ti,wl1835" }, + { .compatible = "ti,wl1837" }, + { } +}; + +static struct wl12xx_platform_data *wlcore_probe_of(struct device *dev) +{ + struct device_node *np = dev->of_node; + struct wl12xx_platform_data *pdata; + + if (!np || !of_match_node(wlcore_sdio_of_match_table, np)) + return NULL; + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return NULL; + + pdata->irq = irq_of_parse_and_map(np, 0); + if (!pdata->irq) { + dev_err(dev, "No irq in platform data\n"); + kfree(pdata); + return NULL; + } + + pdata->irq_trigger = + irqd_get_trigger_type(irq_get_irq_data(pdata->irq)); + + /* optional clock frequency params */ + of_property_read_u32(np, "ref-clock-frequency", + &pdata->ref_clock_freq); + of_property_read_u32(np, "tcxo-clock-frequency", + &pdata->tcxo_clock_freq); + + return pdata; +} +#else +static struct wl12xx_platform_data *wlcore_probe_of(struct device *dev) +{ + return NULL; +} +#endif + +static struct wl12xx_platform_data * +wlcore_get_platform_data(struct device *dev) +{ + struct wl12xx_platform_data *pdata; + + /* first, look for DT data */ + pdata = wlcore_probe_of(dev); + if (pdata) + return pdata; + + /* if not found - fallback to static platform data */ + pdata = wl12xx_get_platform_data(); + if (!IS_ERR(pdata)) + return kmemdup(pdata, sizeof(*pdata), GFP_KERNEL); + + dev_err(dev, "No platform data set\n"); + return NULL; +} + +static void wlcore_del_platform_data(struct wl12xx_platform_data *pdata) +{ + kfree(pdata); +} + static int wl1271_probe(struct sdio_func *func, const struct sdio_device_id *id) { @@ -245,12 +323,9 @@ static int wl1271_probe(struct sdio_func *func, /* Use block mode for transferring over one block size of data */ func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE; - pdev_data.pdata = wl12xx_get_platform_data(); - if (IS_ERR(pdev_data.pdata)) { - ret = PTR_ERR(pdev_data.pdata); - dev_err(glue->dev, "missing wlan platform data: %d\n", ret); + pdev_data.pdata = wlcore_get_platform_data(&func->dev); + if (!pdev_data.pdata) goto out_free_glue; - } /* if sdio can keep power while host is suspended, enable wow */ mmcflags = sdio_get_host_pm_caps(func); @@ -279,7 +354,7 @@ static int wl1271_probe(struct sdio_func *func, if (!glue->core) { dev_err(glue->dev, "can't allocate platform_device"); ret = -ENOMEM; - goto out_free_glue; + goto out_free_pdata; } glue->core->dev.parent = &func->dev; @@ -313,6 +388,9 @@ static int wl1271_probe(struct sdio_func *func, out_dev_put: platform_device_put(glue->core); +out_free_pdata: + wlcore_del_platform_data(pdev_data.pdata); + out_free_glue: kfree(glue); @@ -323,11 +401,14 @@ out: static void wl1271_remove(struct sdio_func *func) { struct wl12xx_sdio_glue *glue = sdio_get_drvdata(func); + struct wlcore_platdev_data *pdev_data = glue->core->dev.platform_data; + struct wl12xx_platform_data *pdata = pdev_data->pdata; /* Undo decrement done above in wl1271_probe */ pm_runtime_get_noresume(&func->dev); platform_device_unregister(glue->core); + wlcore_del_platform_data(pdata); kfree(glue); } -- cgit v0.10.2 From 99f84cae43df242f0d69ffcfee3a4d69f9b71b44 Mon Sep 17 00:00:00 2001 From: Eliad Peller Date: Wed, 18 Mar 2015 18:38:29 +0200 Subject: ARM: dts: add wl12xx/wl18xx bindings Replace all the pdata-quirks for setting wl12xx/wl18xx platform data with proper DT definitions. Signed-off-by: Eliad Peller Acked-by: Javier Martinez Canillas Acked-by: Enric Balletbo i Serra Tested-by: Nikita Kiryanov Tested-by: Tony Lindgren Acked-by: Kalle Valo Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index df5fee6..87fc7a3 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -15,6 +15,7 @@ #include "am33xx.dtsi" #include +#include / { model = "TI AM335x EVM-SK"; @@ -647,6 +648,16 @@ cap-power-off-card; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio1>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */ + ref-clock-frequency = <38400000>; + }; }; &mcasp1 { diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts index 0ab748c..f5b5a1d 100644 --- a/arch/arm/boot/dts/omap3-cm-t3517.dts +++ b/arch/arm/boot/dts/omap3-cm-t3517.dts @@ -133,6 +133,16 @@ non-removable; bus-width = <4>; cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; /* gpio 145 */ + ref-clock-frequency = <38400000>; + }; }; &dss { diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts index 46eadb2..2294f5b 100644 --- a/arch/arm/boot/dts/omap3-cm-t3730.dts +++ b/arch/arm/boot/dts/omap3-cm-t3730.dts @@ -73,6 +73,16 @@ non-removable; bus-width = <4>; cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; /* gpio 136 */ + ref-clock-frequency = <38400000>; + }; }; &dss { diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi index 127f3e7..346552b 100644 --- a/arch/arm/boot/dts/omap3-evm-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-common.dtsi @@ -106,6 +106,16 @@ non-removable; bus-width = <4>; cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 149 */ + ref-clock-frequency = <38400000>; + }; }; &twl_gpio { diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts index cc8bd0c..72f7cdc 100644 --- a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts +++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts @@ -42,4 +42,13 @@ vmmc-supply = <&lbep5clwmc_wlen>; bus-width = <4>; non-removable; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; /* gpio 177 */ + }; }; diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts index 9326b28..b899e34 100644 --- a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts +++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts @@ -64,4 +64,13 @@ vmmc-supply = <&lbep5clwmc_wlen>; bus-width = <4>; non-removable; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; /* gpio 136 */ + }; }; diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts index 6644f51..131448d 100644 --- a/arch/arm/boot/dts/omap3-zoom3.dts +++ b/arch/arm/boot/dts/omap3-zoom3.dts @@ -195,6 +195,16 @@ cap-power-off-card; pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins &mmc3_2_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 162 */ + ref-clock-frequency = <26000000>; + }; }; &uart1 { diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 1505135..1228de5 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -450,6 +450,16 @@ non-removable; bus-width = <4>; cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio2>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */ + ref-clock-frequency = <38400000>; + }; }; &emif1 { diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 3e1da43..8c36f51 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -487,6 +487,17 @@ non-removable; bus-width = <4>; cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1281"; + reg = <2>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */ + ref-clock-frequency = <26000000>; + tcxo-clock-frequency = <26000000>; + }; }; &emif1 { diff --git a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi index cc66af4..9bceeb7 100644 --- a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi +++ b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi @@ -65,4 +65,14 @@ bus-width = <4>; cap-power-off-card; status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */ + ref-clock-frequency = <38400000>; + }; }; diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index cebdf8d..af11511 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include @@ -35,35 +34,6 @@ struct pdata_init { struct of_dev_auxdata omap_auxdata_lookup[]; static struct twl4030_gpio_platform_data twl_gpio_auxdata; -#if IS_ENABLED(CONFIG_WL12XX) - -static struct wl12xx_platform_data wl12xx __initdata; - -static void __init __used legacy_init_wl12xx(u32 ref_clock_freq, - u32 tcxo_clock_freq, - int gpio) -{ - int res; - - wl12xx.ref_clock_freq = ref_clock_freq; - wl12xx.tcxo_clock_freq = tcxo_clock_freq; - wl12xx.irq = gpio_to_irq(gpio); - wl12xx.irq_trigger = IRQ_TYPE_LEVEL_HIGH; - - res = wl12xx_set_platform_data(&wl12xx); - if (res) { - pr_err("error setting wl12xx data: %d\n", res); - return; - } -} -#else -static inline void legacy_init_wl12xx(u32 ref_clock_freq, - u32 tcxo_clock_freq, - int gpio) -{ -} -#endif - #ifdef CONFIG_MACH_NOKIA_N8X0 static void __init omap2420_n8x0_legacy_init(void) { @@ -130,7 +100,6 @@ static void __init omap3_sbc_t3730_twl_init(void) static void __init omap3_sbc_t3730_legacy_init(void) { omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub"); - legacy_init_wl12xx(38400000, 0, 136); } static void __init omap3_sbc_t3530_legacy_init(void) @@ -160,14 +129,12 @@ static struct platform_device btwilink_device = { static void __init omap3_igep0020_rev_f_legacy_init(void) { - legacy_init_wl12xx(0, 0, 177); platform_device_register(&wl18xx_device); platform_device_register(&btwilink_device); } static void __init omap3_igep0030_rev_g_legacy_init(void) { - legacy_init_wl12xx(0, 0, 136); platform_device_register(&wl18xx_device); platform_device_register(&btwilink_device); } @@ -175,12 +142,6 @@ static void __init omap3_igep0030_rev_g_legacy_init(void) static void __init omap3_evm_legacy_init(void) { hsmmc2_internal_input_clk(); - legacy_init_wl12xx(38400000, 0, 149); -} - -static void __init omap3_zoom_legacy_init(void) -{ - legacy_init_wl12xx(26000000, 0, 162); } static void am35xx_enable_emac_int(void) @@ -247,7 +208,6 @@ static void __init omap3_sbc_t3517_legacy_init(void) am35xx_emac_reset(); hsmmc2_internal_input_clk(); omap3_sbc_t3517_wifi_init(); - legacy_init_wl12xx(38400000, 0, 145); } static void __init am3517_evm_legacy_init(void) @@ -289,23 +249,6 @@ static void __init omap3_tao3530_legacy_init(void) } #endif /* CONFIG_ARCH_OMAP3 */ -#ifdef CONFIG_ARCH_OMAP4 -static void __init omap4_sdp_legacy_init(void) -{ - legacy_init_wl12xx(26000000, 26000000, 53); -} - -static void __init omap4_panda_legacy_init(void) -{ - legacy_init_wl12xx(38400000, 0, 53); -} - -static void __init var_som_om44_legacy_init(void) -{ - legacy_init_wl12xx(38400000, 0, 41); -} -#endif - #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) static struct iommu_platform_data omap4_iommu_pdata = { .reset_name = "mmu_cache", @@ -314,13 +257,6 @@ static struct iommu_platform_data omap4_iommu_pdata = { }; #endif -#ifdef CONFIG_SOC_AM33XX -static void __init am335x_evmsk_legacy_init(void) -{ - legacy_init_wl12xx(38400000, 0, 31); -} -#endif - #ifdef CONFIG_SOC_OMAP5 static void __init omap5_uevm_legacy_init(void) { @@ -421,19 +357,9 @@ static struct pdata_init pdata_quirks[] __initdata = { { "isee,omap3-igep0020-rev-f", omap3_igep0020_rev_f_legacy_init, }, { "isee,omap3-igep0030-rev-g", omap3_igep0030_rev_g_legacy_init, }, { "ti,omap3-evm-37xx", omap3_evm_legacy_init, }, - { "ti,omap3-zoom3", omap3_zoom_legacy_init, }, { "ti,am3517-evm", am3517_evm_legacy_init, }, { "technexion,omap3-tao3530", omap3_tao3530_legacy_init, }, #endif -#ifdef CONFIG_ARCH_OMAP4 - { "ti,omap4-sdp", omap4_sdp_legacy_init, }, - { "ti,omap4-panda", omap4_panda_legacy_init, }, - { "variscite,var-dvk-om44", var_som_om44_legacy_init, }, - { "variscite,var-stk-om44", var_som_om44_legacy_init, }, -#endif -#ifdef CONFIG_SOC_AM33XX - { "ti,am335x-evmsk", am335x_evmsk_legacy_init, }, -#endif #ifdef CONFIG_SOC_OMAP5 { "ti,omap5-uevm", omap5_uevm_legacy_init, }, #endif -- cgit v0.10.2 From 83c3a7d4ac7fdc29a64bf9a5467a36b4c72a1eed Mon Sep 17 00:00:00 2001 From: Eliad Peller Date: Wed, 18 Mar 2015 18:38:30 +0200 Subject: wlcore: remove wl12xx_platform_data Now that we have wlcore device-tree bindings in place (for both wl12xx and wl18xx), remove the legacy wl12xx_platform_data struct, and move its members into the platform device data (that is passed to wlcore) Davinci 850 is the only platform that still set the platform data in the legacy way (and doesn't have DT bindings), so remove the relevant code/Kconfig option from the board file (as suggested by Sekhar Nori) Since no one currently uses wlcore_spi, simply remove its platform data support (DT bindings will have to be added if someone actually needs it) Signed-off-by: Luciano Coelho Signed-off-by: Eliad Peller Tested-by: Nikita Kiryanov Acked-by: Kalle Valo Acked-by: Sekhar Nori Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index cd30f6f..dd8f531 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -200,17 +200,6 @@ config DA850_UI_SD_VIDEO_PORT endchoice -config DA850_WL12XX - bool "AM18x wl1271 daughter board" - depends on MACH_DAVINCI_DA850_EVM - help - The wl1271 daughter card for AM18x EVMs is a combo wireless - connectivity add-on card, based on the LS Research TiWi module with - Texas Instruments' wl1271 solution. - Say Y if you want to use a wl1271 expansion card connected to the - AM18x EVM. - - config MACH_MITYOMAPL138 bool "Critical Link MityDSP-L138/MityARM-1808 SoM" depends on ARCH_DAVINCI_DA850 diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 853b941..1ed545c 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -38,7 +38,6 @@ #include #include #include -#include #include #include @@ -60,9 +59,6 @@ #define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) #define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) -#define DA850_WLAN_EN GPIO_TO_PIN(6, 9) -#define DA850_WLAN_IRQ GPIO_TO_PIN(6, 10) - #define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6) static struct mtd_partition da850evm_spiflash_part[] = { @@ -1343,110 +1339,6 @@ static __init void da850_vpif_init(void) static __init void da850_vpif_init(void) {} #endif -#ifdef CONFIG_DA850_WL12XX - -static void wl12xx_set_power(int index, bool power_on) -{ - static bool power_state; - - pr_debug("Powering %s wl12xx", power_on ? "on" : "off"); - - if (power_on == power_state) - return; - power_state = power_on; - - if (power_on) { - /* Power up sequence required for wl127x devices */ - gpio_set_value(DA850_WLAN_EN, 1); - usleep_range(15000, 15000); - gpio_set_value(DA850_WLAN_EN, 0); - usleep_range(1000, 1000); - gpio_set_value(DA850_WLAN_EN, 1); - msleep(70); - } else { - gpio_set_value(DA850_WLAN_EN, 0); - } -} - -static struct davinci_mmc_config da850_wl12xx_mmc_config = { - .set_power = wl12xx_set_power, - .wires = 4, - .max_freq = 25000000, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NONREMOVABLE | - MMC_CAP_POWER_OFF_CARD, -}; - -static const short da850_wl12xx_pins[] __initconst = { - DA850_MMCSD1_DAT_0, DA850_MMCSD1_DAT_1, DA850_MMCSD1_DAT_2, - DA850_MMCSD1_DAT_3, DA850_MMCSD1_CLK, DA850_MMCSD1_CMD, - DA850_GPIO6_9, DA850_GPIO6_10, - -1 -}; - -static struct wl12xx_platform_data da850_wl12xx_wlan_data __initdata = { - .irq = -1, - .irq_trigger = IRQ_TYPE_EDGE_RISING, - .ref_clock_freq = 38400000, - .ref_clock_xtal = false, -}; - -static __init int da850_wl12xx_init(void) -{ - int ret; - - ret = davinci_cfg_reg_list(da850_wl12xx_pins); - if (ret) { - pr_err("wl12xx/mmc mux setup failed: %d\n", ret); - goto exit; - } - - ret = da850_register_mmcsd1(&da850_wl12xx_mmc_config); - if (ret) { - pr_err("wl12xx/mmc registration failed: %d\n", ret); - goto exit; - } - - ret = gpio_request_one(DA850_WLAN_EN, GPIOF_OUT_INIT_LOW, "wl12xx_en"); - if (ret) { - pr_err("Could not request wl12xx enable gpio: %d\n", ret); - goto exit; - } - - ret = gpio_request_one(DA850_WLAN_IRQ, GPIOF_IN, "wl12xx_irq"); - if (ret) { - pr_err("Could not request wl12xx irq gpio: %d\n", ret); - goto free_wlan_en; - } - - da850_wl12xx_wlan_data.irq = gpio_to_irq(DA850_WLAN_IRQ); - - ret = wl12xx_set_platform_data(&da850_wl12xx_wlan_data); - if (ret) { - pr_err("Could not set wl12xx data: %d\n", ret); - goto free_wlan_irq; - } - - return 0; - -free_wlan_irq: - gpio_free(DA850_WLAN_IRQ); - -free_wlan_en: - gpio_free(DA850_WLAN_EN); - -exit: - return ret; -} - -#else /* CONFIG_DA850_WL12XX */ - -static __init int da850_wl12xx_init(void) -{ - return 0; -} - -#endif /* CONFIG_DA850_WL12XX */ - #define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000) static __init void da850_evm_init(void) @@ -1503,11 +1395,6 @@ static __init void da850_evm_init(void) if (ret) pr_warn("%s: MMCSD0 registration failed: %d\n", __func__, ret); - - ret = da850_wl12xx_init(); - if (ret) - pr_warn("%s: WL12xx initialization failed: %d\n", - __func__, ret); } davinci_serial_init(da8xx_serial_device); diff --git a/drivers/net/wireless/ti/wilink_platform_data.c b/drivers/net/wireless/ti/wilink_platform_data.c index a92bd3e..ea0e359 100644 --- a/drivers/net/wireless/ti/wilink_platform_data.c +++ b/drivers/net/wireless/ti/wilink_platform_data.c @@ -23,31 +23,6 @@ #include #include -static struct wl12xx_platform_data *wl12xx_platform_data; - -int __init wl12xx_set_platform_data(const struct wl12xx_platform_data *data) -{ - if (wl12xx_platform_data) - return -EBUSY; - if (!data) - return -EINVAL; - - wl12xx_platform_data = kmemdup(data, sizeof(*data), GFP_KERNEL); - if (!wl12xx_platform_data) - return -ENOMEM; - - return 0; -} - -struct wl12xx_platform_data *wl12xx_get_platform_data(void) -{ - if (!wl12xx_platform_data) - return ERR_PTR(-ENODEV); - - return wl12xx_platform_data; -} -EXPORT_SYMBOL(wl12xx_get_platform_data); - static struct wl1251_platform_data *wl1251_platform_data; int __init wl1251_set_platform_data(const struct wl1251_platform_data *data) diff --git a/drivers/net/wireless/ti/wl12xx/main.c b/drivers/net/wireless/ti/wl12xx/main.c index b3f751f..af0fe2e 100644 --- a/drivers/net/wireless/ti/wl12xx/main.c +++ b/drivers/net/wireless/ti/wl12xx/main.c @@ -24,8 +24,6 @@ #include -#include - #include "../wlcore/wlcore.h" #include "../wlcore/debug.h" #include "../wlcore/io.h" @@ -1808,7 +1806,6 @@ static int wl12xx_setup(struct wl1271 *wl) { struct wl12xx_priv *priv = wl->priv; struct wlcore_platdev_data *pdev_data = dev_get_platdata(&wl->pdev->dev); - struct wl12xx_platform_data *pdata = pdev_data->pdata; BUILD_BUG_ON(WL12XX_MAX_LINKS > WLCORE_MAX_LINKS); BUILD_BUG_ON(WL12XX_MAX_AP_STATIONS > WL12XX_MAX_LINKS); @@ -1834,12 +1831,12 @@ static int wl12xx_setup(struct wl1271 *wl) if (!fref_param) { priv->ref_clock = wl12xx_get_clock_idx(wl12xx_refclock_table, - pdata->ref_clock_freq, - pdata->ref_clock_xtal); + pdev_data->ref_clock_freq, + pdev_data->ref_clock_xtal); if (priv->ref_clock < 0) { wl1271_error("Invalid ref_clock frequency (%d Hz, %s)", - pdata->ref_clock_freq, - pdata->ref_clock_xtal ? + pdev_data->ref_clock_freq, + pdev_data->ref_clock_xtal ? "XTAL" : "not XTAL"); return priv->ref_clock; @@ -1861,13 +1858,13 @@ static int wl12xx_setup(struct wl1271 *wl) wl1271_error("Invalid fref parameter %s", fref_param); } - if (!tcxo_param && pdata->tcxo_clock_freq) { + if (!tcxo_param && pdev_data->tcxo_clock_freq) { priv->tcxo_clock = wl12xx_get_clock_idx(wl12xx_tcxoclock_table, - pdata->tcxo_clock_freq, - true); + pdev_data->tcxo_clock_freq, + true); if (priv->tcxo_clock < 0) { wl1271_error("Invalid tcxo_clock frequency (%d Hz)", - pdata->tcxo_clock_freq); + pdev_data->tcxo_clock_freq); return priv->tcxo_clock; } diff --git a/drivers/net/wireless/ti/wlcore/boot.c b/drivers/net/wireless/ti/wlcore/boot.c index 77752b0..19b7ec7 100644 --- a/drivers/net/wireless/ti/wlcore/boot.c +++ b/drivers/net/wireless/ti/wlcore/boot.c @@ -22,7 +22,6 @@ */ #include -#include #include #include "debug.h" diff --git a/drivers/net/wireless/ti/wlcore/main.c b/drivers/net/wireless/ti/wlcore/main.c index 67518f6..0be8079 100644 --- a/drivers/net/wireless/ti/wlcore/main.c +++ b/drivers/net/wireless/ti/wlcore/main.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include @@ -6390,7 +6389,6 @@ static void wlcore_nvs_cb(const struct firmware *fw, void *context) struct wl1271 *wl = context; struct platform_device *pdev = wl->pdev; struct wlcore_platdev_data *pdev_data = dev_get_platdata(&pdev->dev); - struct wl12xx_platform_data *pdata = pdev_data->pdata; struct resource *res; int ret; @@ -6446,7 +6444,7 @@ static void wlcore_nvs_cb(const struct firmware *fw, void *context) if (!ret) { wl->irq_wake_enabled = true; device_init_wakeup(wl->dev, 1); - if (pdata->pwr_in_suspend) + if (pdev_data->pwr_in_suspend) wl->hw->wiphy->wowlan = &wlcore_wowlan_support; } #endif diff --git a/drivers/net/wireless/ti/wlcore/sdio.c b/drivers/net/wireless/ti/wlcore/sdio.c index b55dc0e..ea7e07a 100644 --- a/drivers/net/wireless/ti/wlcore/sdio.c +++ b/drivers/net/wireless/ti/wlcore/sdio.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include @@ -231,67 +230,37 @@ static const struct of_device_id wlcore_sdio_of_match_table[] = { { } }; -static struct wl12xx_platform_data *wlcore_probe_of(struct device *dev) +static int wlcore_probe_of(struct device *dev, int *irq, + struct wlcore_platdev_data *pdev_data) { struct device_node *np = dev->of_node; - struct wl12xx_platform_data *pdata; if (!np || !of_match_node(wlcore_sdio_of_match_table, np)) - return NULL; + return -ENODATA; - pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); - if (!pdata) - return NULL; - - pdata->irq = irq_of_parse_and_map(np, 0); - if (!pdata->irq) { + *irq = irq_of_parse_and_map(np, 0); + if (!*irq) { dev_err(dev, "No irq in platform data\n"); - kfree(pdata); - return NULL; + kfree(pdev_data); + return -EINVAL; } - pdata->irq_trigger = - irqd_get_trigger_type(irq_get_irq_data(pdata->irq)); - /* optional clock frequency params */ of_property_read_u32(np, "ref-clock-frequency", - &pdata->ref_clock_freq); + &pdev_data->ref_clock_freq); of_property_read_u32(np, "tcxo-clock-frequency", - &pdata->tcxo_clock_freq); + &pdev_data->tcxo_clock_freq); - return pdata; + return 0; } #else -static struct wl12xx_platform_data *wlcore_probe_of(struct device *dev) +static int wlcore_probe_of(struct device *dev, int *irq, + struct wlcore_platdev_data *pdev_data) { - return NULL; + return -ENODATA; } #endif -static struct wl12xx_platform_data * -wlcore_get_platform_data(struct device *dev) -{ - struct wl12xx_platform_data *pdata; - - /* first, look for DT data */ - pdata = wlcore_probe_of(dev); - if (pdata) - return pdata; - - /* if not found - fallback to static platform data */ - pdata = wl12xx_get_platform_data(); - if (!IS_ERR(pdata)) - return kmemdup(pdata, sizeof(*pdata), GFP_KERNEL); - - dev_err(dev, "No platform data set\n"); - return NULL; -} - -static void wlcore_del_platform_data(struct wl12xx_platform_data *pdata) -{ - kfree(pdata); -} - static int wl1271_probe(struct sdio_func *func, const struct sdio_device_id *id) { @@ -300,6 +269,7 @@ static int wl1271_probe(struct sdio_func *func, struct resource res[1]; mmc_pm_flag_t mmcflags; int ret = -ENOMEM; + int irq; const char *chip_family; /* We are only able to handle the wlan function */ @@ -323,8 +293,7 @@ static int wl1271_probe(struct sdio_func *func, /* Use block mode for transferring over one block size of data */ func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE; - pdev_data.pdata = wlcore_get_platform_data(&func->dev); - if (!pdev_data.pdata) + if (wlcore_probe_of(&func->dev, &irq, &pdev_data)) goto out_free_glue; /* if sdio can keep power while host is suspended, enable wow */ @@ -332,7 +301,7 @@ static int wl1271_probe(struct sdio_func *func, dev_dbg(glue->dev, "sdio PM caps = 0x%x\n", mmcflags); if (mmcflags & MMC_PM_KEEP_POWER) - pdev_data.pdata->pwr_in_suspend = true; + pdev_data.pwr_in_suspend = true; sdio_set_drvdata(func, glue); @@ -354,15 +323,16 @@ static int wl1271_probe(struct sdio_func *func, if (!glue->core) { dev_err(glue->dev, "can't allocate platform_device"); ret = -ENOMEM; - goto out_free_pdata; + goto out_free_glue; } glue->core->dev.parent = &func->dev; memset(res, 0x00, sizeof(res)); - res[0].start = pdev_data.pdata->irq; - res[0].flags = IORESOURCE_IRQ | pdev_data.pdata->irq_trigger; + res[0].start = irq; + res[0].flags = IORESOURCE_IRQ | + irqd_get_trigger_type(irq_get_irq_data(irq)); res[0].name = "irq"; ret = platform_device_add_resources(glue->core, res, ARRAY_SIZE(res)); @@ -388,9 +358,6 @@ static int wl1271_probe(struct sdio_func *func, out_dev_put: platform_device_put(glue->core); -out_free_pdata: - wlcore_del_platform_data(pdev_data.pdata); - out_free_glue: kfree(glue); @@ -401,14 +368,11 @@ out: static void wl1271_remove(struct sdio_func *func) { struct wl12xx_sdio_glue *glue = sdio_get_drvdata(func); - struct wlcore_platdev_data *pdev_data = glue->core->dev.platform_data; - struct wl12xx_platform_data *pdata = pdev_data->pdata; /* Undo decrement done above in wl1271_probe */ pm_runtime_get_noresume(&func->dev); platform_device_unregister(glue->core); - wlcore_del_platform_data(pdata); kfree(glue); } diff --git a/drivers/net/wireless/ti/wlcore/spi.c b/drivers/net/wireless/ti/wlcore/spi.c index 69601f6..f1ac283 100644 --- a/drivers/net/wireless/ti/wlcore/spi.c +++ b/drivers/net/wireless/ti/wlcore/spi.c @@ -331,11 +331,7 @@ static int wl1271_probe(struct spi_device *spi) memset(&pdev_data, 0x00, sizeof(pdev_data)); - pdev_data.pdata = dev_get_platdata(&spi->dev); - if (!pdev_data.pdata) { - dev_err(&spi->dev, "no platform data\n"); - return -ENODEV; - } + /* TODO: add DT parsing when needed */ pdev_data.if_ops = &spi_ops; diff --git a/drivers/net/wireless/ti/wlcore/wlcore_i.h b/drivers/net/wireless/ti/wlcore/wlcore_i.h index 3396ce5..39efc6d 100644 --- a/drivers/net/wireless/ti/wlcore/wlcore_i.h +++ b/drivers/net/wireless/ti/wlcore/wlcore_i.h @@ -201,8 +201,12 @@ struct wl1271_if_operations { }; struct wlcore_platdev_data { - struct wl12xx_platform_data *pdata; struct wl1271_if_operations *if_ops; + + bool ref_clock_xtal; /* specify whether the clock is XTAL or not */ + u32 ref_clock_freq; /* in Hertz */ + u32 tcxo_clock_freq; /* in Hertz, tcxo is always XTAL */ + bool pwr_in_suspend; }; #define MAX_NUM_KEYS 14 diff --git a/include/linux/wl12xx.h b/include/linux/wl12xx.h index eea1e6d..95704cd 100644 --- a/include/linux/wl12xx.h +++ b/include/linux/wl12xx.h @@ -33,21 +33,8 @@ struct wl1251_platform_data { bool use_eeprom; }; -struct wl12xx_platform_data { - int irq; - u32 irq_trigger; - bool ref_clock_xtal; /* specify whether the clock is XTAL or not */ - u32 ref_clock_freq; /* in Hertz */ - u32 tcxo_clock_freq; /* in Hertz, tcxo is always XTAL */ - bool pwr_in_suspend; -}; - #ifdef CONFIG_WILINK_PLATFORM_DATA -int wl12xx_set_platform_data(const struct wl12xx_platform_data *data); - -struct wl12xx_platform_data *wl12xx_get_platform_data(void); - int wl1251_set_platform_data(const struct wl1251_platform_data *data); struct wl1251_platform_data *wl1251_get_platform_data(void); @@ -55,18 +42,6 @@ struct wl1251_platform_data *wl1251_get_platform_data(void); #else static inline -int wl12xx_set_platform_data(const struct wl12xx_platform_data *data) -{ - return -ENOSYS; -} - -static inline -struct wl12xx_platform_data *wl12xx_get_platform_data(void) -{ - return ERR_PTR(-ENODATA); -} - -static inline int wl1251_set_platform_data(const struct wl1251_platform_data *data) { return -ENOSYS; -- cgit v0.10.2 From 4f59ebed8945c7102b960113093bb2e5497d2fab Mon Sep 17 00:00:00 2001 From: Seungwon Jeon Date: Fri, 27 Mar 2015 01:52:02 +0900 Subject: ARM: dts: Add HS400 support for exynos5420 and exynos5800 HS400 timing values are added for SMDK5420, exynos5420-peach-pit and exynos5800-peach-pi boards. This also adds RCLK GPIO line, this gpio should be in pull-down state. This also enables HS400 on peach-pi and this updates the clock frequency to 800MHz to be set as input clock to controller. Signed-off-by: Seungwon Jeon [alim.akhtar@samsung.com: addressed review comments] Signed-off-by: Alim Akhtar Acked-by: Jaehoon Chung Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 3f4e2fe..0788d08 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -699,8 +699,10 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; bus-width = <8>; }; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index ba686e4..8b15316 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -201,6 +201,13 @@ samsung,pin-drv = <3>; }; + sd0_rclk: sd0-rclk { + samsung,pins = "gpc0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <3>; + }; + sd1_cmd: sd1-cmd { samsung,pins = "gpc1-1"; samsung,pin-function = <2>; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 7a56852..9103f23 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -80,8 +80,11 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 + &sd0_rclk>; bus-width = <8>; cap-mmc-highspeed; }; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index c833bac..412f41d 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -654,15 +654,18 @@ num-slots = <1>; broken-cd; mmc-hs200-1_8v; + mmc-hs400-1_8v; cap-mmc-highspeed; non-removable; card-detect-delay = <200>; - clock-frequency = <400000000>; + clock-frequency = <800000000>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; bus-width = <8>; }; -- cgit v0.10.2 From f27b907595fc586bce62b8a3dc421e89bb927250 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Fri, 27 Mar 2015 01:55:10 +0900 Subject: ARM: dts: Fixed typo interrupt-cells for exynos5420 and exynos5250 Changes fixes the misspelled of #interrups-cell. arch/arm/boot/dts/exynos5420.dtsi:224: WARNING: 'interrups' may be misspelled - perhaps 'interrupts'? Tested on OdroidXU3 board. Signed-off-by: Anand Moon [kgene@kernel.org: added fixing same typo in exynos5250] Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 9bb1b0b..c411bdf 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -134,7 +134,7 @@ compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; interrupt-controller; - #interrups-cells = <2>; + #interrupt-cells = <2>; interrupt-parent = <&mct_map>; interrupts = <0 0>, <1 0>, <2 0>, <3 0>, <4 0>, <5 0>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index d4d643e..bff96e3 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -221,7 +221,7 @@ compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; interrupt-controller; - #interrups-cells = <1>; + #interrupt-cells = <1>; interrupt-parent = <&mct_map>; interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>, <11>; -- cgit v0.10.2 From 552644687838089766457612f6dcf1c897ea09a8 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Tue, 17 Mar 2015 10:36:11 +0100 Subject: of: Add binding for NVIDIA Tegra ACTMON node This block gathers statistics about various counters and can be configured to fire interrupts when thresholds are crossed. Signed-off-by: Tomeu Vizoso Reviewed-by: Alexandre Courbot [treding@nvidia.com: rename document, minor cleanups] Signed-off-by: Thierry Reding diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt new file mode 100644 index 0000000..ea670a5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt @@ -0,0 +1,32 @@ +NVIDIA Tegra Activity Monitor + +The activity monitor block collects statistics about the behaviour of other +components in the system. This information can be used to derive the rate at +which the external memory needs to be clocked in order to serve all requests +from the monitored clients. + +Required properties: +- compatible: should be "nvidia,tegra-actmon" +- reg: offset and length of the register set for the device +- interrupts: standard interrupt property +- clocks: Must contain a phandle and clock specifier pair for each entry in +clock-names. See ../../clock/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - actmon + - emc +- resets: Must contain an entry for each entry in reset-names. See +../../reset/reset.txt for details. +- reset-names: Must include the following entries: + - actmon + +Example: + actmon@6000c800 { + compatible = "nvidia,tegra124-actmon"; + reg = <0x0 0x6000c800 0x0 0x400>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_ACTMON>, + <&tegra_car TEGRA124_CLK_EMC>; + clock-names = "actmon", "emc"; + resets = <&tegra_car 119>; + reset-names = "actmon"; + }; -- cgit v0.10.2 From c5f8e8ca09e5700cb643ffa78d311f43a16e6432 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Tue, 17 Mar 2015 10:36:18 +0100 Subject: ARM: tegra: Add Tegra124 ACTMON support Add device node for the ACTMON block to the Tegra124 device tree. Signed-off-by: Tomeu Vizoso Reviewed-by: Alexandre Courbot Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 4be06c6..f992557 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -214,6 +214,17 @@ reg = <0x0 0x60007000 0x0 0x1000>; }; + actmon@0,6000c800 { + compatible = "nvidia,tegra124-actmon"; + reg = <0x0 0x6000c800 0x0 0x400>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_ACTMON>, + <&tegra_car TEGRA124_CLK_EMC>; + clock-names = "actmon", "emc"; + resets = <&tegra_car 119>; + reset-names = "actmon"; + }; + gpio: gpio@0,6000d000 { compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; reg = <0x0 0x6000d000 0x0 0x1000>; -- cgit v0.10.2 From b273c8873757a9f990d5aa62af7eeea168bc20c6 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Thu, 12 Mar 2015 15:48:00 +0100 Subject: ARM: tegra: Add EMC to Tegra124 device tree This adds a node for the EMC memory controller. It is always enabled, but only provides read-only functionality without board-specific timing tables. Signed-off-by: Mikko Perttunen Signed-off-by: Tomeu Vizoso Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index f992557..fefec80 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -207,6 +207,7 @@ reg = <0x0 0x60006000 0x0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + nvidia,external-memory-controller = <&emc>; }; flow-controller@0,60007000 { @@ -580,6 +581,13 @@ #iommu-cells = <1>; }; + emc: emc@0,7001b000 { + compatible = "nvidia,tegra124-emc"; + reg = <0x0 0x7001b000 0x0 0x1000>; + + nvidia,memory-controller = <&mc>; + }; + sata@0,70020000 { compatible = "nvidia,tegra124-ahci"; -- cgit v0.10.2 From 6e72cf002708ea636555beacda455cca4a5548d4 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Thu, 12 Mar 2015 15:48:01 +0100 Subject: ARM: tegra: Add EMC timings to Jetson TK1 device tree This adds a new file, tegra124-jetson-tk1-emc.dtsi that contains valid timings for the EMC memory clock. The file is included to the main Jetson TK1 device tree. The data is generated from the V5.0.17 version of the DVFS tables. Signed-off-by: Mikko Perttunen Signed-off-by: Tomeu Vizoso Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi new file mode 100644 index 0000000..2c5cede --- /dev/null +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -0,0 +1,2421 @@ +/ { + clock@0,60006000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + timing-396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + timing-528000000 { + clock-frequency = <528000000>; + nvidia,parent-clock-frequency = <528000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + timing-600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + timing-792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + timing-924000000 { + clock-frequency = <924000000>; + nvidia,parent-clock-frequency = <924000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + }; + + emc@0,7001b000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000060 + 0x00000000 + 0x00000018 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000005 + 0x00000005 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000064 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000007 + 0x00000000 + 0x00000042 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x800001c5 + 0x0000000a + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000005 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x0000009a + 0x00000000 + 0x00000026 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000006 + 0x00000006 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x000000a0 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x0000000b + 0x00000000 + 0x00000042 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000023a + 0x0000000a + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 + 0x0000000a + 0x00000000 + 0x00000001 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000134 + 0x00000000 + 0x0000004d + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000008 + 0x0000000f + 0x0000000c + 0x0000000c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000013f + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000015 + 0x00000000 + 0x00000042 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000370 + 0x0000000a + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 + 0x00000011 + 0x00000000 + 0x00000002 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000202 + 0x00000000 + 0x00000080 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x0000000f + 0x0000000f + 0x00000013 + 0x00000013 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000001 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000213 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000022 + 0x00000000 + 0x00000042 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000050e + 0x0000000a + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 + 0x0000001a + 0x00000000 + 0x00000003 + 0x00000001 + 0x00000004 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000304 + 0x00000000 + 0x000000c1 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000018 + 0x0000000f + 0x0000001c + 0x0000001c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000031c + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000033 + 0x00000000 + 0x00000042 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000713 + 0x0000000a + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008cd>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 + 0x00000035 + 0x00000000 + 0x00000006 + 0x00000002 + 0x00000005 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000004 + 0x00000006 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000003 + 0x0000000d + 0x0000000f + 0x00000011 + 0x00000607 + 0x00000000 + 0x00000181 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000032 + 0x0000000f + 0x00000038 + 0x00000038 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000006 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000638 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00008000 + 0x00000000 + 0x00000000 + 0x00008000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000707 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000066 + 0x00000000 + 0x00000100 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000d2b3 + 0x80000d22 + 0x0000000a + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0173000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d + 0x0000004d + 0x00000000 + 0x00000009 + 0x00000003 + 0x00000004 + 0x00000008 + 0x00000002 + 0x00000009 + 0x00000003 + 0x00000003 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000007 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x0000000e + 0x00000010 + 0x00000012 + 0x000008e4 + 0x00000000 + 0x00000239 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x0000004b + 0x0000000e + 0x00000052 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000008 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000924 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00098000 + 0x00098000 + 0x00000000 + 0x00098000 + 0x00098000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00050000 + 0x00050000 + 0x00050000 + 0x00050000 + 0x00005000 + 0x00005000 + 0x00005000 + 0x00005000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000096 + 0x00000000 + 0x00000100 + 0x0173000e + 0x00000000 + 0x00000003 + 0x000052a3 + 0x800012d7 + 0x00000009 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000011 + 0x00000066 + 0x00000000 + 0x0000000c + 0x00000004 + 0x00000004 + 0x00000008 + 0x00000002 + 0x0000000a + 0x00000004 + 0x00000004 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000001 + 0x00000008 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000f + 0x00000010 + 0x00000012 + 0x00000bd1 + 0x00000000 + 0x000002f4 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x00000063 + 0x0000000f + 0x0000006c + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x0000000b + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000c11 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00070000 + 0x00070000 + 0x00000000 + 0x00070000 + 0x00070000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00038000 + 0x00038000 + 0x00038000 + 0x00038000 + 0x00003800 + 0x00003800 + 0x00003800 + 0x00003800 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x000000c6 + 0x00000000 + 0x00000100 + 0x015b000e + 0x00000000 + 0x00000003 + 0x000052a3 + 0x8000188b + 0x00000009 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000941>; + nvidia,emc-mrs-wait-cnt = <0x0139000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000018 + 0x00000088 + 0x00000000 + 0x00000010 + 0x00000006 + 0x00000006 + 0x00000009 + 0x00000002 + 0x0000000d + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000001 + 0x00000009 + 0x00030000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000010 + 0x00000012 + 0x00000014 + 0x00000fd6 + 0x00000000 + 0x000003f5 + 0x00000002 + 0x0000000b + 0x00000001 + 0x00000000 + 0x00000085 + 0x00000012 + 0x00000090 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000010 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00001017 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe01200b1 + 0x00008000 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00054000 + 0x00054000 + 0x00000000 + 0x00054000 + 0x00054000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x0139000e + 0x00000000 + 0x00000003 + 0x000042a0 + 0x80002062 + 0x0000000a + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0127000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001b + 0x0000009b + 0x00000000 + 0x00000013 + 0x00000007 + 0x00000007 + 0x0000000b + 0x00000003 + 0x00000010 + 0x00000007 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000000a + 0x00000002 + 0x00000000 + 0x00000003 + 0x0000000b + 0x00070000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000002 + 0x00000012 + 0x00000016 + 0x00000018 + 0x00001208 + 0x00000000 + 0x00000482 + 0x00000002 + 0x0000000d + 0x00000001 + 0x00000000 + 0x00000097 + 0x00000015 + 0x000000a3 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000013 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00001248 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00e00b1 + 0x00008000 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x0127000e + 0x00000000 + 0x00000003 + 0x000040a0 + 0x800024aa + 0x0000000e + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f7000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000024 + 0x000000cd + 0x00000000 + 0x00000019 + 0x0000000a + 0x00000008 + 0x0000000d + 0x00000004 + 0x00000013 + 0x0000000a + 0x0000000a + 0x00000004 + 0x00000002 + 0x00000000 + 0x00000006 + 0x00000006 + 0x0000000b + 0x00000002 + 0x00000000 + 0x00000002 + 0x0000000d + 0x00080000 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000014 + 0x00000018 + 0x0000001a + 0x000017e2 + 0x00000000 + 0x000005f8 + 0x00000003 + 0x00000011 + 0x00000001 + 0x00000000 + 0x000000c7 + 0x00000018 + 0x000000d7 + 0x00000200 + 0x00000005 + 0x00000006 + 0x00000005 + 0x00000019 + 0x00000000 + 0x00000008 + 0x00000008 + 0x00001822 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00700b1 + 0x00008000 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00034000 + 0x00034000 + 0x00000000 + 0x00034000 + 0x00034000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000000 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x61861820 + 0x00514514 + 0x00514514 + 0x61861800 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x00f7000e + 0x00000000 + 0x00000004 + 0x00004080 + 0x80003012 + 0x0000000f + >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emc-auto-cal-config = <0xa1430303>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200020>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000f15>; + nvidia,emc-mrs-wait-cnt = <0x00cd000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x0000004c>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000002b + 0x000000f0 + 0x00000000 + 0x0000001e + 0x0000000b + 0x00000009 + 0x0000000f + 0x00000005 + 0x00000016 + 0x0000000b + 0x0000000b + 0x00000004 + 0x00000002 + 0x00000000 + 0x00000007 + 0x00000007 + 0x0000000d + 0x00000002 + 0x00000000 + 0x00000002 + 0x0000000f + 0x000a0000 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000016 + 0x0000001a + 0x0000001c + 0x00001be7 + 0x00000000 + 0x000006f9 + 0x00000004 + 0x00000015 + 0x00000001 + 0x00000000 + 0x000000e7 + 0x0000001b + 0x000000fb + 0x00000200 + 0x00000006 + 0x00000007 + 0x00000006 + 0x0000001e + 0x00000000 + 0x0000000a + 0x0000000a + 0x00001c28 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab898 + 0xe00400b1 + 0x00008000 + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000000 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x5d75d720 + 0x00514514 + 0x00514514 + 0x5d75d700 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000128 + 0x00cd000e + 0x00000000 + 0x00000004 + 0x00004080 + 0x800037ea + 0x00000011 + >; + }; + + }; + }; + + memory-controller@0,70019000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 + 0x8000000a + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x77e30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 + 0x80000012 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x76230303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 + 0x80000017 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x74a30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 + 0x8000001e + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x74230403 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 + 0x80000026 + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0503 + 0x73c30504 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 + 0x80000040 + 0x00000001 + 0x00000001 + 0x00000004 + 0x00000002 + 0x00000003 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040203 + 0x000a0504 + 0x73840a05 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000004 + 0x00000004 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000b0607 + 0x77450e08 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000005 + 0x00000006 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000d0709 + 0x7586120a + 0x70000f03 + 0x001f0000 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 + 0x80000040 + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000007 + 0x00000008 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000006 + 0x06050202 + 0x0010090c + 0x7428180d + 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 + 0x80000040 + 0x00000003 + 0x00000004 + 0x0000000e + 0x00000009 + 0x0000000a + 0x00000001 + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000007 + 0x07050202 + 0x00130b0e + 0x73a91b0f + 0x70000f03 + 0x001f0000 + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b + 0x80000040 + 0x00000004 + 0x00000005 + 0x00000013 + 0x0000000c + 0x0000000d + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000008 + 0x08060202 + 0x00170e13 + 0x736c2414 + 0x70000f02 + 0x001f0000 + >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emem-configuration = < + 0x0e00000d + 0x80000040 + 0x00000005 + 0x00000006 + 0x00000016 + 0x0000000e + 0x0000000f + 0x00000002 + 0x00000004 + 0x0000000e + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000009 + 0x09060202 + 0x001a1016 + 0x734e2a17 + 0x70000f02 + 0x001f0000 + >; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 528768a..ed8a8ac 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -3,6 +3,8 @@ #include #include "tegra124.dtsi" +#include "tegra124-jetson-tk1-emc.dtsi" + / { model = "NVIDIA Tegra124 Jetson TK1"; compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; -- cgit v0.10.2 From 3182c7c6c7244c0ecfc47dad35acfd5f67203a25 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Thu, 12 Mar 2015 15:48:08 +0100 Subject: ARM: tegra: Add EMC timings to Nyan Big device tree This adds a new file, tegra124-nyan-big-emc.dtsi that contains valid timings for the EMC memory clock. The file is included to the main device tree file for the Nyan Big. The frequency 528MHz is missing because we don't currently have a timing configuration that works. Additionally, only the timings for the ram-code 1 is present as that's what could be tested currently, though downstream has timings for more ram-codes. Signed-off-by: Tomeu Vizoso Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi new file mode 100644 index 0000000..1a5748d --- /dev/null +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -0,0 +1,2023 @@ +/ { + clock@0,60006000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + timing-396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + /* TODO: Add 528MHz frequency */ + timing-600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + timing-792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + }; + + emc@0,7001b000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000060 + 0x00000000 + 0x00000018 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000005 + 0x00000005 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000064 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000303 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000007 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x800001c5 + 0x0000000a + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000005 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x0000009a + 0x00000000 + 0x00000026 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000006 + 0x00000006 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x000000a0 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000303 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x0000000b + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000023a + 0x0000000a + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 + 0x0000000a + 0x00000000 + 0x00000001 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000134 + 0x00000000 + 0x0000004d + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000008 + 0x0000000f + 0x0000000c + 0x0000000c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000013f + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000303 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000015 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000370 + 0x0000000a + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 + 0x00000011 + 0x00000000 + 0x00000002 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000202 + 0x00000000 + 0x00000080 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x0000000f + 0x0000000f + 0x00000013 + 0x00000013 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000001 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000213 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000303 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000022 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000050e + 0x0000000a + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 + 0x0000001a + 0x00000000 + 0x00000003 + 0x00000001 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000304 + 0x00000000 + 0x000000c1 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000018 + 0x0000000f + 0x0000001c + 0x0000001c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000003 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000031c + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000303 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000033 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000713 + 0x0000000a + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x0000088d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 + 0x00000035 + 0x00000000 + 0x00000007 + 0x00000002 + 0x00000005 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000004 + 0x00000006 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000003 + 0x0000000d + 0x0000000f + 0x00000011 + 0x00000607 + 0x00000000 + 0x00000181 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000032 + 0x0000000f + 0x00000038 + 0x00000038 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000007 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000638 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00004000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00090000 + 0x00090000 + 0x00094000 + 0x00094000 + 0x00009400 + 0x00009000 + 0x00009000 + 0x00009000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000303 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000066 + 0x00000000 + 0x00000100 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000d2b3 + 0x80000d22 + 0x0000000a + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0174000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d + 0x0000004c + 0x00000000 + 0x00000009 + 0x00000003 + 0x00000004 + 0x00000008 + 0x00000002 + 0x00000009 + 0x00000003 + 0x00000003 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000007 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x0000000e + 0x00000010 + 0x00000012 + 0x000008e4 + 0x00000000 + 0x00000239 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x0000004a + 0x0000000e + 0x00000051 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000009 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000924 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00098000 + 0x00098000 + 0x00000000 + 0x00098000 + 0x00098000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00060000 + 0x00060000 + 0x00060000 + 0x00060000 + 0x00006000 + 0x00006000 + 0x00006000 + 0x00006000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000101 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000096 + 0x00000000 + 0x00000100 + 0x0174000c + 0x00000000 + 0x00000003 + 0x000052a3 + 0x800012d7 + 0x00000009 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000012 + 0x00000065 + 0x00000000 + 0x0000000c + 0x00000004 + 0x00000005 + 0x00000008 + 0x00000002 + 0x0000000a + 0x00000004 + 0x00000004 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000001 + 0x00000008 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000f + 0x00000010 + 0x00000012 + 0x00000bd1 + 0x00000000 + 0x000002f4 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x00000063 + 0x0000000f + 0x0000006b + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x0000000d + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000c11 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00070000 + 0x00070000 + 0x00000000 + 0x00070000 + 0x00070000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00048000 + 0x00048000 + 0x00004800 + 0x00004800 + 0x00004800 + 0x00004800 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000101 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x000000c6 + 0x00000000 + 0x00000100 + 0x015b000c + 0x00000000 + 0x00000003 + 0x000052a3 + 0x8000188b + 0x00000009 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0128000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001c + 0x0000009a + 0x00000000 + 0x00000013 + 0x00000007 + 0x00000007 + 0x0000000b + 0x00000003 + 0x00000010 + 0x00000007 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000000a + 0x00000002 + 0x00000000 + 0x00000003 + 0x0000000b + 0x00070000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000002 + 0x00000012 + 0x00000016 + 0x00000018 + 0x00001208 + 0x00000000 + 0x00000482 + 0x00000002 + 0x0000000d + 0x00000001 + 0x00000000 + 0x00000096 + 0x00000015 + 0x000000a2 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000015 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00001249 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00e00b1 + 0x00008000 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x00000004 + 0x00000002 + 0x00000005 + 0x00000006 + 0x00000003 + 0x00000006 + 0x00000005 + 0x00000004 + 0x00000004 + 0x00000002 + 0x00000005 + 0x00000006 + 0x00000003 + 0x00000006 + 0x00000005 + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000101 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x0128000c + 0x00000000 + 0x00000003 + 0x000040a0 + 0x800024aa + 0x0000000e + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0080089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200418>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f8000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000025 + 0x000000cc + 0x00000000 + 0x0000001a + 0x00000009 + 0x00000008 + 0x0000000d + 0x00000004 + 0x00000013 + 0x00000009 + 0x00000009 + 0x00000003 + 0x00000002 + 0x00000000 + 0x00000006 + 0x00000006 + 0x0000000b + 0x00000002 + 0x00000000 + 0x00000002 + 0x0000000d + 0x00080000 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000014 + 0x00000018 + 0x0000001a + 0x000017e2 + 0x00000000 + 0x000005f8 + 0x00000003 + 0x00000011 + 0x00000001 + 0x00000000 + 0x000000c6 + 0x00000018 + 0x000000d6 + 0x00000200 + 0x00000005 + 0x00000006 + 0x00000005 + 0x0000001d + 0x00000000 + 0x00000008 + 0x00000008 + 0x00001822 + 0x00000000 + 0x80000005 + 0x00000000 + 0x104ab198 + 0xe00700b1 + 0x00008000 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00034000 + 0x00034000 + 0x00000000 + 0x00034000 + 0x00034000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000008 + 0x00000008 + 0x00000005 + 0x00000009 + 0x00000009 + 0x00000007 + 0x00000009 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000005 + 0x00000009 + 0x00000009 + 0x00000007 + 0x00000009 + 0x00000008 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000101 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x61861820 + 0x00514514 + 0x00514514 + 0x61861800 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x00f8000c + 0x00000007 + 0x00000004 + 0x00004080 + 0x80003012 + 0x0000000f + >; + }; + + }; + }; + + memory-controller@0,70019000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 + 0x8000000a + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x77e30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 + 0x80000012 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x76230303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 + 0x80000017 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74a30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 + 0x8000001e + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74230403 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 + 0x80000026 + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0403 + 0x73c30504 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 + 0x80000040 + 0x00000001 + 0x00000001 + 0x00000005 + 0x00000002 + 0x00000004 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040203 + 0x000a0405 + 0x73840a06 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000004 + 0x00000005 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000b0607 + 0x77450e08 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000005 + 0x00000007 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000d0709 + 0x7586120a + 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 + 0x80000040 + 0x00000003 + 0x00000004 + 0x0000000e + 0x00000009 + 0x0000000b + 0x00000001 + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000007 + 0x07050202 + 0x00130b0e + 0x73a91b0f + 0x70000f03 + 0x001f0000 + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b + 0x80000040 + 0x00000004 + 0x00000005 + 0x00000013 + 0x0000000c + 0x0000000f + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000008 + 0x08060202 + 0x00160d13 + 0x734c2414 + 0x70000f02 + 0x001f0000 + >; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts index d34661b..2d21253 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big.dts +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -2,6 +2,8 @@ #include "tegra124-nyan.dtsi" +#include "tegra124-nyan-big-emc.dtsi" + / { model = "Acer Chromebook 13 CB5-311"; compatible = "google,nyan-big", "nvidia,tegra124"; -- cgit v0.10.2 From 03650bd2010b117c5c16a75278b0d01def8e9376 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Thu, 12 Mar 2015 15:48:09 +0100 Subject: ARM: tegra: Add EMC timings to Nyan Blaze device tree This adds a new file, tegra124-nyan-blaze-emc.dtsi that contains valid timings for the EMC memory clock. The file is included to the main device tree file for the Nyan Blaze. The frequency 528MHz is missing because we don't currently have a timing configuration that works. Additionally, only the timings for the ram-code 1 is present as that's what could be tested currently, though downstream has timings for more ram-codes. Signed-off-by: Tomeu Vizoso Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi new file mode 100644 index 0000000..9ecd108 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi @@ -0,0 +1,2049 @@ +/ { + clock@0,60006000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + timing-396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + /* TODO: Add 528MHz frequency */ + timing-600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + timing-792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + }; + + emc@0,7001b000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000060 + 0x00000000 + 0x00000018 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000005 + 0x00000005 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000064 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000007 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x800001c5 + 0x0000000a + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000005 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x0000009a + 0x00000000 + 0x00000026 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000006 + 0x00000006 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x000000a0 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x0000000b + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000023a + 0x0000000a + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 + 0x0000000a + 0x00000000 + 0x00000001 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000134 + 0x00000000 + 0x0000004d + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000008 + 0x0000000f + 0x0000000c + 0x0000000c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000013f + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000015 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000370 + 0x0000000a + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 + 0x00000011 + 0x00000000 + 0x00000002 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000202 + 0x00000000 + 0x00000080 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x0000000f + 0x0000000f + 0x00000013 + 0x00000013 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000001 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000213 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000022 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000050e + 0x0000000a + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 + 0x0000001a + 0x00000000 + 0x00000003 + 0x00000001 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000304 + 0x00000000 + 0x000000c1 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000018 + 0x0000000f + 0x0000001c + 0x0000001c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000003 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000031c + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000033 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000713 + 0x0000000a + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x0000088d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 + 0x00000035 + 0x00000000 + 0x00000007 + 0x00000002 + 0x00000005 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000004 + 0x00000006 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000003 + 0x0000000d + 0x0000000f + 0x00000011 + 0x00000607 + 0x00000000 + 0x00000181 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000032 + 0x0000000f + 0x00000038 + 0x00000038 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000007 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000638 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000066 + 0x00000000 + 0x00000100 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000d2b3 + 0x80000d22 + 0x0000000a + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0174000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d + 0x0000004c + 0x00000000 + 0x00000009 + 0x00000003 + 0x00000004 + 0x00000008 + 0x00000002 + 0x00000009 + 0x00000003 + 0x00000003 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000007 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x0000000e + 0x00000010 + 0x00000012 + 0x000008e4 + 0x00000000 + 0x00000239 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x0000004a + 0x0000000e + 0x00000051 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000009 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000924 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00090000 + 0x00090000 + 0x00000000 + 0x00090000 + 0x00090000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00060000 + 0x00060000 + 0x00060000 + 0x00060000 + 0x00006000 + 0x00006000 + 0x00006000 + 0x00006000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000202 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000096 + 0x00000000 + 0x00000100 + 0x0174000c + 0x00000000 + 0x00000003 + 0x000052a3 + 0x800012d7 + 0x00000009 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000012 + 0x00000065 + 0x00000000 + 0x0000000c + 0x00000004 + 0x00000005 + 0x00000008 + 0x00000002 + 0x0000000a + 0x00000004 + 0x00000004 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000001 + 0x00000008 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000f + 0x00000010 + 0x00000012 + 0x00000bd1 + 0x00000000 + 0x000002f4 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x00000063 + 0x0000000f + 0x0000006b + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x0000000d + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000c11 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00068000 + 0x00068000 + 0x00000000 + 0x00068000 + 0x00068000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00058000 + 0x00058000 + 0x00058000 + 0x00058000 + 0x00005800 + 0x00005800 + 0x00005800 + 0x00005800 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000202 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x000000c6 + 0x00000000 + 0x00000100 + 0x015b000c + 0x00000000 + 0x00000003 + 0x000052a3 + 0x8000188b + 0x00000009 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0128000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001c + 0x0000009a + 0x00000000 + 0x00000013 + 0x00000007 + 0x00000007 + 0x0000000b + 0x00000003 + 0x00000010 + 0x00000007 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000000a + 0x00000002 + 0x00000000 + 0x00000003 + 0x0000000b + 0x00070000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000002 + 0x00000012 + 0x00000016 + 0x00000018 + 0x00001208 + 0x00000000 + 0x00000482 + 0x00000002 + 0x0000000d + 0x00000001 + 0x00000000 + 0x00000096 + 0x00000015 + 0x000000a2 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000015 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00001248 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00e00b1 + 0x00008000 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00040000 + 0x00040000 + 0x00000000 + 0x00040000 + 0x00040000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x00000004 + 0x00000001 + 0x00000005 + 0x00000007 + 0x00000004 + 0x00000006 + 0x00000007 + 0x00000004 + 0x00000004 + 0x00000001 + 0x00000005 + 0x00000007 + 0x00000004 + 0x00000006 + 0x00000007 + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000202 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x0128000c + 0x00000000 + 0x00000003 + 0x000040a0 + 0x800024a9 + 0x0000000e + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f8000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000025 + 0x000000cc + 0x00000000 + 0x0000001a + 0x00000009 + 0x00000008 + 0x0000000d + 0x00000004 + 0x00000013 + 0x00000009 + 0x00000009 + 0x00000003 + 0x00000002 + 0x00000000 + 0x00000006 + 0x00000006 + 0x0000000b + 0x00000002 + 0x00000000 + 0x00000002 + 0x0000000d + 0x00080000 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000014 + 0x00000018 + 0x0000001a + 0x000017e2 + 0x00000000 + 0x000005f8 + 0x00000003 + 0x00000011 + 0x00000001 + 0x00000000 + 0x000000c6 + 0x00000018 + 0x000000d6 + 0x00000200 + 0x00000005 + 0x00000006 + 0x00000005 + 0x0000001d + 0x00000000 + 0x00000008 + 0x00000008 + 0x00001822 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00700b1 + 0x00008000 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000008 + 0x00000008 + 0x00000005 + 0x00000008 + 0x0000000a + 0x00000008 + 0x0000000a + 0x0000000a + 0x00000008 + 0x00000008 + 0x00000005 + 0x00000008 + 0x0000000a + 0x00000008 + 0x0000000a + 0x0000000a + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000202 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x61861820 + 0x00492492 + 0x00492492 + 0x61861800 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x00f8000c + 0x00000000 + 0x00000004 + 0x00004080 + 0x80003012 + 0x0000000f + >; + }; + + }; + }; + + memory-controller@0,70019000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 + 0x8000000a + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x77e30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 + 0x80000012 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x76230303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 + 0x80000017 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74a30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 + 0x8000001e + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74230403 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 + 0x80000026 + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0403 + 0x73c30504 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 + 0x80000040 + 0x00000001 + 0x00000001 + 0x00000005 + 0x00000002 + 0x00000004 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040203 + 0x000a0405 + 0x73840a06 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000004 + 0x00000005 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000b0607 + 0x77450e08 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000005 + 0x00000007 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000d0709 + 0x7586120a + 0x70000f03 + 0x001f0000 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 + 0x80000040 + 0x00000002 + 0x00000003 + 0x0000000d + 0x00000008 + 0x0000000a + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000006 + 0x06050202 + 0x0010090d + 0x7428180e + 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 + 0x80000040 + 0x00000003 + 0x00000004 + 0x0000000e + 0x00000009 + 0x0000000b + 0x00000001 + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000007 + 0x07050202 + 0x00130b0e + 0x73a91b0f + 0x70000f03 + 0x001f0000 + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b + 0x80000040 + 0x00000004 + 0x00000005 + 0x00000013 + 0x0000000c + 0x0000000f + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000008 + 0x08060202 + 0x00160d13 + 0x734c2414 + 0x70000f02 + 0x001f0000 + >; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts index e6e6b80..0d30c51 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze.dts +++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts @@ -2,6 +2,8 @@ #include "tegra124-nyan.dtsi" +#include "tegra124-nyan-blaze-emc.dtsi" + / { model = "HP Chromebook 14"; compatible = "google,nyan-blaze", "google,nyan", "nvidia,tegra124"; -- cgit v0.10.2 From 979275897e5c52945ae10adba98453cf9e2715d2 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 17 Mar 2015 11:14:33 +0100 Subject: dt-bindings: ARM: Mediatek: document binding for the PMIC wrapper This adds documentation for the PMIC wrapper unit found on Mediatek SoCs. Currently support are the MT8135 and MT8173 SoCs, but the PMIC wrapper can also be found on MT6xxx and possibly other SoCs. Signed-off-by: Sascha Hauer Signed-off-by: Matthias Brugger diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt new file mode 100644 index 0000000..ddeb5b6 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt @@ -0,0 +1,58 @@ +MediaTek PMIC Wrapper Driver + +This document describes the binding for the MediaTek PMIC wrapper. + +On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface +is not directly visible to the CPU, but only through the PMIC wrapper +inside the SoC. The communication between the SoC and the PMIC can +optionally be encrypted. Also a non standard Dual IO SPI mode can be +used to increase speed. + +IP Pairing + +on MT8135 the pins of some SoC internal peripherals can be on the PMIC. +The signals of these pins are routed over the SPI bus using the pwrap +bridge. In the binding description below the properties needed for bridging +are marked with "IP Pairing". These are optional on SoCs which do not support +IP Pairing + +Required properties in pwrap device node. +- compatible: + "mediatek,mt8135-pwrap" for MT8135 SoCs + "mediatek,mt8173-pwrap" for MT8173 SoCs +- interrupts: IRQ for pwrap in SOC +- reg-names: Must include the following entries: + "pwrap": Main registers base + "pwrap-bridge": bridge base (IP Pairing) +- reg: Must contain an entry for each entry in reg-names. +- reset-names: Must include the following entries: + "pwrap" + "pwrap-bridge" (IP Pairing) +- resets: Must contain an entry for each entry in reset-names. +- clock-names: Must include the following entries: + "spi": SPI bus clock + "wrap": Main module clock +- clocks: Must contain an entry for each entry in clock-names. + +Optional properities: +- pmic: Mediatek PMIC MFD is the child device of pwrap + See the following for child node definitions: + Documentation/devicetree/bindings/mfd/mt6397.txt + +Example: + pwrap: pwrap@1000f000 { + compatible = "mediatek,mt8135-pwrap"; + reg = <0 0x1000f000 0 0x1000>, + <0 0x11017000 0 0x1000>; + reg-names = "pwrap", "pwrap-bridge"; + interrupts = ; + resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, + <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; + reset-names = "pwrap", "pwrap-bridge"; + clocks = <&clk26m>, <&clk26m>; + clock-names = "spi", "wrap"; + + pmic { + compatible = "mediatek,mt6397"; + }; + }; -- cgit v0.10.2 From 85fc20b2ad9937fccbff3b47841f33d47e5e62c8 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Mon, 16 Mar 2015 10:47:25 +0100 Subject: ARM: DTS: Add watchdog to mt6589 This patch adds the watchdog to the device tree of Mediatek mt6589 SoC. Signed-off-by: Matthias Brugger diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi index 106b61b..88b3cb1 100644 --- a/arch/arm/boot/dts/mt6589.dtsi +++ b/arch/arm/boot/dts/mt6589.dtsi @@ -138,5 +138,10 @@ clocks = <&uart_clk>; status = "disabled"; }; + + wdt: watchdog@010000000 { + compatible = "mediatek,mt6589-wdt"; + reg = <0x10000000 0x44>; + }; }; }; -- cgit v0.10.2 From d24363a5a40a3b7f976faada311b623fc8047b1e Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Wed, 1 Apr 2015 17:05:54 -0700 Subject: ARM: dts: fix typo in makefile for alpine-db File uses dash in the filename, not underscore. Reported-by: Russell King Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4e1b387..a1f1aa7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1,7 +1,7 @@ ifeq ($(CONFIG_OF),y) dtb-$(CONFIG_ARCH_ALPINE) += \ - alpine_db.dtb + alpine-db.dtb dtb-$(CONFIG_MACH_ASM9260) += \ alphascale-asm9260-devkit.dtb # Keep at91 dtb files sorted alphabetically for each SoC -- cgit v0.10.2 From 6054ef25e20219a604429c1437bc601f8ead87a4 Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Fri, 3 Apr 2015 11:24:26 -0700 Subject: ARM: dts: fix typo in bcm7445.dtsi Reported-by: Brian Norris Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi index 9eaeac8..39ac784 100644 --- a/arch/arm/boot/dts/bcm7445.dtsi +++ b/arch/arm/boot/dts/bcm7445.dtsi @@ -97,7 +97,7 @@ reg = <0x452000 0x100>; }; - irq0_intc: interrupt-controller@f040a780 { + irq0_intc: interrupt-controller@40a780 { compatible = "brcm,bcm7120-l2-intc"; interrupt-parent = <&gic>; #interrupt-cells = <1>; -- cgit v0.10.2 From 2d9ad4f85ed43101f55816472895e112203f9881 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 4 Mar 2015 13:52:44 -0600 Subject: arm: qcom: dts: gic: add compatible string for Qualcomm MSM GICs Document the Qualcomm MSM GICs implementation as compatible with the ARM GIC standard. Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt index c97484b..6204630 100644 --- a/Documentation/devicetree/bindings/arm/gic.txt +++ b/Documentation/devicetree/bindings/arm/gic.txt @@ -18,6 +18,8 @@ Main node required properties: "arm,arm11mp-gic" "brcm,brahma-b15-gic" "arm,arm1176jzf-devchip-gic" + "qcom,msm-8660-qgic" + "qcom,msm-qgic2" - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an interrupt source. The type shall be a and the value shall be 3. -- cgit v0.10.2 From a8b21018de2ec8864176670c87015b19babdfe58 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Mon, 9 Feb 2015 16:01:07 -0600 Subject: mfd: qcom,tcsr: Add device tree binding for TCSR This patch adds the device tree binding for the Qualcomm Top Control and Status Register device. The TCSR is comprised of a set of registers that provide various control and status functions for attached peripherals. Signed-off-by: Andy Gross Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt new file mode 100644 index 0000000..e90519d --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt @@ -0,0 +1,22 @@ +QCOM Top Control and Status Register + +Qualcomm devices have a set of registers that provide various control and status +functions for their peripherals. This node is intended to allow access to these +registers via syscon. + +Required properties: +- compatible: Should contain: + "qcom,tcsr-ipq8064", "syscon" for IPQ8064 + "qcom,tcsr-apq8064", "syscon" for APQ8064 + "qcom,tcsr-msm8660", "syscon" for MSM8660 + "qcom,tcsr-msm8960", "syscon" for MSM8960 + "qcom,tcsr-msm8974", "syscon" for MSM8974 + "qcom,tcsr-apq8084", "syscon" for APQ8084 + "qcom,tcsr-msm8916", "syscon" for MSM8916 +- reg: Address range for TCSR registers + +Example: + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-msm8960", "syscon"; + reg = <0x1a400000 0x100>; + }; -- cgit v0.10.2 From 4105d9d60a7f28a60198302e8d4b79bd308cac35 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Mon, 9 Feb 2015 16:01:08 -0600 Subject: arm: dts: qcom: Add TCSR support for APQ8064 This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by: Andy Gross Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index b3154c0..f607900 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -166,6 +166,7 @@ gsbi1: gsbi@12440000 { status = "disabled"; compatible = "qcom,gsbi-v1.0.0"; + cell-index = <1>; reg = <0x12440000 0x100>; clocks = <&gcc GSBI1_H_CLK>; clock-names = "iface"; @@ -173,6 +174,8 @@ #size-cells = <1>; ranges; + syscon-tcsr = <&tcsr>; + i2c1: i2c@12460000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x12460000 0x1000>; @@ -187,6 +190,7 @@ gsbi2: gsbi@12480000 { status = "disabled"; compatible = "qcom,gsbi-v1.0.0"; + cell-index = <2>; reg = <0x12480000 0x100>; clocks = <&gcc GSBI2_H_CLK>; clock-names = "iface"; @@ -194,6 +198,8 @@ #size-cells = <1>; ranges; + syscon-tcsr = <&tcsr>; + i2c2: i2c@124a0000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x124a0000 0x1000>; @@ -208,6 +214,7 @@ gsbi7: gsbi@16600000 { status = "disabled"; compatible = "qcom,gsbi-v1.0.0"; + cell-index = <7>; reg = <0x16600000 0x100>; clocks = <&gcc GSBI7_H_CLK>; clock-names = "iface"; @@ -215,6 +222,8 @@ #size-cells = <1>; ranges; + syscon-tcsr = <&tcsr>; + serial@16640000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16640000 0x1000>, @@ -349,5 +358,10 @@ pinctrl-0 = <&sdc4_gpios>; }; }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-apq8064", "syscon"; + reg = <0x1a400000 0x100>; + }; }; }; -- cgit v0.10.2 From 4d9b766bfe08d63ca1b6867be005a7bc603f9985 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Mon, 9 Feb 2015 16:01:09 -0600 Subject: arm: dts: qcom: Add TCSR support for IPQ8064 This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by: Andy Gross Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index cb225da..4e01f71 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -120,6 +120,7 @@ gsbi2: gsbi@12480000 { compatible = "qcom,gsbi-v1.0.0"; + cell-index = <2>; reg = <0x12480000 0x100>; clocks = <&gcc GSBI2_H_CLK>; clock-names = "iface"; @@ -128,6 +129,8 @@ ranges; status = "disabled"; + syscon-tcsr = <&tcsr>; + serial@12490000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x12490000 0x1000>, @@ -155,6 +158,7 @@ gsbi4: gsbi@16300000 { compatible = "qcom,gsbi-v1.0.0"; + cell-index = <4>; reg = <0x16300000 0x100>; clocks = <&gcc GSBI4_H_CLK>; clock-names = "iface"; @@ -163,6 +167,8 @@ ranges; status = "disabled"; + syscon-tcsr = <&tcsr>; + serial@16340000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16340000 0x1000>, @@ -189,6 +195,7 @@ gsbi5: gsbi@1a200000 { compatible = "qcom,gsbi-v1.0.0"; + cell-index = <5>; reg = <0x1a200000 0x100>; clocks = <&gcc GSBI5_H_CLK>; clock-names = "iface"; @@ -197,6 +204,8 @@ ranges; status = "disabled"; + syscon-tcsr = <&tcsr>; + serial@1a240000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x1a240000 0x1000>, @@ -279,5 +288,10 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-ipq8064", "syscon"; + reg = <0x1a400000 0x100>; + }; }; }; -- cgit v0.10.2 From da047acd173478fd0dd901bfd268d91d35c4f4b8 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Mon, 9 Feb 2015 16:01:10 -0600 Subject: arm: dts: qcom: Add TCSR support for MSM8660 This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by: Andy Gross Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 0affd61..20bbd19 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -82,6 +82,7 @@ gsbi12: gsbi@19c00000 { compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; reg = <0x19c00000 0x100>; clocks = <&gcc GSBI12_H_CLK>; clock-names = "iface"; @@ -89,6 +90,8 @@ #size-cells = <1>; ranges; + syscon-tcsr = <&tcsr>; + serial@19c40000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x19c40000 0x1000>, @@ -196,6 +199,11 @@ vmmc-supply = <&vsdcc_fixed>; }; }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-msm8660", "syscon"; + reg = <0x1a400000 0x100>; + }; }; }; -- cgit v0.10.2 From 3860d43c807c40ad6193280716be2f241f7a4c28 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Mon, 9 Feb 2015 16:01:11 -0600 Subject: arm: dts: qcom: Add TCSR support for MSM8960 This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by: Andy Gross Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index e1b0d5c..27b856a 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -122,6 +122,7 @@ gsbi5: gsbi@16400000 { compatible = "qcom,gsbi-v1.0.0"; + cell-index = <5>; reg = <0x16400000 0x100>; clocks = <&gcc GSBI5_H_CLK>; clock-names = "iface"; @@ -129,6 +130,8 @@ #size-cells = <1>; ranges; + syscon-tcsr = <&tcsr>; + serial@16440000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16440000 0x1000>, @@ -238,5 +241,10 @@ vmmc-supply = <&vsdcc_fixed>; }; }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-msm8960", "syscon"; + reg = <0x1a400000 0x100>; + }; }; }; -- cgit v0.10.2 From 1e1177bf4c24d593afddf40f9f63538136aee6c9 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 28 Jan 2015 13:36:12 -0800 Subject: arm: dts: qcom: Add LCC nodes Add the node for the LPASS clock controller found on a few qcom SoCs so that the clock driver can probe. Signed-off-by: Rajendra Nayak Signed-off-by: Kumar Gala [sboyd@codeaurora.org: Added apq8064 and msm8960 nodes] Signed-off-by: Stephen Boyd Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index f607900..4e3e063 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -248,6 +248,13 @@ #reset-cells = <1>; }; + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-apq8064"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + mmcc: clock-controller@4000000 { compatible = "qcom,mmcc-apq8064"; reg = <0x4000000 0x1000>; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 4e01f71..5afaff9 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -293,5 +293,13 @@ compatible = "qcom,tcsr-ipq8064", "syscon"; reg = <0x1a400000 0x100>; }; + + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-ipq8064"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 27b856a..a02b984 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -91,6 +91,13 @@ reg = <0x900000 0x4000>; }; + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-msm8960"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + clock-controller@4000000 { compatible = "qcom,mmcc-msm8960"; reg = <0x4000000 0x1000>; -- cgit v0.10.2 From af22e46d3e8e29d7a1edb6f171745e4991d40cf1 Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Tue, 3 Feb 2015 14:17:58 +0200 Subject: arm: dts: qcom: Add SPMI PMIC Arbiter nodes for APQ8084 and MSM8974 Add SPMI PMIC Arbiter configuration nodes for APQ8084 and MSM8974. Signed-off-by: Ivan T. Ivanov Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 1f130bc..dbedf64 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -226,5 +226,21 @@ clock-names = "core", "iface"; status = "disabled"; }; + + spmi_bus: spmi@fc4cf000 { + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0xfc4cb000 0x1000>, + <0xfc4ca000 0x1000>; + interrupt-names = "periph_irq"; + interrupts = <0 190 0>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index e265ec1..2d11641 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -247,5 +247,21 @@ #address-cells = <1>; #size-cells = <0>; }; + + spmi_bus: spmi@fc4cf000 { + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0xfc4cb000 0x1000>, + <0xfc4ca000 0x1000>; + interrupt-names = "periph_irq"; + interrupts = <0 190 0>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; }; }; -- cgit v0.10.2 From c91278931d7b469d8203b7c3ea6d202df5832755 Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Tue, 3 Feb 2015 14:17:59 +0200 Subject: arm: dts: qcom: Add 8x74 chipset SPMI PMIC's nodes PM8841 and PM8941 have 2 SPMI devices per physical package. Add their configuration nodes and include them in boards which are using 8x74 based chipset. Signed-off-by: Ivan T. Ivanov Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index 4737049..d484d08 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -1,4 +1,6 @@ #include "qcom-msm8974.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" / { model = "Qualcomm APQ8074 Dragonboard"; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts index cccc21b..bd35b06 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts @@ -1,4 +1,6 @@ #include "qcom-msm8974.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" / { model = "Sony Xperia Z1"; diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom-pm8841.dtsi new file mode 100644 index 0000000..73813cc --- /dev/null +++ b/arch/arm/boot/dts/qcom-pm8841.dtsi @@ -0,0 +1,18 @@ +#include + +&spmi_bus { + + usid4: pm8841@4 { + compatible = "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + usid5: pm8841@5 { + compatible = "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi new file mode 100644 index 0000000..24c5088 --- /dev/null +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -0,0 +1,18 @@ +#include + +&spmi_bus { + + usid0: pm8941@0 { + compatible ="qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + usid1: pm8941@1 { + compatible ="qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; -- cgit v0.10.2 From e321cbbd55270bcced00ab73ea8e2ee1390861af Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Tue, 3 Feb 2015 14:18:00 +0200 Subject: arm: dts: qcom: Add APQ8084 chipset SPMI PMIC's nodes PMA8084 have 2 SPMI devices per physical package. Add their configuration nodes and include them in boards which are using AQP8084 based chipset. Signed-off-by: Ivan T. Ivanov Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts index c9ff108..f7725b9 100644 --- a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts +++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts @@ -1,4 +1,5 @@ #include "qcom-apq8084.dtsi" +#include "qcom-pma8084.dtsi" / { model = "Qualcomm APQ8084/IFC6540"; diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom-apq8084-mtp.dts index 8ecec58..cb43acf 100644 --- a/arch/arm/boot/dts/qcom-apq8084-mtp.dts +++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts @@ -1,4 +1,5 @@ #include "qcom-apq8084.dtsi" +#include "qcom-pma8084.dtsi" / { model = "Qualcomm APQ 8084-MTP"; diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi new file mode 100644 index 0000000..a5a4fe6 --- /dev/null +++ b/arch/arm/boot/dts/qcom-pma8084.dtsi @@ -0,0 +1,18 @@ +#include + +&spmi_bus { + + usid0: pma8084@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + usid1: pma8084@1 { + compatible = "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; -- cgit v0.10.2 From f49cadeb48a2717d1baaab701066bda9b69cfed4 Mon Sep 17 00:00:00 2001 From: Kenneth Westfield Date: Fri, 13 Mar 2015 01:01:08 -0700 Subject: arm: dts: qcom: Add LPASS Audio HW to IPQ8064 device tree Model the Qualcomm Technologies LPASS hardware for the ipq806x SOC. Signed-off-by: Kenneth Westfield Acked-by: Banajit Goswami Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 5afaff9..1bc5fdd 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -2,6 +2,7 @@ #include "skeleton.dtsi" #include +#include #include / { @@ -66,6 +67,21 @@ ranges; compatible = "simple-bus"; + lpass@28100000 { + compatible = "qcom,lpass-cpu"; + status = "disabled"; + clocks = <&lcc AHBIX_CLK>, + <&lcc MI2S_OSR_CLK>, + <&lcc MI2S_BIT_CLK>; + clock-names = "ahbix-clk", + "mi2s-osr-clk", + "mi2s-bit-clk"; + interrupts = <0 85 1>; + interrupt-names = "lpass-irq-lpaif"; + reg = <0x28100000 0x10000>; + reg-names = "lpass-lpaif"; + }; + qcom_pinmux: pinmux@800000 { compatible = "qcom,ipq8064-pinctrl"; reg = <0x800000 0x4000>; -- cgit v0.10.2 From 83bd147952ef5c8a99df27b8597ee21f2424348d Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Wed, 18 Mar 2015 16:08:21 +0200 Subject: dt-bindings: Add #defines for MSM8916 clocks and resets Add clocks/resets defines for the global clock controller found on Qualcomm MSM8916 SoCs. Signed-off-by: Georgi Djakov Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index aba3d25..54c23f3 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -8,6 +8,7 @@ Required properties : "qcom,gcc-apq8084" "qcom,gcc-ipq8064" "qcom,gcc-msm8660" + "qcom,gcc-msm8916" "qcom,gcc-msm8960" "qcom,gcc-msm8974" "qcom,gcc-msm8974pro" diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h new file mode 100644 index 0000000..e430f64 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h @@ -0,0 +1,156 @@ +/* + * Copyright 2015 Linaro Limited + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H +#define _DT_BINDINGS_CLK_MSM_GCC_8916_H + +#define GPLL0 0 +#define GPLL0_VOTE 1 +#define BIMC_PLL 2 +#define BIMC_PLL_VOTE 3 +#define GPLL1 4 +#define GPLL1_VOTE 5 +#define GPLL2 6 +#define GPLL2_VOTE 7 +#define PCNOC_BFDCD_CLK_SRC 8 +#define SYSTEM_NOC_BFDCD_CLK_SRC 9 +#define CAMSS_AHB_CLK_SRC 10 +#define APSS_AHB_CLK_SRC 11 +#define CSI0_CLK_SRC 12 +#define CSI1_CLK_SRC 13 +#define GFX3D_CLK_SRC 14 +#define VFE0_CLK_SRC 15 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27 +#define BLSP1_UART1_APPS_CLK_SRC 28 +#define BLSP1_UART2_APPS_CLK_SRC 29 +#define CCI_CLK_SRC 30 +#define CAMSS_GP0_CLK_SRC 31 +#define CAMSS_GP1_CLK_SRC 32 +#define JPEG0_CLK_SRC 33 +#define MCLK0_CLK_SRC 34 +#define MCLK1_CLK_SRC 35 +#define CSI0PHYTIMER_CLK_SRC 36 +#define CSI1PHYTIMER_CLK_SRC 37 +#define CPP_CLK_SRC 38 +#define CRYPTO_CLK_SRC 39 +#define GP1_CLK_SRC 40 +#define GP2_CLK_SRC 41 +#define GP3_CLK_SRC 42 +#define BYTE0_CLK_SRC 43 +#define ESC0_CLK_SRC 44 +#define MDP_CLK_SRC 45 +#define PCLK0_CLK_SRC 46 +#define VSYNC_CLK_SRC 47 +#define PDM2_CLK_SRC 48 +#define SDCC1_APPS_CLK_SRC 49 +#define SDCC2_APPS_CLK_SRC 50 +#define APSS_TCU_CLK_SRC 51 +#define USB_HS_SYSTEM_CLK_SRC 52 +#define VCODEC0_CLK_SRC 53 +#define GCC_BLSP1_AHB_CLK 54 +#define GCC_BLSP1_SLEEP_CLK 55 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63 +#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64 +#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65 +#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66 +#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67 +#define GCC_BLSP1_UART1_APPS_CLK 68 +#define GCC_BLSP1_UART2_APPS_CLK 69 +#define GCC_BOOT_ROM_AHB_CLK 70 +#define GCC_CAMSS_CCI_AHB_CLK 71 +#define GCC_CAMSS_CCI_CLK 72 +#define GCC_CAMSS_CSI0_AHB_CLK 73 +#define GCC_CAMSS_CSI0_CLK 74 +#define GCC_CAMSS_CSI0PHY_CLK 75 +#define GCC_CAMSS_CSI0PIX_CLK 76 +#define GCC_CAMSS_CSI0RDI_CLK 77 +#define GCC_CAMSS_CSI1_AHB_CLK 78 +#define GCC_CAMSS_CSI1_CLK 79 +#define GCC_CAMSS_CSI1PHY_CLK 80 +#define GCC_CAMSS_CSI1PIX_CLK 81 +#define GCC_CAMSS_CSI1RDI_CLK 82 +#define GCC_CAMSS_CSI_VFE0_CLK 83 +#define GCC_CAMSS_GP0_CLK 84 +#define GCC_CAMSS_GP1_CLK 85 +#define GCC_CAMSS_ISPIF_AHB_CLK 86 +#define GCC_CAMSS_JPEG0_CLK 87 +#define GCC_CAMSS_JPEG_AHB_CLK 88 +#define GCC_CAMSS_JPEG_AXI_CLK 89 +#define GCC_CAMSS_MCLK0_CLK 90 +#define GCC_CAMSS_MCLK1_CLK 91 +#define GCC_CAMSS_MICRO_AHB_CLK 92 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 93 +#define GCC_CAMSS_CSI1PHYTIMER_CLK 94 +#define GCC_CAMSS_AHB_CLK 95 +#define GCC_CAMSS_TOP_AHB_CLK 96 +#define GCC_CAMSS_CPP_AHB_CLK 97 +#define GCC_CAMSS_CPP_CLK 98 +#define GCC_CAMSS_VFE0_CLK 99 +#define GCC_CAMSS_VFE_AHB_CLK 100 +#define GCC_CAMSS_VFE_AXI_CLK 101 +#define GCC_CRYPTO_AHB_CLK 102 +#define GCC_CRYPTO_AXI_CLK 103 +#define GCC_CRYPTO_CLK 104 +#define GCC_OXILI_GMEM_CLK 105 +#define GCC_GP1_CLK 106 +#define GCC_GP2_CLK 107 +#define GCC_GP3_CLK 108 +#define GCC_MDSS_AHB_CLK 109 +#define GCC_MDSS_AXI_CLK 110 +#define GCC_MDSS_BYTE0_CLK 111 +#define GCC_MDSS_ESC0_CLK 112 +#define GCC_MDSS_MDP_CLK 113 +#define GCC_MDSS_PCLK0_CLK 114 +#define GCC_MDSS_VSYNC_CLK 115 +#define GCC_MSS_CFG_AHB_CLK 116 +#define GCC_OXILI_AHB_CLK 117 +#define GCC_OXILI_GFX3D_CLK 118 +#define GCC_PDM2_CLK 119 +#define GCC_PDM_AHB_CLK 120 +#define GCC_PRNG_AHB_CLK 121 +#define GCC_SDCC1_AHB_CLK 122 +#define GCC_SDCC1_APPS_CLK 123 +#define GCC_SDCC2_AHB_CLK 124 +#define GCC_SDCC2_APPS_CLK 125 +#define GCC_GTCU_AHB_CLK 126 +#define GCC_JPEG_TBU_CLK 127 +#define GCC_MDP_TBU_CLK 128 +#define GCC_SMMU_CFG_CLK 129 +#define GCC_VENUS_TBU_CLK 130 +#define GCC_VFE_TBU_CLK 131 +#define GCC_USB2A_PHY_SLEEP_CLK 132 +#define GCC_USB_HS_AHB_CLK 133 +#define GCC_USB_HS_SYSTEM_CLK 134 +#define GCC_VENUS0_AHB_CLK 135 +#define GCC_VENUS0_AXI_CLK 136 +#define GCC_VENUS0_VCODEC0_CLK 137 + +#endif diff --git a/include/dt-bindings/reset/qcom,gcc-msm8916.h b/include/dt-bindings/reset/qcom,gcc-msm8916.h new file mode 100644 index 0000000..3d90410 --- /dev/null +++ b/include/dt-bindings/reset/qcom,gcc-msm8916.h @@ -0,0 +1,108 @@ +/* + * Copyright 2015 Linaro Limited + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_MSM_GCC_8916_H +#define _DT_BINDINGS_RESET_MSM_GCC_8916_H + +#define GCC_BLSP1_BCR 0 +#define GCC_BLSP1_QUP1_BCR 1 +#define GCC_BLSP1_UART1_BCR 2 +#define GCC_BLSP1_QUP2_BCR 3 +#define GCC_BLSP1_UART2_BCR 4 +#define GCC_BLSP1_QUP3_BCR 5 +#define GCC_BLSP1_QUP4_BCR 6 +#define GCC_BLSP1_QUP5_BCR 7 +#define GCC_BLSP1_QUP6_BCR 8 +#define GCC_IMEM_BCR 9 +#define GCC_SMMU_BCR 10 +#define GCC_APSS_TCU_BCR 11 +#define GCC_SMMU_XPU_BCR 12 +#define GCC_PCNOC_TBU_BCR 13 +#define GCC_PRNG_BCR 14 +#define GCC_BOOT_ROM_BCR 15 +#define GCC_CRYPTO_BCR 16 +#define GCC_SEC_CTRL_BCR 17 +#define GCC_AUDIO_CORE_BCR 18 +#define GCC_ULT_AUDIO_BCR 19 +#define GCC_DEHR_BCR 20 +#define GCC_SYSTEM_NOC_BCR 21 +#define GCC_PCNOC_BCR 22 +#define GCC_TCSR_BCR 23 +#define GCC_QDSS_BCR 24 +#define GCC_DCD_BCR 25 +#define GCC_MSG_RAM_BCR 26 +#define GCC_MPM_BCR 27 +#define GCC_SPMI_BCR 28 +#define GCC_SPDM_BCR 29 +#define GCC_MM_SPDM_BCR 30 +#define GCC_BIMC_BCR 31 +#define GCC_RBCPR_BCR 32 +#define GCC_TLMM_BCR 33 +#define GCC_USB_HS_BCR 34 +#define GCC_USB2A_PHY_BCR 35 +#define GCC_SDCC1_BCR 36 +#define GCC_SDCC2_BCR 37 +#define GCC_PDM_BCR 38 +#define GCC_SNOC_BUS_TIMEOUT0_BCR 39 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 40 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 41 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 42 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 43 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 44 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 45 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 46 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 47 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 48 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 49 +#define GCC_MMSS_BCR 50 +#define GCC_VENUS0_BCR 51 +#define GCC_MDSS_BCR 52 +#define GCC_CAMSS_PHY0_BCR 53 +#define GCC_CAMSS_CSI0_BCR 54 +#define GCC_CAMSS_CSI0PHY_BCR 55 +#define GCC_CAMSS_CSI0RDI_BCR 56 +#define GCC_CAMSS_CSI0PIX_BCR 57 +#define GCC_CAMSS_PHY1_BCR 58 +#define GCC_CAMSS_CSI1_BCR 59 +#define GCC_CAMSS_CSI1PHY_BCR 60 +#define GCC_CAMSS_CSI1RDI_BCR 61 +#define GCC_CAMSS_CSI1PIX_BCR 62 +#define GCC_CAMSS_ISPIF_BCR 63 +#define GCC_CAMSS_CCI_BCR 64 +#define GCC_CAMSS_MCLK0_BCR 65 +#define GCC_CAMSS_MCLK1_BCR 66 +#define GCC_CAMSS_GP0_BCR 67 +#define GCC_CAMSS_GP1_BCR 68 +#define GCC_CAMSS_TOP_BCR 69 +#define GCC_CAMSS_MICRO_BCR 70 +#define GCC_CAMSS_JPEG_BCR 71 +#define GCC_CAMSS_VFE_BCR 72 +#define GCC_CAMSS_CSI_VFE0_BCR 73 +#define GCC_OXILI_BCR 74 +#define GCC_GMEM_BCR 75 +#define GCC_CAMSS_AHB_BCR 76 +#define GCC_MDP_TBU_BCR 77 +#define GCC_GFX_TBU_BCR 78 +#define GCC_GFX_TCU_BCR 79 +#define GCC_MSS_TBU_AXI_BCR 80 +#define GCC_MSS_TBU_GSS_AXI_BCR 81 +#define GCC_MSS_TBU_Q6_AXI_BCR 82 +#define GCC_GTCU_AHB_BCR 83 +#define GCC_SMMU_CFG_BCR 84 +#define GCC_VFE_TBU_BCR 85 +#define GCC_VENUS_TBU_BCR 86 +#define GCC_JPEG_TBU_BCR 87 +#define GCC_PRONTO_TBU_BCR 88 +#define GCC_SMMU_CATS_BCR 89 + +#endif -- cgit v0.10.2 From 005c5dc9b3dd72970992d05ea63f1148d020112c Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Wed, 25 Mar 2015 14:25:27 -0600 Subject: devicetree: bindings: Update qcom,saw2 node bindings Update qcom,saw2 node bindings with compatible strings to identify nodes that provides cpuidle functionality for a particular SoC. Remove unused compatible strings. Update examples for different SAW nodes. Signed-off-by: Lina Iyer Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt index 1505fb8..ae4afc6 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt @@ -2,22 +2,31 @@ SPM AVS Wrapper 2 (SAW2) The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable -micro-controller that transitions a piece of hardware (like a processor or +power-controller that transitions a piece of hardware (like a processor or subsystem) into and out of low power modes via a direct connection to the PMIC. It can also be wired up to interact with other processors in the system, notifying them when a low power state is entered or exited. +Multiple revisions of the SAW hardware are supported using these Device Nodes. +SAW2 revisions differ in the register offset and configuration data. Also, the +same revision of the SAW in different SoCs may have different configuration +data due the the differences in hardware capabilities. Hence the SoC name, the +version of the SAW hardware in that SoC and the distinction between cpu (big +or Little) or cache, may be needed to uniquely identify the SAW register +configuration and initialization data. The compatible string is used to +indicate this parameter. + PROPERTIES - compatible: Usage: required Value type: - Definition: shall contain "qcom,saw2". A more specific value should be - one of: - "qcom,saw2-v1" - "qcom,saw2-v1.1" - "qcom,saw2-v2" - "qcom,saw2-v2.1" + Definition: Must have + "qcom,saw2" + A more specific value could be one of: + "qcom,apq8064-saw2-v1.1-cpu" + "qcom,msm8974-saw2-v2.1-cpu" + "qcom,apq8084-saw2-v2.1-cpu" - reg: Usage: required @@ -26,10 +35,23 @@ PROPERTIES the register region. An optional second element specifies the base address and size of the alias register region. +- regulator: + Usage: optional + Value type: boolean + Definition: Indicates that this SPM device acts as a regulator device + device for the core (CPU or Cache) the SPM is attached + to. -Example: +Example 1: - regulator@2099000 { + power-controller@2099000 { compatible = "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + +Example 2: + saw0: power-controller@f9089000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; }; -- cgit v0.10.2 From 52cd8451818bffa25bec2f69bc6286b3cc045bf7 Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Wed, 25 Mar 2015 14:25:28 -0600 Subject: devicetree: bindings: Document qcom,idle-states Document cpuidle states of QCOM cpus. In addition to arm-idle-state compatible string, the ARM idle state definition must define one of the following compatible strings - "qcom,idle-state-ret", "qcom,idle-state-spc", "qcom,idle-state-pc", The compatibles helps the SPM platform driver to use the correct idle function when the index to the idle state is passed to the platform driver. Signed-off-by: Lina Iyer Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt new file mode 100644 index 0000000..06df04c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt @@ -0,0 +1,84 @@ +QCOM Idle States for cpuidle driver + +ARM provides idle-state node to define the cpuidle states, as defined in [1]. +cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle +states. Idle states have different enter/exit latency and residency values. +The idle states supported by the QCOM SoC are defined as - + + * Standby + * Retention + * Standalone Power Collapse (Standalone PC or SPC) + * Power Collapse (PC) + +Standby: Standby does a little more in addition to architectural clock gating. +When the WFI instruction is executed the ARM core would gate its internal +clocks. In addition to gating the clocks, QCOM cpus use this instruction as a +trigger to execute the SPM state machine. The SPM state machine waits for the +interrupt to trigger the core back in to active. This triggers the cache +hierarchy to enter standby states, when all cpus are idle. An interrupt brings +the SPM state machine out of its wait, the next step is to ensure that the +cache hierarchy is also out of standby, and then the cpu is allowed to resume +execution. This state is defined as a generic ARM WFI state by the ARM cpuidle +driver and is not defined in the DT. The SPM state machine should be +configured to execute this state by default and after executing every other +state below. + +Retention: Retention is a low power state where the core is clock gated and +the memory and the registers associated with the core are retained. The +voltage may be reduced to the minimum value needed to keep the processor +registers active. The SPM should be configured to execute the retention +sequence and would wait for interrupt, before restoring the cpu to execution +state. Retention may have a slightly higher latency than Standby. + +Standalone PC: A cpu can power down and warmboot if there is a sufficient time +between the time it enters idle and the next known wake up. SPC mode is used +to indicate a core entering a power down state without consulting any other +cpu or the system resources. This helps save power only on that core. The SPM +sequence for this idle state is programmed to power down the supply to the +core, wait for the interrupt, restore power to the core, and ensure the +system state including cache hierarchy is ready before allowing core to +resume. Applying power and resetting the core causes the core to warmboot +back into Elevation Level (EL) which trampolines the control back to the +kernel. Entering a power down state for the cpu, needs to be done by trapping +into a EL. Failing to do so, would result in a crash enforced by the warm boot +code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to +be flushed in s/w, before powering down the core. + +Power Collapse: This state is similar to the SPC mode, but distinguishes +itself in that the cpu acknowledges and permits the SoC to enter deeper sleep +modes. In a hierarchical power domain SoC, this means L2 and other caches can +be flushed, system bus, clocks - lowered, and SoC main XO clock gated and +voltages reduced, provided all cpus enter this state. Since the span of low +power modes possible at this state is vast, the exit latency and the residency +of this low power mode would be considered high even though at a cpu level, +this essentially is cpu power down. The SPM in this state also may handshake +with the Resource power manager (RPM) processor in the SoC to indicate a +complete application processor subsystem shut down. + +The idle-state for QCOM SoCs are distinguished by the compatible property of +the idle-states device node. + +The devicetree representation of the idle state should be - + +Required properties: + +- compatible: Must be one of - + "qcom,idle-state-ret", + "qcom,idle-state-spc", + "qcom,idle-state-pc", + and "arm,idle-state". + +Other required and optional properties are specified in [1]. + +Example: + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; + +[1]. Documentation/devicetree/bindings/arm/idle-states.txt -- cgit v0.10.2 From 8c76a6382eb0c45d152c0cf37206e4ec9c3781cd Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Wed, 25 Mar 2015 14:25:30 -0600 Subject: ARM: dts: qcom: Add power-controller device node for 8074 Krait CPUs Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to regulate the power to the cpu and aide the core in entering idle states. Reference the SAW instance and associate the instance with the CPU core. Signed-off-by: Lina Iyer Reviewed-by: Stephen Boyd Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 2d11641..1bb1832 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -21,6 +21,7 @@ reg = <0>; next-level-cache = <&L2>; qcom,acc = <&acc0>; + qcom,saw = <&saw0>; }; cpu@1 { @@ -30,6 +31,7 @@ reg = <1>; next-level-cache = <&L2>; qcom,acc = <&acc1>; + qcom,saw = <&saw1>; }; cpu@2 { @@ -39,6 +41,7 @@ reg = <2>; next-level-cache = <&L2>; qcom,acc = <&acc2>; + qcom,saw = <&saw2>; }; cpu@3 { @@ -48,6 +51,7 @@ reg = <3>; next-level-cache = <&L2>; qcom,acc = <&acc3>; + qcom,saw = <&saw3>; }; L2: l2-cache { @@ -144,7 +148,27 @@ }; }; - saw_l2: regulator@f9012000 { + saw0: power-controller@f9089000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; + }; + + saw1: power-controller@f9099000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; + }; + + saw2: power-controller@f90a9000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw3: power-controller@f90b9000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw_l2: power-controller@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; regulator; -- cgit v0.10.2 From 030e27f6c60d37a24bbbff060936954ad6f77b0b Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Wed, 25 Mar 2015 14:25:31 -0600 Subject: ARM: dts: qcom: Add power-controller device node for 8084 Krait CPUs Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to regulate the power to the cpu and aide the core in entering idle states. Reference the SAW instance and associate the instance with the CPU core. Signed-off-by: Lina Iyer Reviewed-by: Stephen Boyd Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index dbedf64..df2e308 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -21,6 +21,7 @@ enable-method = "qcom,kpss-acc-v2"; next-level-cache = <&L2>; qcom,acc = <&acc0>; + qcom,saw = <&saw0>; }; cpu@1 { @@ -30,6 +31,7 @@ enable-method = "qcom,kpss-acc-v2"; next-level-cache = <&L2>; qcom,acc = <&acc1>; + qcom,saw = <&saw1>; }; cpu@2 { @@ -39,6 +41,7 @@ enable-method = "qcom,kpss-acc-v2"; next-level-cache = <&L2>; qcom,acc = <&acc2>; + qcom,saw = <&saw2>; }; cpu@3 { @@ -48,6 +51,7 @@ enable-method = "qcom,kpss-acc-v2"; next-level-cache = <&L2>; qcom,acc = <&acc3>; + qcom,saw = <&saw3>; }; L2: l2-cache { @@ -144,7 +148,27 @@ }; }; - saw_l2: regulator@f9012000 { + saw0: power-controller@f9089000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; + }; + + saw1: power-controller@f9099000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; + }; + + saw2: power-controller@f90a9000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw3: power-controller@f90b9000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw_l2: power-controller@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; regulator; -- cgit v0.10.2 From 9fc23ce3bfb8c205f2a43de94f3730aa301f2efe Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Wed, 25 Mar 2015 14:25:32 -0600 Subject: ARM: dts: qcom: Update power-controller device node for 8064 Krait CPUs Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible binding string to configure SPM registers and allow the SPM to put the core in deeper idle states when the core is idle. Signed-off-by: Lina Iyer Reviewed-by: Stephen Boyd Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 4e3e063..58e1d79 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -139,26 +139,26 @@ reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; }; - saw0: regulator@2089000 { - compatible = "qcom,saw2"; + saw0: power-controller@2089000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw1: regulator@2099000 { - compatible = "qcom,saw2"; + saw1: power-controller@2099000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw2: regulator@20a9000 { - compatible = "qcom,saw2"; + saw2: power-controller@20a9000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw3: regulator@20b9000 { - compatible = "qcom,saw2"; + saw3: power-controller@20b9000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; regulator; }; -- cgit v0.10.2 From d596d620d82f64989aaf73144bac82002204d88c Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Wed, 25 Mar 2015 14:25:33 -0600 Subject: ARM: dts: qcom: Add idle states device nodes for 8974/8074 Add ARM common idle states device bindings for cpuidle support for APQ 8974/8074. Support Standalone power collapse (SPC) idle state (power down that does not affect any SoC idle states) for each cpu. Signed-off-by: Lina Iyer Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 1bb1832..37b47b5 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -22,6 +22,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SPC>; }; cpu@1 { @@ -32,6 +33,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_SPC>; }; cpu@2 { @@ -42,6 +44,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_SPC>; }; cpu@3 { @@ -52,6 +55,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_SPC>; }; L2: l2-cache { @@ -59,6 +63,16 @@ cache-level = <2>; qcom,saw = <&saw_l2>; }; + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", + "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; }; cpu-pmu { -- cgit v0.10.2 From d8664979e6ba97024c43d6248f94982ee0c8d1ee Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Wed, 25 Mar 2015 14:25:34 -0600 Subject: ARM: dts: qcom: Add idle states device nodes for 8084 Add ARM common idle states device bindings for cpuidle support for APQ 8084. Support Standalone power collapse (SPC) idle state (power down that does not affect any SoC idle states) for each cpu. Signed-off-by: Lina Iyer Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index df2e308..7084010 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -22,6 +22,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SPC>; }; cpu@1 { @@ -32,6 +33,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_SPC>; }; cpu@2 { @@ -42,6 +44,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_SPC>; }; cpu@3 { @@ -52,6 +55,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_SPC>; }; L2: l2-cache { @@ -59,6 +63,16 @@ cache-level = <2>; qcom,saw = <&saw_l2>; }; + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", + "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; }; cpu-pmu { -- cgit v0.10.2 From 06c49f2b88eb177f4f96d68d561f28fb125e7c0c Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Wed, 25 Mar 2015 14:25:35 -0600 Subject: ARM: dts: qcom: Add idle state device nodes for 8064 Add ARM common idle state device bindings for cpuidle support for APQ 8064. Support Standalone power collapse (SPC) idle state (power down that does not affect any SoC idle states) for each cpu. Signed-off-by: Lina Iyer Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 58e1d79..6c15112 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -23,6 +23,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SPC>; }; cpu@1 { @@ -33,6 +34,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_SPC>; }; cpu@2 { @@ -43,6 +45,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_SPC>; }; cpu@3 { @@ -53,12 +56,23 @@ next-level-cache = <&L2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_SPC>; }; L2: l2-cache { compatible = "cache"; cache-level = <2>; }; + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", + "arm,idle-state"; + entry-latency-us = <400>; + exit-latency-us = <900>; + min-residency-us = <3000>; + }; + }; }; cpu-pmu { -- cgit v0.10.2 From 4f054d445139d63868f931328f897ac5ef87242e Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 7 Apr 2015 14:23:03 +0200 Subject: ARM: mvebu: use 0xf1000000 as internal registers on Armada 370 DB All Marvell EBU SoCs (Kirkwood, Dove, Orion, Armada) have the capability of changing the location of their internal registers (i.e the registers for most hardware blocks inside the SoC). When coming out of reset, the internal registers are mapped at 0xd0000000, but since years and years, the tradition has been to have the internal registers remapped at 0xf1000000 by the bootloader, and Linux has since then assumed that the internal registers for the SoC were located at 0xf1000000 on Kirkwood, Dove, Orion, etc. Linux has never been aware that those registers are remappable (and there is no way to know where they are mapped at runtime, since the register to configure the address of the registers is itself within the internal registers). Then came the Armada 370 and Armada XP, in which some of the very early silicon steppings had an issue, which forced to use 0xd0000000: the SoC was no longer working properly when the internal registers were remapped at 0xf1000000. This issue is only affecting very early silicon steppings and production steppings are not affected: the issue has been fixed in between. Since what we (Free Electrons) used to do the initial submission of the Armada 370 and Armada XP platforms was evaluation boards with those very early steppings, we submitted Device Tree that assumed the internal registers were mapped at 0xd0000000. This is the case for Armada 370 DB, Armada XP DB and Armada XP GP. However, in practice, since Marvell has been shipping the evaluation boards with production steppings of the SoC, they are shipping those boards with bootloaders that remap the registers to 0xf1000000. We have already changed this internal register address to 0xf1000000 for the Armada XP DB in commit 82066bdb5a75 and for the Armada XP GP in commit 91ed32200e6e (both merged in v3.15). We only recently got our hand on an Armada 370 DB with a production stepping of the SoC, which uses a bootloader that remaps internal registers at 0xf1000000. Therefore, this commit aligns the Armada 370 DB to be like the Armada XP DB and Armada XP GP: assume that the internal registers are mapped at 0xf1000000. We would like to stress out the fact that the usage of 0xd0000000 as the internal register base address was a temporary workaround for early steppings deficiencies, and that the real long-term solution is the usage of 0xf1000000. Having 0xd0000000 is an *accident* in the life of the Marvell platform support in the kernel, as is confirmed by the usage of 0xf1000000 in all previous Marvell platforms (Dove, Kirkwood, Orion). There are unfortunately a number of commercial devices that continue to use 0xd0000000 even though they use production steppings of the SoC, simply because the vendors of such devices have never bothered using a more recent bootloader version from Marvell. There is not much we can do about it, and we plan on keeping 0xd0000000 in the Device Tree of such devices. The main reason for remapping the internal registers at 0xf1000000 instead of 0xd0000000 is that it leaves more space in the 0 -> 4 GB part of the physical address space for RAM. With registers at 0xd0000000, all RAM between 0xd0000000 to 0xffffffff is lost because it's covered by the I/O registers. Signed-off-by: Thomas Petazzoni Acked-by: Andrew Lunn Acked-by: Jason Cooper Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index e993c46..dede3e7 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -45,6 +45,15 @@ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. */ /dts-v1/; @@ -64,7 +73,7 @@ }; soc { - ranges = ; internal-regs { -- cgit v0.10.2 From 2c13d8c7a85fdbf7d5c71b4989bb5c249b76a0c1 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 14 Apr 2015 00:39:27 +0200 Subject: Revert "ARM: dts: mt8135: Add pinctrl/GPIO/EINT node for mt8135." This reverts commit e6f219b8ec5e4227c8b87b758afb48ed102b4210. to fix a build error: arch/arm/boot/dts/mt8135-pinfunc.h:18:40: fatal error: dt-bindings/pinctrl/mt65xx.h: No such file or directory Signed-off-by: Arnd Bergmann diff --git a/arch/arm/boot/dts/mt8135-pinfunc.h b/arch/arm/boot/dts/mt8135-pinfunc.h deleted file mode 100644 index 5a60987..0000000 --- a/arch/arm/boot/dts/mt8135-pinfunc.h +++ /dev/null @@ -1,1302 +0,0 @@ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Hongzhou.Yang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __DTS_MT8135_PINFUNC_H -#define __DTS_MT8135_PINFUNC_H - -#include - -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(0) | 1) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MTK_PIN_NO(0) | 2) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MTK_PIN_NO(0) | 3) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_DAC_DAT_OUT (MTK_PIN_NO(0) | 4) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_PCM1_DO (MTK_PIN_NO(0) | 5) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_SPI1_MO (MTK_PIN_NO(0) | 6) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_NALE (MTK_PIN_NO(0) | 7) - -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(1) | 1) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_EINT48 (MTK_PIN_NO(1) | 2) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_I2SIN_WS (MTK_PIN_NO(1) | 3) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_DAC_WS (MTK_PIN_NO(1) | 4) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_PCM1_WS (MTK_PIN_NO(1) | 5) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_SPI1_CSN (MTK_PIN_NO(1) | 6) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_NCLE (MTK_PIN_NO(1) | 7) - -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(2) | 1) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_EINT47 (MTK_PIN_NO(2) | 2) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_I2SIN_CK (MTK_PIN_NO(2) | 3) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_DAC_CK (MTK_PIN_NO(2) | 4) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_PCM1_CK (MTK_PIN_NO(2) | 5) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_SPI1_CLK (MTK_PIN_NO(2) | 6) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(2) | 7) - -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(3) | 1) -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_EINT46 (MTK_PIN_NO(3) | 2) -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_A_FUNC_CK (MTK_PIN_NO(3) | 3) -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_LSCE1B_2X (MTK_PIN_NO(3) | 6) -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_NLD5 (MTK_PIN_NO(3) | 7) - -#define MT8135_PIN_4_MSDC0_CMD__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(4) | 1) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_EINT41 (MTK_PIN_NO(4) | 2) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_A_FUNC_DOUT_0 (MTK_PIN_NO(4) | 3) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_USB_TEST_IO_0 (MTK_PIN_NO(4) | 5) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_LRSTB_2X (MTK_PIN_NO(4) | 6) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_NRNB (MTK_PIN_NO(4) | 7) - -#define MT8135_PIN_5_MSDC0_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(5) | 1) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_EINT40 (MTK_PIN_NO(5) | 2) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_A_FUNC_DOUT_1 (MTK_PIN_NO(5) | 3) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_USB_TEST_IO_1 (MTK_PIN_NO(5) | 5) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_LPTE (MTK_PIN_NO(5) | 6) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_NREB (MTK_PIN_NO(5) | 7) - -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(6) | 1) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_EINT45 (MTK_PIN_NO(6) | 2) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_A_FUNC_DOUT_2 (MTK_PIN_NO(6) | 3) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_USB_TEST_IO_2 (MTK_PIN_NO(6) | 5) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_LSCE0B_2X (MTK_PIN_NO(6) | 6) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_NLD7 (MTK_PIN_NO(6) | 7) - -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(7) | 1) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_EINT44 (MTK_PIN_NO(7) | 2) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_A_FUNC_DOUT_3 (MTK_PIN_NO(7) | 3) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_USB_TEST_IO_3 (MTK_PIN_NO(7) | 5) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_LSA0_2X (MTK_PIN_NO(7) | 6) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_NLD14 (MTK_PIN_NO(7) | 7) - -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(8) | 1) -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_EINT43 (MTK_PIN_NO(8) | 2) -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_USB_TEST_IO_4 (MTK_PIN_NO(8) | 5) -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_LSCK_2X (MTK_PIN_NO(8) | 6) -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_NLD11 (MTK_PIN_NO(8) | 7) - -#define MT8135_PIN_9_MSDC0_DAT0__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define MT8135_PIN_9_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(9) | 1) -#define MT8135_PIN_9_MSDC0_DAT0__FUNC_EINT42 (MTK_PIN_NO(9) | 2) -#define MT8135_PIN_9_MSDC0_DAT0__FUNC_USB_TEST_IO_5 (MTK_PIN_NO(9) | 5) -#define MT8135_PIN_9_MSDC0_DAT0__FUNC_LSDA_2X (MTK_PIN_NO(9) | 6) - -#define MT8135_PIN_10_NCEB0__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define MT8135_PIN_10_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(10) | 1) -#define MT8135_PIN_10_NCEB0__FUNC_EINT139 (MTK_PIN_NO(10) | 2) -#define MT8135_PIN_10_NCEB0__FUNC_TESTA_OUT4 (MTK_PIN_NO(10) | 7) - -#define MT8135_PIN_11_NCEB1__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define MT8135_PIN_11_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(11) | 1) -#define MT8135_PIN_11_NCEB1__FUNC_EINT140 (MTK_PIN_NO(11) | 2) -#define MT8135_PIN_11_NCEB1__FUNC_USB_DRVVBUS (MTK_PIN_NO(11) | 6) -#define MT8135_PIN_11_NCEB1__FUNC_TESTA_OUT5 (MTK_PIN_NO(11) | 7) - -#define MT8135_PIN_12_NRNB__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define MT8135_PIN_12_NRNB__FUNC_NRNB (MTK_PIN_NO(12) | 1) -#define MT8135_PIN_12_NRNB__FUNC_EINT141 (MTK_PIN_NO(12) | 2) -#define MT8135_PIN_12_NRNB__FUNC_A_FUNC_DOUT_4 (MTK_PIN_NO(12) | 3) -#define MT8135_PIN_12_NRNB__FUNC_TESTA_OUT6 (MTK_PIN_NO(12) | 7) - -#define MT8135_PIN_13_NCLE__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define MT8135_PIN_13_NCLE__FUNC_NCLE (MTK_PIN_NO(13) | 1) -#define MT8135_PIN_13_NCLE__FUNC_EINT142 (MTK_PIN_NO(13) | 2) -#define MT8135_PIN_13_NCLE__FUNC_A_FUNC_DOUT_5 (MTK_PIN_NO(13) | 3) -#define MT8135_PIN_13_NCLE__FUNC_CM2PDN_1X (MTK_PIN_NO(13) | 4) -#define MT8135_PIN_13_NCLE__FUNC_NALE (MTK_PIN_NO(13) | 6) -#define MT8135_PIN_13_NCLE__FUNC_TESTA_OUT7 (MTK_PIN_NO(13) | 7) - -#define MT8135_PIN_14_NALE__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define MT8135_PIN_14_NALE__FUNC_NALE (MTK_PIN_NO(14) | 1) -#define MT8135_PIN_14_NALE__FUNC_EINT143 (MTK_PIN_NO(14) | 2) -#define MT8135_PIN_14_NALE__FUNC_A_FUNC_DOUT_6 (MTK_PIN_NO(14) | 3) -#define MT8135_PIN_14_NALE__FUNC_CM2MCLK_1X (MTK_PIN_NO(14) | 4) -#define MT8135_PIN_14_NALE__FUNC_IRDA_RXD (MTK_PIN_NO(14) | 5) -#define MT8135_PIN_14_NALE__FUNC_NCLE (MTK_PIN_NO(14) | 6) -#define MT8135_PIN_14_NALE__FUNC_TESTA_OUT8 (MTK_PIN_NO(14) | 7) - -#define MT8135_PIN_15_NREB__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define MT8135_PIN_15_NREB__FUNC_NREB (MTK_PIN_NO(15) | 1) -#define MT8135_PIN_15_NREB__FUNC_EINT144 (MTK_PIN_NO(15) | 2) -#define MT8135_PIN_15_NREB__FUNC_A_FUNC_DOUT_7 (MTK_PIN_NO(15) | 3) -#define MT8135_PIN_15_NREB__FUNC_CM2RST_1X (MTK_PIN_NO(15) | 4) -#define MT8135_PIN_15_NREB__FUNC_IRDA_TXD (MTK_PIN_NO(15) | 5) -#define MT8135_PIN_15_NREB__FUNC_TESTA_OUT9 (MTK_PIN_NO(15) | 7) - -#define MT8135_PIN_16_NWEB__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) -#define MT8135_PIN_16_NWEB__FUNC_NWEB (MTK_PIN_NO(16) | 1) -#define MT8135_PIN_16_NWEB__FUNC_EINT145 (MTK_PIN_NO(16) | 2) -#define MT8135_PIN_16_NWEB__FUNC_A_FUNC_DIN_0 (MTK_PIN_NO(16) | 3) -#define MT8135_PIN_16_NWEB__FUNC_CM2PCLK_1X (MTK_PIN_NO(16) | 4) -#define MT8135_PIN_16_NWEB__FUNC_IRDA_PDN (MTK_PIN_NO(16) | 5) -#define MT8135_PIN_16_NWEB__FUNC_TESTA_OUT10 (MTK_PIN_NO(16) | 7) - -#define MT8135_PIN_17_NLD0__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) -#define MT8135_PIN_17_NLD0__FUNC_NLD0 (MTK_PIN_NO(17) | 1) -#define MT8135_PIN_17_NLD0__FUNC_EINT146 (MTK_PIN_NO(17) | 2) -#define MT8135_PIN_17_NLD0__FUNC_A_FUNC_DIN_1 (MTK_PIN_NO(17) | 3) -#define MT8135_PIN_17_NLD0__FUNC_CM2DAT_1X_0 (MTK_PIN_NO(17) | 4) -#define MT8135_PIN_17_NLD0__FUNC_I2SIN_CK (MTK_PIN_NO(17) | 5) -#define MT8135_PIN_17_NLD0__FUNC_DAC_CK (MTK_PIN_NO(17) | 6) -#define MT8135_PIN_17_NLD0__FUNC_TESTA_OUT11 (MTK_PIN_NO(17) | 7) - -#define MT8135_PIN_18_NLD1__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define MT8135_PIN_18_NLD1__FUNC_NLD1 (MTK_PIN_NO(18) | 1) -#define MT8135_PIN_18_NLD1__FUNC_EINT147 (MTK_PIN_NO(18) | 2) -#define MT8135_PIN_18_NLD1__FUNC_A_FUNC_DIN_2 (MTK_PIN_NO(18) | 3) -#define MT8135_PIN_18_NLD1__FUNC_CM2DAT_1X_1 (MTK_PIN_NO(18) | 4) -#define MT8135_PIN_18_NLD1__FUNC_I2SIN_WS (MTK_PIN_NO(18) | 5) -#define MT8135_PIN_18_NLD1__FUNC_DAC_WS (MTK_PIN_NO(18) | 6) -#define MT8135_PIN_18_NLD1__FUNC_TESTA_OUT12 (MTK_PIN_NO(18) | 7) - -#define MT8135_PIN_19_NLD2__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define MT8135_PIN_19_NLD2__FUNC_NLD2 (MTK_PIN_NO(19) | 1) -#define MT8135_PIN_19_NLD2__FUNC_EINT148 (MTK_PIN_NO(19) | 2) -#define MT8135_PIN_19_NLD2__FUNC_A_FUNC_DIN_3 (MTK_PIN_NO(19) | 3) -#define MT8135_PIN_19_NLD2__FUNC_CM2DAT_1X_2 (MTK_PIN_NO(19) | 4) -#define MT8135_PIN_19_NLD2__FUNC_I2SOUT_DAT (MTK_PIN_NO(19) | 5) -#define MT8135_PIN_19_NLD2__FUNC_DAC_DAT_OUT (MTK_PIN_NO(19) | 6) -#define MT8135_PIN_19_NLD2__FUNC_TESTA_OUT13 (MTK_PIN_NO(19) | 7) - -#define MT8135_PIN_20_NLD3__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define MT8135_PIN_20_NLD3__FUNC_NLD3 (MTK_PIN_NO(20) | 1) -#define MT8135_PIN_20_NLD3__FUNC_EINT149 (MTK_PIN_NO(20) | 2) -#define MT8135_PIN_20_NLD3__FUNC_A_FUNC_DIN_4 (MTK_PIN_NO(20) | 3) -#define MT8135_PIN_20_NLD3__FUNC_CM2DAT_1X_3 (MTK_PIN_NO(20) | 4) -#define MT8135_PIN_20_NLD3__FUNC_TESTA_OUT14 (MTK_PIN_NO(20) | 7) - -#define MT8135_PIN_21_NLD4__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define MT8135_PIN_21_NLD4__FUNC_NLD4 (MTK_PIN_NO(21) | 1) -#define MT8135_PIN_21_NLD4__FUNC_EINT150 (MTK_PIN_NO(21) | 2) -#define MT8135_PIN_21_NLD4__FUNC_A_FUNC_DIN_5 (MTK_PIN_NO(21) | 3) -#define MT8135_PIN_21_NLD4__FUNC_CM2DAT_1X_4 (MTK_PIN_NO(21) | 4) -#define MT8135_PIN_21_NLD4__FUNC_TESTA_OUT15 (MTK_PIN_NO(21) | 7) - -#define MT8135_PIN_22_NLD5__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define MT8135_PIN_22_NLD5__FUNC_NLD5 (MTK_PIN_NO(22) | 1) -#define MT8135_PIN_22_NLD5__FUNC_EINT151 (MTK_PIN_NO(22) | 2) -#define MT8135_PIN_22_NLD5__FUNC_A_FUNC_DIN_6 (MTK_PIN_NO(22) | 3) -#define MT8135_PIN_22_NLD5__FUNC_CM2DAT_1X_5 (MTK_PIN_NO(22) | 4) -#define MT8135_PIN_22_NLD5__FUNC_TESTA_OUT16 (MTK_PIN_NO(22) | 7) - -#define MT8135_PIN_23_NLD6__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define MT8135_PIN_23_NLD6__FUNC_NLD6 (MTK_PIN_NO(23) | 1) -#define MT8135_PIN_23_NLD6__FUNC_EINT152 (MTK_PIN_NO(23) | 2) -#define MT8135_PIN_23_NLD6__FUNC_A_FUNC_DIN_7 (MTK_PIN_NO(23) | 3) -#define MT8135_PIN_23_NLD6__FUNC_CM2DAT_1X_6 (MTK_PIN_NO(23) | 4) -#define MT8135_PIN_23_NLD6__FUNC_TESTA_OUT17 (MTK_PIN_NO(23) | 7) - -#define MT8135_PIN_24_NLD7__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define MT8135_PIN_24_NLD7__FUNC_NLD7 (MTK_PIN_NO(24) | 1) -#define MT8135_PIN_24_NLD7__FUNC_EINT153 (MTK_PIN_NO(24) | 2) -#define MT8135_PIN_24_NLD7__FUNC_A_FUNC_DIN_8 (MTK_PIN_NO(24) | 3) -#define MT8135_PIN_24_NLD7__FUNC_CM2DAT_1X_7 (MTK_PIN_NO(24) | 4) -#define MT8135_PIN_24_NLD7__FUNC_TESTA_OUT18 (MTK_PIN_NO(24) | 7) - -#define MT8135_PIN_25_NLD8__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define MT8135_PIN_25_NLD8__FUNC_NLD8 (MTK_PIN_NO(25) | 1) -#define MT8135_PIN_25_NLD8__FUNC_EINT154 (MTK_PIN_NO(25) | 2) -#define MT8135_PIN_25_NLD8__FUNC_CM2DAT_1X_8 (MTK_PIN_NO(25) | 4) - -#define MT8135_PIN_26_NLD9__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define MT8135_PIN_26_NLD9__FUNC_NLD9 (MTK_PIN_NO(26) | 1) -#define MT8135_PIN_26_NLD9__FUNC_EINT155 (MTK_PIN_NO(26) | 2) -#define MT8135_PIN_26_NLD9__FUNC_CM2DAT_1X_9 (MTK_PIN_NO(26) | 4) -#define MT8135_PIN_26_NLD9__FUNC_PWM1 (MTK_PIN_NO(26) | 5) - -#define MT8135_PIN_27_NLD10__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define MT8135_PIN_27_NLD10__FUNC_NLD10 (MTK_PIN_NO(27) | 1) -#define MT8135_PIN_27_NLD10__FUNC_EINT156 (MTK_PIN_NO(27) | 2) -#define MT8135_PIN_27_NLD10__FUNC_CM2VSYNC_1X (MTK_PIN_NO(27) | 4) -#define MT8135_PIN_27_NLD10__FUNC_PWM2 (MTK_PIN_NO(27) | 5) - -#define MT8135_PIN_28_NLD11__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define MT8135_PIN_28_NLD11__FUNC_NLD11 (MTK_PIN_NO(28) | 1) -#define MT8135_PIN_28_NLD11__FUNC_EINT157 (MTK_PIN_NO(28) | 2) -#define MT8135_PIN_28_NLD11__FUNC_CM2HSYNC_1X (MTK_PIN_NO(28) | 4) -#define MT8135_PIN_28_NLD11__FUNC_PWM3 (MTK_PIN_NO(28) | 5) - -#define MT8135_PIN_29_NLD12__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define MT8135_PIN_29_NLD12__FUNC_NLD12 (MTK_PIN_NO(29) | 1) -#define MT8135_PIN_29_NLD12__FUNC_EINT158 (MTK_PIN_NO(29) | 2) -#define MT8135_PIN_29_NLD12__FUNC_I2SIN_CK (MTK_PIN_NO(29) | 3) -#define MT8135_PIN_29_NLD12__FUNC_DAC_CK (MTK_PIN_NO(29) | 4) -#define MT8135_PIN_29_NLD12__FUNC_PCM1_CK (MTK_PIN_NO(29) | 5) - -#define MT8135_PIN_30_NLD13__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) -#define MT8135_PIN_30_NLD13__FUNC_NLD13 (MTK_PIN_NO(30) | 1) -#define MT8135_PIN_30_NLD13__FUNC_EINT159 (MTK_PIN_NO(30) | 2) -#define MT8135_PIN_30_NLD13__FUNC_I2SIN_WS (MTK_PIN_NO(30) | 3) -#define MT8135_PIN_30_NLD13__FUNC_DAC_WS (MTK_PIN_NO(30) | 4) -#define MT8135_PIN_30_NLD13__FUNC_PCM1_WS (MTK_PIN_NO(30) | 5) - -#define MT8135_PIN_31_NLD14__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) -#define MT8135_PIN_31_NLD14__FUNC_NLD14 (MTK_PIN_NO(31) | 1) -#define MT8135_PIN_31_NLD14__FUNC_EINT160 (MTK_PIN_NO(31) | 2) -#define MT8135_PIN_31_NLD14__FUNC_I2SOUT_DAT (MTK_PIN_NO(31) | 3) -#define MT8135_PIN_31_NLD14__FUNC_DAC_DAT_OUT (MTK_PIN_NO(31) | 4) -#define MT8135_PIN_31_NLD14__FUNC_PCM1_DO (MTK_PIN_NO(31) | 5) - -#define MT8135_PIN_32_NLD15__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) -#define MT8135_PIN_32_NLD15__FUNC_NLD15 (MTK_PIN_NO(32) | 1) -#define MT8135_PIN_32_NLD15__FUNC_EINT161 (MTK_PIN_NO(32) | 2) -#define MT8135_PIN_32_NLD15__FUNC_DISP_PWM (MTK_PIN_NO(32) | 3) -#define MT8135_PIN_32_NLD15__FUNC_PWM4 (MTK_PIN_NO(32) | 4) -#define MT8135_PIN_32_NLD15__FUNC_PCM1_DI (MTK_PIN_NO(32) | 5) - -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(33) | 1) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_EINT50 (MTK_PIN_NO(33) | 2) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_I2SIN_DAT (MTK_PIN_NO(33) | 3) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_PCM1_DI (MTK_PIN_NO(33) | 5) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_SPI1_MI (MTK_PIN_NO(33) | 6) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_NLD10 (MTK_PIN_NO(33) | 7) - -#define MT8135_PIN_34_IDDIG__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define MT8135_PIN_34_IDDIG__FUNC_IDDIG (MTK_PIN_NO(34) | 1) -#define MT8135_PIN_34_IDDIG__FUNC_EINT34 (MTK_PIN_NO(34) | 2) - -#define MT8135_PIN_35_SCL3__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define MT8135_PIN_35_SCL3__FUNC_SCL3 (MTK_PIN_NO(35) | 1) -#define MT8135_PIN_35_SCL3__FUNC_EINT96 (MTK_PIN_NO(35) | 2) -#define MT8135_PIN_35_SCL3__FUNC_CLKM6 (MTK_PIN_NO(35) | 3) -#define MT8135_PIN_35_SCL3__FUNC_PWM6 (MTK_PIN_NO(35) | 4) - -#define MT8135_PIN_36_SDA3__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define MT8135_PIN_36_SDA3__FUNC_SDA3 (MTK_PIN_NO(36) | 1) -#define MT8135_PIN_36_SDA3__FUNC_EINT97 (MTK_PIN_NO(36) | 2) - -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(37) | 1) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_ADC_CK (MTK_PIN_NO(37) | 2) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_HDMI_SDATA0 (MTK_PIN_NO(37) | 3) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_EINT19 (MTK_PIN_NO(37) | 4) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_USB_TEST_IO_6 (MTK_PIN_NO(37) | 5) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_TESTA_OUT19 (MTK_PIN_NO(37) | 7) - -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(38) | 1) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_ADC_WS (MTK_PIN_NO(38) | 2) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(38) | 3) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_EINT21 (MTK_PIN_NO(38) | 4) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_USB_TEST_IO_7 (MTK_PIN_NO(38) | 5) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_TESTA_OUT20 (MTK_PIN_NO(38) | 7) - -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(39) | 1) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_ADC_DAT_IN (MTK_PIN_NO(39) | 2) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(39) | 3) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_EINT20 (MTK_PIN_NO(39) | 4) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_USB_TEST_IO_8 (MTK_PIN_NO(39) | 5) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_TESTA_OUT21 (MTK_PIN_NO(39) | 7) - -#define MT8135_PIN_40_DAC_CLK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define MT8135_PIN_40_DAC_CLK__FUNC_DAC_CK (MTK_PIN_NO(40) | 1) -#define MT8135_PIN_40_DAC_CLK__FUNC_EINT22 (MTK_PIN_NO(40) | 2) -#define MT8135_PIN_40_DAC_CLK__FUNC_HDMI_SDATA1 (MTK_PIN_NO(40) | 3) -#define MT8135_PIN_40_DAC_CLK__FUNC_USB_TEST_IO_9 (MTK_PIN_NO(40) | 5) -#define MT8135_PIN_40_DAC_CLK__FUNC_TESTA_OUT22 (MTK_PIN_NO(40) | 7) - -#define MT8135_PIN_41_DAC_WS__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define MT8135_PIN_41_DAC_WS__FUNC_DAC_WS (MTK_PIN_NO(41) | 1) -#define MT8135_PIN_41_DAC_WS__FUNC_EINT24 (MTK_PIN_NO(41) | 2) -#define MT8135_PIN_41_DAC_WS__FUNC_HDMI_SDATA2 (MTK_PIN_NO(41) | 3) -#define MT8135_PIN_41_DAC_WS__FUNC_USB_TEST_IO_10 (MTK_PIN_NO(41) | 5) -#define MT8135_PIN_41_DAC_WS__FUNC_TESTA_OUT23 (MTK_PIN_NO(41) | 7) - -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(42) | 1) -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_EINT23 (MTK_PIN_NO(42) | 2) -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_HDMI_SDATA3 (MTK_PIN_NO(42) | 3) -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_USB_TEST_IO_11 (MTK_PIN_NO(42) | 5) -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_TESTA_OUT24 (MTK_PIN_NO(42) | 7) - -#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(43) | 1) -#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_EINT29 (MTK_PIN_NO(43) | 2) - -#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(44) | 1) -#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_EINT28 (MTK_PIN_NO(44) | 2) - -#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(45) | 1) -#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_EINT27 (MTK_PIN_NO(45) | 2) - -#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(46) | 1) -#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_EINT26 (MTK_PIN_NO(46) | 2) - -#define MT8135_PIN_47_PWRAP_EVENT__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define MT8135_PIN_47_PWRAP_EVENT__FUNC_PWRAP_EVENT_IN (MTK_PIN_NO(47) | 1) -#define MT8135_PIN_47_PWRAP_EVENT__FUNC_EINT25 (MTK_PIN_NO(47) | 2) -#define MT8135_PIN_47_PWRAP_EVENT__FUNC_TESTA_OUT2 (MTK_PIN_NO(47) | 7) - -#define MT8135_PIN_48_RTC32K_CK__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define MT8135_PIN_48_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(48) | 1) - -#define MT8135_PIN_49_WATCHDOG__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define MT8135_PIN_49_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(49) | 1) -#define MT8135_PIN_49_WATCHDOG__FUNC_EINT36 (MTK_PIN_NO(49) | 2) - -#define MT8135_PIN_50_SRCLKENA__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) -#define MT8135_PIN_50_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(50) | 1) -#define MT8135_PIN_50_SRCLKENA__FUNC_EINT38 (MTK_PIN_NO(50) | 2) - -#define MT8135_PIN_51_SRCVOLTEN__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) -#define MT8135_PIN_51_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(51) | 1) -#define MT8135_PIN_51_SRCVOLTEN__FUNC_EINT37 (MTK_PIN_NO(51) | 2) - -#define MT8135_PIN_52_EINT0__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) -#define MT8135_PIN_52_EINT0__FUNC_EINT0 (MTK_PIN_NO(52) | 1) -#define MT8135_PIN_52_EINT0__FUNC_PWM1 (MTK_PIN_NO(52) | 2) -#define MT8135_PIN_52_EINT0__FUNC_CLKM0 (MTK_PIN_NO(52) | 3) -#define MT8135_PIN_52_EINT0__FUNC_SPDIF_OUT (MTK_PIN_NO(52) | 4) -#define MT8135_PIN_52_EINT0__FUNC_USB_TEST_IO_12 (MTK_PIN_NO(52) | 5) -#define MT8135_PIN_52_EINT0__FUNC_USB_SCL (MTK_PIN_NO(52) | 7) - -#define MT8135_PIN_53_URXD2__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define MT8135_PIN_53_URXD2__FUNC_URXD2 (MTK_PIN_NO(53) | 1) -#define MT8135_PIN_53_URXD2__FUNC_EINT83 (MTK_PIN_NO(53) | 2) -#define MT8135_PIN_53_URXD2__FUNC_HDMI_LRCK (MTK_PIN_NO(53) | 4) -#define MT8135_PIN_53_URXD2__FUNC_CLKM3 (MTK_PIN_NO(53) | 5) -#define MT8135_PIN_53_URXD2__FUNC_UTXD2 (MTK_PIN_NO(53) | 7) - -#define MT8135_PIN_54_UTXD2__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define MT8135_PIN_54_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(54) | 1) -#define MT8135_PIN_54_UTXD2__FUNC_EINT82 (MTK_PIN_NO(54) | 2) -#define MT8135_PIN_54_UTXD2__FUNC_HDMI_BCK_OUT (MTK_PIN_NO(54) | 4) -#define MT8135_PIN_54_UTXD2__FUNC_CLKM2 (MTK_PIN_NO(54) | 5) -#define MT8135_PIN_54_UTXD2__FUNC_URXD2 (MTK_PIN_NO(54) | 7) - -#define MT8135_PIN_55_UCTS2__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define MT8135_PIN_55_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(55) | 1) -#define MT8135_PIN_55_UCTS2__FUNC_EINT84 (MTK_PIN_NO(55) | 2) -#define MT8135_PIN_55_UCTS2__FUNC_PWM1 (MTK_PIN_NO(55) | 5) -#define MT8135_PIN_55_UCTS2__FUNC_URTS2 (MTK_PIN_NO(55) | 7) - -#define MT8135_PIN_56_URTS2__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define MT8135_PIN_56_URTS2__FUNC_URTS2 (MTK_PIN_NO(56) | 1) -#define MT8135_PIN_56_URTS2__FUNC_EINT85 (MTK_PIN_NO(56) | 2) -#define MT8135_PIN_56_URTS2__FUNC_PWM2 (MTK_PIN_NO(56) | 5) -#define MT8135_PIN_56_URTS2__FUNC_UCTS2 (MTK_PIN_NO(56) | 7) - -#define MT8135_PIN_57_JTCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define MT8135_PIN_57_JTCK__FUNC_JTCK (MTK_PIN_NO(57) | 1) -#define MT8135_PIN_57_JTCK__FUNC_EINT188 (MTK_PIN_NO(57) | 2) -#define MT8135_PIN_57_JTCK__FUNC_DSP1_ICK (MTK_PIN_NO(57) | 3) - -#define MT8135_PIN_58_JTDO__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define MT8135_PIN_58_JTDO__FUNC_JTDO (MTK_PIN_NO(58) | 1) -#define MT8135_PIN_58_JTDO__FUNC_EINT190 (MTK_PIN_NO(58) | 2) -#define MT8135_PIN_58_JTDO__FUNC_DSP2_IMS (MTK_PIN_NO(58) | 3) - -#define MT8135_PIN_59_JTRST_B__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) -#define MT8135_PIN_59_JTRST_B__FUNC_JTRST_B (MTK_PIN_NO(59) | 1) -#define MT8135_PIN_59_JTRST_B__FUNC_EINT0 (MTK_PIN_NO(59) | 2) -#define MT8135_PIN_59_JTRST_B__FUNC_DSP2_ICK (MTK_PIN_NO(59) | 3) - -#define MT8135_PIN_60_JTDI__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) -#define MT8135_PIN_60_JTDI__FUNC_JTDI (MTK_PIN_NO(60) | 1) -#define MT8135_PIN_60_JTDI__FUNC_EINT189 (MTK_PIN_NO(60) | 2) -#define MT8135_PIN_60_JTDI__FUNC_DSP1_IMS (MTK_PIN_NO(60) | 3) - -#define MT8135_PIN_61_JRTCK__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) -#define MT8135_PIN_61_JRTCK__FUNC_JRTCK (MTK_PIN_NO(61) | 1) -#define MT8135_PIN_61_JRTCK__FUNC_EINT187 (MTK_PIN_NO(61) | 2) -#define MT8135_PIN_61_JRTCK__FUNC_DSP1_ID (MTK_PIN_NO(61) | 3) - -#define MT8135_PIN_62_JTMS__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) -#define MT8135_PIN_62_JTMS__FUNC_JTMS (MTK_PIN_NO(62) | 1) -#define MT8135_PIN_62_JTMS__FUNC_EINT191 (MTK_PIN_NO(62) | 2) -#define MT8135_PIN_62_JTMS__FUNC_DSP2_ID (MTK_PIN_NO(62) | 3) - -#define MT8135_PIN_63_MSDC1_INSI__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) -#define MT8135_PIN_63_MSDC1_INSI__FUNC_MSDC1_INSI (MTK_PIN_NO(63) | 1) -#define MT8135_PIN_63_MSDC1_INSI__FUNC_SCL5 (MTK_PIN_NO(63) | 3) -#define MT8135_PIN_63_MSDC1_INSI__FUNC_PWM6 (MTK_PIN_NO(63) | 4) -#define MT8135_PIN_63_MSDC1_INSI__FUNC_CLKM5 (MTK_PIN_NO(63) | 5) -#define MT8135_PIN_63_MSDC1_INSI__FUNC_TESTB_OUT6 (MTK_PIN_NO(63) | 7) - -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_MSDC1_SDWPI (MTK_PIN_NO(64) | 1) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_EINT58 (MTK_PIN_NO(64) | 2) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_SDA5 (MTK_PIN_NO(64) | 3) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_PWM7 (MTK_PIN_NO(64) | 4) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_CLKM6 (MTK_PIN_NO(64) | 5) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_TESTB_OUT7 (MTK_PIN_NO(64) | 7) - -#define MT8135_PIN_65_MSDC2_INSI__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) -#define MT8135_PIN_65_MSDC2_INSI__FUNC_MSDC2_INSI (MTK_PIN_NO(65) | 1) -#define MT8135_PIN_65_MSDC2_INSI__FUNC_USB_TEST_IO_27 (MTK_PIN_NO(65) | 5) -#define MT8135_PIN_65_MSDC2_INSI__FUNC_TESTA_OUT3 (MTK_PIN_NO(65) | 7) - -#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) -#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_MSDC2_SDWPI (MTK_PIN_NO(66) | 1) -#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_EINT66 (MTK_PIN_NO(66) | 2) -#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_USB_TEST_IO_28 (MTK_PIN_NO(66) | 5) - -#define MT8135_PIN_67_URXD4__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) -#define MT8135_PIN_67_URXD4__FUNC_URXD4 (MTK_PIN_NO(67) | 1) -#define MT8135_PIN_67_URXD4__FUNC_EINT89 (MTK_PIN_NO(67) | 2) -#define MT8135_PIN_67_URXD4__FUNC_URXD1 (MTK_PIN_NO(67) | 3) -#define MT8135_PIN_67_URXD4__FUNC_UTXD4 (MTK_PIN_NO(67) | 6) -#define MT8135_PIN_67_URXD4__FUNC_TESTB_OUT10 (MTK_PIN_NO(67) | 7) - -#define MT8135_PIN_68_UTXD4__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) -#define MT8135_PIN_68_UTXD4__FUNC_UTXD4 (MTK_PIN_NO(68) | 1) -#define MT8135_PIN_68_UTXD4__FUNC_EINT88 (MTK_PIN_NO(68) | 2) -#define MT8135_PIN_68_UTXD4__FUNC_UTXD1 (MTK_PIN_NO(68) | 3) -#define MT8135_PIN_68_UTXD4__FUNC_URXD4 (MTK_PIN_NO(68) | 6) -#define MT8135_PIN_68_UTXD4__FUNC_TESTB_OUT11 (MTK_PIN_NO(68) | 7) - -#define MT8135_PIN_69_URXD1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) -#define MT8135_PIN_69_URXD1__FUNC_URXD1 (MTK_PIN_NO(69) | 1) -#define MT8135_PIN_69_URXD1__FUNC_EINT79 (MTK_PIN_NO(69) | 2) -#define MT8135_PIN_69_URXD1__FUNC_URXD4 (MTK_PIN_NO(69) | 3) -#define MT8135_PIN_69_URXD1__FUNC_UTXD1 (MTK_PIN_NO(69) | 6) -#define MT8135_PIN_69_URXD1__FUNC_TESTB_OUT24 (MTK_PIN_NO(69) | 7) - -#define MT8135_PIN_70_UTXD1__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) -#define MT8135_PIN_70_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(70) | 1) -#define MT8135_PIN_70_UTXD1__FUNC_EINT78 (MTK_PIN_NO(70) | 2) -#define MT8135_PIN_70_UTXD1__FUNC_UTXD4 (MTK_PIN_NO(70) | 3) -#define MT8135_PIN_70_UTXD1__FUNC_URXD1 (MTK_PIN_NO(70) | 6) -#define MT8135_PIN_70_UTXD1__FUNC_TESTB_OUT25 (MTK_PIN_NO(70) | 7) - -#define MT8135_PIN_71_UCTS1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) -#define MT8135_PIN_71_UCTS1__FUNC_UCTS1 (MTK_PIN_NO(71) | 1) -#define MT8135_PIN_71_UCTS1__FUNC_EINT80 (MTK_PIN_NO(71) | 2) -#define MT8135_PIN_71_UCTS1__FUNC_CLKM0 (MTK_PIN_NO(71) | 5) -#define MT8135_PIN_71_UCTS1__FUNC_URTS1 (MTK_PIN_NO(71) | 6) -#define MT8135_PIN_71_UCTS1__FUNC_TESTB_OUT31 (MTK_PIN_NO(71) | 7) - -#define MT8135_PIN_72_URTS1__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -#define MT8135_PIN_72_URTS1__FUNC_URTS1 (MTK_PIN_NO(72) | 1) -#define MT8135_PIN_72_URTS1__FUNC_EINT81 (MTK_PIN_NO(72) | 2) -#define MT8135_PIN_72_URTS1__FUNC_CLKM1 (MTK_PIN_NO(72) | 5) -#define MT8135_PIN_72_URTS1__FUNC_UCTS1 (MTK_PIN_NO(72) | 6) -#define MT8135_PIN_72_URTS1__FUNC_TESTB_OUT21 (MTK_PIN_NO(72) | 7) - -#define MT8135_PIN_73_PWM1__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -#define MT8135_PIN_73_PWM1__FUNC_PWM1 (MTK_PIN_NO(73) | 1) -#define MT8135_PIN_73_PWM1__FUNC_EINT73 (MTK_PIN_NO(73) | 2) -#define MT8135_PIN_73_PWM1__FUNC_USB_DRVVBUS (MTK_PIN_NO(73) | 5) -#define MT8135_PIN_73_PWM1__FUNC_DISP_PWM (MTK_PIN_NO(73) | 6) -#define MT8135_PIN_73_PWM1__FUNC_TESTB_OUT8 (MTK_PIN_NO(73) | 7) - -#define MT8135_PIN_74_PWM2__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) -#define MT8135_PIN_74_PWM2__FUNC_PWM2 (MTK_PIN_NO(74) | 1) -#define MT8135_PIN_74_PWM2__FUNC_EINT74 (MTK_PIN_NO(74) | 2) -#define MT8135_PIN_74_PWM2__FUNC_DPI33_CK (MTK_PIN_NO(74) | 3) -#define MT8135_PIN_74_PWM2__FUNC_PWM5 (MTK_PIN_NO(74) | 4) -#define MT8135_PIN_74_PWM2__FUNC_URXD2 (MTK_PIN_NO(74) | 5) -#define MT8135_PIN_74_PWM2__FUNC_DISP_PWM (MTK_PIN_NO(74) | 6) -#define MT8135_PIN_74_PWM2__FUNC_TESTB_OUT9 (MTK_PIN_NO(74) | 7) - -#define MT8135_PIN_75_PWM3__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) -#define MT8135_PIN_75_PWM3__FUNC_PWM3 (MTK_PIN_NO(75) | 1) -#define MT8135_PIN_75_PWM3__FUNC_EINT75 (MTK_PIN_NO(75) | 2) -#define MT8135_PIN_75_PWM3__FUNC_DPI33_D0 (MTK_PIN_NO(75) | 3) -#define MT8135_PIN_75_PWM3__FUNC_PWM6 (MTK_PIN_NO(75) | 4) -#define MT8135_PIN_75_PWM3__FUNC_UTXD2 (MTK_PIN_NO(75) | 5) -#define MT8135_PIN_75_PWM3__FUNC_DISP_PWM (MTK_PIN_NO(75) | 6) -#define MT8135_PIN_75_PWM3__FUNC_TESTB_OUT12 (MTK_PIN_NO(75) | 7) - -#define MT8135_PIN_76_PWM4__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) -#define MT8135_PIN_76_PWM4__FUNC_PWM4 (MTK_PIN_NO(76) | 1) -#define MT8135_PIN_76_PWM4__FUNC_EINT76 (MTK_PIN_NO(76) | 2) -#define MT8135_PIN_76_PWM4__FUNC_DPI33_D1 (MTK_PIN_NO(76) | 3) -#define MT8135_PIN_76_PWM4__FUNC_PWM7 (MTK_PIN_NO(76) | 4) -#define MT8135_PIN_76_PWM4__FUNC_DISP_PWM (MTK_PIN_NO(76) | 6) -#define MT8135_PIN_76_PWM4__FUNC_TESTB_OUT13 (MTK_PIN_NO(76) | 7) - -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(77) | 1) -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_EINT63 (MTK_PIN_NO(77) | 2) -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DSP2_IMS (MTK_PIN_NO(77) | 4) -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DPI33_D6 (MTK_PIN_NO(77) | 6) -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_TESTA_OUT25 (MTK_PIN_NO(77) | 7) - -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(78) | 1) -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_EINT64 (MTK_PIN_NO(78) | 2) -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DSP2_ID (MTK_PIN_NO(78) | 4) -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DPI33_D7 (MTK_PIN_NO(78) | 6) -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_TESTA_OUT26 (MTK_PIN_NO(78) | 7) - -#define MT8135_PIN_79_MSDC2_CMD__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(79) | 1) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_EINT60 (MTK_PIN_NO(79) | 2) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_DSP1_IMS (MTK_PIN_NO(79) | 4) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_PCM1_WS (MTK_PIN_NO(79) | 5) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_DPI33_D3 (MTK_PIN_NO(79) | 6) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_TESTA_OUT0 (MTK_PIN_NO(79) | 7) - -#define MT8135_PIN_80_MSDC2_CLK__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(80) | 1) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_EINT59 (MTK_PIN_NO(80) | 2) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_DSP1_ICK (MTK_PIN_NO(80) | 4) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_PCM1_CK (MTK_PIN_NO(80) | 5) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_DPI33_D2 (MTK_PIN_NO(80) | 6) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_TESTA_OUT1 (MTK_PIN_NO(80) | 7) - -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(81) | 1) -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_EINT62 (MTK_PIN_NO(81) | 2) -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DSP2_ICK (MTK_PIN_NO(81) | 4) -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_PCM1_DO (MTK_PIN_NO(81) | 5) -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DPI33_D5 (MTK_PIN_NO(81) | 6) - -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1) -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_EINT61 (MTK_PIN_NO(82) | 2) -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DSP1_ID (MTK_PIN_NO(82) | 4) -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_PCM1_DI (MTK_PIN_NO(82) | 5) -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DPI33_D4 (MTK_PIN_NO(82) | 6) - -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(83) | 1) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_EINT53 (MTK_PIN_NO(83) | 2) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_SCL1 (MTK_PIN_NO(83) | 3) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_PWM2 (MTK_PIN_NO(83) | 4) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_CLKM1 (MTK_PIN_NO(83) | 5) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_TESTB_OUT2 (MTK_PIN_NO(83) | 7) - -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(84) | 1) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_EINT54 (MTK_PIN_NO(84) | 2) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_SDA1 (MTK_PIN_NO(84) | 3) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_PWM3 (MTK_PIN_NO(84) | 4) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_CLKM2 (MTK_PIN_NO(84) | 5) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_TESTB_OUT3 (MTK_PIN_NO(84) | 7) - -#define MT8135_PIN_85_MSDC1_CMD__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(85) | 1) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_EINT52 (MTK_PIN_NO(85) | 2) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_SDA0 (MTK_PIN_NO(85) | 3) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_PWM1 (MTK_PIN_NO(85) | 4) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_CLKM0 (MTK_PIN_NO(85) | 5) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_TESTB_OUT1 (MTK_PIN_NO(85) | 7) - -#define MT8135_PIN_86_MSDC1_CLK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) -#define MT8135_PIN_86_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(86) | 1) -#define MT8135_PIN_86_MSDC1_CLK__FUNC_EINT51 (MTK_PIN_NO(86) | 2) -#define MT8135_PIN_86_MSDC1_CLK__FUNC_SCL0 (MTK_PIN_NO(86) | 3) -#define MT8135_PIN_86_MSDC1_CLK__FUNC_DISP_PWM (MTK_PIN_NO(86) | 4) -#define MT8135_PIN_86_MSDC1_CLK__FUNC_TESTB_OUT0 (MTK_PIN_NO(86) | 7) - -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(87) | 1) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_EINT55 (MTK_PIN_NO(87) | 2) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_SCL4 (MTK_PIN_NO(87) | 3) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_PWM4 (MTK_PIN_NO(87) | 4) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_CLKM3 (MTK_PIN_NO(87) | 5) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_TESTB_OUT4 (MTK_PIN_NO(87) | 7) - -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(88) | 1) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_EINT56 (MTK_PIN_NO(88) | 2) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_SDA4 (MTK_PIN_NO(88) | 3) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_PWM5 (MTK_PIN_NO(88) | 4) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_CLKM4 (MTK_PIN_NO(88) | 5) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_TESTB_OUT5 (MTK_PIN_NO(88) | 7) - -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_MSDC4_DAT0 (MTK_PIN_NO(89) | 1) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EINT133 (MTK_PIN_NO(89) | 2) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(89) | 4) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_USB_DRVVBUS (MTK_PIN_NO(89) | 5) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_A_FUNC_DIN_9 (MTK_PIN_NO(89) | 6) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_LPTE (MTK_PIN_NO(89) | 7) - -#define MT8135_PIN_90_MSDC4_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) -#define MT8135_PIN_90_MSDC4_DAT1__FUNC_MSDC4_DAT1 (MTK_PIN_NO(90) | 1) -#define MT8135_PIN_90_MSDC4_DAT1__FUNC_EINT134 (MTK_PIN_NO(90) | 2) -#define MT8135_PIN_90_MSDC4_DAT1__FUNC_A_FUNC_DIN_10 (MTK_PIN_NO(90) | 6) -#define MT8135_PIN_90_MSDC4_DAT1__FUNC_LRSTB_1X (MTK_PIN_NO(90) | 7) - -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_MSDC4_DAT5 (MTK_PIN_NO(91) | 1) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_EINT136 (MTK_PIN_NO(91) | 2) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_I2SIN_WS (MTK_PIN_NO(91) | 3) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_DAC_WS (MTK_PIN_NO(91) | 4) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_PCM1_WS (MTK_PIN_NO(91) | 5) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_A_FUNC_DIN_11 (MTK_PIN_NO(91) | 6) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_SPI1_CSN (MTK_PIN_NO(91) | 7) - -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_MSDC4_DAT6 (MTK_PIN_NO(92) | 1) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_EINT137 (MTK_PIN_NO(92) | 2) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_I2SOUT_DAT (MTK_PIN_NO(92) | 3) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_DAC_DAT_OUT (MTK_PIN_NO(92) | 4) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_PCM1_DO (MTK_PIN_NO(92) | 5) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_A_FUNC_DIN_12 (MTK_PIN_NO(92) | 6) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_SPI1_MO (MTK_PIN_NO(92) | 7) - -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_MSDC4_DAT7 (MTK_PIN_NO(93) | 1) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_EINT138 (MTK_PIN_NO(93) | 2) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_I2SIN_DAT (MTK_PIN_NO(93) | 3) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_PCM1_DI (MTK_PIN_NO(93) | 5) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_A_FUNC_DIN_13 (MTK_PIN_NO(93) | 6) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_SPI1_MI (MTK_PIN_NO(93) | 7) - -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_MSDC4_DAT4 (MTK_PIN_NO(94) | 1) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_EINT135 (MTK_PIN_NO(94) | 2) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_I2SIN_CK (MTK_PIN_NO(94) | 3) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_DAC_CK (MTK_PIN_NO(94) | 4) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_PCM1_CK (MTK_PIN_NO(94) | 5) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_A_FUNC_DIN_14 (MTK_PIN_NO(94) | 6) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_SPI1_CLK (MTK_PIN_NO(94) | 7) - -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_MSDC4_DAT2 (MTK_PIN_NO(95) | 1) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_EINT131 (MTK_PIN_NO(95) | 2) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_I2SIN_WS (MTK_PIN_NO(95) | 3) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_CM2PDN_2X (MTK_PIN_NO(95) | 4) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_DAC_WS (MTK_PIN_NO(95) | 5) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_PCM1_WS (MTK_PIN_NO(95) | 6) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_LSCE0B_1X (MTK_PIN_NO(95) | 7) - -#define MT8135_PIN_96_MSDC4_CLK__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_MSDC4_CLK (MTK_PIN_NO(96) | 1) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_EINT129 (MTK_PIN_NO(96) | 2) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_DPI1_CK_2X (MTK_PIN_NO(96) | 3) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_CM2PCLK_2X (MTK_PIN_NO(96) | 4) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_PWM4 (MTK_PIN_NO(96) | 5) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_PCM1_DI (MTK_PIN_NO(96) | 6) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_LSCK_1X (MTK_PIN_NO(96) | 7) - -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_MSDC4_DAT3 (MTK_PIN_NO(97) | 1) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_EINT132 (MTK_PIN_NO(97) | 2) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_I2SOUT_DAT (MTK_PIN_NO(97) | 3) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_CM2RST_2X (MTK_PIN_NO(97) | 4) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_DAC_DAT_OUT (MTK_PIN_NO(97) | 5) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_PCM1_DO (MTK_PIN_NO(97) | 6) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_LSCE1B_1X (MTK_PIN_NO(97) | 7) - -#define MT8135_PIN_98_MSDC4_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) -#define MT8135_PIN_98_MSDC4_CMD__FUNC_MSDC4_CMD (MTK_PIN_NO(98) | 1) -#define MT8135_PIN_98_MSDC4_CMD__FUNC_EINT128 (MTK_PIN_NO(98) | 2) -#define MT8135_PIN_98_MSDC4_CMD__FUNC_DPI1_DE_2X (MTK_PIN_NO(98) | 3) -#define MT8135_PIN_98_MSDC4_CMD__FUNC_PWM3 (MTK_PIN_NO(98) | 5) -#define MT8135_PIN_98_MSDC4_CMD__FUNC_LSDA_1X (MTK_PIN_NO(98) | 7) - -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_MSDC4_RSTB (MTK_PIN_NO(99) | 1) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_EINT130 (MTK_PIN_NO(99) | 2) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_I2SIN_CK (MTK_PIN_NO(99) | 3) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_CM2MCLK_2X (MTK_PIN_NO(99) | 4) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_DAC_CK (MTK_PIN_NO(99) | 5) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_PCM1_CK (MTK_PIN_NO(99) | 6) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_LSA0_1X (MTK_PIN_NO(99) | 7) - -#define MT8135_PIN_100_SDA0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) -#define MT8135_PIN_100_SDA0__FUNC_SDA0 (MTK_PIN_NO(100) | 1) -#define MT8135_PIN_100_SDA0__FUNC_EINT91 (MTK_PIN_NO(100) | 2) -#define MT8135_PIN_100_SDA0__FUNC_CLKM1 (MTK_PIN_NO(100) | 3) -#define MT8135_PIN_100_SDA0__FUNC_PWM1 (MTK_PIN_NO(100) | 4) -#define MT8135_PIN_100_SDA0__FUNC_A_FUNC_DIN_15 (MTK_PIN_NO(100) | 7) - -#define MT8135_PIN_101_SCL0__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define MT8135_PIN_101_SCL0__FUNC_SCL0 (MTK_PIN_NO(101) | 1) -#define MT8135_PIN_101_SCL0__FUNC_EINT90 (MTK_PIN_NO(101) | 2) -#define MT8135_PIN_101_SCL0__FUNC_CLKM0 (MTK_PIN_NO(101) | 3) -#define MT8135_PIN_101_SCL0__FUNC_DISP_PWM (MTK_PIN_NO(101) | 4) -#define MT8135_PIN_101_SCL0__FUNC_A_FUNC_DIN_16 (MTK_PIN_NO(101) | 7) - -#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_EINT10 (MTK_PIN_NO(102) | 1) -#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_USB_TEST_IO_16 (MTK_PIN_NO(102) | 5) -#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_TESTB_OUT16 (MTK_PIN_NO(102) | 6) -#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_A_FUNC_DIN_17 (MTK_PIN_NO(102) | 7) - -#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_EINT11 (MTK_PIN_NO(103) | 1) -#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_USB_TEST_IO_17 (MTK_PIN_NO(103) | 5) -#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_TESTB_OUT17 (MTK_PIN_NO(103) | 6) -#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_A_FUNC_DIN_18 (MTK_PIN_NO(103) | 7) - -#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_EINT16 (MTK_PIN_NO(104) | 1) -#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_USB_TEST_IO_18 (MTK_PIN_NO(104) | 5) -#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_TESTB_OUT18 (MTK_PIN_NO(104) | 6) -#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_A_FUNC_DIN_19 (MTK_PIN_NO(104) | 7) - -#define MT8135_PIN_105_I2S_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define MT8135_PIN_105_I2S_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(105) | 1) -#define MT8135_PIN_105_I2S_CLK__FUNC_EINT10 (MTK_PIN_NO(105) | 2) -#define MT8135_PIN_105_I2S_CLK__FUNC_DAC_CK (MTK_PIN_NO(105) | 3) -#define MT8135_PIN_105_I2S_CLK__FUNC_PCM1_CK (MTK_PIN_NO(105) | 4) -#define MT8135_PIN_105_I2S_CLK__FUNC_USB_TEST_IO_19 (MTK_PIN_NO(105) | 5) -#define MT8135_PIN_105_I2S_CLK__FUNC_TESTB_OUT19 (MTK_PIN_NO(105) | 6) -#define MT8135_PIN_105_I2S_CLK__FUNC_A_FUNC_DIN_20 (MTK_PIN_NO(105) | 7) - -#define MT8135_PIN_106_I2S_WS__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define MT8135_PIN_106_I2S_WS__FUNC_I2SIN_WS (MTK_PIN_NO(106) | 1) -#define MT8135_PIN_106_I2S_WS__FUNC_EINT13 (MTK_PIN_NO(106) | 2) -#define MT8135_PIN_106_I2S_WS__FUNC_DAC_WS (MTK_PIN_NO(106) | 3) -#define MT8135_PIN_106_I2S_WS__FUNC_PCM1_WS (MTK_PIN_NO(106) | 4) -#define MT8135_PIN_106_I2S_WS__FUNC_USB_TEST_IO_20 (MTK_PIN_NO(106) | 5) -#define MT8135_PIN_106_I2S_WS__FUNC_TESTB_OUT20 (MTK_PIN_NO(106) | 6) -#define MT8135_PIN_106_I2S_WS__FUNC_A_FUNC_DIN_21 (MTK_PIN_NO(106) | 7) - -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_I2SIN_DAT (MTK_PIN_NO(107) | 1) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_EINT11 (MTK_PIN_NO(107) | 2) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_PCM1_DI (MTK_PIN_NO(107) | 4) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_USB_TEST_IO_21 (MTK_PIN_NO(107) | 5) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_TESTB_OUT22 (MTK_PIN_NO(107) | 6) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_A_FUNC_DIN_22 (MTK_PIN_NO(107) | 7) - -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_I2SOUT_DAT (MTK_PIN_NO(108) | 1) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_EINT12 (MTK_PIN_NO(108) | 2) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(108) | 3) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_PCM1_DO (MTK_PIN_NO(108) | 4) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_USB_TEST_IO_22 (MTK_PIN_NO(108) | 5) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_TESTB_OUT23 (MTK_PIN_NO(108) | 6) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_A_FUNC_DIN_23 (MTK_PIN_NO(108) | 7) - -#define MT8135_PIN_109_EINT5__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define MT8135_PIN_109_EINT5__FUNC_EINT5 (MTK_PIN_NO(109) | 1) -#define MT8135_PIN_109_EINT5__FUNC_PWM5 (MTK_PIN_NO(109) | 2) -#define MT8135_PIN_109_EINT5__FUNC_CLKM3 (MTK_PIN_NO(109) | 3) -#define MT8135_PIN_109_EINT5__FUNC_GPU_JTRSTB (MTK_PIN_NO(109) | 4) -#define MT8135_PIN_109_EINT5__FUNC_USB_TEST_IO_23 (MTK_PIN_NO(109) | 5) -#define MT8135_PIN_109_EINT5__FUNC_TESTB_OUT26 (MTK_PIN_NO(109) | 6) -#define MT8135_PIN_109_EINT5__FUNC_A_FUNC_DIN_24 (MTK_PIN_NO(109) | 7) - -#define MT8135_PIN_110_EINT6__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define MT8135_PIN_110_EINT6__FUNC_EINT6 (MTK_PIN_NO(110) | 1) -#define MT8135_PIN_110_EINT6__FUNC_PWM6 (MTK_PIN_NO(110) | 2) -#define MT8135_PIN_110_EINT6__FUNC_CLKM4 (MTK_PIN_NO(110) | 3) -#define MT8135_PIN_110_EINT6__FUNC_GPU_JTMS (MTK_PIN_NO(110) | 4) -#define MT8135_PIN_110_EINT6__FUNC_USB_TEST_IO_24 (MTK_PIN_NO(110) | 5) -#define MT8135_PIN_110_EINT6__FUNC_TESTB_OUT27 (MTK_PIN_NO(110) | 6) -#define MT8135_PIN_110_EINT6__FUNC_A_FUNC_DIN_25 (MTK_PIN_NO(110) | 7) - -#define MT8135_PIN_111_EINT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define MT8135_PIN_111_EINT7__FUNC_EINT7 (MTK_PIN_NO(111) | 1) -#define MT8135_PIN_111_EINT7__FUNC_PWM7 (MTK_PIN_NO(111) | 2) -#define MT8135_PIN_111_EINT7__FUNC_CLKM5 (MTK_PIN_NO(111) | 3) -#define MT8135_PIN_111_EINT7__FUNC_GPU_JTDO (MTK_PIN_NO(111) | 4) -#define MT8135_PIN_111_EINT7__FUNC_USB_TEST_IO_25 (MTK_PIN_NO(111) | 5) -#define MT8135_PIN_111_EINT7__FUNC_TESTB_OUT28 (MTK_PIN_NO(111) | 6) -#define MT8135_PIN_111_EINT7__FUNC_A_FUNC_DIN_26 (MTK_PIN_NO(111) | 7) - -#define MT8135_PIN_112_EINT8__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define MT8135_PIN_112_EINT8__FUNC_EINT8 (MTK_PIN_NO(112) | 1) -#define MT8135_PIN_112_EINT8__FUNC_DISP_PWM (MTK_PIN_NO(112) | 2) -#define MT8135_PIN_112_EINT8__FUNC_CLKM6 (MTK_PIN_NO(112) | 3) -#define MT8135_PIN_112_EINT8__FUNC_GPU_JTDI (MTK_PIN_NO(112) | 4) -#define MT8135_PIN_112_EINT8__FUNC_USB_TEST_IO_26 (MTK_PIN_NO(112) | 5) -#define MT8135_PIN_112_EINT8__FUNC_TESTB_OUT29 (MTK_PIN_NO(112) | 6) -#define MT8135_PIN_112_EINT8__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(112) | 7) - -#define MT8135_PIN_113_EINT9__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define MT8135_PIN_113_EINT9__FUNC_EINT9 (MTK_PIN_NO(113) | 1) -#define MT8135_PIN_113_EINT9__FUNC_GPU_JTCK (MTK_PIN_NO(113) | 4) -#define MT8135_PIN_113_EINT9__FUNC_USB_DRVVBUS (MTK_PIN_NO(113) | 5) -#define MT8135_PIN_113_EINT9__FUNC_TESTB_OUT30 (MTK_PIN_NO(113) | 6) -#define MT8135_PIN_113_EINT9__FUNC_A_FUNC_DIN_27 (MTK_PIN_NO(113) | 7) - -#define MT8135_PIN_114_LPCE1B__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define MT8135_PIN_114_LPCE1B__FUNC_LPCE1B (MTK_PIN_NO(114) | 1) -#define MT8135_PIN_114_LPCE1B__FUNC_EINT127 (MTK_PIN_NO(114) | 2) -#define MT8135_PIN_114_LPCE1B__FUNC_PWM2 (MTK_PIN_NO(114) | 5) -#define MT8135_PIN_114_LPCE1B__FUNC_TESTB_OUT14 (MTK_PIN_NO(114) | 6) -#define MT8135_PIN_114_LPCE1B__FUNC_A_FUNC_DIN_28 (MTK_PIN_NO(114) | 7) - -#define MT8135_PIN_115_LPCE0B__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define MT8135_PIN_115_LPCE0B__FUNC_LPCE0B (MTK_PIN_NO(115) | 1) -#define MT8135_PIN_115_LPCE0B__FUNC_EINT126 (MTK_PIN_NO(115) | 2) -#define MT8135_PIN_115_LPCE0B__FUNC_PWM1 (MTK_PIN_NO(115) | 5) -#define MT8135_PIN_115_LPCE0B__FUNC_TESTB_OUT15 (MTK_PIN_NO(115) | 6) -#define MT8135_PIN_115_LPCE0B__FUNC_A_FUNC_DIN_29 (MTK_PIN_NO(115) | 7) - -#define MT8135_PIN_116_DISP_PWM__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define MT8135_PIN_116_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(116) | 1) -#define MT8135_PIN_116_DISP_PWM__FUNC_EINT77 (MTK_PIN_NO(116) | 2) -#define MT8135_PIN_116_DISP_PWM__FUNC_LSDI (MTK_PIN_NO(116) | 3) -#define MT8135_PIN_116_DISP_PWM__FUNC_PWM1 (MTK_PIN_NO(116) | 4) -#define MT8135_PIN_116_DISP_PWM__FUNC_PWM2 (MTK_PIN_NO(116) | 5) -#define MT8135_PIN_116_DISP_PWM__FUNC_PWM3 (MTK_PIN_NO(116) | 7) - -#define MT8135_PIN_117_EINT1__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define MT8135_PIN_117_EINT1__FUNC_EINT1 (MTK_PIN_NO(117) | 1) -#define MT8135_PIN_117_EINT1__FUNC_PWM2 (MTK_PIN_NO(117) | 2) -#define MT8135_PIN_117_EINT1__FUNC_CLKM1 (MTK_PIN_NO(117) | 3) -#define MT8135_PIN_117_EINT1__FUNC_USB_TEST_IO_13 (MTK_PIN_NO(117) | 5) -#define MT8135_PIN_117_EINT1__FUNC_USB_SDA (MTK_PIN_NO(117) | 7) - -#define MT8135_PIN_118_EINT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define MT8135_PIN_118_EINT2__FUNC_EINT2 (MTK_PIN_NO(118) | 1) -#define MT8135_PIN_118_EINT2__FUNC_PWM3 (MTK_PIN_NO(118) | 2) -#define MT8135_PIN_118_EINT2__FUNC_CLKM2 (MTK_PIN_NO(118) | 3) -#define MT8135_PIN_118_EINT2__FUNC_USB_TEST_IO_14 (MTK_PIN_NO(118) | 5) -#define MT8135_PIN_118_EINT2__FUNC_SRCLKENAI2 (MTK_PIN_NO(118) | 6) -#define MT8135_PIN_118_EINT2__FUNC_A_FUNC_DIN_30 (MTK_PIN_NO(118) | 7) - -#define MT8135_PIN_119_EINT3__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define MT8135_PIN_119_EINT3__FUNC_EINT3 (MTK_PIN_NO(119) | 1) -#define MT8135_PIN_119_EINT3__FUNC_USB_TEST_IO_15 (MTK_PIN_NO(119) | 5) -#define MT8135_PIN_119_EINT3__FUNC_SRCLKENAI1 (MTK_PIN_NO(119) | 6) -#define MT8135_PIN_119_EINT3__FUNC_EXT_26M_CK (MTK_PIN_NO(119) | 7) - -#define MT8135_PIN_120_EINT4__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define MT8135_PIN_120_EINT4__FUNC_EINT4 (MTK_PIN_NO(120) | 1) -#define MT8135_PIN_120_EINT4__FUNC_PWM4 (MTK_PIN_NO(120) | 2) -#define MT8135_PIN_120_EINT4__FUNC_USB_DRVVBUS (MTK_PIN_NO(120) | 5) -#define MT8135_PIN_120_EINT4__FUNC_A_FUNC_DIN_31 (MTK_PIN_NO(120) | 7) - -#define MT8135_PIN_121_DPIDE__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) -#define MT8135_PIN_121_DPIDE__FUNC_DPI0_DE (MTK_PIN_NO(121) | 1) -#define MT8135_PIN_121_DPIDE__FUNC_EINT100 (MTK_PIN_NO(121) | 2) -#define MT8135_PIN_121_DPIDE__FUNC_I2SOUT_DAT (MTK_PIN_NO(121) | 3) -#define MT8135_PIN_121_DPIDE__FUNC_DAC_DAT_OUT (MTK_PIN_NO(121) | 4) -#define MT8135_PIN_121_DPIDE__FUNC_PCM1_DO (MTK_PIN_NO(121) | 5) -#define MT8135_PIN_121_DPIDE__FUNC_IRDA_TXD (MTK_PIN_NO(121) | 6) - -#define MT8135_PIN_122_DPICK__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define MT8135_PIN_122_DPICK__FUNC_DPI0_CK (MTK_PIN_NO(122) | 1) -#define MT8135_PIN_122_DPICK__FUNC_EINT101 (MTK_PIN_NO(122) | 2) -#define MT8135_PIN_122_DPICK__FUNC_I2SIN_DAT (MTK_PIN_NO(122) | 3) -#define MT8135_PIN_122_DPICK__FUNC_PCM1_DI (MTK_PIN_NO(122) | 5) -#define MT8135_PIN_122_DPICK__FUNC_IRDA_PDN (MTK_PIN_NO(122) | 6) - -#define MT8135_PIN_123_DPIG4__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) -#define MT8135_PIN_123_DPIG4__FUNC_DPI0_G4 (MTK_PIN_NO(123) | 1) -#define MT8135_PIN_123_DPIG4__FUNC_EINT114 (MTK_PIN_NO(123) | 2) -#define MT8135_PIN_123_DPIG4__FUNC_CM2DAT_2X_0 (MTK_PIN_NO(123) | 4) -#define MT8135_PIN_123_DPIG4__FUNC_DSP2_ID (MTK_PIN_NO(123) | 5) - -#define MT8135_PIN_124_DPIG5__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define MT8135_PIN_124_DPIG5__FUNC_DPI0_G5 (MTK_PIN_NO(124) | 1) -#define MT8135_PIN_124_DPIG5__FUNC_EINT115 (MTK_PIN_NO(124) | 2) -#define MT8135_PIN_124_DPIG5__FUNC_CM2DAT_2X_1 (MTK_PIN_NO(124) | 4) -#define MT8135_PIN_124_DPIG5__FUNC_DSP2_ICK (MTK_PIN_NO(124) | 5) - -#define MT8135_PIN_125_DPIR3__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define MT8135_PIN_125_DPIR3__FUNC_DPI0_R3 (MTK_PIN_NO(125) | 1) -#define MT8135_PIN_125_DPIR3__FUNC_EINT121 (MTK_PIN_NO(125) | 2) -#define MT8135_PIN_125_DPIR3__FUNC_CM2DAT_2X_7 (MTK_PIN_NO(125) | 4) - -#define MT8135_PIN_126_DPIG1__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) -#define MT8135_PIN_126_DPIG1__FUNC_DPI0_G1 (MTK_PIN_NO(126) | 1) -#define MT8135_PIN_126_DPIG1__FUNC_EINT111 (MTK_PIN_NO(126) | 2) -#define MT8135_PIN_126_DPIG1__FUNC_DSP1_ICK (MTK_PIN_NO(126) | 5) - -#define MT8135_PIN_127_DPIVSYNC__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) -#define MT8135_PIN_127_DPIVSYNC__FUNC_DPI0_VSYNC (MTK_PIN_NO(127) | 1) -#define MT8135_PIN_127_DPIVSYNC__FUNC_EINT98 (MTK_PIN_NO(127) | 2) -#define MT8135_PIN_127_DPIVSYNC__FUNC_I2SIN_CK (MTK_PIN_NO(127) | 3) -#define MT8135_PIN_127_DPIVSYNC__FUNC_DAC_CK (MTK_PIN_NO(127) | 4) -#define MT8135_PIN_127_DPIVSYNC__FUNC_PCM1_CK (MTK_PIN_NO(127) | 5) - -#define MT8135_PIN_128_DPIHSYNC__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) -#define MT8135_PIN_128_DPIHSYNC__FUNC_DPI0_HSYNC (MTK_PIN_NO(128) | 1) -#define MT8135_PIN_128_DPIHSYNC__FUNC_EINT99 (MTK_PIN_NO(128) | 2) -#define MT8135_PIN_128_DPIHSYNC__FUNC_I2SIN_WS (MTK_PIN_NO(128) | 3) -#define MT8135_PIN_128_DPIHSYNC__FUNC_DAC_WS (MTK_PIN_NO(128) | 4) -#define MT8135_PIN_128_DPIHSYNC__FUNC_PCM1_WS (MTK_PIN_NO(128) | 5) -#define MT8135_PIN_128_DPIHSYNC__FUNC_IRDA_RXD (MTK_PIN_NO(128) | 6) - -#define MT8135_PIN_129_DPIB0__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) -#define MT8135_PIN_129_DPIB0__FUNC_DPI0_B0 (MTK_PIN_NO(129) | 1) -#define MT8135_PIN_129_DPIB0__FUNC_EINT102 (MTK_PIN_NO(129) | 2) -#define MT8135_PIN_129_DPIB0__FUNC_SCL0 (MTK_PIN_NO(129) | 4) -#define MT8135_PIN_129_DPIB0__FUNC_DISP_PWM (MTK_PIN_NO(129) | 5) - -#define MT8135_PIN_130_DPIB1__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) -#define MT8135_PIN_130_DPIB1__FUNC_DPI0_B1 (MTK_PIN_NO(130) | 1) -#define MT8135_PIN_130_DPIB1__FUNC_EINT103 (MTK_PIN_NO(130) | 2) -#define MT8135_PIN_130_DPIB1__FUNC_CLKM0 (MTK_PIN_NO(130) | 3) -#define MT8135_PIN_130_DPIB1__FUNC_SDA0 (MTK_PIN_NO(130) | 4) -#define MT8135_PIN_130_DPIB1__FUNC_PWM1 (MTK_PIN_NO(130) | 5) - -#define MT8135_PIN_131_DPIB2__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) -#define MT8135_PIN_131_DPIB2__FUNC_DPI0_B2 (MTK_PIN_NO(131) | 1) -#define MT8135_PIN_131_DPIB2__FUNC_EINT104 (MTK_PIN_NO(131) | 2) -#define MT8135_PIN_131_DPIB2__FUNC_CLKM1 (MTK_PIN_NO(131) | 3) -#define MT8135_PIN_131_DPIB2__FUNC_SCL1 (MTK_PIN_NO(131) | 4) -#define MT8135_PIN_131_DPIB2__FUNC_PWM2 (MTK_PIN_NO(131) | 5) - -#define MT8135_PIN_132_DPIB3__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) -#define MT8135_PIN_132_DPIB3__FUNC_DPI0_B3 (MTK_PIN_NO(132) | 1) -#define MT8135_PIN_132_DPIB3__FUNC_EINT105 (MTK_PIN_NO(132) | 2) -#define MT8135_PIN_132_DPIB3__FUNC_CLKM2 (MTK_PIN_NO(132) | 3) -#define MT8135_PIN_132_DPIB3__FUNC_SDA1 (MTK_PIN_NO(132) | 4) -#define MT8135_PIN_132_DPIB3__FUNC_PWM3 (MTK_PIN_NO(132) | 5) - -#define MT8135_PIN_133_DPIB4__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) -#define MT8135_PIN_133_DPIB4__FUNC_DPI0_B4 (MTK_PIN_NO(133) | 1) -#define MT8135_PIN_133_DPIB4__FUNC_EINT106 (MTK_PIN_NO(133) | 2) -#define MT8135_PIN_133_DPIB4__FUNC_CLKM3 (MTK_PIN_NO(133) | 3) -#define MT8135_PIN_133_DPIB4__FUNC_SCL2 (MTK_PIN_NO(133) | 4) -#define MT8135_PIN_133_DPIB4__FUNC_PWM4 (MTK_PIN_NO(133) | 5) - -#define MT8135_PIN_134_DPIB5__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) -#define MT8135_PIN_134_DPIB5__FUNC_DPI0_B5 (MTK_PIN_NO(134) | 1) -#define MT8135_PIN_134_DPIB5__FUNC_EINT107 (MTK_PIN_NO(134) | 2) -#define MT8135_PIN_134_DPIB5__FUNC_CLKM4 (MTK_PIN_NO(134) | 3) -#define MT8135_PIN_134_DPIB5__FUNC_SDA2 (MTK_PIN_NO(134) | 4) -#define MT8135_PIN_134_DPIB5__FUNC_PWM5 (MTK_PIN_NO(134) | 5) - -#define MT8135_PIN_135_DPIB6__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) -#define MT8135_PIN_135_DPIB6__FUNC_DPI0_B6 (MTK_PIN_NO(135) | 1) -#define MT8135_PIN_135_DPIB6__FUNC_EINT108 (MTK_PIN_NO(135) | 2) -#define MT8135_PIN_135_DPIB6__FUNC_CLKM5 (MTK_PIN_NO(135) | 3) -#define MT8135_PIN_135_DPIB6__FUNC_SCL3 (MTK_PIN_NO(135) | 4) -#define MT8135_PIN_135_DPIB6__FUNC_PWM6 (MTK_PIN_NO(135) | 5) - -#define MT8135_PIN_136_DPIB7__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) -#define MT8135_PIN_136_DPIB7__FUNC_DPI0_B7 (MTK_PIN_NO(136) | 1) -#define MT8135_PIN_136_DPIB7__FUNC_EINT109 (MTK_PIN_NO(136) | 2) -#define MT8135_PIN_136_DPIB7__FUNC_CLKM6 (MTK_PIN_NO(136) | 3) -#define MT8135_PIN_136_DPIB7__FUNC_SDA3 (MTK_PIN_NO(136) | 4) -#define MT8135_PIN_136_DPIB7__FUNC_PWM7 (MTK_PIN_NO(136) | 5) - -#define MT8135_PIN_137_DPIG0__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) -#define MT8135_PIN_137_DPIG0__FUNC_DPI0_G0 (MTK_PIN_NO(137) | 1) -#define MT8135_PIN_137_DPIG0__FUNC_EINT110 (MTK_PIN_NO(137) | 2) -#define MT8135_PIN_137_DPIG0__FUNC_DSP1_ID (MTK_PIN_NO(137) | 5) - -#define MT8135_PIN_138_DPIG2__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) -#define MT8135_PIN_138_DPIG2__FUNC_DPI0_G2 (MTK_PIN_NO(138) | 1) -#define MT8135_PIN_138_DPIG2__FUNC_EINT112 (MTK_PIN_NO(138) | 2) -#define MT8135_PIN_138_DPIG2__FUNC_DSP1_IMS (MTK_PIN_NO(138) | 5) - -#define MT8135_PIN_139_DPIG3__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) -#define MT8135_PIN_139_DPIG3__FUNC_DPI0_G3 (MTK_PIN_NO(139) | 1) -#define MT8135_PIN_139_DPIG3__FUNC_EINT113 (MTK_PIN_NO(139) | 2) -#define MT8135_PIN_139_DPIG3__FUNC_DSP2_IMS (MTK_PIN_NO(139) | 5) - -#define MT8135_PIN_140_DPIG6__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) -#define MT8135_PIN_140_DPIG6__FUNC_DPI0_G6 (MTK_PIN_NO(140) | 1) -#define MT8135_PIN_140_DPIG6__FUNC_EINT116 (MTK_PIN_NO(140) | 2) -#define MT8135_PIN_140_DPIG6__FUNC_CM2DAT_2X_2 (MTK_PIN_NO(140) | 4) - -#define MT8135_PIN_141_DPIG7__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) -#define MT8135_PIN_141_DPIG7__FUNC_DPI0_G7 (MTK_PIN_NO(141) | 1) -#define MT8135_PIN_141_DPIG7__FUNC_EINT117 (MTK_PIN_NO(141) | 2) -#define MT8135_PIN_141_DPIG7__FUNC_CM2DAT_2X_3 (MTK_PIN_NO(141) | 4) - -#define MT8135_PIN_142_DPIR0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) -#define MT8135_PIN_142_DPIR0__FUNC_DPI0_R0 (MTK_PIN_NO(142) | 1) -#define MT8135_PIN_142_DPIR0__FUNC_EINT118 (MTK_PIN_NO(142) | 2) -#define MT8135_PIN_142_DPIR0__FUNC_CM2DAT_2X_4 (MTK_PIN_NO(142) | 4) - -#define MT8135_PIN_143_DPIR1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) -#define MT8135_PIN_143_DPIR1__FUNC_DPI0_R1 (MTK_PIN_NO(143) | 1) -#define MT8135_PIN_143_DPIR1__FUNC_EINT119 (MTK_PIN_NO(143) | 2) -#define MT8135_PIN_143_DPIR1__FUNC_CM2DAT_2X_5 (MTK_PIN_NO(143) | 4) - -#define MT8135_PIN_144_DPIR2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) -#define MT8135_PIN_144_DPIR2__FUNC_DPI0_R2 (MTK_PIN_NO(144) | 1) -#define MT8135_PIN_144_DPIR2__FUNC_EINT120 (MTK_PIN_NO(144) | 2) -#define MT8135_PIN_144_DPIR2__FUNC_CM2DAT_2X_6 (MTK_PIN_NO(144) | 4) - -#define MT8135_PIN_145_DPIR4__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) -#define MT8135_PIN_145_DPIR4__FUNC_DPI0_R4 (MTK_PIN_NO(145) | 1) -#define MT8135_PIN_145_DPIR4__FUNC_EINT122 (MTK_PIN_NO(145) | 2) -#define MT8135_PIN_145_DPIR4__FUNC_CM2DAT_2X_8 (MTK_PIN_NO(145) | 4) - -#define MT8135_PIN_146_DPIR5__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) -#define MT8135_PIN_146_DPIR5__FUNC_DPI0_R5 (MTK_PIN_NO(146) | 1) -#define MT8135_PIN_146_DPIR5__FUNC_EINT123 (MTK_PIN_NO(146) | 2) -#define MT8135_PIN_146_DPIR5__FUNC_CM2DAT_2X_9 (MTK_PIN_NO(146) | 4) - -#define MT8135_PIN_147_DPIR6__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) -#define MT8135_PIN_147_DPIR6__FUNC_DPI0_R6 (MTK_PIN_NO(147) | 1) -#define MT8135_PIN_147_DPIR6__FUNC_EINT124 (MTK_PIN_NO(147) | 2) -#define MT8135_PIN_147_DPIR6__FUNC_CM2VSYNC_2X (MTK_PIN_NO(147) | 4) - -#define MT8135_PIN_148_DPIR7__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) -#define MT8135_PIN_148_DPIR7__FUNC_DPI0_R7 (MTK_PIN_NO(148) | 1) -#define MT8135_PIN_148_DPIR7__FUNC_EINT125 (MTK_PIN_NO(148) | 2) -#define MT8135_PIN_148_DPIR7__FUNC_CM2HSYNC_2X (MTK_PIN_NO(148) | 4) - -#define MT8135_PIN_149_TDN3__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) -#define MT8135_PIN_149_TDN3__FUNC_EINT36 (MTK_PIN_NO(149) | 2) - -#define MT8135_PIN_150_TDP3__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) -#define MT8135_PIN_150_TDP3__FUNC_EINT35 (MTK_PIN_NO(150) | 2) - -#define MT8135_PIN_151_TDN2__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) -#define MT8135_PIN_151_TDN2__FUNC_EINT169 (MTK_PIN_NO(151) | 2) - -#define MT8135_PIN_152_TDP2__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) -#define MT8135_PIN_152_TDP2__FUNC_EINT168 (MTK_PIN_NO(152) | 2) - -#define MT8135_PIN_153_TCN__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) -#define MT8135_PIN_153_TCN__FUNC_EINT163 (MTK_PIN_NO(153) | 2) - -#define MT8135_PIN_154_TCP__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) -#define MT8135_PIN_154_TCP__FUNC_EINT162 (MTK_PIN_NO(154) | 2) - -#define MT8135_PIN_155_TDN1__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) -#define MT8135_PIN_155_TDN1__FUNC_EINT167 (MTK_PIN_NO(155) | 2) - -#define MT8135_PIN_156_TDP1__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) -#define MT8135_PIN_156_TDP1__FUNC_EINT166 (MTK_PIN_NO(156) | 2) - -#define MT8135_PIN_157_TDN0__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) -#define MT8135_PIN_157_TDN0__FUNC_EINT165 (MTK_PIN_NO(157) | 2) - -#define MT8135_PIN_158_TDP0__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) -#define MT8135_PIN_158_TDP0__FUNC_EINT164 (MTK_PIN_NO(158) | 2) - -#define MT8135_PIN_159_RDN3__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) -#define MT8135_PIN_159_RDN3__FUNC_EINT18 (MTK_PIN_NO(159) | 2) - -#define MT8135_PIN_160_RDP3__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) -#define MT8135_PIN_160_RDP3__FUNC_EINT30 (MTK_PIN_NO(160) | 2) - -#define MT8135_PIN_161_RDN2__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) -#define MT8135_PIN_161_RDN2__FUNC_EINT31 (MTK_PIN_NO(161) | 2) - -#define MT8135_PIN_162_RDP2__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) -#define MT8135_PIN_162_RDP2__FUNC_EINT32 (MTK_PIN_NO(162) | 2) - -#define MT8135_PIN_163_RCN__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) -#define MT8135_PIN_163_RCN__FUNC_EINT33 (MTK_PIN_NO(163) | 2) - -#define MT8135_PIN_164_RCP__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) -#define MT8135_PIN_164_RCP__FUNC_EINT39 (MTK_PIN_NO(164) | 2) - -#define MT8135_PIN_165_RDN1__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) - -#define MT8135_PIN_166_RDP1__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) - -#define MT8135_PIN_167_RDN0__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) - -#define MT8135_PIN_168_RDP0__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) - -#define MT8135_PIN_169_RDN1_A__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) -#define MT8135_PIN_169_RDN1_A__FUNC_CMDAT6 (MTK_PIN_NO(169) | 1) -#define MT8135_PIN_169_RDN1_A__FUNC_EINT175 (MTK_PIN_NO(169) | 2) - -#define MT8135_PIN_170_RDP1_A__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) -#define MT8135_PIN_170_RDP1_A__FUNC_CMDAT7 (MTK_PIN_NO(170) | 1) -#define MT8135_PIN_170_RDP1_A__FUNC_EINT174 (MTK_PIN_NO(170) | 2) - -#define MT8135_PIN_171_RCN_A__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) -#define MT8135_PIN_171_RCN_A__FUNC_CMDAT8 (MTK_PIN_NO(171) | 1) -#define MT8135_PIN_171_RCN_A__FUNC_EINT171 (MTK_PIN_NO(171) | 2) - -#define MT8135_PIN_172_RCP_A__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) -#define MT8135_PIN_172_RCP_A__FUNC_CMDAT9 (MTK_PIN_NO(172) | 1) -#define MT8135_PIN_172_RCP_A__FUNC_EINT170 (MTK_PIN_NO(172) | 2) - -#define MT8135_PIN_173_RDN0_A__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) -#define MT8135_PIN_173_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(173) | 1) -#define MT8135_PIN_173_RDN0_A__FUNC_EINT173 (MTK_PIN_NO(173) | 2) - -#define MT8135_PIN_174_RDP0_A__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) -#define MT8135_PIN_174_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(174) | 1) -#define MT8135_PIN_174_RDP0_A__FUNC_EINT172 (MTK_PIN_NO(174) | 2) - -#define MT8135_PIN_175_RDN1_B__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) -#define MT8135_PIN_175_RDN1_B__FUNC_CMDAT2 (MTK_PIN_NO(175) | 1) -#define MT8135_PIN_175_RDN1_B__FUNC_EINT181 (MTK_PIN_NO(175) | 2) -#define MT8135_PIN_175_RDN1_B__FUNC_CMCSD2 (MTK_PIN_NO(175) | 3) - -#define MT8135_PIN_176_RDP1_B__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) -#define MT8135_PIN_176_RDP1_B__FUNC_CMDAT3 (MTK_PIN_NO(176) | 1) -#define MT8135_PIN_176_RDP1_B__FUNC_EINT180 (MTK_PIN_NO(176) | 2) -#define MT8135_PIN_176_RDP1_B__FUNC_CMCSD3 (MTK_PIN_NO(176) | 3) - -#define MT8135_PIN_177_RCN_B__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) -#define MT8135_PIN_177_RCN_B__FUNC_CMDAT4 (MTK_PIN_NO(177) | 1) -#define MT8135_PIN_177_RCN_B__FUNC_EINT177 (MTK_PIN_NO(177) | 2) - -#define MT8135_PIN_178_RCP_B__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) -#define MT8135_PIN_178_RCP_B__FUNC_CMDAT5 (MTK_PIN_NO(178) | 1) -#define MT8135_PIN_178_RCP_B__FUNC_EINT176 (MTK_PIN_NO(178) | 2) - -#define MT8135_PIN_179_RDN0_B__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) -#define MT8135_PIN_179_RDN0_B__FUNC_CMDAT0 (MTK_PIN_NO(179) | 1) -#define MT8135_PIN_179_RDN0_B__FUNC_EINT179 (MTK_PIN_NO(179) | 2) -#define MT8135_PIN_179_RDN0_B__FUNC_CMCSD0 (MTK_PIN_NO(179) | 3) - -#define MT8135_PIN_180_RDP0_B__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) -#define MT8135_PIN_180_RDP0_B__FUNC_CMDAT1 (MTK_PIN_NO(180) | 1) -#define MT8135_PIN_180_RDP0_B__FUNC_EINT178 (MTK_PIN_NO(180) | 2) -#define MT8135_PIN_180_RDP0_B__FUNC_CMCSD1 (MTK_PIN_NO(180) | 3) - -#define MT8135_PIN_181_CMPCLK__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) -#define MT8135_PIN_181_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(181) | 1) -#define MT8135_PIN_181_CMPCLK__FUNC_EINT182 (MTK_PIN_NO(181) | 2) -#define MT8135_PIN_181_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(181) | 3) -#define MT8135_PIN_181_CMPCLK__FUNC_CM2MCLK_4X (MTK_PIN_NO(181) | 4) -#define MT8135_PIN_181_CMPCLK__FUNC_TS_AUXADC_SEL_3 (MTK_PIN_NO(181) | 5) -#define MT8135_PIN_181_CMPCLK__FUNC_VENC_TEST_CK (MTK_PIN_NO(181) | 6) -#define MT8135_PIN_181_CMPCLK__FUNC_TESTA_OUT27 (MTK_PIN_NO(181) | 7) - -#define MT8135_PIN_182_CMMCLK__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) -#define MT8135_PIN_182_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(182) | 1) -#define MT8135_PIN_182_CMMCLK__FUNC_EINT183 (MTK_PIN_NO(182) | 2) -#define MT8135_PIN_182_CMMCLK__FUNC_TS_AUXADC_SEL_2 (MTK_PIN_NO(182) | 5) -#define MT8135_PIN_182_CMMCLK__FUNC_TESTA_OUT28 (MTK_PIN_NO(182) | 7) - -#define MT8135_PIN_183_CMRST__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) -#define MT8135_PIN_183_CMRST__FUNC_CMRST (MTK_PIN_NO(183) | 1) -#define MT8135_PIN_183_CMRST__FUNC_EINT185 (MTK_PIN_NO(183) | 2) -#define MT8135_PIN_183_CMRST__FUNC_TS_AUXADC_SEL_1 (MTK_PIN_NO(183) | 5) -#define MT8135_PIN_183_CMRST__FUNC_TESTA_OUT30 (MTK_PIN_NO(183) | 7) - -#define MT8135_PIN_184_CMPDN__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) -#define MT8135_PIN_184_CMPDN__FUNC_CMPDN (MTK_PIN_NO(184) | 1) -#define MT8135_PIN_184_CMPDN__FUNC_EINT184 (MTK_PIN_NO(184) | 2) -#define MT8135_PIN_184_CMPDN__FUNC_TS_AUXADC_SEL_0 (MTK_PIN_NO(184) | 5) -#define MT8135_PIN_184_CMPDN__FUNC_TESTA_OUT29 (MTK_PIN_NO(184) | 7) - -#define MT8135_PIN_185_CMFLASH__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) -#define MT8135_PIN_185_CMFLASH__FUNC_CMFLASH (MTK_PIN_NO(185) | 1) -#define MT8135_PIN_185_CMFLASH__FUNC_EINT186 (MTK_PIN_NO(185) | 2) -#define MT8135_PIN_185_CMFLASH__FUNC_CM2MCLK_3X (MTK_PIN_NO(185) | 3) -#define MT8135_PIN_185_CMFLASH__FUNC_MFG_TEST_CK_1 (MTK_PIN_NO(185) | 6) -#define MT8135_PIN_185_CMFLASH__FUNC_TESTA_OUT31 (MTK_PIN_NO(185) | 7) - -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_MRG_I2S_P_CLK (MTK_PIN_NO(186) | 1) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_EINT14 (MTK_PIN_NO(186) | 2) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(186) | 3) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_PCM0_CK (MTK_PIN_NO(186) | 4) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_DSP2_ICK (MTK_PIN_NO(186) | 5) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_IMG_TEST_CK (MTK_PIN_NO(186) | 6) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_USB_SCL (MTK_PIN_NO(186) | 7) - -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_MRG_I2S_SYNC (MTK_PIN_NO(187) | 1) -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_EINT16 (MTK_PIN_NO(187) | 2) -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_I2SIN_WS (MTK_PIN_NO(187) | 3) -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_PCM0_WS (MTK_PIN_NO(187) | 4) -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_DISP_TEST_CK (MTK_PIN_NO(187) | 6) - -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MRG_I2S_PCM_RX (MTK_PIN_NO(188) | 1) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_EINT15 (MTK_PIN_NO(188) | 2) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_I2SIN_DAT (MTK_PIN_NO(188) | 3) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_PCM0_DI (MTK_PIN_NO(188) | 4) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_DSP2_ID (MTK_PIN_NO(188) | 5) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MFG_TEST_CK (MTK_PIN_NO(188) | 6) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_USB_SDA (MTK_PIN_NO(188) | 7) - -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_MRG_I2S_PCM_TX (MTK_PIN_NO(189) | 1) -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_EINT17 (MTK_PIN_NO(189) | 2) -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_I2SOUT_DAT (MTK_PIN_NO(189) | 3) -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_PCM0_DO (MTK_PIN_NO(189) | 4) -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_VDEC_TEST_CK (MTK_PIN_NO(189) | 6) - -#define MT8135_PIN_190_SRCLKENAI__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) -#define MT8135_PIN_190_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(190) | 1) - -#define MT8135_PIN_191_URXD3__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) -#define MT8135_PIN_191_URXD3__FUNC_URXD3 (MTK_PIN_NO(191) | 1) -#define MT8135_PIN_191_URXD3__FUNC_EINT87 (MTK_PIN_NO(191) | 2) -#define MT8135_PIN_191_URXD3__FUNC_UTXD3 (MTK_PIN_NO(191) | 3) -#define MT8135_PIN_191_URXD3__FUNC_TS_AUX_ST (MTK_PIN_NO(191) | 5) -#define MT8135_PIN_191_URXD3__FUNC_PWM4 (MTK_PIN_NO(191) | 6) - -#define MT8135_PIN_192_UTXD3__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) -#define MT8135_PIN_192_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(192) | 1) -#define MT8135_PIN_192_UTXD3__FUNC_EINT86 (MTK_PIN_NO(192) | 2) -#define MT8135_PIN_192_UTXD3__FUNC_URXD3 (MTK_PIN_NO(192) | 3) -#define MT8135_PIN_192_UTXD3__FUNC_TS_AUX_CS_B (MTK_PIN_NO(192) | 5) -#define MT8135_PIN_192_UTXD3__FUNC_PWM3 (MTK_PIN_NO(192) | 6) - -#define MT8135_PIN_193_SDA2__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) -#define MT8135_PIN_193_SDA2__FUNC_SDA2 (MTK_PIN_NO(193) | 1) -#define MT8135_PIN_193_SDA2__FUNC_EINT95 (MTK_PIN_NO(193) | 2) -#define MT8135_PIN_193_SDA2__FUNC_CLKM5 (MTK_PIN_NO(193) | 3) -#define MT8135_PIN_193_SDA2__FUNC_PWM5 (MTK_PIN_NO(193) | 4) -#define MT8135_PIN_193_SDA2__FUNC_TS_AUX_PWDB (MTK_PIN_NO(193) | 5) - -#define MT8135_PIN_194_SCL2__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) -#define MT8135_PIN_194_SCL2__FUNC_SCL2 (MTK_PIN_NO(194) | 1) -#define MT8135_PIN_194_SCL2__FUNC_EINT94 (MTK_PIN_NO(194) | 2) -#define MT8135_PIN_194_SCL2__FUNC_CLKM4 (MTK_PIN_NO(194) | 3) -#define MT8135_PIN_194_SCL2__FUNC_PWM4 (MTK_PIN_NO(194) | 4) -#define MT8135_PIN_194_SCL2__FUNC_TS_AUXADC_TEST_CK (MTK_PIN_NO(194) | 5) - -#define MT8135_PIN_195_SDA1__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) -#define MT8135_PIN_195_SDA1__FUNC_SDA1 (MTK_PIN_NO(195) | 1) -#define MT8135_PIN_195_SDA1__FUNC_EINT93 (MTK_PIN_NO(195) | 2) -#define MT8135_PIN_195_SDA1__FUNC_CLKM3 (MTK_PIN_NO(195) | 3) -#define MT8135_PIN_195_SDA1__FUNC_PWM3 (MTK_PIN_NO(195) | 4) -#define MT8135_PIN_195_SDA1__FUNC_TS_AUX_SCLK_PWDB (MTK_PIN_NO(195) | 5) - -#define MT8135_PIN_196_SCL1__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) -#define MT8135_PIN_196_SCL1__FUNC_SCL1 (MTK_PIN_NO(196) | 1) -#define MT8135_PIN_196_SCL1__FUNC_EINT92 (MTK_PIN_NO(196) | 2) -#define MT8135_PIN_196_SCL1__FUNC_CLKM2 (MTK_PIN_NO(196) | 3) -#define MT8135_PIN_196_SCL1__FUNC_PWM2 (MTK_PIN_NO(196) | 4) -#define MT8135_PIN_196_SCL1__FUNC_TS_AUX_DIN (MTK_PIN_NO(196) | 5) - -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(197) | 1) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_EINT71 (MTK_PIN_NO(197) | 2) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_SCL6 (MTK_PIN_NO(197) | 3) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_PWM5 (MTK_PIN_NO(197) | 4) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_CLKM4 (MTK_PIN_NO(197) | 5) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MFG_TEST_CK_2 (MTK_PIN_NO(197) | 6) - -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(198) | 1) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_EINT72 (MTK_PIN_NO(198) | 2) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_SDA6 (MTK_PIN_NO(198) | 3) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_PWM6 (MTK_PIN_NO(198) | 4) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_CLKM5 (MTK_PIN_NO(198) | 5) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MFG_TEST_CK_3 (MTK_PIN_NO(198) | 6) - -#define MT8135_PIN_199_MSDC3_CMD__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(199) | 1) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_EINT68 (MTK_PIN_NO(199) | 2) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_SDA2 (MTK_PIN_NO(199) | 3) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_PWM2 (MTK_PIN_NO(199) | 4) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_CLKM1 (MTK_PIN_NO(199) | 5) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_MFG_TEST_CK_4 (MTK_PIN_NO(199) | 6) - -#define MT8135_PIN_200_MSDC3_CLK__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) -#define MT8135_PIN_200_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(200) | 1) -#define MT8135_PIN_200_MSDC3_CLK__FUNC_EINT67 (MTK_PIN_NO(200) | 2) -#define MT8135_PIN_200_MSDC3_CLK__FUNC_SCL2 (MTK_PIN_NO(200) | 3) -#define MT8135_PIN_200_MSDC3_CLK__FUNC_PWM1 (MTK_PIN_NO(200) | 4) -#define MT8135_PIN_200_MSDC3_CLK__FUNC_CLKM0 (MTK_PIN_NO(200) | 5) - -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(201) | 1) -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_EINT70 (MTK_PIN_NO(201) | 2) -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_SDA3 (MTK_PIN_NO(201) | 3) -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_PWM4 (MTK_PIN_NO(201) | 4) -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_CLKM3 (MTK_PIN_NO(201) | 5) - -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(202) | 1) -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_EINT69 (MTK_PIN_NO(202) | 2) -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_SCL3 (MTK_PIN_NO(202) | 3) -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_PWM3 (MTK_PIN_NO(202) | 4) -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_CLKM2 (MTK_PIN_NO(202) | 5) - -#endif /* __DTS_MT8135_PINFUNC_H */ diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi index a069afd..a161e99 100644 --- a/arch/arm/boot/dts/mt8135.dtsi +++ b/arch/arm/boot/dts/mt8135.dtsi @@ -15,7 +15,6 @@ #include #include #include "skeleton64.dtsi" -#include "mt8135-pinfunc.h" / { compatible = "mediatek,mt8135"; @@ -102,30 +101,6 @@ compatible = "simple-bus"; ranges; - syscfg_pctl_a: syscfg_pctl_a@10005000 { - compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - syscfg_pctl_b: syscfg_pctl_b@1020C000 { - compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; - reg = <0 0x1020C000 0 0x1000>; - }; - - pio: pinctrl@10005000 { - compatible = "mediatek,mt8135-pinctrl"; - reg = <0 0x1000B000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; - pins-are-numbered; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - ; - }; - timer: timer@10008000 { compatible = "mediatek,mt8135-timer", "mediatek,mt6577-timer"; -- cgit v0.10.2 From 8b036556d68175caa9bea3fb98768f733fde33c6 Mon Sep 17 00:00:00 2001 From: Tsahee Zidenberg Date: Sun, 5 Apr 2015 15:43:53 +0300 Subject: ARM: dts: alpine: add internal pci This patch adds device-tree entry for the internal pci bus on Alpine. Alpine's on-chip devices appear as pci devices on this bus. Signed-off-by: Tsahee Zidenberg Signed-off-by: Arnd Bergmann diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi index 519f58c..9af2d60 100644 --- a/arch/arm/boot/dts/alpine.dtsi +++ b/arch/arm/boot/dts/alpine.dtsi @@ -137,5 +137,24 @@ reg-shift = <2>; reg-io-width = <4>; }; + + /* Internal PCIe Controller */ + pcie-internal@0xfbc00000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + #interrupt-cells = <1>; + reg = <0x0 0xfbc00000 0x0 0x100000>; + interrupt-map-mask = <0xf800 0 0 7>; + /* Add legacy interrupts for SATA devices only */ + interrupt-map = <0x4000 0 0 1 &gic 0 43 4>, + <0x4800 0 0 1 &gic 0 44 4>; + + /* 32 bit non prefetchable memory space */ + ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; + + bus-range = <0x00 0x00>; + }; }; }; -- cgit v0.10.2