From 22ca335f6db9cf614696bbcb83eb0b80db7b4110 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Thu, 7 Feb 2013 13:07:11 +0800 Subject: clk: tegra: fix wrong clock index between se to sata_cold The index of se should be 127. And the previous clock index was 125. So we need to set up the index for se to get the correct index between se to sata_cold. Signed-off-by: Joseph Lo Signed-off-by: Stephen Warren diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index a163812..1d41b35 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -332,9 +332,9 @@ enum tegra30_clk { cdev1, cdev2, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4, i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x, atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x, - spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda, se, - hda2hdmi, sata_cold, uartb = 160, vfir, spdif_out, spdif_in, vi, - vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2, + spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda, + se = 127, hda2hdmi, sata_cold, uartb = 160, vfir, spdif_out, spdif_in, + vi, vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2, clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0, pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e, -- cgit v0.10.2 From c64c65d494ade53fa41fb0b980381807743b5095 Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Thu, 7 Feb 2013 18:24:14 +0200 Subject: clk: tegra: Implement locking for super clock Although tegra_clk_register_super_mux() has a lock parameter, the lock is not actually used by the code. Fixed with this patch. Signed-off-by: Peter De Schrijver Acked-by: Mike Turquette Reviewed-by: Prashant Gaikwad Signed-off-by: Stephen Warren diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c index 7ad48a8..2fd924d 100644 --- a/drivers/clk/tegra/clk-super.c +++ b/drivers/clk/tegra/clk-super.c @@ -73,7 +73,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index) { struct tegra_clk_super_mux *mux = to_clk_super_mux(hw); u32 val, state; + int err = 0; u8 parent_index, shift; + unsigned long flags = 0; + + if (mux->lock) + spin_lock_irqsave(mux->lock, flags); val = readl_relaxed(mux->reg); state = val & SUPER_STATE_MASK; @@ -92,8 +97,10 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index) (index == mux->pllx_index))) { parent_index = clk_super_get_parent(hw); if ((parent_index == mux->div2_index) || - (parent_index == mux->pllx_index)) - return -EINVAL; + (parent_index == mux->pllx_index)) { + err = -EINVAL; + goto out; + } val ^= SUPER_LP_DIV2_BYPASS; writel_relaxed(val, mux->reg); @@ -107,7 +114,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index) writel_relaxed(val, mux->reg); udelay(2); - return 0; + +out: + if (mux->lock) + spin_unlock_irqrestore(mux->lock, flags); + + return err; } const struct clk_ops tegra_clk_super_ops = { -- cgit v0.10.2 From d076a206b2dfa8ef7a735289fe1221e77d1fa83f Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Thu, 7 Feb 2013 18:37:35 +0200 Subject: clk: tegra: Add missing spinlock for hclk and pclk The hclk and pclk clocks are controlled by the same register. Hence a lock is required to avoid corruption. Signed-off-by: Peter De Schrijver Acked-by: Mike Turquette Reviewed-by: Prashant Gaikwad Signed-off-by: Stephen Warren diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 5d41569..4612b2e 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -194,6 +194,7 @@ static void __iomem *clk_base; static void __iomem *pmc_base; static DEFINE_SPINLOCK(pll_div_lock); +static DEFINE_SPINLOCK(sysrate_lock); #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ _clk_num, _regs, _gate_flags, _clk_id) \ @@ -768,19 +769,21 @@ static void tegra20_super_clk_init(void) /* HCLK */ clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, - clk_base + CLK_SYSTEM_RATE, 4, 2, 0, NULL); + clk_base + CLK_SYSTEM_RATE, 4, 2, 0, + &sysrate_lock); clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT, clk_base + CLK_SYSTEM_RATE, 7, - CLK_GATE_SET_TO_DISABLE, NULL); + CLK_GATE_SET_TO_DISABLE, &sysrate_lock); clk_register_clkdev(clk, "hclk", NULL); clks[hclk] = clk; /* PCLK */ clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, - clk_base + CLK_SYSTEM_RATE, 0, 2, 0, NULL); + clk_base + CLK_SYSTEM_RATE, 0, 2, 0, + &sysrate_lock); clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT, clk_base + CLK_SYSTEM_RATE, 3, - CLK_GATE_SET_TO_DISABLE, NULL); + CLK_GATE_SET_TO_DISABLE, &sysrate_lock); clk_register_clkdev(clk, "pclk", NULL); clks[pclk] = clk; diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 1d41b35..8a4fec4 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -275,6 +275,7 @@ static DEFINE_SPINLOCK(clk_out_lock); static DEFINE_SPINLOCK(pll_div_lock); static DEFINE_SPINLOCK(cml_lock); static DEFINE_SPINLOCK(pll_d_lock); +static DEFINE_SPINLOCK(sysrate_lock); #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ _clk_num, _regs, _gate_flags, _clk_id) \ @@ -1348,19 +1349,21 @@ static void __init tegra30_super_clk_init(void) /* HCLK */ clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, - clk_base + SYSTEM_CLK_RATE, 4, 2, 0, NULL); + clk_base + SYSTEM_CLK_RATE, 4, 2, 0, + &sysrate_lock); clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT, clk_base + SYSTEM_CLK_RATE, 7, - CLK_GATE_SET_TO_DISABLE, NULL); + CLK_GATE_SET_TO_DISABLE, &sysrate_lock); clk_register_clkdev(clk, "hclk", NULL); clks[hclk] = clk; /* PCLK */ clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, - clk_base + SYSTEM_CLK_RATE, 0, 2, 0, NULL); + clk_base + SYSTEM_CLK_RATE, 0, 2, 0, + &sysrate_lock); clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT, clk_base + SYSTEM_CLK_RATE, 3, - CLK_GATE_SET_TO_DISABLE, NULL); + CLK_GATE_SET_TO_DISABLE, &sysrate_lock); clk_register_clkdev(clk, "pclk", NULL); clks[pclk] = clk; -- cgit v0.10.2 From b4c154a339b7efe48f2801d7fb10199c57dddafd Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Thu, 7 Feb 2013 18:30:36 +0200 Subject: clk: tegra: local arrays should be static cclk_g_parents, cclk_lp_parents and sclk_parents are only accessed from within clk-tegra30.c. Declare them static to avoid namespace polution. Signed-off-by: Peter De Schrijver Acked-by: Mike Turquette Reviewed-by: Prashant Gaikwad Signed-off-by: Stephen Warren diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 8a4fec4..bf050bc 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1250,16 +1250,16 @@ static void __init tegra30_pmc_clk_init(void) } -const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", - "pll_p_cclkg", "pll_p_out4_cclkg", - "pll_p_out3_cclkg", "unused", "pll_x" }; -const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", - "pll_p_cclklp", "pll_p_out4_cclklp", - "pll_p_out3_cclklp", "unused", "pll_x", - "pll_x_out0" }; -const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", - "pll_p_out3", "pll_p_out2", "unused", - "clk_32k", "pll_m_out1" }; +static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", + "pll_p_cclkg", "pll_p_out4_cclkg", + "pll_p_out3_cclkg", "unused", "pll_x" }; +static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", + "pll_p_cclklp", "pll_p_out4_cclklp", + "pll_p_out3_cclklp", "unused", "pll_x", + "pll_x_out0" }; +static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", + "pll_p_out3", "pll_p_out2", "unused", + "clk_32k", "pll_m_out1" }; static void __init tegra30_super_clk_init(void) { -- cgit v0.10.2 From 0203d91247090e57063e1ef63a6019e87548dfbc Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 12 Feb 2013 12:17:37 -0700 Subject: clk: tegra: fix driver to match DT binding enum tegra*_clk is intended to match the IDs listed in the Tegra clock bindings. There are a few mismatches, which this patch fixes: 1) pll_s and cop were left out of the Tegra20 enum. 2) spdif_in and spdif_out were swapped relative to the Tegra30 binding. 3) i2cslow was misnamed as i2c_slow, and a duplicate i2cslow clock added to the Tegra30 enum. Signed-off-by: Stephen Warren Reviewed-by: Thierry Reding Tested-by: Thierry Reding diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 4612b2e..3d70634 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -240,8 +240,8 @@ enum tegra20_clk { uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve, osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0, pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1, - pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_u, - pll_x, audio, pll_ref, twd, clk_max, + pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_s, pll_u, + pll_x, cop, audio, pll_ref, twd, clk_max, }; static struct clk *clks[clk_max]; diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index bf050bc..bfe3dd4 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -328,13 +328,13 @@ enum tegra30_clk { kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46, i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2, usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3, - pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2c_slow, + pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow, dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92, cdev1, cdev2, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4, i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x, atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x, spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda, - se = 127, hda2hdmi, sata_cold, uartb = 160, vfir, spdif_out, spdif_in, + se = 127, hda2hdmi, sata_cold, uartb = 160, vfir, spdif_in, spdif_out, vi, vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2, clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0, @@ -342,7 +342,7 @@ enum tegra30_clk { spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1, - i2cslow, hclk, pclk, clk_out_1_mux = 300, clk_max + hclk, pclk, clk_out_1_mux = 300, clk_max }; static struct clk *clks[clk_max]; -- cgit v0.10.2 From 8364f5d96509e206f02a74bbdc2d4e3742cdefe4 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 12 Feb 2013 10:26:45 -0700 Subject: ARM: tegra: remove clock-frequency properties from serial nodes Currently, the serial nodes define both a clock-frequency and a clocks property. We should not provide both, since they might conflict. In practice, this also causes problems since the of_serial driver uses the clock-frequency property in preference to the clocks property, and hence doesn't clk_prepare_enable() the clock, which may then leave it with no known users, and hence the common clock framework will disable it, thus breaking the port, which is usually the console. Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index cdb8da0..9a42893 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -247,7 +247,6 @@ reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = <0 36 0x04>; - clock-frequency = <216000000>; nvidia,dma-request-selector = <&apbdma 8>; clocks = <&tegra_car 6>; status = "disabled"; @@ -258,7 +257,6 @@ reg = <0x70006040 0x40>; reg-shift = <2>; interrupts = <0 37 0x04>; - clock-frequency = <216000000>; nvidia,dma-request-selector = <&apbdma 9>; clocks = <&tegra_car 96>; status = "disabled"; @@ -269,7 +267,6 @@ reg = <0x70006200 0x100>; reg-shift = <2>; interrupts = <0 46 0x04>; - clock-frequency = <216000000>; nvidia,dma-request-selector = <&apbdma 10>; clocks = <&tegra_car 55>; status = "disabled"; @@ -280,7 +277,6 @@ reg = <0x70006300 0x100>; reg-shift = <2>; interrupts = <0 90 0x04>; - clock-frequency = <216000000>; nvidia,dma-request-selector = <&apbdma 19>; clocks = <&tegra_car 65>; status = "disabled"; @@ -291,7 +287,6 @@ reg = <0x70006400 0x100>; reg-shift = <2>; interrupts = <0 91 0x04>; - clock-frequency = <216000000>; nvidia,dma-request-selector = <&apbdma 20>; clocks = <&tegra_car 66>; status = "disabled"; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 572a45b..767803e 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -234,7 +234,6 @@ reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = <0 36 0x04>; - clock-frequency = <408000000>; nvidia,dma-request-selector = <&apbdma 8>; clocks = <&tegra_car 6>; status = "disabled"; @@ -244,7 +243,6 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006040 0x40>; reg-shift = <2>; - clock-frequency = <408000000>; interrupts = <0 37 0x04>; nvidia,dma-request-selector = <&apbdma 9>; clocks = <&tegra_car 160>; @@ -255,7 +253,6 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006200 0x100>; reg-shift = <2>; - clock-frequency = <408000000>; interrupts = <0 46 0x04>; nvidia,dma-request-selector = <&apbdma 10>; clocks = <&tegra_car 55>; @@ -266,7 +263,6 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006300 0x100>; reg-shift = <2>; - clock-frequency = <408000000>; interrupts = <0 90 0x04>; nvidia,dma-request-selector = <&apbdma 19>; clocks = <&tegra_car 65>; @@ -277,7 +273,6 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006400 0x100>; reg-shift = <2>; - clock-frequency = <408000000>; interrupts = <0 91 0x04>; nvidia,dma-request-selector = <&apbdma 20>; clocks = <&tegra_car 66>; -- cgit v0.10.2 From 527fad1bc519df8eedd397482febb51526e5d987 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 12 Feb 2013 20:47:59 +0530 Subject: clk: tegra: initialise parent of uart clocks Initialise the parent of UARTs to PLLP and disabling clock by default. Signed-off-by: Laxman Dewangan Acked-by: Mike Turquette Signed-off-by: Stephen Warren diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 3d70634..143ce1f 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1254,8 +1254,11 @@ static __initdata struct tegra_clk_init_table init_table[] = { {csite, clk_max, 0, 1}, {emc, clk_max, 0, 1}, {cclk, clk_max, 0, 1}, - {uarta, pll_p, 0, 1}, - {uartd, pll_p, 0, 1}, + {uarta, pll_p, 0, 0}, + {uartb, pll_p, 0, 0}, + {uartc, pll_p, 0, 0}, + {uartd, pll_p, 0, 0}, + {uarte, pll_p, 0, 0}, {usbd, clk_max, 12000000, 0}, {usb2, clk_max, 12000000, 0}, {usb3, clk_max, 12000000, 0}, diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index bfe3dd4..32c61cb 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1877,7 +1877,11 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = { }; static __initdata struct tegra_clk_init_table init_table[] = { - {uarta, pll_p, 408000000, 1}, + {uarta, pll_p, 408000000, 0}, + {uartb, pll_p, 408000000, 0}, + {uartc, pll_p, 408000000, 0}, + {uartd, pll_p, 408000000, 0}, + {uarte, pll_p, 408000000, 0}, {pll_a, clk_max, 564480000, 1}, {pll_a_out0, clk_max, 11289600, 1}, {extern1, pll_a_out0, 0, 1}, -- cgit v0.10.2