From 1d50d2ce6337724d30055bdbe082236cc86e6785 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 26 Jun 2014 12:40:19 +0530 Subject: irqchip: crossbar: Dont use '0' to mark reserved interrupts Today '0' is actually reserved, but may not be the same in the future. So, use a flag to mark the GIC interrupts that are reserved. Signed-off-by: Nishanth Menon Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Link: https://lkml.kernel.org/r/1403766634-18543-2-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c index 3d15d16..20105bc 100644 --- a/drivers/irqchip/irq-crossbar.c +++ b/drivers/irqchip/irq-crossbar.c @@ -17,6 +17,7 @@ #include #define IRQ_FREE -1 +#define IRQ_RESERVED -2 #define GIC_IRQ_START 32 /* @@ -139,7 +140,7 @@ static int __init crossbar_of_init(struct device_node *node) pr_err("Invalid reserved entry\n"); goto err3; } - cb->irq_map[entry] = 0; + cb->irq_map[entry] = IRQ_RESERVED; } } @@ -170,7 +171,7 @@ static int __init crossbar_of_init(struct device_node *node) * reserved irqs. so find and store the offsets once. */ for (i = 0; i < max; i++) { - if (!cb->irq_map[i]) + if (cb->irq_map[i] == IRQ_RESERVED) continue; cb->register_offsets[i] = reserved; -- cgit v0.10.2 From 6f16fc878a51572a998655e5ef1c396cb269648d Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 26 Jun 2014 12:40:20 +0530 Subject: irqchip: crossbar: Check for premapped crossbar before allocating If irq_of_parse_and_map is executed twice, the same crossbar is mapped to two different GIC interrupts. This is completely undesirable. Instead, check if the requested crossbar event is pre-allocated and provide that GIC mapping back to caller if already allocated. Signed-off-by: Nishanth Menon Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Link: https://lkml.kernel.org/r/1403766634-18543-3-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c index 20105bc..51d4b87 100644 --- a/drivers/irqchip/irq-crossbar.c +++ b/drivers/irqchip/irq-crossbar.c @@ -51,6 +51,17 @@ static inline void crossbar_writeb(int irq_no, int cb_no) writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); } +static inline int get_prev_map_irq(int cb_no) +{ + int i; + + for (i = 0; i < cb->int_max; i++) + if (cb->irq_map[i] == cb_no) + return i; + + return -ENODEV; +} + static inline int allocate_free_irq(int cb_no) { int i; @@ -88,11 +99,16 @@ static int crossbar_domain_xlate(struct irq_domain *d, { unsigned long ret; + ret = get_prev_map_irq(intspec[1]); + if (!IS_ERR_VALUE(ret)) + goto found; + ret = allocate_free_irq(intspec[1]); if (IS_ERR_VALUE(ret)) return ret; +found: *out_hwirq = ret + GIC_IRQ_START; return 0; } -- cgit v0.10.2 From 64e0f8ba5cae74471f72e0cb218c67915e365f47 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 26 Jun 2014 12:40:21 +0530 Subject: irqchip: crossbar: Introduce ti, irqs-skip to skip irqs that bypass crossbar When, in the system due to varied reasons, interrupts might be unusable due to hardware behavior, but register maps do exist, then those interrupts should be skipped while mapping irq to crossbars. Signed-off-by: Nishanth Menon Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Link: https://lkml.kernel.org/r/1403766634-18543-4-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt index fb88585..0795765 100644 --- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt +++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt @@ -17,6 +17,11 @@ Required properties: so crossbar bar driver should not consider them as free lines. +Optional properties: +- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for + SOC-specific hard-wiring of those irqs which unexpectedly bypasses the + crossbar. These irqs have a crossbar register, but still cannot be used. + Examples: crossbar_mpu: @4a020000 { compatible = "ti,irq-crossbar"; @@ -24,4 +29,5 @@ Examples: ti,max-irqs = <160>; ti,reg-size = <2>; ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>; + ti,irqs-skip = <10 133 139 140>; }; diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c index 51d4b87..0533a71 100644 --- a/drivers/irqchip/irq-crossbar.c +++ b/drivers/irqchip/irq-crossbar.c @@ -18,6 +18,7 @@ #define IRQ_FREE -1 #define IRQ_RESERVED -2 +#define IRQ_SKIP -3 #define GIC_IRQ_START 32 /* @@ -160,6 +161,25 @@ static int __init crossbar_of_init(struct device_node *node) } } + /* Skip irqs hardwired to bypass the crossbar */ + irqsr = of_get_property(node, "ti,irqs-skip", &size); + if (irqsr) { + size /= sizeof(__be32); + + for (i = 0; i < size; i++) { + of_property_read_u32_index(node, + "ti,irqs-skip", + i, &entry); + if (entry > max) { + pr_err("Invalid skip entry\n"); + ret = -EINVAL; + goto err3; + } + cb->irq_map[entry] = IRQ_SKIP; + } + } + + cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL); if (!cb->register_offsets) goto err3; -- cgit v0.10.2 From a35057d1dcb11ae67c9347ef7987cf65ac743c36 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 26 Jun 2014 12:40:22 +0530 Subject: irqchip: crossbar: Initialise the crossbar with a safe value Since crossbar is s/w configurable, the initial settings of the crossbar cannot be assumed to be sane. This implies that: a) On initialization all un-reserved crossbars must be initialized to a known 'safe' value. b) When unmapping the interrupt, the safe value must be written to ensure that the crossbar mapping matches with interrupt controller usage. So provide a safe value in the dt data to map if '0' is not safe for the platform and use it during init and unmap While at this, fix the below checkpatch warning. Fixes checkpatch warning: WARNING: Unnecessary space before function pointer arguments #37: FILE: drivers/irqchip/irq-crossbar.c:37: + void (*write) (int, int); Signed-off-by: Nishanth Menon Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Link: https://lkml.kernel.org/r/1403766634-18543-5-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt index 0795765..5f45c78 100644 --- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt +++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt @@ -22,6 +22,9 @@ Optional properties: SOC-specific hard-wiring of those irqs which unexpectedly bypasses the crossbar. These irqs have a crossbar register, but still cannot be used. +- ti,irqs-safe-map: integer which maps to a safe configuration to use + when the interrupt controller irq is unused (when not provided, default is 0) + Examples: crossbar_mpu: @4a020000 { compatible = "ti,irq-crossbar"; diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c index 0533a71..4be30c0 100644 --- a/drivers/irqchip/irq-crossbar.c +++ b/drivers/irqchip/irq-crossbar.c @@ -23,16 +23,18 @@ /* * @int_max: maximum number of supported interrupts + * @safe_map: safe default value to initialize the crossbar * @irq_map: array of interrupts to crossbar number mapping * @crossbar_base: crossbar base address * @register_offsets: offsets for each irq number */ struct crossbar_device { uint int_max; + uint safe_map; uint *irq_map; void __iomem *crossbar_base; int *register_offsets; - void (*write) (int, int); + void (*write)(int, int); }; static struct crossbar_device *cb; @@ -88,8 +90,10 @@ static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq) { irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq; - if (hw > GIC_IRQ_START) + if (hw > GIC_IRQ_START) { cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE; + cb->write(hw - GIC_IRQ_START, cb->safe_map); + } } static int crossbar_domain_xlate(struct irq_domain *d, @@ -214,6 +218,17 @@ static int __init crossbar_of_init(struct device_node *node) reserved += size; } + of_property_read_u32(node, "ti,irqs-safe-map", &cb->safe_map); + + /* Initialize the crossbar with safe map to start with */ + for (i = 0; i < max; i++) { + if (cb->irq_map[i] == IRQ_RESERVED || + cb->irq_map[i] == IRQ_SKIP) + continue; + + cb->write(i, cb->safe_map); + } + register_routable_domain_ops(&routable_irq_domain_ops); return 0; -- cgit v0.10.2 From ddee0fb46d26174e71ee1df225b9f9feaff05e10 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 26 Jun 2014 12:40:23 +0530 Subject: irqchip: crossbar: Change allocation logic by reversing search for free irqs Reverse the search algorithm to ensure that address mapping and IRQ allocation logics are proper. This makes the below bugs visible sooner. class 1. address space errors -> example: reg = ti,max-irqs = is a wrong parameter class 2: irq-reserved list - which decides which entries in the address space is not actually wired in class 3: wrong list of routable-irqs. In general allocating from max to min tends to have benefits in ensuring the different issues that may be present in dts is easily caught at definition time, rather than at a later point in time. Signed-off-by: Nishanth Menon Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Link: https://lkml.kernel.org/r/1403766634-18543-6-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c index 4be30c0..a39cb31 100644 --- a/drivers/irqchip/irq-crossbar.c +++ b/drivers/irqchip/irq-crossbar.c @@ -58,7 +58,7 @@ static inline int get_prev_map_irq(int cb_no) { int i; - for (i = 0; i < cb->int_max; i++) + for (i = cb->int_max - 1; i >= 0; i--) if (cb->irq_map[i] == cb_no) return i; @@ -69,7 +69,7 @@ static inline int allocate_free_irq(int cb_no) { int i; - for (i = 0; i < cb->int_max; i++) { + for (i = cb->int_max - 1; i >= 0; i--) { if (cb->irq_map[i] == IRQ_FREE) { cb->irq_map[i] = cb_no; return i; -- cgit v0.10.2 From d4922a95a70f0c8c5e45e22af629a5b5f370b867 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 26 Jun 2014 12:40:24 +0530 Subject: irqchip: crossbar: Remove IS_ERR_VALUE check IS_ERR_VALUE makes sense only *if* there could be valid values in negative error range. But in the cases that we do use it, there is no such case. Just remove the same. Signed-off-by: Nishanth Menon Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Link: https://lkml.kernel.org/r/1403766634-18543-7-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c index a39cb31..88fbe0f 100644 --- a/drivers/irqchip/irq-crossbar.c +++ b/drivers/irqchip/irq-crossbar.c @@ -102,15 +102,15 @@ static int crossbar_domain_xlate(struct irq_domain *d, unsigned long *out_hwirq, unsigned int *out_type) { - unsigned long ret; + int ret; ret = get_prev_map_irq(intspec[1]); - if (!IS_ERR_VALUE(ret)) + if (ret >= 0) goto found; ret = allocate_free_irq(intspec[1]); - if (IS_ERR_VALUE(ret)) + if (ret < 0) return ret; found: -- cgit v0.10.2 From 4dbf45e3c2f3acfd2096cb6a731d159492ddca99 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 26 Jun 2014 12:40:25 +0530 Subject: irqchip: crossbar: Fix sparse and checkpatch warnings There is absolutely no need for crossbar driver to expose functions and variables into global namespace. So make them all static Also fix a couple of checkpatch warnings. Fixes sparse warnings: drivers/irqchip/irq-crossbar.c:129:29: warning: symbol 'routable_irq_domain_ops' was not declared. Should it be static? drivers/irqchip/irq-crossbar.c:261:12: warning: symbol 'irqcrossbar_init' was not declared. Should it be static? Checkpatch warnings: WARNING: Prefer kcalloc over kzalloc with multiply + cb->irq_map = kzalloc(max * sizeof(int), GFP_KERNEL); WARNING: Prefer kcalloc over kzalloc with multiply + cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL); Signed-off-by: Nishanth Menon Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Link: https://lkml.kernel.org/r/1403766634-18543-8-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c index 88fbe0f..f7eda9f 100644 --- a/drivers/irqchip/irq-crossbar.c +++ b/drivers/irqchip/irq-crossbar.c @@ -15,6 +15,7 @@ #include #include #include +#include #define IRQ_FREE -1 #define IRQ_RESERVED -2 @@ -118,7 +119,7 @@ found: return 0; } -const struct irq_domain_ops routable_irq_domain_ops = { +static const struct irq_domain_ops routable_irq_domain_ops = { .map = crossbar_domain_map, .unmap = crossbar_domain_unmap, .xlate = crossbar_domain_xlate @@ -139,7 +140,7 @@ static int __init crossbar_of_init(struct device_node *node) goto err1; of_property_read_u32(node, "ti,max-irqs", &max); - cb->irq_map = kzalloc(max * sizeof(int), GFP_KERNEL); + cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL); if (!cb->irq_map) goto err2; @@ -184,7 +185,7 @@ static int __init crossbar_of_init(struct device_node *node) } - cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL); + cb->register_offsets = kcalloc(max, sizeof(int), GFP_KERNEL); if (!cb->register_offsets) goto err3; -- cgit v0.10.2 From e30ef8abb383903f2b7e1bced971b98fd30cafc3 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 26 Jun 2014 12:40:26 +0530 Subject: irqchip: crossbar: Fix kerneldoc warning Adding missing properties for kerneldoc (@write) and cleanup of harmless warnings while we are here. kerneldoc warnings: Warning(drivers/irqchip/irq-crossbar.c:27): missing initial short description on line: * struct crossbar_device: crossbar device description Info(drivers/irqchip/irq-crossbar.c:27): Scanning doc for struct Warning(drivers/irqchip/irq-crossbar.c:39): No description found for parameter 'write' 2 warnings Signed-off-by: Nishanth Menon Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Link: https://lkml.kernel.org/r/1403766634-18543-9-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c index f7eda9f..cee556bf 100644 --- a/drivers/irqchip/irq-crossbar.c +++ b/drivers/irqchip/irq-crossbar.c @@ -22,12 +22,14 @@ #define IRQ_SKIP -3 #define GIC_IRQ_START 32 -/* +/** + * struct crossbar_device - crossbar device description * @int_max: maximum number of supported interrupts * @safe_map: safe default value to initialize the crossbar * @irq_map: array of interrupts to crossbar number mapping * @crossbar_base: crossbar base address * @register_offsets: offsets for each irq number + * @write: register write function pointer */ struct crossbar_device { uint int_max; -- cgit v0.10.2 From edb442def98c3c64acc316b6b1a64791c138ab07 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 26 Jun 2014 12:40:27 +0530 Subject: irqchip: crossbar: Return proper error value crossbar_of_init always returns -ENOMEM in case of errors. There can be other causes of failure like invalid data from DT. So return a appropriate error value for that case. Signed-off-by: Nishanth Menon Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Link: https://lkml.kernel.org/r/1403766634-18543-10-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c index cee556bf..10d723d 100644 --- a/drivers/irqchip/irq-crossbar.c +++ b/drivers/irqchip/irq-crossbar.c @@ -129,19 +129,25 @@ static const struct irq_domain_ops routable_irq_domain_ops = { static int __init crossbar_of_init(struct device_node *node) { - int i, size, max, reserved = 0, entry; + int i, size, max = 0, reserved = 0, entry; const __be32 *irqsr; + int ret = -ENOMEM; cb = kzalloc(sizeof(*cb), GFP_KERNEL); if (!cb) - return -ENOMEM; + return ret; cb->crossbar_base = of_iomap(node, 0); if (!cb->crossbar_base) goto err1; of_property_read_u32(node, "ti,max-irqs", &max); + if (!max) { + pr_err("missing 'ti,max-irqs' property\n"); + ret = -EINVAL; + goto err2; + } cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL); if (!cb->irq_map) goto err2; @@ -162,6 +168,7 @@ static int __init crossbar_of_init(struct device_node *node) i, &entry); if (entry > max) { pr_err("Invalid reserved entry\n"); + ret = -EINVAL; goto err3; } cb->irq_map[entry] = IRQ_RESERVED; @@ -205,6 +212,7 @@ static int __init crossbar_of_init(struct device_node *node) break; default: pr_err("Invalid reg-size property\n"); + ret = -EINVAL; goto err4; break; } @@ -243,7 +251,7 @@ err2: iounmap(cb->crossbar_base); err1: kfree(cb); - return -ENOMEM; + return ret; } static const struct of_device_id crossbar_match[] __initconst = { -- cgit v0.10.2 From 3c44d5151246947442f2fe8eede842e3f76dd2f1 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 26 Jun 2014 12:40:28 +0530 Subject: irqchip: crossbar: Change the goto naming Using err1,2,3,4 etc makes it hard to ensure a new exit path in the middle will not result in spurious changes, so rename the error paths as per the function it does. Signed-off-by: Nishanth Menon Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Link: https://lkml.kernel.org/r/1403766634-18543-11-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c index 10d723d..afc35fd 100644 --- a/drivers/irqchip/irq-crossbar.c +++ b/drivers/irqchip/irq-crossbar.c @@ -140,17 +140,17 @@ static int __init crossbar_of_init(struct device_node *node) cb->crossbar_base = of_iomap(node, 0); if (!cb->crossbar_base) - goto err1; + goto err_cb; of_property_read_u32(node, "ti,max-irqs", &max); if (!max) { pr_err("missing 'ti,max-irqs' property\n"); ret = -EINVAL; - goto err2; + goto err_base; } cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL); if (!cb->irq_map) - goto err2; + goto err_base; cb->int_max = max; @@ -169,7 +169,7 @@ static int __init crossbar_of_init(struct device_node *node) if (entry > max) { pr_err("Invalid reserved entry\n"); ret = -EINVAL; - goto err3; + goto err_irq_map; } cb->irq_map[entry] = IRQ_RESERVED; } @@ -187,7 +187,7 @@ static int __init crossbar_of_init(struct device_node *node) if (entry > max) { pr_err("Invalid skip entry\n"); ret = -EINVAL; - goto err3; + goto err_irq_map; } cb->irq_map[entry] = IRQ_SKIP; } @@ -196,7 +196,7 @@ static int __init crossbar_of_init(struct device_node *node) cb->register_offsets = kcalloc(max, sizeof(int), GFP_KERNEL); if (!cb->register_offsets) - goto err3; + goto err_irq_map; of_property_read_u32(node, "ti,reg-size", &size); @@ -213,7 +213,7 @@ static int __init crossbar_of_init(struct device_node *node) default: pr_err("Invalid reg-size property\n"); ret = -EINVAL; - goto err4; + goto err_reg_offset; break; } @@ -230,7 +230,6 @@ static int __init crossbar_of_init(struct device_node *node) } of_property_read_u32(node, "ti,irqs-safe-map", &cb->safe_map); - /* Initialize the crossbar with safe map to start with */ for (i = 0; i < max; i++) { if (cb->irq_map[i] == IRQ_RESERVED || @@ -243,13 +242,13 @@ static int __init crossbar_of_init(struct device_node *node) register_routable_domain_ops(&routable_irq_domain_ops); return 0; -err4: +err_reg_offset: kfree(cb->register_offsets); -err3: +err_irq_map: kfree(cb->irq_map); -err2: +err_base: iounmap(cb->crossbar_base); -err1: +err_cb: kfree(cb); return ret; } -- cgit v0.10.2 From 99e37d0ea607623f286b4841cc355e65b297170c Mon Sep 17 00:00:00 2001 From: Sricharan R Date: Thu, 26 Jun 2014 12:40:29 +0530 Subject: irqchip: crossbar: Set cb pointer to null in case of error If crossbar_of_init returns with a error, then set the cb pointer to null. Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Link: https://lkml.kernel.org/r/1403766634-18543-12-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c index afc35fd..a8c6156 100644 --- a/drivers/irqchip/irq-crossbar.c +++ b/drivers/irqchip/irq-crossbar.c @@ -250,6 +250,8 @@ err_base: iounmap(cb->crossbar_base); err_cb: kfree(cb); + + cb = NULL; return ret; } -- cgit v0.10.2 From 8b09a45dc12f83f2312a47f0f0087ec4004ebacc Mon Sep 17 00:00:00 2001 From: Sricharan R Date: Thu, 26 Jun 2014 12:40:30 +0530 Subject: irqchip: crossbar: Add kerneldoc for crossbar_domain_unmap callback Adding kerneldoc for unmap callback function. Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Link: https://lkml.kernel.org/r/1403766634-18543-13-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c index a8c6156..518d712 100644 --- a/drivers/irqchip/irq-crossbar.c +++ b/drivers/irqchip/irq-crossbar.c @@ -89,6 +89,17 @@ static int crossbar_domain_map(struct irq_domain *d, unsigned int irq, return 0; } +/** + * crossbar_domain_unmap - unmap a crossbar<->irq connection + * @d: domain of irq to unmap + * @irq: virq number + * + * We do not maintain a use count of total number of map/unmap + * calls for a particular irq to find out if a irq can be really + * unmapped. This is because unmap is called during irq_dispose_mapping(irq), + * after which irq is anyways unusable. So an explicit map has to be called + * after that. + */ static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq) { irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq; -- cgit v0.10.2 From 2f7d2fb71dd0c14f9c0fe66f2ed7b4685fa745e2 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 26 Jun 2014 12:40:31 +0530 Subject: irqchip: crossbar: Introduce ti, max-crossbar-sources to identify valid crossbar mapping Currently we attempt to map any crossbar value to an IRQ, however, this is not correct from hardware perspective. There is a max crossbar event number upto which hardware supports. So describe the same in device tree using 'ti,max-crossbar-sources' property and use it to validate requests. [ jac - remove MAX_SOURCES from binding doc, use integer because we shouldn't put implementation details in the binding docs ] Signed-off-by: Nishanth Menon Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Link: https://lkml.kernel.org/r/1403766634-18543-14-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt index 5f45c78..a6e462f 100644 --- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt +++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt @@ -10,6 +10,7 @@ Required properties: - compatible : Should be "ti,irq-crossbar" - reg: Base address and the size of the crossbar registers. - ti,max-irqs: Total number of irqs available at the interrupt controller. +- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed. - ti,reg-size: Size of a individual register in bytes. Every individual register is assumed to be of same size. Valid sizes are 1, 2, 4. - ti,irqs-reserved: List of the reserved irq lines that are not muxed using @@ -30,6 +31,7 @@ Examples: compatible = "ti,irq-crossbar"; reg = <0x4a002a48 0x130>; ti,max-irqs = <160>; + ti,max-crossbar-sources = <400>; ti,reg-size = <2>; ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>; ti,irqs-skip = <10 133 139 140>; diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c index 518d712..c9f068c 100644 --- a/drivers/irqchip/irq-crossbar.c +++ b/drivers/irqchip/irq-crossbar.c @@ -26,6 +26,7 @@ * struct crossbar_device - crossbar device description * @int_max: maximum number of supported interrupts * @safe_map: safe default value to initialize the crossbar + * @max_crossbar_sources: Maximum number of crossbar sources * @irq_map: array of interrupts to crossbar number mapping * @crossbar_base: crossbar base address * @register_offsets: offsets for each irq number @@ -34,6 +35,7 @@ struct crossbar_device { uint int_max; uint safe_map; + uint max_crossbar_sources; uint *irq_map; void __iomem *crossbar_base; int *register_offsets; @@ -117,12 +119,19 @@ static int crossbar_domain_xlate(struct irq_domain *d, unsigned int *out_type) { int ret; + int req_num = intspec[1]; - ret = get_prev_map_irq(intspec[1]); + if (req_num >= cb->max_crossbar_sources) { + pr_err("%s: requested crossbar number %d > max %d\n", + __func__, req_num, cb->max_crossbar_sources); + return -EINVAL; + } + + ret = get_prev_map_irq(req_num); if (ret >= 0) goto found; - ret = allocate_free_irq(intspec[1]); + ret = allocate_free_irq(req_num); if (ret < 0) return ret; @@ -153,6 +162,14 @@ static int __init crossbar_of_init(struct device_node *node) if (!cb->crossbar_base) goto err_cb; + of_property_read_u32(node, "ti,max-crossbar-sources", + &cb->max_crossbar_sources); + if (!cb->max_crossbar_sources) { + pr_err("missing 'ti,max-crossbar-sources' property\n"); + ret = -EINVAL; + goto err_base; + } + of_property_read_u32(node, "ti,max-irqs", &max); if (!max) { pr_err("missing 'ti,max-irqs' property\n"); -- cgit v0.10.2 From 29918b6790d92456cab87ff41a01224e0882d04a Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 26 Jun 2014 12:40:32 +0530 Subject: irqchip: crossbar: Introduce centralized check for crossbar write This is a basic check to ensure that crossbar register needs to be written. This ensures that we have a common check which is used in both map and unmap logic. Signed-off-by: Nishanth Menon Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Link: https://lkml.kernel.org/r/1403766634-18543-15-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c index c9f068c..83f803b 100644 --- a/drivers/irqchip/irq-crossbar.c +++ b/drivers/irqchip/irq-crossbar.c @@ -84,10 +84,20 @@ static inline int allocate_free_irq(int cb_no) return -ENODEV; } +static inline bool needs_crossbar_write(irq_hw_number_t hw) +{ + if (hw > GIC_IRQ_START) + return true; + + return false; +} + static int crossbar_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) { - cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]); + if (needs_crossbar_write(hw)) + cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]); + return 0; } @@ -106,7 +116,7 @@ static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq) { irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq; - if (hw > GIC_IRQ_START) { + if (needs_crossbar_write(hw)) { cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE; cb->write(hw - GIC_IRQ_START, cb->safe_map); } -- cgit v0.10.2 From 9a34f73fb75531507760b957407fb55278b38ae8 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 26 Jun 2014 12:40:33 +0530 Subject: documentation: dt: omap: crossbar: Add description for interrupt consumer The current crossbar description does not include the description required for the consumer of the crossbar, a.k.a devices whoes events pass through the crossbar into the GIC interrupt controller. So, provide documentation for the same. Signed-off-by: Nishanth Menon Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Link: https://lkml.kernel.org/r/1403766634-18543-16-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt index a6e462f..ce7d01d8 100644 --- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt +++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt @@ -36,3 +36,20 @@ Examples: ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>; ti,irqs-skip = <10 133 139 140>; }; + +Consumer: +======== +See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and +Documentation/devicetree/bindings/arm/gic.txt for further details. + +An interrupt consumer on an SoC using crossbar will use: + interrupts = +request number shall be between 0 to that described by +"ti,max-crossbar-sources" + +Example: + device_x@0x4a023000 { + /* Crossbar 8 used */ + interrupts = ; + ... + }; -- cgit v0.10.2 From d360892d37b5d0e82595001c4be6d49311e2c265 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 26 Jun 2014 12:40:34 +0530 Subject: irqchip: crossbar: Allow for quirky hardware with direct hardwiring of GIC On certain platforms such as DRA7, SPIs 0, 1, 2, 3, 5, 6, 10, 131, 132, 133 are direct wired to hardware blocks bypassing crossbar. This quirky implementation is *NOT* supposed to be the expectation of crossbar hardware usage. However, these are already marked in our description of the hardware with SKIP and RESERVED where appropriate. Unfortunately, we need to be able to refer to these hardwired IRQs. So, to request these, crossbar driver can use the existing information from it's table that these SKIP/RESERVED maps are direct wired sources and generic allocation/programming of crossbar should be avoided. Signed-off-by: Nishanth Menon Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Link: https://lkml.kernel.org/r/1403766634-18543-17-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt index ce7d01d8..4139db3 100644 --- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt +++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt @@ -44,8 +44,10 @@ Documentation/devicetree/bindings/arm/gic.txt for further details. An interrupt consumer on an SoC using crossbar will use: interrupts = -request number shall be between 0 to that described by -"ti,max-crossbar-sources" +When the request number is between 0 to that described by +"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the +request_number is greater than "ti,max-crossbar-sources", then it is mapped as a +quirky hardware mapping direct to GIC. Example: device_x@0x4a023000 { @@ -53,3 +55,9 @@ Example: interrupts = ; ... }; + + device_y@0x4a033000 { + /* Direct mapped GIC SPI 1 used */ + interrupts = ; + ... + }; diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c index 83f803b..85c2985 100644 --- a/drivers/irqchip/irq-crossbar.c +++ b/drivers/irqchip/irq-crossbar.c @@ -86,8 +86,13 @@ static inline int allocate_free_irq(int cb_no) static inline bool needs_crossbar_write(irq_hw_number_t hw) { - if (hw > GIC_IRQ_START) - return true; + int cb_no; + + if (hw > GIC_IRQ_START) { + cb_no = cb->irq_map[hw - GIC_IRQ_START]; + if (cb_no != IRQ_RESERVED && cb_no != IRQ_SKIP) + return true; + } return false; } @@ -130,8 +135,19 @@ static int crossbar_domain_xlate(struct irq_domain *d, { int ret; int req_num = intspec[1]; + int direct_map_num; if (req_num >= cb->max_crossbar_sources) { + direct_map_num = req_num - cb->max_crossbar_sources; + if (direct_map_num < cb->int_max) { + ret = cb->irq_map[direct_map_num]; + if (ret == IRQ_RESERVED || ret == IRQ_SKIP) { + /* We use the interrupt num as h/w irq num */ + ret = direct_map_num; + goto found; + } + } + pr_err("%s: requested crossbar number %d > max %d\n", __func__, req_num, cb->max_crossbar_sources); return -EINVAL; -- cgit v0.10.2 From 08ecb28a7047d4431b61b73ebf9b216de6b29444 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 23 Jun 2014 13:20:58 -0500 Subject: ARM: dts: am4372: let boards access all nodes through labels By providing labels for rtc, wdt, cpu and dispc nodes, boards can access them to add board-specific data. Signed-off-by: Felipe Balbi Tested-by: Franklin Cooper Jr. Tested-by: Tom Rini Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 49fa596..8d3c163 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -30,7 +30,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; @@ -270,7 +270,7 @@ ti,hwmods = "counter_32k"; }; - rtc@44e3e000 { + rtc: rtc@44e3e000 { compatible = "ti,am4372-rtc","ti,da830-rtc"; reg = <0x44e3e000 0x1000>; interrupts = ; interrupts = ; @@ -871,7 +871,7 @@ #size-cells = <1>; ranges; - dispc@4832a400 { + dispc: dispc@4832a400 { compatible = "ti,omap3-dispc"; reg = <0x4832a400 0x400>; interrupts = ; -- cgit v0.10.2 From 4a45787dec8a15b211110be807b4f4aad2828385 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 23 Jun 2014 13:20:59 -0500 Subject: ARM: dts: add support for AM437x StarterKit Add support for TI's AM437x StarterKit Evaluation Module. Cc: Josh Elliot Signed-off-by: Felipe Balbi Tested-by: Franklin Cooper Jr. Tested-by: Tom Rini Tested-by: Darren Etheridge Signed-off-by: Tony Lindgren diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt index d22b216..0edc903 100644 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt @@ -129,6 +129,9 @@ Boards: - AM437x GP EVM compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43" +- AM437x SK EVM: AM437x StarterKit Evaluation Module + compatible = "ti,am437x-sk-evm", "ti,am4372", "ti,am43" + - DRA742 EVM: Software Development Board for DRA742 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7" diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5986ff63..63d1e53 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -301,6 +301,7 @@ dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \ omap4-var-dvk-om44.dtb \ omap4-var-stk-om44.dtb dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \ + am437x-sk-evm.dtb \ am437x-gp-evm.dtb dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \ omap5-sbc-t54.dtb \ diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts new file mode 100644 index 0000000..859ff3d --- /dev/null +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -0,0 +1,613 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* AM437x SK EVM */ + +/dts-v1/; + +#include "am4372.dtsi" +#include +#include +#include +#include + +/ { + model = "TI AM437x SK EVM"; + compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43"; + + aliases { + display0 = &lcd0; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; + + sound { + compatible = "ti,da830-evm-audio"; + ti,model = "AM437x-SK-EVM"; + ti,audio-codec = <&tlv320aic3106>; + ti,mcasp-controller = <&mcasp1>; + ti,codec-clock-rate = <24000000>; + ti,audio-routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT"; + }; + + matrix_keypad: matrix_keypad@0 { + compatible = "gpio-matrix-keypad"; + + pinctrl-names = "default"; + pinctrl-0 = <&matrix_keypad_pins>; + + debounce-delay-ms = <5>; + col-scan-delay-us = <1500>; + + row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ + &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ + + col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */ + &gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */ + + linux,keymap = < + MATRIX_KEY(0, 0, KEY_DOWN) + MATRIX_KEY(0, 1, KEY_RIGHT) + MATRIX_KEY(1, 0, KEY_LEFT) + MATRIX_KEY(1, 1, KEY_UP) + >; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins>; + + led@0 { + label = "am437x-sk:red:heartbeat"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */ + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led@1 { + label = "am437x-sk:green:mmc1"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */ + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@2 { + label = "am437x-sk:blue:cpu0"; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */ + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led@3 { + label = "am437x-sk:blue:usr3"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */ + default-state = "off"; + }; + }; + + lcd0: display { + compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; + label = "lcd"; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + + panel-timing { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <43>; + hsync-len = <4>; + vback-porch = <12>; + vfront-porch = <4>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; +}; + +&am43xx_pinmux { + matrix_keypad_pins: matrix_keypad_pins { + pinctrl-single,pins = < + 0x24c (PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */ + 0x250 (PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */ + 0x254 (PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */ + 0x258 (PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */ + >; + }; + + leds_pins: leds_pins { + pinctrl-single,pins = < + 0x228 (PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */ + 0x22c (PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */ + 0x230 (PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */ + 0x234 (PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */ + >; + }; + + i2c0_pins: i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c1_pins: i2c1_pins { + pinctrl-single,pins = < + 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + ecap0_pins: backlight_pins { + pinctrl-single,pins = < + 0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ + >; + }; + + edt_ft5306_ts_pins: edt_ft5306_ts_pins { + pinctrl-single,pins = < + 0x74 (PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + 0x78 (PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ + + /* Slave 2 */ + 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + + /* Slave 2 reset value */ + 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + dss_pins: dss_pins { + pinctrl-single,pins = < + 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ + 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */ + 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ + 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ + 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ + 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ + 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ + 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ + + >; + }; + + qspi_pins: qspi_pins { + pinctrl-single,pins = < + 0x7c (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */ + 0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ + 0x90 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ + 0x94 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ + 0x98 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */ + 0x9c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ + >; + }; + + mcasp1_pins: mcasp1_pins { + pinctrl-single,pins = < + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ + 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ + >; + }; + + lcd_pins: lcd_pins { + pinctrl-single,pins = < + /* GPIO 5_8 to select LCD / HDMI */ + 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + + tps@24 { + compatible = "ti,tps65218"; + reg = <0x24>; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + compatible = "ti,tps65218-dcdc1"; + /* VDD_CORE limits min of OPP50 and max of OPP100 */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + compatible = "ti,tps65218-dcdc2"; + /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + compatible = "ti,tps65218-dcdc3"; + regulator-name = "vdds_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc4: regulator-dcdc4 { + compatible = "ti,tps65218-dcdc4"; + regulator-name = "v3_3d"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,tps65218-ldo1"; + regulator-name = "v1_8d"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + }; + + at24@50 { + compatible = "at24,24c256"; + pagesize = <64>; + reg = <0x50>; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + + edt-ft5306@38 { + status = "okay"; + compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; + pinctrl-names = "default"; + pinctrl-0 = <&edt_ft5306_ts_pins>; + + reg = <0x38>; + interrupt-parent = <&gpio0>; + interrupts = <31 0>; + + wake-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + + touchscreen-size-x = <480>; + touchscreen-size-y = <272>; + }; + + tlv320aic3106: tlv320aic3106@1b { + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + status = "okay"; + + /* Regulators */ + AVDD-supply = <&dcdc4>; + IOVDD-supply = <&dcdc4>; + DRVDD-supply = <&dcdc4>; + DVDD-supply = <&ldo1>; + }; + + lis331dlh@18 { + compatible = "st,lis331dlh"; + reg = <0x18>; + status = "okay"; + + Vdd-supply = <&dcdc4>; + Vdd_IO-supply = <&dcdc4>; + interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&ecap0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + + vmmc-supply = <&dcdc4>; + bus-width = <4>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; +}; + +&usb2_phy1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb2_phy2 { + status = "okay"; +}; + +&usb2 { + dr_mode = "host"; + status = "okay"; +}; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_pins>; + + spi-max-frequency = <48000000>; + m25p80@0 { + compatible = "mx66l51235l"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-cpol; + spi-cpha; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first 512KiB + * for a valid file to boot(XIP). + */ + partition@0 { + label = "QSPI.U_BOOT"; + reg = <0x00000000 0x000080000>; + }; + partition@1 { + label = "QSPI.U_BOOT.backup"; + reg = <0x00080000 0x00080000>; + }; + partition@2 { + label = "QSPI.U-BOOT-SPL_OS"; + reg = <0x00100000 0x00010000>; + }; + partition@3 { + label = "QSPI.U_BOOT_ENV"; + reg = <0x00110000 0x00010000>; + }; + partition@4 { + label = "QSPI.U-BOOT-ENV.backup"; + reg = <0x00120000 0x00010000>; + }; + partition@5 { + label = "QSPI.KERNEL"; + reg = <0x00130000 0x0800000>; + }; + partition@6 { + label = "QSPI.FILESYSTEM"; + reg = <0x00930000 0x36D0000>; + }; + }; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + dual_emac = <1>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <4>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <5>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <2>; +}; + +&elm { + status = "okay"; +}; + +&mcasp1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcasp1_pins>; + + status = "okay"; + + op-mode = <0>; + tdm-slots = <2>; + serial-dir = < + 0 0 1 2 + >; + + tx-num-evt = <1>; + rx-num-evt = <1>; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_pins>; + + port { + dpi_out: endpoint@0 { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; -- cgit v0.10.2 From 944ee5dc154b1618d4c794376af237f370c1e6b3 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 20 Feb 2014 19:09:18 +0200 Subject: ARM: OMAP2: convert sys_ck and osc_ck to standard clock types osc_ck can be simply defined as a multiplexer clock, and the sys_ck can be a simple divider. Signed-off-by: Tero Kristo diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 8421f38..b5dc4b5 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -174,10 +174,9 @@ obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o +obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c index 3662f4d..3e46ac1 100644 --- a/arch/arm/mach-omap2/cclock2420_data.c +++ b/arch/arm/mach-omap2/cclock2420_data.c @@ -57,40 +57,39 @@ DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); -static struct clk osc_ck; +DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0); -static const struct clk_ops osc_ck_ops = { - .recalc_rate = &omap2_osc_clk_recalc, -}; +DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0); -static struct clk_hw_omap osc_ck_hw = { - .hw = { - .clk = &osc_ck, - }, -}; +DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_26m_ck, CLK_IS_ROOT, 26000000, 0x0); -static struct clk osc_ck = { - .name = "osc_ck", - .ops = &osc_ck_ops, - .hw = &osc_ck_hw.hw, - .flags = CLK_IS_ROOT, +/* 26M ck is a dummy, added to fill the hole in the aplls_clkin parent list */ +static const char *aplls_clkin_ck_parent_names[] = { + "virt_19200000_ck", "virt_26m_ck", "virt_13m_ck", "virt_12m_ck", }; +DEFINE_CLK_MUX(aplls_clkin_ck, aplls_clkin_ck_parent_names, NULL, 0x0, + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_APLLS_CLKIN_SHIFT, + OMAP24XX_APLLS_CLKIN_WIDTH, 0x0, NULL); + DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); -static struct clk sys_ck; +DEFINE_CLK_FIXED_FACTOR(aplls_clkin_x2_ck, "aplls_clkin_ck", &aplls_clkin_ck, + 0x0, 2, 1); -static const char *sys_ck_parent_names[] = { - "osc_ck", +static const char *osc_ck_parent_names[] = { + "aplls_clkin_ck", "aplls_clkin_x2_ck", }; -static const struct clk_ops sys_ck_ops = { - .init = &omap2_init_clk_clkdm, - .recalc_rate = &omap2xxx_sys_clk_recalc, -}; +DEFINE_CLK_MUX(osc_ck, osc_ck_parent_names, NULL, 0x0, + OMAP2420_PRCM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT, + OMAP_SYSCLKDIV_WIDTH, CLK_MUX_INDEX_ONE, NULL); -DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm"); -DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops); +DEFINE_CLK_DIVIDER(sys_ck, "osc_ck", &osc_ck, 0x0, OMAP2420_PRCM_CLKSRC_CTRL, + OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); static struct dpll_data dpll_dd = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), @@ -1741,6 +1740,12 @@ static struct omap_clk omap2420_clks[] = { /* external root sources */ CLK(NULL, "func_32k_ck", &func_32k_ck), CLK(NULL, "secure_32k_ck", &secure_32k_ck), + CLK(NULL, "virt_12m_ck", &virt_12m_ck), + CLK(NULL, "virt_13m_ck", &virt_13m_ck), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), + CLK(NULL, "virt_26m_ck", &virt_26m_ck), + CLK(NULL, "aplls_clkin_ck", &aplls_clkin_ck), + CLK(NULL, "aplls_clkin_x2_ck", &aplls_clkin_x2_ck), CLK(NULL, "osc_ck", &osc_ck), CLK(NULL, "sys_ck", &sys_ck), CLK(NULL, "alt_ck", &alt_ck), @@ -1904,7 +1909,6 @@ static const char *enable_init_clks[] = { int __init omap2420_clk_init(void) { - prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; cpu_mask = RATE_IN_242X; rate_table = omap2420_rate_table; diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c index 5e4b037..582abc2 100644 --- a/arch/arm/mach-omap2/cclock2430_data.c +++ b/arch/arm/mach-omap2/cclock2430_data.c @@ -55,42 +55,39 @@ DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); -static struct clk osc_ck; +DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0); -static const struct clk_ops osc_ck_ops = { - .enable = &omap2_enable_osc_ck, - .disable = omap2_disable_osc_ck, - .recalc_rate = &omap2_osc_clk_recalc, -}; +DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0); -static struct clk_hw_omap osc_ck_hw = { - .hw = { - .clk = &osc_ck, - }, -}; +DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); -static struct clk osc_ck = { - .name = "osc_ck", - .ops = &osc_ck_ops, - .hw = &osc_ck_hw.hw, - .flags = CLK_IS_ROOT, +DEFINE_CLK_FIXED_RATE(virt_26m_ck, CLK_IS_ROOT, 26000000, 0x0); + +/* 26M ck is a dummy, added to filla hole in the aplls_clkin parent list */ +static const char *aplls_clkin_ck_parent_names[] = { + "virt_19200000_ck", "virt_26m_ck", "virt_13m_ck", "virt_12m_ck", }; +DEFINE_CLK_MUX(aplls_clkin_ck, aplls_clkin_ck_parent_names, NULL, 0x0, + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_APLLS_CLKIN_SHIFT, + OMAP24XX_APLLS_CLKIN_WIDTH, 0x0, NULL); + DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); -static struct clk sys_ck; +DEFINE_CLK_FIXED_FACTOR(aplls_clkin_x2_ck, "aplls_clkin_ck", &aplls_clkin_ck, + 0x0, 2, 1); -static const char *sys_ck_parent_names[] = { - "osc_ck", +static const char *osc_ck_parent_names[] = { + "aplls_clkin_ck", "aplls_clkin_x2_ck", }; -static const struct clk_ops sys_ck_ops = { - .init = &omap2_init_clk_clkdm, - .recalc_rate = &omap2xxx_sys_clk_recalc, -}; +DEFINE_CLK_MUX(osc_ck, osc_ck_parent_names, NULL, 0x0, + OMAP2430_PRCM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT, + OMAP_SYSCLKDIV_WIDTH, CLK_MUX_INDEX_ONE, NULL); -DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm"); -DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops); +DEFINE_CLK_DIVIDER(sys_ck, "osc_ck", &osc_ck, 0x0, OMAP2430_PRCM_CLKSRC_CTRL, + OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); static struct dpll_data dpll_dd = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), @@ -1308,7 +1305,11 @@ static struct clk_hw_omap mdm_osc_ck_hw = { .clkdm_name = "mdm_clkdm", }; -DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops); +static const char *mdm_osc_ck_parent_names[] = { + "osc_ck", +}; + +DEFINE_STRUCT_CLK(mdm_osc_ck, mdm_osc_ck_parent_names, aes_ick_ops); static struct clk mmchs1_fck; @@ -1842,6 +1843,12 @@ static struct omap_clk omap2430_clks[] = { /* external root sources */ CLK(NULL, "func_32k_ck", &func_32k_ck), CLK(NULL, "secure_32k_ck", &secure_32k_ck), + CLK(NULL, "virt_12m_ck", &virt_12m_ck), + CLK(NULL, "virt_13m_ck", &virt_13m_ck), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), + CLK(NULL, "virt_26m_ck", &virt_26m_ck), + CLK(NULL, "aplls_clkin_ck", &aplls_clkin_ck), + CLK(NULL, "aplls_clkin_x2_ck", &aplls_clkin_x2_ck), CLK(NULL, "osc_ck", &osc_ck), CLK("twl", "fck", &osc_ck), CLK(NULL, "sys_ck", &sys_ck), @@ -2021,7 +2028,6 @@ static const char *enable_init_clks[] = { int __init omap2430_clk_init(void) { - prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; cpu_mask = RATE_IN_243X; rate_table = omap2430_rate_table; diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c deleted file mode 100644 index 0717dff..0000000 --- a/arch/arm/mach-omap2/clkt2xxx_osc.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * OMAP2xxx osc_clk-specific clock code - * - * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2010 Nokia Corporation - * - * Contacts: - * Richard Woodruff - * Paul Walmsley - * - * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, - * Gordon McNutt and RidgeRun, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include -#include -#include -#include -#include - -#include "clock.h" -#include "clock2xxx.h" -#include "prm2xxx_3xxx.h" -#include "prm-regbits-24xx.h" - -/* - * XXX This does not actually enable the osc_ck, since the osc_ck must - * be running for this function to be called. Instead, this function - * is used to disable an autoidle mode on the osc_ck. The existing - * clk_enable/clk_disable()-based usecounting for osc_ck should be - * replaced with autoidle-based usecounting. - */ -int omap2_enable_osc_ck(struct clk_hw *clk) -{ - u32 pcc; - - pcc = readl_relaxed(prcm_clksrc_ctrl); - - writel_relaxed(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); - - return 0; -} - -/* - * XXX This does not actually disable the osc_ck, since doing so would - * immediately halt the system. Instead, this function is used to - * enable an autoidle mode on the osc_ck. The existing - * clk_enable/clk_disable()-based usecounting for osc_ck should be - * replaced with autoidle-based usecounting. - */ -void omap2_disable_osc_ck(struct clk_hw *clk) -{ - u32 pcc; - - pcc = readl_relaxed(prcm_clksrc_ctrl); - - writel_relaxed(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); -} - -unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, - unsigned long parent_rate) -{ - return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv(); -} diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c deleted file mode 100644 index 58dd3a9..0000000 --- a/arch/arm/mach-omap2/clkt2xxx_sys.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * OMAP2xxx sys_clk-specific clock code - * - * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2010 Nokia Corporation - * - * Contacts: - * Richard Woodruff - * Paul Walmsley - * - * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, - * Gordon McNutt and RidgeRun, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include -#include -#include -#include - -#include "clock.h" -#include "clock2xxx.h" -#include "prm2xxx_3xxx.h" -#include "prm-regbits-24xx.h" - -void __iomem *prcm_clksrc_ctrl; - -u32 omap2xxx_get_sysclkdiv(void) -{ - u32 div; - - div = readl_relaxed(prcm_clksrc_ctrl); - div &= OMAP_SYSCLKDIV_MASK; - div >>= OMAP_SYSCLKDIV_SHIFT; - - return div; -} - -unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk, - unsigned long parent_rate) -{ - return parent_rate / omap2xxx_get_sysclkdiv(); -} diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index 45f41a4..a090225 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h @@ -45,8 +45,6 @@ int omap2430_clk_init(void); #define omap2430_clk_init() do { } while(0) #endif -extern void __iomem *prcm_clksrc_ctrl; - extern struct clk_hw *dclk_hw; int omap2_enable_osc_ck(struct clk_hw *hw); void omap2_disable_osc_ck(struct clk_hw *hw); diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 8538669..d7a5d11 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -107,6 +107,7 @@ #define OMAP24XX_AUTO_DPLL_SHIFT 0 #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) #define OMAP24XX_APLLS_CLKIN_SHIFT 23 +#define OMAP24XX_APLLS_CLKIN_WIDTH 3 #define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) #define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index a5ea988..d7ac05c 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -249,6 +249,10 @@ static void __init prcm_setup_regs(void) /* Enable wake-up events */ omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, WKUP_MOD, PM_WKEN); + + /* Enable SYS_CLKEN control when all domains idle */ + omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD, + OMAP2_PRCM_CLKSRC_CTRL_OFFSET); } int __init omap2_pm_init(void) -- cgit v0.10.2 From b675d1ecced015f180d5d43056bed94cda87d80f Mon Sep 17 00:00:00 2001 From: Darren Etheridge Date: Tue, 1 Jul 2014 16:00:20 -0500 Subject: ARM: dts: am335x-evmsk: enable display and lcd panel support Add the necessary nodes to enable the LCD controller and the LCD panel that is attached to the Texas Instruments AM335x EVMSK platform. Also setup the necessary pin mux within the DT file to drive the LCD connector and add the correct pinmux settings for the lcd pins to be configured to when the SoC goes into sleep state for the minimum power consumption. For the sleep mode LCD pin settings, MUX_MODE7 is chosen as this corresponds to switching the pins into input GPIO's with an internal pulldown. Which has been determined to offer the lowest power solution vs leaving the pins configured in LCD mode. Signed-off-by: Darren Etheridge Acked-by: Wolfram Sang Tested-by: Felipe Balbi Acked-by: Tomi Valkeinen Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index ab9a34c..59766e2 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -149,12 +149,113 @@ "Headphone Jack", "HPLOUT", "Headphone Jack", "HPROUT"; }; + + panel { + compatible = "ti,tilcdc,panel"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcd_pins_default>; + pinctrl-1 = <&lcd_pins_sleep>; + status = "okay"; + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <32>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + display-timings { + 480x272 { + hactive = <480>; + vactive = <272>; + hback-porch = <43>; + hfront-porch = <8>; + hsync-len = <4>; + vback-porch = <12>; + vfront-porch = <4>; + vsync-len = <10>; + clock-frequency = <9000000>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; + }; }; &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; + lcd_pins_default: lcd_pins_default { + pinctrl-single,pins = < + 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ + 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ + 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ + 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ + 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ + 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ + 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ + 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ + 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + + lcd_pins_sleep: lcd_pins_sleep { + pinctrl-single,pins = < + 0x20 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */ + 0x24 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */ + 0x28 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */ + 0x2c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */ + 0x30 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */ + 0x34 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */ + 0x38 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */ + 0x3c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */ + 0xa0 (PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */ + 0xa4 (PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */ + 0xa8 (PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */ + 0xac (PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */ + 0xb0 (PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */ + 0xb4 (PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */ + 0xb8 (PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */ + 0xbc (PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */ + 0xc0 (PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */ + 0xc4 (PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */ + 0xc8 (PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */ + 0xcc (PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */ + 0xd0 (PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */ + 0xd4 (PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */ + 0xd8 (PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */ + 0xdc (PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */ + 0xe0 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */ + 0xe4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */ + 0xe8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */ + 0xec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + + user_leds_s0: user_leds_s0 { pinctrl-single,pins = < 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ @@ -573,3 +674,7 @@ ti,wire-config = <0x00 0x11 0x22 0x33>; }; }; + +&lcdc { + status = "okay"; +}; -- cgit v0.10.2 From a37f05ac094fb0474ddaea8bcfa2c18e0df8cb2e Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 21 Feb 2014 15:33:05 +0200 Subject: ARM: OMAP2420: clock: get rid of fixed-div property use Cleans up the code a bit and is useful for clock data DT conversion. Signed-off-by: Tero Kristo diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c index 3e46ac1..3b0beea 100644 --- a/arch/arm/mach-omap2/cclock2420_data.c +++ b/arch/arm/mach-omap2/cclock2420_data.c @@ -1025,18 +1025,12 @@ DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel, OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait, dsp_fck_parent_names, dsp_fck_ops); +DEFINE_CLK_FIXED_FACTOR(iva1_ifck_div, "iva1_ifck", &iva1_ifck, 0x0, 1, 2); + static struct clk iva1_mpu_int_ifck; static const char *iva1_mpu_int_ifck_parent_names[] = { - "iva1_ifck", -}; - -static const struct clk_ops iva1_mpu_int_ifck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap_fixed_divisor_recalc, + "iva1_ifck_div", }; static struct clk_hw_omap iva1_mpu_int_ifck_hw = { @@ -1047,11 +1041,10 @@ static struct clk_hw_omap iva1_mpu_int_ifck_hw = { .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, .clkdm_name = "iva1_clkdm", - .fixed_div = 2, }; DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names, - iva1_mpu_int_ifck_ops); + aes_ick_ops); static struct clk mailboxes_ick; diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 591581a..4ac6e3d 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -82,27 +82,6 @@ u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) } /* - * Used for clocks that have the same value as the parent clock, - * divided by some factor - */ -unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_hw_omap *oclk; - - if (!hw) { - pr_warn("%s: hw is NULL\n", __func__); - return -EINVAL; - } - - oclk = to_clk_hw_omap(hw); - - WARN_ON(!oclk->fixed_div); - - return parent_rate / oclk->fixed_div; -} - -/* * OMAP2+ specific clock functions */ diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 12f54d4..bb67238 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -178,9 +178,6 @@ struct clksel { const struct clksel_rate *rates; }; -unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, - unsigned long parent_rate); - /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0 #define CORE_CLK_SRC_DPLL 0x1 -- cgit v0.10.2 From ee200119c03c7d43ebaf7ae70985244aedb0586d Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 25 Feb 2014 09:21:39 +0200 Subject: ARM: OMAP2: PRM: add support for OMAP2 specific clock providers This patch adds support for initializing also omap2-prcm and omap2-scrm through DT. Signed-off-by: Tero Kristo diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt new file mode 100644 index 0000000..79074da --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt @@ -0,0 +1,65 @@ +OMAP PRCM bindings + +Power Reset and Clock Manager lists the device clocks and clockdomains under +a DT hierarchy. Each TI SoC can have multiple PRCM entities listed for it, +each describing one module and the clock hierarchy under it. see [1] for +documentation about the individual clock/clockdomain nodes. + +[1] Documentation/devicetree/bindings/clock/ti/* + +Required properties: +- compatible: Must be one of: + "ti,am3-prcm" + "ti,am3-scrm" + "ti,am4-prcm" + "ti,am4-scrm" + "ti,omap2-prcm" + "ti,omap2-scrm" + "ti,omap3-prm" + "ti,omap3-cm" + "ti,omap3-scrm" + "ti,omap4-cm1" + "ti,omap4-prm" + "ti,omap4-cm2" + "ti,omap4-scrm" + "ti,omap5-prm" + "ti,omap5-cm-core-aon" + "ti,omap5-scrm" + "ti,omap5-cm-core" + "ti,dra7-prm" + "ti,dra7-cm-core-aon" + "ti,dra7-cm-core" +- reg: Contains PRCM module register address range + (base address and length) +- clocks: clocks for this module +- clockdomains: clockdomains for this module + +Example: + +cm: cm@48004000 { + compatible = "ti,omap3-cm"; + reg = <0x48004000 0x4000>; + + cm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_clockdomains: clockdomains { + }; +} + +&cm_clocks { + omap2_32k_fck: omap_32k_fck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; +}; + +&cm_clockdomains { + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&sdrc_ick>; + }; +}; diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 25e8b82..76ca320 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -472,6 +472,8 @@ static struct of_device_id omap_prcm_dt_match_table[] = { { .compatible = "ti,am3-scrm" }, { .compatible = "ti,am4-prcm" }, { .compatible = "ti,am4-scrm" }, + { .compatible = "ti,omap2-prcm" }, + { .compatible = "ti,omap2-scrm" }, { .compatible = "ti,omap3-prm" }, { .compatible = "ti,omap3-cm" }, { .compatible = "ti,omap3-scrm" }, -- cgit v0.10.2 From 69a1e7a1feb5bac44a5a76380768596a12a33050 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 24 Feb 2014 18:51:05 +0200 Subject: ARM: OMAP2: clock: use DT clock boot if available Otherwise legacy boot clock data is used. This patch also includes the clock data files to the base dtsi files. Signed-off-by: Tero Kristo diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index e83b046..2ad3e3b 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -182,3 +182,6 @@ &i2c2 { compatible = "ti,omap2420-i2c"; }; + +/include/ "omap24xx-clocks.dtsi" +/include/ "omap2420-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index c4e8013..f9ab99d 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -288,3 +288,6 @@ &i2c2 { compatible = "ti,omap2430-i2c"; }; + +/include/ "omap24xx-clocks.dtsi" +/include/ "omap2430-clocks.dtsi" diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 8f55945..80bf633 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -53,6 +53,7 @@ #include "prm2xxx.h" #include "prm3xxx.h" #include "prm44xx.h" +#include "opp2xxx.h" /* * omap_clk_soc_init: points to a function that does the SoC-specific @@ -410,7 +411,12 @@ void __init omap2420_init_early(void) omap242x_clockdomains_init(); omap2420_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_soc_init = omap2420_clk_init; + if (of_have_populated_dt()) { + omap_clk_soc_init = omap2420_dt_clk_init; + rate_table = omap2420_rate_table; + } else { + omap_clk_soc_init = omap2420_clk_init; + } } void __init omap2420_init_late(void) @@ -439,7 +445,12 @@ void __init omap2430_init_early(void) omap243x_clockdomains_init(); omap2430_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_soc_init = omap2430_clk_init; + if (of_have_populated_dt()) { + omap_clk_soc_init = omap2430_dt_clk_init; + rate_table = omap2430_rate_table; + } else { + omap_clk_soc_init = omap2430_clk_init; + } } void __init omap2430_init_late(void) -- cgit v0.10.2 From 6a194a6e2a8fa55e133936a124ed500aea434116 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 4 Mar 2014 10:53:54 +0200 Subject: ARM: OMAP24xx: clock: remove legacy clock data This is no longer needed as clock data is provided through DT. Signed-off-by: Tero Kristo diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index b5dc4b5..7d387c0 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -178,8 +178,7 @@ obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o -obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o -obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o +obj-$(CONFIG_SOC_OMAP2430) += clock2430.o obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c deleted file mode 100644 index 3b0beea..0000000 --- a/arch/arm/mach-omap2/cclock2420_data.c +++ /dev/null @@ -1,1928 +0,0 @@ -/* - * OMAP2420 clock data - * - * Copyright (C) 2005-2012 Texas Instruments, Inc. - * Copyright (C) 2004-2011 Nokia Corporation - * - * Contacts: - * Richard Woodruff - * Paul Walmsley - * Updated to COMMON clk format by Rajendra Nayak - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include "soc.h" -#include "iomap.h" -#include "clock.h" -#include "clock2xxx.h" -#include "opp2xxx.h" -#include "cm2xxx.h" -#include "prm2xxx.h" -#include "prm-regbits-24xx.h" -#include "cm-regbits-24xx.h" -#include "sdrc.h" -#include "control.h" - -#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR - -/* - * 2420 clock tree. - * - * NOTE:In many cases here we are assigning a 'default' parent. In - * many cases the parent is selectable. The set parent calls will - * also switch sources. - * - * Several sources are given initial rates which may be wrong, this will - * be fixed up in the init func. - * - * Things are broadly separated below by clock domains. It is - * noteworthy that most peripherals have dependencies on multiple clock - * domains. Many get their interface clocks from the L4 domain, but get - * functional clocks from fixed sources or other core domain derived - * clocks. - */ - -DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0); - -DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); - -DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_26m_ck, CLK_IS_ROOT, 26000000, 0x0); - -/* 26M ck is a dummy, added to fill the hole in the aplls_clkin parent list */ -static const char *aplls_clkin_ck_parent_names[] = { - "virt_19200000_ck", "virt_26m_ck", "virt_13m_ck", "virt_12m_ck", -}; - -DEFINE_CLK_MUX(aplls_clkin_ck, aplls_clkin_ck_parent_names, NULL, 0x0, - OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_APLLS_CLKIN_SHIFT, - OMAP24XX_APLLS_CLKIN_WIDTH, 0x0, NULL); - -DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); - -DEFINE_CLK_FIXED_FACTOR(aplls_clkin_x2_ck, "aplls_clkin_ck", &aplls_clkin_ck, - 0x0, 2, 1); - -static const char *osc_ck_parent_names[] = { - "aplls_clkin_ck", "aplls_clkin_x2_ck", -}; - -DEFINE_CLK_MUX(osc_ck, osc_ck_parent_names, NULL, 0x0, - OMAP2420_PRCM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT, - OMAP_SYSCLKDIV_WIDTH, CLK_MUX_INDEX_ONE, NULL); - -DEFINE_CLK_DIVIDER(sys_ck, "osc_ck", &osc_ck, 0x0, OMAP2420_PRCM_CLKSRC_CTRL, - OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -static struct dpll_data dpll_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .mult_mask = OMAP24XX_DPLL_MULT_MASK, - .div1_mask = OMAP24XX_DPLL_DIV_MASK, - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_mask = OMAP24XX_EN_DPLL_MASK, - .max_multiplier = 1023, - .min_divider = 1, - .max_divider = 16, -}; - -static struct clk dpll_ck; - -static const char *dpll_ck_parent_names[] = { - "sys_ck", -}; - -static const struct clk_ops dpll_ck_ops = { - .init = &omap2_init_clk_clkdm, - .get_parent = &omap2_init_dpll_parent, - .recalc_rate = &omap2_dpllcore_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap2_reprogram_dpllcore, -}; - -static struct clk_hw_omap dpll_ck_hw = { - .hw = { - .clk = &dpll_ck, - }, - .ops = &clkhwops_omap2xxx_dpll, - .dpll_data = &dpll_dd, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); - -static struct clk core_ck; - -static const char *core_ck_parent_names[] = { - "dpll_ck", -}; - -static const struct clk_ops core_ck_ops = { - .init = &omap2_init_clk_clkdm, -}; - -DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm"); -DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops); - -DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -static struct clk aes_ick; - -static const char *aes_ick_parent_names[] = { - "l4_ck", -}; - -static const struct clk_ops aes_ick_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, -}; - -static struct clk_hw_omap aes_ick_hw = { - .hw = { - .clk = &aes_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_AES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk apll54_ck; - -static const struct clk_ops apll54_ck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_clk_apll54_enable, - .disable = &omap2_clk_apll54_disable, - .recalc_rate = &omap2_clk_apll54_recalc, -}; - -static struct clk_hw_omap apll54_ck_hw = { - .hw = { - .clk = &apll54_ck, - }, - .ops = &clkhwops_apll54, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); - -static struct clk apll96_ck; - -static const struct clk_ops apll96_ck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_clk_apll96_enable, - .disable = &omap2_clk_apll96_disable, - .recalc_rate = &omap2_clk_apll96_recalc, -}; - -static struct clk_hw_omap apll96_ck_hw = { - .hw = { - .clk = &apll96_ck, - }, - .ops = &clkhwops_apll96, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops); - -static struct clk func_96m_ck; - -static const char *func_96m_ck_parent_names[] = { - "apll96_ck", -}; - -DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm"); -DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops); - -static struct clk cam_fck; - -static const char *cam_fck_parent_names[] = { - "func_96m_ck", -}; - -static struct clk_hw_omap cam_fck_hw = { - .hw = { - .clk = &cam_fck, - }, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_CAM_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk cam_ick; - -static struct clk_hw_omap cam_ick_hw = { - .hw = { - .clk = &cam_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_CAM_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk des_ick; - -static struct clk_hw_omap des_ick_hw = { - .hw = { - .clk = &des_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_DES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate dsp_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_242X }, - { .div = 8, .val = 8, .flags = RATE_IN_242X }, - { .div = 12, .val = 12, .flags = RATE_IN_242X }, - { .div = 0 } -}; - -static const struct clksel dsp_fck_clksel[] = { - { .parent = &core_ck, .rates = dsp_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *dsp_fck_parent_names[] = { - "core_ck", -}; - -static const struct clk_ops dsp_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, -}; - -DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_DSP_MASK, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, - dsp_fck_parent_names, dsp_fck_ops); - -static const struct clksel dsp_ick_clksel[] = { - { .parent = &dsp_fck, .rates = dsp_ick_rates }, - { .parent = NULL }, -}; - -static const char *dsp_ick_parent_names[] = { - "dsp_fck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_DSP_IF_MASK, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), - OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait, - dsp_ick_parent_names, dsp_fck_ops); - -static const struct clksel_rate dss1_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate dss1_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 5, .val = 5, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_24XX }, - { .div = 8, .val = 8, .flags = RATE_IN_24XX }, - { .div = 9, .val = 9, .flags = RATE_IN_24XX }, - { .div = 12, .val = 12, .flags = RATE_IN_24XX }, - { .div = 16, .val = 16, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel dss1_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, - { .parent = &core_ck, .rates = dss1_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *dss1_fck_parent_names[] = { - "sys_ck", "core_ck", -}; - -static struct clk dss1_fck; - -static const struct clk_ops dss1_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_DSS1_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_DSS1_SHIFT, NULL, - dss1_fck_parent_names, dss1_fck_ops); - -static const struct clksel_rate dss2_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate dss2_fck_48m_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate func_48m_apll96_rates[] = { - { .div = 2, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate func_48m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel func_48m_clksel[] = { - { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, - { .parent = &alt_ck, .rates = func_48m_alt_rates }, - { .parent = NULL }, -}; - -static const char *func_48m_ck_parent_names[] = { - "apll96_ck", "alt_ck", -}; - -static struct clk func_48m_ck; - -static const struct clk_ops func_48m_ck_ops = { - .init = &omap2_init_clk_clkdm, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -static struct clk_hw_omap func_48m_ck_hw = { - .hw = { - .clk = &func_48m_ck, - }, - .clksel = func_48m_clksel, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_48M_SOURCE_MASK, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops); - -static const struct clksel dss2_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, - { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, - { .parent = NULL }, -}; - -static const char *dss2_fck_parent_names[] = { - "sys_ck", "func_48m_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_DSS2_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_DSS2_SHIFT, NULL, - dss2_fck_parent_names, dss1_fck_ops); - -static const char *func_54m_ck_parent_names[] = { - "apll54_ck", "alt_ck", -}; - -DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, - OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, - 0x0, NULL); - -static struct clk dss_54m_fck; - -static const char *dss_54m_fck_parent_names[] = { - "func_54m_ck", -}; - -static struct clk_hw_omap dss_54m_fck_hw = { - .hw = { - .clk = &dss_54m_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_TV_SHIFT, - .clkdm_name = "dss_clkdm", -}; - -DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); - -static struct clk dss_ick; - -static struct clk_hw_omap dss_ick_hw = { - .hw = { - .clk = &dss_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_DSS1_SHIFT, - .clkdm_name = "dss_clkdm", -}; - -DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk eac_fck; - -static struct clk_hw_omap eac_fck_hw = { - .hw = { - .clk = &eac_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_EAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk eac_ick; - -static struct clk_hw_omap eac_ick_hw = { - .hw = { - .clk = &eac_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_EAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk emul_ck; - -static struct clk_hw_omap emul_ck_hw = { - .hw = { - .clk = &emul_ck, - }, - .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL, - .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); - -DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); - -static struct clk fac_fck; - -static const char *fac_fck_parent_names[] = { - "func_12m_ck", -}; - -static struct clk_hw_omap fac_fck_hw = { - .hw = { - .clk = &fac_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk fac_ick; - -static struct clk_hw_omap fac_ick_hw = { - .hw = { - .clk = &fac_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel gfx_fck_clksel[] = { - { .parent = &core_l3_ck, .rates = gfx_l3_rates }, - { .parent = NULL }, -}; - -static const char *gfx_2d_fck_parent_names[] = { - "core_l3_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel, - OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - OMAP_CLKSEL_GFX_MASK, - OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - OMAP24XX_EN_2D_SHIFT, &clkhwops_wait, - gfx_2d_fck_parent_names, dsp_fck_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, - OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - OMAP_CLKSEL_GFX_MASK, - OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, - gfx_2d_fck_parent_names, dsp_fck_ops); - -static struct clk gfx_ick; - -static const char *gfx_ick_parent_names[] = { - "core_l3_ck", -}; - -static struct clk_hw_omap gfx_ick_hw = { - .hw = { - .clk = &gfx_ick, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), - .enable_bit = OMAP_EN_GFX_SHIFT, - .clkdm_name = "gfx_clkdm", -}; - -DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); - -static struct clk gpios_fck; - -static const char *gpios_fck_parent_names[] = { - "func_32k_ck", -}; - -static struct clk_hw_omap gpios_fck_hw = { - .hw = { - .clk = &gpios_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops); - -static struct clk gpios_ick; - -static const char *gpios_ick_parent_names[] = { - "sys_ck", -}; - -static struct clk_hw_omap gpios_ick_hw = { - .hw = { - .clk = &gpios_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk gpmc_fck; - -static struct clk_hw_omap gpmc_fck_hw = { - .hw = { - .clk = &gpmc_fck, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops); - -static const struct clksel_rate gpt_alt_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel omap24xx_gpt_clksel[] = { - { .parent = &func_32k_ck, .rates = gpt_32k_rates }, - { .parent = &sys_ck, .rates = gpt_sys_rates }, - { .parent = &alt_ck, .rates = gpt_alt_rates }, - { .parent = NULL }, -}; - -static const char *gpt10_fck_parent_names[] = { - "func_32k_ck", "sys_ck", "alt_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT10_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt10_ick; - -static struct clk_hw_omap gpt10_ick_hw = { - .hw = { - .clk = &gpt10_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT10_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT11_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt11_ick; - -static struct clk_hw_omap gpt11_ick_hw = { - .hw = { - .clk = &gpt11_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT11_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT12_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt12_ick; - -static struct clk_hw_omap gpt12_ick_hw = { - .hw = { - .clk = &gpt12_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT12_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clk_ops gpt1_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_GPT1_MASK, - OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, gpt1_fck_ops); - -static struct clk gpt1_ick; - -static struct clk_hw_omap gpt1_ick_hw = { - .hw = { - .clk = &gpt1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_GPT1_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT2_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt2_ick; - -static struct clk_hw_omap gpt2_ick_hw = { - .hw = { - .clk = &gpt2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT3_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt3_ick; - -static struct clk_hw_omap gpt3_ick_hw = { - .hw = { - .clk = &gpt3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT4_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt4_ick; - -static struct clk_hw_omap gpt4_ick_hw = { - .hw = { - .clk = &gpt4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT5_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt5_ick; - -static struct clk_hw_omap gpt5_ick_hw = { - .hw = { - .clk = &gpt5_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT5_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT6_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt6_ick; - -static struct clk_hw_omap gpt6_ick_hw = { - .hw = { - .clk = &gpt6_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT6_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT7_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt7_ick; - -static struct clk_hw_omap gpt7_ick_hw = { - .hw = { - .clk = &gpt7_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT7_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT8_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt8_ick; - -static struct clk_hw_omap gpt8_ick_hw = { - .hw = { - .clk = &gpt8_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT8_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT9_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt9_ick; - -static struct clk_hw_omap gpt9_ick_hw = { - .hw = { - .clk = &gpt9_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT9_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk hdq_fck; - -static struct clk_hw_omap hdq_fck_hw = { - .hw = { - .clk = &hdq_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk hdq_ick; - -static struct clk_hw_omap hdq_ick_hw = { - .hw = { - .clk = &hdq_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk i2c1_fck; - -static struct clk_hw_omap i2c1_fck_hw = { - .hw = { - .clk = &i2c1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_I2C1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk i2c1_ick; - -static struct clk_hw_omap i2c1_ick_hw = { - .hw = { - .clk = &i2c1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_I2C1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk i2c2_fck; - -static struct clk_hw_omap i2c2_fck_hw = { - .hw = { - .clk = &i2c2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_I2C2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk i2c2_ick; - -static struct clk_hw_omap i2c2_ick_hw = { - .hw = { - .clk = &i2c2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_I2C2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - OMAP2420_CLKSEL_IVA_MASK, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait, - dsp_fck_parent_names, dsp_fck_ops); - -DEFINE_CLK_FIXED_FACTOR(iva1_ifck_div, "iva1_ifck", &iva1_ifck, 0x0, 1, 2); - -static struct clk iva1_mpu_int_ifck; - -static const char *iva1_mpu_int_ifck_parent_names[] = { - "iva1_ifck_div", -}; - -static struct clk_hw_omap iva1_mpu_int_ifck_hw = { - .hw = { - .clk = &iva1_mpu_int_ifck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, - .clkdm_name = "iva1_clkdm", -}; - -DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names, - aes_ick_ops); - -static struct clk mailboxes_ick; - -static struct clk_hw_omap mailboxes_ick_hw = { - .hw = { - .clk = &mailboxes_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate common_mcbsp_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel mcbsp_fck_clksel[] = { - { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, - { .parent = NULL }, -}; - -static const char *mcbsp1_fck_parent_names[] = { - "func_96m_ck", "mcbsp_clks", -}; - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - OMAP2_MCBSP1_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp1_ick; - -static struct clk_hw_omap mcbsp1_ick_hw = { - .hw = { - .clk = &mcbsp1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - OMAP2_MCBSP2_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp2_ick; - -static struct clk_hw_omap mcbsp2_ick_hw = { - .hw = { - .clk = &mcbsp2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mcspi1_fck; - -static const char *mcspi1_fck_parent_names[] = { - "func_48m_ck", -}; - -static struct clk_hw_omap mcspi1_fck_hw = { - .hw = { - .clk = &mcspi1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk mcspi1_ick; - -static struct clk_hw_omap mcspi1_ick_hw = { - .hw = { - .clk = &mcspi1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mcspi2_fck; - -static struct clk_hw_omap mcspi2_fck_hw = { - .hw = { - .clk = &mcspi2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk mcspi2_ick; - -static struct clk_hw_omap mcspi2_ick_hw = { - .hw = { - .clk = &mcspi2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mmc_fck; - -static struct clk_hw_omap mmc_fck_hw = { - .hw = { - .clk = &mmc_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_MMC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk mmc_ick; - -static struct clk_hw_omap mmc_ick_hw = { - .hw = { - .clk = &mmc_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_MMC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, - OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -static struct clk mpu_wdt_fck; - -static struct clk_hw_omap mpu_wdt_fck_hw = { - .hw = { - .clk = &mpu_wdt_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops); - -static struct clk mpu_wdt_ick; - -static struct clk_hw_omap mpu_wdt_ick_hw = { - .hw = { - .clk = &mpu_wdt_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk mspro_fck; - -static struct clk_hw_omap mspro_fck_hw = { - .hw = { - .clk = &mspro_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk mspro_ick; - -static struct clk_hw_omap mspro_ick_hw = { - .hw = { - .clk = &mspro_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk omapctrl_ick; - -static struct clk_hw_omap omapctrl_ick_hw = { - .hw = { - .clk = &omapctrl_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk pka_ick; - -static struct clk_hw_omap pka_ick_hw = { - .hw = { - .clk = &pka_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_PKA_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk rng_ick; - -static struct clk_hw_omap rng_ick_hw = { - .hw = { - .clk = &rng_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_RNG_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk sdma_fck; - -DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); -DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); - -static struct clk sdma_ick; - -static struct clk_hw_omap sdma_ick_hw = { - .hw = { - .clk = &sdma_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); - -static struct clk sdrc_ick; - -static struct clk_hw_omap sdrc_ick_hw = { - .hw = { - .clk = &sdrc_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); - -static struct clk sha_ick; - -static struct clk_hw_omap sha_ick_hw = { - .hw = { - .clk = &sha_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_SHA_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk ssi_l4_ick; - -static struct clk_hw_omap ssi_l4_ick_hw = { - .hw = { - .clk = &ssi_l4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_SSI_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_242X }, - { .div = 8, .val = 8, .flags = RATE_IN_242X }, - { .div = 0 } -}; - -static const struct clksel ssi_ssr_sst_fck_clksel[] = { - { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *ssi_ssr_sst_fck_parent_names[] = { - "core_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", - ssi_ssr_sst_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_SSI_MASK, - OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, - ssi_ssr_sst_fck_parent_names, dsp_fck_ops); - -static struct clk sync_32k_ick; - -static struct clk_hw_omap sync_32k_ick_hw = { - .hw = { - .clk = &sync_32k_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate common_clkout_src_core_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_96m_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_54m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel common_clkout_src_clksel[] = { - { .parent = &core_ck, .rates = common_clkout_src_core_rates }, - { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, - { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, - { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, - { .parent = NULL }, -}; - -static const char *sys_clkout_src_parent_names[] = { - "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel, - OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK, - OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT, - NULL, sys_clkout_src_parent_names, gpt1_fck_ops); - -DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0, - OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT, - OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); - -DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm", - common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL, - OMAP2420_CLKOUT2_SOURCE_MASK, - OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT, - NULL, sys_clkout_src_parent_names, gpt1_fck_ops); - -DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0, - OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT, - OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); - -static struct clk uart1_fck; - -static struct clk_hw_omap uart1_fck_hw = { - .hw = { - .clk = &uart1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_UART1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart1_ick; - -static struct clk_hw_omap uart1_ick_hw = { - .hw = { - .clk = &uart1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_UART1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk uart2_fck; - -static struct clk_hw_omap uart2_fck_hw = { - .hw = { - .clk = &uart2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_UART2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart2_ick; - -static struct clk_hw_omap uart2_ick_hw = { - .hw = { - .clk = &uart2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_UART2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk uart3_fck; - -static struct clk_hw_omap uart3_fck_hw = { - .hw = { - .clk = &uart3_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_UART3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart3_ick; - -static struct clk_hw_omap uart3_ick_hw = { - .hw = { - .clk = &uart3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_UART3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk usb_fck; - -static struct clk_hw_omap usb_fck_hw = { - .hw = { - .clk = &usb_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_USB_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel usb_l4_ick_clksel[] = { - { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, - { .parent = NULL }, -}; - -static const char *usb_l4_ick_parent_names[] = { - "core_l3_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_USB_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, - usb_l4_ick_parent_names, dsp_fck_ops); - -static struct clk virt_prcm_set; - -static const char *virt_prcm_set_parent_names[] = { - "mpu_ck", -}; - -static const struct clk_ops virt_prcm_set_ops = { - .recalc_rate = &omap2_table_mpu_recalc, - .set_rate = &omap2_select_table_rate, - .round_rate = &omap2_round_to_table_rate, -}; - -DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL); -DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops); - -static const struct clksel_rate vlynq_fck_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_242X }, - { .div = 0 } -}; - -static const struct clksel_rate vlynq_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_242X }, - { .div = 2, .val = 2, .flags = RATE_IN_242X }, - { .div = 3, .val = 3, .flags = RATE_IN_242X }, - { .div = 4, .val = 4, .flags = RATE_IN_242X }, - { .div = 6, .val = 6, .flags = RATE_IN_242X }, - { .div = 8, .val = 8, .flags = RATE_IN_242X }, - { .div = 9, .val = 9, .flags = RATE_IN_242X }, - { .div = 12, .val = 12, .flags = RATE_IN_242X }, - { .div = 16, .val = 16, .flags = RATE_IN_242X }, - { .div = 18, .val = 18, .flags = RATE_IN_242X }, - { .div = 0 } -}; - -static const struct clksel vlynq_fck_clksel[] = { - { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, - { .parent = &core_ck, .rates = vlynq_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *vlynq_fck_parent_names[] = { - "func_96m_ck", "core_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP2420_CLKSEL_VLYNQ_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait, - vlynq_fck_parent_names, dss1_fck_ops); - -static struct clk vlynq_ick; - -static struct clk_hw_omap vlynq_ick_hw = { - .hw = { - .clk = &vlynq_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops); - -static struct clk wdt1_ick; - -static struct clk_hw_omap wdt1_ick_hw = { - .hw = { - .clk = &wdt1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_WDT1_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk wdt3_fck; - -static struct clk_hw_omap wdt3_fck_hw = { - .hw = { - .clk = &wdt3_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_WDT3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops); - -static struct clk wdt3_ick; - -static struct clk_hw_omap wdt3_ick_hw = { - .hw = { - .clk = &wdt3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_WDT3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk wdt4_fck; - -static struct clk_hw_omap wdt4_fck_hw = { - .hw = { - .clk = &wdt4_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_WDT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops); - -static struct clk wdt4_ick; - -static struct clk_hw_omap wdt4_ick_hw = { - .hw = { - .clk = &wdt4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_WDT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); - -/* - * clkdev integration - */ - -static struct omap_clk omap2420_clks[] = { - /* external root sources */ - CLK(NULL, "func_32k_ck", &func_32k_ck), - CLK(NULL, "secure_32k_ck", &secure_32k_ck), - CLK(NULL, "virt_12m_ck", &virt_12m_ck), - CLK(NULL, "virt_13m_ck", &virt_13m_ck), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), - CLK(NULL, "virt_26m_ck", &virt_26m_ck), - CLK(NULL, "aplls_clkin_ck", &aplls_clkin_ck), - CLK(NULL, "aplls_clkin_x2_ck", &aplls_clkin_x2_ck), - CLK(NULL, "osc_ck", &osc_ck), - CLK(NULL, "sys_ck", &sys_ck), - CLK(NULL, "alt_ck", &alt_ck), - CLK(NULL, "mcbsp_clks", &mcbsp_clks), - /* internal analog sources */ - CLK(NULL, "dpll_ck", &dpll_ck), - CLK(NULL, "apll96_ck", &apll96_ck), - CLK(NULL, "apll54_ck", &apll54_ck), - /* internal prcm root sources */ - CLK(NULL, "func_54m_ck", &func_54m_ck), - CLK(NULL, "core_ck", &core_ck), - CLK(NULL, "func_96m_ck", &func_96m_ck), - CLK(NULL, "func_48m_ck", &func_48m_ck), - CLK(NULL, "func_12m_ck", &func_12m_ck), - CLK(NULL, "sys_clkout_src", &sys_clkout_src), - CLK(NULL, "sys_clkout", &sys_clkout), - CLK(NULL, "sys_clkout2_src", &sys_clkout2_src), - CLK(NULL, "sys_clkout2", &sys_clkout2), - CLK(NULL, "emul_ck", &emul_ck), - /* mpu domain clocks */ - CLK(NULL, "mpu_ck", &mpu_ck), - /* dsp domain clocks */ - CLK(NULL, "dsp_fck", &dsp_fck), - CLK(NULL, "dsp_ick", &dsp_ick), - CLK(NULL, "iva1_ifck", &iva1_ifck), - CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck), - /* GFX domain clocks */ - CLK(NULL, "gfx_3d_fck", &gfx_3d_fck), - CLK(NULL, "gfx_2d_fck", &gfx_2d_fck), - CLK(NULL, "gfx_ick", &gfx_ick), - /* DSS domain clocks */ - CLK("omapdss_dss", "ick", &dss_ick), - CLK(NULL, "dss_ick", &dss_ick), - CLK(NULL, "dss1_fck", &dss1_fck), - CLK(NULL, "dss2_fck", &dss2_fck), - CLK(NULL, "dss_54m_fck", &dss_54m_fck), - /* L3 domain clocks */ - CLK(NULL, "core_l3_ck", &core_l3_ck), - CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck), - CLK(NULL, "usb_l4_ick", &usb_l4_ick), - /* L4 domain clocks */ - CLK(NULL, "l4_ck", &l4_ck), - CLK(NULL, "ssi_l4_ick", &ssi_l4_ick), - /* virtual meta-group clock */ - CLK(NULL, "virt_prcm_set", &virt_prcm_set), - /* general l4 interface ck, multi-parent functional clk */ - CLK(NULL, "gpt1_ick", &gpt1_ick), - CLK(NULL, "gpt1_fck", &gpt1_fck), - CLK(NULL, "gpt2_ick", &gpt2_ick), - CLK(NULL, "gpt2_fck", &gpt2_fck), - CLK(NULL, "gpt3_ick", &gpt3_ick), - CLK(NULL, "gpt3_fck", &gpt3_fck), - CLK(NULL, "gpt4_ick", &gpt4_ick), - CLK(NULL, "gpt4_fck", &gpt4_fck), - CLK(NULL, "gpt5_ick", &gpt5_ick), - CLK(NULL, "gpt5_fck", &gpt5_fck), - CLK(NULL, "gpt6_ick", &gpt6_ick), - CLK(NULL, "gpt6_fck", &gpt6_fck), - CLK(NULL, "gpt7_ick", &gpt7_ick), - CLK(NULL, "gpt7_fck", &gpt7_fck), - CLK(NULL, "gpt8_ick", &gpt8_ick), - CLK(NULL, "gpt8_fck", &gpt8_fck), - CLK(NULL, "gpt9_ick", &gpt9_ick), - CLK(NULL, "gpt9_fck", &gpt9_fck), - CLK(NULL, "gpt10_ick", &gpt10_ick), - CLK(NULL, "gpt10_fck", &gpt10_fck), - CLK(NULL, "gpt11_ick", &gpt11_ick), - CLK(NULL, "gpt11_fck", &gpt11_fck), - CLK(NULL, "gpt12_ick", &gpt12_ick), - CLK(NULL, "gpt12_fck", &gpt12_fck), - CLK("omap-mcbsp.1", "ick", &mcbsp1_ick), - CLK(NULL, "mcbsp1_ick", &mcbsp1_ick), - CLK(NULL, "mcbsp1_fck", &mcbsp1_fck), - CLK("omap-mcbsp.2", "ick", &mcbsp2_ick), - CLK(NULL, "mcbsp2_ick", &mcbsp2_ick), - CLK(NULL, "mcbsp2_fck", &mcbsp2_fck), - CLK("omap2_mcspi.1", "ick", &mcspi1_ick), - CLK(NULL, "mcspi1_ick", &mcspi1_ick), - CLK(NULL, "mcspi1_fck", &mcspi1_fck), - CLK("omap2_mcspi.2", "ick", &mcspi2_ick), - CLK(NULL, "mcspi2_ick", &mcspi2_ick), - CLK(NULL, "mcspi2_fck", &mcspi2_fck), - CLK(NULL, "uart1_ick", &uart1_ick), - CLK(NULL, "uart1_fck", &uart1_fck), - CLK(NULL, "uart2_ick", &uart2_ick), - CLK(NULL, "uart2_fck", &uart2_fck), - CLK(NULL, "uart3_ick", &uart3_ick), - CLK(NULL, "uart3_fck", &uart3_fck), - CLK(NULL, "gpios_ick", &gpios_ick), - CLK(NULL, "gpios_fck", &gpios_fck), - CLK("omap_wdt", "ick", &mpu_wdt_ick), - CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick), - CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck), - CLK(NULL, "sync_32k_ick", &sync_32k_ick), - CLK(NULL, "wdt1_ick", &wdt1_ick), - CLK(NULL, "omapctrl_ick", &omapctrl_ick), - CLK("omap24xxcam", "fck", &cam_fck), - CLK(NULL, "cam_fck", &cam_fck), - CLK("omap24xxcam", "ick", &cam_ick), - CLK(NULL, "cam_ick", &cam_ick), - CLK(NULL, "mailboxes_ick", &mailboxes_ick), - CLK(NULL, "wdt4_ick", &wdt4_ick), - CLK(NULL, "wdt4_fck", &wdt4_fck), - CLK(NULL, "wdt3_ick", &wdt3_ick), - CLK(NULL, "wdt3_fck", &wdt3_fck), - CLK(NULL, "mspro_ick", &mspro_ick), - CLK(NULL, "mspro_fck", &mspro_fck), - CLK("mmci-omap.0", "ick", &mmc_ick), - CLK(NULL, "mmc_ick", &mmc_ick), - CLK("mmci-omap.0", "fck", &mmc_fck), - CLK(NULL, "mmc_fck", &mmc_fck), - CLK(NULL, "fac_ick", &fac_ick), - CLK(NULL, "fac_fck", &fac_fck), - CLK(NULL, "eac_ick", &eac_ick), - CLK(NULL, "eac_fck", &eac_fck), - CLK("omap_hdq.0", "ick", &hdq_ick), - CLK(NULL, "hdq_ick", &hdq_ick), - CLK("omap_hdq.0", "fck", &hdq_fck), - CLK(NULL, "hdq_fck", &hdq_fck), - CLK("omap_i2c.1", "ick", &i2c1_ick), - CLK(NULL, "i2c1_ick", &i2c1_ick), - CLK(NULL, "i2c1_fck", &i2c1_fck), - CLK("omap_i2c.2", "ick", &i2c2_ick), - CLK(NULL, "i2c2_ick", &i2c2_ick), - CLK(NULL, "i2c2_fck", &i2c2_fck), - CLK(NULL, "gpmc_fck", &gpmc_fck), - CLK(NULL, "sdma_fck", &sdma_fck), - CLK(NULL, "sdma_ick", &sdma_ick), - CLK(NULL, "sdrc_ick", &sdrc_ick), - CLK(NULL, "vlynq_ick", &vlynq_ick), - CLK(NULL, "vlynq_fck", &vlynq_fck), - CLK(NULL, "des_ick", &des_ick), - CLK("omap-sham", "ick", &sha_ick), - CLK(NULL, "sha_ick", &sha_ick), - CLK("omap_rng", "ick", &rng_ick), - CLK(NULL, "rng_ick", &rng_ick), - CLK("omap-aes", "ick", &aes_ick), - CLK(NULL, "aes_ick", &aes_ick), - CLK(NULL, "pka_ick", &pka_ick), - CLK(NULL, "usb_fck", &usb_fck), - CLK("musb-hdrc", "fck", &osc_ck), - CLK(NULL, "timer_32k_ck", &func_32k_ck), - CLK(NULL, "timer_sys_ck", &sys_ck), - CLK(NULL, "timer_ext_ck", &alt_ck), - CLK(NULL, "cpufreq_ck", &virt_prcm_set), -}; - - -static const char *enable_init_clks[] = { - "apll96_ck", - "apll54_ck", - "sync_32k_ick", - "omapctrl_ick", - "gpmc_fck", - "sdrc_ick", -}; - -/* - * init code - */ - -int __init omap2420_clk_init(void) -{ - cpu_mask = RATE_IN_242X; - rate_table = omap2420_rate_table; - - omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw); - - omap2xxx_clkt_vps_check_bootloader_rates(); - - omap_clocks_register(omap2420_clks, ARRAY_SIZE(omap2420_clks)); - - omap2xxx_clkt_vps_late_init(); - - omap2_clk_disable_autoidle_all(); - - omap2_clk_enable_init_clocks(enable_init_clks, - ARRAY_SIZE(enable_init_clks)); - - pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(&sys_ck) / 1000000), - (clk_get_rate(&sys_ck) / 100000) % 10, - (clk_get_rate(&dpll_ck) / 1000000), - (clk_get_rate(&mpu_ck) / 1000000)); - - return 0; -} diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c deleted file mode 100644 index 582abc2..0000000 --- a/arch/arm/mach-omap2/cclock2430_data.c +++ /dev/null @@ -1,2054 +0,0 @@ -/* - * OMAP2430 clock data - * - * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc. - * Copyright (C) 2004-2011 Nokia Corporation - * - * Contacts: - * Richard Woodruff - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include "soc.h" -#include "iomap.h" -#include "clock.h" -#include "clock2xxx.h" -#include "opp2xxx.h" -#include "cm2xxx.h" -#include "prm2xxx.h" -#include "prm-regbits-24xx.h" -#include "cm-regbits-24xx.h" -#include "sdrc.h" -#include "control.h" - -#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR - -/* - * 2430 clock tree. - * - * NOTE:In many cases here we are assigning a 'default' parent. In - * many cases the parent is selectable. The set parent calls will - * also switch sources. - * - * Several sources are given initial rates which may be wrong, this will - * be fixed up in the init func. - * - * Things are broadly separated below by clock domains. It is - * noteworthy that most peripherals have dependencies on multiple clock - * domains. Many get their interface clocks from the L4 domain, but get - * functional clocks from fixed sources or other core domain derived - * clocks. - */ - -DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0); - -DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); - -DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_26m_ck, CLK_IS_ROOT, 26000000, 0x0); - -/* 26M ck is a dummy, added to filla hole in the aplls_clkin parent list */ -static const char *aplls_clkin_ck_parent_names[] = { - "virt_19200000_ck", "virt_26m_ck", "virt_13m_ck", "virt_12m_ck", -}; - -DEFINE_CLK_MUX(aplls_clkin_ck, aplls_clkin_ck_parent_names, NULL, 0x0, - OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_APLLS_CLKIN_SHIFT, - OMAP24XX_APLLS_CLKIN_WIDTH, 0x0, NULL); - -DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); - -DEFINE_CLK_FIXED_FACTOR(aplls_clkin_x2_ck, "aplls_clkin_ck", &aplls_clkin_ck, - 0x0, 2, 1); - -static const char *osc_ck_parent_names[] = { - "aplls_clkin_ck", "aplls_clkin_x2_ck", -}; - -DEFINE_CLK_MUX(osc_ck, osc_ck_parent_names, NULL, 0x0, - OMAP2430_PRCM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT, - OMAP_SYSCLKDIV_WIDTH, CLK_MUX_INDEX_ONE, NULL); - -DEFINE_CLK_DIVIDER(sys_ck, "osc_ck", &osc_ck, 0x0, OMAP2430_PRCM_CLKSRC_CTRL, - OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -static struct dpll_data dpll_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .mult_mask = OMAP24XX_DPLL_MULT_MASK, - .div1_mask = OMAP24XX_DPLL_DIV_MASK, - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_mask = OMAP24XX_EN_DPLL_MASK, - .max_multiplier = 1023, - .min_divider = 1, - .max_divider = 16, -}; - -static struct clk dpll_ck; - -static const char *dpll_ck_parent_names[] = { - "sys_ck", -}; - -static const struct clk_ops dpll_ck_ops = { - .init = &omap2_init_clk_clkdm, - .get_parent = &omap2_init_dpll_parent, - .recalc_rate = &omap2_dpllcore_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap2_reprogram_dpllcore, -}; - -static struct clk_hw_omap dpll_ck_hw = { - .hw = { - .clk = &dpll_ck, - }, - .ops = &clkhwops_omap2xxx_dpll, - .dpll_data = &dpll_dd, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); - -static struct clk core_ck; - -static const char *core_ck_parent_names[] = { - "dpll_ck", -}; - -static const struct clk_ops core_ck_ops = { - .init = &omap2_init_clk_clkdm, -}; - -DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm"); -DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops); - -DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -static struct clk aes_ick; - -static const char *aes_ick_parent_names[] = { - "l4_ck", -}; - -static const struct clk_ops aes_ick_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, -}; - -static struct clk_hw_omap aes_ick_hw = { - .hw = { - .clk = &aes_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_AES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk apll54_ck; - -static const struct clk_ops apll54_ck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_clk_apll54_enable, - .disable = &omap2_clk_apll54_disable, - .recalc_rate = &omap2_clk_apll54_recalc, -}; - -static struct clk_hw_omap apll54_ck_hw = { - .hw = { - .clk = &apll54_ck, - }, - .ops = &clkhwops_apll54, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); - -static struct clk apll96_ck; - -static const struct clk_ops apll96_ck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_clk_apll96_enable, - .disable = &omap2_clk_apll96_disable, - .recalc_rate = &omap2_clk_apll96_recalc, -}; - -static struct clk_hw_omap apll96_ck_hw = { - .hw = { - .clk = &apll96_ck, - }, - .ops = &clkhwops_apll96, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops); - -static const char *func_96m_ck_parent_names[] = { - "apll96_ck", "alt_ck", -}; - -DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0, - OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT, - OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL); - -static struct clk cam_fck; - -static const char *cam_fck_parent_names[] = { - "func_96m_ck", -}; - -static struct clk_hw_omap cam_fck_hw = { - .hw = { - .clk = &cam_fck, - }, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_CAM_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk cam_ick; - -static struct clk_hw_omap cam_ick_hw = { - .hw = { - .clk = &cam_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_CAM_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk des_ick; - -static struct clk_hw_omap des_ick_hw = { - .hw = { - .clk = &des_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_DES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate dsp_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel dsp_fck_clksel[] = { - { .parent = &core_ck, .rates = dsp_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *dsp_fck_parent_names[] = { - "core_ck", -}; - -static struct clk dsp_fck; - -static const struct clk_ops dsp_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, -}; - -DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_DSP_MASK, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, - dsp_fck_parent_names, dsp_fck_ops); - -static const struct clksel_rate dss1_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate dss1_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 5, .val = 5, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_24XX }, - { .div = 8, .val = 8, .flags = RATE_IN_24XX }, - { .div = 9, .val = 9, .flags = RATE_IN_24XX }, - { .div = 12, .val = 12, .flags = RATE_IN_24XX }, - { .div = 16, .val = 16, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel dss1_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, - { .parent = &core_ck, .rates = dss1_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *dss1_fck_parent_names[] = { - "sys_ck", "core_ck", -}; - -static const struct clk_ops dss1_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_DSS1_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_DSS1_SHIFT, NULL, - dss1_fck_parent_names, dss1_fck_ops); - -static const struct clksel_rate dss2_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate dss2_fck_48m_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate func_48m_apll96_rates[] = { - { .div = 2, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate func_48m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel func_48m_clksel[] = { - { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, - { .parent = &alt_ck, .rates = func_48m_alt_rates }, - { .parent = NULL }, -}; - -static const char *func_48m_ck_parent_names[] = { - "apll96_ck", "alt_ck", -}; - -static struct clk func_48m_ck; - -static const struct clk_ops func_48m_ck_ops = { - .init = &omap2_init_clk_clkdm, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -static struct clk_hw_omap func_48m_ck_hw = { - .hw = { - .clk = &func_48m_ck, - }, - .clksel = func_48m_clksel, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_48M_SOURCE_MASK, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops); - -static const struct clksel dss2_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, - { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, - { .parent = NULL }, -}; - -static const char *dss2_fck_parent_names[] = { - "sys_ck", "func_48m_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_DSS2_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_DSS2_SHIFT, NULL, - dss2_fck_parent_names, dss1_fck_ops); - -static const char *func_54m_ck_parent_names[] = { - "apll54_ck", "alt_ck", -}; - -DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, - OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL); - -static struct clk dss_54m_fck; - -static const char *dss_54m_fck_parent_names[] = { - "func_54m_ck", -}; - -static struct clk_hw_omap dss_54m_fck_hw = { - .hw = { - .clk = &dss_54m_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_TV_SHIFT, - .clkdm_name = "dss_clkdm", -}; - -DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); - -static struct clk dss_ick; - -static struct clk_hw_omap dss_ick_hw = { - .hw = { - .clk = &dss_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_DSS1_SHIFT, - .clkdm_name = "dss_clkdm", -}; - -DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk emul_ck; - -static struct clk_hw_omap emul_ck_hw = { - .hw = { - .clk = &emul_ck, - }, - .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL, - .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); - -DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); - -static struct clk fac_fck; - -static const char *fac_fck_parent_names[] = { - "func_12m_ck", -}; - -static struct clk_hw_omap fac_fck_hw = { - .hw = { - .clk = &fac_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk fac_ick; - -static struct clk_hw_omap fac_ick_hw = { - .hw = { - .clk = &fac_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel gfx_fck_clksel[] = { - { .parent = &core_l3_ck, .rates = gfx_l3_rates }, - { .parent = NULL }, -}; - -static const char *gfx_2d_fck_parent_names[] = { - "core_l3_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel, - OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - OMAP_CLKSEL_GFX_MASK, - OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - OMAP24XX_EN_2D_SHIFT, &clkhwops_wait, - gfx_2d_fck_parent_names, dsp_fck_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, - OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - OMAP_CLKSEL_GFX_MASK, - OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, - gfx_2d_fck_parent_names, dsp_fck_ops); - -static struct clk gfx_ick; - -static const char *gfx_ick_parent_names[] = { - "core_l3_ck", -}; - -static struct clk_hw_omap gfx_ick_hw = { - .hw = { - .clk = &gfx_ick, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), - .enable_bit = OMAP_EN_GFX_SHIFT, - .clkdm_name = "gfx_clkdm", -}; - -DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); - -static struct clk gpio5_fck; - -static const char *gpio5_fck_parent_names[] = { - "func_32k_ck", -}; - -static struct clk_hw_omap gpio5_fck_hw = { - .hw = { - .clk = &gpio5_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_GPIO5_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops); - -static struct clk gpio5_ick; - -static struct clk_hw_omap gpio5_ick_hw = { - .hw = { - .clk = &gpio5_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_GPIO5_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk gpios_fck; - -static struct clk_hw_omap gpios_fck_hw = { - .hw = { - .clk = &gpios_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops); - -static struct clk gpios_ick; - -static const char *gpios_ick_parent_names[] = { - "sys_ck", -}; - -static struct clk_hw_omap gpios_ick_hw = { - .hw = { - .clk = &gpios_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk gpmc_fck; - -static struct clk_hw_omap gpmc_fck_hw = { - .hw = { - .clk = &gpmc_fck, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops); - -static const struct clksel_rate gpt_alt_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel omap24xx_gpt_clksel[] = { - { .parent = &func_32k_ck, .rates = gpt_32k_rates }, - { .parent = &sys_ck, .rates = gpt_sys_rates }, - { .parent = &alt_ck, .rates = gpt_alt_rates }, - { .parent = NULL }, -}; - -static const char *gpt10_fck_parent_names[] = { - "func_32k_ck", "sys_ck", "alt_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT10_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt10_ick; - -static struct clk_hw_omap gpt10_ick_hw = { - .hw = { - .clk = &gpt10_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT10_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT11_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt11_ick; - -static struct clk_hw_omap gpt11_ick_hw = { - .hw = { - .clk = &gpt11_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT11_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT12_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt12_ick; - -static struct clk_hw_omap gpt12_ick_hw = { - .hw = { - .clk = &gpt12_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT12_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clk_ops gpt1_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_GPT1_MASK, - OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, gpt1_fck_ops); - -static struct clk gpt1_ick; - -static struct clk_hw_omap gpt1_ick_hw = { - .hw = { - .clk = &gpt1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_GPT1_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT2_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt2_ick; - -static struct clk_hw_omap gpt2_ick_hw = { - .hw = { - .clk = &gpt2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT3_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt3_ick; - -static struct clk_hw_omap gpt3_ick_hw = { - .hw = { - .clk = &gpt3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT4_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt4_ick; - -static struct clk_hw_omap gpt4_ick_hw = { - .hw = { - .clk = &gpt4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT5_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt5_ick; - -static struct clk_hw_omap gpt5_ick_hw = { - .hw = { - .clk = &gpt5_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT5_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT6_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt6_ick; - -static struct clk_hw_omap gpt6_ick_hw = { - .hw = { - .clk = &gpt6_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT6_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT7_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt7_ick; - -static struct clk_hw_omap gpt7_ick_hw = { - .hw = { - .clk = &gpt7_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT7_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk gpt8_fck; - -DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT8_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt8_ick; - -static struct clk_hw_omap gpt8_ick_hw = { - .hw = { - .clk = &gpt8_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT8_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT9_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt9_ick; - -static struct clk_hw_omap gpt9_ick_hw = { - .hw = { - .clk = &gpt9_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT9_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk hdq_fck; - -static struct clk_hw_omap hdq_fck_hw = { - .hw = { - .clk = &hdq_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk hdq_ick; - -static struct clk_hw_omap hdq_ick_hw = { - .hw = { - .clk = &hdq_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk i2c1_ick; - -static struct clk_hw_omap i2c1_ick_hw = { - .hw = { - .clk = &i2c1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_I2C1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk i2c2_ick; - -static struct clk_hw_omap i2c2_ick_hw = { - .hw = { - .clk = &i2c2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_I2C2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk i2chs1_fck; - -static struct clk_hw_omap i2chs1_fck_hw = { - .hw = { - .clk = &i2chs1_fck, - }, - .ops = &clkhwops_omap2430_i2chs_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk i2chs2_fck; - -static struct clk_hw_omap i2chs2_fck_hw = { - .hw = { - .clk = &i2chs2_fck, - }, - .ops = &clkhwops_omap2430_i2chs_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk icr_ick; - -static struct clk_hw_omap icr_ick_hw = { - .hw = { - .clk = &icr_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP2430_EN_ICR_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(icr_ick, gpios_ick_parent_names, aes_ick_ops); - -static const struct clksel dsp_ick_clksel[] = { - { .parent = &dsp_fck, .rates = dsp_ick_rates }, - { .parent = NULL }, -}; - -static const char *iva2_1_ick_parent_names[] = { - "dsp_fck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_DSP_IF_MASK, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, - iva2_1_ick_parent_names, dsp_fck_ops); - -static struct clk mailboxes_ick; - -static struct clk_hw_omap mailboxes_ick_hw = { - .hw = { - .clk = &mailboxes_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate common_mcbsp_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel mcbsp_fck_clksel[] = { - { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, - { .parent = NULL }, -}; - -static const char *mcbsp1_fck_parent_names[] = { - "func_96m_ck", "mcbsp_clks", -}; - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - OMAP2_MCBSP1_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp1_ick; - -static struct clk_hw_omap mcbsp1_ick_hw = { - .hw = { - .clk = &mcbsp1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - OMAP2_MCBSP2_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp2_ick; - -static struct clk_hw_omap mcbsp2_ick_hw = { - .hw = { - .clk = &mcbsp2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), - OMAP2_MCBSP3_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - OMAP2430_EN_MCBSP3_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp3_ick; - -static struct clk_hw_omap mcbsp3_ick_hw = { - .hw = { - .clk = &mcbsp3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp3_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), - OMAP2_MCBSP4_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - OMAP2430_EN_MCBSP4_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp4_ick; - -static struct clk_hw_omap mcbsp4_ick_hw = { - .hw = { - .clk = &mcbsp4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp4_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), - OMAP2_MCBSP5_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - OMAP2430_EN_MCBSP5_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp5_ick; - -static struct clk_hw_omap mcbsp5_ick_hw = { - .hw = { - .clk = &mcbsp5_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp5_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mcspi1_fck; - -static const char *mcspi1_fck_parent_names[] = { - "func_48m_ck", -}; - -static struct clk_hw_omap mcspi1_fck_hw = { - .hw = { - .clk = &mcspi1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk mcspi1_ick; - -static struct clk_hw_omap mcspi1_ick_hw = { - .hw = { - .clk = &mcspi1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mcspi2_fck; - -static struct clk_hw_omap mcspi2_fck_hw = { - .hw = { - .clk = &mcspi2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk mcspi2_ick; - -static struct clk_hw_omap mcspi2_ick_hw = { - .hw = { - .clk = &mcspi2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mcspi3_fck; - -static struct clk_hw_omap mcspi3_fck_hw = { - .hw = { - .clk = &mcspi3_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi3_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk mcspi3_ick; - -static struct clk_hw_omap mcspi3_ick_hw = { - .hw = { - .clk = &mcspi3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi3_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate mdm_ick_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_243X }, - { .div = 4, .val = 4, .flags = RATE_IN_243X }, - { .div = 6, .val = 6, .flags = RATE_IN_243X }, - { .div = 9, .val = 9, .flags = RATE_IN_243X }, - { .div = 0 } -}; - -static const struct clksel mdm_ick_clksel[] = { - { .parent = &core_ck, .rates = mdm_ick_core_rates }, - { .parent = NULL }, -}; - -static const char *mdm_ick_parent_names[] = { - "core_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(mdm_ick, "mdm_clkdm", mdm_ick_clksel, - OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), - OMAP2430_CLKSEL_MDM_MASK, - OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), - OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, - &clkhwops_iclk_wait, mdm_ick_parent_names, - dsp_fck_ops); - -static struct clk mdm_intc_ick; - -static struct clk_hw_omap mdm_intc_ick_hw = { - .hw = { - .clk = &mdm_intc_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mdm_intc_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mdm_osc_ck; - -static struct clk_hw_omap mdm_osc_ck_hw = { - .hw = { - .clk = &mdm_osc_ck, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), - .enable_bit = OMAP2430_EN_OSC_SHIFT, - .clkdm_name = "mdm_clkdm", -}; - -static const char *mdm_osc_ck_parent_names[] = { - "osc_ck", -}; - -DEFINE_STRUCT_CLK(mdm_osc_ck, mdm_osc_ck_parent_names, aes_ick_ops); - -static struct clk mmchs1_fck; - -static struct clk_hw_omap mmchs1_fck_hw = { - .hw = { - .clk = &mmchs1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchs1_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk mmchs1_ick; - -static struct clk_hw_omap mmchs1_ick_hw = { - .hw = { - .clk = &mmchs1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchs1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mmchs2_fck; - -static struct clk_hw_omap mmchs2_fck_hw = { - .hw = { - .clk = &mmchs2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchs2_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk mmchs2_ick; - -static struct clk_hw_omap mmchs2_ick_hw = { - .hw = { - .clk = &mmchs2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchs2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mmchsdb1_fck; - -static struct clk_hw_omap mmchsdb1_fck_hw = { - .hw = { - .clk = &mmchsdb1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchsdb1_fck, gpio5_fck_parent_names, aes_ick_ops); - -static struct clk mmchsdb2_fck; - -static struct clk_hw_omap mmchsdb2_fck_hw = { - .hw = { - .clk = &mmchsdb2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchsdb2_fck, gpio5_fck_parent_names, aes_ick_ops); - -DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, - OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -static struct clk mpu_wdt_fck; - -static struct clk_hw_omap mpu_wdt_fck_hw = { - .hw = { - .clk = &mpu_wdt_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(mpu_wdt_fck, gpio5_fck_parent_names, aes_ick_ops); - -static struct clk mpu_wdt_ick; - -static struct clk_hw_omap mpu_wdt_ick_hw = { - .hw = { - .clk = &mpu_wdt_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk mspro_fck; - -static struct clk_hw_omap mspro_fck_hw = { - .hw = { - .clk = &mspro_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk mspro_ick; - -static struct clk_hw_omap mspro_ick_hw = { - .hw = { - .clk = &mspro_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk omapctrl_ick; - -static struct clk_hw_omap omapctrl_ick_hw = { - .hw = { - .clk = &omapctrl_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk pka_ick; - -static struct clk_hw_omap pka_ick_hw = { - .hw = { - .clk = &pka_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_PKA_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk rng_ick; - -static struct clk_hw_omap rng_ick_hw = { - .hw = { - .clk = &rng_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_RNG_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk sdma_fck; - -DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); -DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); - -static struct clk sdma_ick; - -static struct clk_hw_omap sdma_ick_hw = { - .hw = { - .clk = &sdma_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); - -static struct clk sdrc_ick; - -static struct clk_hw_omap sdrc_ick_hw = { - .hw = { - .clk = &sdrc_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP2430_EN_SDRC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); - -static struct clk sha_ick; - -static struct clk_hw_omap sha_ick_hw = { - .hw = { - .clk = &sha_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_SHA_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk ssi_l4_ick; - -static struct clk_hw_omap ssi_l4_ick_hw = { - .hw = { - .clk = &ssi_l4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_SSI_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 5, .val = 5, .flags = RATE_IN_243X }, - { .div = 0 } -}; - -static const struct clksel ssi_ssr_sst_fck_clksel[] = { - { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *ssi_ssr_sst_fck_parent_names[] = { - "core_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", - ssi_ssr_sst_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_SSI_MASK, - OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, - ssi_ssr_sst_fck_parent_names, dsp_fck_ops); - -static struct clk sync_32k_ick; - -static struct clk_hw_omap sync_32k_ick_hw = { - .hw = { - .clk = &sync_32k_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate common_clkout_src_core_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_96m_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_54m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel common_clkout_src_clksel[] = { - { .parent = &core_ck, .rates = common_clkout_src_core_rates }, - { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, - { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, - { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, - { .parent = NULL }, -}; - -static const char *sys_clkout_src_parent_names[] = { - "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel, - OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK, - OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT, - NULL, sys_clkout_src_parent_names, gpt1_fck_ops); - -DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0, - OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT, - OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); - -static struct clk uart1_fck; - -static struct clk_hw_omap uart1_fck_hw = { - .hw = { - .clk = &uart1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_UART1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart1_ick; - -static struct clk_hw_omap uart1_ick_hw = { - .hw = { - .clk = &uart1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_UART1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk uart2_fck; - -static struct clk_hw_omap uart2_fck_hw = { - .hw = { - .clk = &uart2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_UART2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart2_ick; - -static struct clk_hw_omap uart2_ick_hw = { - .hw = { - .clk = &uart2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_UART2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk uart3_fck; - -static struct clk_hw_omap uart3_fck_hw = { - .hw = { - .clk = &uart3_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_UART3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart3_ick; - -static struct clk_hw_omap uart3_ick_hw = { - .hw = { - .clk = &uart3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_UART3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk usb_fck; - -static struct clk_hw_omap usb_fck_hw = { - .hw = { - .clk = &usb_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_USB_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel usb_l4_ick_clksel[] = { - { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, - { .parent = NULL }, -}; - -static const char *usb_l4_ick_parent_names[] = { - "core_l3_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_USB_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, - usb_l4_ick_parent_names, dsp_fck_ops); - -static struct clk usbhs_ick; - -static struct clk_hw_omap usbhs_ick_hw = { - .hw = { - .clk = &usbhs_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_USBHS_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(usbhs_ick, gfx_ick_parent_names, aes_ick_ops); - -static struct clk virt_prcm_set; - -static const char *virt_prcm_set_parent_names[] = { - "mpu_ck", -}; - -static const struct clk_ops virt_prcm_set_ops = { - .recalc_rate = &omap2_table_mpu_recalc, - .set_rate = &omap2_select_table_rate, - .round_rate = &omap2_round_to_table_rate, -}; - -DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL); -DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops); - -static struct clk wdt1_ick; - -static struct clk_hw_omap wdt1_ick_hw = { - .hw = { - .clk = &wdt1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_WDT1_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk wdt4_fck; - -static struct clk_hw_omap wdt4_fck_hw = { - .hw = { - .clk = &wdt4_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_WDT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt4_fck, gpio5_fck_parent_names, aes_ick_ops); - -static struct clk wdt4_ick; - -static struct clk_hw_omap wdt4_ick_hw = { - .hw = { - .clk = &wdt4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_WDT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); - -/* - * clkdev integration - */ - -static struct omap_clk omap2430_clks[] = { - /* external root sources */ - CLK(NULL, "func_32k_ck", &func_32k_ck), - CLK(NULL, "secure_32k_ck", &secure_32k_ck), - CLK(NULL, "virt_12m_ck", &virt_12m_ck), - CLK(NULL, "virt_13m_ck", &virt_13m_ck), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), - CLK(NULL, "virt_26m_ck", &virt_26m_ck), - CLK(NULL, "aplls_clkin_ck", &aplls_clkin_ck), - CLK(NULL, "aplls_clkin_x2_ck", &aplls_clkin_x2_ck), - CLK(NULL, "osc_ck", &osc_ck), - CLK("twl", "fck", &osc_ck), - CLK(NULL, "sys_ck", &sys_ck), - CLK(NULL, "alt_ck", &alt_ck), - CLK(NULL, "mcbsp_clks", &mcbsp_clks), - /* internal analog sources */ - CLK(NULL, "dpll_ck", &dpll_ck), - CLK(NULL, "apll96_ck", &apll96_ck), - CLK(NULL, "apll54_ck", &apll54_ck), - /* internal prcm root sources */ - CLK(NULL, "func_54m_ck", &func_54m_ck), - CLK(NULL, "core_ck", &core_ck), - CLK(NULL, "func_96m_ck", &func_96m_ck), - CLK(NULL, "func_48m_ck", &func_48m_ck), - CLK(NULL, "func_12m_ck", &func_12m_ck), - CLK(NULL, "sys_clkout_src", &sys_clkout_src), - CLK(NULL, "sys_clkout", &sys_clkout), - CLK(NULL, "emul_ck", &emul_ck), - /* mpu domain clocks */ - CLK(NULL, "mpu_ck", &mpu_ck), - /* dsp domain clocks */ - CLK(NULL, "dsp_fck", &dsp_fck), - CLK(NULL, "iva2_1_ick", &iva2_1_ick), - /* GFX domain clocks */ - CLK(NULL, "gfx_3d_fck", &gfx_3d_fck), - CLK(NULL, "gfx_2d_fck", &gfx_2d_fck), - CLK(NULL, "gfx_ick", &gfx_ick), - /* Modem domain clocks */ - CLK(NULL, "mdm_ick", &mdm_ick), - CLK(NULL, "mdm_osc_ck", &mdm_osc_ck), - /* DSS domain clocks */ - CLK("omapdss_dss", "ick", &dss_ick), - CLK(NULL, "dss_ick", &dss_ick), - CLK(NULL, "dss1_fck", &dss1_fck), - CLK(NULL, "dss2_fck", &dss2_fck), - CLK(NULL, "dss_54m_fck", &dss_54m_fck), - /* L3 domain clocks */ - CLK(NULL, "core_l3_ck", &core_l3_ck), - CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck), - CLK(NULL, "usb_l4_ick", &usb_l4_ick), - /* L4 domain clocks */ - CLK(NULL, "l4_ck", &l4_ck), - CLK(NULL, "ssi_l4_ick", &ssi_l4_ick), - /* virtual meta-group clock */ - CLK(NULL, "virt_prcm_set", &virt_prcm_set), - /* general l4 interface ck, multi-parent functional clk */ - CLK(NULL, "gpt1_ick", &gpt1_ick), - CLK(NULL, "gpt1_fck", &gpt1_fck), - CLK(NULL, "gpt2_ick", &gpt2_ick), - CLK(NULL, "gpt2_fck", &gpt2_fck), - CLK(NULL, "gpt3_ick", &gpt3_ick), - CLK(NULL, "gpt3_fck", &gpt3_fck), - CLK(NULL, "gpt4_ick", &gpt4_ick), - CLK(NULL, "gpt4_fck", &gpt4_fck), - CLK(NULL, "gpt5_ick", &gpt5_ick), - CLK(NULL, "gpt5_fck", &gpt5_fck), - CLK(NULL, "gpt6_ick", &gpt6_ick), - CLK(NULL, "gpt6_fck", &gpt6_fck), - CLK(NULL, "gpt7_ick", &gpt7_ick), - CLK(NULL, "gpt7_fck", &gpt7_fck), - CLK(NULL, "gpt8_ick", &gpt8_ick), - CLK(NULL, "gpt8_fck", &gpt8_fck), - CLK(NULL, "gpt9_ick", &gpt9_ick), - CLK(NULL, "gpt9_fck", &gpt9_fck), - CLK(NULL, "gpt10_ick", &gpt10_ick), - CLK(NULL, "gpt10_fck", &gpt10_fck), - CLK(NULL, "gpt11_ick", &gpt11_ick), - CLK(NULL, "gpt11_fck", &gpt11_fck), - CLK(NULL, "gpt12_ick", &gpt12_ick), - CLK(NULL, "gpt12_fck", &gpt12_fck), - CLK("omap-mcbsp.1", "ick", &mcbsp1_ick), - CLK(NULL, "mcbsp1_ick", &mcbsp1_ick), - CLK(NULL, "mcbsp1_fck", &mcbsp1_fck), - CLK("omap-mcbsp.2", "ick", &mcbsp2_ick), - CLK(NULL, "mcbsp2_ick", &mcbsp2_ick), - CLK(NULL, "mcbsp2_fck", &mcbsp2_fck), - CLK("omap-mcbsp.3", "ick", &mcbsp3_ick), - CLK(NULL, "mcbsp3_ick", &mcbsp3_ick), - CLK(NULL, "mcbsp3_fck", &mcbsp3_fck), - CLK("omap-mcbsp.4", "ick", &mcbsp4_ick), - CLK(NULL, "mcbsp4_ick", &mcbsp4_ick), - CLK(NULL, "mcbsp4_fck", &mcbsp4_fck), - CLK("omap-mcbsp.5", "ick", &mcbsp5_ick), - CLK(NULL, "mcbsp5_ick", &mcbsp5_ick), - CLK(NULL, "mcbsp5_fck", &mcbsp5_fck), - CLK("omap2_mcspi.1", "ick", &mcspi1_ick), - CLK(NULL, "mcspi1_ick", &mcspi1_ick), - CLK(NULL, "mcspi1_fck", &mcspi1_fck), - CLK("omap2_mcspi.2", "ick", &mcspi2_ick), - CLK(NULL, "mcspi2_ick", &mcspi2_ick), - CLK(NULL, "mcspi2_fck", &mcspi2_fck), - CLK("omap2_mcspi.3", "ick", &mcspi3_ick), - CLK(NULL, "mcspi3_ick", &mcspi3_ick), - CLK(NULL, "mcspi3_fck", &mcspi3_fck), - CLK(NULL, "uart1_ick", &uart1_ick), - CLK(NULL, "uart1_fck", &uart1_fck), - CLK(NULL, "uart2_ick", &uart2_ick), - CLK(NULL, "uart2_fck", &uart2_fck), - CLK(NULL, "uart3_ick", &uart3_ick), - CLK(NULL, "uart3_fck", &uart3_fck), - CLK(NULL, "gpios_ick", &gpios_ick), - CLK(NULL, "gpios_fck", &gpios_fck), - CLK("omap_wdt", "ick", &mpu_wdt_ick), - CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick), - CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck), - CLK(NULL, "sync_32k_ick", &sync_32k_ick), - CLK(NULL, "wdt1_ick", &wdt1_ick), - CLK(NULL, "omapctrl_ick", &omapctrl_ick), - CLK(NULL, "icr_ick", &icr_ick), - CLK("omap24xxcam", "fck", &cam_fck), - CLK(NULL, "cam_fck", &cam_fck), - CLK("omap24xxcam", "ick", &cam_ick), - CLK(NULL, "cam_ick", &cam_ick), - CLK(NULL, "mailboxes_ick", &mailboxes_ick), - CLK(NULL, "wdt4_ick", &wdt4_ick), - CLK(NULL, "wdt4_fck", &wdt4_fck), - CLK(NULL, "mspro_ick", &mspro_ick), - CLK(NULL, "mspro_fck", &mspro_fck), - CLK(NULL, "fac_ick", &fac_ick), - CLK(NULL, "fac_fck", &fac_fck), - CLK("omap_hdq.0", "ick", &hdq_ick), - CLK(NULL, "hdq_ick", &hdq_ick), - CLK("omap_hdq.1", "fck", &hdq_fck), - CLK(NULL, "hdq_fck", &hdq_fck), - CLK("omap_i2c.1", "ick", &i2c1_ick), - CLK(NULL, "i2c1_ick", &i2c1_ick), - CLK(NULL, "i2chs1_fck", &i2chs1_fck), - CLK("omap_i2c.2", "ick", &i2c2_ick), - CLK(NULL, "i2c2_ick", &i2c2_ick), - CLK(NULL, "i2chs2_fck", &i2chs2_fck), - CLK(NULL, "gpmc_fck", &gpmc_fck), - CLK(NULL, "sdma_fck", &sdma_fck), - CLK(NULL, "sdma_ick", &sdma_ick), - CLK(NULL, "sdrc_ick", &sdrc_ick), - CLK(NULL, "des_ick", &des_ick), - CLK("omap-sham", "ick", &sha_ick), - CLK(NULL, "sha_ick", &sha_ick), - CLK("omap_rng", "ick", &rng_ick), - CLK(NULL, "rng_ick", &rng_ick), - CLK("omap-aes", "ick", &aes_ick), - CLK(NULL, "aes_ick", &aes_ick), - CLK(NULL, "pka_ick", &pka_ick), - CLK(NULL, "usb_fck", &usb_fck), - CLK("musb-omap2430", "ick", &usbhs_ick), - CLK(NULL, "usbhs_ick", &usbhs_ick), - CLK("omap_hsmmc.0", "ick", &mmchs1_ick), - CLK(NULL, "mmchs1_ick", &mmchs1_ick), - CLK(NULL, "mmchs1_fck", &mmchs1_fck), - CLK("omap_hsmmc.1", "ick", &mmchs2_ick), - CLK(NULL, "mmchs2_ick", &mmchs2_ick), - CLK(NULL, "mmchs2_fck", &mmchs2_fck), - CLK(NULL, "gpio5_ick", &gpio5_ick), - CLK(NULL, "gpio5_fck", &gpio5_fck), - CLK(NULL, "mdm_intc_ick", &mdm_intc_ick), - CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck), - CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck), - CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck), - CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck), - CLK(NULL, "timer_32k_ck", &func_32k_ck), - CLK(NULL, "timer_sys_ck", &sys_ck), - CLK(NULL, "timer_ext_ck", &alt_ck), - CLK(NULL, "cpufreq_ck", &virt_prcm_set), -}; - -static const char *enable_init_clks[] = { - "apll96_ck", - "apll54_ck", - "sync_32k_ick", - "omapctrl_ick", - "gpmc_fck", - "sdrc_ick", -}; - -/* - * init code - */ - -int __init omap2430_clk_init(void) -{ - cpu_mask = RATE_IN_243X; - rate_table = omap2430_rate_table; - - omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw); - - omap2xxx_clkt_vps_check_bootloader_rates(); - - omap_clocks_register(omap2430_clks, ARRAY_SIZE(omap2430_clks)); - - omap2xxx_clkt_vps_late_init(); - - omap2_clk_disable_autoidle_all(); - - omap2_clk_enable_init_clocks(enable_init_clks, - ARRAY_SIZE(enable_init_clks)); - - pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(&sys_ck) / 1000000), - (clk_get_rate(&sys_ck) / 100000) % 10, - (clk_get_rate(&dpll_ck) / 1000000), - (clk_get_rate(&mpu_ck) / 1000000)); - - return 0; -} diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 80bf633..1271fe9 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -411,12 +411,8 @@ void __init omap2420_init_early(void) omap242x_clockdomains_init(); omap2420_hwmod_init(); omap_hwmod_init_postsetup(); - if (of_have_populated_dt()) { - omap_clk_soc_init = omap2420_dt_clk_init; - rate_table = omap2420_rate_table; - } else { - omap_clk_soc_init = omap2420_clk_init; - } + omap_clk_soc_init = omap2420_dt_clk_init; + rate_table = omap2420_rate_table; } void __init omap2420_init_late(void) @@ -445,12 +441,8 @@ void __init omap2430_init_early(void) omap243x_clockdomains_init(); omap2430_hwmod_init(); omap_hwmod_init_postsetup(); - if (of_have_populated_dt()) { - omap_clk_soc_init = omap2430_dt_clk_init; - rate_table = omap2430_rate_table; - } else { - omap_clk_soc_init = omap2430_clk_init; - } + omap_clk_soc_init = omap2430_dt_clk_init; + rate_table = omap2430_rate_table; } void __init omap2430_init_late(void) -- cgit v0.10.2 From 513006334fb01c7c19b5e005357d94de43a370dd Mon Sep 17 00:00:00 2001 From: R Sricharan Date: Thu, 26 Jun 2014 12:55:30 +0530 Subject: ARM: dts: dra7: add routable-irqs property for gic node There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Signed-off-by: Sricharan R Signed-off-by: Nishanth Menon Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c29945e..1cf4ee1 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -45,6 +45,7 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; + arm,routable-irqs = <192>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>, <0x48214000 0x2000>, -- cgit v0.10.2 From a46631c4cda1488a69600efb93f38d84b7a57541 Mon Sep 17 00:00:00 2001 From: R Sricharan Date: Thu, 26 Jun 2014 12:55:31 +0530 Subject: ARM: dts: dra7: add crossbar device binding There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The Peripheral irq requests are connected to only one crossbar input and the output of the crossbar is connected to only one controller's input line. The crossbar device is used to map a peripheral input to a free mpu's interrupt controller line. Here, adding a new crossbar device node and replacing all the peripheral interrupt numbers with its fixed crossbar input lines. Signed-off-by: Sricharan R Signed-off-by: Nishanth Menon Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 1cf4ee1..961be6b 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -12,6 +12,9 @@ #include "skeleton.dtsi" +#define MAX_SOURCES 400 +#define DIRECT_IRQ(irq) (MAX_SOURCES + irq) + / { #address-cells = <1>; #size-cells = <1>; @@ -80,8 +83,8 @@ ti,hwmods = "l3_main_1", "l3_main_2"; reg = <0x44000000 0x1000000>, <0x45000000 0x1000>; - interrupts = , - ; + interrupts = , + ; prm: prm@4ae06000 { compatible = "ti,dra7-prm"; @@ -156,10 +159,10 @@ sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; #dma-cells = <1>; #dma-channels = <32>; #dma-requests = <127>; @@ -168,7 +171,7 @@ gpio1: gpio@4ae10000 { compatible = "ti,omap4-gpio"; reg = <0x4ae10000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio1"; gpio-controller; #gpio-cells = <2>; @@ -179,7 +182,7 @@ gpio2: gpio@48055000 { compatible = "ti,omap4-gpio"; reg = <0x48055000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>; @@ -190,7 +193,7 @@ gpio3: gpio@48057000 { compatible = "ti,omap4-gpio"; reg = <0x48057000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>; @@ -201,7 +204,7 @@ gpio4: gpio@48059000 { compatible = "ti,omap4-gpio"; reg = <0x48059000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>; @@ -212,7 +215,7 @@ gpio5: gpio@4805b000 { compatible = "ti,omap4-gpio"; reg = <0x4805b000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio5"; gpio-controller; #gpio-cells = <2>; @@ -223,7 +226,7 @@ gpio6: gpio@4805d000 { compatible = "ti,omap4-gpio"; reg = <0x4805d000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio6"; gpio-controller; #gpio-cells = <2>; @@ -234,7 +237,7 @@ gpio7: gpio@48051000 { compatible = "ti,omap4-gpio"; reg = <0x48051000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio7"; gpio-controller; #gpio-cells = <2>; @@ -245,7 +248,7 @@ gpio8: gpio@48053000 { compatible = "ti,omap4-gpio"; reg = <0x48053000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio8"; gpio-controller; #gpio-cells = <2>; @@ -256,7 +259,7 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; reg = <0x4806a000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart1"; clock-frequency = <48000000>; status = "disabled"; @@ -265,7 +268,7 @@ uart2: serial@4806c000 { compatible = "ti,omap4-uart"; reg = <0x4806c000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart2"; clock-frequency = <48000000>; status = "disabled"; @@ -274,7 +277,7 @@ uart3: serial@48020000 { compatible = "ti,omap4-uart"; reg = <0x48020000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart3"; clock-frequency = <48000000>; status = "disabled"; @@ -283,7 +286,7 @@ uart4: serial@4806e000 { compatible = "ti,omap4-uart"; reg = <0x4806e000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart4"; clock-frequency = <48000000>; status = "disabled"; @@ -292,7 +295,7 @@ uart5: serial@48066000 { compatible = "ti,omap4-uart"; reg = <0x48066000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart5"; clock-frequency = <48000000>; status = "disabled"; @@ -301,7 +304,7 @@ uart6: serial@48068000 { compatible = "ti,omap4-uart"; reg = <0x48068000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart6"; clock-frequency = <48000000>; status = "disabled"; @@ -310,6 +313,7 @@ uart7: serial@48420000 { compatible = "ti,omap4-uart"; reg = <0x48420000 0x100>; + interrupts = ; ti,hwmods = "uart7"; clock-frequency = <48000000>; status = "disabled"; @@ -318,6 +322,7 @@ uart8: serial@48422000 { compatible = "ti,omap4-uart"; reg = <0x48422000 0x100>; + interrupts = ; ti,hwmods = "uart8"; clock-frequency = <48000000>; status = "disabled"; @@ -326,6 +331,7 @@ uart9: serial@48424000 { compatible = "ti,omap4-uart"; reg = <0x48424000 0x100>; + interrupts = ; ti,hwmods = "uart9"; clock-frequency = <48000000>; status = "disabled"; @@ -334,6 +340,7 @@ uart10: serial@4ae2b000 { compatible = "ti,omap4-uart"; reg = <0x4ae2b000 0x100>; + interrupts = ; ti,hwmods = "uart10"; clock-frequency = <48000000>; status = "disabled"; @@ -342,7 +349,7 @@ timer1: timer@4ae18000 { compatible = "ti,omap5430-timer"; reg = <0x4ae18000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer1"; ti,timer-alwon; }; @@ -350,28 +357,28 @@ timer2: timer@48032000 { compatible = "ti,omap5430-timer"; reg = <0x48032000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer2"; }; timer3: timer@48034000 { compatible = "ti,omap5430-timer"; reg = <0x48034000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer3"; }; timer4: timer@48036000 { compatible = "ti,omap5430-timer"; reg = <0x48036000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer4"; }; timer5: timer@48820000 { compatible = "ti,omap5430-timer"; reg = <0x48820000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer5"; ti,timer-dsp; }; @@ -379,7 +386,7 @@ timer6: timer@48822000 { compatible = "ti,omap5430-timer"; reg = <0x48822000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer6"; ti,timer-dsp; ti,timer-pwm; @@ -388,7 +395,7 @@ timer7: timer@48824000 { compatible = "ti,omap5430-timer"; reg = <0x48824000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer7"; ti,timer-dsp; }; @@ -396,7 +403,7 @@ timer8: timer@48826000 { compatible = "ti,omap5430-timer"; reg = <0x48826000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer8"; ti,timer-dsp; ti,timer-pwm; @@ -405,21 +412,21 @@ timer9: timer@4803e000 { compatible = "ti,omap5430-timer"; reg = <0x4803e000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer9"; }; timer10: timer@48086000 { compatible = "ti,omap5430-timer"; reg = <0x48086000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer10"; }; timer11: timer@48088000 { compatible = "ti,omap5430-timer"; reg = <0x48088000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer11"; ti,timer-pwm; }; @@ -427,6 +434,7 @@ timer13: timer@48828000 { compatible = "ti,omap5430-timer"; reg = <0x48828000 0x80>; + interrupts = ; ti,hwmods = "timer13"; status = "disabled"; }; @@ -434,6 +442,7 @@ timer14: timer@4882a000 { compatible = "ti,omap5430-timer"; reg = <0x4882a000 0x80>; + interrupts = ; ti,hwmods = "timer14"; status = "disabled"; }; @@ -441,6 +450,7 @@ timer15: timer@4882c000 { compatible = "ti,omap5430-timer"; reg = <0x4882c000 0x80>; + interrupts = ; ti,hwmods = "timer15"; status = "disabled"; }; @@ -448,6 +458,7 @@ timer16: timer@4882e000 { compatible = "ti,omap5430-timer"; reg = <0x4882e000 0x80>; + interrupts = ; ti,hwmods = "timer16"; status = "disabled"; }; @@ -455,7 +466,7 @@ wdt2: wdt@4ae14000 { compatible = "ti,omap4-wdt"; reg = <0x4ae14000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "wd_timer2"; }; @@ -469,14 +480,14 @@ dmm@4e000000 { compatible = "ti,omap5-dmm"; reg = <0x4e000000 0x800>; - interrupts = <0 113 0x4>; + interrupts = ; ti,hwmods = "dmm"; }; i2c1: i2c@48070000 { compatible = "ti,omap4-i2c"; reg = <0x48070000 0x100>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; @@ -486,7 +497,7 @@ i2c2: i2c@48072000 { compatible = "ti,omap4-i2c"; reg = <0x48072000 0x100>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; @@ -496,7 +507,7 @@ i2c3: i2c@48060000 { compatible = "ti,omap4-i2c"; reg = <0x48060000 0x100>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; @@ -506,7 +517,7 @@ i2c4: i2c@4807a000 { compatible = "ti,omap4-i2c"; reg = <0x4807a000 0x100>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c4"; @@ -516,7 +527,7 @@ i2c5: i2c@4807c000 { compatible = "ti,omap4-i2c"; reg = <0x4807c000 0x100>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c5"; @@ -526,7 +537,7 @@ mmc1: mmc@4809c000 { compatible = "ti,omap4-hsmmc"; reg = <0x4809c000 0x400>; - interrupts = ; + interrupts = ; ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset; @@ -539,7 +550,7 @@ mmc2: mmc@480b4000 { compatible = "ti,omap4-hsmmc"; reg = <0x480b4000 0x400>; - interrupts = ; + interrupts = ; ti,hwmods = "mmc2"; ti,needs-special-reset; dmas = <&sdma 47>, <&sdma 48>; @@ -550,7 +561,7 @@ mmc3: mmc@480ad000 { compatible = "ti,omap4-hsmmc"; reg = <0x480ad000 0x400>; - interrupts = ; + interrupts = ; ti,hwmods = "mmc3"; ti,needs-special-reset; dmas = <&sdma 77>, <&sdma 78>; @@ -561,7 +572,7 @@ mmc4: mmc@480d1000 { compatible = "ti,omap4-hsmmc"; reg = <0x480d1000 0x400>; - interrupts = ; + interrupts = ; ti,hwmods = "mmc4"; ti,needs-special-reset; dmas = <&sdma 57>, <&sdma 58>; @@ -704,7 +715,7 @@ mcspi1: spi@48098000 { compatible = "ti,omap4-mcspi"; reg = <0x48098000 0x200>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi1"; @@ -725,7 +736,7 @@ mcspi2: spi@4809a000 { compatible = "ti,omap4-mcspi"; reg = <0x4809a000 0x200>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi2"; @@ -741,7 +752,7 @@ mcspi3: spi@480b8000 { compatible = "ti,omap4-mcspi"; reg = <0x480b8000 0x200>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi3"; @@ -754,7 +765,7 @@ mcspi4: spi@480ba000 { compatible = "ti,omap4-mcspi"; reg = <0x480ba000 0x200>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi4"; @@ -774,7 +785,7 @@ clocks = <&qspi_gfclk_div>; clock-names = "fck"; num-cs = <4>; - interrupts = <0 343 0x4>; + interrupts = ; status = "disabled"; }; @@ -810,7 +821,7 @@ sata: sata@4a141100 { compatible = "snps,dwc-ahci"; reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; - interrupts = ; + interrupts = ; phys = <&sata_phy>; phy-names = "sata-phy"; clocks = <&sata_ref_clk>; @@ -887,7 +898,7 @@ compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss1"; reg = <0x48880000 0x10000>; - interrupts = <0 77 4>; + interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; @@ -895,7 +906,7 @@ usb1: usb@48890000 { compatible = "snps,dwc3"; reg = <0x48890000 0x17000>; - interrupts = <0 76 4>; + interrupts = ; phys = <&usb2_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; tx-fifo-resize; @@ -908,7 +919,7 @@ compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss2"; reg = <0x488c0000 0x10000>; - interrupts = <0 92 4>; + interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; @@ -916,7 +927,7 @@ usb2: usb@488d0000 { compatible = "snps,dwc3"; reg = <0x488d0000 0x17000>; - interrupts = <0 78 4>; + interrupts = ; phys = <&usb2_phy2>; phy-names = "usb2-phy"; tx-fifo-resize; @@ -930,7 +941,7 @@ compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss3"; reg = <0x48900000 0x10000>; - /* interrupts = <0 TBD 4>; */ + interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; @@ -939,7 +950,7 @@ usb3: usb@48910000 { compatible = "snps,dwc3"; reg = <0x48910000 0x17000>; - /* interrupts = <0 93 4>; */ + interrupts = ; tx-fifo-resize; maximum-speed = "high-speed"; dr_mode = "otg"; @@ -950,7 +961,7 @@ compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss4"; reg = <0x48940000 0x10000>; - /* interrupts = <0 TBD 4>; */ + interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; @@ -959,7 +970,7 @@ usb4: usb@48950000 { compatible = "snps,dwc3"; reg = <0x48950000 0x17000>; - /* interrupts = <0 TBD 4>; */ + interrupts = ; tx-fifo-resize; maximum-speed = "high-speed"; dr_mode = "otg"; @@ -969,7 +980,7 @@ elm: elm@48078000 { compatible = "ti,am3352-elm"; reg = <0x48078000 0xfc0>; /* device IO registers */ - interrupts = ; + interrupts = ; ti,hwmods = "elm"; status = "disabled"; }; @@ -978,13 +989,24 @@ compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; reg = <0x50000000 0x37c>; /* device IO registers */ - interrupts = ; + interrupts = ; gpmc,num-cs = <8>; gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; status = "disabled"; }; + + crossbar_mpu: crossbar@4a020000 { + compatible = "ti,irq-crossbar"; + reg = <0x4a002a48 0x130>; + ti,max-irqs = <160>; + ti,max-crossbar-sources = ; + ti,reg-size = <2>; + ti,irqs-reserved = <0 1 2 3 5 6 131 132>; + ti,irqs-skip = <10 133 139 140>; + ti,irqs-safe-map = <0>; + }; }; }; -- cgit v0.10.2 From 4341881d0562309ca9fd5e0bc5a2a85f2945f74a Mon Sep 17 00:00:00 2001 From: Ash Charles Date: Tue, 10 Jun 2014 15:22:00 -0700 Subject: ARM: dts: Add devicetree for Gumstix Pepper board This adds the Gumstix Pepper[1] single-board computer based on the TI AM335x processor. Schematics are available [2]. [1] https://store.gumstix.com/index.php/products/344/ [2] https://pubs.gumstix.com/boards/PEPPER/ Signed-off-by: Ash Charles Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 63d1e53..b19f0c8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -291,7 +291,8 @@ dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \ am335x-boneblack.dtb \ am335x-evm.dtb \ am335x-evmsk.dtb \ - am335x-nano.dtb + am335x-nano.dtb \ + am335x-pepper.dtb dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \ omap4-panda.dtb \ omap4-panda-a4.dtb \ diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts new file mode 100644 index 0000000..0d35ab6 --- /dev/null +++ b/arch/arm/boot/dts/am335x-pepper.dts @@ -0,0 +1,653 @@ +/* + * Copyright (C) 2014 Gumstix, Inc. - https://www.gumstix.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include +#include "am33xx.dtsi" + +/ { + model = "Gumstix Pepper"; + compatible = "gumstix,am335x-pepper", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc3_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + buttons: user_buttons { + compatible = "gpio-keys"; + }; + + leds: user_leds { + compatible = "gpio-leds"; + }; + + panel: lcd_panel { + compatible = "ti,tilcdc,panel"; + }; + + sound: sound_iface { + compatible = "ti,da830-evm-audio"; + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + }; + + v3v3c_reg: fixedregulator@1 { + compatible = "regulator-fixed"; + }; + + vdd5_reg: fixedregulator@2 { + compatible = "regulator-fixed"; + }; +}; + +/* I2C Busses */ +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + + eeprom: eeprom@50 { + compatible = "at,24c256"; + reg = <0x50>; + }; + + audio_codec: tlv320aic3106@1b { + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + }; + + accel: lis331dlh@1d { + compatible = "st,lis3lv02d"; + reg = <0x1d>; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; +}; + +&am33xx_pinmux { + i2c0_pins: pinmux_i2c0 { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + i2c1_pins: pinmux_i2c1 { + pinctrl-single,pins = < + 0x10C (PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_crs,i2c1_sda */ + 0x110 (PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_rxerr,i2c1_scl */ + >; + }; +}; + +/* Accelerometer */ +&accel { + pinctrl-names = "default"; + pinctrl-0 = <&accel_pins>; + + Vdd-supply = <&ldo3_reg>; + Vdd_IO-supply = <&ldo3_reg>; + st,irq1-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <92>; + st,max-limit-x = <14>; + st,min-limit-y = <14>; + st,max-limit-y = <92>; + st,min-limit-z = <92>; + st,max-limit-z = <14>; +}; + +&am33xx_pinmux { + accel_pins: pinmux_accel { + pinctrl-single,pins = < + 0x98 (PIN_INPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */ + >; + }; +}; + +/* Audio */ +&audio_codec { + status = "okay"; + + gpio-reset = <&gpio1 16 GPIO_ACTIVE_LOW>; + AVDD-supply = <&ldo3_reg>; + IOVDD-supply = <&ldo3_reg>; + DRVDD-supply = <&ldo3_reg>; + DVDD-supply = <&dcdc1_reg>; +}; + +&sound { + ti,model = "AM335x-EVM"; + ti,audio-codec = <&audio_codec>; + ti,mcasp-controller = <&mcasp0>; + ti,codec-clock-rate = <12000000>; + ti,audio-routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In"; +}; + +&mcasp0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; + + op-mode = <0>; /* MCASP_ISS_MODE */ + tdm-slots = <2>; + serial-dir = < + 1 2 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <1>; + rx-num-evt = <1>; +}; + +&am33xx_pinmux { + audio_pins: pinmux_audio { + pinctrl-single,pins = < + 0x1AC (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ + 0x194 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ + 0x190 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ + 0x198 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ + 0x1A8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */ + 0x40 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a0.gpio1_16 */ + >; + }; +}; + +/* Display: 24-bit LCD Screen */ +&panel { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <32>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + display-timings { + native-mode = <&timing0>; + timing0: 480x272 { + clock-frequency = <18400000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vfront-porch = <4>; + vback-porch = <2>; + vsync-len = <10>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; +}; + +&lcdc { + status = "okay"; +}; + +&am33xx_pinmux { + lcd_pins: pinmux_lcd { + pinctrl-single,pins = < + 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data16 */ + 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data17 */ + 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data18 */ + 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data19 */ + 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data20 */ + 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data21 */ + 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data22 */ + 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data23 */ + 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + /* Display Enable */ + 0x6c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a11.gpio1_27 */ + >; + }; +}; + +/* Ethernet */ +&cpsw_emac0 { + status = "okay"; + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rgmii"; +}; + +&cpsw_emac1 { + status = "okay"; + phy_id = <&davinci_mdio>, <1>; + phy-mode = "rgmii"; +}; + +&davinci_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; +}; + +&mac { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_pins>; +}; + + +&am33xx_pinmux { + ethernet_pins: pinmux_ethernet { + pinctrl-single,pins = < + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + 0x118 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + 0x12c (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + 0x130 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + 0x134 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd3.rgmii1_rxd3 */ + 0x138 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd2.rgmii1_rxd2 */ + 0x13c (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ + 0x140 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ + /* ethernet interrupt */ + 0x144 (PIN_INPUT_PULLUP | MUX_MODE7) /* rmii2_refclk.gpio0_29 */ + /* ethernet PHY nReset */ + 0x108 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mii1_col.gpio3_0 */ + >; + }; + + mdio_pins: pinmux_mdio { + pinctrl-single,pins = < + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; +}; + +/* MMC */ +&mmc1 { + /* Bootable SD card slot */ + status = "okay"; + vmmc-supply = <&ldo3_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&mmc2 { + /* eMMC (not populated) on MMC #2 */ + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + vmmc-supply = <&ldo3_reg>; + bus-width = <8>; + ti,non-removable; +}; + +&edma { + /* Map eDMA MMC2 Events from Crossbar */ + ti,edma-xbar-event-map = /bits/ 16 <1 12 + 2 13>; +}; + + +&mmc3 { + /* Wifi & Bluetooth on MMC #3 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wireless_pins>; + vmmmc-supply = <&v3v3c_reg>; + bus-width = <4>; + ti,non-removable; + dmas = <&edma 12 + &edma 13>; + dma-names = "tx", "rx"; +}; + + +&am33xx_pinmux { + sd_pins: pinmux_sd_card { + pinctrl-single,pins = < + 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + 0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + 0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + 0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + emmc_pins: pinmux_emmc { + pinctrl-single,pins = < + 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + /* EMMC nReset */ + 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + >; + }; + wireless_pins: pinmux_wireless { + pinctrl-single,pins = < + 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ + 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ + 0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ + 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3 */ + 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ + 0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc1_clk */ + /* WLAN nReset */ + 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + /* WLAN nPower down */ + 0x70 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ + /* 32kHz Clock */ + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; +}; + +/* Power */ +&vbat { + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; +}; + +&v3v3c_reg { + regulator-name = "v3v3c_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vbat>; +}; + +&vdd5_reg { + regulator-name = "vdd5_reg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbat>; +}; + +/include/ "tps65217.dtsi" + +&tps { + backlight { + isel = <1>; /* ISET1 */ + fdim = <200>; /* TPS65217_BL_FDIM_200HZ */ + default-brightness = <80>; + }; + + regulators { + dcdc1_reg: regulator@0 { + /* VDD_1V8 system supply */ + }; + + dcdc2_reg: regulator@1 { + /* VDD_CORE voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + }; + + ldo1_reg: regulator@3 { + /* VRTC 1.8V always-on supply */ + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + /* 3.3V rail */ + }; + + ldo3_reg: regulator@5 { + /* VDD_3V3A 3.3V rail */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo4_reg: regulator@6 { + /* VDD_3V3B 3.3V rail */ + }; + }; +}; + +/* SPI Busses */ +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; +}; + +&am33xx_pinmux { + spi0_pins: pinmux_spi0 { + pinctrl-single,pins = < + 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */ + 0x15C (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */ + 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ + >; + }; +}; + +/* Touch Screen */ +&tscadc { + status = "okay"; + tsc { + ti,wires = <4>; + ti,x-plate-resistance = <200>; + ti,coordinate-readouts = <5>; + ti,wire-config = <0x00 0x11 0x22 0x33>; + }; + + adc { + ti,adc-channels = <4 5 6 7>; + }; +}; + +/* UARTs */ +&uart0 { + /* Serial Console */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart1 { + /* Broken out to J6 header */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&am33xx_pinmux { + uart0_pins: pinmux_uart0 { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + uart1_pins: pinmux_uart1 { + pinctrl-single,pins = < + 0x178 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ + 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ + 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ + 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ + >; + }; +}; + +/* USB */ +&usb { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins>; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +&am33xx_pinmux { + usb_pins: pinmux_usb { + pinctrl-single,pins = < + /* USB0 Over-Current (active low) */ + 0x64 (PIN_INPUT | MUX_MODE7) /* gpmc_a9.gpio1_25 */ + /* USB1 Over-Current (active low) */ + 0x68 (PIN_INPUT | MUX_MODE7) /* gpmc_a10.gpio1_26 */ + >; + }; +}; + +/* User IO */ +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_pins>; + + led@0 { + label = "pepper:user0:blue"; + gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + }; + + led@1 { + label = "pepper:user1:red"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + }; +}; + +&buttons { + pinctrl-names = "default"; + pinctrl-0 = <&user_buttons_pins>; + #address-cells = <1>; + #size-cells = <0>; + + button@0 { + label = "home"; + linux,code = ; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + }; + + button@1 { + label = "menu"; + linux,code = ; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + }; + + buttons@2 { + label = "power"; + linux,code = ; + gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + }; +}; + +&am33xx_pinmux { + user_leds_pins: pinmux_user_leds { + pinctrl-single,pins = < + 0x50 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a4.gpio1_20 */ + 0x54 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */ + >; + }; + + user_buttons_pins: pinmux_user_buttons { + pinctrl-single,pins = < + 0x58 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ + 0x5C (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a7.gpio1_21 */ + 0x164 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio0_7 */ + >; + }; +}; -- cgit v0.10.2 From 497d64a34bbd7fad024c38c4a0efaa2d92664ca1 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 9 Jul 2014 11:06:30 +0530 Subject: ARM: dts: AM43x: Add TPS65218 device tree nodes Add TPS65218 device tree nodes. i2c clock frequency setting also added as part of tps65218 nodes addition. As i2c clock enabling is required. Signed-off-by: Keerthy Reviewed-by: Felipe Balbi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 19f1f7e..11ffb50 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -323,6 +323,65 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + + tps65218: tps65218@24 { + reg = <0x24>; + compatible = "ti,tps65218"; + interrupts = ; /* NMIn */ + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + compatible = "ti,tps65218-dcdc1"; + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + compatible = "ti,tps65218-dcdc2"; + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + compatible = "ti,tps65218-dcdc3"; + regulator-name = "vdcdc3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc5: regulator-dcdc5 { + compatible = "ti,tps65218-dcdc5"; + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + dcdc6: regulator-dcdc6 { + compatible = "ti,tps65218-dcdc6"; + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,tps65218-ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; at24@50 { compatible = "at24,24c256"; -- cgit v0.10.2 From 1fc98144cd7325af8a7d6325776bbb71b1c17c3b Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 9 Jul 2014 11:06:31 +0530 Subject: ARM: dts: AM437x: Fix i2c nodes indentation Fix i2c nodes indentation. Signed-off-by: Keerthy Reviewed-by: Felipe Balbi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 003766c..85ca430 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -257,16 +257,15 @@ }; &i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; }; &i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; pixcir_ts@5c { compatible = "pixcir,pixcir_tangoc"; pinctrl-names = "default"; -- cgit v0.10.2 From 0e2da5e661002330dee480731d8877d5c342ac65 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 9 Jul 2014 11:06:32 +0530 Subject: ARM: dts: AM437x: Add TPS65218 device tree nodes Add TPS65218 device tree nodes. i2c clock frequency setting also added as part of tps65218 nodes addition. As i2c clock enabling is required. Signed-off-by: Keerthy Reviewed-by: Felipe Balbi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 85ca430..f0422c2 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -260,6 +260,64 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + + tps65218: tps65218@24 { + reg = <0x24>; + compatible = "ti,tps65218"; + interrupts = ; /* NMIn */ + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + compatible = "ti,tps65218-dcdc1"; + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + compatible = "ti,tps65218-dcdc2"; + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + compatible = "ti,tps65218-dcdc3"; + regulator-name = "vdcdc3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + dcdc5: regulator-dcdc5 { + compatible = "ti,tps65218-dcdc5"; + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + dcdc6: regulator-dcdc6 { + compatible = "ti,tps65218-dcdc6"; + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,tps65218-ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; }; &i2c1 { -- cgit v0.10.2 From a186cf10da84a50358f813de0edebf45ddadf624 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 9 Jul 2014 11:06:33 +0530 Subject: ARM: omap2plus_defconfig: enable TPS65218 configs Enable TPS65218 config options. Signed-off-by: Keerthy Acked-by: Felipe Balbi Signed-off-by: Tony Lindgren diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 59066cf..2b53efa 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -179,6 +179,7 @@ CONFIG_TWL4030_WATCHDOG=y CONFIG_MFD_SYSCON=y CONFIG_MFD_PALMAS=y CONFIG_MFD_TPS65217=y +CONFIG_MFD_TPS65218=y CONFIG_MFD_TPS65910=y CONFIG_TWL6040_CORE=y CONFIG_REGULATOR_FIXED_VOLTAGE=y @@ -187,6 +188,7 @@ CONFIG_REGULATOR_TI_ABB=y CONFIG_REGULATOR_TPS65023=y CONFIG_REGULATOR_TPS6507X=y CONFIG_REGULATOR_TPS65217=y +CONFIG_REGULATOR_TPS65218=y CONFIG_REGULATOR_TPS65910=y CONFIG_REGULATOR_TWL4030=y CONFIG_REGULATOR_PBIAS=y -- cgit v0.10.2 From ae28ea88a38decac2a0dc1abc23936e59a08b6f3 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 30 Jun 2014 14:00:38 +0300 Subject: ARM: dts: dra7-evm: Add regulator information to USB2 PHYs The ldousb_reg regulator provides power to the USB1 and USB2 High Speed PHYs. Signed-off-by: Roger Quadros Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 4adc280..fd96ced 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -495,3 +495,11 @@ }; }; }; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldousb_reg>; +}; -- cgit v0.10.2 From 147e5413696c3d385283ceda73efb2b098657477 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Mon, 14 Jul 2014 16:12:16 +0530 Subject: ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div clock Add divider table to optfclk_pciephy_div clock. The 8th bit of CM_CLKMODE_APLL_PCIE can be programmed to either 0x0 or 0x1 based on if the divider value is 0x2 or 0x1. Figure 26-21. PCIe PHY Clock Generator Overview in vE of DRA7xx ES1.0 shows the block diagram of Clock Generator Subsystem of PCIe PHY module. The divider value if '1' should be programmed in order to get the correct PCIE_PHY_DIV_GCLK frequency (2.5GHz). Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Signed-off-by: Keerthy Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index b03cfe4..7148e7c 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1170,6 +1170,7 @@ clocks = <&apll_pcie_ck>; #clock-cells = <0>; reg = <0x021c>; + ti,dividers = <2>, <1>; ti,bit-shift = <8>; ti,max-div = <2>; }; -- cgit v0.10.2 From 4310e90847f18e09559b65c1897e5a88313e3fea Mon Sep 17 00:00:00 2001 From: Keerthy Date: Mon, 14 Jul 2014 16:12:17 +0530 Subject: ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck from dpll_pcie_ref_ck. Figure 26-22. DPLL_PCIE_REF Functional Block Diagram in vE of DRA7xx ES1.0 TRM shows the signal name for the output of post divider (M2) is CLKOUTLDO. Figure 26-21. PCIe PHY Clock Generator Overview shows CLKOUTLDO is used as input to apll mux. So the actual output of dpll is dpll_pcie_ref_m2ldo_ck which is also the input of apll. Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Signed-off-by: Keerthy Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 7148e7c..f5dca1f 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1152,7 +1152,7 @@ apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { compatible = "ti,mux-clock"; - clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>; + clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; #clock-cells = <0>; reg = <0x021c 0x4>; ti,bit-shift = <7>; -- cgit v0.10.2 From ba5137b27281f9016a5b2f6177f02595252305bd Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Jul 2014 16:12:18 +0530 Subject: ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY Added missing 32KHz clock used by PCIe PHY. Figure 26-19. PCIe PHY Subsystem Integration in vE of DRA7xx ES1.0 TRM shows 32KHz is used by PCIe PHY. Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index f5dca1f..3ff6d7c 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1165,6 +1165,14 @@ reg = <0x021c>, <0x0220>; }; + optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 { + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + #clock-cells = <0>; + reg = <0x13b0>; + ti,bit-shift = <8>; + }; + optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { compatible = "ti,divider-clock"; clocks = <&apll_pcie_ck>; -- cgit v0.10.2 From b700f42c863e17569ca4d864e369210d9ff00b8a Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Jul 2014 16:12:19 +0530 Subject: ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance There are two instances of PCIe PHY in DRA7xx. So renamed optfclk_pciephy_32khz, optfclk_pciephy_clk and optfclk_pciephy_div_clk to optfclk_pciephy1_32khz, optfclk_pciephy1_clk and optfclk_pciephy1_div_clk respectively. This is needed for adding the clocks for second PCIe PHY instance. Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Keerthy Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 3ff6d7c..fe5db55 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1165,7 +1165,7 @@ reg = <0x021c>, <0x0220>; }; - optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 { + optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 { compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; #clock-cells = <0>; @@ -1183,7 +1183,7 @@ ti,max-div = <2>; }; - optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 { + optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 { compatible = "ti,gate-clock"; clocks = <&apll_pcie_ck>; #clock-cells = <0>; @@ -1191,7 +1191,7 @@ ti,bit-shift = <9>; }; - optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 { + optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 { compatible = "ti,gate-clock"; clocks = <&optfclk_pciephy_div>; #clock-cells = <0>; -- cgit v0.10.2 From 00b0af5b68fc8bde724f7d491099179253bc4da8 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Jul 2014 16:12:20 +0530 Subject: ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance Added missing clocks used by second instance of PCIe PHY. The documention for this nodes can be found @ ../bindings/clock/ti/gate.txt. Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index fe5db55..b48f18b 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1173,6 +1173,14 @@ ti,bit-shift = <8>; }; + optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 { + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + #clock-cells = <0>; + reg = <0x13b8>; + ti,bit-shift = <8>; + }; + optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { compatible = "ti,divider-clock"; clocks = <&apll_pcie_ck>; @@ -1191,6 +1199,14 @@ ti,bit-shift = <9>; }; + optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 { + compatible = "ti,gate-clock"; + clocks = <&apll_pcie_ck>; + #clock-cells = <0>; + reg = <0x13b8>; + ti,bit-shift = <9>; + }; + optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 { compatible = "ti,gate-clock"; clocks = <&optfclk_pciephy_div>; @@ -1199,6 +1215,14 @@ ti,bit-shift = <10>; }; + optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 { + compatible = "ti,gate-clock"; + clocks = <&optfclk_pciephy_div>; + #clock-cells = <0>; + reg = <0x13b8>; + ti,bit-shift = <10>; + }; + apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; -- cgit v0.10.2 From d1ff66b52dbe6ac7c13c77767759d1ac84f5da9d Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Jul 2014 16:12:21 +0530 Subject: ARM: dts: dra7: Add dt data for PCIe PHY control module Added dt data for PCIe PHY control module used by PCIe PHY. The documention for this node can be found @ ../bindings/phy/ti-phy.txt Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 961be6b..e4999e4 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -828,6 +828,23 @@ ti,hwmods = "sata"; }; + omap_control_pcie1phy: control-phy@0x4a003c40 { + compatible = "ti,control-phy-pcie"; + reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; + reg-names = "power", "control_sma", "pcie_pcs"; + clocks = <&sys_clkin1>; + clock-names = "sysclk"; + }; + + omap_control_pcie2phy: control-pcie@0x4a003c44 { + compatible = "ti,control-phy-pcie"; + reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; + reg-names = "power", "control_sma", "pcie_pcs"; + clocks = <&sys_clkin1>; + clock-names = "sysclk"; + status = "disabled"; + }; + omap_control_usb2phy1: control-phy@4a002300 { compatible = "ti,control-phy-usb2"; reg = <0x4a002300 0x4>; -- cgit v0.10.2 From 692df0ef5abb7d8b36d70762134b842b70a55c31 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Jul 2014 16:12:22 +0530 Subject: ARM: dts: dra7: Add dt data for PCIe PHY Added dt data for PCIe PHY as a child node of ocp2scp3. The documention for this node can be found @ ../bindings/phy/ti-phy.txt. 26.3.3 PCIe Shared PHY Subsystem Integration in vE of DRA7xx ES1.0 describes the PCIe PHY subsystem-related components integrated in the device. Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index e4999e4..cbaf47d 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -816,6 +816,47 @@ clock-names = "sysclk"; #phy-cells = <0>; }; + + pcie1_phy: pciephy@4a094000 { + compatible = "ti,phy-pipe3-pcie"; + reg = <0x4a094000 0x80>, /* phy_rx */ + <0x4a094400 0x64>; /* phy_tx */ + reg-names = "phy_rx", "phy_tx"; + ctrl-module = <&omap_control_pcie1phy>; + clocks = <&dpll_pcie_ref_ck>, + <&dpll_pcie_ref_m2ldo_ck>, + <&optfclk_pciephy1_32khz>, + <&optfclk_pciephy1_clk>, + <&optfclk_pciephy1_div_clk>, + <&optfclk_pciephy_div>; + clock-names = "dpll_ref", "dpll_ref_m2", + "wkupclk", "refclk", + "div-clk", "phy-div"; + #phy-cells = <0>; + id = <1>; + ti,hwmods = "pcie1-phy"; + }; + + pcie2_phy: pciephy@4a095000 { + compatible = "ti,phy-pipe3-pcie"; + reg = <0x4a095000 0x80>, /* phy_rx */ + <0x4a095400 0x64>; /* phy_tx */ + reg-names = "phy_rx", "phy_tx"; + ctrl-module = <&omap_control_pcie2phy>; + clocks = <&dpll_pcie_ref_ck>, + <&dpll_pcie_ref_m2ldo_ck>, + <&optfclk_pciephy2_32khz>, + <&optfclk_pciephy2_clk>, + <&optfclk_pciephy2_div_clk>, + <&optfclk_pciephy_div>; + clock-names = "dpll_ref", "dpll_ref_m2", + "wkupclk", "refclk", + "div-clk", "phy-div"; + #phy-cells = <0>; + ti,hwmods = "pcie2-phy"; + id = <2>; + status = "disabled"; + }; }; sata: sata@4a141100 { -- cgit v0.10.2 From 18dcd79db798f710a25dee203b765ef62389f0e1 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Jul 2014 16:12:23 +0530 Subject: ARM: dts: dra7: Add dt data for PCIe controller Added dt data for PCIe controller. This node contains dt data for both the DRA7 part of designware controller and for the designware core. The documention for this node can be found @ ../bindings/pci/ti-pci.txt. Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Cc: Bjorn Helgaas Cc: Jingoo Han Cc: Jason Gunthorpe Cc: Marek Vasut Cc: Arnd Bergmann Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index cbaf47d..b6060d3 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -99,6 +99,75 @@ }; }; + axi@0 { + compatible = "simple-bus"; + #size-cells = <1>; + #address-cells = <1>; + ranges = <0x51000000 0x51000000 0x3000 + 0x0 0x20000000 0x10000000>; + pcie@51000000 { + compatible = "ti,dra7-pcie"; + reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; + reg-names = "rc_dbics", "ti_conf", "config"; + interrupts = <0 232 0x4>, <0 233 0x4>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x03000 0 0x00010000 + 0x82000000 0 0x20013000 0x13000 0 0xffed000>; + #interrupt-cells = <1>; + num-lanes = <1>; + ti,hwmods = "pcie1"; + phys = <&pcie1_phy>; + phy-names = "pcie-phy0"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 1>, + <0 0 0 2 &pcie1_intc 2>, + <0 0 0 3 &pcie1_intc 3>, + <0 0 0 4 &pcie1_intc 4>; + pcie1_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + axi@1 { + compatible = "simple-bus"; + #size-cells = <1>; + #address-cells = <1>; + ranges = <0x51800000 0x51800000 0x3000 + 0x0 0x30000000 0x10000000>; + status = "disabled"; + pcie@51000000 { + compatible = "ti,dra7-pcie"; + reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; + reg-names = "rc_dbics", "ti_conf", "config"; + interrupts = <0 355 0x4>, <0 356 0x4>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x03000 0 0x00010000 + 0x82000000 0 0x30013000 0x13000 0 0xffed000>; + #interrupt-cells = <1>; + num-lanes = <1>; + ti,hwmods = "pcie2"; + phys = <&pcie2_phy>; + phy-names = "pcie-phy0"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 1>, + <0 0 0 2 &pcie2_intc 2>, + <0 0 0 3 &pcie2_intc 3>, + <0 0 0 4 &pcie2_intc 4>; + pcie2_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + cm_core_aon: cm_core_aon@4a005000 { compatible = "ti,dra7-cm-core-aon"; reg = <0x4a005000 0x2000>; -- cgit v0.10.2 From 55be2c5376df16933219bbec98bfdfe2db158f69 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 10 Jul 2014 14:24:01 +0300 Subject: ARM: DTS: omap5-uevm: Enable palmas clk32kgaudio clock clk32kg-audio clock is needed for twl6040 codec. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 1e1b057..9166d479 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -306,6 +306,11 @@ ti,wakeup; }; + clk32kgaudio: palmas_clk32k@1 { + compatible = "ti,palmas-clk32kgaudio"; + #clock-cells = <0>; + }; + palmas_pmic { compatible = "ti,palmas-pmic"; interrupt-parent = <&palmas>; -- cgit v0.10.2 From 4b54a2cb14c370ee388d17a3ac084c4839a7933e Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 10 Jul 2014 14:24:02 +0300 Subject: ARM: DTS: omap5-uevm: Add node for twl6040 audio codec The board uses twl6040 as audio codec. Move the corresponding pinctrl as well under the node. twl6040 needs 32k clock from palams. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 9166d479..c928616 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -105,7 +105,6 @@ &omap5_pmx_core { pinctrl-names = "default"; pinctrl-0 = < - &twl6040_pins &mcpdm_pins &mcbsp1_pins &mcbsp2_pins @@ -494,6 +493,25 @@ }; }; }; + + twl6040: twl@4b { + compatible = "ti,twl6040"; + reg = <0x4b>; + + pinctrl-names = "default"; + pinctrl-0 = <&twl6040_pins>; + + interrupts = ; /* IRQ_SYS_2N cascaded to gic */ + interrupt-parent = <&gic>; + ti,audpwron-gpio = <&gpio5 13 0>; /* gpio line 141 */ + + vio-supply = <&smps7_reg>; + v2v1-supply = <&smps9_reg>; + enable-active-high; + + clocks = <&clk32kgaudio>; + clock-names = "clk32k"; + }; }; &i2c5 { -- cgit v0.10.2 From 3c9464ed75d6c15ee864da6d8f6a4cd3b0f2c934 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 10 Jul 2014 14:24:03 +0300 Subject: ARM: DTS: omap5-uevm: Enable basic audio (McPDM <-> twl6040) The board uses twl6040 codec connected via McPDM link. McBSP1 and McBSP2 can be used for FM/BT. At the same time move the pinctrl handling to the correct place - under the corresponding nodes. Audio connectors on the board: Headset in/out Stereo Line out Stereo Line in. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index c928616..159720d 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -100,14 +100,33 @@ }; }; }; + + sound: sound { + compatible = "ti,abe-twl6040"; + ti,model = "omap5-uevm"; + + ti,mclk-freq = <19200000>; + + ti,mcpdm = <&mcpdm>; + + ti,twl6040 = <&twl6040>; + + /* Audio routing */ + ti,audio-routing = + "Headset Stereophone", "HSOL", + "Headset Stereophone", "HSOR", + "Line Out", "AUXL", + "Line Out", "AUXR", + "HSMIC", "Headset Mic", + "Headset Mic", "Headset Mic Bias", + "AFML", "Line In", + "AFMR", "Line In"; + }; }; &omap5_pmx_core { pinctrl-names = "default"; pinctrl-0 = < - &mcpdm_pins - &mcbsp1_pins - &mcbsp2_pins &usbhost_pins &led_gpio_pins >; @@ -528,8 +547,22 @@ }; }; -&mcbsp3 { - status = "disabled"; +&mcpdm { + pinctrl-names = "default"; + pinctrl-0 = <&mcpdm_pins>; + status = "okay"; +}; + +&mcbsp1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp1_pins>; + status = "okay"; +}; + +&mcbsp2 { + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; + status = "okay"; }; &usbhshost { -- cgit v0.10.2