From 301d2d87cb4f826a38548f692e1b3c8c23590a9f Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 13 Feb 2013 15:21:21 +0100 Subject: Documentation/devicetree: add a small note on PCI Throw in a file with references to the IEEE binding documents. Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt new file mode 100644 index 0000000..41aeed3 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -0,0 +1,9 @@ +PCI bus bridges have standardized Device Tree bindings: + +PCI Bus Binding to: IEEE Std 1275-1994 +http://www.openfirmware.org/ofwg/bindings/pci/pci2_1.pdf + +And for the interrupt mapping part: + +Open Firmware Recommended Practice: Interrupt Mapping +http://www.openfirmware.org/1275/practice/imap/imap0_9d.pdf -- cgit v0.10.2 From 14d86e725ed034917bc721cf5deea019857b6cf0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 11 Apr 2013 23:32:28 +0200 Subject: ARM: pci: create pci_common_init_dev() When working with device tree support for PCI on ARM you run into a problem when mapping IRQs from the device tree irqmaps: doing this the code in drivers/of/of_pci_irq.c will try to find the OF node on the root bridge and this fails, because bus->dev.of_node is NULL, and that in turn boils down to the fact that pci_set_bus_of_node() has called pcibios_get_phb_of_node() from drivers/pci/of.c to obtain the OF node of the bridge or its parent and none is set and thus NULL is returned. Fix this by adding an additional parent argument API for registering PCI bridges on the ARM architecture called pci_common_init_dev(), and pass along this parent to pci_scan_root_bus() called from pcibios_init_hw() in bios32.c and voila: the IRQ mappings start working: the OF node can be retrieved from the parent. Create the old pci_common_init() as a wrapper around the new call. Cc: Mike Rapoport Cc: Russell King Cc: Ralf Baechle Cc: Arnd Bergmann Cc: Benjamin Herrenschmitt Reviewed-by: Andrew Murray Reviewed-by: Thierry Reding Signed-off-by: Linus Walleij diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index 7d2c3c8..038d657 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -16,6 +16,7 @@ struct pci_sys_data; struct pci_ops; struct pci_bus; +struct device; struct hw_pci { #ifdef CONFIG_PCI_DOMAINS @@ -68,7 +69,16 @@ struct pci_sys_data { /* * Call this with your hw_pci struct to initialise the PCI system. */ -void pci_common_init(struct hw_pci *); +void pci_common_init_dev(struct device *, struct hw_pci *); + +/* + * Compatibility wrapper for older platforms that do not care about + * passing the parent device. + */ +static inline void pci_common_init(struct hw_pci *hw) +{ + pci_common_init_dev(NULL, hw); +} /* * Setup early fixed I/O mapping. diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index b2ed73c..261fcc8 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -445,7 +445,8 @@ static int pcibios_init_resources(int busnr, struct pci_sys_data *sys) return 0; } -static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head) +static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, + struct list_head *head) { struct pci_sys_data *sys = NULL; int ret; @@ -480,7 +481,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head) if (hw->scan) sys->bus = hw->scan(nr, sys); else - sys->bus = pci_scan_root_bus(NULL, sys->busnr, + sys->bus = pci_scan_root_bus(parent, sys->busnr, hw->ops, sys, &sys->resources); if (!sys->bus) @@ -497,7 +498,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head) } } -void pci_common_init(struct hw_pci *hw) +void pci_common_init_dev(struct device *parent, struct hw_pci *hw) { struct pci_sys_data *sys; LIST_HEAD(head); @@ -505,7 +506,7 @@ void pci_common_init(struct hw_pci *hw) pci_add_flags(PCI_REASSIGN_ALL_RSRC); if (hw->preinit) hw->preinit(); - pcibios_init_hw(hw, &head); + pcibios_init_hw(parent, hw, &head); if (hw->postinit) hw->postinit(); -- cgit v0.10.2 From f4bc4f0ab4081b5bf99c92663877a41adf8c843a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 29 Jan 2013 17:14:18 +0100 Subject: ARM: integrator: merge PCIv3 driver into one file The Integrator/AP PCI bridget, "v3" is contained in two files, where pci.c is a socket container to plug in the v3 device. However to transition the v3 to enable device tree probing, it need to be converted to a platform device (so that it can have a device node in the device tree) and then we want the PCI driver in a single file, as any other device driver, so we can handle variants using compatible strings and device name, and get the base address etc from resources connected to the device node. To move toward this goal we consolidate all code in the pci_v3.c file. Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index 038d657..a1c90d7 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -106,9 +106,4 @@ extern struct pci_ops via82c505_ops; extern int via82c505_setup(int nr, struct pci_sys_data *); extern void via82c505_init(void *sysdata); -extern struct pci_ops pci_v3_ops; -extern int pci_v3_setup(int nr, struct pci_sys_data *); -extern void pci_v3_preinit(void); -extern void pci_v3_postinit(void); - #endif /* __ASM_MACH_PCI_H */ diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile index d14d6b7..ec759de 100644 --- a/arch/arm/mach-integrator/Makefile +++ b/arch/arm/mach-integrator/Makefile @@ -8,5 +8,5 @@ obj-y := core.o lm.o leds.o obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o -obj-$(CONFIG_PCI) += pci_v3.o pci.o +obj-$(CONFIG_PCI) += pci_v3.o obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o diff --git a/arch/arm/mach-integrator/pci.c b/arch/arm/mach-integrator/pci.c deleted file mode 100644 index 6c1667e..0000000 --- a/arch/arm/mach-integrator/pci.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * linux/arch/arm/mach-integrator/pci-integrator.c - * - * Copyright (C) 1999 ARM Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * - * PCI functions for Integrator - */ -#include -#include -#include -#include - -#include -#include - -#include - -/* - * A small note about bridges and interrupts. The DECchip 21050 (and - * later) adheres to the PCI-PCI bridge specification. This says that - * the interrupts on the other side of a bridge are swizzled in the - * following manner: - * - * Dev Interrupt Interrupt - * Pin on Pin on - * Device Connector - * - * 4 A A - * B B - * C C - * D D - * - * 5 A B - * B C - * C D - * D A - * - * 6 A C - * B D - * C A - * D B - * - * 7 A D - * B A - * C B - * D C - * - * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A. - * Thus, each swizzle is ((pin-1) + (device#-4)) % 4 - */ - -/* - * This routine handles multiple bridges. - */ -static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp) -{ - if (*pinp == 0) - *pinp = 1; - - return pci_common_swizzle(dev, pinp); -} - -static int irq_tab[4] __initdata = { - IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3 -}; - -/* - * map the specified device/slot/pin to an IRQ. This works out such - * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1. - */ -static int __init integrator_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int intnr = ((slot - 9) + (pin - 1)) & 3; - - return irq_tab[intnr]; -} - -extern void pci_v3_init(void *); - -static struct hw_pci integrator_pci __initdata = { - .swizzle = integrator_swizzle, - .map_irq = integrator_map_irq, - .setup = pci_v3_setup, - .nr_controllers = 1, - .ops = &pci_v3_ops, - .preinit = pci_v3_preinit, - .postinit = pci_v3_postinit, -}; - -static int __init integrator_pci_init(void) -{ - if (machine_is_integrator()) - pci_common_init(&integrator_pci); - return 0; -} - -subsys_initcall(integrator_pci_init); diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index e7fcea7..b8d7033 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -35,6 +35,7 @@ #include #include #include +#include #include @@ -337,7 +338,7 @@ static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where, return PCIBIOS_SUCCESSFUL; } -struct pci_ops pci_v3_ops = { +static struct pci_ops pci_v3_ops = { .read = v3_read_config, .write = v3_write_config, }; @@ -471,7 +472,7 @@ static irqreturn_t v3_irq(int dummy, void *devid) return IRQ_HANDLED; } -int __init pci_v3_setup(int nr, struct pci_sys_data *sys) +static int __init pci_v3_setup(int nr, struct pci_sys_data *sys) { int ret = 0; @@ -490,7 +491,7 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys) * V3_LB_BASE? - local bus address * V3_LB_MAP? - pci bus address */ -void __init pci_v3_preinit(void) +static void __init pci_v3_preinit(void) { unsigned long flags; unsigned int temp; @@ -589,7 +590,7 @@ void __init pci_v3_preinit(void) raw_spin_unlock_irqrestore(&v3_lock, flags); } -void __init pci_v3_postinit(void) +static void __init pci_v3_postinit(void) { unsigned int pci_cmd; @@ -610,3 +611,82 @@ void __init pci_v3_postinit(void) register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0); } + +/* + * A small note about bridges and interrupts. The DECchip 21050 (and + * later) adheres to the PCI-PCI bridge specification. This says that + * the interrupts on the other side of a bridge are swizzled in the + * following manner: + * + * Dev Interrupt Interrupt + * Pin on Pin on + * Device Connector + * + * 4 A A + * B B + * C C + * D D + * + * 5 A B + * B C + * C D + * D A + * + * 6 A C + * B D + * C A + * D B + * + * 7 A D + * B A + * C B + * D C + * + * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A. + * Thus, each swizzle is ((pin-1) + (device#-4)) % 4 + */ + +/* + * This routine handles multiple bridges. + */ +static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp) +{ + if (*pinp == 0) + *pinp = 1; + + return pci_common_swizzle(dev, pinp); +} + +static int irq_tab[4] __initdata = { + IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3 +}; + +/* + * map the specified device/slot/pin to an IRQ. This works out such + * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1. + */ +static int __init integrator_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + int intnr = ((slot - 9) + (pin - 1)) & 3; + + return irq_tab[intnr]; +} + +static struct hw_pci integrator_pci __initdata = { + .swizzle = integrator_swizzle, + .map_irq = integrator_map_irq, + .setup = pci_v3_setup, + .nr_controllers = 1, + .ops = &pci_v3_ops, + .preinit = pci_v3_preinit, + .postinit = pci_v3_postinit, +}; + +static int __init integrator_pci_init(void) +{ + if (machine_is_integrator()) + pci_common_init(&integrator_pci); + return 0; +} + +subsys_initcall(integrator_pci_init); -- cgit v0.10.2 From 86adc39ffc9360eee43ff5913468620a3fdd7289 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 2 Feb 2013 23:16:57 +0100 Subject: ARM: integrator: convert PCIv3 bridge to platform device This converts the PCIv3 driver to a platform device driver, and registers the device only on the Integrator/AP instead of bailing out in the initcall if the platform is not correct. Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index b23c8e4..0fff21c 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -494,6 +494,15 @@ static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = { { /* sentinel */ }, }; +/* + * This is a placeholder that will get deleted when we move the PCI + * device over to the device tree. + */ +static struct platform_device pci_v3_device_of = { + .name = "pci-v3", + .id = 0, +}; + static void __init ap_init_of(void) { unsigned long sc_dec; @@ -548,6 +557,8 @@ static void __init ap_init_of(void) of_platform_populate(root, of_default_bus_match_table, ap_auxdata_lookup, parent); + platform_device_register(&pci_v3_device_of); + sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET); for (i = 0; i < 4; i++) { struct lm_device *lmdev; @@ -615,6 +626,11 @@ static void __init ap_map_io_atag(void) * for eventual deletion. */ +static struct platform_device pci_v3_device = { + .name = "pci-v3", + .id = 0, +}; + static struct resource cfi_flash_resource = { .start = INTEGRATOR_FLASH_BASE, .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1, @@ -672,6 +688,7 @@ static void __init ap_init(void) unsigned long sc_dec; int i; + platform_device_register(&pci_v3_device); platform_device_register(&cfi_flash_device); ap_syscon_base = __io_address(INTEGRATOR_SC_BASE); diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index b8d7033..2733c6c 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -35,7 +36,6 @@ #include #include #include -#include #include @@ -649,7 +649,7 @@ static void __init pci_v3_postinit(void) /* * This routine handles multiple bridges. */ -static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp) +static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp) { if (*pinp == 0) *pinp = 1; @@ -665,16 +665,16 @@ static int irq_tab[4] __initdata = { * map the specified device/slot/pin to an IRQ. This works out such * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1. */ -static int __init integrator_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +static int __init pci_v3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { int intnr = ((slot - 9) + (pin - 1)) & 3; return irq_tab[intnr]; } -static struct hw_pci integrator_pci __initdata = { - .swizzle = integrator_swizzle, - .map_irq = integrator_map_irq, +static struct hw_pci pci_v3 __initdata = { + .swizzle = pci_v3_swizzle, + .map_irq = pci_v3_map_irq, .setup = pci_v3_setup, .nr_controllers = 1, .ops = &pci_v3_ops, @@ -682,11 +682,21 @@ static struct hw_pci integrator_pci __initdata = { .postinit = pci_v3_postinit, }; -static int __init integrator_pci_init(void) +static int __init pci_v3_probe(struct platform_device *pdev) { - if (machine_is_integrator()) - pci_common_init(&integrator_pci); + pci_common_init(&pci_v3); return 0; } -subsys_initcall(integrator_pci_init); +static struct platform_driver pci_v3_driver = { + .driver = { + .name = "pci-v3", + }, +}; + +static int __init pci_v3_init(void) +{ + return platform_driver_probe(&pci_v3_driver, pci_v3_probe); +} + +subsys_initcall(pci_v3_init); -- cgit v0.10.2 From 5283456dad4a57fe1940cec4d7a99ac93ee3127f Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 4 Apr 2013 14:02:57 +0200 Subject: ARM: integrator: grab PCI error IRQ in probe() This moves the request of the PCI error interrupt to the probe() function for the device, uses the devm* managed call and switch to a dev_err() error print. Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index 2733c6c..f027596 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -495,7 +495,6 @@ static void __init pci_v3_preinit(void) { unsigned long flags; unsigned int temp; - int ret; /* Remap the Integrator system controller */ ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100); @@ -579,14 +578,6 @@ static void __init pci_v3_preinit(void) v3_writeb(V3_LB_IMASK, 0x28); __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET); - /* - * Grab the PCI error interrupt. - */ - ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL); - if (ret) - printk(KERN_ERR "PCI: unable to grab PCI error " - "interrupt: %d\n", ret); - raw_spin_unlock_irqrestore(&v3_lock, flags); } @@ -684,7 +675,17 @@ static struct hw_pci pci_v3 __initdata = { static int __init pci_v3_probe(struct platform_device *pdev) { + int ret; + + ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL); + if (ret) { + dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n", + ret); + return -ENODEV; + } + pci_common_init(&pci_v3); + return 0; } -- cgit v0.10.2 From 03884f4e6d638a10901e599c9591ffa1530e23c0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 3 Feb 2013 00:06:04 +0100 Subject: ARM: integrator: move PCI base address grab to probe This moves the point where the PCIv3 driver grabs the SC base address to the probe function. Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index f027596..756a5f2 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -496,13 +496,6 @@ static void __init pci_v3_preinit(void) unsigned long flags; unsigned int temp; - /* Remap the Integrator system controller */ - ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100); - if (!ap_syscon_base) { - pr_err("unable to remap the AP syscon for PCIv3\n"); - return; - } - pcibios_min_mem = 0x00100000; /* @@ -677,6 +670,13 @@ static int __init pci_v3_probe(struct platform_device *pdev) { int ret; + /* Remap the Integrator system controller */ + ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100); + if (!ap_syscon_base) { + dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n"); + return -ENODEV; + } + ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL); if (ret) { dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n", -- cgit v0.10.2 From 207bcf45193bd6b847373246b37a3b673b1c81ca Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 3 Feb 2013 00:20:44 +0100 Subject: ARM: integrator: move V3 register definitions into driver This moves the PCIv3 register definitions into the driver itself. There is no other driver or board code including this file, nor will there be. If some other platform needs this driver it should be generalized to support several platforms. Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij diff --git a/arch/arm/include/asm/hardware/pci_v3.h b/arch/arm/include/asm/hardware/pci_v3.h deleted file mode 100644 index 2811c7e..0000000 --- a/arch/arm/include/asm/hardware/pci_v3.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * arch/arm/include/asm/hardware/pci_v3.h - * - * Internal header file PCI V3 chip - * - * Copyright (C) ARM Limited - * Copyright (C) 2000-2001 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef ASM_ARM_HARDWARE_PCI_V3_H -#define ASM_ARM_HARDWARE_PCI_V3_H - -/* ------------------------------------------------------------------------------- - * V3 Local Bus to PCI Bridge definitions - * ------------------------------------------------------------------------------- - * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04 - * All V3 register names are prefaced by V3_ to avoid clashing with any other - * PCI definitions. Their names match the user's manual. - * - * I'm assuming that I20 is disabled. - * - */ -#define V3_PCI_VENDOR 0x00000000 -#define V3_PCI_DEVICE 0x00000002 -#define V3_PCI_CMD 0x00000004 -#define V3_PCI_STAT 0x00000006 -#define V3_PCI_CC_REV 0x00000008 -#define V3_PCI_HDR_CFG 0x0000000C -#define V3_PCI_IO_BASE 0x00000010 -#define V3_PCI_BASE0 0x00000014 -#define V3_PCI_BASE1 0x00000018 -#define V3_PCI_SUB_VENDOR 0x0000002C -#define V3_PCI_SUB_ID 0x0000002E -#define V3_PCI_ROM 0x00000030 -#define V3_PCI_BPARAM 0x0000003C -#define V3_PCI_MAP0 0x00000040 -#define V3_PCI_MAP1 0x00000044 -#define V3_PCI_INT_STAT 0x00000048 -#define V3_PCI_INT_CFG 0x0000004C -#define V3_LB_BASE0 0x00000054 -#define V3_LB_BASE1 0x00000058 -#define V3_LB_MAP0 0x0000005E -#define V3_LB_MAP1 0x00000062 -#define V3_LB_BASE2 0x00000064 -#define V3_LB_MAP2 0x00000066 -#define V3_LB_SIZE 0x00000068 -#define V3_LB_IO_BASE 0x0000006E -#define V3_FIFO_CFG 0x00000070 -#define V3_FIFO_PRIORITY 0x00000072 -#define V3_FIFO_STAT 0x00000074 -#define V3_LB_ISTAT 0x00000076 -#define V3_LB_IMASK 0x00000077 -#define V3_SYSTEM 0x00000078 -#define V3_LB_CFG 0x0000007A -#define V3_PCI_CFG 0x0000007C -#define V3_DMA_PCI_ADR0 0x00000080 -#define V3_DMA_PCI_ADR1 0x00000090 -#define V3_DMA_LOCAL_ADR0 0x00000084 -#define V3_DMA_LOCAL_ADR1 0x00000094 -#define V3_DMA_LENGTH0 0x00000088 -#define V3_DMA_LENGTH1 0x00000098 -#define V3_DMA_CSR0 0x0000008B -#define V3_DMA_CSR1 0x0000009B -#define V3_DMA_CTLB_ADR0 0x0000008C -#define V3_DMA_CTLB_ADR1 0x0000009C -#define V3_DMA_DELAY 0x000000E0 -#define V3_MAIL_DATA 0x000000C0 -#define V3_PCI_MAIL_IEWR 0x000000D0 -#define V3_PCI_MAIL_IERD 0x000000D2 -#define V3_LB_MAIL_IEWR 0x000000D4 -#define V3_LB_MAIL_IERD 0x000000D6 -#define V3_MAIL_WR_STAT 0x000000D8 -#define V3_MAIL_RD_STAT 0x000000DA -#define V3_QBA_MAP 0x000000DC - -/* PCI COMMAND REGISTER bits - */ -#define V3_COMMAND_M_FBB_EN (1 << 9) -#define V3_COMMAND_M_SERR_EN (1 << 8) -#define V3_COMMAND_M_PAR_EN (1 << 6) -#define V3_COMMAND_M_MASTER_EN (1 << 2) -#define V3_COMMAND_M_MEM_EN (1 << 1) -#define V3_COMMAND_M_IO_EN (1 << 0) - -/* SYSTEM REGISTER bits - */ -#define V3_SYSTEM_M_RST_OUT (1 << 15) -#define V3_SYSTEM_M_LOCK (1 << 14) - -/* PCI_CFG bits - */ -#define V3_PCI_CFG_M_I2O_EN (1 << 15) -#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) -#define V3_PCI_CFG_M_IO_DIS (1 << 13) -#define V3_PCI_CFG_M_EN3V (1 << 12) -#define V3_PCI_CFG_M_RETRY_EN (1 << 10) -#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) -#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) - -/* PCI_BASE register bits (PCI -> Local Bus) - */ -#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 -#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 -#define V3_PCI_BASE_M_PREFETCH (1 << 3) -#define V3_PCI_BASE_M_TYPE (3 << 1) -#define V3_PCI_BASE_M_IO (1 << 0) - -/* PCI MAP register bits (PCI -> Local bus) - */ -#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 -#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) -#define V3_PCI_MAP_M_ROM_SIZE (3 << 10) -#define V3_PCI_MAP_M_SWAP (3 << 8) -#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 -#define V3_PCI_MAP_M_REG_EN (1 << 1) -#define V3_PCI_MAP_M_ENABLE (1 << 0) - -/* - * LB_BASE0,1 register bits (Local bus -> PCI) - */ -#define V3_LB_BASE_ADR_BASE 0xfff00000 -#define V3_LB_BASE_SWAP (3 << 8) -#define V3_LB_BASE_ADR_SIZE (15 << 4) -#define V3_LB_BASE_PREFETCH (1 << 3) -#define V3_LB_BASE_ENABLE (1 << 0) - -#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) -#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) -#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) -#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) -#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) -#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) -#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) -#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) -#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) -#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) -#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) -#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) - -#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) - -/* - * LB_MAP0,1 register bits (Local bus -> PCI) - */ -#define V3_LB_MAP_MAP_ADR 0xfff0 -#define V3_LB_MAP_TYPE (7 << 1) -#define V3_LB_MAP_AD_LOW_EN (1 << 0) - -#define V3_LB_MAP_TYPE_IACK (0 << 1) -#define V3_LB_MAP_TYPE_IO (1 << 1) -#define V3_LB_MAP_TYPE_MEM (3 << 1) -#define V3_LB_MAP_TYPE_CONFIG (5 << 1) -#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) - -#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) - -/* - * LB_BASE2 register bits (Local bus -> PCI IO) - */ -#define V3_LB_BASE2_ADR_BASE 0xff00 -#define V3_LB_BASE2_SWAP (3 << 6) -#define V3_LB_BASE2_ENABLE (1 << 0) - -#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) - -/* - * LB_MAP2 register bits (Local bus -> PCI IO) - */ -#define V3_LB_MAP2_MAP_ADR 0xff00 - -#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) - -#endif diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index 756a5f2..604064b 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -37,7 +37,165 @@ #include #include -#include +/* + * V3 Local Bus to PCI Bridge definitions + * + * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04 + * All V3 register names are prefaced by V3_ to avoid clashing with any other + * PCI definitions. Their names match the user's manual. + * + * I'm assuming that I20 is disabled. + * + */ +#define V3_PCI_VENDOR 0x00000000 +#define V3_PCI_DEVICE 0x00000002 +#define V3_PCI_CMD 0x00000004 +#define V3_PCI_STAT 0x00000006 +#define V3_PCI_CC_REV 0x00000008 +#define V3_PCI_HDR_CFG 0x0000000C +#define V3_PCI_IO_BASE 0x00000010 +#define V3_PCI_BASE0 0x00000014 +#define V3_PCI_BASE1 0x00000018 +#define V3_PCI_SUB_VENDOR 0x0000002C +#define V3_PCI_SUB_ID 0x0000002E +#define V3_PCI_ROM 0x00000030 +#define V3_PCI_BPARAM 0x0000003C +#define V3_PCI_MAP0 0x00000040 +#define V3_PCI_MAP1 0x00000044 +#define V3_PCI_INT_STAT 0x00000048 +#define V3_PCI_INT_CFG 0x0000004C +#define V3_LB_BASE0 0x00000054 +#define V3_LB_BASE1 0x00000058 +#define V3_LB_MAP0 0x0000005E +#define V3_LB_MAP1 0x00000062 +#define V3_LB_BASE2 0x00000064 +#define V3_LB_MAP2 0x00000066 +#define V3_LB_SIZE 0x00000068 +#define V3_LB_IO_BASE 0x0000006E +#define V3_FIFO_CFG 0x00000070 +#define V3_FIFO_PRIORITY 0x00000072 +#define V3_FIFO_STAT 0x00000074 +#define V3_LB_ISTAT 0x00000076 +#define V3_LB_IMASK 0x00000077 +#define V3_SYSTEM 0x00000078 +#define V3_LB_CFG 0x0000007A +#define V3_PCI_CFG 0x0000007C +#define V3_DMA_PCI_ADR0 0x00000080 +#define V3_DMA_PCI_ADR1 0x00000090 +#define V3_DMA_LOCAL_ADR0 0x00000084 +#define V3_DMA_LOCAL_ADR1 0x00000094 +#define V3_DMA_LENGTH0 0x00000088 +#define V3_DMA_LENGTH1 0x00000098 +#define V3_DMA_CSR0 0x0000008B +#define V3_DMA_CSR1 0x0000009B +#define V3_DMA_CTLB_ADR0 0x0000008C +#define V3_DMA_CTLB_ADR1 0x0000009C +#define V3_DMA_DELAY 0x000000E0 +#define V3_MAIL_DATA 0x000000C0 +#define V3_PCI_MAIL_IEWR 0x000000D0 +#define V3_PCI_MAIL_IERD 0x000000D2 +#define V3_LB_MAIL_IEWR 0x000000D4 +#define V3_LB_MAIL_IERD 0x000000D6 +#define V3_MAIL_WR_STAT 0x000000D8 +#define V3_MAIL_RD_STAT 0x000000DA +#define V3_QBA_MAP 0x000000DC + +/* PCI COMMAND REGISTER bits + */ +#define V3_COMMAND_M_FBB_EN (1 << 9) +#define V3_COMMAND_M_SERR_EN (1 << 8) +#define V3_COMMAND_M_PAR_EN (1 << 6) +#define V3_COMMAND_M_MASTER_EN (1 << 2) +#define V3_COMMAND_M_MEM_EN (1 << 1) +#define V3_COMMAND_M_IO_EN (1 << 0) + +/* SYSTEM REGISTER bits + */ +#define V3_SYSTEM_M_RST_OUT (1 << 15) +#define V3_SYSTEM_M_LOCK (1 << 14) + +/* PCI_CFG bits + */ +#define V3_PCI_CFG_M_I2O_EN (1 << 15) +#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) +#define V3_PCI_CFG_M_IO_DIS (1 << 13) +#define V3_PCI_CFG_M_EN3V (1 << 12) +#define V3_PCI_CFG_M_RETRY_EN (1 << 10) +#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) +#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) + +/* PCI_BASE register bits (PCI -> Local Bus) + */ +#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 +#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 +#define V3_PCI_BASE_M_PREFETCH (1 << 3) +#define V3_PCI_BASE_M_TYPE (3 << 1) +#define V3_PCI_BASE_M_IO (1 << 0) + +/* PCI MAP register bits (PCI -> Local bus) + */ +#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 +#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) +#define V3_PCI_MAP_M_ROM_SIZE (3 << 10) +#define V3_PCI_MAP_M_SWAP (3 << 8) +#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 +#define V3_PCI_MAP_M_REG_EN (1 << 1) +#define V3_PCI_MAP_M_ENABLE (1 << 0) + +/* + * LB_BASE0,1 register bits (Local bus -> PCI) + */ +#define V3_LB_BASE_ADR_BASE 0xfff00000 +#define V3_LB_BASE_SWAP (3 << 8) +#define V3_LB_BASE_ADR_SIZE (15 << 4) +#define V3_LB_BASE_PREFETCH (1 << 3) +#define V3_LB_BASE_ENABLE (1 << 0) + +#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) +#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) +#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) +#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) +#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) +#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) +#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) +#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) +#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) +#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) +#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) +#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) + +#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) + +/* + * LB_MAP0,1 register bits (Local bus -> PCI) + */ +#define V3_LB_MAP_MAP_ADR 0xfff0 +#define V3_LB_MAP_TYPE (7 << 1) +#define V3_LB_MAP_AD_LOW_EN (1 << 0) + +#define V3_LB_MAP_TYPE_IACK (0 << 1) +#define V3_LB_MAP_TYPE_IO (1 << 1) +#define V3_LB_MAP_TYPE_MEM (3 << 1) +#define V3_LB_MAP_TYPE_CONFIG (5 << 1) +#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) + +#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) + +/* + * LB_BASE2 register bits (Local bus -> PCI IO) + */ +#define V3_LB_BASE2_ADR_BASE 0xff00 +#define V3_LB_BASE2_SWAP (3 << 6) +#define V3_LB_BASE2_ENABLE (1 << 0) + +#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) + +/* + * LB_MAP2 register bits (Local bus -> PCI IO) + */ +#define V3_LB_MAP2_MAP_ADR 0xff00 + +#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) /* * The V3 PCI interface chip in Integrator provides several windows from -- cgit v0.10.2 From a5ecbab7d9b606bdfbec67ccda0fde0f82e1e70e Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 16 Mar 2013 21:51:02 +0100 Subject: ARM: integrator: remap PCIv3 base dynamically Remove the static mapping for the PCIv3 PCI bridge controller and do this dynamically when probing instead. Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h index be5859e..62fa119 100644 --- a/arch/arm/mach-integrator/include/mach/platform.h +++ b/arch/arm/mach-integrator/include/mach/platform.h @@ -325,7 +325,6 @@ #define PCI_MEMORY_VADDR IOMEM(0xe8000000) #define PCI_CONFIG_VADDR IOMEM(0xec000000) -#define PCI_V3_VADDR IOMEM(0xed000000) /* ------------------------------------------------------------------------ * Integrator Interrupt Controllers diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 0fff21c..8db3799 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -80,7 +80,6 @@ void __iomem *ap_syscon_base; * Logical Physical * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) - * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k) * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) * ef000000 Cache flush * f1000000 10000000 Core module registers @@ -140,11 +139,6 @@ static struct map_desc ap_io_desc[] __initdata __maybe_unused = { .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE), .length = SZ_16M, .type = MT_DEVICE - }, { - .virtual = (unsigned long)PCI_V3_VADDR, - .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE), - .length = SZ_64K, - .type = MT_DEVICE } }; diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index 604064b..9dd7125 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -260,15 +260,17 @@ * the mappings into PCI memory. */ +static void __iomem *pci_v3_base; + // V3 access routines -#define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o)) -#define v3_readb(o) (__raw_readb(PCI_V3_VADDR + (unsigned int)(o))) +#define v3_writeb(o,v) __raw_writeb(v, pci_v3_base + (unsigned int)(o)) +#define v3_readb(o) (__raw_readb(pci_v3_base + (unsigned int)(o))) -#define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o)) -#define v3_readw(o) (__raw_readw(PCI_V3_VADDR + (unsigned int)(o))) +#define v3_writew(o,v) __raw_writew(v, pci_v3_base + (unsigned int)(o)) +#define v3_readw(o) (__raw_readw(pci_v3_base + (unsigned int)(o))) -#define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o)) -#define v3_readl(o) (__raw_readl(PCI_V3_VADDR + (unsigned int)(o))) +#define v3_writel(o,v) __raw_writel(v, pci_v3_base + (unsigned int)(o)) +#define v3_readl(o) (__raw_readl(pci_v3_base + (unsigned int)(o))) /*============================================================================ * @@ -835,6 +837,12 @@ static int __init pci_v3_probe(struct platform_device *pdev) return -ENODEV; } + pci_v3_base = devm_ioremap(&pdev->dev, PHYS_PCI_V3_BASE, SZ_64K); + if (!pci_v3_base) { + dev_err(&pdev->dev, "unable to remap PCIv3 base\n"); + return -ENODEV; + } + ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL); if (ret) { dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n", -- cgit v0.10.2 From 01ef31053ddda5d5aee86dca61193d1395273d53 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 16 Mar 2013 22:03:41 +0100 Subject: ARM: integrator: move VGA base assignment The global vga_base is used for things like getting an early console on a PCI-based VGA adapter. Move this assignment into the probe function for the PCI bridge. Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 8db3799..6375657 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -41,7 +41,6 @@ #include #include #include -#include