From 974a2aba99d29bada9212134e7565d2364967636 Mon Sep 17 00:00:00 2001 From: Arun Chandran Date: Fri, 12 Jun 2015 12:23:24 +0530 Subject: ARM: zynq: Fix earlyprintk in big endian mode earlyprintk messages are not appearing on the terminal emulator during a big endian kernel boot. In BE mode sending full words to UART will result in unprintable characters as they are byte swapped versions of printable ones. So send only bytes. Signed-off-by: Arun Chandran Tested-by: Michal Simek Signed-off-by: Michal Simek diff --git a/arch/arm/include/debug/zynq.S b/arch/arm/include/debug/zynq.S index bd13ded..de86b92 100644 --- a/arch/arm/include/debug/zynq.S +++ b/arch/arm/include/debug/zynq.S @@ -38,7 +38,7 @@ .endm .macro senduart,rd,rx - str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA + strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA .endm .macro waituart,rd,rx -- cgit v0.10.2 From 6632d4fdd790965a2e4741a3652a1c365d52ae2e Mon Sep 17 00:00:00 2001 From: Thomas Betker Date: Tue, 12 May 2015 08:22:01 +0200 Subject: ARM: zynq: Set bit 22 in PL310 AuxCtrl register (6395/1) This patch is based on the commit 1a8e41cd672f ("ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register") Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. For Zynq, this fix avoids memory inconsistencies between Gigabit Ethernet controller (GEM) and CPU when DMA_CMA is disabled. Suggested-by: Punnaiah Choudary Kalluri Signed-off-by: Thomas Betker Signed-off-by: Michal Simek diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 616d584..6bd4a43 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -197,8 +197,8 @@ static const char * const zynq_dt_match[] = { DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") /* 64KB way size, 8-way associativity, parity disabled */ - .l2c_aux_val = 0x00000000, - .l2c_aux_mask = 0xffffffff, + .l2c_aux_val = 0x00400000, + .l2c_aux_mask = 0xffbfffff, .smp = smp_ops(zynq_smp_ops), .map_io = zynq_map_io, .init_irq = zynq_irq_init, -- cgit v0.10.2 From d6448b76ab260457d78e9d09465afaec2697e20d Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Fri, 26 Jun 2015 09:04:32 -0700 Subject: MAINTAINERS: Update Zynq git tree location The git tree for Zynq moved to Github. Update the MAINTAINERS record to reflect the change. Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek diff --git a/MAINTAINERS b/MAINTAINERS index 8133cef..9cde7e5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1672,7 +1672,7 @@ M: Michal Simek R: Sören Brinkmann L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) W: http://wiki.xilinx.com -T: git git://git.xilinx.com/linux-xlnx.git +T: git https://github.com/Xilinx/linux-xlnx.git S: Supported F: arch/arm/mach-zynq/ F: drivers/cpuidle/cpuidle-zynq.c -- cgit v0.10.2 From 07e4d3d9e281136fdd781e8c3b9146b97f2d28d6 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 27 Jul 2015 16:36:42 +0900 Subject: clk: zynq: remove redundant $(CONFIG_ARCH_ZYNQ) in Makefile Kbuild descends into drivers/clk/zynq/ only when CONFIG_ARCH_ZYNQ is enabled. (see drivers/clk/Makefile) $(CONFIG_ARCH_ZYNQ) in drivers/clk/zynq/Makefile always evaluates to 'y'. Signed-off-by: Masahiro Yamada Signed-off-by: Michal Simek diff --git a/drivers/clk/zynq/Makefile b/drivers/clk/zynq/Makefile index 156d923..0afc2e7 100644 --- a/drivers/clk/zynq/Makefile +++ b/drivers/clk/zynq/Makefile @@ -1,3 +1,3 @@ # Zynq clock specific Makefile -obj-$(CONFIG_ARCH_ZYNQ) += clkc.o pll.o +obj-y += clkc.o pll.o -- cgit v0.10.2 From e4a9288942392965bd5cfad93d9996b83c0dc4a6 Mon Sep 17 00:00:00 2001 From: Nathan Lynch Date: Fri, 17 Jul 2015 16:01:02 -0500 Subject: ARM: zynq: reserve space for jump target in secondary trampoline Add a zero argument to the .word directive in zynq_secondary_trampoline. Without an expression the assembler emits nothing for the .word directive. This makes it so that the intended range is communicated to ioremap and outer_flush_range in zynq_cpun_start; e.g. for LE trampoline_code_size evaluates to 12 now instead of 8. Found by inspection. I'm not aware of any real problem this fixes. Tested by doing on online/offline loop on ZC702. Signed-off-by: Nathan Lynch Signed-off-by: Michal Simek diff --git a/arch/arm/mach-zynq/headsmp.S b/arch/arm/mach-zynq/headsmp.S index 045c727..f6d5de0 100644 --- a/arch/arm/mach-zynq/headsmp.S +++ b/arch/arm/mach-zynq/headsmp.S @@ -18,7 +18,7 @@ ARM_BE8(rev r0, r0) .globl zynq_secondary_trampoline_jump zynq_secondary_trampoline_jump: /* Space for jumping address */ - .word /* cpu 1 */ + .word 0 /* cpu 1 */ .globl zynq_secondary_trampoline_end zynq_secondary_trampoline_end: ENDPROC(zynq_secondary_trampoline) -- cgit v0.10.2